XILINX XC2S50-6TQ144C, XC2S50-6PQ208C, XC2S50-6FG256C, XC2S50-5TQ144I, XC2S50-5TQ144C Datasheet
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DS001-1 (v2.3) November 1, 2001 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
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Introduction
The Spartan™-II 2.5V Field-Programmable Gate Array f amily gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in Table 1. System perfor-
mance is supported up to 200 MHz.
Spartan-II devices deliver more gates, I/Os, and features
per dollar than other FPGAs by comb ining advanced process technology with a streamlined Virtex-based architecture. Features include block RAM (to 56K bits), distributed
RAM (to 75,264 bits), 16 selectable I/O standards, and four
DLLs. Fast, predictable interconnect means that successive
design iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
• Second generation ASIC replacement technology
- Densities as high as 5,292 logic cells with up to
200,000 system gates
- Streamlined features based on Virtex architecture
- Unlimited reprogrammability
- Very low cost
• System level features
- SelectRAM+™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K bit block RAM
· Fast interfaces to external RAM
- Fully P C I co mpliant
- Low-power segmented routing architecture
- Full readba ck ability for verification /observability
- Dedicated carry logi c for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary
low-skew global clock distribution nets
- IEEE 1149.1 compati ble boundar y scan logic
• Versatile I/O and packaging
- Low cost packages available in all densities
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Hot swap Compact PCI friendly
- Zero hold time simplifies system timing
• Fully s upported by powerful Xilinx development system
- Foundation ISE Series: Fully integrated software
- Alliance Series: For use with third-party tools
- Fully automatic mapping, placem ent, and routing
0
Spartan-II 2.5V FPGA Family:
Introduction and Ordering
Information
DS001-1 (v2.3) November 1, 2001
00
Preliminary Product Specification
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Table 1: Spa rtan-II FP G A Family M e mbers
Device
Logic
Cells
System Gates
(Logic and RAM)
CLB
Array
(R x C)
Total
CLBs
Maximum
Available
User I/O
(1)
Total
Distributed RAM
Bits
Total
Block RAM
Bits
XC2S15 432 15,000 8 x 12 96 86 6,144 16K
XC2S30 972 30,000 12 x 18 216 132 13,824 24K
XC2S50 1,728 50,000 16 x 24 384 176 24,576 32K
XC2S100 2,700 100,000 20 x 30 600 196 38,400 40K
XC2S150 3,888 150,000 24 x 36 864 260 55,296 48K
XC2S200 5,292 200,000 28 x 42 1,176 284 75,264 56K
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3.
Spar tan- II 2.5V F P G A Family: Introd uc t ion and Orde ring Informa t ion
2 www.xilinx.com DS001-1 (v2.3) November 1, 2001
1-800-255-7778 Preliminary Product Specification
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General Overview
The Spartan-II family of FPGAs have a regular, fle xible , programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB colum ns. These funct iona l elemen ts are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-II FPGA s are customized by loading configuration
data into internal static memory cells. Unlimited reprogramming cycles are possible with this approach. Stored values
in these cells determine logic functions and interconnections implemented in the FPGA . Configuration dat a can be
read from an external serial PROM (master serial mode), or
written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes.
Spartan-II FPGAs are typically used in high-volume applications w here the ver satility of a fast program mable soluti on
adds benefits. Spartan-II FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
Spartan-II FPGAs achieve high-performance, low-cost
operation through advanced architecture an d semiconductor technology. Spartan-II devices provide system clock
rates up to 200 MHz. Spartan-II FPGAs offer the most
cost-effective solution while maintaining leading edge performance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-II
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distributed form), DL L clock drivers, programmable set and reset on all flip-flops, fast carry
logic, and many other features.
The Xilinx XC17S00A PROM family is recommended for
serial configuration of Spartan-II FPGAs. The In-System
Programmable (ISP) XC18V00 PROM family is recommended for parallel or serial configuration.
Figure 1: Basic Spartan-II Family FPGA Block Diagram
XC2S15
DLL
DLL
DLL
DLL
BLOCK RAM
BLOCK RAM
BLOCK RAMBLOCK RAM
I/O LOGIC
CLBs CLBs
CLBs CLBs
DS001_01_091800
Spartan - II 2.5V FPGA Family: Int roduct i on a nd Ordering Informa tion
DS001-1 (v2.3) November 1, 2001 www.xilinx.com 3
Preliminary Product Specification 1-800-255-7778
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Spartan-II Product Availability
Table 2 shows the pa ckage and speed grades available for
Spartan-II family devices. Table 3 shows the maximum user
I/Os available on the device and the number of user I/Os
available for each device/package combination. The four
global clock pins are usable as additional user I/Os wh en
not used as a global c lock pin. These pins are not includ ed
in user I/O counts.
Table 2: Spartan-II Package and Speed Grade Availability
Device
Pins 100 144 144 208 256 456
Type
Plastic
VQFP
Plastic
TQFP
Chip Scale
BGA
Plastic
PQFP
Fine Pitch
BGA
Fine Pitch
BGA
Code VQ100 T Q144 CS144 PQ208 FG256 FG456
XC2S15 -5 C, I C, I C, I - - -
-6CCC- - -
XC2S30-5 C, IC, IC, IC, I - -
-6CCCC- -
XC2S50 -5 - C, I - C, I C, I -
-6-C-CC-
XC2S100 -5 - C, I - C, I C, I C, I
-6-C-CCC
XC2S150 -5 - - - C, I C, I C, I
-6---CCC
XC2S200 -5 - - - C, I C, I C, I
-6---CCC
Notes:
1. C = Commercial, T
J
= 0° to +85°C; I = Industrial, TJ = –40°C to +10 0 °C.
Table 3: Spa rtan - II User I/O Chart
(1)
Device
Maximum
User I/O
Available User I/O According to Package Type
VQ100 TQ144 CS144 PQ208 FG256 FG456
XC2S15 86 60 86 86 - - XC2S30 132 60 92 92 132 - -
XC2S50 176 - 92 - 140 176 XC2S100 196 - 92 - 140 176 196
XC2S150 260 - - - 140 176 260
XC2S200 284 - - - 140 176 284
Notes:
1. All user I/O counts do not include the four global clock/user input pins.
Spar tan- II 2.5V F P G A Family: Introd uc t ion and Orde ring Informa t ion
4 www.xilinx.com DS001-1 (v2.3) November 1, 2001
1-800-255-7778 Preliminary Product Specification
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Ordering Information
Revision History
The Spartan-II Family Data Sheet
DS001-1, Spartan-II 2.5V FPGA Family: Introduction and Ordering Information (Module 1)
DS001-2, Sparta n-I I 2.5V FPGA Fami ly: Functional Description
(Module 2)
DS001-3, Sparta n-I I 2.5V FPGA Fami ly: DC and Switching Characteristics
(Module 3)
DS001-4, Sparta n-I I 2.5V FPGA Fami ly: Pinout Tables
(Module 4)
XC2S50 -6 PQ 208 C
Example:
Temperature Range
Number of Pins
Package Type
Device Type
Speed Grade
Device Ordering Options
Device Speed Grade Number of Pins / Package Type Temper ature Range (TJ)
XC2S15 -5 Standard Performance VQ100 100-pin Plastic Very Thin QFP C = Commercial 0°C to +85°C
XC2S30 -6 Higher Per formance CS144 144-ball Chip-Scale BGA I = Industrial –40°C to +100°C
XC2S50 TQ144 144-pin Plastic Thin QFP
XC2S100 PQ208 208-pin Plastic QFP
XC2S150 FG256 256-ball Fine Pitch BGA
XC2S200 FG456 456-ball Fine Pitch BGA
Ver sion No. Date Description
2.0 09/18/00 Sectioned the Spartan-II Family data sheet into four modules. Added industrial temperature
range information.
2.1 10/31/00 Removed Power down feature.
2.2 03/05/01 Added statement on PROMs.
2.3 11/01/01 Upda te Product Availability chart. Minor text edits.
PN 0113 11
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