XILINX XC2S50E-7PQ208I, XC2S50E-7PQ208C, XC2S50E-7FT456I, XC2S50E-7FT456C, XC2S50E-7FT256I Datasheet
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DS077-1 (v1.0) November 15, 2001 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
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Introduction
The Spartan™-IIE 1.8V Field-Programmable Gate Array
family gives users high performance, abundant logic
resources, and a rich feature set, all at an exceptionally low
price. The five-member family offers densities ranging from
50,000 to 300,000 system gates, as shown in Table 1. System performance is supported beyond 200 MHz.
Spartan-IIE d evices deliver more gates, I/Os, and features
per dollar than other FPGAs by comb ining advanced process technology with a streamlined architecture based on
the proven Virtex™-E platform. Features include block RAM
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable
I/O standards, and four DLLs (Delay-Locked Loops). Fast,
predictable interconnect means that successive design iterations continue to meet timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
• Second generation ASIC replacement technology
- Densities as high as 6,912 logic cells with up to
300,000 system gates
- Streamlined features based on Virtex-E
architecture
- Unlimited in-system reprogrammability
- Very low cost
• System level features
- SelectRAM+™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K-bit true dual-port block RAM
· Fast interfaces to external RAM
- Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
- Low-power segmented routing architecture
- Full readba ck ability for verification /observability
- Dedicated carry logi c for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary
low-skew global clock distribution nets
- IEEE 1149.1 compati ble boundar y scan logic
• Versatile I/O and packaging
- Low cost packages available in all densities
- Family footprint compatibility in common packages
- 19 high-performance interface standards, including
LVDS and LVPECL
- Up to 120 differential I/O pairs that can be input,
output, or bidirectional
- Zero hold time simplifies system timing
• Fully s upported by powerful Xilinx ISE development
system
- Fully automatic mapping, placem ent, and routing
- Integrated with design entry and verification tools
0
Spartan-IIE 1.8V FPGA Family:
Introduction and Ordering
Information
DS077-1 (v1.0) November 15, 2001
00
Preliminary Product Specification
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Table 1: Spartan-IIE FPGA Family Members
Device
Logic
Cells
Typical
System Gate Range
(Logic and RAM)
CLB
Array
(R x C )
Total
CLBs
Maximum
Available
User I/O
Maximum
Differential
I/O Pairs
Distributed
RAM Bits
Block
RAM Bits
XC2S50E 1,728 23,000 - 50,000 16 x 24 384 182 84 24,576 32K
XC2S100E 2,700 37,000 - 100,000 20 x 30 600 202 86 38,400 40K
XC2S150E 3,888 52,000 - 150,000 24 x 36 864 263 114 55,296 48K
XC2S200E 5,292 71,000 - 200,000 28 x 42 1,176 289 120 75,264 56K
XC2S300E 6,912 93,000 - 300,000 32 x 48 1,536 329 120 98,304 64K
Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
2 www.xilinx.com DS077-1 (v1.0) November 15, 2001
1-800-255-7778 Preliminary Product Specification
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General Overview
The Spartan-I IE family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB colum ns. These funct iona l elemen ts are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-IIE FPGAs are customized by loading configuration data into interna l static memor y cells. Unlimited reprogramming cycles are possible with this approach. Stored
values in these cells determine logic functions and interconnections implemented in the FPGA . Configu ration data can
be read from an external serial PROM (master serial mode),
or written into the FPGA i n slave serial, slave parallel, or
Boundary Scan modes. The Xilinx XC17S00A PROM family
is recommended for serial configuration of Spartan-IIE
FPGAs. The XC18V00 reprogrammable PROM family is
recommended for parallel or serial configuration.
Spartan-IIE FPGAs are typica lly used in high-volume applications where the versatility of a f ast programmable solution
adds benefits. Spartan-IIE FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
Spartan-IIE FPGAs achieve high-performance, low-cost
operation through advanced architecture an d semiconductor technology. Spartan-IIE devices provide system clock
rates beyond 200 MHz. Spartan-IIE FPGA s offer the most
cost-effective solution while maintaining leading edge performance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-IIE
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distributed form), DL L clock drivers, programmable set and reset on all flip-flops, fast carry
logic, and many other features.
Spartan-IIE Famil y Compar ed to Spartan- II
Family
• Higher density and more I/O
• Higher performance
• Unique pinouts in cost-effective packages
• Differential signaling
- LVDS, Bus LVDS, LVPECL
• V
CCINT
= 1.8V
- Lower power
- 5V tolerance with 100
Ω external resistor
- 3V tolerance directly
• PCI, LVTTL, and LVCMOS2 input buffers powered by
V
CCO
instead of V
CCINT
• Unique larger bitstream
Figure 1: Basic Spar tan -IIE Family FPGA Block Diagram
DL
L
OC
K RAM
L
OC
K RAM
L
OC
K RAM
L
OC
K RAM
I/O LOGI
C
DS077_01_10220
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