XILINX XC2C64-7VQ44I, XC2C64-7VQ44C, XC2C64-7VQ100I, XC2C64-7VQ100C, XC2C64-7PC44I Datasheet

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Advance Product Specification 1-800-255-7778

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Features

• Optimized for 1.8V systems

- Industry’s fastest low power CPLD

- Static Icc of less than 100 microamps at all times

- Densities from 32 to 512 macrocells

• Industry’s best 0.18 micron CMOS CPLD

- Optimized architecture for effective logic synthesis

- Multi-voltage I/O operation — 1.5V to 3.3V

• Available in multiple package options

- 44-pin PLCC with 33 user I/O

- 44-pin VQFP with 33 user I/O

- 56-ball CP (0.05mm) BGA with 45 user I/O

- 100-pin VQFP with 64 user I/O

• Advanced syste m features

- Fastest in system programming

· 1.8V ISP using IEEE 1532 (JTAG) interface

- IEEE1149.1 JTA G Boundary Scan Test

- Optional Schmitt trigger input (per pin)

- Unsurpassed low power management

- FZP 100% CMOS product ter m gene ration

- Flexible clocking modes

· Optional DualEDGE triggered registers

- Global signal options with macrocell control

· Multiple global clocks with phase selection per
macrocell

· Multiple global output enables

· Global set/reset

- Abundant product term clocks, output enables and
set/resets

- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks

- Advanced design security

- Open-drain output option for Wired-OR and LED
drive

- Optional bus-hold or weak pullup on selected I/O
pins

- Optional configurable grounds on unused I/Os

- Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels on all parts

- PLA architecture

· Superior pinout retention

· 100% product term routability across function

block

- Hot pluggable

- Design entry /verification using Xilinx and industry
standard CAE tools

- Free software support for all densities using Xilinx
WebPACK™ or WebFITTER™ tools

- Industr y leading nonvolatile 0.18 micron CMOS
process

- Guaranteed 1,000 program /era se cycl e s

- Guaranteed 20 year data retention

Refer to the CoolRunner™-II family data sheet for architec-
ture description.

Description

The CoolRunner-II 64-macrocell device is designed for both
high performance and low po wer applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli­ability is improved

This device consists of four Function Blocks inter-con­nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combina tional or registered
modes of operation.

Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. T here
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output
control signals include slew rate control, bus hold and open
drain. A Schmitt trigger input is available on a per input pin
basis. In addition to com binatorial and registered outputs,
the registers may be configured as fast inputs.

Clocking is available on a global or Function Block basis.
Three global clocks are available for all Fun ction Blocks as
a synchronous clock source. These clocks are additionally
used to set or preset individual macrocell registers on
power up. Local clocks are generated i n specific Function
Blocks and only available to macrocell registers in that
Function Block.

A DualEDGE flip-flop feature is also available on a per mac­rocell basis. This feature allows performance where it is
needed without raisin g the total power consum ption of the
entire device.

The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL33 and LVCMOS18, 25, and 33 volts
(see Table 1). This device is also 1.5 volt I/O compatible
with the use of Schmitt inputs.

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Fast Zero Power Design Technology

Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. Cool Runner-II CPLDs em ploy
Fast Zer o Power™ (FZP), a design tec hnique that makes
use of CMOS technology in both the fabrication and design
methodology. FZP design technology employs a cascade of
CMOS gates to implement sum of products instead of tradi­tional sense amplifier m ethodolog y. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high performance
and low power operation.

Support ed I/O S tandards

The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See Table 1 for I/ O stan-
dard voltages. The LVTTL I/O standard is a general purpose

EIA/JESDSA standard for 3.3V applications that use an
LVTTL input buffer and Push-Pull output buffer. The LVC­MOS standard is used in 3.3V, 2.5V, 1.8V applications.
CoolRunner-II CPLDs are also 1.5V I/O compatible with the
use of Schmitt inputs.

Table 1: I/O Standards for XC2 C64

I/O

Standard

Output

V

CCIO

Input

V

CCIO

Input

V

REF

Board

Termination

Voltage V

T

LVTTL 3.3V 3.3V N/A N/A
LVCMOS33 3.3 3.3 N/A N/A
LVCMOS25 2.5 2.5 N/A N/A
LVCMOS18 1.8 1.8 N/A N/A

Figure 1: ICC vs Frequency

Table 2: I

CC

vs Frequency (LVCMOS 1.8V TA = 25°C)

(1)

Frequency (MHz)

50 75 100 125 150 175 200 225 250 275 300

Typical I

CC

(mA) 3.6 5.5 7.3 9.1 10.8 12.5 14.2 15.9 17.5 19.2 20.8

Notes:

1. 16-bit up/do wn, r esettable binary counter (one counter per funct ion block).

Frequency (MHz)

DS092_07_121501

I

CC

(mA)

0

0

5

10

15

20

25

30025020015010050

XC2C64 CoolRunner-II CPLD

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Recommended Operating Conditi ons

DC Electrical Characteristics (Over Recommended Operating Conditions)

Absolute Maximum Ratings

Symbol Description Value Units

V

CC

Supply voltage relative to ground –0.5 to 2.0 V

V

CCIO

Supply voltage for output drivers –0.5 to 4.0 V

V

IN

Input voltage relative to ground

(1)

–0.5 to 4.0 V

V

TS

Voltage applied to 3-state output

(1)

–0.5 to 4.0 V

V

STG

Storage Temperature (ambient) –65 to +150 °C

T

SOL

Maximum Soldering temperature (10s @ 1/16in. = 1.5mm) + 60 °C

T

J

Junction Temperature + 50 °C

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During tran sitions,
the device pins may under shoot to –2.0v or overshoot to +4.5V, provided this over or undershoot l asts less than 10 ns and with the
forcing current being limited to 200 mA.

Symbol Parameter Min Max Units

V

CC

Supply voltage for internal logic
and input buffers

Commercial TA = 0°C to +70°C1.7 1.9 V
Industrial T

A

= –40°C to +85°C1.7 1.9 V

V

CCIO

Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V
Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V
Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V
Supply voltage for output drivers @ 1.5V operation

(1)

1.4 1.6 V

Notes:

1. Use input hysteresis for 1.5V LVCMOS.

Symbol Parameter Test Conditions Min. Max. Units

I

CCSB

Standby current V

CC

= 1.9V, V

CCIO

= 3.6V 100 µA

I

CC

Dynamic current f = 1 MHz mA

f = 50 MHz mA

C

JTA G

JTAG input capacitance f = 1 MHz pF

C

CLK

Global clock input capacitance f = 1 MHz pF

C

IO

I/O capacitance f = 1 MHz pF

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LVCMOS 3.3V DC Voltage Specifications

LVCMOS 2.5V DC Voltage Specifications

Symbol Parameter Test Conditions Min. Max. Units

V

CCIO

Input source voltage 3.0 3.6 V

V

IH

High level input voltage 2 V

CCIO

+ 0.3V V

V

IL

Low level input voltage –0.3 0.8 V

V

OH

High l evel output voltag e IOH = –8 mA, V

CCIO

= 3V V

CCIO

– 0.4V - V

I

OH

= –0.1 mA, V

CCIO

= 3V V

CCIO

– 0.2V - V

V

OL

Low level output voltage IOL = 8 mA, V

CCIO

= 3V - 0.4 V

I

OL

= 0.1 mA, V

CCIO

= 3V - 0.2 V

I

IL

Input leakage current VIN = 0V or V

CCIO

to 3.9V –10 10 µA

I

IH

I/O High-Z leakage VIN = 0V or V

CCIO

to 3.9V –10 10 µA

C

JTA G

JTAG input capacitance f = 1 MHz pF

C

CLK

Global clock input capacitance f = 1 MHz pF

C

IO

I/O capacita nce f = 1 MHz pF

Symbol Parameter Test Conditions Min. M ax. Units

V

CCIO

Input source voltage 2.3 2.7 V

V

IH

High level input voltage 1.7 3.9 V

V

IL

Low level input voltage –0.3 0.7 V

V

OH

High l evel output voltag e IOH = –8 mA, V

CCIO

= 3V V

CCIO

– 0.4V - V

I

OH

= –0.1 mA, V

CCIO

= 3V V

CCIO

– 0.2V - V

V

OL

Low level output voltage IOL = 8 mA, V

CCIO

= 3V - 0.4 V

I

OL

= 0.1mA, V

CCIO

= 3V - 0.2 V

I

IL

Input leakage current VIN = 0V or V

CCIO

to 3.9V –10 10 µA

I

IH

I/O High-Z leakage VIN = 0V or V

CCIO

to 3.9V –10 10 µA

C

JTA G

JTAG input capacitance f = 1 MHz pF

C

CLK

Global clock input capacitance f = 1 MHz pF

C

IO

I/O capacitance f = 1 MHz pF