XILINX XC18V512PC20C, XC18V256VQ44I, XC18V256VQ44C, XC18V256SO20I, XC18V256SO20C Datasheet
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DS026 (v3.0) November 12, 2001 www.xilinx.com 1
Product Specification 1-800-255-7778
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
- Endurance of 20,000 program/erase cycles
- Program/erase over full commercial/industrial
voltage and temperature range
• IEEE Std 1149.1 boundary-scan (JTAG) support
• Simple interface to the FPGA
• Cascadable for storing longer or multiple bitstreams
• Low-power advanced CMOS FLASH process
• Dual configuration modes
- Serial Slow/Fast configuration (up to 33 MHz)
- Parallel (up to 264 Mb/s at 33 MHz)
• 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals
• 3.3V or 2.5V output capability
• Available in PC20, SO20, PC44 and VQ44 packages
• Design support using the Xilinx Alliance and
Foundation series software packages.
• JTAG command initiation of standard FPGA
configuration
Description
Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs (Figure 1). Initial de vices i n this
3.3V family are a 4-megabit, a 2-megabit, a 1-megabit, a
512-Kbit, and a 256-Kbit PROM that provide an
easy-to-use, cost-effective method for re-programming an d
storing large Xilinx FPGA or CPLD configuration bitstreams.
When the FPGA is in Master Seri al mode, it generates a
configuration clock that dr ives the PROM. A short access
time after the rising CCLK , data is available on the PROM
DATA (D0) pin that is connecte d to the F PGA D
IN
pin. The
FPGA generates the appro priate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA a re clocked by an
external clock.
When the FPGA is in Sl av e-P ara llel or Sele ctMAP Mode , an
external oscillator generates the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, dat a ar e a v ai lab l e on t he PR OM s D ATA (D0-D7) pi n s.
The data is clocked into the F PGA on the following rising
edge of the CCLK. Neither Slave-Parallel nor SelectMAP
utilize a Length Count, so a free-r unning oscillator can be
used.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other memb ers of the family or with
the XC17V00 one-time programmable Serial PROM family.
0
XC18V00 Series of In-System
Programmable Configuration
PROMs
DS026 (v3.0) November 12, 2001
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Product Specification
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Figure 1: XC18V00 Series Block Diagram
Control
and
JTAG
Interface
Memory
Serial
or
Parallel
Interface
D0 DATA
(Serial or Parallel
[Slave-Parallel/SelectMAP] Mode)
D[1:7]
Slave-Parallel and
SelectMAP Interface
Data
Address
CLK
CE
TCK
TMS
TDI
TDO
OE/Reset
CEO
Data
DS026_01_111201
7
CF
XC18V00 Series of In-System Programmable Configuration PROMs
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1-800-255-7778 Product Specification
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Pinout and Pin Description
Table 1: Pin Names and Descriptions (pins not listed are “no connect”)
Pin
Name
Boundary
Scan
Order Function Pin Description
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC and
PLCC
D0 4 DATA OUT D0 is the DATA output pin to provide data for
configuring an FPGA in serial mode.
40 2 1
3OUTPUT
ENABLE
D1 6 DATA OUT D0-D7 are the output pins to provide parallel data
for configuring a Xilinx FPGA in
Slave-Parallel/SelectMap mode.
29 35 16
5OUTPUT
ENABLE
D2 2 DATA OUT 42 4 2
1OUTPUT
ENABLE
D3 8 DATA OUT 27 33 15
7OUTPUT
ENABLE
D4 24 DATA OUT 9 15 7
(1)
23 OUTPUT
ENABLE
D5 10 DATA OUT 25 31 14
9OUTPUT
ENABLE
D6 17 DATA OUT 14 20 9
16 OUTPUT
ENABLE
D7 14 DATA OUT 19 25 12
13 OUTPUT
ENABLE
CLK 0 DATA IN Each rising edge on the CLK input increments the
internal address counter if both CE
is Low and
OE/RESET
is High.
43 5 3
OE/
RESET
20 DATA IN When Low, this input holds the address counter
reset and the DATA output is in a high-impedance
state. This is a bidirectional open-drain pin that is
held Low while the PROM is reset. Polarity is NOT
programmable.
13 19 8
19 DATA OUT
18 OUTPUT
ENABLE
CE
15 DATA IN When CE is High, this pin puts the device into
standby mode and resets the address counter. The
DATA output pin is in a high-impedance state, and
the device is in low power standby mode.
15 21 10
XC18V00 Series of In-System Pr ogrammable Configuration PROMs
DS026 (v3.0) November 12, 2001 www.xilinx.com 3
Product Specification 1-800-255-7778
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CF 22 DATA OUT Allows JTAG CONFIG instructio n to initiate FPGA
configuration without powering down FPGA. This is
an open-drain output that is pulsed Low by the
JTAG CONFIG command.
10 16 7
(1)
21 OUTPUT
ENABLE
CEO
11 DATA OUT Chip Enable Output (CEO) is connected to the CE
input of the next PROM in the chain. This output is
Low when CE
is Low and OE/RESET input is High,
AND the internal address counter has been
incremented beyond its T erminal Count (TC) value.
When OE/RESET
goes Low, CEO stays High until
the PROM is brought out of reset by bringing
OE/RESET
High.
21 27 13
12 OUTPUT
ENABLE
GND GND is the ground connection. 6, 18,
28 &
41
3, 12,
24 &
34
11
TMS MODE
SELECT
The state of TMS on the rising edge of TCK
determines the state transitions at the T est Access
Port (T AP) controller. TMS has an internal 50K ohm
resistive pull-up on it to provide a logic “1” to the
device if the pin is not driven.
511 5
TCK CLOCK This pin is the JTAG test clock. It sequences the
TAP controller and all the JTAG test and
programming electronics.
713 6
TDI DATA IN This pin is the serial input to all JTAG instruction
and data registers. TDI has an internal 50K ohm
resistive pull-up on it to provide a logic “1” to the
system if the pin is not driven.
39 4
TDO DATA OUT This pin is the serial output for all JTAG instruction
and data registers. TDO has an internal 50K ohm
resistive pull-up on it to provide a logic “1” to the
system if the pin is not driven.
31 37 17
V
CC
Positive 3.3V supply voltage for internal logic and
input buffers.
17, 35
& 38
23, 41
& 44
18 & 20
V
CCO
Positive 3.3V or 2.5V supply voltage connected to
the output voltage drivers.
8, 16,
26 &
36
14, 22,
32 &
42
19
Notes:
1. Pin 7 is CF
in Serial Mode, D4 in Slave-Parallel Mode for 20-pin packages.
Table 1: Pin Names and Descriptions (pins not listed are “no connect”) (Continued)
Pin
Name
Boundary
Scan
Order Function Pin Description
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC and
PLCC
XC18V00 Series of In-System Programmable Configuration PROMs
4 www.xilinx.com DS026 (v3.0) November 12, 2001
1-800-255-7778 Product Specification
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Xilinx FPGAs and Compatible PROMs
Table 2 provides a list of Xilinx FPGAs and compatible
PROMs.
Capacity
In-System Programming
In-System Programmable PROMs can be programmed individually, or two or more can be daisy-chained tog ether and
programmed in-system vi a the standard 4- pin JTAG protocol as shown in Figure 2. In-system programming offers
quick and efficient desig n iterations and el iminates unnecessary package handling or socketing of devices. The Xilinx
development system provides the programming data
sequence using either Xilinx JTAG Programmer software
and a download cable, a third-party JT A G dev elopment system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction
sequence. The JTAG Programmer software also outputs
Table 2: Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
XC18V00
Solution
XC2V40 360,160 XC18V512
XC2V80 635,360 XC18V01
XC2V250 1,697,248 XC18V02
XC2V500 2,761,952 XC18V04
XC2V1000 4,082,656 XC18V04
XC2V1500 5,659,360 XC18V04
+ XC18V02
XC2V2000 7,492,064 2 of XC18V04
XC2V3000 10,494,432 3 of XC18V04
XC2V4000 15,660,000 4 of XC18V04
XC2V6000 21,849,568 5 of XC18V04
+ XC18V02
XC2V8000 29,063,136 7 of XC18V04
XCV50 559,200 XC18V01
XCV100 781,216 XC18V01
XCV150 1,040,096 XC18V01
XCV200 1,335,840 XC18V02
XCV300 1,751,808 XC18V02
XCV400 2,546,048 XC18V04
XCV600 3,607,968 XC18V04
XCV800 4,715,616 XC18V04 +
XC18V512
XCV1000 6,127,744 XC18V04 +
XC18V02
XCV50E 630,048 XC18V01
XCV100E 863,840 XC18V01
XCV200E 1,442,106 XC18V02
XCV300E 1,875,648 XC18V02
XCV400E 2,693,440 XC18V04
XCV405E 3,430,400 XC18V04
XCV600E 3,961,632 XC18V04
XCV812E 6,519,648 2 of XC18V04
XCV1000E 6,587,520 2 of XC18V04
XCV1600E 8,308,992 2 of XC18V04
XCV2000E 10,159,648 3 of XC18V04
XCV2600E 12,922,336 4 of XC18V04
XCV3200E 16,283,712 4 of XC18V04
XC2S15 197,696 XC18V256
XC2S30 336,768 XC18V512
XC2S50 559,200 XC18V01
XC2S100 781,216 XC18V01
XC2S150 1,040,096 XC18V01
XC2S200 1,335,840 XC18V02
XC2S50E 630,048 XC18V01
XC2S100E 863,840 XC18V01
XC2S150E 1,134,528 XC18V02
XC2S200E 1,442,016 XC18V02
XC2S300E 1,875,648 XC18V02
Devices Configuration Bits
XC18V04 4,194,304
XC18V02 2,097,152
XC18V01 1,048,576
XC18V512 524,288
XC18V256 262,144
Table 2: Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
XC18V00
Solution
XC18V00 Series of In-System Pr ogrammable Configuration PROMs
DS026 (v3.0) November 12, 2001 www.xilinx.com 5
Product Specification 1-800-255-7778
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serial vector format (SVF) files for use with any tools tha t
accept SVF format and with automatic test equipment.
All outputs are held in a high-impedance state or held at
clamp levels during in-system programming.
OE/RESET
The ISP programming algorithm requires issuance of a
reset that causes OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx HW-130 device programmer. This provides the
added flexibility of using pre-pr ogrammed devices in board
design and boundary-scan manufacturing tools, with an
in-system programmable option for future enhancements
and design changes.
Reliability and Endurance
Xilinx in-system p rogrammable product s provide a guaranteed endurance level of 20,000 in-system program/erase
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data retention
specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading. Table 3
shows the security setting available.
The read security bit ca n be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
Table 3: Data Security Options
IEEE 1149.1 Boundary-Scan (JTAG)
The XC18V00 family is fully comp liant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are pr ovided to s up port all
required boundary scan instructions, as well as many of the
optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system pro-
gramming (ISP) to facilitate configuration, erasure, and
verification operations on the XC18V00 device.
Table 4 lists the required and optional boundary-scan
instruction s supported in the XC18V 00. Refer to the IEEE
Std. 1149.1 specification for a complete description of
boundary-sc an architecture and the required and optional
instructions.
Default = Reset Set
Read Allowed
Program/Erase Allowed
Read Inhibited via JTAG
Erase Allowed
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
DS026_02_011100
GND
V
CC
(a) (b)
XC18V00 Series of In-System Programmable Configuration PROMs
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1-800-255-7778 Product Specification
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Instruction Register
The Instruction Register (IR) for the XC18V00 is eight bits
wide and is connected between TDI and TDO during an
instruction scan s equenc e. In pre paration for an inst r uctio n
scan sequence, the instruction register is parallel loaded
with a fixed instruction capture pattern. This pattern is
shifted out onto TDO (LSB first), while an instruction is
shifted into the instr uction register from TDI. The detailed
composition of the in struction capture pat tern is illustrated
in Figure 3.
The ISP Status field, IR(4), contains logic “1” if the device is
currently in ISP m ode; otherwise, it contains log ic “0”. The
Security field, IR(3), contains logic “1” if the device has been
programmed with the security option turned on; otherwise, it
contains logic “0”.
Boundary Scan Register
The boundary -scan registe r is used to cont rol and obser ve
the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instruction s. Each output pin
on the XC18V00 has two regist er stages that cont ribute to
the boundary -scan register, while each input pin o nly has
one register stage.
For each output pin, the register stage neare st to TDI controls and obser ves the output state, and th e second stage
closest to TDO controls and observes the High-Z enable
state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is use d
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be sh ifte d ou t for examination by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (50h for XC18V00 family)
a = the ISP PROM product ID (26h for the XC18V04)
c = the company code (49h for Xilinx)
Note: The LSB of the I DCODE register is always read as
logic “1” as defined by IEEE Std. 1149.1
Table 5 lists th e IDCODE register values for the XC18V0 0
devices.
The USERCODE instr uction gives access to a 32-bit user
programmable scratch pad typically used to supply information about the device’s programmed contents. By using th e
USERCODE instruction, a user-programmable identification code can be shifte d out for examination. This code is
loaded into the USERCODE register during programming of
the XC18V00 device. If the device is blank or was not
loaded during programming, the US ERCODE registe r c ontains FFFFFFFFh.
Table 4: Boundary Scan Instructions
Boundary-Scan
Command
Binary
Code [7:0] Description
Required Instructions
BYPASS 11111111 Enab l es BYPASS
SAMPLE/
PRELOAD
00000001 Enables boundary-scan
SAMPLE/PRELOAD operation
EXTEST 00000000 Enabl es bou ndary-scan
EXTEST operation
Optional Instructions
CLAMP 11111010 Enables boundary-scan
CLAMP operation
HIGHZ 11111100 all outputs in high-impedance
state simultaneously
IDCODE 11111110 Enables shifting out
32-bit IDCODE
USERCODE 11111101 Enables shifting out
32-bit USERCODE
XC18V00 Specific Instructions
CONFIG 11101110 Initiates FPGA configuration
by pulsing CF
pin Low
IR[7:5] IR[4] IR[3] IR[2] IR[1:0]
TDI-> 0 0 0 ISP
Status
Security 0 0 1 ->TD
O
Notes:
1. IR(1:0) = 01 is specified by IEEE Std. 1149.1
Figure 3: Instruction Register Values Loaded into IR as
Part of an Instruction Scan Sequence
Table 5: IDCODES Assigned to XC18V00 Devices
ISP-PROM IDCODE
XC18V01 05024093h
XC18V02 05025093h
XC18V04 05026093h
XC18V256 05022093h
XC18V512 05023093h
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