XILINX XC17V16VQ44I, XC17V16VQ44C, XC17V16PC44I, XC17V16PC44C, XC17V08VQ44I Datasheet

DS073 (v1.5) October 9, 2001 www.xilinx.com 1
Advance Product Specification 1-800-255-7778

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Features

• One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices

• Simple interface to the FPGA

• Cascadable for storing longer or multiple bitstreams

• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions

• Low-power CMOS Floating Gate process

• 3.3V supply voltage

• Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20

• Programming support by leading programmer
manufacturers.

• Design support using the Xilinx Alliance and
Foundation series software packages.

• Dual configuration modes for the XC17V16 and
XC17V08 devices

- Serial slow/fast configuration (up to 33 Mb/s)

- Parallel (up to 264 Mb/s at 33 MHz)

• Guaranteed 20 year life data retention

Description

Xilinx introduces the high-density XC17V00 family of config­uration PROMs which provide an easy-to-use, cost-effec­tive method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1
and Figure 2 for simplified block diagrams of the XC17V00
family.

When the FPGA is in Master Seri al mode, it generates a
configuration clock that dr ives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appro priate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.

When the FPGA is in SelectMAP mode, an external oscilla­tor will generate the configuration clock that drives the
PROM and the FPGA. After the rising CCLK edge, data are
available on the PROMs DATA (D0-D7) p ins. The data will
be clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator may be used to drive CCLK.
See Figure 3.

Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.

For device programming, either the Xilinx Alli ance or Foun­dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans­ferred to most commercial PROM programmers.

0

XC17V00 Series Configuration
PROM

DS073 (v1.5) October 9, 2001

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Advance Product Specification

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XC17V00 Series Configuration PROM

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Figure 1: Simplified Block Diagram for XC17V04, XC17V02 , and XC17V01 (does not show programming circuit)

Figure 2: Simplified Block Diagram for XC17V16 and XC17V08 (does not show programming circuit)

EPROM

Cell

Matrix

Address Counter

CE

DATA

OE

Output

CLK

V

CC

V

PP

GND

DS073_01_072600

TC

OE

RESET/

OE/

RESET

or

CEO

EPROM

Cell

Matrix

Address Counter

CE

D0 Data
(Serial or Parallel Mode)

OE

8

Output

CLK

BUSY

V

CC

V

PP

GND

DS073_02_072600

TC

OE

RESET/

OE/

RESET

or

D[1:7]
(SelectMAP Interface)

CEO

77

XC17V00 Series Configuration PROM

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Pin Description

DATA[0:7]

Data output is in a high-impedance state when either CE or
OE

are inactive. During programming, the D0 pin is I/O.

Note that OE

can be programmed to be either active High or

active Low.

Note: XC17V04, XC17V02, and XC17 V01 have serial output
only.

CLK

Each rising edge on the CLK input incr ements the inter nal
address counter, if both CE

and OE are active.

RESET/OE

When High, this input holds th e address counte r reset and
puts the DATA output in a high-impedance state. The polar­ity of this input pin is programmable as either RESET/OE

or

OE/RESET

. To avoid confusion, this document describes

the pin as RESET/OE

, although the opposite polarity is pos­sible on all devices. When RESET is active, the address
counter is held at “0”, and puts the DATA output in a
high-impedance state. The po larity of this input is program­mable. The default is active High RESET, but the preferred
option is active Low RESET

, because it can connected to

the FPGAs INIT

pin and a pullup resistor.

The polarity of this pin is controlled in the programmer inter­face. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have differ­ent methods to invert this pin.

CE

When High, this p in disables the inter nal address coun ter,
puts the DAT A output in a high-impedance state, and forces
the device into low-I

CC

standby mode.

CEO

Chip Enable output, to be c onnect ed to th e C E input of the
next PROM in the daisy chain. This output is Low when the
CE

and OE inputs are both active AND the internal address
counter has been increm ented beyond its Terminal Coun t
(TC) value. In other words: when the PROM has been read,
CEO

will follow CE as long as OE is active. When OE goes

inactive, CEO

stays High until the PROM is reset. Note that

OE

can be programmed to be either active High or active
Low .

BUSY (XC17V16 and XC17V08 only)

If BUSY pin is floating, the user must program the BUSY bit
which will cause BUSY pin to be internally tied to a
pull-down resistor. When asserted High, output data are
held and when BUSY pin goes Low, data output will
resume.

V

PP

Programming voltage. No overshoot above the specified
max voltage is permitted on th is p in . For normal read oper ­ation, this pin must be connected to V

CC

. Failure to do so
may lead to unpredictable, temperature-dependent op era­tion and severe problems in circuit debugging. Do not leave
V

PP

floating!

VCC and GND

Positive supply and ground pins.

PROM Pinouts for XC17V16 and XC17V08

(Pins not listed are “no connect”)

Capacity

Pin Name 44-pin VQFP 44-pin PLCC

BUSY 24 30
D0 40 2
D1 29 35
D2 42 4
D3 27 33
D4 9 15
D5 25 31
D6 14 20
D7 19 25
CLK 43 5
RESET/OE

(OE/RESET)

13 19

CE

15 21
GND 6, 18, 28, 37, 41 3, 12, 24, 34, 43
CEO

21 27
V

PP

35 41
V

CC

8, 16, 17, 26, 36, 3814, 22, 23, 32,

42, 44

Devices Configuration Bits

XC17V16 16,777,216
XC17V08 8,388,608

XC17V00 Series Configuration PROM

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PROM Pinouts for XC17V04, XC17V02, and
XC17V01

(Pins not listed are “no connect”)

Capacity

Controlling PROMs

Connecting the FPGA device with the PROM.

• The DATA output(s) of the PROM(s) drives the D

IN

input of the lead FPGA device.

• The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).

• The CEO

output of a PROM drives the CE in put of the

next PROM in a daisy chain (if any).

• The RESET

/OE input of all PROMs is best driven by

the INIT

output of the lead FPGA device. This
connection assur es that th e PROM addres s counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V

CC

glitch.

• The PROM CE

input is best connected to the FPGA

DONE pin(s) and a pullup resistor. CE

can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
15 mA maximum.

• SelectMAP mode is similar to Slave Serial mo de. The
DATA is clocked out of the P ROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.

Pin Name

8-pi

VOIC

(1)

20-pin

SOIC

(1)

20-pin

PLCC

(1,2)

44-pin

VQFP

(2)

44-pin

PLCC

(2)

DA TA 1 1 1 40 2
CLK 2 3 3 43 5
RESET/OE

(OE/RESET)

38 8 1319

CE 410101521
GND 5 11 11 18, 41 24, 3
CEO

613132127

V

PP

718183541

V

CC

820203844

Notes:

1. XC17V01 available in these packages.

2. XC17V02 and XC17V04 available in these packages.

Devices Configuration Bits

XC17V04 4,194,304
XC17V02 2,097,152
XC17V01 1,679,360

Xilinx FPGAs and Compatible PROMs

Device

Configuration

Bits PROM

XC2V40 360,160 XC17V01

XC2V80 635,360 XC17V01
XC2V250 1,697,248 XC17V02
XC2V500 2,761,952 XC17V04

XC2V1000 4,082,656 XC17V04
XC2V1500 5,659,360 XC17V08
XC2V2000 7,492,064 XC17V08
XC2V3000 10,494,432 XC17V16
XC2V4000 15,660,000 XC17V16
XC2V6000 21,849, 568 XC17V16 +

XC17V08

XC2V8000 29,063,072 2 of XC17V16

XCV50 559,200 XC17V01
XCV100 781,216 XC17V01
XCV150 1,040,096 XC17V01
XCV200 1,335,840 XC17V01
XCV300 1,751,808 XC17V02

XCV400 2,546,048 XC17V04
XCV600 3,607,968 XC17V04
XCV800 4,715,616 XC17V08

XCV1000 6,127,744 XC17V08

XCV50E 630,048 XC17V01
XCV100E 863,840 XC17V01
XCV200E 1,442,106 XC17V01
XCV300E 1,875,648 XC17V02
XCV400E 2,693,440 XC17V04
XCV405E 3,430,400 XC17V04
XCV600E 3,961,632 XC17V04
XCV812E 6,519,648 XC17V08

XCV1000E 6,587,520 XC17V08
XCV1600E 8,308,992 XC17V08
XCV2000E 10,159,648 XC17V16
XCV2600E 12,922,336 XC17V16
XCV3200E 16,283,712 XC17V16

Notes:

1. The suggested PR OM is det ermined by compati bility with the
higher configuration frequency of the Xilinx FPGA CCLK.

Xilinx FPGAs and Compatible PROMs

Device

Configuration

Bits PROM