XILINX XC17V00 Product Specification
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DS073 (v1.0) July 26, 2000
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Features
• One-time programmable (OTP) read-only memory
designe d to sto re c on f ig ur ation bitstr ea m s o f X ilinx
FPGA devices
• Simple interface to the FPGA; configurable to use a
one user I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibilit y with d iffe re nt FP GA solution s
• Supports fast configuration
• Low-power CMOS Floating Gate process
• 3.3V supply voltage
• Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20
• Programming support by leading programmer
manufacturers.
• Design support using the Xilin x Alli anc e and
Foundation series software packages.
• Dual configuration modes for the XC17V16 and
XC17V08
- Serial slow/fast configuration (up to 33 MHz)
- Parallel (up to 264 MHz)
• Guaranteed 20 year life data retention
XC17V00 Series Configuration
PROM
Advance Product Specification
Description
Xilinx introduces the high-density XC17V00 family of configuration PROMs which provide an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA out put pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate num ber of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
When the FPGA is in SelectMAP mode, an external oscillator will generate the configuration clock that drives the
PROM and the FPGA. After the rising CCLK edge, data are
available on the P ROMs DATA (D0-D7) pins. The data will
be clocked into the FPGA on the following rising edge of the
CCLK. SelectMAP does not utilize a Length Count, so a
free-running oscillator may be used. See Figure 3.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA
design file into a standard He x format, which is then t ransferred to most commercial PROM programmers.
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS073 (v1.0) July 26, 2000 www.xilinx.com 1
Advance Product Specifi cation 1-800-255-7778
XC17V00 Series Configuration PR OM
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RESET/
OE
or
OE/
RESET
CE
CLK
V
CC
V
PP
GND
CEO
Address Counter
EPROM
Cell
TC
Output
OE
DATA
Matrix
DS073_01_072600
Figure 1: Simplified Block Diagram for XC17V04, XC17V02, and XC17V01 (does not show programming circuit)
RESET/
OE
or
OE/
RESET
CE
CLK
BUSY
V
CC
V
PP
GND
CEO
Address Counter
EPROM
Cell
Matrix
TC
Output
8
OE
D0 Data
(Serial or Parallel Mode)
77
D[1:7]
(SelectMAP Interface)
DS073_02_072600
Figure 2: Simplified Block Diagram for XC17V16 and XC 17V08 (does not show programming circuit)
2 www.xilinx.com DS073 (v1.0) July 26, 2000
1-800-255-7778 Advance Product Specification
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XC17V00 Series Configuration PR OM
Pin Description
DATA[0:7]
Data output is in a high-impedance state when either CE or
OE
are inactive. During programming, the D0 pin is I/O.
Note that OE
active Low.
Note: XC17V04, XC17V02, and XC17V01 have serial output
only.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE
RESET/OE
When High, this input hol ds the ad dress counter res et and
puts the DATA output in a high-impedance state. The polarity of this input pin is programmable as either RESET/OE
OE/RESET
the pin as RESET/OE
sible on all devices. When RESET is active, the address
counter is held at "0", and puts the DATA output in a
high-impedance state. The polarity of this input is programmable. The default is ac tive High RE SET, but the preferred
option is active Low RESET
FPGAs INIT
The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have different methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I
can be programmed to be either active High or
and OE are ac tive .
or
. To avoid confusion, this document describes
, although the opposite polarity is pos-
, because it can be driven by the
pin.
standby mode.
CC
BUSY (XC17V16 and XC17V08 only)
If BUSY pin is floating, the user must program the BUSY bit
which will cause BUSY pin to go Low internally. When
asserted High, output data are held and when BUSY pin
goes Low, data output will resume.
V
PP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read operation, this pin must be connected to V
may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave
V
floating!
PP
. Failure to do so
CC
VCC and GND
Positive supply and ground pins.
PROM Pinouts for XC17V16 and XC17V08
Pin Name 44-pin VQFP 44-pin PLCC
BUSY 24 30
D0 40 2
D1 29 35
D2 42 4
D3 27 33
D4 9 15
D5 25 31
D6 14 20
D7 19 25
CLK 43 5
CEO
Chip Enable output, to be connected t o the CE input of t he
next PROM in the daisy chain. This output is Low when the
CE
and OE inputs are both active AND the internal address
counter has been increment ed beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO
will follow C E as long as OE is act i v e . W h en OE goes
inactive, CE O
OE
can be programmed t o be either active High or active
Low.
stays High until the PROM is reset. Note that
RESET/OE
(OE/RESET)
CE
GND 6, 18, 28, 27, 41 3, 12, 24, 34, 43
CEO
V
PP
V
CC
8, 16, 17, 26, 36, 3814, 22, 23, 32,
13 19
15 21
21 27
35 41
42, 44
Capacity
Devices Configuration Bits
XC17V16 16,777,216
XC17V08 8,388,608
DS073 (v1.0) July 26, 2000 www.xilinx.com 3
Advance Product Specifi cation 1-800-255-7778
XC17V00 Series Configuration PR OM
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PROM Pinouts for XC17V04, XC17V02, and XC17V01
8-pin
Pin Name
VOIC
DATA 112402
CLK 2 3 4 43 5
RESET/OE
(OE/RESET)
CE
GND 5 11 10 18, 41 24, 3
CEO
V
PP
V
CC
20-pin
SOIC
20-pin
PLCC
44-pin
VQFP
44-pin
PLCC
38 6 1319
410 8 15 21
61314 2127
71817 35 41
82020 38 44
Capacity
Devices Configuration Bits
XC17V04 4,194,304
XC17V02 2,701,312
XC17V01 1,679,360
Xilinx FPGAs and Compatible PROMs
Configuration
Device
XCV50 559,200 XC17V01
XCV100 781,216 XC17V01
XCV150 1,040,096 XC17V01
XCV200 1,335,840 XC17V01
XCV300 1,751,808 XC17V02
XCV400 2,546,048 XC17V02
XCV600 3,607,968 XC17V04
XCV800 4,715,616 XC17V08
XCV1000 6,127,744 XC17V08
XCV50E 630,048 XC17V01
XCV100E 863,840 XC17V01
XCV200E 1,442,106 XC17V01
XCV300E 1,875,648 XC17V02
XCV400E 2,693,440 XC17V02
Bits PROM
Xilinx FPGAs and Compatible PROMs
Configuration
Device
Bits PROM
XCV600E 3,961,632 XC17V04
XCV812E 6,519,648 XC17V08
XCV1000E 6,587,520 XC17V08
XCV1600E 8,308,992 XC17V08
XCV2000E 10,159,648 XC17V16
XCV2600E 12,922,336 XC17V16
XCV3200E 16,283,712 XC17V16
Notes:
1. The sugges ted PROM is determined by compat ibility wi th the
higher configuration frequency of the Xil inx FPGA CCLK.
Controlling PROMs
Connecting the FPGA device with the PROM.
• The DATA output(s) of the of the PROM(s) drives the
input of the lead FPGA device.
D
IN
• The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
• The CEO
next PROM in a daisy chain (if any).
• The RESET
the INIT
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V
Other methods—such as d riving RESET
or system reset—assume the PROM internal
power-on-reset is always in step with the FPGA’s
internal power-on-reset. This may not be a safe
assumption.
• The PROM CE
or DONE pins. Using LDC avoids potential contention
on the D
• The CE
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC
unconditionally High during user operation. CE
also be permanent ly tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
• SelectMA P mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte p er CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.
output of a PROM drives the CE inp ut of the
/OE input of all PROMs is best driven by
output of the lead FPGA device. This
glitch.
CC
/OE from LDC
input can be driven from either the LDC
pin.
IN
input of the lead (or on ly) PROM is driven by
can be used to drive CE, but must then be
can
XCV405E 3,340,400 XC17V04
4 www.xilinx.com DS073 (v1.0) July 26, 2000
1-800-255-7778 Advance Product Specification
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