XILINX XC17S50XLPD8C, XC17S40XLSO20I, XC17S40XLSO20C, XC17S40XLPD8I, XC17S50XLSO20I Datasheet
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DS030 (v1.8) October 10, 2001 www.xilinx.com 1
Product Specification 1-800-255-7778
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
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Introduction
The Spartan™ family of PROMs provides an easy-to-us e,
cost-effective method for storing Sp ar tan device configuration bitstreams.
When the Spartan device is in Master Serial mode, it generates a configuration clock that drives the Spartan PROM. A
short ac cess time after the r ising c lock edg e, data ap pears
on the PROM DATA output pin that is connected to the Spartan device D
IN
pin. The Spartan device generates the
appropriate number of c lock pulses to com plete th e confi guration. Once configured, it disables the PROM. When a
Spartan device is in Sl ave Serial mode, the P ROM and the
Spartan device must both be clocked by an incoming signal.
For device programming, either the Xilinx Alliance or the
Foundation series development systems compiles the Spartan device design file into a standard HEX format which is
then transferred to most commercial PROM programmers.
Spartan PROM Features
• Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan, Spartan-XL, and Spartan-II FPGA devices
• Simple interface to the Spartan device requires only
one user I/O pin
• Programmable reset polarity (active High or active
Low)
• Low-power CMOS floating gate process
• Available in 5V and 3.3V versions
• Available in compact plastic 8-pin DIP, 8-pin VOIC, or
20-pin SOIC packages.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• Guaranteed 20 year life data retention
0
Spartan Family of One-Time
Programmable Configuration
PROMs (XC17S00)
DS030 (v1.8) October 10, 2001
05
Product Specification
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Spartan FPGA Configuration Bits Compatible Spartan PROM
XCS05 53,984 XC17S05
XCS05XL 54,544 XC17S05XL
XCS10 95,008 XC17S10
XCS10XL 95,752 XC17S10XL
XCS20 178,144 XC17S20
XCS20XL 179,160 XC17S20XL
XCS30 247,968 XC17S30
XCS30XL 249,168 XC17S30XL
XCS40 329,312 XC17S40
XCS40XL 330,696 XC17S40XL
XC2S50 559,232 XC17S50XL
XC2S100 781,248 XC17S100XL
XC2S150 1,040,128 XC17S150XL
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
2 www.xilinx.com DS030 (v1.8) October 10, 2001
1-800-255-7778 Product Specification
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Pin Description
Controlling PROMs
Connecting the Spartan device with the PROM:
• The DATA output of the PROM drives the D
IN
input of
the lead Spartan device.
• The Master Spartan device CCLK output drives the
CLK input of the PROM.
• The RESET
/OE input of the PROM is driven by the
INIT
output of the Spartan device. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
reconfiguration is initiated by a V
CC
glitch. Other
methods—such as driving RESET
/OE from LDC or
system reset—assume that the PROM internal
power-on-reset is always in step with the FPGAs
internal power-on-reset, which may not be a safe
assumption.
• The CE
input of the PROM is driven by the DONE
output of the Spartan device, provided that DONE is
not permanently grounded. Otherwise, LDC
can be
used to drive CE
, but must then be unconditionally
High during user operation. CE
can also be
permanently tied Low, but this keeps the DATA o utput
active and causes an unnecessary supply current of
10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic B lock
(CLB) and their associated interconnections are established
by a configuration program. The pr ogram is loaded either
automatically upon power up, or on command, de pending
on the state of the Spar tan device MODE pin. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memor y. The Spartan PROM has been designed for compatibility with the
Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Ser ial mo de when the MODE pi n is Low.
Data is read from the PROM sequentially o n a single dat a
line. Synchronization i s provided by the rising edge of the
temporary signal CCLK, which is generated during configuration.
Table 1: Spartan PROM Pinouts
Pin Name
8-pin
PDIP and
VOIC
20-pin
SOIC Pin Description
DAT A 1 1 Data output, High-Z state when either CE
or OE are inactive. During programming,
the DATA pin is I/O. Note that OE
can be programmed to be either active High or
active Low.
CLK 2 3 Each rising edge on the CLK input increments the internal address counter, if both
CE
and OE are active.
RESET/OE
(OE/RESET
)
3 8 When High, this input holds the address counter reset and puts the DAT A output in
a high-impedance state. The polarity of this input pin is programmable as either
RESET/OE
or OE/RESET. T o a v oid confusion, this document describes the pin as
RESET/OE
, although the opposite polarity is possible on all devices. When RESET
is active, the address counter is held at zero, and the DATA output is in a
high-impedance state. The polarity of this input is programmable. The default is
active High RESET, but the preferred option is active Low RESET
, because it can
be driven by the FPGAs INIT
pin.
The polarity of this pin is controlled in the programmer interface. This input pin is
easily inverted using the Xilinx HW-130 programmer software. Third-party
programmers have different methods to invert this pin.
CE 4 10 When High, this pin disables the internal address counter, puts the DAT A output in
a high-impedance state, and forces the device into low-I
CC
standby mode.
GND 5 11 GND is the ground connection.
V
CC
7, 8 18, 20 The VCC pins are to be connected to the positive voltage supply.
Notes:
1. Pins not listed in the table are reserved and must not be externally connected.
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
DS030 (v1.8) October 10, 2001 www.xilinx.com 3
Product Specification 1-800-255-7778
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Master Serial mod e provides a simple configuration interface (Figure 1). Only a serial data line and two control lines
are required to configure the Spartan device. Data from the
PROM is read sequentially, accessed via the internal
address and bit counte rs which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function D
IN
pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal o peration. The S partan family takes care of this automatic ally with an on-chip
default pull-up resistor.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple-configurations for a single Spartan device
are stored in a PROM, the OE
pin should be tied Low. Upon
power-up, the internal address counte rs are re set and co nfiguration begins with the first program stor ed in memory.
Since the OE
pin is held Low, the address counters are left
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and config uration begins at the last value of
the address counters.
This method fails if a user appli es RE SET
during the Spartan device configuration process. The Spartan device
aborts the c onfig uration and th en res tarts a new configuration, as intended, but the PROM does no t reset its addre ss
counter, since it never saw a High level on its OE
input. The
new configuration, therefore, reads the remaining data in
the PROM and interpr ets it as preamble, length count etc .
Since the Spartan device is the Master, it issues the necessary number of CCLK pulses, up to 16 million (2
24
) and
DONE goes High. However, the S partan device configuration will be completely wrong, with potential contentions
inside the Spartan device and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
Figure 1: Master Serial Mode.
The one-time-programmable Spartan PROM supports automatic loading of configuration programs.
An early DONE inhibits the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.
D
IN
CCLK
INIT
DONE
Spartan
PROM
DATA
3.3V
CLK
CE
Spartan
Master Serial
(Low Resets the Address Pointer)
DS030_01_101001
CCLK
(Output)
D
IN
D
OUT
(Output)
OE/RESET
MODE
4.7K
V
CC
V
CCVCC
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