Xicor X9269 Technical data

•

A

查询X9269供应商

PPLICATION

AN99 • AN115 • AN124 •AN133 • AN134 • AN135

N

OTES

AND

D

EVELOPMENT

A V A I L A B L E

S

YSTEM

Single Supply / Low Power / 256-tap / 2-Wire bus

X9269

Dual Digitally-Controlled (XDCP

FEATURES

• Dual–Two separate potentiometers

• 256 resistor taps/pot–0.4% resolution

• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer single
supply device
Wiper Resistance, 100 Ω typical V

• 4 Nonvolatile Data Registers for Each
Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power On Recall. Loads Saved Wiper Position on
Power Up.

• Standby Current < 5µA Max

• 50K Ω , 100K Ω versions of End to End Pot
Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes per Bit per
Register

• 24-Lead SOIC, 16-Lead CSP (Chip Scale Pack­age), 24-Lead TSSOP

• Low Power CMOS

• Power Supply V

= 2.7V to 5.5V

CC

CC

= 5V

TM

) Potentiometers

DESCRIPTION

The X9269 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default Data Register (DR0)
to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Address

Data

2-Wire

Bus

Interface

Status

and Control

V

CC

Bus

Interface

V

SS

Write
Read

Transfer

Inc/Dec

Control

Power On Recall

Wiper Counter

Registers (WCR)

Data Registers

(DR0–DR3)

R

H0

W0

R

R

L0

R

R

H1

R

W1

L1

50KΩ or 100KΩ versions

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Characteristics subject to change without notice.

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X9269

DETAILED FUNCTIONAL DIAGRAM

SCL

SDA

A3
A2

A1

A0

WP

INTERFACE

CONTROL

CIRCUITRY

V

CC

AND

Data

R

R

R

H0

L0

W0

Power On
Recall

R0R

1

Wiper
Counter
Register

3

1

3

(WCR)

Wiper
Counter
Register

(WCR)

R2R

8

Power On
Recall

R0R

R2R

Pot 0

50KΩ and 100KΩ

256-taps

Resistor

Array
Pot 1

V

SS

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

R

R

R

H1

L1

W1

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF wireless
systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

REV 1.1.11 2/17/03

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Characteristics subject to change without notice.

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X9269

PIN CONFIGURATION

SOIC/TSSOP

V

R

NC

NC

NC

NC

NC

R

R

WP

A0

CC

H0

W0

A2

1

2

3

4

5

6

X9269

7

8

L0

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

A3

SCL

NC

NC

NC

NC

V

SS

R

W1

R

H1

R

L1

A1

SDA

CSP

2 3 4

1

A

R

H0

B

R

W0

C

R

L0

D

V

CC

A2 A1 R

WP SDA R

NC A3 R

A0 SCL V

Top View–Bumps Down

H1

L1

W1

SS

PIN ASSIGNMENTS

Pin

(SOIC/TSSOP)

1 C2 NC No Connect

2 D2 A0 Device Address for 2-Wire bus.

3 N/A NC No Connect

4 N/A NC No Connect

5 N/A NC No Connect

6 N/A NC No Connect

7D1V

8C1R

9A1R

10 B1 R

11 A2 A2 Device Address for 2-Wire bus.

12 B2 WP

13 B3 SDA Serial Data Input/Output for 2-Wire bus.

14 A3 A1 Device Address for 2-Wire bus.

15 B4 R

16 A4 R

17 C4 R

18 D4 V

19 N/A NC No Connect

20 N/A NC No Connect

21 N/A NC No Connect

22 N/A NC No Connect

23 D3 SCL Serial Clock for 2-Wire bus.

24 C3 A3 Device Address for 2-Wire bus.

Pin

(CSP) Symbol Function

CC

L0

H0

W0

System Supply Voltage

Low Terminal for Potentiometer 0.

High Terminal for Potentiometer 0.

Wiper Terminal for Potentiometer 0.

Hardware Write Protect

L1

H1

W1

SS

Low Terminal for Potentiometer 1.

High Terminal for Potentiometer 1.

Wiper Terminal for Potentiometer 1.

System Ground

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Characteristics subject to change without notice.

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X9269

)

PIN DESCRIPTIONS

Bus Interface Pins

S

ERIAL

D

ATA

I

NPUT

/O

UTPUT

(SDA)

The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.

It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.

S

ERIAL

C

LOCK

(SCL)

This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9269.

Potentiometer Pins

R

, R

H

L

The R

and R

H

pins are equivalent to the terminal

L

connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R
R

such that R

L

and R

H0

are the terminals of POT 0

L0

H

and

and so on.

R

W

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 2 sets of R

such that R

W

W0

is the terminal of POT 0 and so on.

Bias Supply Pins

S

YSTEM

S

UPPLY

V

OLTAGE

(V

)

AND

S

UPPLY

G

ROUND

(V

SS

SS

pin

The V

CC

pin is the system supply voltage. The V

CC

is the system ground.

Other Pins

D

EVICE

A

DDRESS

(A3–A0)

The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9269. A maximum of 16 devices may occupy the
2-Wire serial bus.

N

O

C

ONNECT

No connect pins should be left open. This pins are used for
Xicor manufacturing and testing purposes.

H

ARDWARE

W

RITE

P

ROTECT INPUT (WP)

The WP pin when LOW prevents nonvolatile writes to
the Data Registers.

REV 1.1.11 2/17/03

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Characteristics subject to change without notice.

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X9269

PRINCIPLES OF OPERATION

The X9269 is a integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:

– Resistor Array Description

– Serial Interface Description

– Instruction and Register Description.

Array Description

The X9269 is comprised of a resistor array (see Figure

1). Each array contains 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).

The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.

Power Up and Down Requirements.

There are no restrictions on the power-up or power­down conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH,
VL, VW. The VCC ramp rate specification is always in
effect.

Figure 1. Detailed Potentiometer Block Diagram

One of Two Potentiometers

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] THEN RW = R
IF WCR = FF[H] THEN RW = R

REGISTER 0 REGISTER 1

(DR0) (DR1)

8 8

REGISTER 2 REGISTER 3

(DR2) (DR3)

L

H

MODIFIED SCL

UP/DN

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

WIPER

COUNTER

REGISTER

(WCR)

INC/DEC

LOGIC

UP/DN

CLK

R

H

C
O
U
N
T
E
R

D
E
C
O
D
E

R

L

R

W

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Characteristics subject to change without notice. 5 of 25

X9269

SERIAL INTERFACE DESCRIPTION

Serial Interface

The X9269 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9269 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.

Start Condition

All commands to the X9269 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9269 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
See Figure 2.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9269 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9269 will respond with a final acknowledge.
See Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START ACKNOWLEDGE

1

89

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Characteristics subject to change without notice. 6 of 25

X9269

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9269
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9269 is still busy with the write operation no ACK
will be returned. If the X9269 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

FLOW 1: ACK Polling Sequence

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Yes

No

Issue STOP

INSTRUCTION AND REGISTER DESCRIPTION

Instructions

DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)

The first byte sent to the X9269 from the host is called
the Identification Byte. The most significant four bits of
the slave address are a device type identifier. The
ID[3:0] bits is the device id for the X9269; this is fixed
as 0101[B] (refer to Table 1).

The A[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3-A0 input pins. The slave address is
externally specified by the user. The X9269 compares
the serial data stream with the address input state; a
successful compare of both address bits is required
for the X9269 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A3-A0 inputs
can be actively driven by CMOS input signals or tied
to V

or VSS.

CC

INSTRUCTION BYTE (I)

The next byte sent to the X9269 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [3:0]. The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots. The format is shown in Table 2.

Further

Operation?

Issue

Instruction

Proceed

REV 1.1.11 2/17/03

Yes

No

Issue STOP

Proceed

Register Selection

Register Selected RB RA

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DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

Characteristics subject to change without notice. 7 of 25

X9269

Table 1. Identification Byte Format

Device Type

Identifier

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0101

(MSB) (LSB)

Table 2. Instruction Byte Format

Slave Address

Instruction

Opcode

Register

Selection

Pot Selection

(WCR Selection)

I3 I2 I1 I0 RB RA 0 P0

(MSB) (LSB)

Table 3. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

100100 01/0Read the contents of the Wiper Counter

Register pointed to by P0

OperationI3 I2 I1 I0 RB RA 0 P0

Write Wiper Counter Register 101000 01/0Write new value to the Wiper Counter

Register pointed to by P0

Read Data Register 10111/01/001/0Read the contents of the Data Register

pointed to by P0 and RB-RA

Write Data Register 11001/01/001/0Write new value to the Data Register

pointed to by P0 and RB-RA

XFR Data Register to Wiper
Counter Register

11011/01/001/0Transfer the contents of the Data Register

pointed to by P0 and RB-RA to its
associated Wiper Counter Register

XFR Wiper Counter Register
to Data Register

11101/01/001/0Transfer the contents of the Wiper Counter

Register pointed to by P0 to the Data Reg­ister pointed to by RB-RA

Global XFR Data Registers
to Wiper Counter Registers

00011/01/00 0Transfer the contents of the Data Registers

pointed to by RB-RA of all four pots to their
respective Wiper Counter Registers

Global XFR Wiper Counter
Registers to Data Register

10001/01/00 0Transfer the contents of both Wiper Counter

Registers to their respective data Registers
pointed to by RB-RA of all four pots

Increment/Decrement Wiper
Counter Register

001000 01/0Enable Increment/decrement of the Control

Latch pointed to by P0

Note: 1/0 = data is one or zero

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Characteristics subject to change without notice. 8 of 25