Xicor X9269 Technical data

•

A

查询X9269供应商

PPLICATION

AN99 • AN115 • AN124 •AN133 • AN134 • AN135

N

OTES

AND

D

EVELOPMENT

A V A I L A B L E

S

YSTEM

Single Supply / Low Power / 256-tap / 2-Wire bus

X9269

Dual Digitally-Controlled (XDCP

FEATURES

• Dual–Two separate potentiometers

• 256 resistor taps/pot–0.4% resolution

• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer single
supply device
Wiper Resistance, 100 Ω typical V

• 4 Nonvolatile Data Registers for Each
Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power On Recall. Loads Saved Wiper Position on
Power Up.

• Standby Current < 5µA Max

• 50K Ω , 100K Ω versions of End to End Pot
Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes per Bit per
Register

• 24-Lead SOIC, 16-Lead CSP (Chip Scale Pack­age), 24-Lead TSSOP

• Low Power CMOS

• Power Supply V

= 2.7V to 5.5V

CC

CC

= 5V

TM

) Potentiometers

DESCRIPTION

The X9269 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default Data Register (DR0)
to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Address

Data

2-Wire

Bus

Interface

Status

and Control

V

CC

Bus

Interface

V

SS

Write
Read

Transfer

Inc/Dec

Control

Power On Recall

Wiper Counter

Registers (WCR)

Data Registers

(DR0–DR3)

R

H0

W0

R

R

L0

R

R

H1

R

W1

L1

50KΩ or 100KΩ versions

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Characteristics subject to change without notice.

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X9269

DETAILED FUNCTIONAL DIAGRAM

SCL

SDA

A3
A2

A1

A0

WP

INTERFACE

CONTROL

CIRCUITRY

V

CC

AND

Data

R

R

R

H0

L0

W0

Power On
Recall

R0R

1

Wiper
Counter
Register

3

1

3

(WCR)

Wiper
Counter
Register

(WCR)

R2R

8

Power On
Recall

R0R

R2R

Pot 0

50KΩ and 100KΩ

256-taps

Resistor

Array
Pot 1

V

SS

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

R

R

R

H1

L1

W1

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF wireless
systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

REV 1.1.11 2/17/03

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Characteristics subject to change without notice.

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X9269

PIN CONFIGURATION

SOIC/TSSOP

V

R

NC

NC

NC

NC

NC

R

R

WP

A0

CC

H0

W0

A2

1

2

3

4

5

6

X9269

7

8

L0

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

A3

SCL

NC

NC

NC

NC

V

SS

R

W1

R

H1

R

L1

A1

SDA

CSP

2 3 4

1

A

R

H0

B

R

W0

C

R

L0

D

V

CC

A2 A1 R

WP SDA R

NC A3 R

A0 SCL V

Top View–Bumps Down

H1

L1

W1

SS

PIN ASSIGNMENTS

Pin

(SOIC/TSSOP)

1 C2 NC No Connect

2 D2 A0 Device Address for 2-Wire bus.

3 N/A NC No Connect

4 N/A NC No Connect

5 N/A NC No Connect

6 N/A NC No Connect

7D1V

8C1R

9A1R

10 B1 R

11 A2 A2 Device Address for 2-Wire bus.

12 B2 WP

13 B3 SDA Serial Data Input/Output for 2-Wire bus.

14 A3 A1 Device Address for 2-Wire bus.

15 B4 R

16 A4 R

17 C4 R

18 D4 V

19 N/A NC No Connect

20 N/A NC No Connect

21 N/A NC No Connect

22 N/A NC No Connect

23 D3 SCL Serial Clock for 2-Wire bus.

24 C3 A3 Device Address for 2-Wire bus.

Pin

(CSP) Symbol Function

CC

L0

H0

W0

System Supply Voltage

Low Terminal for Potentiometer 0.

High Terminal for Potentiometer 0.

Wiper Terminal for Potentiometer 0.

Hardware Write Protect

L1

H1

W1

SS

Low Terminal for Potentiometer 1.

High Terminal for Potentiometer 1.

Wiper Terminal for Potentiometer 1.

System Ground

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Characteristics subject to change without notice.

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X9269

)

PIN DESCRIPTIONS

Bus Interface Pins

S

ERIAL

D

ATA

I

NPUT

/O

UTPUT

(SDA)

The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.

It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.

S

ERIAL

C

LOCK

(SCL)

This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9269.

Potentiometer Pins

R

, R

H

L

The R

and R

H

pins are equivalent to the terminal

L

connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R
R

such that R

L

and R

H0

are the terminals of POT 0

L0

H

and

and so on.

R

W

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 2 sets of R

such that R

W

W0

is the terminal of POT 0 and so on.

Bias Supply Pins

S

YSTEM

S

UPPLY

V

OLTAGE

(V

)

AND

S

UPPLY

G

ROUND

(V

SS

SS

pin

The V

CC

pin is the system supply voltage. The V

CC

is the system ground.

Other Pins

D

EVICE

A

DDRESS

(A3–A0)

The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9269. A maximum of 16 devices may occupy the
2-Wire serial bus.

N

O

C

ONNECT

No connect pins should be left open. This pins are used for
Xicor manufacturing and testing purposes.

H

ARDWARE

W

RITE

P

ROTECT INPUT (WP)

The WP pin when LOW prevents nonvolatile writes to
the Data Registers.

REV 1.1.11 2/17/03

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Characteristics subject to change without notice.

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X9269

PRINCIPLES OF OPERATION

The X9269 is a integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:

– Resistor Array Description

– Serial Interface Description

– Instruction and Register Description.

Array Description

The X9269 is comprised of a resistor array (see Figure

1). Each array contains 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).

The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.

Power Up and Down Requirements.

There are no restrictions on the power-up or power­down conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH,
VL, VW. The VCC ramp rate specification is always in
effect.

Figure 1. Detailed Potentiometer Block Diagram

One of Two Potentiometers

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] THEN RW = R
IF WCR = FF[H] THEN RW = R

REGISTER 0 REGISTER 1

(DR0) (DR1)

8 8

REGISTER 2 REGISTER 3

(DR2) (DR3)

L

H

MODIFIED SCL

UP/DN

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

WIPER

COUNTER

REGISTER

(WCR)

INC/DEC

LOGIC

UP/DN

CLK

R

H

C
O
U
N
T
E
R

D
E
C
O
D
E

R

L

R

W

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Characteristics subject to change without notice. 5 of 25

X9269

SERIAL INTERFACE DESCRIPTION

Serial Interface

The X9269 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9269 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.

Start Condition

All commands to the X9269 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9269 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
See Figure 2.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9269 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9269 will respond with a final acknowledge.
See Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START ACKNOWLEDGE

1

89

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X9269

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9269
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9269 is still busy with the write operation no ACK
will be returned. If the X9269 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

FLOW 1: ACK Polling Sequence

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Yes

No

Issue STOP

INSTRUCTION AND REGISTER DESCRIPTION

Instructions

DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)

The first byte sent to the X9269 from the host is called
the Identification Byte. The most significant four bits of
the slave address are a device type identifier. The
ID[3:0] bits is the device id for the X9269; this is fixed
as 0101[B] (refer to Table 1).

The A[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3-A0 input pins. The slave address is
externally specified by the user. The X9269 compares
the serial data stream with the address input state; a
successful compare of both address bits is required
for the X9269 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A3-A0 inputs
can be actively driven by CMOS input signals or tied
to V

or VSS.

CC

INSTRUCTION BYTE (I)

The next byte sent to the X9269 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [3:0]. The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots. The format is shown in Table 2.

Further

Operation?

Issue

Instruction

Proceed

REV 1.1.11 2/17/03

Yes

No

Issue STOP

Proceed

Register Selection

Register Selected RB RA

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DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

Characteristics subject to change without notice. 7 of 25

X9269

Table 1. Identification Byte Format

Device Type

Identifier

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0101

(MSB) (LSB)

Table 2. Instruction Byte Format

Slave Address

Instruction

Opcode

Register

Selection

Pot Selection

(WCR Selection)

I3 I2 I1 I0 RB RA 0 P0

(MSB) (LSB)

Table 3. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

100100 01/0Read the contents of the Wiper Counter

Register pointed to by P0

OperationI3 I2 I1 I0 RB RA 0 P0

Write Wiper Counter Register 101000 01/0Write new value to the Wiper Counter

Register pointed to by P0

Read Data Register 10111/01/001/0Read the contents of the Data Register

pointed to by P0 and RB-RA

Write Data Register 11001/01/001/0Write new value to the Data Register

pointed to by P0 and RB-RA

XFR Data Register to Wiper
Counter Register

11011/01/001/0Transfer the contents of the Data Register

pointed to by P0 and RB-RA to its
associated Wiper Counter Register

XFR Wiper Counter Register
to Data Register

11101/01/001/0Transfer the contents of the Wiper Counter

Register pointed to by P0 to the Data Reg­ister pointed to by RB-RA

Global XFR Data Registers
to Wiper Counter Registers

00011/01/00 0Transfer the contents of the Data Registers

pointed to by RB-RA of all four pots to their
respective Wiper Counter Registers

Global XFR Wiper Counter
Registers to Data Register

10001/01/00 0Transfer the contents of both Wiper Counter

Registers to their respective data Registers
pointed to by RB-RA of all four pots

Increment/Decrement Wiper
Counter Register

001000 01/0Enable Increment/decrement of the Control

Latch pointed to by P0

Note: 1/0 = data is one or zero

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X9269

DEVICE DESCRIPTION

Wiper Counter Register (WCR)

The X9269 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9269 is powered­down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down. Power­up guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR (See Design
Considerations Section).

Data Registers (DR)

Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bit [7:0] are used to store one of the 256 wiper
positions (0~255).

Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVV

(MSB) (LSB)

Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NV NV NV NV NV NV NV NV

MSB LSB

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X9269

DEVICE DESCRIPTION

Instructions

Four of the nine instructions are three bytes in length.
These instructions are:

– Read Wiper Counter Register – read the current

wiper position of the selected potentiometer,

– Write Wiper Counter Register – change current

wiper position of the selected potentiometer,

– Read Data Register – read the contents of the

selected Data Register;

– Write Data Register – write a new value to the

selected Data Register.

The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t

. A transfer

WRL

from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where the
transfer occurs between all potentiometers and one
associated register

Four instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9269; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:

– XFR Data Register to Wiper Counter Register –

This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register –

This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

– Global XFR Data Register to Wiper Counter

Register – This transfers the contents of all specified
Data Registers to the associated Wiper Counter Reg­isters.

– Global XFR Wiper Counter Register to Data

Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is different
from the other commands. Once the command is
issued and the X9269 has responded with an
acknowledge, the master can clock the selected wiper
up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each
SCL clock pulse (t

) while SDA is HIGH, the

HIGH

selected wiper will move one resistor segment towards
the RH terminal. Similarly, for each SCL clock pulse
while SDA is LOW, the selected wiper will move one
resistor segment towards the RL terminal.

See Instruction format for more details.

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X9269

Figure 3. Two-Byte Instruction Sequence

SCL

SDA

0101

ID3 ID2 ID1 ID0

S
T
A
R

T

Device ID

A3

A2 A0

A1

External
Address

A

I3
C
K

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

0 101

S

ID3 ID2

T
A

Device ID

R
T

ID1

ID0

A2 A1 A0

A3

External
Address

A
C
K

I3

I1

I2

Instruction
Opcode

I0

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

0101

ID3 ID2 ID1 ID0

S
T

A

Device ID
R
T

A3

A2 A1 A0

External
Address

A
C

K

I3 I2

Instruction
Opcode

I1

I2 I1

Instruction
Opcode

RB RA

Register
Address

I0

RB

Register
Address

I0

RB RA 0

Register
Address

0

0P0A

Pot/WCR

Address

0

RA 0 P0

Pot/WCR

Address

I

S

A

T

C

O

K

P

WCR[7:0]

I

N
C

2

or

I

N
C

n

P0

Pot/WCR

Address

D7 D6 D5 D4 D3 D2 D1 D0
C
K

Data Register D[7:0]

A
C

N

K

C
1

S

A

T

C

O

K

P

D
E

C
1

S

D

T

E

O

C

P

n

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

SDA

R

W

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Voltage Out

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t

WRID

Characteristics subject to change without notice. 11 of 25

X9269

INSTRUCTION FORMAT

Read Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A
R

0 1 0 1 A3A2A1A0 1 0 0 1 0 0 0 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

Write Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A
R

0 1 0 1 A3A2A1A0 1 0 1 0 0 0 0 P0

T

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

Read Data Register (DR)

Device Type

S

Identifier

T
A
R

0 1 0 1 A3A2A1A0 1 0 1 1RBRA 0 P0

T

Device

Addresses

Instruction

S
A

C

K

Opcode

DR/WCR

Addresses

Wiper Position

S

(Sent by X9269 on SDA)

A

W

W

W

W

C

C

C

R

K

R

7

6

Wiper Position

S

(Sent by Master on SDA)

A

W

W

C

C

C

R

K

R

7

6

S

(Sent by X9269 on SDA)

A

W

W

C

C

C

R

K

R

7

W

C

C

C

R

R

R

5

4

3

W

W

W

C

C

C

R

R

R

5

4

3

Wiper Position

W

W

W

C

C

C

R

R

R

5

4

6

3

W

C
R

W

C
R

M

S

A

W

W

1

T

C

O

C

K

P

R
0

S

S

A

T

C

O

C

K

P

R
0

M

S

A

T

W

C

O

C

K

P

R

0

W

C
R

2

1

W

C
R

2

1

W

W

C

C

R

R

2

Write Data Register (DR)

Device Type

S

Identifier

T
A
R

01 0 1A3A2A1A0 1100RBRA0 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

S
A

C

K

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

S

Device Type

T

Identifier
A
R

0101A3A2A1A0 0001RBRA 0 0

T

REV 1.1.11 2/17/03

Device

Addresses

S

A
C
K

Instruction

Opcode

DR/WCR

Addresses

www.xicor.com

Wiper Position

(Sent by Master on SDA)

W

W

W

W

W

W

W

C

C

C

C

R

R

7

6

S
A
C
K

C

R

R

R

5

4

3

S
T
O
P

Characteristics subject to change without notice. 12 of 25

W

C

C

C

R

R

R

2

1

S

S

A

T

C

O

K

P

0

WRITE CYCLE

HIGH-VOLTAGE

X9269

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

S

Device Type

T

Identifier
A
R

0101A3A2A1A0 1000RBRA0 0

T

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S

A
C
K

S

HIGH-VOLTAGE

T

WRITE CYCLE

O

P

Device Type

S

Identifier

T

Device

Addresses
A
R

0101A3A2A1A0 1110RBRA 0 P0

T

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S

S

T

A

C

K

HIGH-VOLTAGE

O

WRITE CYCLE

P

Transfer Data Register (DR) to Wiper Counter Register (WCR)

S

Device Type

T

Identifier
A
R

0 1 0 1 A3 A2 A1 A0 1 1 0 1 RB RA 0 P0

T

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S

S

A

T

C

O

K

P

Increment/Decrement Wiper Counter Register (WCR)

S

Device Type

T

Identifier
A
R

0101A3A2A1A0 001000 0 P0 I/DI/D....I/DI/D

T

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S
A

Increment/Decrement

(Sent by Master on SDA)

C
K

S
T

O

P

REV 1.1.11 2/17/03

www.xicor.com

Characteristics subject to change without notice. 13 of 25

X9269

ABSOLUTE MAXIMUM RATINGS

Temperature under bias ....................–65°C to +135°C

Storage temperature .........................–65°C to +150°C

Voltage on SCL, SDA any address input

with respect to VSS..................................–1V to +7V

∆V = | (VH–VL) |.................................................... 5.5V

Lead temperature (soldering, 10 seconds).........300°C

IW (10 seconds) ................................................. ±6mA

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C +70°C

Industrial –40°C +85°C

Device Supply Voltage (VCC)

X9269 5V ±10%

X9269-2.7 2.7V to 5.5V

(4)

Limits

POTENTIOMETER CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.)

Limits

Symbol Parameter

R

TOTAL

R

TOTAL

End to End Resistance 100 kΩ T version

End to End Resistance 50 kΩ U version

End to End Resistance

±20 %

Test ConditionsMin. Typ. Max. Units

Tolerance

Power Rating 50 mW 25°C, each pot

I

W

R

W

R

W

V

TERM

Wiper Current ±3 mA

Wiper Resistance 300 Ω IW = ± 3mA @ VCC = 3V

Wiper Resistance 150 Ω IW = ± 3mA @ VCC = 5V

Voltage on any RH or RL Pin V

SS

V

CC

VV

SS

= 0V

Noise -120 dBV Ref: 1V

Resolution

Absolute Linearity

Relative Linearity

(1)

(2)

Temperature Coefficient of
R

TOTAL

0.4 %

±1 MI

±0.6 MI

(3)

(3)

±300 ppm/°C

R

w(n)(actual)

R

w(n + 1)

– [R

– R

w(n)(expected)

w(n) + MI

(5)

(5)

]

Ratiometric Temp. Coefficient 20 ppm/°C

C

H/CL/CW

I

al

Potentiometer Capacitances 10/10/25 pF See Macro model

RW, RH, RL Leakage 0.1 10.0 µA Device in stand by.

Vin = V

SS

to V

CC

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used

as a potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (RH – RL) / 255, single pot
(4) During power up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.

REV 1.1.11 2/17/03

www.xicor.com

Characteristics subject to change without notice. 14 of 25

X9269

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

VCC supply current
(active)

I

CC2

VCC supply current
(nonvolatile write)

I

I

I

V

V

V

V

V

SB

LI

LO

IH

IL

OL

OH

OH

VCC current (standby) 5 µAV

Input leakage current 10 µAVIN = VSS to V

Output leakage current 10 µAV

Input HIGH voltage VCC x 0.7 VCC + 1 V

Input LOW voltage –1 VCC x 0.3 V

Output LOW voltage 0.4 V IOL = 3mA

Output HIGH voltage VCC - 0.8 V IOH = -1mA, VCC ≥ +3V

Output HIGH voltage VCC - 0.4 V IOH = -0.4mA, VCC ≤ +3V

400 µA f

1 5 mA f

SCL

SDA = Open; (for 2-Wire, Active, Read
and

SCL

SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)

CC

V

CC

OUT

Test ConditionsMin. Typ. Max. Units

= 400KHz; VCC = +6V;

= 400KHz; VCC = +6V;

= +6V; VIN = VSS or VCC; SDA =

; (for 2-Wire, Standby State only)

CC

= VSS to V

CC

ENDURANCE AND DATA RETENTION

Parameter Min. Units

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

CAPACITANCE

Symbol Test Max. Units Test Conditions

IN/OUT

(6)

IN

(6)

Input / Output capacitance (SDA) 8 pF V

OUT

= 0V

Input capacitance (SCL, WP, A3, A2, A1 and A0) 6 pF VIN = 0V

C

C

POWER-UP TIMING

Symbol Parameter Min. Max. Units

(6)

tr V

t

PUR

CC

(7)

VCC Power-up rate 0.2 50 V/ms

Power-up to initiation of read operation 1 ms

POWER UP AND DOWN REQUIREMENTS

The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the poten­tiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The
VCC power-up timing spec is always in effect.

A.C. TEST CONDITIONS

Input Pulse Levels V

x 0.1 to VCC x 0.9

CC

Input rise and fall times 10ns

Input and output timing level V

Notes: (6) This parameter is not 100% tested

(7) t

and t

PUR

issued. These parameters are periodically sampled and not 100% tested.

are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be

PUW

CC

x 0.5

REV 1.1.11 2/17/03

www.xicor.com

Characteristics subject to change without notice. 15 of 25

X9269

EQUIVALENT A.C. LOAD CIRCUIT

SDA pin

5V

1533Ω

SDA pin

100pF

3V

867Ω

100pF

SPICE Macromodel

R

R

H

10pF

TOTAL

C

L

C

W

25pF

R

W

C

L

10pF

R

L

AC TIMING

Symbol Parameter Min. Max. Units

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock Frequency 400 kHz

Clock Cycle Time 2500 ns

Clock High Time 600 ns

Clock Low Time 1300 ns

Start Setup Time 600 ns

Start Hold Time 600 ns

Stop Setup Time 600 ns

SDA Data Input Setup Time 100 ns

SDA Data Input Hold Time 30 ns

SCL and SDA Rise Time 300 ns

SCL and SDA Fall Time 300 ns

SCL Low to SDA Data Output Valid Time 0.9 µs

SDA Data Output Hold Time 0 ns

Noise Suppression Time Constant at SCL and SDA inputs 50 ns

Bus Free Time (Prior to Any Transmission) 1200 ns

A0, A1, A2, A3 Setup Time 0 ns

A0, A1, A2, A3 Hold Time 0 ns

REV 1.1.11 2/17/03

www.xicor.com

Characteristics subject to change without notice. 16 of 25

X9269

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Units

t

WR

XDCP TIMING

Symbol Parameter Min. Max. Units

t

WRPO

t

WRL

SYMBOL TABLE

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 5 10 µs

Wiper response time after instruction issued (all load instructions) 5 10 µs

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

.

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

REV 1.1.11 2/17/03

www.xicor.com

Characteristics subject to change without notice. 17 of 25

X9269

TIMING DIAGRAMS

Start and Stop Timing

SCL

t

SU:STA

SDA

Input Timing

(START) (STOP)

t

F

t

SU:STO

t

F

t

HD:STA

t

R

t

R

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

DH

t

BUF

REV 1.1.11 2/17/03

www.xicor.com

Characteristics subject to change without notice. 18 of 25

X9269

XDCP Timing (for All Load Instructions)

SCL

(STOP)

SDA

VWx

Write Protect and Device Address Pins Timing

(START) (STOP)

SCL

SDA

t

SU:WPA

WP

A0, A1

LSB

t

WRL

...

(Any Instruction)

...

...

t

HD:WPA

REV 1.1.11 2/17/03

www.xicor.com

Characteristics subject to change without notice. 19 of 25

X9269

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

V

R

RW

+V

R

I

Three terminal Potentiometer;

Application Circuits

Noninverting Amplifier Voltage Regulator

V

S

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysterisis

Variable voltage divider

+

–

R

2

R

1

S

Two terminal Variable Resistor;

Variable current

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

317

R

1

I

adj

R

2

adj R2

VO (REG)V

REV 1.1.11 2/17/03

V

S

10KΩ

R

1

100KΩ

-12V+12V

R

2

V

S

–

V

+

O

–

V

+

TL072

10KΩ

10KΩ10KΩ

10KΩ

O

V

CC

www.xicor.com

}

}

R

R

2

1

VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)

Characteristics subject to change without notice. 20 of 25

X9269

Application Circuits (continued)

Attenuator Filter

R

1

V

S

R

3

R

4

VO = G V

-1/2 ≤ G ≤ +1/2

Inverting Amplifier Equivalent L-R Circuit

R

R

V

S

1

}

VO = G V
G = - R2/R

2

}

R

–

+

R1 = R2 = R3 = R4 = 10kΩ

S

–

+

S

1

C

V

S

2

V

O

V

V

O

S

Z

IN

R

C

1

G

O

fc = 1/(2πRC)

R

= 1 + R2/R

R

1

R

3

+

–

R

1

1

R

2

+

–

V

O

2

REV 1.1.11 2/17/03

Function Generator

–

+

frequency ∝ R1, R2, C
amplitude ∝ RA, R

B

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R

R

2

R

}

A

R

}

B

www.xicor.com

R

1

–

+

Characteristics subject to change without notice. 21 of 25

2

C

X9269

PACKAGING INFORMATION

16-Bump Chip Scale Package (CSP B16)
Package Outline Drawing

9269TRR

YWW I

LOT #

Top View (Marking Side)

a

A4

f

j

m

Bottom View (Bumped Side)

e

A3 A2 A1

B4

B3 B2 B1

C4

C3 C2 C1

D4

D3 D2 D1

l

Side View

b

k

Side View

c

d

e

Package Dimensions

Millimeters Inches

Symbol

Package Width a 2.745 2.775 2.805

Package Length b 4.523 4.553 4.583

Package Height c 0.644 0.677 0.710

Body Thickness d 0.444 0.457 0.470

Ball Height e 0.200 0.220 0.240

Ball Diameter f 0.300 0.320 0.340

Ball Pitch – Width j 0.65

Ball Pitch – Length k 0.65

Ball to Edge Spacing – Width l 0.388 0.413 0.438

Ball to Edge Spacing – Length m 1.277 1.302 1.327

REV 1.1.11 2/17/03

Min Nominal Max Min Nominal Max

www.xicor.com

Ball Matrix:

4321

R

A

B

R

C

D Vss SCL A0 Vcc

Characteristics subject to change without notice. 22 of 25

H1

R

L1

W1

A1 A2

SDA WP

A3 NC

R

H0

R

W0

R

L0

X9269

PACKAGING INFORMATION

.026 (.65) BSC

24-Lead Plastic, TSSOP, Package Code V24

0°–8°

.0075 (.19)

.0118 (.30)

.303 (7.70)
.311 (7.90)

.020 (.50)
.030 (.75)

Detail A (20X)

.169 (4.3)
.177 (4.5)

.041 (1.05)

0.002 (0.05)

0.005 (0.15)

.010 (.25)

Gage Plane

Seating Plane

.252 (6.4) BSC

(1.78)

(0.42)

(0.65)

(4.16)

(7.72)

See Detail “A”

REV 1.1.11 2/17/03

.031 (.80)

.041 (1.05)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

www.xicor.com

ALL MEASUREMENTS ARE TYPICAL

Characteristics subject to change without notice. 23 of 25

X9269

PACKAGING INFORMATION

24-Lead Plastic Small Outline Gull Wing Package Type S

0° – 8°

Pin 1 Index

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

0.015 (0.40)

0.050 (1.27)

Pin 1

X 45°

0.014 (0.35)

0.020 (0.50)

0.598 (15.20)

0.610 (15.49)

0.009 (0.22)

0.013 (0.33)

0.420"

0.290 (7.37)

0.299 (7.60)

0.003 (0.10)

0.012 (0.30)

0.050" Typical

0.393 (10.00)

0.420 (10.65)

0.092 (2.35)

0.105 (2.65)

0.050"

Typical

REV 1.1.11 2/17/03

0.030" Typical

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

www.xicor.com

Characteristics subject to change without notice. 24 of 25

24 Places

X9269

ORDERING INFORMATION

X9269 P T VY

Device

VCC Limits

Blank = 5V ±10%
–2.7 = 2.7 to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C

Package

S24 = 24-Lead SOIC
B16 = 16-Lead CSP
V24 = 24-Lead TSSOP

Potentiometer Organization

Pot
U = 50KΩ
T = 100KΩ

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

COPYRIGHTS AND TRADEMARKS

2

Xicor, Inc., the Xicor logo, E

2

KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are

E
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

REV 1.1.11 2/17/03

POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,

www.xicor.com

Characteristics subject to change without notice. 25 of 25

©Xicor, Inc. 2003 Patents Pending