Xicor X9119 Technical data

查询X9119TB15供应商

A

PPLICATION

AN99 • AN115 • AN124 •AN133 • AN134 • AN135

N

OTES

AND

D

EVELOPMENT

A V A I L A B L E

S

YSTEM

Single Supply / Low Power / 1024-tap / 2-Wire bus

Preliminary Information

X9119

Single Digitally-Controlled (XDCP

FEATURES

• 1024 Resistor Taps – 10-Bit Resolution

• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer

• Wiper Resistance, 40 ΩΩ

• Four Non-Volatile Data Registers

• Non-Volatile Storage of Multiple Wiper Positions

• Power On Recall. Loads Saved Wiper Position on
Power Up.

• Standby Current < 3µA Max

•V

: 2.7V to 5.5V Operation

CC

• 100K ΩΩ

ΩΩ

End to End Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes Per Bit Per
Register

• 14-Lead TSSOP, 15-Lead XBGA

• Low Power CMOS

• Single Supply version of the X9118

ΩΩ

Typical @ V

CC

= 5V

™

) Potentiometer

DESCRIPTION

The X9119 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. The potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and a
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Address

2-Wire

Bus

Interface

REV 1.1.11 3/12/02

Status

Data

V

CC

Bus

Interface &

Control

V

SS

Write
Read

Transfer

Control

NC NC

Power On Recall

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Wiper Counter

Register (WCR)

Data Registers

(DR0-DR3)

R

H

100KΩ
1024-taps

POT

Wiper

R

Characteristics subject to change without notice.

R

W

L

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X9119

– Preliminary Information

DETAILED FUNCTIONAL DIAGRAM

V

CC

SCL

SDA

A2

A1

A0

WP

Interface

and

Control

Circuitry

Data

Control

Power On

Recall

DR0 DR1

DR2 DR3

Wiper

Counter

Register

(WCR)

100KΩ
1024-taps

R

H

R

L

R

W

V

SS

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF
wireless systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

REV 1.1.11 3/12/02

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Characteristics subject to change without notice.

2 of 22

X9119

– Preliminary Information

PIN CONFIGURATION

TSSOP

NC

A0

NC

A2

SCL

SDA

V

SS

1
2
3
4
5
6
7

X9119

14
13
12
11
10

V

CC

R

L

R

H

R

W

NC
A1

9
8

WP

PIN ASSIGNMENTS

Pin

(TSSOP)

Pin

(XBGA) Symbol Function

1 D1, A3 NC No Connect

2 B3 A0 Device Address for 2-wire bus

3 B2 NC No Connect

4 C3 A2 Device Address for 2-wire bus

5 D3 SCL Serial Clock for 2-wire bus

6 E3 SDA Serial Data Input/Output for 2-wire bus

7E2 V

SS

8D2 WP

9 E1 A1 Device Address for 2-wire bus

10 C2 NC No Connect

11 C1 R

12 B1 R

13 A1 R

14 A2 V

W

H

L

CC

XBGA

X9119

NC

SDA

CC

SS

RLV

RHNCA0

RWNCA2

NCWPNSCL

A1V

System Ground

Hardware Write Protect

Wiper terminal of the Potentiometer

High terminal of the Potentiometer

Low terminal of the Potentiometer

System Supply Voltage

A1A2A3

B1B2B3

C1C2C3

D1D2D3

E1E2E3

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Characteristics subject to change without notice.

3 of 22

X9119 – Preliminary Information

)

)

PIN DESCRIPTIONS

Bus Interface Pins

S

ERIAL

D

ATA

I

NPUT

/O

UTPUT

(SDA)

The SDA is a bidirectional serial data input/output pin
for a 2-wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.

It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.

S

ERIAL

C

LOCK

(SCL)

This input is used by 2-wire master to supply 2-wire
serial clock to the X9119.

D

EVICE

A

DDRESS

(A

–A

2

0

The Address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9119. A maximum of 8 devices may occupy the 2­wire serial bus.

Hardware Write Protect Input (WP)

The WP pin when LOW prevents nonvolatile writes to
the Data Registers.

Potentiometer Pins

R

, R

H

L

The R

and R

H

pins are equivalent to the terminal

L

connections on a mechanical potentiometer.

R

W

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.

Bias Supply Pins

S

YSTEM

S

UPPLY

V

OLTAGE

(V

)

AND

S

UPPLY

G

ROUND

(V

SS

SS

pin

The V

CC

pin is the system supply voltage. The V

CC

is the system ground.

Other Pins

N

O

C

ONNECT

No connect pins should be left open. These pins are
used for Xicor manufacturing and testing purposes.

PRINCIPLES OF OPERATION

The X9119 is an integrated microcircuit incorporating a
resistor array and its associated registers and counters
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometer. This section provides detail
description of the following:

– Resistor Array Description

– Serial Interface Description

– Instruction and Register Description

Resistor Array Description

The X9119 is comprised of a resistor array. The array
contains, in effect, 1023 discrete resistive segments
that are connected in series (see Figure 1). The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R

and R

H

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R

) output. Within each individual array only one

W

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.

The WCR may be written directly. The Data Registers
and the WCR can be read and written by the host
system.

L

REV 1.1.11 3/12/02

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Characteristics subject to change without notice.

4 of 22

X9119 – Preliminary Information

Figure 1. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

If WCR = 000[HEX] then RW = R
If WCR = 3FF[HEX] then RW = R

Register 0

(DR0)

10 10

Register 2

(DR2)

L

H

Register 1

(DR1)

Register 3

(DR3)

Serial Interface Description

S

ERIAL

I

NTERFACE

The X9119 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9119 will be considered a
slave device in all applications.

C

LOCK

AND

D

ATA

C

ONVENTIONS

Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.

S

TART

C

ONDITION

All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9119 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
See Figure 3.

Serial
Bus
Input

Parallel
Bus
Input

Wiper

Counter

Register

(WCR)

S

TOP

C

ONDITION

C
O
U
N
T
E
R

D
E
C
O
D
E

R

H

R

L

R

W

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.

A

CKNOWLEDGE

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9119 will respond with a final acknowledge.
See Figure 2.

REV 1.1.11 3/12/02

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Characteristics subject to change without notice.

5 of 22

X9119 – Preliminary Information

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Issue STOP

No

Yes

Yes

Proceed

Issue STOP

No

Proceed

Figure 2. Acknowledge Response from Receiver

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

START ACKNOWLEDGE

ACKNOWLEDGE POLLING

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9119
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9119 is still busy with the write operation no ACK
will be returned. If the X9119 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

1

89

FLOW 1. ACK Polling Sequence

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Characteristics subject to change without notice.

6 of 22

X9119 – Preliminary Information

Instruction and Register Description

matches the incoming device address sent by the
master executes the instruction. The A2–A0 inputs can

EVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)

D

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier. The ID[3:0] bits is the device id for the
X9119; this is fixed as 0101[B] (refer to Table 1).

The A2–A0 bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A2–A0 input pins. The slave address is
externally specified by the user. The X9119 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9119 to successfully continue the command

be actively driven by CMOS input signals or tied to V
or VSS. The R/W bit is the LSB and is be used to
program the device for read or write operations.

INSTRUCTION BYTE AND REGISTER SELECTION

The next byte sent to the X9119 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (IOP[2:0]). The RB and RA bits point to one of
the four registers. The format is shown below in
Table 2.

Table 3 provides a complete summary of the
instruction set opcodes.

sequence. Only the device which slave address

Table 1. Identification Byte Format

Device Type

Identifies

Internal Slave

Address

ID3 ID2 ID1 ID0 A2 A1 A0 R/W

0101

(MSB) (LSB)

CC

Read or
Write Bit

Table 2. Instruction Byte Format

Instruction

Opcode

Register

Selection

I2 I1 I0 0 RB RA 0 0

(MSB) (LSB)

Register Selected RB RA

DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

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Characteristics subject to change without notice. 7 of 22