Xicor X9119 Technical data

查询X9119TB15供应商

A

PPLICATION

AN99 • AN115 • AN124 •AN133 • AN134 • AN135

N

OTES

AND

D

EVELOPMENT

A V A I L A B L E

S

YSTEM

Single Supply / Low Power / 1024-tap / 2-Wire bus

Preliminary Information

X9119

Single Digitally-Controlled (XDCP

FEATURES

• 1024 Resistor Taps – 10-Bit Resolution

• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer

• Wiper Resistance, 40 ΩΩ

• Four Non-Volatile Data Registers

• Non-Volatile Storage of Multiple Wiper Positions

• Power On Recall. Loads Saved Wiper Position on
Power Up.

• Standby Current < 3µA Max

•V

: 2.7V to 5.5V Operation

CC

• 100K ΩΩ

ΩΩ

End to End Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes Per Bit Per
Register

• 14-Lead TSSOP, 15-Lead XBGA

• Low Power CMOS

• Single Supply version of the X9118

ΩΩ

Typical @ V

CC

= 5V

™

) Potentiometer

DESCRIPTION

The X9119 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. The potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and a
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Address

2-Wire

Bus

Interface

REV 1.1.11 3/12/02

Status

Data

V

CC

Bus

Interface &

Control

V

SS

Write
Read

Transfer

Control

NC NC

Power On Recall

www.xicor.com

Wiper Counter

Register (WCR)

Data Registers

(DR0-DR3)

R

H

100KΩ
1024-taps

POT

Wiper

R

Characteristics subject to change without notice.

R

W

L

1 of 22

X9119

– Preliminary Information

DETAILED FUNCTIONAL DIAGRAM

V

CC

SCL

SDA

A2

A1

A0

WP

Interface

and

Control

Circuitry

Data

Control

Power On

Recall

DR0 DR1

DR2 DR3

Wiper

Counter

Register

(WCR)

100KΩ
1024-taps

R

H

R

L

R

W

V

SS

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF
wireless systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

REV 1.1.11 3/12/02

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Characteristics subject to change without notice.

2 of 22

X9119

– Preliminary Information

PIN CONFIGURATION

TSSOP

NC

A0

NC

A2

SCL

SDA

V

SS

1
2
3
4
5
6
7

X9119

14
13
12
11
10

V

CC

R

L

R

H

R

W

NC
A1

9
8

WP

PIN ASSIGNMENTS

Pin

(TSSOP)

Pin

(XBGA) Symbol Function

1 D1, A3 NC No Connect

2 B3 A0 Device Address for 2-wire bus

3 B2 NC No Connect

4 C3 A2 Device Address for 2-wire bus

5 D3 SCL Serial Clock for 2-wire bus

6 E3 SDA Serial Data Input/Output for 2-wire bus

7E2 V

SS

8D2 WP

9 E1 A1 Device Address for 2-wire bus

10 C2 NC No Connect

11 C1 R

12 B1 R

13 A1 R

14 A2 V

W

H

L

CC

XBGA

X9119

NC

SDA

CC

SS

RLV

RHNCA0

RWNCA2

NCWPNSCL

A1V

System Ground

Hardware Write Protect

Wiper terminal of the Potentiometer

High terminal of the Potentiometer

Low terminal of the Potentiometer

System Supply Voltage

A1A2A3

B1B2B3

C1C2C3

D1D2D3

E1E2E3

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Characteristics subject to change without notice.

3 of 22

X9119 – Preliminary Information

)

)

PIN DESCRIPTIONS

Bus Interface Pins

S

ERIAL

D

ATA

I

NPUT

/O

UTPUT

(SDA)

The SDA is a bidirectional serial data input/output pin
for a 2-wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.

It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.

S

ERIAL

C

LOCK

(SCL)

This input is used by 2-wire master to supply 2-wire
serial clock to the X9119.

D

EVICE

A

DDRESS

(A

–A

2

0

The Address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9119. A maximum of 8 devices may occupy the 2­wire serial bus.

Hardware Write Protect Input (WP)

The WP pin when LOW prevents nonvolatile writes to
the Data Registers.

Potentiometer Pins

R

, R

H

L

The R

and R

H

pins are equivalent to the terminal

L

connections on a mechanical potentiometer.

R

W

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.

Bias Supply Pins

S

YSTEM

S

UPPLY

V

OLTAGE

(V

)

AND

S

UPPLY

G

ROUND

(V

SS

SS

pin

The V

CC

pin is the system supply voltage. The V

CC

is the system ground.

Other Pins

N

O

C

ONNECT

No connect pins should be left open. These pins are
used for Xicor manufacturing and testing purposes.

PRINCIPLES OF OPERATION

The X9119 is an integrated microcircuit incorporating a
resistor array and its associated registers and counters
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometer. This section provides detail
description of the following:

– Resistor Array Description

– Serial Interface Description

– Instruction and Register Description

Resistor Array Description

The X9119 is comprised of a resistor array. The array
contains, in effect, 1023 discrete resistive segments
that are connected in series (see Figure 1). The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R

and R

H

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R

) output. Within each individual array only one

W

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.

The WCR may be written directly. The Data Registers
and the WCR can be read and written by the host
system.

L

REV 1.1.11 3/12/02

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Characteristics subject to change without notice.

4 of 22

X9119 – Preliminary Information

Figure 1. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

If WCR = 000[HEX] then RW = R
If WCR = 3FF[HEX] then RW = R

Register 0

(DR0)

10 10

Register 2

(DR2)

L

H

Register 1

(DR1)

Register 3

(DR3)

Serial Interface Description

S

ERIAL

I

NTERFACE

The X9119 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9119 will be considered a
slave device in all applications.

C

LOCK

AND

D

ATA

C

ONVENTIONS

Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.

S

TART

C

ONDITION

All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9119 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
See Figure 3.

Serial
Bus
Input

Parallel
Bus
Input

Wiper

Counter

Register

(WCR)

S

TOP

C

ONDITION

C
O
U
N
T
E
R

D
E
C
O
D
E

R

H

R

L

R

W

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.

A

CKNOWLEDGE

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9119 will respond with a final acknowledge.
See Figure 2.

REV 1.1.11 3/12/02

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Characteristics subject to change without notice.

5 of 22

X9119 – Preliminary Information

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Issue STOP

No

Yes

Yes

Proceed

Issue STOP

No

Proceed

Figure 2. Acknowledge Response from Receiver

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

START ACKNOWLEDGE

ACKNOWLEDGE POLLING

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9119
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9119 is still busy with the write operation no ACK
will be returned. If the X9119 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

1

89

FLOW 1. ACK Polling Sequence

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Characteristics subject to change without notice.

6 of 22

X9119 – Preliminary Information

Instruction and Register Description

matches the incoming device address sent by the
master executes the instruction. The A2–A0 inputs can

EVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)

D

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier. The ID[3:0] bits is the device id for the
X9119; this is fixed as 0101[B] (refer to Table 1).

The A2–A0 bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A2–A0 input pins. The slave address is
externally specified by the user. The X9119 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9119 to successfully continue the command

be actively driven by CMOS input signals or tied to V
or VSS. The R/W bit is the LSB and is be used to
program the device for read or write operations.

INSTRUCTION BYTE AND REGISTER SELECTION

The next byte sent to the X9119 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (IOP[2:0]). The RB and RA bits point to one of
the four registers. The format is shown below in
Table 2.

Table 3 provides a complete summary of the
instruction set opcodes.

sequence. Only the device which slave address

Table 1. Identification Byte Format

Device Type

Identifies

Internal Slave

Address

ID3 ID2 ID1 ID0 A2 A1 A0 R/W

0101

(MSB) (LSB)

CC

Read or
Write Bit

Table 2. Instruction Byte Format

Instruction

Opcode

Register

Selection

I2 I1 I0 0 RB RA 0 0

(MSB) (LSB)

Register Selected RB RA

DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

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Characteristics subject to change without notice. 7 of 22

X9119 – Preliminary Information

Table 3. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter
Register

Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register

Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register

XFR Data Register to
Wiper Counter Register

XFR Wiper Counter
Register to Data Regis­ter

Note: (1) 1/o = data is one or zero.

2I1I0

1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter

0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter

1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register

0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter

0RBRA 0 0

Register

Register

pointed to RB-RA.

pointed to RB-RA.

pointed to by RB-RA.to the Wiper Counter
Register

Register to the Data Register pointed to by
RB-RA.

OperationR/W I

Instruction and Register Description

DEVICE ADDRESSING

WIPER COUNTER REGISTER (WCR)

The X9119 contains a Wiper Counter Registers (see
Table 4) for the XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 1024
switches along its resistor array. The contents of the
WCR can be altered in one of three ways: (1) it may be
written directly by the host via the write wiper counter
register instruction (serial load); (2) it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR data register; (3)
it is loaded with the contents of its data register zero
(R0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9119 is powered­down. Although the register is automatically loaded

with the value in DR0 upon power-up, this may be
different from the value present at power-down. Power­up guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR.

DATA REGISTERS (DR0 TO DR3)

The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the Wiper Counter Register.
All operations changing data in one of the data
registers is a nonvolatile operation and will take a
maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bit 9–Bit 0 are used to store one of the 1024 wiper
position (0 ~1023).

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Characteristics subject to change without notice. 8 of 22

X9119 – Preliminary Information

Table 4. Wiper Control Register, WCR (10-bit), WCR9–WCR0: Used to store the current wiper position (Volatile, V)

WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVVVV

(MSB) (LSB)

Table 5. Data Register, DR (10-bit), Bit 9–Bit 0: Used to store wiper positions or data (Non-Volatile, NV)

Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NV NV NV NV NV NV NV NV NV NV

MSB LSB

Four of the six instructions are four bytes in length.
These instructions are:

– Read Wiper Counter Register – read the current

wiper position of the selected potentiometer,

– Write Wiper Counter Register – change current

wiper position of the selected potentiometer,

– Read Data Register – read the contents of the

selected Data Register;

– Write Data Register – write a new value to the

selected Data Register.

The basic sequence of the four byte instructions is
illustrated in Figure 3. These four-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t

. A transfer

WRL

from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers.

Two instructions (see Figure 4) require a two-byte
sequence to complete. These instructions transfer data
between the host and the X9119; either between the
host and one of the data registers or directly between
the host and the Wiper Counter Register. These
instructions are:

– XFR Data Register to Wiper Counter Register –

This transfers the contents of one specified Data
Register to the Wiper Counter Register.

– XFR Wiper Counter Register to Data Register –

This transfers the contents of the Wiper Counter
Register to the specified Data Register.

See Instruction format for more details.

POWER UP AND DOWN REQUIREMENTS

There are no restrictions on the power-up condition of
Vcc and the voltages applied to the potentiometer pins
provided that the Vcc is always more positive than or
equal to the voltages at RH, RL, and RW, i.e. VCC ≥ RH,
RL, RW. There are no restrictions on the power-down
condition. However, the datasheet parameters for the
DCP do not apply until 1milisecond after V

reaches

CC

its final value.

Figure 3. Two-Byte Instruction Sequence

SCL

SDA

REV 1.1.11 3/12/02

01 0 1

S

ID3 ID2 ID1 ID0

T
A

Device ID

R
T

A2 A1 A0 R/W

Internal

Address

I2I1I0

A
C
K

Instruction

Opcode

www.xicor.com

0

0 RBRA0 A

Register

00

Address

Characteristics subject to change without notice. 9 of 22

S
T

C

O

K

P

X9119 – Preliminary Information

Figure 4. Four-Byte Instruction Sequence (Write or Read for WCR or Data Registers)

SCL

A0

R/W

0

I2

A
C
K

Instruction

I1

Opcode

SDA

0101

ID3 ID2 ID1 ID0A2A1

S
T
A

Device ID

R
T

Internal
Address

INSTRUCTION FORMAT

Read Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A

R

0101A2A1A0

T

Device

Addresses

Instruction

Opcode

S
A
C

10000000 XXXXXX

K

R / W = 1

Write Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A

R

0101A2A1A0

T

Device

Addresses

Instruction

Opcode

S
A
C

10100000 XXXXXX

K

R / W = 0

0XX0

0

I0

RB RA

Register
Address

Register

Addresses

Register

Addresses

0

A

0

C
K

XX

XX X

Wiper Position

(Sent by Slave on SDA)

S
A
C
K

Wiper Position

(Sent by Master on SDA)

S
A
C
K

X

A

W

W

W

W

W

W

W

C

C

C

C

C

R

R

K

8

9

C

R

R

R

7

6

5

Wiper or Data

Position

W

C

C

C

R

R

R

4

3

2

A

W
C

R
1

S

W
C

C

T

K

O

R
0

P

Wiper Position

(Sent by Slave on SDA)

M
A

W

W
C
R

9

W

W

W

W

W

C

C

C

C

K

R
8

C

R

R

R

7

6

5

W

C

C

C

R

R

R

4

3

2

M

S

A

W

C
R
1

T

W

C

O

C

K

P

R
0

Wiper Position

(Sent by Master on SDA)

S
A

W

W

W

W

W

W

W

C

C

C

C

C

K

R

R

9

8

C

R

R

R

7

6

5

W

C

C

C

R

R

R

4

3

2

S

S

A

W

C
R
1

T

W

C

O

C

K

P

R

0

Read Data Register (DR)

Device Type

S

Identifier

T
A

R

0101A2A1A0

T

REV 1.1.11 3/12/02

Device

Addresses

Instruction

Opcode

S
A
C

1010RBRA00 XXXXXX

K

Register

Addresses

Wiper Position

(Sent by Slave on SDA)

S
A
C
K

R / W = 1

www.xicor.com

wiper position or data

(Sent by Slave on SDA)

M
A

W

W

W

W

W

W

W

C

C

C

C

C

K

R

R

9

8

Characteristics subject to change without notice. 10 of 22

C

R

R

R

7

6

5

W

C

C

C

R

R

R

4

3

2

M

S

A

W

C
R

1

T

W

C

O

C

K

P

R
0

X9119 – Preliminary Information

Write Data Register (DR)

Device Type

Identifier

S
T
A

R

0101A2A1A0

T

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Device Type

S

Identifier

T
A

R

0101A2A1A0

T

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A

R

0101A2A1A0

T

Device

Addresses

Device

Addresses

Device

Addresses

Instruction

Opcode
S
A
C

1100RBRA00 XXXXXX

K

R / W = 0

Instruction

Opcode

S
A
C

1110RBRA00

K

R / W = 0

Instruction

Opcode

S
A
C

1100RBRA00

K

R / W = 1

Register

Addresses

Register

Addresses

Register

Addresses

Wiper Position or Data

(Sent by Master on SDA)
S
A
C
K

S

S

A

T

C

O

K

P

S

S

A

T

C

O

K

P

W

W

C

C

R

R

9

8

HIGH-VOLTAGE

WRITE CYCLE

Wiper Position or Data

(Sent by Master on SDA)
S
A

W

W

W

W

C

C

C

K

R

R

7

6

W

C

C

C

R

R

R

5

4

3

S

S

A

W

W

C

C

R

R

2

1

T

W

C

O

C

K

P

R

0

WRITE CYCLE

HIGH-VOLTAGE

Notes: (1) “A2 ~ A0”: stand for the device addresses sent by the master.

(2) WCRx refers to wiper position data in the Wiper Counter Register

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Characteristics subject to change without notice. 11 of 22

X9119 – Preliminary Information

ABSOLUTE MAXIMUM RATINGS

Temperature under bias.................... –65°C to +135°C

Storage temperature......................... –65°C to +150°C

Voltage on SCL, SDA, or any address input

with respect to V

................................. –1V to +7V

SS

∆V = | (VH–VL) | ......................................................5V

Lead temperature (soldering, 10 seconds) ........ 300°C

IW (10 seconds) ..................................................±6mA

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C +70°C

Industrial –40°C +85°C

Device Supply Voltage (VCC) Limits

X9119 5V ±10%

X9119-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operation conditions unless otherwise stated.)

Limits

Symbol Parameter

R

TOTAL

End to End Resistance 100 kΩ

Test ConditionsMin. Typ. Max. Units

End to End Resistance Tolerance ±20 %

Power Rating 50 mW 25°C, each pot

Wiper Current ±3 mA

Wiper Resistance 150 500 Ω Wiper Current = ± 3mA, VCC = 3V

Wiper Resistance 40 100 Ω IW = ± 3mA, VCC = 5V

Voltage on any RH or RL Pin V

SS

5VV

SS

= 0V

R

R

V

TERM

I

W

W

W

Noise -120 dBV Ref: 1V

Resolution 0.1 %

Absolute Linearity

(1)

±1 MI

(3)

R

w(n)(actual)

– R

w(n)(expected)

,

where n=8 to 1006

Relative Linearity

(2)

±1.5 MI

±0.5 MI

(3)

(3)

R

w(n)(actual)

R

w(m + 1)

– R

– [R

w(n)(expected)

+ MI], where

w(m)

(5)

m=8 to 1006

Temperature Coefficient of R

TOTAL

±1 MI

(3)

±300 ppm/°C

R

w(m + 1)

– [R

w(m)

+ MI]

(5)

Ratiometric Temp. Coefficient 20 ppm/°C

C

H/CL/CW

Potentiometer Capacitancies 10/10/25 pF See Macro model

(4)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used

as a potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 1023 or (RH – RL) / 1023, single pot
(4) n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
(5) ESD Rating on RH, RL, RW pins is 1.5KV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.

REV 1.1.11 3/12/02

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Characteristics subject to change without notice. 12 of 22

X9119 – Preliminary Information

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

VCC supply current
(active)

I

CC2

VCC supply current
(nonvolatile write)

I

SB

I

LI

I

LO

VCC current (standby) 3 µAV

Input leakage current 10 µAVIN = VSS to V

Output leakage
current

V

V

V

OL

V

OH

Input HIGH voltage VCC x 0.7 VCC + 1 V

IH

Input LOW voltage –1 VCC x 0.3 V

IL

Output LOW voltage 0.4 V IOL = 3mA

Output HIGH voltage

3mAf

= 400KHz; VCC = +5.5V;

SCL

SDA = Open; (for 2-wire, Active, Read and
Volatile Write States only)

5mAf

= 400KHz; VCC = +5.5V;

SCL

SDA = Open; (for 2-wire, Active,
Non-volatile Write State only)

= +5.5V; VIN = VSS or VCC; SDA =

CC

;

V

CC

(for 2-wire, Standby State only)

10 µAV

OUT

= VSS to V

Test ConditionsMin. Typ. Max. Units

CC

CC

ENDURANCE AND DATA RETENTION

Parameter Min. Units

Minimum Endurance 100,000 Data changes per bit per register

Data Retention 100 years

CAPACITANCE

Symbol Test Max. Units Test Conditions

IN/OUT

(6)

C

IN

(6)

Input/Output capacitance (SI) 8 pF V

Input capacitance (SCL, WP, A1 and A0) 6 pF VIN = 0V

OUT

C

POWER-UP TIMING

Symbol Parameter Min. Max. Units

(6)

tr V

CC

(7)

t

PUR

(7)

t

PUW

Notes: (6) This parameter is not 100% tested.

(7) t

issued. These parameters are not 100% tested.
(8) This is not a tested or guaranteed parameter and should be used only as a guideline.

VCC Power-up Rate 0.2 50 V/ms

Power-up to Initiation of read operation 1 ms

Power-up to Initiation of write operation 50 ms

PUR

and t

are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be

PUW

= 0V

REV 1.1.11 3/12/02

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Characteristics subject to change without notice. 13 of 22

X9119 – Preliminary Information

A.C. TEST CONDITIONS

nput pulse levels VCC x 0.1 to VCC x 0.9

I

Input rise and fall times 10ns

Input and output timing level V

EQUIVALENT A.C. LOAD CIRCUIT

5V

CC

x 0.5

3V

SPICE Macromodel

SDA OUTPUT

1533Ω

SDA OUTPUT

100pF

867Ω

100pF

R

C

L

10pF

TOTAL

R

W

C

W

25pF

C

L

10pF

R

H

AC TIMINGHIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Min. Max. Units

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock Frequency 400 kHz

Clock Cycle Time 2500 ns

Clock High Time 600 ns

Clock Low Time 1300 ns

Start Setup Time 600 ns

Start Hold Time 600 ns

Stop Setup Time 600 ns

SDA Data Input Setup Time 100 ns

SDA Data Input Hold Time 0 ns

SCL and SDA Rise Time 300 ns

SCL and SDA Fall Time 300 ns

SCL Low to SDA Data Output Valid Time 250 ns

SDA Data Output Hold Time 0 ns

Noise Suppression Time Constant at SCL and SDA inputs 50 ns

Bus Free Time (Prior to Any Transmission) 1300 ns

A0, A1, A2 Setup Time 0 ns

A0, A1, A2 Hold Time 0 ns

R

L

REV 1.1.11 3/12/02

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Characteristics subject to change without notice. 14 of 22

X9119 – Preliminary Information

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Units

t

WR

XDCP TIMING

Symbol Parameter Min. Max. Units

t

WRPO

t

WRL

SYMBOL TABLE

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 5 10 µs

Wiper response time after instruction issued (all load

510µs

instructions)

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

REV 1.1.11 3/12/02

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Characteristics subject to change without notice. 15 of 22

X9119 – Preliminary Information

TIMING DIAGRAMS

Start and Stop Timing

(START) (STOP)

SCL

SDA

Input Timing

t

SU:STA

t

HD:STA

t

R

t

R

t

F

t

SU:STO

t

F

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

DH

t

BUF

REV 1.1.11 3/12/02

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Characteristics subject to change without notice. 16 of 22

X9119 – Preliminary Information

XDCP Timing (for All Load Instructions)

SCL

(STOP)

SDA

R

W

Write Protect and Device Address Pins Timing

(START) (STOP)

SCL

SDA

t

SU:WPA

WP

A0, A1, A2

LSB

t

...

(Any Instruction)

...

...

WRL

t

HD:WPA

.

REV 1.1.11 3/12/02

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Characteristics subject to change without notice. 17 of 22

X9119 – Preliminary Information

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

V

R

RW

Three terminal Potentiometer;
Variable voltage divider

Application Circuits

+V

R

I

Two terminal Variable Resistor;
Variable current

Noninverting Amplifier Voltage Regulator

V

S

VO = (1+R2/R1)V

+

–

R

R

1

S

V

O

2

IN

VO (REG) = 1.25V (1+R2/R1)+I

317

R

I

adj

R

2

Offset Voltage Adjustment Comparator with Hysterisis

–

+

R

2

TL072

V

S

V

O

R

VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)

–

+

}

}

R

2

1

V

S

10KΩ

R

1

100KΩ

10KΩ10KΩ

1

adj R2

VO (REG)V

V

O

REV 1.1.11 3/12/02

-12V+12V

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Characteristics subject to change without notice. 18 of 22

X9119 – Preliminary Information

Application Circuits (Continued)

Attenuator Filter

R

1

V

S

R

3

R

4

VO = G V

-1/2 ≤ G ≤ +1/2

Inverting Amplifier Equivalent L-R Circuit

R

R

V

S

1

}

VO = G V
G = - R2/R

2

}

R

2

–

+

R1 = R2 = R3 = R4 = 10kΩ

S

–

+

S

1

V

O

V

O

C

V

S

R

G

O

fc = 1/(2πRC)

C

1

V

S

Z

IN

+

–

R

1

= 1 + R2/R

R

R

1

R

3

V

O

R

2

1

2

+

–

REV 1.1.11 3/12/02

Function Generator

–

+

frequency ∝ R1, R2, C
amplitude ∝ RA, R

B

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R

R

2

R

}

A

R

}

B

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R

1

–

+

Characteristics subject to change without notice. 19 of 22

2

C

X9119 – Preliminary Information

15-ball BGA (X9119TB15)

a

a

l

j

b

Top View (Bump Side Down)

c

Side View (Bump Side Down)

m

k

f

Bottom View (Bump Side Up)

d

e

23

1

A

B

C

b

D

E

Note: Drawing not to scale

= Die Orientation mark

Millimeters Inches

Symbol

Min Nom. Max Min Nom. Max

Package Width a 2.534 2.564 2.594 0.0998 0.1010 0.1021

Package Length b 3.271 3.301 3.331 0.1288 0.1300 0.1311

Package Height c 0.654 0.682 0.710 0.0258 0.0269 0.0280

Body Thickness d 0.444 0.457 0.470 0.0175 0.0180 0.0185

Ball Height e 0.210 0.225 0.240 0.0083 0.0089 0.0094

Ball Base Diameter f 0.270 0.280 0.290 0.0106 0.0110 0.0114

Ball Pitch – Width j 0.5 0.0197

Ball Pitch – Length k 0.5 0.0197

Ball to Edge Spacing – Width l 0.747 0.782 0.817 0.0294 0.0308 0.0322

Ball to Edge Spacing – Length m 0.615 0.650 0.685 0.0242 0.0256 0.0270

REV 1.1.11 3/12/02

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Characteristics subject to change without notice. 20 of 22

X9119 – Preliminary Information

PACKAGING INFORMATION

14-Lead Plastic, TSSOP, Package Code V14

.025 (.65) BSC

0° - 8°

.0075 (.19)
.0118 (.30)

.193 (4.9)
.200 (5.1)

.019 (.50)
.029 (.75)

Detail A (20X)

.169 (4.3)
.177 (4.5)

.041 (1.05)

.002 (.05)
.006 (.15)

.010 (.25)

Gage Plane

Seating Plane

.252 (6.4) BSC

REV 1.1.11 3/12/02

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

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Characteristics subject to change without notice. 21 of 22

X9119 – Preliminary Information

ORDERING INFORMATION

X9119 P T VY

Device

PART MARK CONVENTION

15 Lead XBGA Top Mark

X9119TB15I-2.7 XAFF

X9119TB15 XAFC

VCC Limits

Blank = 5V ±10%
–2.7 = 2.7 to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C

Package

V14 = 14-Lead TSSOP
B15 = 15-Lead XBGA

Potentiometer Organization

Pot

T = 100KΩ

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

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Characteristics subject to change without notice. 22 of 22

©Xicor, Inc. 2000 Patents Pending

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