XICOR X88C75JISLIC, X88C75PSLIC, X88C75PMSLIC, X88C75PISLIC, X88C75LSLIC Datasheet
...
X88C75 SLIC® E
2
1
Port Expander and E2 Memory
FEATURES
• Highly Integrated Microcontroller Peripheral
—8K x 8 E2 Memory
—2 x 8 General Purpose Bidirectional I/O Ports
—16 x 8 General Purpose Registers
—Integerated Interrupt Controller Module
—Internal Programmable Address Decoding
• Self Loading Integrated Code (SLIC)
—On-Chip BIOS and Boot Loader
—IBM/PC Based Interface Software(XSLIC)
• Concurrent Read During Write
—Dual Plane Architecture
• Isolates Read/Write Functions Between Planes
• Allows Continuous Execution Of Code From
One Plane While Writing In The Other Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 80C51 Family of
Microcontrollers
• Software Data Protection
—Protect Entire Array During Power-up/-down
• Block Lock™ Data Protection
—Set Write Lockout in 1K Blocks
• Toggle Bit Polling
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
• 60mA Active
• 100µA Standby
• PDIP, PLCC, and TQFP Packaging Available
DESCRIPTION
The X88C75 SLIC is a highly integrated peripheral for
the 80C51 family of microcontrollers. The device integrates 8K-bytes of 5V byte-alterable nonvolatile memory,
two bidirectional 8-bit ports, 16 general purpose registers, programmable internal address decoding and a
multiplexed address and data bus.
The 5V byte-alterable nonvolatile memory can be used
as program storage, data storage, or a combination of
both. The memory array is separated into two 4K-bytes
sections which allows read accesses to one section
while a write operation is taking place in the other
section. The nonvolatile memory also features Software
Data Protection to protect the contents during power
transitions, and an advanced Block Protect register
©Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice
2887-2.5 4/11/97 T0/C0/D1 SH
SLIC
2887 ILL F01
RESET
A
12
WC
PSEN
STRA
A
15
NC
A
14
A
13
PA
7
PA
6
PA
5
PA
4
PA
3
PA
2
PA
1
PA
0
NC
A/D
0
A/D
1
A/D
2
A/D
3
A/D
4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
WR
ALE
A
8
A
9
A
11
NC
IRQ
STRB
PB
7
PB
6
PB
5
PB
4
PB
3
PB
2
PB
1
PB
0
NC
RD
A
10
CE
A/D
7
A/D
6
A/D
5
X88C75
PIN CONFIGURATIONS
DIP
2887 ILL F01
X88C75 SLIC® E2 Microperipheral
Concurrent Read During Write, Block Lock, and
SLIC
®
E2 are registered trademarks of Xicor, Inc.
APPLICATION NOTES
AVAILABLE
AN62 • AN64 • AN66
INDEX
CORNER
2887 ILL F02.4
6 5 4 3 2 1 44 43 42 41 40
18 19 20
22 23
24 25 26 27 28
21
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
A
15
STRA
PSEN
WC
A
12
RESET
V
CC
WR
ALE
A
8
A
9
A
11
IRQ
STRB
PB
7
PB
6
PB
5
PB
4
PB
3
PB
2
PB
1
PB
0
A
14
A
13
PA
7
PA
6
PA
5
PA
4
4
PA
3
33
PA
2
PA
1
PA
0
A/D
0
A/D
1
A/D
2
A/D
3
A/D
4
V
SS
A/D
5
A/D
6
A/D
7
CE
A
10
RD
X88C75
SLIC
PLCC
TQFP
X88C75 SLIC® E
2
2
Reading and writing of the nonvolatile memory array is
analogous to RAM operation. During a write operation to
either the nonvolatile memory or the control registers,
ALE latches the address to be written into the X88C75.
The rising edge of WR latches the data to be written.
The nonvolatile memory of the X88C75 is internally
organized as two independent arrays of 4K-bytes with
the A12 input selecting which of the two planes of
memory is to be accessed. While the processor is
executing code out of one plane, write operations can
take place in the other plane; allowing the processor to
continue execution of code out of the X88C75 during a
byte or page write to the device. This feature is called
Concurrent Read During Write.
The X88C75 also features an advanced implementation
of the Software Data Protection scheme, called Block
Lock Protect, which allows the nonvolatile memory array
to be treated as 8 independent sections of 1K-bytes.
Each of these sections can be independently enabled
for write operations. This allows segmentation of the
memory contents into writable and non-writable sections, thereby, allowing certain sections of the device to
be secured so that updates can only occur in a controlled
environment. (e.g. in an automotive application, only at
which allows Individual blocks of the memory to be
configured as read-only or read/write.
Each bidirectional port consists of 8 general purpose
I/O lines and 1 data strobe line. The ports also feature a
configurable interrupt request output.
Access to the X88C75 is accomplished through the
multiplexed address/data bus of the 80C51 type controllers. An internal programmable address decoder maps
the internal memory and register locations into the
desired address space.
ARCHITECTURAL OVERVIEW
The X88C75 incorporates the interface circuitry normally needed to decode the control signals and
demultiplex the address/data bus to provide a “seamless” interface.
The control inputs on the X88C75 are configured such
that it is possible to directly connect them to the proper
interface signals of the 80C51 microcontroller. The
reading of data from the chip is controlled either by the
PSEN or the RD signal, which essentially maps the
X88C75 into both the Program and the Data Memory
address map.
FUNCTIONAL DIAGRAM
2887 ILL F03
ADDRESS
LATCH
I/O
BUFFER
&
LATCH
MASTER
CONTROL
LOGIC
LEFT PLANE
DECODE
RIGHT PLANE
DECODE
1K X 8
1K X 8
E2PROM
CE
ALE
PSEN
RD
WR
RESET
IRQ
1K X 8
1K X 8
1K X 8
1K X 8
1K X 8
1K X 8
SDP
DECODE
CONFIG
REGISTER
MAPMEM.
PORT
SPECIAL
FUNCTION
REGISTERS
PORT
A
PORT
B
PORT SELECT
DAT A I/O BUS
A0–A
15
I/O0–I/O
7
WC
E2PROM
16 X 8
GENERAL
PURPOSE
REGISTERS
X88C75 SLIC® E
2
3
an authorized service center). The Block Protect configuration is stored in a nonvolatile register, ensuring
that the configuration data will be maintained after the
device is powered-down.
The X88C75 write control input, serves as an external
control over the completion of a previously initiated page
load cycle.
The X88C75 also features the industry standard 5V E
2
memory characteristics such as byte or page mode write
and Toggle Bit Polling.
Read
A HIGH to LOW transition on ALE latches the address;
the data will be output on the AD pins after either RD or
PSEN goes LOW (t
RDLV
).
Write
A write is performed by latching the addresses on the
falling edge of ALE. The WR is strobed LOW followed by
valid data being presented on the AD0–AD7 pins. The
data will be latched into the X88C75 on the rising edge
of WR.
Page Write Operation
The X88C75 supports page mode write operations. This
allows the microcontroller to write from one to thirty-two
bytes of data to the X88C75. Each individual write within
a page write operation must conform to the byte write
timing requirements. The falling edge of WR starts a
timer delaying the internal programming cycle 100µs:
therefore, each successive write operation must begin
within 100µs of the last byte written. The waveform
on page 4 illustrates the sequence and timing
requirements.
PIN DESCRIPTIONS
PIN NAME I/O DESCRIPTION
RESET I RESET is used to initialize the internal static registers and has no effect on the E2 memory opera-
tions. The default active level is HIGH, but it can be reconfigured in EEM register.
PSEN I Content of E
2
memory can be read by lowering the PSEN and holding both RD and WR HIGH. The
device then places on the data bus (AD7–AD0) the contents of E2 memory at the latched address.
STRA, STRB I/O The STRA controls port A and STRB controls port B. When ports are configured as inputs, a valid
transition on their strobe pins will latch into their port data register the data present at the port input
pins. Writing to an output port data register generates a pulse of fixed duration on its corresponding
strobe pin. The output data presented at the output pins stay valid until the next data is written to the
output port data register.
PA
7
–PA
0
I/O The I/O lines of port A. The output driver can be configured as either CMOS or open-drain using the
AWO bit in CR. The I/O direction bit (DIRA) in CR is used to select port A I/O mode.
PB
7
–PB
0
I/O The I/O lines of port B. The output driver can be configured as either CMOS or open-drain using the
BWO bit in CR. The I/O direction bit (DIRB) in CR is used to select port B I/O mode.
A15–A
8
I Non-multiplexed high-order Address Bus inputs for the upper byte of the address.
AD
7
–AD
0
I/O Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a HIGH
to LOW transition.
WR I During a byte/page write cycle WR is brought LOW while RD is held HIGH and the data is placed on
the Data Bus. The rising edge of WR will latch the data into the device.
RD I The RD input is active LOW and is used to read content of either the E
2
memory or the SFR at the
latched address. Both PSEN and WR signals must be held HIGH during RD controlled read
operation.
IRQ O The IRQ is an open-drain output. It can be configured to signal latching of new data into any of the
ports, and/or completion of the E2 memory internal write cycle.
WC I WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to
disable write to the E
2
memory. Taking WC HIGH prior to t
BLC
(100µs, the time delay from the last
write cycle to the start of internal programming cycle) will inhibit the write operation.
CE I The device select (CE) is an active LOW input. This signal has to be asserted prior to ALE HIGH to
LOW transition in order to generate a valid internal device select signal. Holding this pin HIGH and
ALE LOW will place the device in standby mode. The ports stay active at all times.
ALE I Address Latch Enable input is used to latch the addresses present on the address lines A
15–A8
and
AD7–AD0 into the device. The addresses are latched when ALE transitions from HIGH to LOW.
2887 PGM T01.1
X88C75 SLIC® E
2
4
Page Write Operation
Toggle Bit Polling
Because the X88C75 typical write timing is less than the
specified 5ms, Toggle Bit Polling has been provided to
determine the early completion of a write cycle. During
the internal programming cycle, I/O6 will toggle from “1”
to “0” and “0” to “1” on subsequent attempts to read from
the memory plane that is being updated. When the
Figure 1. Toggle Bit Polling
internal cycle is complete, the toggling will cease and
the device will be accessible for additional read or write
operations. Due to the dual plane architecture, reads for
polling must occur from the plane that was written; that
is, the state of A
12
during a write must match the state
of A12 during polling.
t
BLC
CE
ALE
A/D0–A/D
7
A8–A
12
WR
PSEN(RD)
A
IN
D
IN
A12=n
OPERATION
BYTE 0
BYTE 1
BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR
NEXT WRITE OPERATION
t
WC
2887 ILL F04
A
IN
D
IN
A12=n
A
IN
D
IN
A12=n
A
IN
D
IN
A12=n
A
IN
D
OUT
A12=x
A
IN
ADDR
A
IN
Next Address
RD
LAST BYTE
WRITTEN
CE
ALE
A/D0–A/D
7
A8–A
12
WR
A
IN
D
IN
A12=n
OPERATION
A
IN
D
OUT
A12=n
A
IN
D
OUT
A12=n
A
IN
D
OUT
A12=n
A
IN
D
OUT
A12=x
A
IN
ADDR
I/O6=X
X88C75 READY FOR
NEXT OPERATION
2887 ILL F05
I/O6=X I/O6=X I/O6=X
X88C75 SLIC® E
2
5
DATA PROTECTION
The X88C75 provides two levels of data protection
through software control. There is a global software data
protection feature similar to the industry standard for
E2PROMs and a new Block Lock Protect write lockout
protection providing a secondary level data security
option.
Software Data Protection
Software Data Protection (SDP) can be employed to
protect the entire array against inadvertent writes during
power-up/power-down operations. The X88C75 is
shipped from the factory with SDP enabled. With SDP
enabled, inadvertent attempts to write to the X88C75 will
be blocked.
The system can still write data, but only when the write
operation (page or byte) is preceded by the three-byte
command sequence. All write operations, both the command sequence and any data write operations must
conform to the page write timing requirements.
The SDP mode is also enabled anytime one of the
nonvolatile configuration registers are modified. These
include writing to EE map, SFR map, and BPR.
Block Lock Protect Write Lockout
The X88C75 provides a second level of data security
referred to as Block Lock Protect write lockout (or Block
Protect). This is accessed through an extension of the
SDP command sequence. Block Protect allows the user
to lockout writes to 1K x 8 blocks of memory. Unlike SDP
which prevents inadvertent writes, but still allows easy
system access to writing the memory, Block Protect will
lockout all attempts unless it is specifically disabled by
issuing the deactivation sequence. This feature can be
used to set a higher level of protection in a system where
a portion of the memory is used to store the system
kernel and protect it from the application programs
residing in the other blocks.
Setting write lockout is accomplished by writing a fivebyte command sequence opening access to the Block
Protect Register (BPR). After the fifth byte is written, the
user writes to the BPR, selecting which blocks to protect
or unprotect. All write operations, both the command
sequence and writing the data to the BPR, must conform
to the page write timing requirements. It should be noted
Figure 2. Writing With SDP Enabled
AA
b
2
P 555b1b
0
55
b
2
AAAb1b
0
A0
b
2
P 555b1b
0
2887 ILL F06
Perform Byte or
Page Write Operations
Reference the A15–A13
setting in EEM register
P = Address bit (A12) of the
updated memory plane
Delay of t
WC
Exit Routine
b2b1b
0
P
Figure 3. Sequence to Deactivate Software Data
Protection
AA
b
2
P 555b1b
0
55
b
2
AAA
AAA
b1b
0
A0
b
2
P 555b1b
0
AA
b
2
P 555b1b
0
80
b
2
P
2887 ILL F07
b1b
0
Reference the A15–A13
setting in EEM register
Delay of t
WC
Exit Routine
b2b1b
0
P
P = Address bit (A12) of the
memory plane not being read.
X88C75 SLIC® E
2
6
that accessing the BPR automatically sets the upper
level SDP. If for some reason the user does not want
SDP enabled, they may reset it using the normal reset
command sequence. This will not affect the state of the
BPR and any 1K x 8 blocks that were set to the write
lockout state will remain in the write lockout state.
Figure 4. Block Protect Register Format
Figure 5. Setting BPR Command Sequence
The BPR format and block map are illustrated above.
The command sequence is illustrated to the right.
MSB LSB
01234567
BLOCK
ADDRESS
0000-03FF
0400-07FF
0800-0BFF
0C00-0FFF
1000-13FF
1400-17FF
1800-1BFF
1C00-1FFF
“1” = Protect, “0” = Unprotect Block Specified
2887 ILL F08.1
AA
b
2
P 555b1b
0
55
b
2
AAA
AAA
b1b
0
A0
b
2
P 555b1b
0
AA
b
2
P 555b1b
0
C0
b
2
P
2887 ILL F09.1
b1b
0
Write BPR mask value
to any address
Reference the A15–A13
setting in E2M register
Delay of t
WC
Exit Routine
(BPR Register Set Global SDP Set)
b2b1b
0
P
P = Address bit (A12) of the
memory plane not being read.
Figure 6. Microcontroller Map
0000
1FFF
FFFF
2887 ILL F29.1
RESET/ISR VECTORS
USER
APPLICATION
CODE/DATA
8K BYTES OF BYTE
ALTERABLE DUAL
PLANE ARCHITECTURED
NON-VOLATILE MEMORY
(MAPPABLE TO ANY 8K
PAGE BY THE E2M BITS 2–0)
SRF (SPECIAL FUNCTION
REGISTER) BLOCK
(MAPPABLE TO ANY 1K
PAGE BY THE SFRM
REGISTER)
0030
0150
0000
1F00
1FFF
FC00
FFFF
SLIC
SLIC
X88C75 SLIC® E
2
7
Figure 7. On-Chip Registers
Programmable Address Decoding
The X88C75 features an internal programmable address decoder which allows the nonvolatile memory
array and the internal registers to be mapped in various
locations of the 64K-byte memory map. The register set
is mappable into a 1K-byte block, while the nonvolatile
memory array is mappable into an 8K-byte block. The
mapping is controlled by two nonvolatile configuration
registers, the SFR Map Register and the E2 Memory
Map Register. Their bits are mapped as follows:
SFR Map Register (SFRM) Default = 3F
0 0 A15 A14 A13 A12 A11 A10
76
2887 ILL F10
543210
A15-A10
The A15-A10 are upper address bits for the 1K-byte
page where the SFR memory is mapped.
0
2887 ILL F30.2
0 LAM 0 RST A15 A14 A13
76543210
FC38
EEM*
E2 Memory Map Register
MSB LSB
FC08
PDRB
Port Data Register B
MSB LSB
FC10
PDRA
Port Data Register A
INT INTA INTB ENA ENB ENEE 0 EOW
FC18
ISR
Interrupt Status Register
IRST 1 AWO BWO DIRA DIRB STRA STRB
FC20
CR
Configuration Register
MSB LSB
FC28
PPRB
Port Pin Register B
MSB LSB
FC30
PPRA
Port Pin Register A
Special Function Register
Memory Map Register
0
NOTE: * The value returned by reading these registers is the complement of the
actual data. These registers are nonvolatile and a special SDP sequence
is used to alter their contents. All the other registers are initialized by a
valid reset input signal and when the device is power cycled.
0 A15 A14 A13 A12 A11 A10
FC00
SFRM*
FE00
FE0F
16 Bytes General Purpose SRAM
MSB LSB
MSB LSB
X88C75 SLIC® E
2
8
Figure 8. Setting the SFR Map Register
Figure 9. Setting Program Memory Map Register
BITS 7:6
Setting these two bits to any combination other than “00”
or “11” will interfere with device proper operation.
E2 Memory Map Register (EEM) Default = 08
0 0 LAM 0 RST A15 A14 A13
76
2887 ILL F11
543210
A15-A13
Modifying these three bits changes the location of the
program memory within the address map.The A15-A13
correspond to the upper three address bits of the 8Kbyte page where program memory will be mapped.
RST
The RST bit controls the polarity of the RESET input pin.
“0” = RESET is Active LOW
“1” = RESET is Active HIGH
LAM
Port B can be configured as either a general purpose
I/O port (normal I/O mode), or latched address mode
(LAM). The LAM option programs port B to output the
demultiplexed low order byte of the address latched into
the X88C75 by ALE. The LAM bit selects between these
two modes.
“0” = PORT B is I/O Port
“1” = Port B outputs low address byte (A7-A0)
Setting the Mapping Registers
The mapping registers are written using a modified
version of the Software Data Protection sequence. All
timings must adhere to the normal Software Data Protection sequence.
The complemented contents of the SFR map register
and the E2 memory map register can be read by the
microcontroller at their corresponding SFR addresses.
The physical memory location of these registers can be
derived by adding the following offset to the SFR base
address:
SFR Map Register 00H
E2 Memory Map Register 38H
If the regions specified in the map registers overlap, only
the SFR will be accessible.
AA
b
2
P 555b1b
0
55
b
2
AAA
AAA
b1b
0
A0
b
2
P 555b1b
0
AA
b
2
P 555b1b
0
D0
Delay of t
WC
Exit Routine
b
2
P
2887 ILL F12.1
b1b
0
XXX
Desired
Value
b
2Pb1b0
X = Don’t Care
B[2:0] = E2M [2:0]
P = Address bit (A12) of the
memory plane not being read.
P
AA
b
2
P 555b1b
0
55
b
2
AAA
AAA
b1b
0
A0
b
2
P 555b1b
0
AA
b
2
P 555b1b
0
E0
b
2
P
2887 ILL F13.1
b1b
0
XXX
Desired
Value
b
2Pb1b0
P
Delay of t
WC
Exit Routine
X = Don’t Care
B[2:0] = E2M [2:0]
P = Address bit (A12) of the
memory plane not being read.
X88C75 SLIC® E
2
9
Interrupt Status Register (ISR)
The Interrupt Status Register is a volatile register used
to configure the interrupt condition for the I/O ports as
well as to determine the interrupt status of the ports. The
X88C75 ports can generate an interrupt to the microcontroller upon the proper transition (as specified in the
configuration register) on either STRA or STRB pins
when the corresponding I/O port is configured as an
input.
The INT flag is set when any of the input strobes are
toggled provided that their corresponding interrupt enable bits (ENA, ENB) are set. The INT flag is cleared
when latched data is read (PDR) or pending interrupt
status flag (INTA, INTB) in ISR is forced to “0” by the
interrupt service routine. Interrupt service routine should
examine the interrupt status flags (INTA, INTB) and
identify the source of pending interrupt.
The E2 memory interrupt status flag (EOW) is another
means to detect the early completion of a write cycle.
When ENEE is enabled, the hardware will set the EOW
flag, and interrupt the microcontroller at the end of an
internal programming cycle. Toggle Bit Polling can be
replaced by this hardware interrupt, which reduces the
software overhead. The EOW flag should be cleared by
software. The interrupt status register bits are mapped
as follows.
Figure 10. Interrupt Status Register
INT
2887 ILL F14.1
INTA INTB ENA ENB ENEE 0 EOW
76543210
Interrupt Flag
“0” = No pending interrupt
“1” = Interrupt request
Port B – Interrupt Status
“0” = No pending interrupt
“1” = Port B latched data when a valid
transition occurred on the STRB
and port B was an input port.
Port A – Interrupt Enable
“0” = Mask off interrupt
“1” = Interrupt enabled
Port B – Interrupt Enable
“0” = Mask off interrupt
“1” = Interrupt enabled
EEPROM Interrupt Enable
“0” = Mask off interrupt
“1” = Interrupt enabled
EEPROM Interrupt Status
“0” = Programming in progress
“1” = Set by hardware when it completes
programming the previously
written data
Port A – Interrupt Status
“0” = No pending interrupt
“1” = Port A latched data when a valid
transition occurred on the STRA
and port A was an input port.
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