XICOR X86C64SM, X86C64SI, X86C64S, X86C64PM, X86C64PI Datasheet
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Preliminary Information
X86C64
Z8® Microcontroller Family Compatible
64K X86C64 8192 x 8 Bit
E2 Micro-Peripheral
FEATURES
• CONCURRENT READ WRITE
™
—Dual Plane Architecture
Isolates Read/Write Functions
Between Planes
Allows Continuous Execution of Code
From One Plane While Writing in the Other
Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g. Zilog Z8 Family
• High Performance CMOS
—Fast Access Time, 120 ns
—Low Power
60 mA Maximum Active
200 µA Maximum Standby
• Software Data Protection
• Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
• Toggle Bit
—Early End of Write Detection
• Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
DESCRIPTION
The X86C64 is an 8K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technology. The X86C64 features a Multiplexed Address and
Data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface
circuitry.
The X86C64 is internally configured as two independent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an auxiliary memory device for code storage.
To write to the X86C64, a three byte command
sequence must precede the byte(s) being written. The
X86C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight, 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the
memory to have varying degrees of alterability in normal system operation.
FUNCTIONAL DIAGRAM
CE
R/W
DS
SEL
A8–A11
AS
Z8® is a registered trademark of Zilog Corporation
CONCURRENT READ WRITE™ is a trademark of Xicor, Inc.
© Xicor, 1991 Patents Pending Characteristics subject to change without notice
3819-2.1 7/29/96 T0/C1/D1 SH
CONTROL
LOGIC
L
A
T
C
H
E
S
Y DECODE
X
D
E
C
O
D
E
I/O & ADDRESS LATCHES AND BUFFERS
WC
SOFTWARE
DATA
PROTECT
1K BYTES
1K BYTES
1K BYTES
1K BYTES
1
A12
A12
A12
M
U
X
A/D0–A/D7
1K BYTES
1K BYTES
1K BYTES
1K BYTES
3819 FHD F02
X86C64
PIN DESCRIPTIONS
Address/Data (A/D0–A/D7)
Multiplexed low-order addresses and data. The addresses flow into the device while AS is LOW. After AS
transitions from a LOW to HIGH the addresses are
latched. Once the addresses are latched these pins input
data or output data depending on DS, R/W, and CE.
Addresses (A8–A12)
High order addresses flow into the device when AS = V
and are latched when AS goes HIGH.
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. When CE is LOW and AS is HIGH, the
X86C64 is placed in the low power standby mode.
Data Strobe (DS)
When used with a Z8 the DS input is tied directly to the
DS output of the microcontroller.
Read/Write (R/W)
When used with a Z8 the R/W input is tied directly to the
R/W output of the microcontroller.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is LOW and are latched when AS transitions
from a LOW to HIGH.
Device Select (SEL)
Must be connected to VSS.
Write Control (WC)
The Write Control allows external circuitry to abort a
page load cycle once it has been initiated. This input is
useful in applications in which a power failure or processor RESET could interrupt a page load cycle. In this
case, the microcontroller might drive all signals HIGH,
causing bad data to be latched into the E2PROM. If the
Write Control input is driven HIGH (before t
TBLC
Max)
after Read/Write (R/W) goes HIGH, the write cycle will
be aborted.
PIN CONFIGURATION
DIP/SOIC
NC
1
A12
IL
SEL
A/D0
A/D1
A/D2
A/D3
A/D4
V
NC
NC
WC
SS
2
3
4
5
6
7
8
9
10
11
12
X86C64
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
R/W
AS
A8
A9
A11
DS
A10
CE
A/D7
A/D6
A/D5
3819 FHD F01
PIN NAMES
Symbol Description
AS Address Strobe
A/D0–A/D
A8–A
12
7
Address Inputs/Data I/O
Address Inputs
DS Data Strobe Input
R/W Read/Write Input
CE Chip Enable
WC Write Control
SEL Device Select—Connect to V
V
SS
V
CC
Ground
Supply Voltage
SS
3819 PGM T01
When WC is LOW (tied to VSS) the X86C64 will be
enabled to perform write operations. When WC is HIGH
normal read operations may be performed, but all attempts to write to the device will be disabled.
2
X86C64
PRINCIPLES OF OPERATION
The X86C64 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The
X86C64 provides 8K bytes of 5-volt E2PROM which can
be used either for Program Storage, Data Storage or a
combination of both in systems based upon Von
Neumann (86XX) architectures. The X86C64 incorporates the interface circuitry normally needed to decode
the control signals and demultiplex the Address/Data
bus to provide a “ Seamless” interface.
The interface inputs on the X86C64 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip
microcontroller.
The X86C64 is internally organized as two independent
planes of 4K bytes of memory with the A12 input selecting which of the two planes of memory are to be
accessed. While the processor is executing code out of
one plane, write operations can take place in the other
plane, allowing the processor to continue execution of
code out of the X86C64 during a byte or page write to the
device.
The X86C64 also features an advanced implementation
of the Software Data Protection scheme, called Block
Protect, which allows the device to be broken into 8
independent sections of 1K bytes. Each of these sections can be independently enabled for write operations;
thereby allowing certain sections of the device to be
secured so that updates can only occur in a controlled
environment (e.g. in an automotive application, only at
an authorized service center). The desired set-up configuration is stored in a nonvolatile register, ensuring the
configuration data will be maintained after the device is
powered down.
The X86C64 also features a Write Control input (WC),
which serves as an external control over the completion
of a previously initiated page load cycle.
DEVICE OPERATION
Zilog Z8 operation requires the microcontroller’s AS, DS
and R/W outputs tied to the X86C64 AS, DS and
R/W inputs respectively.
The rising edge of AS will latch the addresses for both a
read and write operation. The state of R/W output
determines the operation to be performed, with the DS
signal acting as a data strobe.
If R/W is HIGH and CE HIGH (read operation) data will
be output on A/D0–A/D7 after DS transitions LOW. If
R/W is LOW and CE is HIGH (write operation) data
presented at A/D0–A/D7 will be strobed into the X86C64
on the LOW to HIGH transition of DS.
Typical Application
X86C64Z8
24
V
CC
V
SS
12
3819 FHD F03
21
P10
22
P11
23
P12
24
P13
25
2
XTAL
3
EXTAL
P14
P15
P16
P17
P00
P01
P02
P03
P04
P07
AS
DS
R/W
26
27
28
13
14
15
16
17
20
9
8
7
7
A/D0
8
A/D1
9
A/D2
10
A/D3
11
A/D4
13
A/D5
14
A/D6
15
A/D7
21
A8
20
A9
17
A10
19
A11
2
A12
16
CE
5
WC
22
AS
18
DS
23
R/W
6
SEL
The X86C64 also features the industry standard 5-volt
E2PROM characteristics such a byte or page mode write
and toggle-bit polling.
3
X86C64
MODE SELECTION
CE DS R/W Mode I/O Power
V
SS
V
IL
V
IH
V
IH
X X Standby High Z Standby (CMOS)
X X Standby High Z Standby (TTL)
V
IL
V
IH
V
IL
Read D
Write D
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X86C64
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X86C64. Each individual write within a page
write operation must conform to the byte write timing
requirements. The falling edge of DS starts a timer
delaying the internal programming cycle 100 µs. Therefore, each successive write operation must begin within
100 µs of the last byte written. The following waveforms
illustrate the sequence and timing requirements.
Page Write Timing Sequence for DS Controlled Operation
OPERATION
CE
AS
A/D0–A/D
7
BYTE 0
A
IN
D
IN
BYTE 1
A
IN
BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR
D
IN
A
D
IN
IN
A
OUT
IN
D
IN
IN
A
D
IN
IN
Active
Active
NEXT WRITE OPERATION
A
IN
A
IN
3819 PGM T08
A8–A
R/W
DS
12
A12=n
t
A12=n
BLC
A12=n
A12=n
A12=x
t
ADDR
WC
Notes: (1) For each successive write within a page write cycle A5–A12 must be the same.
(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page
write operation. Two responses are possible.
a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation.
b. Reading from the opposite plane being written (A12 of Read ≠ A12 of Write) true data will be returned, facilitating the use of a
single memory component as both program and data store.
Next Address
3819 FHD F07
3819 FHD F07
4
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