XICOR X84641V20I-2,5, X84641V20I-1,8, X84641V20I, X84641V20-2,5, X84641V20-1,8 Datasheet



Xicor, Inc. 1994, 1997Patents Pending

7008-1.2 8/26/97 T2/C0/D0 SH

1

Characteristics subject to change without notice

APPLICATION NOTE

A V A I L A B L E

16K/64K/128K MPS



EEPROM

µ

Port Saver EEPROM

FEATURES

• Up to 10MHz data transfer rate

• 25ns Read Access Time

• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters

• Low Power CMOS
—1.8V–3.6V, 2.5V–5.5V and 5V ± 10% Versions
—Standby Current Less than 1 µ A
—Active Current Less than 1mA

• Byte or Page Write Capable
—32-Byte Page Write Mode

• Typical Nonvolatile Write Cycle Time: 2ms

• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years

DESCRIPTION

The µ Port Saver memories need no serial ports or spe­cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µ Port Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µ Port Saver provides all
the serial benefits, such as low cost, low power, low volt­age, and small package size while releasing I/Os for
more important uses.

The µ Port Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the µ Port Saver supplies data faster than required
by most host read cycle specifications. This eliminates
the need for software NOPs.

The µ Port Saver memories communicate ov er one line of
the data bus using a sequence of standard bus read and
write operations. This “bit serial” interface allows the

µ

Port Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit

systems.
A Write Protect (WP

) pin prevents inadvertent writes to

the memory .
Xicor EEPROMs are designed and tested for applica-

tions requiring extended endurance. Inherent data reten­tion is greater than 100 years.

BLOCK DIAGRAM

CE

I/O

H.V. GENERATION

TIMING & CONTROL

EEPROM

COMMAND

DECODE

AND

CONTROL

LOGIC

X

DEC

Y DECODE

DATA REGISTER

WP

7008 FRM F02.1

OE

WE

ARRAY
16K x 8

P0/CS
P1/CLK
P2/DI
P3/DO

System Connection

Internal Block Diagram

µP
µC

Ports

8K x 8
2K x 8

Saved

DSP

ASIC

A15

A0
D7

D0

OE

WE

MPS

RISC

X84161/641/129

AN95 • AN103 • AN107

X84161/641/129

2

PIN DESCRIPTIONS
Chip Enable (CE

)

The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese­lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby pow er mode.

Output Enable (OE)

The Output Enable input must be LOW to enab le the out­put buffer and to read data from the de vice on the I/O line.

Write Enable (WE)

The Write Enable input must be LO W to write either data
or command sequences to the device.

Data In/Data Out (I/O)

Data and command sequences are serially written to or
serially read from the device through the I/O pin.

Write Protect (WP)

When the Write Protect input is LOW, nonvolatile writes
to the device are disabled. When WP is HIGH, all func­tions, including nonvolatile writes, operate normally. If a
nonvolatile write cycle is in progress, WP going LOW will
have no effect on the cycle already underway, but will
inhibit any additional nonvolatile write cycles.

PIN CONFIGURATIONS: Drawings are to the same scale, actual package sizes are shown in inches:

V

CC

NC
OE
WE

CE
I/O

WP

V

SS

1
2
3
4

8
7

6
5

8-LEAD SOIC

7008 FRM F01

1
2
3
4
5
6
7

8

14
13
12
11
10

9

14-LEAD SOIC

CE
I/O

NC
NC
NC

WP

V

SS

V

CC

NC
NC
NC
NC
OE
WE

PIN NAMES

7008 FRM T01

I/O Data Input/Output
CE

Chip Enable Input

OE

Output Enable Input

WE

Write Enable Input

WP

Write Protect Input

V

CC

Supply Voltage

V

SS

Ground

NC No Connect

PACKAGE
SELECTION GUIDE

7008 FRM T0A

84161

8-Lead PDIP
8-Lead SOIC
8-Lead TSSOP

84641

8-Lead PDIP
8-Lead SOIC
20-Lead TSSOP

84129

8-Lead PDIP
14-Lead SOIC
28-Lead TSSOP

1
2
3
4
5
6
7

20
19
18
17
16
15
14

20-LEAD TSSOP

CE
I/O
NC
NC
NC

WP

V

SS

V

CC

NC
NC
NC
NC
OE
WE

8
9
10

13
12
11

NC

NC

NC

NC

NC

NC

1
2
3
4
5
6
7

20
19
18
17
16
15

28-LEAD TSSOP

NC
NC

WP
V

SS

NC
NC
NC
OE
WE
NC
NC

8
9
10

I/O

CE

NC

V

CC

NC

NC

CE

CE

NC

NC

NC

NC

NC

NC

11
12
13
14

21

22

23

24

25

26

27

28

X84161
X84641

X84129

.190 in.

.230 in.

.230 in.

.390 in.

.250 in.

.394 in.

.252 in.

. 252 in.

X84129

X84641

NC

NC

NC

OE

NC

V

CC

CE

I/O

1
2

3

4

8
7
6

5

8-LEAD TSSOP

X84161

.114 in.

.252 in.

WE
WP

V

SS

8-LEAD PDIP

X84161/641/129

3

DEVICE OPERATION

The X84161/641/129 are serial EEPROMs designed to
interface directly with most microprocessor buses. Stan­dard CE, OE, and WE signals control the read and write
operations, and a single l/O line is used to send and
receive data and commands serially .

Data Timing

Data input on the l/O line is latched on the rising edge of
either WE

or CE, whichever occurs first. Data output on
the l/O line is active whenev er both OE and CE are LO W.
Care should be taken to ensure that WE and OE are
never both LO W while CE is LO W .

Read Sequence

A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and CE
LOW, OE HIGH) to the part without a read cycle between
the write cycles. The address is sent serially, most signifi­cant bit first, over the I/O line. Note that this sequence is
fully static, with no special timing restrictions, and the pro­cessor is free to perform other tasks on the bus when­ever the device CE pin is HIGH. Once the 16 address
bits are sent, a byte of data can be read on the I/O line by
issuing 8 separate read cycles (OE and CE LOW, WE
HIGH). At this point, writing a ‘1’ will terminate the read

sequence and enter the low power standby state, other­wise the device will await further reads in the sequential
read mode.

Sequential Read

The byte address is automatically incremented to the
next higher address after each byte of data is read. The
data stored in the memory at the next address can be
read sequentially by continuing to issue read cycles.
When the highest address in the array is reached, the
address counter rolls over to address $0000 and reading
may be continued indefinitely.

Reset Sequence

The reset sequence resets the device and sets an inter­nal write enable latch. A reset sequence can be sent at
any time by performing a read/write “0”/read operation
(see Figs. 1 and 2). This breaks the multiple read or write
cycle sequences that are normally used to read from or
write to the part. The reset sequence can be used at any
time to interrupt or end a sequential read or page load.
As soon as the write “0” cycle is complete, the part is
reset (unless a nonvolatile write cycle is in progress). The
second read cycle in this sequence, and any further read
cycles, will read a HIGH on the l/O pin until a valid read
sequence (which includes the address) is issued. The
reset sequence must be issued at the beginning of both
read and write sequences to be sure the device initiates
these operations properly .

Figure 1. Read Sequence

CE

OE

WE

I/O (IN)

"0"

RESET

WHEN ACCESSING: X84161 ARRAY: A15–A11=0
X84641 ARRAY: A15–A13=0
X84129 ARRAY: A15–A14=0

LOAD ADDRESS READ DATA

A15 A14 A13 A12 A11

A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

I/O (OUT)

7008 FRM F04.1

D7 D6 D5 D4 D3 D2 D1 D0

X84161/641/129

4

Write Sequence

A nonvolatile write sequence consists of sending a reset
sequence, a 16-bit address, up to 32 bytes of data, and
then a special “start nonvolatile write cycle” command
sequence.

The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write enable
latch. The address is written serially by issuing 16
separate write cycles (WE

and CE LOW, OE HIGH) to
the part without any read cycles between the writes. The
address is sent serially, most significant bit first, on the
l/O pin. Up to 32 bytes of data are written by issuing a
multiple of 8 write cycles. Again, no read cycles are
allowed between writes.

The nonvolatile write cycle is initiated by issuing a special
read/write “1”/read sequence. The first read cycle ends
the page load, then the write “1” followed by a read starts
the nonvolatile write cycle. The device recognizes 32­byte pages (e.g., beginning at addresses XXXXXX00000
for X84161).

When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the

page, where data loading can continue. For this reason,
sending more than 256 consecutive data bits will result in
overwriting previous data.

A nonvolatile write cycle will not start if a partial or incom­plete write sequence is issued. The internal write enable
latch is reset when the nonvolatile write cycle is com­pleted and after an invalid write to prevent inadvertent
writes. Note that this sequence is fully static , with no spe­cial timing restrictions. The processor is free to perform
other tasks on the bus whenev er the chip enable pin (CE)
is HIGH.

Nonvolatile Write Status

The status of a nonvolatile write cycle can be determined
at any time by simply reading the state of the l/O pin on
the device. This pin is read when OE and CE are LOW
and WE is HIGH. During a nonvolatile write cycle the l/O
pin is LOW. When the nonvolatile write cycle is complete,
the l/O pin goes HIGH. A reset sequence can also be
issued during a nonvolatile write cycle with the same
result: I/O is LOW as long as a nonvolatile write cycle is
in progress, and l/O is HIGH when the nonvolatile write
cycle is done.

Figure 2: Write Sequence

CE

OE

WE

I/O (IN)

"0"

"0"

"1"

RESET LOAD ADDRESS LOAD DATA START

NONVOLATILE

WRITE

A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

I/O (OUT)

7008 FRM F05.1

WHEN ACCESSING: X84161 ARRAY: A15–A11=0
X84641 ARRAY: A15–A13=0
X84129 ARRAY: A15–A14=0

A15 A14 A13 A12 A11

A10

A9

X84161/641/129

5

Low Power Operation

The device enters an idle state, which dra ws minimal cur­rent when:

—an illegal sequence is entered. The following are the

more common illegal sequences:

• Read/Write/Write—any time

• Read/Write ‘1’—When writing the address or
writing data.

• Write ‘1’—when reading data

• Read/Read/Write ‘1’—after data is written to
device, but bef ore entering the NV write sequence.

—the device powers-up;
—a nonvolatile write operation completes.
While a sequential read is in progress, the device

remains in an active state. This state draws more current
than the idle state, but not as much as during a read
itself. To go back to the lowest power condition, an inv alid
condition is created by writing a ‘1’ after the last bit of a
read operation.

Write Protection

The following circuitry has been included to prevent
inadvertent nonvolatile writes:

—The internal Write Enable latch is reset upon

power-up.

—A reset sequence must be issued to set the internal

write enable latch before starting a write sequence.

—A special “start nonvolatile write” command sequence

is required to start a nonvolatile write cycle.

—The internal Write Enable latch is reset automatically

at the end of a nonvolatile write cycle.

—The internal Write Enable latch is reset and remains

reset as long as the WP

pin is LOW, which blocks all

nonvolatile write cycles.

—The internal Write Enable latch resets on an invalid

write operation.

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

Must be
steady

Will be
steady

May change
from LOW to
HIGH

Will change
from LOW to
HIGH

May change
from HIGH to
LOW

Will change
from HIGH to
LOW

Don’t Care:
Changes
Allowed

Changing:
State Not
Known

N/A Center Line

is High
Impedance

X84161/641/129

6

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias ......................–65 ° C to +135 ° C

Storage Temperature...........................–65 ° C to +150 ° C

Terminal Voltage with

Respect to V

SS

.......................................–1V to +7V

DC Output Current................................................... 5mA

Lead Temperature (Soldering, 10 seconds)..........300 ° C

RECOMMENDED OPERATING CONDITIONS

7008 FRM T02

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this speci­fication is not implied. Exposure to absolute maximum
rating conditions for e xtended periods ma y affect device
reliability.

7008 FRM T03

Temperature Min. Max.

Commercial 0 ° C +70 ° C

Industrial –40 ° C +85 ° C

Military† –55 ° C +125 ° C

Supply Voltage Limits

X84161/641/129 5V ± 10%
X84161/641/129 – 2.5 2.5V to 5.5V
X84161/641/129 – 1.8 1.8V to 3.6V

D.C. OPERATING CHARACTERISTICS (V

CC

= 5V ± 10%)

(Over the recommended operating conditions, unless otherwise specified.)

7008 FRM T04.2

Notes: (1) V

IL

Min. and V

IH

Max. are f or reference only and are not tested.

Symbol Parameter

Limits

Units Test ConditionsMin. Max.

I

CC1

V

CC

Supply Current (Read) 1 mA OE

= V

IL

, WE

= V

IH

,

I/O = Open, CE

clocking @ 10MHz

I

CC2

V

CC

Supply Current (Write)

2 mA

I

CC

During Nonvolatile Write Cycle

All Inputs at CMOS Levels

I

SB1

V

CC

Standby Current

1

µ

A

CE = V

CC

, Other Inputs = V

CC

or V

SS

I

LI

Input Leakage Current 10

µ

A

V

IN

= V

SS

to V

CC

I

LO

Output Leakage Current 10

µ

A

V

OUT

= V

SS

to V

CC

V

lL

(1)

Input LOW Voltage –0.5

V

CC

x 0.3

V

V

IH

(1)

Input HIGH Voltage

VCC x 0.7 VCC + 0.5

V

V

OL

Output LOW Voltage 0.4 V

IOL = 2.1mA

V

OH

Output HIGH Voltage

VCC – 0.8

V

IOH = –1mA

Notes: † Contact factory for Military availability