Xicor X84256 Technical data

查询X84256供应商
Preliminary 256K MPS
X84256
µPort Saver EEPROM
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct Interface to Microprocessors and Microcontrollers —Eliminates I/O port requirements —No interface glue logic required —Eliminates need for parallel to serial converters
• Low Power CMOS —2.5V–5.5V and 5V ±10% Versions —Standby Current Less than 1µA —Active Current Less than 3mA
• Byte or Page Write Capable —64-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 2ms
• High Reliability —1,000,000 Endurance Cycles —Guaranteed Data Retention: 100 Years
• Small Packages Options —8, 16-Lead SOIC Packages —14-Lead TSSOP Packages —8-Lead XBGA Packages
DESCRIPTION
The µPort Saver memories need no serial ports or spe­cial hardware and connect to the processor memory bus. Replacing bytewide data memory, the µPort Saver uses bytewide memory control functions, takes a fraction of the board space and consumes much less power. Replacing serial memories, the µPort Saver provides all the serial benefits, such as low cost, low power, low volt­age, and small package size while releasing I/Os for more important uses.
The µPort Saver memory outputs data within 25ns of an active read signal. This is less than the read access time of most hosts and provides “no-wait-state” operation. This prevents bottlenecks on the bus. With rates to 10 MHz, the µPort Saver supplies data faster than required by most host read cycle specifications. This eliminates the need for software NOPs.
The µPort Saver memories communicate over one line of the data bus using a sequence of standard bus read and write operations. This “bit serial” interface allows the µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit systems.
EEPROM
BLOCK DIAGRAM
System Connection
P0/CS
Ports Saved
P1/CLK P2/DI P3/DO
µP µC
DSP
ASIC RISC
A15
A0 D7
D0
OE
WE
A Write Protect (WP
) pin prevents inadvertent writes to
the memory . Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten­tion is greater than 100 years.
Internal Block Diagram
MPS
WP
CE
I/O
OE
WE
COMMAND
DECODE
AND
CONTROL
LOGIC
DEC
H.V. GENERATION
TIMING & CONTROL
X
Y DECODE
DATA REGISTER
EEPROM
ARRAY 32K x 8
Xicor, Inc. 1998 Patents Pending
1
Characteristics subject to change without notice
X84256 Preliminary
PIN CONFIGURATIONS
Drawings are to the same scale, actual package siz es are shown in inches:
8-LEAD SOIC
V NC
OE WE
V
NC NC NC NC
OE
WE
I/O CE
V WP
V
NC NC NC NC NC
OE
WE
CC
CC
SS
CC
8
7
6 5
8
7
6 5
V
CE
I/O
WP
V
SS
CE
V
CC
NC
WE OE
CE
V
14-LEAD TSSOP
I/O NC
NC NC WP
SS
16-LEAD SOIC
I/O NC
NC NC NC WP
SS
1
2 3 4
1 2
3 4
5 6
7
8-LEAD XBGA
14 13
12 11
10
1
2
X84256
3 4
1 2
3 4
5 6
7 8
16 15
14 13
12 11 10
9 8
9
PIN NAMES
I/O Data Input/Output CE OE WE WP V
CC
V
SS
Chip Enable Input Output Enable Input Write Enable Input Write Protect Input Supply Voltage
Ground
NC No Connect
PIN DESCRIPTIONS Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, the chip is dese­lected, the I/O pin is in the high impedance state, and unless a nonvolatile write operation is underway, the device is in the standby pow er mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the out­put buffer and to read data from the de vice on the I/O line.
Write Enable (WE)
The Write Enable input must be LOW to write either data or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to or serially read from the device through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes to the device are disabled. When WP is HIGH, all functions, including nonvolatile writes, operate normally. If a nonvol­atile write cycle is in progress, WP going LOW will have no effect on the cycle already underway, but will inhibit any additional nonvolatile write cycles.
DEVICE OPERATION
The X84256 serial EEPROM is designed to interface directly with most microprocessor buses. Standard CE, OE, and WE signals control the read and write opera­tions, and a single l/O line is used to send and receive data and commands serially .
2
X84256 Preliminary
Data Timing
Data input on the l/O line is latched on the rising edge of either WE or CE, whichever occurs first. Data output on the l/O line is active whenev er both OE and CE are LO W. Care should be taken to ensure that WE and OE are never both LO W while CE is LO W .
Read Sequence
A read sequence consists of sending a 16-bit address followed by the reading of data serially. The address is written by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without a read cycle between the write cycles. The address is sent serially, most signifi­cant bit first, over the I/O line. Note that this sequence is fully static, with no special timing restrictions, and the processor is free to perform other tasks on the bus when­ever the device CE pin is HIGH. Once the 16 address bits are sent, a byte of data can be read on the I/O line by issuing 8 separate read cycles (OE and CE LOW, WE HIGH). At this point, writing a ‘1’ will terminate the read sequence and enter the low power standby state, other­wise the device will await further reads in the sequential read mode.
Sequential Read
The byte address is automatically incremented to the next higher address after each byte of data is read. The data stored in the memory at the next address can be read sequentially by continuing to issue read cycles. When the highest address in the array is reached, the address counter rolls over to address $0000 and reading may be continued indefinitely.
Reset Sequence
The reset sequence resets the device and sets an inter­nal write enable latch. A reset sequence can be sent at any time by performing a read/write “0”/read operation (see Figs. 1 and 2). This breaks the multiple read or write cycle sequences that are normally used to read from or write to the part. The reset sequence can be used at any time to interrupt or end a sequential read or page load. As soon as the write “0” cycle is complete, the part is reset (unless a nonvolatile write cycle is in progress). The second read cycle in this sequence, and any further read cycles, will read a HIGH on the l/O pin until a valid read sequence (which includes the address) is issued. The reset sequence must be issued at the beginning of both read and write sequences to be sure the device initiates these operations properly .
Write Sequence
A nonvolatile write sequence consists of sending a reset sequence, a 16-bit address, up to 64 bytes of data, and then a special “start nonvolatile write cycle” command sequence.
The reset sequence is issued first (as described in the Reset Sequence section) to set an internal write enable latch. The address is written serially by issuing 16 separate write cycles (WE
and CE LOW, OE HIGH) to the part without any read cycles between the writes. The address is sent serially, most significant bit first, on the l/O pin. Up to 64 bytes of data are written by issuing a multiple of 8 write cycles. Again, no read cycles are allowed between writes.
CE
OE
WE
"0"
I/O (IN)
I/O (OUT)
RESET
WHEN ACCESSING: X84256 ARRAY: A15=0
A15 A14 A13 A12 A11
A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
LOAD ADDRESS READ DATA
Figure 1. Read Sequence
3
X84256 Preliminary
CE
OE
WE
"0"
I/O (IN)
I/O (OUT)
RESET LOAD ADDRESS LOAD DATA START
WHEN ACCESSING: X84256 ARRAY: A15=0
A15 A14 A13 A12 A11
A10
A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A9
Figure 2. Write Sequence
The nonvolatile write cycle is initiated by issuing a special read/write “1”/read sequence. The first read cycle ends the page load, then the write “1” followed by a read starts the nonvolatile write cycle. The device recognizes 64­byte pages (e.g., beginning at addresses XXXXXXXXX 000000 for X84256).
When sending data to the part, attempts to exceed the upper address of the page will result in the address counter “wrapping-around” to the first address on the page, where data loading can continue. For this reason, sending more than 512 consecutive data bits will result in overwriting previous data.
A nonvolatile write cycle will not start if a partial or incom­plete write sequence is issued. The inter nal wr ite enable latch is reset when the nonvolatile write cycle is com­pleted and after an invalid write to prevent inadvertent writes. Note that this sequence is fully static , with no spe­cial timing restrictions. The processor is free to perform other tasks on the bus whenever the chip enable pin (CE) is HIGH.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be determined at any time by simply reading the state of the l/O pin on the device. This pin is read when OE and CE are LOW and WE is HIGH. During a nonvolatile write cycle the l/O pin is LOW. When the non volatile write cycle is complete, the l/O pin goes HIGH. A reset sequence can also be issued during a nonvolatile write cycle with the same
"1"
"0"
NONVOLATILE
WRITE
result: I/O is LOW as long as a nonvolatile write cycle is in progress, and l/O is HIGH when the nonvolatile write cycle is done.
Low Power Operation
The device enters an idle state, which draws minimal current when:
• an illegal sequence is entered. The following are the more common illegal sequences:
—Read/Write/Write—any time —Read/Write ‘1’—When writing the address or writ-
ing data.
SYMBOL TABLE
WAVEFORM INPUTS OUTPUTS
Must be steady
May change from LOW to HIGH
May change from HIGH to LOW
Don’t Care: Changes Allowed
N/A Center Line
Will be steady
Will change from LOW to HIGH
Will change from HIGH to LOW
Changing: State Not Known
is High Impedance
4
µ
µ
µ
X84256 Preliminary
—Write ‘1’—when reading data —Read/Read/Write ‘1’—after data is written to device,
but before entering the NV write sequence. —the device powers-up; —a nonvolatile write operation completes.
While a sequential read is in progress, the device remains in an active state. This state draws more current than the idle state, but not as much as during a read itself. To go back to the lowest pow er condition, an inv alid condition is created by writing a ‘1’ after the last bit of a read operation.
Write Protection
The following circuitry has been included to prevent inadvertent nonvolatile writes:
—A special “start nonvolatile write” command sequence
is required to start a nonvolatile write cycle.
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias......................–65°C to +135°C
Storage Temperature...........................–65°C to +150°C
T erminal V oltage with
Respect to V
.......................................–1V to +7V
SS
DC Output Current................................................... 5mA
Lead Temperature (Soldering, 10 seconds)..........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Military† –55°C +125°C
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci­fication is not implied. Exposure to absolute maximum rating conditions for e xtended periods ma y affect device reliability.
Supply Voltage Limits
X84256 5V ± 10% X84256 – 2.5 2.5V to 5.5V X84256 – 1.8 1.8V to 3.6V
D.C. OPERATING CHARACTERISTICS (V
= 5V ± 10%)
CC
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol Parameter
I
CC1
I
CC2
I
SB1
I
LI
I
LO
(1)
V
lL
(1)
V
IH
V
OL
V
OH
Notes: (1) V
V
Supply Current (Read) 1 mA OE = V
CC
V
Supply Current (Write)
CC
V
Standby Current
CC
3mA
1 Input Leakage Current 10 Output Leakage Current 10
V
Input LOW Voltage –0.5
V
Input HIGH Voltage
x 0.7 V
CC
CC CC
x 0.3
+ 0.5 Output LOW Voltage 0.4 V
V
Output HIGH Voltage
Min. and V
IL
Max. are f or reference only and are not tested.
IH
CC
– 0.8
Units Test ConditionsMin. Max.
, WE = V
IL
IH
,
I/O = Open, CE clocking @ 10MHz
During Nonvolatile Write Cycle
I
CC
All Inputs at CMOS Levels CE = V
A
V
A A
V
IN OUT
, Other Inputs = V
CC
= V
to V
SS
= V
to V
SS
CC
CC
CC
or V
SS
V V
I
= 2.1mA
OL
I
V
= –1mA
OH
5
X84256 Preliminary
D.C. OPERATING CHARACTERISTICS (V
= 2.5V to 5.5V)
CC
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol Parameter
Units Test Conditions
Min. Max.
I
CC1
I
CC2
I
SB1
I
LI
I
LO
(1)
V
lL
(1)
V
IH
V
OL
V
OH
D.C. OPERATING CHARACTERISTICS (V
VCC Supply Current (Read)
VCC Supply Current (Write) VCC Standby Current
1mA
3mA
A Input Leakage Current 10 µA Output Leakage Current 10 µA Input LOW Voltage –0.5
Input HIGH Voltage
VCC x 0.7 VCC + 0.5
VCC x 0.3
Output LOW Voltage 0.4 V Output HIGH Voltage
VCC – 0.4
= 1.8V to 3.6V)
CC
(Over the recommended operating conditions, unless otherwise specified.)
OE = VIL, WE = VIH, I/O = Open, CE clocking @ 5MHz
ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels
CE = VCC, Other Inputs = VCC or V VIN = VSS to V V
= VSS to V
OUT
CC
CC
V V
IOL = 1mA, VCC = 3V IOH = –400µA, VCC = 3V
V
SS
Symbol Parameter
I
CC1
I
CC2
I
SB1
I
LI
I
LO
(1)
V
lL
(1)
V
IH
V
OL
V
OH
Notes: (1) V
VCC Supply Current (Read)
VCC Supply Current (Write) VCC Standby Current
Input Leakage Current 10 µA Output Leakage Current 10 µA Input LOW Voltage –0.5
Input HIGH Voltage Output LOW Voltage 0.4 V Output HIGH Voltage
Min. and V
IL
Max. are f or reference only and are not tested.
IH
Limits
Min. Max.
500 µA
2mA
A
VCC x 0.3
VCC x 0.7 VCC + 0.5
VCC – 0.2
Units Test Conditions
OE = VIL, WE = VIH, I/O = Open, CE clocking @ 3MHz
ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels
CE = VCC, Other Inputs = VCC or V VIN = VSS to V V
= VSS to V
OUT
CC
CC
V V
IOL = 0.5mA, VCC = 2V IOH = –250µA, VCC = 2V
V
SS
6
X84256 Preliminary
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol Parameter Max. Units Test Conditions
(2)
C
I/O
(2)
C
IN
Notes: (2) Periodically sampled, but not 100% tested.
Input/Output Capacitance 8 pF Input Capacitance 6 pF
POWER-UP TIMING
Symbol Parameter Max. Units
(3)
t
PUR
t
PUW
(3)
Power-up to Read Operation 2 ms Power-up to Write Operation 5 ms
V
= 0V
I/O
VIN = 0V
Notes: (3) Time delays required from the time the VCC is stable until the specific operation can be initiated.
Periodically sampled, but not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels
VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 5ns Input and Output Timing Levels
VCC x 0.5
EQUIVALENT A.C. LOAD CIRCUITS
2.06K
OUTPUT
3.03K
5V
30pF
7008 FRM F06
2.39K
OUTPUT
4.58K
3V
OUTPUT
30pF
7008 FRM F07
2.8K
5.6K
2V
30pF
7
X84256 Preliminary
A.C. CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits – X84256
VCC = 5V±10% VCC = 2.5V – 5.5V VCC = 1.8V – 3.6V
Symbol Parameter
t
RC
t
CE
t
OE
t
OEL
t
OEH
t
LOW
t
HIGH
(4)
t
LZ
(4)
t
HZ
t
OLZ
t
OHZ
t
OH
t
WES
t
WEH
Notes: (4) Periodically sampled, but not 100% tested. tHZ and t
Read Cycle Time 100 200 330 ns CE Access Time 25 50 70 ns OE Access Time 25 50 70 ns OE Pulse Width 50 60 90 ns OE High Recovery Time 50 60 90 ns CE LOW Time 50 70 90 ns CE HIGH Time 50 120 180 ns CE LOW to Output In Low Z 0 0 0 ns
CE HIGH to Output In High Z 0 25 0 30 0 35 ns
(4)
OE LOW to Output In Low Z 0 0 0 ns
(4)
OE HIGH to Output In High Z 0 25 0 30 0 35 ns Output Hold from CE or OE HIGH 0 0 0 ns WE HIGH Setup Time 25 25 25 ns WE HIGH Hold Time 25 25 25 ns
first) to the time when I/O is no longer being driven into a 5pF load.
are measured from the point where CE or OE goes HIGH (whichever occurs
OHZ
UnitsMin. Max Min. Max. Min. Max.
CE
WE
OE
I/O
t
WES
t
RC
t
LOW
t
CE
t
OEL
t
OE
DATA
t
t t
OLZ LZ
OH
8
t
HIGH
t
WEH
t
OHZ
t
HZ
t
OEH
HIGH Z
X84256 Preliminary
Write Cycle Limits – X84256
Symbol Parameter
(5)
t
NVWC
t
WC
t
WP
t
WPH
t
CS
t
CH
t
CP
t
CPH
t
OES
t
OEH
(6)
t
DS
(6)
t
DH
t
WPSU
t
WPHD
Nonvolatile Write Cycle Time 5 5 5 ms Write Cycle Time 100 200 330 ns
WE Pulse Width 25 40 70 ns WE HIGH Recovery Time 65 150 200 ns Write Setup Time 0 0 0 ns Write Hold Time 0 0 0 ns CE Pulse Width 25 40 70 ns CE HIGH Recovery Time 65 150 200 ns OE HIGH Setup Time 25 25 50 ns OE HIGH Hold Time 25 25 50 ns Data Setup Time 12 20 30 ns
Data Hold Time 5 5 5 ns
(7)
WP HIGH Setup 100 100 150 ns
(7)
WP HIGH Hold 100 100 150 ns
VCC = 5V ±10% VCC = 2.5V – 5.5V VCC = 1.8V – 3.6V
Units
Min. Max. Min. Max. Min. Max.
Notes: (5) t
(6) Data is latched into the X84256 on the rising edge of CE or WE, whichev er occurs first.
(7) Periodically sampled, but not 100% tested.
is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write cycle”
NVWC
sequence until the self-timed, internal nonvolatile write cycle is completed.
9
X84256 Preliminary
CE Controlled Write Cycle
t
CPH
t
CP
CE
OE
WE
WP
I/O
WE Controlled Write Cycle
CE
t
WPSU
t
OES
t
OES
t
CS
t
t
t
DS
CP
WP
t
OEH
t
CH
t
WPHD
DATA
t
WC
t
WPH
t
DH
HIGH Z
t
CPH
OE
WE
WP
I/O
t
WPSU
t
CS
t
t
DS
WP
t
CH
t
OEH
DATA
t
WC
t
WPH
t
WPHD
t
DH
HIGH Z
10
X84256 Preliminary
PACKAGING INFORMATION
8-LEAD XBGA
X84256: Bottom View
D1
V
I/O
B
CE
V
SS
e
A
WP
CC
NC
C
WE
OE
D
D
E
A1
E
A1
NOTE: ALL DIMENSIONS IN µM
ALL DIMENSIONS ARE TYPICAL VALUES
11
X84256 Preliminary
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
PIN 1 INDEX
(4X) 7°
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
X 45°
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
0.150 (3.80)
0.158 (4.00)
0.004 (0.19)
0.010 (0.25)
0.228 (5.80)
0.244 (6.20)
0.053 (1.35)
0.069 (1.75)
0.050"TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.250"
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
12
0.050" TYPICAL
0.030"
TYPICAL
8 PLACES
X84256 Preliminary
16-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
PIN 1 INDEX
(4X) 7°
0.050 (1.27)
PIN 1
0.010 (0.25)
0.020 (0.50)
X 45°
0.014 (0.35)
0.020 (0.51)
0.386 (9.80)
0.394 (10.01)
0.150 (3.80)
0.158 (4.00)
0.004 (0.19)
0.010 (0.25)
0.228 (5.80)
0.244 (6.20)
0.053 (1.35)
0.069 (1.75)
0.050" Typical
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.250"
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
0.030" Typical 16 Places
0.050"
Typical
X84256 Preliminary
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
0° – 8°
.0075 (.19)
.0118 (.30)
.193 (4.9) .200 (5.1)
.019 (.50) .029 (.75)
DetailA (20X)
.169 (4.3) .177 (4.5)
.047 (1.20)
.002 (.05) .006 (.15)
.010 (.25)
Seating Plane
.252 (6.4) BSC
Gage Plane
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14
X84256 Preliminary
ORDERING INFORMATION
Device
*PART MARK CONVENTION 14-Lead TSSOP
YWW
84256
F = 2.5 to 5.5V, 0 to +70°C G = 2.5 to 5.5V, -40 to +85°C Blank = 4.5 to 5.5V, 0 to +70°C I = 4.5 to 5.5V, -40 to +85°C
X84256 X X
–X
8-Lead SOIC
X84256 X
Blank = 8-Lead SOIC
XX
F = 2.5 to 5.5V, 0 to +70°C G = 2.5 to 5.5V, -40 to +85°C Blank = 4.5 to 5.5V, 0 to +70°C I = 4.5 to 5.5V, -40 to +85°C
VCC Range
Blank = 4.5V to 5.5V, 10 MHz
2.5 = 2.5V to 5.5V, 5 MHz
1.8 = 1.8V to 3.6V, 3MHz (contact factory)
Temperature Range
Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C
Military = –55°C to +125°C (contact factory)
Packages: X84256
S8 = 8-Lead SOIC S16 = 16-Lead SOIC V14 = 14-Lead TSSOP Z = 8-Lead XBGA
8-Lead XBGA
Complete Part Number Top Mark
X84256Z–2.5 X84256ZI–2.5
XABA XABB
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. F oreign patents and additional patents pending.
LIFE RELA TED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prev ent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its saf ety or effectiveness.
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