XICOR X4005S8I, X4005S8, X4005M8I, X4003S8I, X4003S8 Datasheet

REV 1.1.3 4/30/02

Characteristics subject to change without notice.

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X4003/X4005

CPU Supervisor

FEATURES

• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off

•Low V

CC

detection and reset assertion

—Five standard reset threshold voltages

nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V

—Adjust low V

CC

reset threshold voltage using

special programming sequence

—Reset signal valid to V

CC

= 1V

• Low power CMOS
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current

• 400kHz I

2

C interface

• 1.8V to 5.5V power supply operation

• Available packages
—8-lead SOIC
—8-lead MSOP

DESCRIPTION

These devices combine three popular functions, Power­on Reset Control, Watchdog Timer, and Supply Voltage
Supervision. This combination lowers system cost,
reduces board space requirements, and increases
reliability.

Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla­tor to stabilize before the processor can execute code.

The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select­able time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.

The device’s low V

CC

detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when V

CC

falls below the minimum V

CC

trip

point. RESET/RESET is asserted until V

CC

returns to
proper operating level and stabilizes. Five industry stan­dard V

TRIP

thresholds are available; however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh­old for applications requiring higher precision.

BLOCK DIAGRAM

Data

Register

Command

Decode &

Control

Logic

SDA

SCL

V

CC

Reset &

Watchdog

Timebase

Power on and

Generation

+

-

RESET (X4003)

Reset

Low Voltage

Control

Register

Watchdog Transition

Detector

WP

VCC Threshold

Reset logic

RESET (X4005)

V

TRIP

Watchdog

Timer Reset

X4003/X4005

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PIN CONFIGURATION

NC

V

SS

V

CC

SDA

SCL

3

2

4

1

6

7

5

8

NC

WP

RESET

8-Pin JEDEC SOIC, MSOP

PIN DESCRIPTION

Pin

(SOIC/DIP)

Pin

TSSOP

Pin

(MSOP) Name Function

1 3 NC No internal connections

2 4 NC No internal connections

3 5 2 RESET

/

RESET

Reset Output .

RESET/RESET is an active LOW/HIGH, open

drain output which goes active whenever V

CC

falls below the

minimum V

CC

sense level. It will remain active until V

CC

rises

above the minimum V

CC

sense level for 250ms. RESET/
RESET goes active if the watchdog timer is enabled and SDA
remains either HIGH or LOW longer than the selectable
Watchdog time out period. A falling edge of SDA, while SCL
also toggles from HIGH to LOW followed by a stop condition
resets the watchdog timer. RESET

/RESET goes active on
power up and remains active for 250ms after the power supply
stabilizes.

463V

SS

Ground

5 7 4 SDA

Serial Data. SDA is a bidirectional pin used to transfer data

into and out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector outputs.
This pin requires a pull up resistor and the input buffer is
always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA while

SCL also toggles from HIGH to LOW follow by a stop condition
resets the watchdog timer. The absence of this procedure with­in the watchdog time out period results in RESET

/RESET going

active.

6 8 5 SCL

Serial Clock. The serial clock controls the serial bus timing for

data input and output.

716WP

Write Protect. WP HIGH prevents changes to the watchdog timer

setting.

821V

CC

Supply voltage

X4003/X4005

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PRINCIPLES OF OPERATION

Power On Reset

Application of power to the X4003/X4005 activates a
power on reset circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.

– It prevents the system microprocessor from starting

to operate with insufficient voltage.

– It prevents the processor from operating prior to

stabilization of the oscillator.

– It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

When V

CC

exceeds the device V

TRIP

threshold value
for 200ms (nominal) the circuit releases RESET/
RESET, allowing the system to begin operation.

Low Voltage Monitoring

During operation, the X4003/X4005 monitors the V

CC

level and asserts RESET/RESET if supply voltage falls
below a preset minimum V

TRIP

. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET

signal remains active until the voltage drops below 1V.
It also remains active until V

CC

returns and exceeds

V

TRIP

for 200ms.

Watchdog Timer

The watchdog timer circuit monitors the microproces­sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre­vent a RESET/RESET signal. The state of two nonvol­atile control bits in the control register determine the
watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.

Figure 1. Watchdog Restart

SCL

SDA

.6µs

.6µs

Start
Condition

Stop
Condition

Restart

Set V

TRIP

Level Sequence (V

CC

= desired V

TRIP

value)

012 4567

SCL

SDA

A0h

01234567

01h

WP

V

P

= 15-18V

01234567

00h

3

V

CC

THRESHOLD RESET PROCEDURE

The X4003/X4005 is shipped with a standard V

CC

threshold (V

TRIP

) voltage. This value will not change
over normal operating and storage conditions. How­ever, in applications where the standard V

TRIP

is not
exactly right, or if higher precision is needed in the
V

TRIP

value, the X4003/X4005 threshold may be
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.

Setting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a higher

voltage value. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

is 4.6V, this procedure will directly
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.

X4003/X4005

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To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold voltage to the V

CC

pin and tie the WP pin to

the programming voltage V

P

. Then write data 00hto
address 01h. The stop bit following a valid write operation
initiates the V

TRIP

programing sequence. Bring WP

LOW to complete the operation.

Resetting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a “native”

voltage level. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

must be 4.0V, then the V

TRIP

must

be reset. When V

TRIP

is reset, the new V

TRIP

is some­thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.

To reset the new V

TRIP

voltage, apply the desired

V

TRIP

threshold voltage to the V

CC

pin and tie the WP

pin to the programming voltage V

P

. Then write 00h to
address 03h. The stop bit of a valid write operation ini­tiates the V

TRIP

programming sequence. Bring WP

LOW to complete the operation.

Figure 2. Reset V

TRIP

Level Sequence (V

CC

> 3V. WP = 15-18V)

Figure 3. Sample V

TRIP

Reset Circuit

01234567

SCL

SDA

A0h

01234567

03h

WP

V

P

= 15-18V

01234567

00h

1

2
3

4

8

7
6

5

X4003/05

V

TRIP

Adj.

V

P

RESET/

4.7K

SDA

SCL

µC

Adjust

Run

RESET

X4003/X4005

Characteristics subject to change without notice.

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Figure 4. V

TRIP

Programming Sequence

V

TRIP

Programming

Apply 5V to V

CC

Decrement V

CC

RESET pin

goes active?

Measured V

TRIP

-

Desired V

TRIP

DONE

Execute

Sequence

Reset V

TRIP

Set VCC = VCC Applied =

Desired V

TRIP

Execute

Sequence

Set V

TRIP

New VCC Applied =

Old V

CC

applied + Error

(VCC = VCC–50mV)

Execute

Sequence

Reset V

TRIP

New VCC Applied =

Old V

CC

Applied - Error

Error ≤ –Emax

-Emax < Error < Emax

YES

NO

Error ≥ Emax

Emax = Maximum Allowable V

TRIP

Error

Control Register

The control register provides the user a mechanism for
changing the watchdog timer settings. watchdog timer
bits are nonvolatile and do not change when power is
removed.

The control register is accessed with a special pream­ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a control
register write operation. Only one data byte is allowed
for each register write operation. Prior to writing to the

control register, the WEL and RWEL bits must be set
using a two step process, with the whole sequence
requiring 3 steps. See "Writing to the Control Register"
below.

The user must issue a stop after sending the control
byte to the register to initiate the nonvolatile cycle that
stores WD1 and WD0. The X4003/X4005 will not
acknowledge any data bytes written after the first byte
is entered.

X4003/X4005

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The state of the control register can be read at any
time by performing a serial read operation. Only one
byte is read by each register read operation. The
X4003/X4005 resets itself after the first byte is read.
The master should supply a stop condition to be con­sistent with the bus protocol, but a stop is not required
to end this operation.

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the
control register.

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the control register
during a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL
bit is LOW, writes the control register will be ignored
(no acknowledge will be issued after the data byte).
The WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by writ­ing a “0” to the WEL bit and zeroes to the other bits of
the control register) or until the part powers up again.
Writes to the WEL bit do not cause a nonvolatile write
cycle, so the device is ready for the next operation
immediately after the stop condition.

WD1, WD0: Watchdog Timer Bits

The bits WD1 and WD0 control the period of the watch­dog timer. The options are shown below.

Writing to the Control Register

Changing any of the nonvolatile bits of the control register
requires the following steps:

– Write a 02H to the control register to set the write

enable latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre­ceeded by a start and ended with a stop.)

– Write a 06H to the control register to set both the

register write enable latch (RWEL) and the WEL bit.
This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop.)

– Write a value to the control register that has all the

control bits set to the desired state. This can be rep­resented as 0xy0 0010 in binary, where xy are the
WD bits. (Operation preceeded by a start and ended
with a stop.) Since this is a nonvolatile write cycle it
will take up to 10ms to complete. The RWEL bit is
reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2
is set to ‘1’ in this third step (0xy0 0110) then the
RWEL bit is set, but the WD1 and WD0 bits remain
unchanged. Writing a second byte to the control reg­ister is not allowed. Doing so aborts the write opera­tion and returns a NACK.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write
operation.

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.

To illustrate, a sequence of writes to the device consist­ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits in the control register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.

SERIAL INTERFACE

Serial Interface Conventions

The device supports a bidirectional bus oriented proto­col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans­fers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.

76543 2 10

0 WD1 WD0 0 0 RWEL WEL 0

WD1 WD0 Watchdog Time Out Period

0 0 1.4 seconds

0 1 600 milliseconds

1 0 200 milliseconds

1 1 Disabled (factory setting)