X28C64
64K X28C64 8K x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
• 150ns Access Time
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS
—60mA Active Current Max.
—200µA Standby Current Max.
• Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 0.625 sec. Typical
—Effective Byte Write Cycle Time: 78µs Typical
• Software Data Protection
• End of Write Detection
—DATA Polling
—Toggle Bit
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The X28C64 is an 8K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable nonvolatile memories the X28C64 is a 5V only device. The
X28C64 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs.
The X28C64 supports a 64-byte page write operation,
effectively providing a 78µs/byte write cycle and enabling the entire memory to be typically written in 0.625
seconds. The X28C64 also features DATA and Toggle
Bit Polling, a system software support scheme used to
indicate the early completion of a write cycle. In addition, the X28C64 includes a user-optional software data
protection mode that further enhances Xicor’s hardware write protect capability.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
PIN CONFIGURATION
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
NC
1
A
2
12
A
3
7
A
4
6
A
5
5
A
6
4
A
7
3
A
8
2
A
9
1
A
10
0
I/O
11
0
I/O
12
1
I/O
13
2
V
14
SS
© Xicor, Inc. 1991, 1995 Patents Pending Characteristics subject to change without notice
3853-2.7 4/2/96 T0/C3/D2 NS
X28C64
28
27
26
25
24
23
22
21
20
19
18
17
16
15
3853 FHD F02
V
WE
NC
A
A
A
OE
A
CE
I/O
I/O
I/O
I/0
I/O
CC
8
9
11
10
A
5
6
6
A
5
7
A
4
8
A
3
9
A
2
10
A
1
11
A
0
12
NC
7
6
5
4
3
I/O
13
0
LCC
PLCC
A7A12NCNCVCCWE
4 3 2 1 32 31 30
X28C64
14 15 16 17 18 19 20
2
SS
V
NC
I/O3I/O4I/O
I/O1I/O
NC
29
A
28
A
27
A
26
NC
25
OE
24
A
23
CE
22
I/O
21
I/O
5
3853 FHD F03
TSOP
A
1
2
A
2
1
3
A
8
9
11
10
0
4
I/O
0
5
I/O
1
6
I/O
2
7
NC
I/O
I/O
I/O
I/O
I/O
8
SS
9
NC
10
3
11
4
12
5
13
6
14
7
15
CE
16
A
10
X28C64
3853 ILL F23.1
V
7
6
A
32
A
31
A
30
A
29
A
28
A
27
26
NC
25
NC
24
V
23
NC
22
WE
21
NC
20
A
19
A
18
A
17
OE
1
3
4
5
6
7
12
CC
8
9
11
X28C64
PIN DESCRIPTIONS
Addresses (A0–A12)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
PIN NAMES
Symbol Description
A0–A
12
I/O0–I/O
7
Address Inputs
Data Input/Output
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
V
SS
+5V
Ground
NC No Connect
3853 PGM T01
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C64 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C64.
PIN CONFIGURATION
PGA
I/O
I/O
I/O
I/O
I/O
CE
OE
A
WE
I/O
5
6
18
I/O
4
7
19
A
10
21
A
11
23
A
9
8
25
NC
26
3853 FHD F04
1
2
12
13
I/O
A
0
10
1
8
3
6
5
2
6
3
0
A
2
A
4
A
12
A
7
BOTTOM VIEW
11
A
9
A
7
A
5
A
4
15
V
SS
14
X28C64
V
CC
28
NC
1
3
17
16
20
22
24
27
FUNCTIONAL DIAGRAM
ADDRESS
A0–A
12
INPUTS
CE
OE
WE
V
V
CC
SS
X BUFFERS
LATCHES AND
DECODER
Y BUFFERS
LATCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
65,536-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0–I/O
7
DATA INPUTS/OUTPUTS
3853 FHD F01
2
X28C64
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C64 supports both a CE
and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C64 allows the entire
memory to be written in 0.625 seconds. Page write
allows two to sixty-four bytes of data to be consecutively
written to the X28C64 prior to the commencement of the
internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A6 through A12) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to sixty-three bytes in the
same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28C64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
5TBDP 43210I/O
RESERVED
TOGGLE BIT
DATA POLLING
3853 FHD F11
DATA Polling (I/O7)
The X28C64 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C64,
eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data. Note: If the
X28C64 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
Toggle Bit (I/O6)
The X28C64 also provides another method for determining when the internal write cycle is complete. During
the internal programming cycle I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3
X28C64
DATA Polling I/O
7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
A0–A
I/O
IH
7
An An An An An An
12
HIGH Z
Figure 3. DATA Polling Software Flow
WRITE DATA
V
OH
V
OL
An
X28C64
READY
3853 FHD F12
DATA Polling can effectively halve the time for writing to
the X28C64. The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3 illustrates one method of implementing the routine.
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
COMPARE?
YES
X28C64
READY
NO
NO
3853 FHD F13
4
X28C64
The Toggle Bit I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
I/O
6
* Beginning and ending state of I/O6 will vary.
V
*
Figure 5. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
OH
HIGH Z
V
OL
*
X28C64
READY
3853 FHD F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C64 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
X28C64
READY
NO
3853 FHD F15
5
X28C64
HARDWARE DATA PROTECTION
The X28C64 provides three hardware features (compatible with X2864A) that protect nonvolatile data from
inadvertent writes.
• Noise Protection—A WE pulse typically less than
20ns will not initiate a write cycle.
• Default V
when VCC is ≤3V typically.
Sense—All write functions are inhibited
CC
• Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28C64 offers a software controlled data protection
feature. The X28C64 is shipped from Xicor with the
software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once VCC was stable.
The X28C64 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.
Once the software protection is enabled, the X28C64 is
also protected from inadvertent and accidental writes in
the powered-on state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to sixty-four bytes of
data*. Once the page load cycle has been completed,
the device will automatically be returned to the data
protected state.
Note: *Once the three-byte sequence is issued it must be
followed by a valid byte or page write operation.
6
X28C64
Software Data Protection
Figure 6. Timing Sequence—Byte or Page Write
V
CC
0V
DATA
ADDRESSAA1555
CE
WE
55
0AAA
Figure 7. Write Sequence for Software Data
Protection
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
A0
1555
≤t
BLC MAX
(VCC)
t
WPH2
WRITES
OK
BYTE
OR
PAGE
t
WC
WRITE
PROTECTED
3853 FHD F16
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the X28C64
will automatically disable further writes unless another
command is issued to cancel it. If no further commands
are issued the X28C64 will be write protected during
power-down and after any subsequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
1555
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
PROTECTED STATE
WC
BYTE/PAGE
LOAD ENABLED
3853 FHD F17
3853 FHD F17
7
X28C64
Resetting Software Data Protection
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
DATA
ADDRESSAA1555
CE
WE
55
0AAA
80
1555
Figure 9. Software Sequence to Deactivate
Software Data Protection
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 80
TO ADDRESS
1555
AA
1555
55
0AAA
20
1555
≥t
WC
STANDARD
OPERATING
MODE
3853 FHD F18.1
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC,
the X28C64 will be in standard operating mode.
Note: Once initiated, the sequence of write opera-
tions should not be interrupted.
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 20
TO ADDRESS
1555
3853 ILL F19.2
8
X28C64
SYSTEM CONSIDERATIONS
Because the X28C64 is frequently used in large memory
arrays, it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28C64 has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and
VSS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
9
X28C64
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X28C64........................................ –10°C to +85°C
X28C64I, X28C64M................... –65°C to +135°C
Storage Temperature .......................–65°C to +150°C
Voltage on any Pin with
Respect to V
.......................................
SS
–1V to +7V
D.C. Output Current .............................................5mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Supply Voltage Limits
X28C64 5V ±10%
3853 PGM T03.1
Military –55°C +125°C
3853 PGM T02.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified)
Limits
Symbol Parameter Min. Typ.
I
CC
VCC Current (Active) 30 60 mA CE = OE = VIL, WE = VIH, All
(1)
Max. Units Test Conditions
(TTL Inputs) I/O’s = Open, Address Inputs =
0.4V/2.4V Levels @ f = 5MHz
I
SB1
I
SB2
VCC Current (Standby) 1 2 mA CE = VIH, OE = V
IL
(TTL Inputs) All I/O’s = Open, Other Inputs = V
VCC Current (Standby) 100 200 µA CE = WE = VCC – 0.3V
IH
(CMOS Inputs) All I/O’s = Open,
Other Inputs = Don’t Care
I
LI
I
LO
V
lL
V
IH
V
OL
V
OH
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage and are not tested.
Input Leakage Current 10 µAVIN = VSS to V
Output Leakage Current 10 µAV
(2)
Input LOW Voltage –1 0.8 V
(2)
Input HIGH Voltage 2 VCC + 1 V
Output LOW Voltage 0.4 V IOL = 2.1mA
Output HIGH Voltage 2.4 V IOH = –400µA
(2) VIL min. and VIH max. are for reference only and are not tested.
CC
= VSS to VCC, CE = V
OUT
IH
3853 PGM T04.2
10
X28C64
ENDURANCE AND DATA RETENTION
Parameter Min. Units
Minimum Endurance 100,000 Cycles
Data Retention 100 Years
POWER-UP TIMING
Symbol Parameter Typ.
(3)
t
PUR
t
PUW
(3)
Power-up to Read Operation 100 µs
Power-up to Write Operation 5 ms
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol Parameter Max. Units Test Conditions
(3)
C
I/O
(3)
C
IN
Input/Output Capacitance 10 pF V
Input Capacitance 6 pF V
(1)
Units
I/O
IN
3853 PGM T05.1
3853 PGM T06
= 0V
= 0V
3853 PGM T07.1
A.C. CONDITIONS OF TEST
Input Pulse Levels 0V to 3V
Input Rise and
Fall Times 10ns
Input and Output
Timing Levels 1.5V
3853 PGM T08.1
EQUIVALENT A.C. LOAD CIRCUIT
5V
1.92KΩ
OUTPUT
1.37KΩ
100pF
3853 FHD F20.3
MODE SELECTION
CE OE WE Mode I/O Power
L L H Read D
L H L Write D
OUT
IN
Active
Active
H X X Standby and High Z Standby
Write Inhibit
X L X Write Inhibit — —
X X H Write Inhibit — —
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
3853 PGM T09
Note: (3) This parameter is periodically sampled and not 100% tested.
11
X28C64
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28C64-15 X28C64-20 X28C64-25
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
t
RC
t
CE
t
AA
t
OE
(4)
t
LZ
(4)
t
OLZ
(4)
t
HZ
(4)
t
OHZ
t
OH
Read Cycle
ADDR.
CE
OE
Read Cycle Time 150 200 250 ns
Chip Enable Access Time 150 200 250 ns
Address Access Time 150 200 250 ns
Output Enable Access Time 70 80 100 ns
CE LOW to Active Output 0 0 0 ns
OE LOW to Active Output 0 0 0 ns
CE HIGH to High Z Output 50 50 50 ns
OE HIGH to High Z Output 50 50 50 ns
Output Hold from Address Change 0 0 0 ns
3856 PGM T10.1
t
RC
t
CE
t
OE
V
WE
DATA I/O
Notes: (4) tLZ min.,tHZ, t
IH
HIGH Z
CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
min., and t
OLZ
t
OLZ
t
LZ
DATA VALID
are periodically sampled and not 100% tested. tHZ max. and t
OHZ
12
t
OH
t
AA
t
HZ
DATA VALID
max. are measured, with
OHZ
t
OHZ
3853 FHD F05
X28C64
WRITE CYCLE LIMITS
Symbol Parameter Min.
(5)
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW
t
OES
t
OEH
t
WP
t
WPH
(6)
t
WPH2
t
DV
t
DS
t
DH
t
DW
(7)
t
BLC
WE Controlled Write Cycle
Write Cycle Time 5 10 ms
Address Setup Time 0 ns
Address Hold Time 100 ns
Write Setup Time 0 ns
Write Hold Time 0 ns
CE Pulse Width 100 ns
OE HIGH Setup Time 10 ns
OE HIGH Hold Time 10 ns
WE Pulse Width 100 ns
WE HIGH Recovery 200 ns
SDP WE Recovery 1 µs
Data Valid 1 µs
Data Setup 50 ns
Data Hold 10 ns
Delay to Next Write 10 µs
Byte Load Cycle 1 100 µs
(7)
Typ.
(1)
Max. Units
3853 PGM T11.1
t
WC
ADDRESS
t
AS
t
CS
CE
OE
WE
DATA IN
DATA OUT
Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
(6) t
(7) For faster tWC and t
is the normal page write operation WE recovery time. t
WPH
the three-byte SDP command sequence and before writing the first byte of data to the array. Refer to Figure 6 which illustrates
the t
WPH2
requirement.
t
OES
t
DV
times, refer to X28HC64.
BLC
t
AH
t
WP
t
OEH
DATA VALID
t
DS
WPH2
t
CH
t
DH
HIGH Z
3853 FHD F06
is the WE recovery time needed only after the end of issuing
13
X28C64
CE Controlled Write Cycle
ADDRESS
CE
t
OES
t
AS
t
AH
t
CW
t
WC
OE
WE
DATA IN
DATA OUT
Page Write Cycle
(8)
OE
CE
WE
t
WP
t
CS
t
DV
t
WPH
t
BLC
t
DS
HIGH Z
t
OEH
DATA VALID
t
t
CH
DH
3853 FHD F07
ADDRESS *
Notes: (8) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
(9)
I/O
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
*For each successive write within the page write operation, A6–A12 should be the same or
writes to an unknown address could occur.
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(9) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the CE or WE controlled write cycle timing.
LAST BYTE
t
WC
3853 FHD F08
14
X28C64
DATA Polling Timing Diagram
ADDRESS
CE
WE
OE
I/O
7
Toggle Bit Timing Diagram
CE
A
N
DIN=X D
(10)
(10)
t
OEH
A
N
=X D
OUT
t
WC
A
N
t
OES
t
DW
=X
OUT
3853 FHD F09
WE
t
OEH
OE
I/O
6
* Starting and ending state of I/O
Note: (10) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
HIGH Z
*
t
WC
will vary, depending upon actual t
.
*
t
t
DW
OES
3853 FHD F10
15
X28C64
NOTES
16
X28C64
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
PIN 1 INDEX
PIN 1
1.460 (37.08)
1.400 (35.56)
1.300 (33.02)
REF.
0.550 (13.97)
0.510 (12.95)
0.085 (2.16)
0.040 (1.02)
0.160 (4.06)
0.125 (3.17)
SEATING
PLANE
0.150 (3.81)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
TYP. 0.010 (0.25)
0.062 (1.57)
0.050 (1.27)
0.610 (15.49)
0.590 (14.99)
0.030 (0.76)
0.015 (0.38)
0.020 (0.51)
0.016 (0.41)
0°
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
17
X28C64
PACKAGING INFORMATION
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
PIN 1
1.490 (37.85)
1.435 (36.45)
1.30 (33.02)
REF.
0.610 (15.49)
0.500 (12.70)
0.100 (2.54)
0.035 (0.89)
SEATING
PLANE
0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
TYP. 0.100 (2.54)
TYP. 0.010 (0.25)
0.070 (1.78)
0.030 (0.76)
TYP. 0.055 (1.40)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0.225 (5.72)
0.140 (3.56)
0.060 (1.52)
0.015 (0.38)
0.026 (0.66)
0.014 (0.36)
TYP. 0.018 (0.46)
0°
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
18
X28C64
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
TYP. 0.490 (12.45)
TYP. 0.450 (11.43)
0.420 (10.67)
0.495 (12.57)
0.485 (12.32)
0.453 (11.51)
0.447 (11.35)
0.300 (7.62)
REF.
0.050 (1.27) TYP.
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)0.045 (1.14) x 45°
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.015 (0.38)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
TYP. 0.136 (3.45)
0.048 (1.22)
0.042 (1.07)
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
19
X28C64
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.1040 (2.6416)
0.0940 (2.3876)
0.0192 (0.4877)
0.0138 (0.3505)
0.7080 (17.9832)
0.7020 (17.8308)
0.050 (1.270)
BSC
0.0160 (0.4064)
0.0100 (0.2540)
X 45°
0.2980 (7.5692)
0.2920 (7.4168)
0.0110 (0.2794)
0.0040 (0.1016)
0.4160 (10.5664)
0.3980 (10.1092)
BASE PLANE
SEATING PLANE
0° – 8°
0.0350 (0.8890)
0.0160 (0.4064)
0.0125 (0.3175)
0.0090 (0.2311)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3. BACK EJECTOR PIN MARKED “KOREA”
4. CONTROLLING DIMENSION: INCHES (MM)
3926 FHD F17
20
X28C64
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.150 (3.81) BSC
PIN 1
0.020 (0.51) x 45° REF.
0.095 (2.41)
0.075 (1.91)
0.022 (0.56)
0.006 (0.15)
0.200 (5.08)
BSC
0.028 (0.71)
0.022 (0.56)
(32) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.442 (11.22)
0.458 (11.63)
––
0.300 (7.62)
BSC
0.055 (1.39)
0.045 (1.14)
TYP. (4) PLCS.
0.040 (1.02) x 45° REF.
TYP. (3) PLCS.
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
0.120 (3.05)
0.060 (1.52)
0.558 (14.17)
––
0.088 (2.24)
0.050 (1.27)
PIN 1 INDEX CORDER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
21
3926 FHD F14
X28C64
PACKAGING INFORMATION
28-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
12 13 15 17 18
11 10 14 16 19
9 8 20 21
A
0.008
0.660 (16.76)
0.640 (16.26)
7 6 22 23
5 2 28 24 25
4 3 1 27 26
TYP. 0.100
ALL LEADS
PIN 1 INDEX
0.080
0.070
A
NOTE: LEADS 4,12,18 & 26
4 CORNERS
0.080
0.070
0.100
0.080
0.072
0.061
A
0.050
0.020
0.016
A
0.561 (14.25)
0.541 (13.75)
0.185 (4.70)
0.175 (4.44)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F15
22
X28C64
PACKAGING INFORMATION
28-LEAD CERAMIC FLAT PACK
0.740 (18.80)
MAX.
0.006 (0.15)
0.003 (0.08)
0.370 (9.40)
0.250 (6.35)
TYP. 0.300 2 PLCS.
0.030 (0.76)
MIN.
PIN 1 INDEX
128
0.440 (11.18)
MAX.
0.180 (4.57)
MIN.
0.019 (0.48)
0.015 (0.38)
0.050 (1.27) BSC
0.045 (1.14) MAX.
0.130 (3.30)
0.090 (2.29)
0.045 (1.14)
0.025 (0.66)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
23
3926 FHD F16
X28C64
PACKAGING INFORMATION
SEE NOTE 2
8.02 (0.315)
7.98 (0.314)
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
SEE NOTE 2
12.50 (0.492)
12.30 (0.484)
PIN #1 IDENT.
O 0.76 (0.03)
0.50 (0.0197) BSC
0.26 (0.010)
0.14 (0.006)
1.18 (0.046)
1.02 (0.040)
FOOTPRINT
0.58 (0.023)
0.42 (0.017)
SOLDER PADS
14.15 (0.557)
13.83 (0.544)
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
TYPICAL
32 PLACES
0.17 (0.007)
0.03 (0.001)
1.30 ± 0.05
(0.051 ± 0.002)
0.17 (0.007)
0.03 (0.001)
SEATING
PLANE
15 EQ. SPC. 0.50 ± 0.04
0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.50 ± 0.04
(0.0197 ± 0.0016)
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
24
3926 ILL F38.1
X28C64
ORDERING INFORMATION
X28C64 X X -X
Device
Access Time
–15 = 150ns
–20 = 200ns
–25 = 250ns
Blank = 300ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
S = 28-Lead Plastic SOIC
E = 32-Pad LCC
K = 28-Pin Pin Grid Array
F = 28-Lead Flat Pack
T = 32-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
25
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