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X28C512/X28C513
512K X28C512/X28C513 64K x 8 Bit
2
5 Volt, Byte Alterable E
PROM
FEATURES
• Access Time: 90ns
• Simple Byte and Page Write
—Single 5V Supply
— No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
—Active: 50mA
—Standby: 500µA
• Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
• Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
PIN CONFIGURATIONS
1
A
11
2
A
9
3
A
8
4
A
13
5
A
14
6
NC
7
NC
8
NC
9
WE
10
V
CC
11
NC
12
NC
13
NC
14
NC
15
A
15
16
A
12
17
A
7
18
A
6
19
A
5
20
A
4
NC
NC
A
15
A
12
A
A
A
A
A
A
A
A
I/O
I/O
I/O
V
SS
1
2
3
4
5
7
6
6
7
5
8
4
9
3
10
2
11
1
12
0
13
0
14
1
15
2
16
PLASTIC DIP
CERDIP
FLAT PACK
SOIC (R)
X28C512
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3856 FHD F01
V
WE
NC
A
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/0
I/O
CC
14
13
8
9
11
10
7
6
5
4
3
TSOP
X28C512
I/O
I/O
0
2
15
17
A
A
13
A
12
A
10
A
8
A
6
I/O
0
1
2
4
6
12
1
14
16
A
3
11
A
5
9
A
7
7
A
15
5
2NC36
4NC3NC1NC35WE33
• Two PLCC and LCC Pinouts
—X28C512
—X28C010 E2PROM Pin Compatible
—X28C513
—Compatible with Lower Density E2PROMs
DESCRIPTION
The X28C512/513 is an 64K x 8 E2PROM, fabricated
with Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable nonvolatile memories the X28C512/513 is a 5V only device.
The X28C512/513 features the JEDEC approved pinout
for bytewide memories, compatible with industry standard EPROMS.
The X28C512/513 supports a 128-byte page write operation, effectively providing a 39µs/byte write cycle and
enabling the entire memory to be written in less than 2.5
seconds. The X28C512/513 also features DATA Polling
and Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C512/513 supports the Software Data
Protection option.
PLCC / LCC
40
PGA
I/O
19
V
18
BOTTOM
VIEW
V
OE
39
A
10
38
CE
37
I/O
7
36
I/O
6
35
I/O
5
34
I/O
4
33
I/O
3
32
NC
31
NC
30
V
SS
29
NC
28
NC
27
I/O
2
26
I/O
1
25
I/O
0
24
A
0
23
A
1
22
A
2
21
A
3
3856 ILL F22
I/O
I/O
3
5
6
21
22
I/O
SS
20
NC
CC
34
CE
I/O
4
7
23
24
OE
A
10
25
26
A
A
11
9
27
28
A
A
8
13
29
30
NC
A
14
32
31
NC
3856 FHD F02
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
A12A15NCNCVCCWE
232
43
5
6
7
8
X28C512
9
(TOP VIEW)
10
11
12
13
15 1716 18 19 20
14
2
SS
I/O1I/O
V
A7A12A14A15VCCWE
232
43
5
6
7
8
X28C513
9
(TOP VIEW)
10
11
12
13
15 1716 18 19 20
14
2
SS
I/O1I/O
V
1
I/O3I/O4I/O5I/O
1
NC
31
29
28
27
26
25
24
23
22
31
29
28
27
26
25
24
23
22
I/O3I/O4I/O
NC
30
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
21
6
3856 FHD F03
13
A
30
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
I/O
21
5
3856 FHD F04
7
7
6
© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
3856-3.2 8/5/97 T1/C0/D0 EW
1
X28C512/X28C513
PIN DESCRIPTIONS
Addresses (A0–A15)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C512/513 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C512/513.
FUNCTIONAL DIAGRAM
PIN NAMES
Symbol Description
A0–A
15
I/O0–I/O
7
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
V
SS
NC No Connect
Address Inputs
Data Input/Output
+5V
Ground
3856 PGM T01
A7–A
A0–A
15
6
WE
V
V
CE
OE
CC
SS
X BUFFERS
LATCHES AND
DECODER
Y BUFFERS
LATCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
512K-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0–I/O
DATA INPUTS/OUTPUTS
7
3856 FHD F05
2
X28C512/X28C513
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C512/513 supports both
a CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms.
Page Write Operation
The page write feature of the X28C512/513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
be consecutively written to the X28C512/513 prior to the
commencement of the internal programming cycle. The
host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A7 through A15) for
each subsequent valid write cycle to the part during this
operation must be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Write Operation Status Bits
The X28C512/513 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
5
TBDP 43210I/O
RESERVED
TOGGLE BIT
DATA POLLING
3856 FHD F06
DATA Polling (I/O7)
The X28C512/513 features DATA Polling as a method
to indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C512/
513, eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data.
Toggle Bit (I/O6)
The X28C512/513 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O6 will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3
X28C512/X28C513
DATA Polling I/O
7
Figure 2a. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
A0–A
I/O
IH
7
An An An An An An
15
HIGH Z
Figure 2b. DATA Polling Software Flow
WRITE DATA
V
OH
V
OL
An
X28C512/513
READY
3856 FHD F07.1
DATA Polling can effectively halve the time for writing to
the X28C512/513. The timing diagram in Figure 2a
illustrates the sequence of events on the bus. The
software flow diagram in Figure 2b illustrates one method
of implementing the routine.
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
COMPARE?
YES
X28C512
READY
NO
NO
3856 FHD F08
4
X28C512/X28C513
The Toggle Bit I/O
6
Figure 3a. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
I/O
6
* Beginning and ending state of I/O6 will vary.
OH
*
Figure 3b. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
HIGH Z
V
OL
*
X28C512/513
READY
3856 FHD F09.1
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C512/513 memories that is frequently updated. Toggle Bit Polling can also provide a method for
status checking in multiprocessor applications. The
timing diagram in Figure 3a illustrates the sequence of
events on the bus. The software flow diagram in Figure
3b illustrates a method for polling the Toggle Bit.
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
X28C512
READY
NO
3856 FHD F10
5
X28C512/X28C513
HARDWARE DATA PROTECTION
The X28C512/513 provides three hardware features
that protect nonvolatile data from inadvertent writes.
• Noise Protection—A WE pulse typically less than
10ns will not initiate a write cycle.
• Default VCC Sense—All write functions are inhibited
when VCC is ≤3.6V.
• Write Inhibit—Holding either OE LOW, WE HIGH,
or CE HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity. Write cycle timing specifications must be
observed concurrently.
SOFTWARE DATA PROTECTION
The X28C512/513 offers a software controlled data
protection feature. The X28C512/513 is shipped from
Xicor with the software data protection NOT ENABLED;
that is, the device will be in the standard operating mode.
In this mode data should be protected during power-up/
-down operations through the use of external circuits.
The host would then have open read and write access
of the device once VCC was stable.
The X28C512/513 can be automatically protected during power-up and power-down without the need for
external circuits by employing the software data protection feature. The internal software data protection circuit
is enabled after the first write operation utilizing the
software algorithm. This circuit is nonvolatile and will
remain set for the life of the device unless the reset
command is issued.
Once the software protection is enabled, the X28C512/
513 is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional data
to the device. Note: The data in the three-byte enable
sequence is not written to the memory array.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific addresses. Refer to Figure 4a and 4b for the sequence.
The three byte sequence opens the page write window
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle has
been completed, the device will automatically be returned to the data protected state.
6
X28C512/X28C513
Software Data Protection
Figure 4a. Timing Sequence—Software Data Protect Enable Sequence followed by Byte or Page Write
V
CC
0V
DATA
ADDR
CE
WE
NOTE: All other timings and control pins are per page write timing requirements.
AA
5555
55
2AAA
A0
5555
Figure 4b. Write Sequence for Software Data
Protection
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
≤t
BLC MAX
(VCC)
WRITES
OK
BYTE
OR
PAGE
t
WC
WRITE
PROTECTED
3856 FHD F11
Regardless of whether the device has previously been
protected or not, once the software data protected
algorithm is used and data has been written, the
X28C512/513 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28C512/513 will be
write protected during power-down and after any subsequent power-up. The state of A15 while executing the
algorithm is don’t care.
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
PROTECTED STATE
WC
Note: Once initiated, the sequence of write operations
should not be interrupted.
OPTIONAL
BYTE/PAGE
LOAD OPERATION
3856 FHD F12
7
X28C512/X28C513
Resetting Software Data Protection
Figure 5a. Reset Software Data Protection Timing Sequence
V
CC
DATA
ADDRAA5555
CE
WE
NOTE: All other timings and control pins are per page write timing requirements.
55
2AAA
80
5555
Figure 5b. Software Sequence to Deactivate
Software Data Protection
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
AA
5555
55
2AAA
20
5555
≥t
WC
STANDARD
OPERATING
MODE
3856 FHD F13
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC,
the X28C512/513 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
3856 FHD F14
8
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