X28C256
256K X28C256 32K x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
• Access Time: 200ns
• Simple Byte and Page Write
— Single 5V Supply
—No External High Voltages or VPP Control
Circuits
— Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
—Active: 60mA
—Standby: 200µA
• Software Data Protection
— Protects Data Against System Level
Inadvertent Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write
— Endurance: 100,000 Write Cycles
— Data Retention: 100 Years
™
Cell
• Early End of Write Detection
— DATA Polling
—Toggle Bit Polling
DESCRIPTION
The X28C256 is an 32K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable nonvolatile memories the X28C256 is a 5V only device. The
X28C256 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs.
The X28C256 supports a 64-byte page write operation,
effectively providing a 78µs/byte write cycle and enabling the entire memory to be typically written in less
than 2.5 seconds. The X28C256 also features DATA
and Toggle Bit Polling, a system software support
scheme used to indicate the early completion of a write
cycle. In addition, the X28C256 includes a user-optional
software data protection mode that further enhances
Xicor’s hardware write protect capability.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
PIN CONFIGURATION
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
A14
1
A
2
12
A
3
7
A
4
6
A
5
5
A
6
4
A
7
3
A
8
2
A
9
1
A
10
0
I/O
11
0
I/O
12
1
I/O
13
2
V
14
SS
X28C256
28
V
27
WE
26
A
25
A
24
A
23
A
22
OE
21
A
20
CE
19
I/O
18
I/O
17
I/O
16
I/0
15
I/O
3855 FHD F02
CC
13
8
9
11
10
4
LCC
PLCC
A7A12A14NC
4 3 2 1 32 31 30
5
A
6
6
A
5
7
A
4
8
A
3
A
2
A
1
A
0
NC
7
I/O
0
6
5
3
X28C256
9
10
11
12
13
14 15 16 17 18 19 20
2
SS
I/O1I/O
NC
V
13
VCCWE
A
29
28
27
26
25
24
23
22
21
5
I/O3I/O4I/O
3855 FHD F03
A
A
A
NC
OE
A
CE
I/O
I/O
A
1
2
A
2
1
A
3
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4
0
5
1
6
2
NC
7
8
SS
NC
9
10
3
11
4
12
5
13
6
14
7
15
CE
16
A
10
8
9
11
V
10
7
6
TSOP
X28C256
A
32
A
31
A
30
A
29
A
28
A
27
26
A
25
NC
24
V
23
NC
22
WE
21
A
20
A
19
A
18
A
17
OE
3855 ILL F23
3
4
5
6
7
12
14
CC
13
8
9
11
© Xicor, Inc. 1991, 1995 Patents Pending Characteristics subject to change without notice
3855-1.9 8/1/97 T1/C0/D8 EW
1
X28C256
X28C256
11
I/O
0
10
A
0
14
V
SS
9
A
1
8
A
2
7
A
3
6
A
4
5
A
5
2
A
12
28
V
CC
12
I/O
1
13
I/O
2
15
I/O
3
4
A
6
3
A
7
1
A
14
16
I/O
4
20
CE
22
OE
24
A
9
17
I/O
5
27
WE
19
I/O
7
21
A
10
23
A
11
25
A
8
18
I/O
6
26
A
13
BOTTOM VIEW
PIN DESCRIPTIONS
Addresses (A0–A14)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C256 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C256.
PIN NAMES
Symbol Description
A0–A
14
I/O0–I/O
7
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
V
SS
NC No Connect
PIN CONFIGURATION
Address Inputs
Data Input/Output
+5V
Ground
3855 PGM T01
PGA
FUNCTIONAL DIAGRAM
A0–A
14
ADDRESS
INPUTS
CE
OE
WE
V
V
CC
SS
X BUFFERS
LATCHES AND
DECODER
Y BUFFERS
LATCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
3855 FHD F04
256K-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0–I/O
7
DATA INPUTS/OUTPUTS
3855 FHD F01
2
X28C256
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C256 supports both a CE
and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C256 allows the entire
memory to be written in 2.5 seconds. Page write allows
two to sixty-four bytes of data to be consecutively written
to the X28C256 prior to the commencement of the
internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A6 through A14) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to sixty-three bytes in the
same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28C256 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
5TBDP 43210I/O
RESERVED
TOGGLE BIT
DATA POLLING
3855 FHD F11
DATA Polling (I/O7)
The X28C256 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C256,
eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data. Note: If the
X28C256 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
Toggle Bit (I/O6)
The X28C256 also provides another method for determining when the internal write cycle is complete. During
the internal programming cycle I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3
X28C256
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
A0–A
I/O
IH
7
An An An An An An
14
HIGH Z
Figure 3. DATA Polling Software Flow
WRITE DATA
V
OH
V
OL
An
X28C256
READY
3855 FHD F12
DATA Polling can effectively halve the time for writing to
the X28C256. The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3 illustrates one method of implementing the routine.
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
COMPARE?
YES
X28C256
READY
NO
NO
3855 FHD F13
4
X28C256
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
I/O
6
* Beginning and ending state of I/O6 will vary.
OH
*
Figure 5. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
HIGH Z
V
OL
*
X28C256
READY
3855 FHD F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C256 memories that is frequently updated.
The timing diagram in Figure 4 illustrates the sequence
of events on the bus. The software flow diagram in
Figure 5 illustrates a method for polling the Toggle Bit.
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
X28C256
READY
NO
3855 FHD F15
5
X28C256
HARDWARE DATA PROTECTION
The X28C256 provides three hardware features (compatible with X28C64) that protect nonvolatile data from
inadvertent writes.
• Noise Protection—A WE pulse typically less than
20ns will not initiate a write cycle.
• Default VCC Sense—All write functions are inhibited
when VCC is ≤3.5V typically.
• Write Inhibit—Holding either OE LOW, WE HIGH,
or CE HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
The X28C256 offers a software controlled data protection feature. The X28C256 is shipped from Xicor with the
software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once VCC was stable.
The X28C256 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.
Once the software protection is enabled, the X28C256
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
Software Algorithm
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to sixty-four bytes of
data.* Once the page load cycle has been completed,
the device will automatically be returned to the data
protected state.
*Note: Once the three-byte sequence is issued it
must be followed by a valid byte or page write
operation.
6
X28C256
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
V
CC
0V
DATA
ADDR.AA5555
CE
WE
Figure 7. Write Sequence for
Software Data Protection
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
55
2AAA
A0
5555
≤t
≤t
BLC MAX
BLC MAX
(VCC)
t
WPH2
WRITES
OK
BYTE
OR
PAGE
t
WC
WRITE
PROTECTED
3855 FHD F16
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the X28C256
will automatically disable further writes unless another
command is issued to cancel it. If no further commands
are issued the X28C256 will be write protected during
power-down and after any subsequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
PROTECTED STATE
WC
BYTE/PAGE
LOAD ENABLED
3855 FHD F17
7
X28C256
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
DATA
ADDR.AA5555
CE
WE
55
2AAA
Figure 9. Software Sequence to
Deactivate Software Data Protection
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
80
5555
AA
5555
55
2AAA
20
5555
≥t
WC
STANDARD
OPERATING
MODE
3855 FHD F18
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC,
the X28C256 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
3855 FHD F19
8
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