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X28C010
1M X28C010 128K x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
• Access Time: 120ns
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
—Active: 50mA
—Standby: 500µA
• Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
• Early End of Write Detection
DESCRIPTION
The Xicor X28C010 is a 128K x 8 E2PROM, fabricated
with Xicor's proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable nonvolatile memories the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pinout for bytewide memories, compatible with industry standard
EPROMs.
The X28C010 supports a 256-byte page write operation,
effectively providing a 19µs/byte write cycle and enabling the entire memory to be typically written in less
than 2.5 seconds. The X28C010 also features DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the X28C010 supports Software Data
Protection option.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Data retention is
specified to be greater than 100 years.
—DATA Polling
—Toggle Bit Polling
PIN CONFIGURATIONS
PLCC
LCC
CERDIP
FLAT PACK
SOIC (R)
NC
1
A
2
16
A
3
15
A
4
12
A
5
7
A
6
6
A
7
5
A
8
4
A
9
3
A
10
2
A
11
1
A
12
0
I/O
13
0
I/O
14
1
I/O
15
2
V
16
SS
© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
3858-3.1 4/3/97 T1/C0/D0 SH
X28C010
32
V
31
WE
30
NC
29
A
28
A
27
A
26
A
25
A
24
OE
23
A
22
CE
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
3858 FHD F02.1
CC
14
13
8
9
11
10
15
A
1
14
13
A
2
11
12
A
4
10
A
6
8
A
12
6
7
6
5
4
3
PGA
I/O
I/O
0
2
17
A
I/O
0
1
16
A
3
A
5
X28C010
9
(BOTTOM VIEW)
A
7
7
A
15
5
2NC36
A
16
4
3NC1NC35WE33
I/O
I/O
I/O
3
5
19
V
SS
18
V
CC
6
21
22
I/O
20
NC
34
CE
I/O
4
7
23
24
OE
A
10
25
26
A
A
11
9
27
28
A
A
8
13
29
30
NC
A
14
32
31
NC
3858 FHD F20
1
A12A15A16NC
43
A
5
7
6
A
6
7
A
5
A
8
4
9
A
3
A
10
2
11
A
1
12
A
0
13
I/O
0
14
I/O1I/O
A
11
A
9
A
8
A
13
A
14
NC
NC
NC
WE
V
CC
NC
NC
NC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
VCCWE
232
31
1
X28C010
(TOP VIEW)
15 1716 18 19 20
2
SS
I/O3I/O4I/O5I/O
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
30
29
A
14
28
A
13
27
A
8
26
A
9
25
A
11
24
OE
23
A
10
22
CE
I/O
7
21
6
TSOP
X28C010
EXTENDED LCC
A12A15A16NC
43
A
5
7
6
A
6
7
A
5
A
8
4
9
A
3
A
10
2
A
11
1
A
12
0
13
I/O
0
14
I/O1I/O
VCCWE
232
31
1
X28C010
(TOP VIEW)
15 1716 18 19 20
2
SS
I/O3I/O4I/O5I/O
V
3858 FHD F03.1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
3858 ILL F21
NC
30
A
29
14
28
A
13
A
27
8
26
A
9
25
A
11
24
OE
A
23
10
22
CE
I/O
21
7
6
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
NC
V
SS
NC
NC
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
X28C010
PIN DESCRIPTIONS
Addresses (A0–A16)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C010 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010.
FUNCTIONAL DIAGRAM
PIN NAMES
Symbol Description
A0–A
16
I/O0–I/O
7
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
V
SS
NC No Connect
Address Inputs
Data Input/Output
+5V
Ground
3858 PGM T01
A8–A
A0–A
16
7
CE
OE
WE
V
V
CC
SS
X BUFFERS
LATCHES AND
DECODER
Y BUFFERS
LATCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
1M-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0–I/O
DATA INPUTS/OUTPUTS
7
3858 FHD F01
2
X28C010
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by
the rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows
two to two hundred fifty-six bytes of data to be consecutively written to the X28C010 prior to the commencement of the internal programming cycle. The host can
fetch data from another device within the system during
a page write operation (change the source address), but
the page address (A8 through A16) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28C010 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
5TBDP 43210I/O
RESERVED
TOGGLE BIT
DATA POLLING
3858 FHD F11
DATA Polling (I/O7)
The X28C010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C010,
eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data. Note: If the
X28C010 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
Toggle Bit (I/O6)
The X28C010 also provides another method for determining when the internal write cycle is complete. During
the internal programming cycle, I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3
X28C010
DATA Polling I/O
7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
A0–A
I/O
IH
7
An An An An An An
14
HIGH Z
Figure 3. DATA Polling Software Flow
WRITE DATA
V
OH
V
OL
An
X28C010
READY
3858 FHD F12
DATA Polling can effectively halve the time for writing to
the X28C010. The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3 illustrates one method of implementing the routine.
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
I/O
7
COMPARE?
YES
X28C010
READY
NO
NO
3858 FHD F13
4
X28C010
The Toggle Bit I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
I/O
6
* Beginning and ending state of I/O6 will vary.
OH
*
Figure 5. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
HIGH Z
V
OL
*
X28C010
READY
3858 FHD F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C010 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
X28C010
READY
NO
3858 FHD F15
5
X28C010
HARDWARE DATA PROTECTION
The X28C010 provides three hardware features that
protect nonvolatile data from inadvertent writes.
• Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.
• Default V
VCC is ≤3.5V.
Sense—All functions are inhibited when
CC
• Write inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
The X28C010 offers a software controlled data protection feature. The X28C010 is shipped from Xicor with the
software data protection NOT ENABLED: that is the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once VCC was stable.
The X28C010 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.
Once the software protection is enabled, the X28C010
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific addresses. Refer to Figures 6 and 7 for the sequence. The
three byte sequence opens the page write window
enabling the host to write from one to two hundred fiftysix bytes of data. Once the page load cycle has been
completed, the device will automatically be returned to
the data protected state.
6
X28C010
Software Data Protection
Figure 6. Timing Sequence—Byte or Page Write
V
CC
0V
DATA
ADDR
CE
WE
AA
5555
Figure 7. Write Sequence for
Software Data Protection
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
55
2AAA
A0
5555
≤t
BLC MAX
(VCC)
WRITES
OK
BYTE
OR
PAGE
t
WC
WRITE
PROTECTED
3858 FHD F16
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the X28C010
will automatically disable further writes unless another
command is issued to cancel it. If no further commands
are issued the X28C010 will be write protected during
power-down and after any subsequent power-up. The
state of A15 and A16 while executing the algorithm is
don’t care.
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
PROTECTED STATE
WC
Note: Once initiated, the sequence of write operations
should not be interrupted.
OPTIONAL
BYTE/PAGE
LOAD OPERATION
3858 FHD F17
7
X28C010
Resetting Software Data Protection
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
DATA
ADDRAA5555
CE
WE
55
2AAA
80
5555
Figure 9. Software Sequence to Deactivate
Software Data Protection
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
AA
5555
55
2AAA
20
5555
≥t
WC
STANDARD
OPERATING
MODE
3858 FHD F18
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC,
the X28C010 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
3858 FHD F19
8
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