查询X25168供应商
64K
32K
16K
V
Supervisory Circuit w/Serial E
CC
X25648/49,
X25328/29,
X25168/69
FEATURES
• Low Vcc Detection and Reset Assertion
—Reset Signal Valid to Vcc=1V
• Save Critical Data With Block Lock
—Block Lock
Serial E
TM
Protect 0, 1/4, 1/2 or all of
2
PROM Memory Array
TM
Protection
• In Circuit Programmable ROM Mode
• Long Battery Life With Low Power Consumption
—<1 µ A Max Standby Current
—<5mA Max Active Current during Write
—<400 µ A Max Active Current during Read
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• 2MHz Clock Rate
• Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• SPI Modes (0,0 & 1,1)
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• High Reliability
• Available Packages
—14-Lead SOIC (X2564X)
—14-Lead TSSOP (X2532X, X2516X)
—8-Lead SOIC (X2532X, X2516X)
8K x 8 Bit
4K x 8 Bit
2K x 8 Bit
2
PROM
DESCRIPTION
These devices combines two popular functions, Supply
Voltage Supervision and Serial E
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
The user’s system is protected from low voltage conditions by the devices low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET
/RESET is asserted until Vcc returns to
proper operating levels and stabiliz es.
The memory portion of the device is a CMOS Serial
2
E
PROM array with Xicor’s Block Lock
array is internally organized as x 8. The de vice features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire b us.
The device utilizes Xicor’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
2
PROM Memory in one
TM
Protection. The
TM
cell,
BLOCK DIAGRAM
SI
SO
SCK
CS
RESET/RESET
V
CC
WP
Xicor, Inc. 1994, 1995, 1996 Patents Pending
7032 -1.1 6/17/97 T1/C0/D0 SH
ICP ROM CONTROL
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
LOW
VOLTAGE
SENSE
PROGRAMMING,
BLOCK LOCK &
X - DECODE
LOGIC
STATUS
REGISTER
1
PAGE DECODE LOGIC
32 8
SERIAL
2
E
PROM
ARRAY
HIGH
VOLTAGE
CONTROL
Characteristics subject to change without notice
7036 FRM 01
14-LEAD SOIC
X25648/49
NC
CS
CS
SO
WP
V
SS
1
2
3
4
5
6
7
RESET/RESET
SCK
SI
NC
14
13
12
11
10
9
8
NC
V
CC
V
CC
NC
7036 FRM 02
8-LEAD SOIC
X25328/29
CS
WP
SO
1
2
3
4
RESET
/RESET
8
7
6
5
V
CC
14-LEAD TSSOP
X25328/29
SO
WP
V
SS
1
2
3
4
5
6
7
RESET
/RESET
SCK
SI
14
13
12
11
10
9
8
NC
V
CC
NC
X25168/69
V
SS
SCK
SI
CS
NC
NC
NC
NC
X25168/69
X25648/49, X25328/29, X25168/69
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clock ed out b y
the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this pin.
Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes , addresses, or data present on
the SI pin are latched on the rising edge of the clock input,
while data on the SO pin change after the falling edge of
the clock input.
Chip Select (CS
)
When CS is HIGH, the device is deselected and the SO
output pin is at high impedance and unless a nonvolatile
write cycle is underway, the device will be in the standby
power mode. CS LOW enables the device, placing it in
the active power mode. It should be noted that after
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Write Protect (WP)
When WP is low and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the device Status Register are
disabled, but the part otherwise functions normally. When
WP is held high, all functions, including nonvolatile writes
to the Status Register operate normally. If an internal
Status Register Write Cycle has already been initiated,
WP going low while WPEN is a “1” will have no effect on
this write. Subsequent write attempts to the Status
Register under these conditions will be disabled.
The WP pin function is blocked when the WPEN bit in the
Status Register is “0”. This allows the user to install the
device in a system with WP pin g rounded and still be ab le
to program the Status Register. The WP pin functions will
be enabled when the WPEN bit is set to a “1”.
Reset (RESET/RESET)
RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever Vcc falls below the minimum Vcc sense level. It will remain active until Vcc rises
above the minimum Vcc sense le vel f or 200ms.
PIN CONFIGURATION
PIN NAMES
Symbol Description
CS
SO Serial Output
SI Serial Input
SCK Serial Clock Input
WP Program Protect Input
V
SS
V
CC
RESET/RESET
2
Chip Select Input
Ground
Supply Voltage
Reset Output
7036 FRM T01
X25648/49, X25328/29, X25168/69
PRINCIPLES OF OPERATION
The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families.
The device monitors V
and asserts RESET
CC
/RESET
output if the supply voltage falls below a preset minimum
V
. The device contains an 8-bit instruction register. It is
trip
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS
must be LOW during the
entire operation.
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on the
first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
Write Enable Latch
The device contains a Write Enable Latch. This latch m ust
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status Register. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
7 6 5 4 3 2 1 0
WPEN FLB 1 1 BL1 BL0 WEL WIP
7036 FRM T02
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL=1, the latch is set
HIGH and when WEL=0 the latch is reset LO W. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
The Block Lock bits, BL0 and BL1, set the level of Block
TM
Lock
Protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user
to protect one quarter, one half, all or none of the
2
E
PROM array. An y portion of the array that is Bloc k Lock
Protected can be read but not written. It will remain protected until the BL bits are altered to disable Block Lock
Protection of that portion of memory.
Status
Register
Bits Array Addresses Protected
BL1 BL0 X2564X X2532X X2516X
0 0 None None None
0 1 $1800–$1FFF $0C00–$0FFF $0600–$07FF
1 0 $1000–$1FFF $0800–$0FFF $0400–$07FF
1 1 $0000–$1FFF $0000–$0FFF $0000–$07FF
7036 FRM T03
Bits 4 and 5 of the Status Register will be read as “1’s”
and must be written as “1’ s” on all Status Register writes.
Table 1. Instruction Set
Instruction Name Instruction Format* Operation
WREN 0000 0110
SFLB 0000 0000
WRDI/RFLB 0000 0100
RSDR 0000 0101
WRSR 0000 0001
READ 0000 0011
WRITE 0000 0010
*Instructions are shown MSB in leftmost position. Instructions are transf erred MSB first.
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
Write Status Register (BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
3
7036 FRM T04
X25648/49, X25328/29, X25168/69
The read only FLAG bit shows the status of a v olatile latch
that can be set and reset by the system using the SFLB
and RFLB instructions. The Flag bit is automatically reset
upon power up.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
pin to provide Programmable Hardw are Write Protec-
WP
tion (Table 2). When WP is LO W and the WPEN bit is programmed HIGH, all Status Register Write Operations are
disabled.
In Circuit Programmable ROM Mode
This mechanism protects the Block Lock and Watchdog
bits from inadvertant corruption. It may be used to perform an In Circuit Programmable ROM function by hardwiring the WP
pin to ground, writing and Block Locking
the desired portion of the array to be ROM, and then programming the WPEN bit HIGH.
Read Sequence
When reading from the E
2
PROM memory array, CS
is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, f ollow ed b y the 16bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is automatically incremented to the next higher address after
each byte of data is shifted out. When the highest address
is reached, the address counter rolls over to address
$0000 allowing the read cycle to be continued indefinitely.
The read operation is terminated by taking CS high. Ref er
to the Read E
2
PROM Array Sequence (Figure 1).
To read the Status Register, the CS
line is first pulled low
to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the
Status Register are shifted out on the SO line. Refer to
the Read Status Register Sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the Write
Operation without taking CS HIGH after issuing the
WREN instruction, the Write Operation will be ignored.
To write data to the E
2
PROM memory array, the user then
issues the WRITE instruction followed by the 16 bit
address and then the data to be written. Any unused bits
are specified to be “0’s”. The WRITE operation minimally
takes 32 clocks. CS
must go low and remain low for the
duration of the operation. If the address counter reaches
the end of a page and the clock continues, the counter will
roll back to the first address of the page and overwrite any
data that may hav e been previously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0
and 1 must be “0”. Data bits 4 and 5 must be “1”.
Table 2.
STATUS
REGISTER
STATUS
REGISTER
WEL WPEN WP#
0 X X Protected Protected Protected
1 1 0 Protected Writable Protected
1 0 X Protected Writable Writable
1 X 1 Protected Writable Writable
DEVICE
PIN BLOCK BLOCK
PROTECTED
BLOCK
4
UNPROTECTED
BLOCK
STATUS
REGISTER
WPEN, BL0,
BL1 BITS
7036 FRM T06
.
X25648/49, X25328/29, X25168/69
While the write is in progress following a Status Register
2
or E
PROM Sequence, the Status Register may be read
to check the WIP bit. During this time the WIP bit will be
high.
RESET
/RESET Operation
The RESET (X25XX3) output is designed to go LOW
whenever V
V
.
trip
has dropped below the minimum trip point,
CC
The RESET (X25XX5) output is designed to go HIGH
whenever V
V
.
trip
The RESET
has dropped below the minimum trip point,
CC
/RESET output is an open drain output and
requires a pull up resistor.
Operational Notes
The device powers-up in the f ollowing state:
• The device is in the low power standb y state.
• A HIGH to LOW transition on CS
is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The Write Enable Latch is reset.
• The Flag Bit is reset.
• Reset Signal is active for t
PURST
Data Protection
The following circuitry has been included to prevent inadvertent writes:
• A WREN instruction must be issued to set the Write
Enable Latch.
must come HIGH at the proper clock count in order
• CS
to start a nonvolatile write cycle.
Figure 1. Read E
CS
SCK
SI
HIGH IMPEDANCE
SO
2
PROM Array Sequence
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION 16 BIT ADDRESS
15 14 13 3 2 1 0
DATA OUT
7 6 5 4 3 2 1 0
MSB
7036 FRM 03
5
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