Xicor X25138 Technical data
查询X25138供应商
128K
5MHz SPI Serial E
FEATURES
5MHz Clock Rate
•
•
Low Power CMOS
<1
m
A Standby Current
<5mA Active Current
2.5V To 5.5V Power Supply
•
SPI Modes (0,0 & 1,1)
•
16K X 8 Bits
•
32 Byte Page Mode
•
Block Lock™ Protection
Protect 1/4, 1/2 or all of E
•
Programmable Hardware Write Protection
In-Circuit Programmable ROM Mode
Built-in Inadvertent Write Protection
•
Power-Up/Down protection circuitry
Write Enable Latch
Write Protect Pin
•
Self-Timed Write Cycle
5ms Write Cycle Time (Typical)
High Reliability
•
Endurance: 100,000 cycles
Data Retention: 100 Years
ESD protection: 2000V on all pins
•
Packages
8-Lead XBGA
8, 14-Lead SOIC
8-Lead PDIP
8-Lead TSSOP
2
PROM Array
X25138
2
PROM with Block Lock
DESCRIPTION
The X25138 is a CMOS 128K-bit serial E
internally organized as 16K x 8. The X25138 features
a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate
data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25138 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25138 disabling all write
attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory .
The X25138 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
16K x 8 Bit
TM
Protection
2
PROM,
input, the X25138 will ignore tran-
TM
FUNCTIONAL DIAGRAM
STATUS
REGISTER
SO
SI
SCK
CS
HOLD
WP
Direct WriteÔ and Block LockÔ Protection is a trademark of Xicor, Inc.
Ó
Xicor, Inc. 1998 Patents Pending 1 Characteristics subject to change without notice
7056–1.5 8/13/98 T2/C0/D1 EW
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
TIMING
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
256
128
128
16K BYTE
ARRAY
128 X 256
128 X 256
256 X 256
832
Y DECODE
DATA REGISTER
7037 FRM F01
X25138
CS
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the r ising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes , addresses , or data present
on the SI pin are latched on the rising edge of the
clock input, while data on the SO pin change after the
falling edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25138 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25138 will be
in the standby power mode. CS LOW enables the
X25138, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25138 status register are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including
nonvolatile writes operate normally. WP going LOW
while CS is still LOW will interrupt a write to the
PIN NAMES
Symbol Description
Chip Select Input
SO Serial Output
SI Serial Input
SCK Serial Clock Input
WP
V
SS
V
CC
HOLD
Write Protect Input
Ground
Supply Voltage
Hold Input
NC No Connect
7037 FRM T01
X25138 status register. If the internal wr ite cycle has
already been initiated, WP going LOW will have no
affect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25138 in a system with WP pin grounded and still
be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to pause
the device. Once the part is selected and a serial
sequence is underway, HOLD
may be used to pause
PIN CONFIGURATION
8-LEAD TSSOP
HOLD
.336”
V
cc
CS
SO
1
2
3
4
8-Lead XBGA: Top View
HOLD
V
CC
SI
SCK
14 Lead SOIC
1
CS
SO
2
NC
3
4
NC
NC
5
6
WP
V
V
CS
SO
WP
SS
7
SS
8 Lead PDIP/SOIC
1
2
3
4
X25138
.252 in.
.078”
1
8
2
7
3
6
4
5
X25138
.228”
X25138
S0
CS
V
WP
SS
14
13
12
11
10
9
8
8
7
6
5
8
7
6
5
.238”
V
CC
HOLD
NC
NC
NC
SCK
SI
V
CC
HOLD
SCK
SI
SCK
SI
V
ss
WP
.114”
3091 FM 03
2
X25138
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
PRINCIPLES OF OPERATION
The X25138 is a 16K x 8 E
2
PROM designed to interface directly with the synchronous serial peripheral
interface (SPI) of many popular microcontroller families.
The X25138 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and
WP inputs must be HIGH during the entire operation.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25138 into a “PAUSE” condition. After releasing
HOLD, the X25138 will resume operation from the
point when HOLD was first asserted.
Write Enable Latch
The X25138 contains a “write enable” latch. This latch
must be SET before a write operation will be
completed internally . The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status
register write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is
formatted as follows:
76543210
WPEN X X X BL1 BL0 WEL WIP
7037 FRM T02
WPEN, BL0 and BL1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
The Write-In-Process (WIP) bit indicates whether the
X25138 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Lock (BL0 and BL1) bits are nonvolatile and
allow the user to select one of four levels of protection.
The X25138 is divided into four 32K-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated
below.
Status Register Bits Array Addresses
BL1 BL0
0 0 None
0 1 $3000–$3FFF
1 0 $2000–$3FFF
1 1 $0000–$3FFF
Protected
7037 FRM T03
Table 1. Instruction Set
Instruction Name Instruction Format* Operation
WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations)
WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations)
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register
READ 0000 0011 Read Data from Memory Array beginning at selected address
WRITE 0000 0010 Write Data to Memory Array beginning at Selected Address (1 to 32
Bytes)
*Instructions are shown MSB in leftmost position. Instructions are transf erred MSB first.
3
7037 FRM T04
X25138
The Write-Protect-Enable (WPEN) bit is available for
the X25138 as a nonvolatile enable bit for the WP pin.
WPEN
WP
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 LOW 0 Protected Protected Protected
1 LOW 1 Protected Writable Protected
X HIGH 0 Protected Protected Protected
X HIGH 1 Protected Writable Writable
WEL
Protected
Blocks
Unprotected
Blocks
Status
Register
7037 FRM T05
Programmable Hardware Write Protection
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register
control the Programmable Hardware Write Protect
feature. Hardware Write Protection is enabled when
WP pin is LOW, and the WPEN bit is “1”. Hardware
Write Protection is disabled when either the WP pin is
HIGH or the WPEN bit is “0”. When the chip is hardware write protected, nonvolatile writes are disabled to
the Status Register, including the Block Lock bits and
the WPEN bit itself, as well as the block-protected
sections in the memory array. Only the sections of the
memory array that are not block-protected can be
written.
In Circuit Programmable ROM Mode
Note that since the WPEN bit is write protected, it
cannot be changed back to a LOW state; so write
protection is enabled as long as the WP pin is held
LOW. Thus an In Circuit Programmable ROM function
can be emplemented by hardwiring the WP pin to Vss,
writing to and Block Locking the desired portion of the
array to be ROM, and then prog ramming the WPEN bit
HIGH. The table above defines the program protect
status for each combination of WPEN and WP .
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the E
2
PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25138, followed by
the 16-bit address of which the last 14 are used. After
the READ opcode and address are sent, the data
stored in the memory at the selected address is
shifted out on the SO line. The data stored in memory
at the next address can be read sequentially by
continuing to provide clock pulses. The address is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached ($3FFF) the address counter rolls
over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E
2
PROM
array operation sequence illustrated in Figure 1.
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the status register are shifted out on the SO line.
Figure 2 illustrates the read status register sequence.
Write Sequence
Prior to any attempt to write data into the X25138, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS
is first taken
LOW, then the WREN instruction is clocked into the
X25138. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user
continues the write operation without taking CS HIGH
after issuing the WREN instruction, the write operation
will be ignored.
To write data to the E
2
PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS m ust go LOW and remain
LOW for the duration of the operation. The host may
continue to write up to 32 bytes of data to the X25138.
The only restriction is the 32 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may hav e been written.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
data byte N is clocked in. If it is brought HIGH at any
other time the write operation will not be completed.
Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which
CS going HIGH are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”. Figure 6 illustrates this sequence.
While the write is in progress following a status
register or E
2
PROM write sequence, the status
register may be read to check the WIP bit. During this
time the WIP bit will be HIGH.
4
X25138
012345678910 2021222324252627282930
76543210
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION 16 BITADDRESS
15 14 13 3 2 1 0
7037 FRM F03
Hold Operation
The HOLD input should be HIGH (at V
) under normal
IH
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW and SCK
must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to
V
or tied to V
CC
Figure 1. Read E
through a resistor.
CC
2
PROM Array Operation Sequence
Operational Notes
The X25138 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
•CS must come HIGH at the proper clock count in order to start a write cycle.
Figure 2. Read Status Register Operation Sequence
CS
01234567891011121314
SCK
SI
HIGH IMPEDANCE
SO
INSTRUCTION
DATA OUT
76543210
MSB
5
7037 FRM F04
X25138
Figure 3. Write Enable Latch Sequence
CS
SCK
SI
01234567
SO
HIGH IMPEDANCE
Figure 4. Byte Write Operation Sequence
CS
012345678910
SCK
INSTRUCTION 16 BIT ADDRESS DATA BYTE
SI
SO
HIGH IMPEDANCE
7037 FRM F05
20 21 22 23 24 25 26 27 28 29 30 31
76543210151413 3210
7037 FRM F06
6
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