APPLICATION NOTE
A V A I L A B L E
AN84
128K
2-Wire SerialFlash with Block Lock
FEATURES
Save Critical Data With Programmable
•
Block Lock Protection
—Block Lock (0, 1/4, 1/2, or all of E
—Software Program Protection
—Programmable Hardware Program Protect
•
In Circuit Programmable ROM Mode
•
Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Program Current Less Than 3mA
—Standby Current Less Than 1 µ A
•
1.8V to 3.6V or 5V “Univolt” Read and
Program Power Supply Versions
32 Word Sector Program Mode
•
—Minimizes T otal Program Time P er Word
100KHz 2-Wire Serial Interface
•
Internally Organized 16K x 8
•
Bidirectional Data Transfer Protocol
•
Self-Timed Program Cycle
•
—Typical Program Cycle Time of 5ms
•
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
•
8-Lead DIP
•
16-Lead SOIC
2
PROM Array)
X24F128
DESCRIPTION
The X24F128 is a CMOS SerialFlash Memory, internally organized 16K x 8. The device features a serial
interface and software protocol allowing oper ation on a
simple two wire bus.
Three device select inputs (S
devices to share a common two wire bus .
A Program Protect Register at the address location
FFFFh provides three program protection features:
Software Program Protect, Block Lock Protect, and
Hardware Program Protect. The Software Program
Protect feature prevents any nonvolatile writes to the
device until the PEL bit in the Program Protect
Register is set. The Block Lock Protection feature
allows the user to individually block protect four blocks
of the array by programming two bits in the Program
Protect Register. The Programmable Hardware
Program Protect feature allows the user to install the
device with PP tied to V
array in circuit, and then enable the hardware program
protection by programming a PPEN bit in the Program
Protect Register. After this, selected blocks of the
array, including the Program Protect Register itself, are
permanently protected from being erased.
TM
Protection
CC
16K x 8 Bit
–S
) allow up to eight
0
2
, program the entire memory
FUNCTIONAL DIAGRAM
SERIALFLASH DATA
AND ADDRESS (SDA)
SCL
S2
S1
S0
PP
Xicor, 1995, 1996 Patents Pending Characteristics subject to change without notice
7012-0.8 11/25/96 T1/C0/D0 SH
COMMAND
DECODE
AND
CONTROL
LOGIC
DEVICE
SELECT
LOGIC
SECTOR
DECODE
LOGIC
BLOCK LOCK AND
PROGRAM PROTECT
CONTROL LOGIC
PROGRAM
PROTECT
REGISTER
1
DATA REGISTER
Y DECODE LOGIC
SERIALFLASH
ARRAY
16K x 8
4K x 8
4K x 8
8K x 8
PROGRAM VOLTAGE
CONTROL
7012 ILL F01.4
X24F128
)
Xicor SerialFlash Memories are designed and tested
for applications requiring extended endurance.
Inherent data retention is greater than 100 years.
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data
sheet.
Device Select (S
The device select inputs (S
, S
, S
0
1
2
, S
, S
0
) are used to set
1
2
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to V
SS
or V
as appro-
CC
priate. If actively driven, they must be driven with
CMOS levels .
Program Protect (PP)
The Program Protect input controls the Hardware
Program Protect feature. When held LOW, hardware
program protection is disabled and the device can be
programmed normally. When this input is held HIGH,
and the PPEN bit in the Program Protect Register is
set HIGH, program protection is enabled, and nonv olatile writes are disabled to the selected blocks as well
as the Program Protect Register itself.
PIN NAMES
Symbol Description
S
, S
, S
0
1
2
SDA Serial Data
SCL Serial Clock
PP Program Protect
V
SS
V
CC
NC No Connect
PIN CONFIGURATION
1
S0
S
2
1
S
3
2
VSS
NC
NC
NC
NC
VSS
S
0
S
1
S
2
4
16-LEAD SOIC
1
2
3
4
5
6
7
8
Device Select Inputs
Ground
Supply Voltage
8-LEAD DIP
8
X24F128
X24F128
7
6
5
16
15
14
13
12
11
10
9
VCC
PP
SCL
SDA
V
CC
PP
NC
NC
NC
NC
SCL
SDA
7012 ILL F02.1
7012 FRM T01
2
X24F128
SCL
SDA
DATA STABLE DATA
CHANGE
7012 ILL F03
SCL
SDA
START BIT STOP BIT
7012 ILL F04
DEVICE OPERATION
The device supports a bidirectional, bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers, and provide the clock for both transmit and
receive operations. Therefore, the X24F128 will be
considered a slave in all applications.
Figure 1. Data Validity
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
Figure 2. Definition of Start and Stop
3
X24F128
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus .
Acknowledge
Acknowledge is a software con v ention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Ref er to Figure 3.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
1
The device will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a program operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent byte.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data transmissions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
8 9
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
7012 ILL F05
4
X24F128
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the de vice type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S
0
, S
, and S
1
. This allows up to 8
2
devices to share a single bus. These bits are
compared to the S
0
, S
, and S
1
device select input
2
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a read operation is selected. When it is zero then
a program operation is selected. Refer to figure 4.
After loading the Slave Address Byte from the SDA
bus, the device compares the device type bits with the
value “1010” and the device select bits with the status
Figure 4. Device Addressing
DEVICE TYPE
IDENTIFIER
1
0 1
0
DEVICE
SELECT
S
S1S0R/W
2
of the device select input pins. If the compare is not
successful, no acknowledge is output during the ninth
clock cycle and the device returns to the standby mode.
The byte address is either supplied by the master or
obtained from an internal counter, depending on the
operation. When required, the master must supply the
two Address Bytes as shown in figure 4.
The internal organization of the E
2
array is 512 sectors
by 32 bytes per sector. The sector address is partially
contained in the Address Byte 1 and partially in bits 7
through 5 of the Address Byte 0. The specific byte
address is contained in bits 4 through 0 of the Address
Byte 0. Ref er to figure 4.
SLAVE ADDRESS BYTE
0 A10 A9 A80 A13
LOW ORDER ADDRESS
A7 A6
D7
A5
D6 D5
HIGH ORDER ADDRESS
A12
A11
ADDRESS BYTE 1
A3
A4
ADDRESS BYTE 0
D4
DATA BYTE
A2 A1 A0
D3
D2 D1
D0
7012 ILL F06.1
5
X24F128
PROGRAMMING OPERATIONS
Sector Program Operation
The device executes a thirty-two byte sector program
operation. For a sector program operation, the device
requires the Slave Address Byte, Address Byte 1, and
Address Byte 0. Address Byte 0 must contain the first
byte of the sector to be programmed. Upon receipt of
Address Byte 0, the device responds with an acknowledge, and waits for the first eight bits of data. After
receiving the 8 bits of the first data byte, the device
again responds with an acknowledge. The device will
Figure 5. Sector Program Sequence
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
S
T
SLAVE
A
ADDRESS
R
T
1 0 1 0 0
S P
ADDRESS
BYTE 1
A
C
K
respond with an acknowledge after the receipt of each
of 31 more bytes. Each time the byte address is internally incremented by one, while the sector address
remains constant. When the counter reaches the end
of the sector, the master terminates the data loading
by issuing a stop condition, which causes the device to
begin the nonvolatile write cycle. All inputs are
disabled until completion of the nonvolatile write cycle.
The SDA pin is at high impedance. Refer to figure 5 f or
the address, acknowledge, and data transfer
sequence.
DATA
(32)
7012 ILL F08.1
A
C
K
ADDRESS
BYTE 0
A
C
K
DATA
(1)
A
C
K
S
T
O
P
A
C
K
6
X24F128
Acknowledge Polling
The maximum program cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a program
or read operation. If the device is still busy with the
nonvolatile write cycle, then no ACK will be returned. If
the device has completed the nonvolatile write operation, an ACK will be returned and the host can then
proceed with the read or program operation. Refer to
figure 6.
Figure 6. Acknowledge Polling Sequence
BYTE LOAD COMPLETED
BY ISSUING STOP.
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS BYTE
(READ OR PROGRAM)
ACK
RETURNED?
YES
NO
ISSUE STOP
READ OPERATIONS
Read operations are initiated in the same manner as
program operations with the exception that the R/W bit
of the Slave Address Byte is set to one. There are
three basic read operations: Current Address Reads,
Random Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last byte read or
programmed, incremented by one. After a read operation from the last address in the array, the counter will
“roll over” to the first address in the array. After a
program operation to the last address in a given sector,
the counter will “roll over” to the first address of the
same sector.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the byte at the current address. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to figure 7 for
the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 7. Current Address Read Sequence
NONVOLATILE
WRITE
CYCLE COMPLETE.
CONTINUE
SEQUENCE?
YES
CONTINUE NORMAL
READ OR PROGRAM
COMMAND SEQUENCE
PROCEED
NO
ISSUE STOP
7012 ILL F09
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
7
S
T
SLAVE
A
ADDRESS
R
T
1010 1S P
A
C
DATA
K
7012 ILL F10
S
T
O
P
X24F128
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W
bit set to one, the
master must first perform a “Dummy” program operation. The master issues the start condition and the
Slave Address Byte with the R/W bit low, receives an
acknowledge, then issues Address Byte 1, receives
another acknowledge, then issues Address Byte 0
containing the address of the byte to be read. After the
device acknowledges receipt of Address Byte 0, the
master issues another start condition and the Slave
Address Byte with the R/W
bit set to one. This is
followed b y an ac kno wledge and then eight bits of data
from the device. The master terminates the read operation by not responding with an acknowledge and then
issuing a stop condition. Refer to figure 8 for the
address, acknowledge, and data tr ansf er sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the
second start shown in figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the
address counter, b ut no data is output by the de vice .
The next Current Address Read operation will read
from the newly loaded address.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first byte is transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it
requires additional data. The device continues to
output data for each acknowledge received. The
master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all byte
addresses, allowing the entire memory contents to be
read during one operation. At the end of the address
space the counter “rolls over” to address 0000h and the
device continues to output data for each acknowledge
received. Refer to figure 9 for the acknowledge and data
transfer sequence.
Figure 8. Random Read Sequence
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
S
T
SLAVE
A
ADDRESS
R
T
S PS
1 0 1 0 0
Figure 9. Sequential Read Sequence
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
SLAVE
ADDRESS
S
1
A
C
K
A
C
K
ADDRESS
BYTE 1
DATA
(1)
S
T
ADDRESS
BYTE 0
A
C
K
A
C
K
DATA
(2)
A
C
K
A
C
K
A
R
T
SLAVE
ADDRESS
DATA
(n–1)
1
A
C
DATA
K
7012 ILL F11.1
A
C
K
DATA
(n)
7012 ILL F12.1
S
T
O
P
S
T
O
P
P
8
X24F128
PROGRAM PROTECT REGISTER (PPR)
Register Program Operation
The Program Protect Register can only be modified by
programming one data byte directly to the address
FFFFh as described below.
The data byte must contain zeroes where indicated in
the procedural descriptions below; otherwise the operation will not be performed. Only one data byte is
allowed for each Register Program Operation. The
part will not acknowledge any data bytes after the first
byte is entered. The user then has to issue a stop to
initiate the nonvolatile write cycle that programs BL0,
BL1, and PPEN to the nonvolatile bits. A stop must
also be issued after volatile register program operations to put the device into Standby.
The state of the Program Protect Register can be read
by performing a random read at FFFFh at any time.
The part will reset itself after the first byte is read. The
master should supply a stop condition to be consistent
with the protocol. After the read, the address counter
contains 0000h.
Program Protect Register: PPR (ADDR = FFFF
7 6 5 4 3 2 1 0
PPEN 0 0 BL1 BL0 RPEL PEL 0
)
h
PEL: Program Enable Latch (Volatile)
0 = PEL reset, programming disabled.
1 = PEL set, programming enabled.
RPEL: Register Program Enable Latch (Volatile)
0 = RPEL reset, programs to the Program Protect
Register disabled.
1 = RPEL set, programs to the Program Protect
Register enabled.
BL0, BL1: Block Lock Protect Bits (Nonvolatile)
The Block Lock Protect Bits, BL0 and BL1, determine
which blocks of the arra y are protected. A program to a
protected block of memory is ignored, but will receive
an acknowledge. The master must issue a stop to put
the part into standby, just as it would for a valid
program; but the stop will not initiate an internal
nonvolatile write cycle. See figure 10.
PPEN: Program Protect Enable Bit (Nonvolatile)
The Program Protect (PP) pin and the Program
Protect Enable (PPEN) bit in the Program Protect
Register control the Programmable Hardware
Program Protection feature. Hardware Program
Protection is enabled when the PP pin is HIGH and the
PPEN bit is HIGH, and disabled when either the PP
pin is LOW or the PPEN bit is LOW. When the chip is
Hardware Program Protected, nonvolatile writes are
disabled to the Program Protect Register, including the
Block Lock Protect bits and the PPEN bit itself, as well
as to the Block Lock protected sections in the memory
array. Only the sections of the memory array that are
not Block Lock protected, and the volatile bits PEL and
RPEL, can be programmed.
In Circuit Programmable ROM Mode
Note that since the PPEN bit is program protected, it
cannot be changed back to a LOW state; so program
protection is enabled as long as the PP pin is held
HIGH. Thus an In Circuit Programmable ROM function
can be implemented by hardwiring the PP pin to Vcc,
programming and Block Locking the desired portion of
the array to be ROM, and then programming the
PPEN bit HIGH. Figure 11 defines the program protect
status for each combination of PPEN and PP.
Programming the PEL and RPEL bits
PEL and RPEL are volatile latches that power up in
the LOW (disabled) state. While the PEL bit is LOW,
program operations to any address other than FFFFh
will be ignored (no acknowledge will be issued after
the data byte). The PEL bit is set by programming
00000010 to address FFFFh. Once set, PEL remains
HIGH until either it is reset to 0 (by programming
00000000 to FFFFh) or until power cycles. Programming PEL and RPEL does not cause a nonvolatile
write cycle, so the device is ready for the next operation immediately after the stop condition.
The RPEL bit controls programming to the Block Lock
Protect bits, BL0 and BL1, and the PPEN bit. If RPEL
is 0 then no programming operations can be
performed on BL0, BL1, or PPEN. RPEL is reset when
power cycles or after any nonvolatile write, including
those to the Block Lock Protect bits, the PPEN bit, or
any sector in the memory array. RPEL must be reset
before PEL can be reset. RPEL and PEL cannot be
reset in one program operation. RPEL can also be
reset by programming u00xy010 to FFFFh ONLY
when the PPR is NOT protected. This is the same
operation as in step 3 described below, and will result
in programming BL0, BL1, and PPEN.
9
X24F128
1)
2)
3)
Programming to the BL and PPEN Bits
A 3 step sequence is required to change the nonvolatile Block Lock Protect or Program Protect Enab le bits:
Set PEL=1, Program 00000010 to address FFFFh
(Volatile Wr ite Cycle.)
RPEL bit in the data byte for step 3 is a one, then no
changes are made to the Program Protect Register
and the device remains at step 2.
The PP pin must be LOW or the PPEN bit must be
LOW before a nonvolatile register program operation
is initiated. Otherwise, the program operation will abort
Set RPEL=1, Program 00000110 to address FFFFh
(Volatile Write Cycle.)
Set BL1, BL0, and/or PPEN bits, Program
u00xy010 to address FFFFh, where u=PPEN, x=BL1,
and y=BL0. (Non v olatile Write Cycle.)
The three step sequence was created to make it difficult to change the contents of the Program Protect
Register accidentally. If PEL was set to one by a
previous register program operation, the user may
start at step 2. RPEL is reset to zero in step 3 so that
user is required to perform steps 2 and 3 to make
another change. RPEL must be 0 in step 3. If the
and the device will go into standby mode after the
master issues the stop condition in step 3.
Step 3 is a nonvolatile write operation, requiring 10mS
max to complete (acknowledge polling may be used to
reduce this time requirement). It should be noted that
step 3 MUST end with a stop condition. If a start
condition is issued during or at the end of step 3
(instead of a stop condition) the device will abort the
nonvolatile register program and remain at step 2. If
the operation is aborted with a start condition, the
master must issue a stop to put the device into
standby mode.
Figure 10. Block Lock Protect Bits and Protected Addresses
Protected Addresses
BL1 BL0
X24F128
Array Location
0 0 None No Protect
0 1 3000h - 3FFFh Upper 1/4
1 0 2000h - 3FFFh Upper 1/2
1 1 0000h - 3FFFh Full Array
Figure 11. PP Pin and PPEN Bit Functionality
PP PPEN
Memory Array Not
Lock Block Protected
Memory Array Block
Lock Protected
Block Lock Bits
0 X Programmable Protected Programmable Programmable
X 0 Programmable Protected Programmable Programmable
1 1 Programmable Protected Protected Protected
7012 FRM T02
PPEN
Bit
7012 FRM T03
10
X24F128
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X24F128.....................................–65 ° C to +135 ° C
Storage Temperature........................–65 ° C to +150 ° C
Voltage on any Pin with
Respect to V
....................................–1V to +7V
SS
D.C. Output Current..............................................5mA
Lead Temperature
(Soldering, 10 seconds) ..............................300 ° C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Extended –20°C +85°C
7012 FRM T04
Supply Voltage Limits
X24F128 1.8V to 3.6V
X24F128–5 4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS
Limits
Symbol Parameter Min. Max. Units Test Conditions
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
V
V
V
lL
IH
OL
hys
(1)
(1)
(2)
(2)
(3)
VCC Supply Current (Read) 1 mA SCL = VCC X 0.1/VCC X 0.9 Levels
VCC Supply Current
(Program)
3 mA
@ 100KHz, SDA = Open, All Other
V
Inputs =
or VCC – 0.3V
SS
VCC Standby Current 10 µA SCL = SDA = VCC – 0.3V,
V
All Other Inputs =
= 5V ± 10%
V
CC
or VCC – 0.3V,
SS
VCC Standby Current 1 µA SCL = SDA = VCC – 0.1V,
V
or VCC – 0.1V,
SS
CC
Input Leakage Current 10 µA
Output Leakage Current 10 µA
All Other Inputs =
= 1.8V
V
CC
V
= VSS to V
V
IN
OUT
= VSS to V
CC
Input LOW Voltage –0.5 VCC x 0.3 V
Input HIGH Voltage VCC x 0.7 VCC + 0.5 V
Output LOW Voltage 0.4 V IOL = 3mA
Hysteresis of Schmitt
V
x 0.05 V
CC
Trigger Inputs
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
7012 FRM T05
7012 FRM T06.1
Symbol Parameter Max. Units Test Conditions
(3)
C
I/O
(3)
C
IN
Notes: (1) Must perform a stop command prior to measurement.
(2) VIL min. and VIH max. are f or ref erence only and are not 100% tested.
(3) This parameter is periodically sampled and not 100% tested.
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
Input Capacitance (S0, S1, S2, SCL, PP) 6 pF VIN = 0V
11
7012 FRM T07
X24F128
A.C. CONDITIONS OF TEST
Input Pulse Levels VCC x 0.1 to VCC x 0.9
EQUIVALENT A.C. LOAD CIRCUIT
5V
Input Rise and
Fall Times 10ns
Input and Output
Timing Levels
X 0.5
V
CC
OUTPUT
7012 FRM T08
1.53KΩ
100pF
7012 ILL F14.1
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Program Cycle Limits
Symbol Parameter Min. Max. Units
f
SCL
T
I
SCL Clock Frequency 0 100 KHz
Noise Suppression Time
50 100 ns
Constant at SCL, SDA Inputs
t
AA
t
BUF
SCL LOW to SDA Data Out Valid 0.3 3.5 µs
Time the Bus Must Be Free Before a
4.7 µs
New Transmission Can Start
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
Start Condition Hold Time 4 µs
Clock LOW Period 4.7 µs
Clock HIGH Period 4 µs
Start Condition Setup Time
4.7 µs
(for a Repeated Start Condition)
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
Data In Hold Time 0 µs
Data In Setup Time 250 ns
SDA and SCL Rise Time 1 µs
SDA and SCL Fall Time 300 ns
Stop Condition Setup Time 4.7 µs
Data Out Hold Time 300 ns
7012 FRM T09
POWER-UP TIMING
(4)
Symbol Parameter Max. Units
t
PUR
t
PUW
Notes: (4) t
and t
PUR
are periodically sampled and not 100% tested.
Power-up to Read Operation 1 ms
Power-up to Write Operation 5 ms
are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
PUW
12
7012 FRM T10
X24F128
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
7012 ILL F16
SCL
SDA 8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
START
CONDITION
Bus Timing
SCL
SDA IN
SDA OUT
t
SU:STA
t
AA
t
HIGH
t
F
t
HD:STAtHD:DAT
t
LOW
t
DH
t
SU:DAT
t
R
t
SU:STO
t
BUF
7012 ILL F15
Program Cycle Limits
Symbol Parameter Min. Typ.
(6)
T
WR
Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V).
(6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the nonvolatile write operation.
Program Cycle Time 5 10 ms
(5)
Max. Units
7012 FRM T11
The program cycle time is the time from a valid stop condition of a program sequence to the end of the internal
erase/program cycle. During the program cycle, the X24F128 bus interface circuits are disabled, SDA is allowed to
remain HIGH, and the device does not respond to its slav e address.
Bus Timing
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
100
80
60
40
RESISTANCE (KΩ)
20
0
V
R
R
MIN.
RESISTANCE
20 40 60 80
0
BUS CAPACITANCE (pF)
CC MAX
=
MIN
I
OL MIN
t
R
=
MAX
C
MAX.
RESISTANCE
BUS
=1.8KΩ
100
120
7012 ILL F17
SYMBOL TABLE
13
X24F128
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
0.060 (1.52)
0.020 (0.51)
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
SEATING
PLANE
0.150 (3.81)
0.125 (3.18)
0.015 (0.38)
MAX.
TYP. 0.010 (0.25)
0.110 (2.79)
0.090 (2.29)
0.325 (8.25)
0.300 (7.62)
0.065 (1.65)
0.045 (1.14)
0.020 (0.51)
0.016 (0.41)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.145 (3.68)
0.128 (3.25)
0.025 (0.64)
0.015 (0.38)
0°
15°
14
3926 FHD F01
X24F128
PACKAGING INFORMATION
16-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
PIN 1 INDEX
(4X) 7°
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
PIN 1
X 45°
0.014 (0.35)
0.020 (0.51)
0.386 (9.80)
0.394 (10.01)
0.150 (3.80)
0.158 (4.00)
0.004 (0.19)
0.010 (0.25)
0.228 (5.80)
0.244 (6.20)
0.053 (1.35)
0.069 (1.75)
0.050" Typical
0° – 8°
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.012 (0.30)
0.250"
0.030" Typical
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F26
15
0.050"
Typical
16 Places
X24F128
ORDERING INFORMATION
X24F128 X X -X
Device
Part Mark Convention
X24F128 X
VCC Range
Blank = 1.8V to 3.6V
5 = 4.5V to 5.5V
Temperature Range
Blank = 0°C to +70°C
E = –20°C to +85°C
Package
X24F128
P = 8-Lead Plastic DIP
S = 16-Lead SOIC
P = 8-Lead Plastic DIP
S = 16-Lead SOIC
X
Blank = 1.8V to 3.6V, 0°C to +70°C
E = 1.8V to 3.6V, –20°C to +85°C
5 = 4.5V to 5.5V, 0°C to +70°C
E5 = 4.5V to 5.5V, –20°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no w arranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PA TENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELA TED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prev ent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Lif e support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably e xpected to cause the
failure of the life support device or system, or to affect its saf ety or effectiveness.
16
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