XICOR X24F064VI-5, X24F064VI, X24F064VE-5, X24F032PE, X24F032P-5 Datasheet



A

PPLICATION NOTE

A V A I L A B L E

AN76 • AN78 • AN81 • AN87

64K/32K/16K

SerialFlash

X24F064/032/016

TM

Memory with Block Lock

FEATURES

1.8V to 3.6V or 5V “Univolt” Read and

•

Program Power Supply Versions
Low Power CMOS

•

—Active Read Current Less Than 1mA
—Active Program Current Less Than 3mA
—Standby Current Less Than 1 µ A

•

Internally Organized 8K/4K/2K x 8

•

New Programmable Block Lock Protection
—Software Write Protection
—Programmable hardware Write Protect

•

Block Lock (0, 1/4, 1/2, or all of the Flash
Memory array)
2 Wire Serial Interface

•

Bidirectional Data Transfer Protocol

•

32 Byte Sector Programming

•

Self Timed Program Cycle

•

—Typical Programming Time of 5ms

Per Sector

•

High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years

•

Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead TSSOP (X24F032/016)
—20-Lead TSSOP (X24F064)

8K/4K/2K x 8 Bit

TM

Protection

DESCRIPTION

The X24F064/032/016 is a CMOS SerialFlash
Memory Family, internally organized 8K/4K/2K x 8.
The family features a serial interface and software
protocol allowing operation on a simple two wire bus .

Device select inputs (S
devices to share a common two wire bus .

A Program Protect Register accessed at the highest
address location, provides three new programming
protection features: Software Programming Protection,
Block Lock Protection, and Hardware Programming
Protection. The Software Programming Protection
feature prevents any nonvolatile writes to the device
until the WEL bit in the program protect register is set.
The Block Lock

TM

Protection feature allows the user to
individually protect four bloc ks of the arra y b y prog ram­ming two bits in the programming protect register. The
Programmable Hardware Program Protect feature
allows the user to install each device with PP tied to
V

, program the entire memory array in place, and

CC

then enable the hardware programming protection by
programming a PPEN bit in the program protect
register. After this, selected blocks of the array,
including the program protect register itself, are
permanently protected from being programmed.

,

S

,

S

0

) allow up to eight

1

2

FUNCTIONAL DIAGRAM



SerialFlash
Protection are trademarks of Xicor, Inc.

6686-3.8 8/29/96 T3/C0/D0 SH

Memory and Block Lock

Xicor, 1995, 1996 Patents Pending



SDA

SCL

S0/S

S1/S

S2/S

PP

DATA REGISTER

SECTOR DECODE LOGIC

32 8

X

COMMAND

0

1

2

DECODE

AND CONTROL

LOGIC

PROGRAMMING

CONTROL LOGIC

1

DECODE

LOGIC

PROGRAM

PROTECT

REGISTER

SECTORED

MEMORY

ARRAY

HIGH VOLTAGE

CONTROL

6686 ILL F01.5

Characteristics subject to change without notice

X24F064/032/016

)

).

Xicor SerialFlash Memories are designed and tested for
applications requiring extended endurance. Inherent
data retention is greater than 100 years.

PIN DESCRIPTIONS
Serial Clock (SCL)

The SCL input is used to clock all data into and out of
the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.

An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the pull­up resistor selection graph at the end of this data
sheet.

Device Select (S

, S

, S

, S

, S

0

0

1

, S

1

2

2

The device select inputs are used to set the device
select bits of the 8-bit slave address. This allows
multiple devices to share a common bus. These inputs
can be static or actively driven. If used statically they
must be tied to V

SS

or V

as appropriate. If actively

CC

driven, they must be driven with CMOS levels (driven
to V

or V

CC

SS

Program Protect (PP)

The program protect input controls the hardware
program protect feature. When held LOW, hardware
program protection is disabled and the X24F064/
032/016 can be programmed normally. When this
input is held HIGH, and the PPEN bit in the
program protect register is set HIGH, program
protection is enabled, and nonvolatile writes are
disabled to the selected blocks as well as the
program protect register itself.

PIN CONFIGURATION

X24F016

8-LEAD DIP & SOIC

S0

1

S

2

1

3

S

2

4

VSS

8-LEAD DIP & SOIC

S0

1

S

2

1

S

3

2

VSS

4

8-LEAD DIP & SOIC

NC

1

S

2

1

S

3

2

VSS

4

X24F032

8
7
6
5

8
7
6
5

X24F064

8
7
6
5

VCC
PP
SCL
SDA

VCC
PP
SCL
SDA

VCC
PP
SCL
SDA

S

0

S

1

NC
NC
NC

S

2

V

SS

S

0

S

1

NC
NC
NC

S

2

V

SS

NC
NC

S

1

NC
NC
NC

S

2

V

SS
NC
NC

14-LEAD TSSOP

1
2
3
4
5
6
7

14-LEAD TSSOP

1
2
3
4
5
6
7

20-LEAD TSSOP

1
2
3
4
5
6
7
8
9
10

14
13
12
11
10

9
8

14
13
12

11

10

9
8

20
19
18
17
16
15
14
13
12

11

6686 ILL F02.4

V

CC

PP
NC
NC
NC
SCL
SDA

V
PP
NC
NC
NC
SCL
SDA

NC
V

CC

PP
NC
NC
NC
SCL
SDA
NC
NC

CC

PIN NAMES

Symbol Description

S

, S

, S

0

0

, S

, S

1

, S

1

2

2

Device Select Inputs

SDA Serial Data
SCL Serial Clock
PP Program Protect
V

SS

V

CC

Ground
Supply Voltage

NC No Connect

6686 FRM T01.1

2

X24F064/032/016

SCL

SDA

DATA STABLE DATA

CHANGE

6686 ILL F04

SCL

SDA

START BIT STOP BIT

6686 ILL F05

DEVICE OPERATION

The X24F064/032/016 supports a bidirectional bus ori­ented protocol. The protocol defines any device that
sends data onto the bus as a transmitter, and the re­ceiving device as the receiver. The device controlling
the transfer is a master and the device being controlled
is the slave. The master will always initiate data trans­fers, and provide the clock for both transmit and receive
operations. Therefore, the X24F064/032/016 will be
considered a slave in all applications.

Figure 1. Data Validity

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24F064/032/016 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition has
been met.

Notes: (5) Typical values are for T

(6) t

is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the

PR

device requires to perform the internal program operation.

= 25 ° C and nominal supply voltage (2.7V)

A

Figure 2. Definition of Start and Stop

3

X24F064/032/016

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus .

Acknowledge

Acknowledge is a software con v ention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans­mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Ref er to Figure 3.

Figure 3. Acknowledge Response From Receiver

SCL FROM

MASTER

DATA OUTPUT

FROM

TRANSMITTER

1

The X24F064/032/016 will respond with an acknowl­edge after recognition of a start condition and its slave
address. If both the device and a write operation have
been selected, the X24F064/032/016 will respond with
an acknowledge after the receipt of each subsequent
eight-bit word.

In the read mode the X24F064/032/016 will transmit
eight bits of data, release the SDA line and monitor
the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the
master, the X24F064/032/016 will continue to
transmit data. If an acknowledge is not detected, the
device will terminate further data transmissions. The
master must then issue a stop condition to return the
X24F064/032/016 to the standby power mode and
place the device into a known state.

8 9

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

6686 ILL F06

4

X24F064/032/016

BUS ACTIVITY:
MASTER

SDA LINE

BUS ACTIVITY:
X24F016/032/064

S
T
A
R
T

SLAVE

ADDRESS

S

S
T
O
P

P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

SECTOR ADDRESS DATA n DATA n+1 DATA n+31

6686 ILL F10.3

DEVICE ADDRESSING

Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next two bits are the device select bits. A system could
have up to eight X24F032/016’s on the bus or up to
four 24F064’s on the bus. The device addresses are
defined by the state of the S

0

, S

, and S

1

inputs. Note

2

some of the slave addresses must be the inverse of
the corresponding input pin.

Figure 4. Slave Address

X24F064

DEVICE
SELECT

S2

S2

DEVICE

TYPE

IDENTIFIER

1

S1 A12

DEVICE
SELECT

S1 S0

S2 S1

DEVICE

SELECT

HIGH ORDER

SECTOR ADDRESS

A10

A11

X24F032

HIGH ORDER

SECTOR ADDRESS

A10

A11

X24F016

HIGH ORDER

SECTOR ADDRESS

A10

S0

A9 A8 R/W

A9 A8 R/W

A9 A8 R/W

6686 ILL F07.4

Figure 5. Sector Programming

Also included in the slave address is an extension of
the array’s address which is concatenated with the
eight bits of address in the sector address field,
providing direct access to the entire SerialFlash
Memory array.

The last bit of the slave address defines the operation
to be performed. When set HIGH a read operation is
selected, when set LOW a program operation is
selected.

Following the start condition, the X24F064/032/016
monitors the SDA bus comparing the slave address
being transmitted with its slave address device type
identifier. Upon a correct comparison of the device
select inputs, the X24F064/032/016 outputs an
acknowledge on the SDA line. Depending on the state
of the R/W

bit, the X24F064/032/016 will execute a

read or program operation.

PROGRAMMING OPERATIONS

The X24F064/032/016 offers a 32-byte sector pro­gramming operation. For a program operation, the
X24F064/032/016 requires a second address field.
This field contains the address of the first byte in the
sector. Upon receipt of the address, comprised of
eight bits, the X24F064/032/016 responds with an ac­knowledge and awaits the next eight bits of data,
again responding with an acknowledge. The master
then transmits 31 more bytes. After the receipt of
each byte, the X24F064/032/016 will respond with an
acknowledge.

5

X24F064/032/016

Flow 1. ACK Polling Sequence

PROGRAM OPERATION

COMPLETED

ENTER ACK POLLING

ISSUE
START

ISSUE SLAVE

ADDRESS AND R/W = 0

ACK

RETURNED?

YES

NEXT

OPERATION

A WRITE?

YES

ISSUE SECTOR

ADDRESS

PROCEED

NO

NO

ISSUE STOP

ISSUE STOP

PROCEED

After the receipt of each byte, the five low order ad­dress bits are internally incremented by one. The high
order bits of the sector address remain constant. If the
master should transmit more or less than 32 bytes prior
to generating the stop condition, the contents of the
sector cannot be guaranteed. All inputs are disabled
until completion of the internal program cycle. Refer to
Figure 5 for the address, acknowledge and data trans­fer sequence.

Acknowledge Polling

The Max Write Cycle Time can be significantly reduced
using Acknowledge Polling. To initiate Acknowledge
Polling, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle, then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
Refer to Flow 1.

READ OPERATIONS

Read operations are initiated in the same manner as
program operations with the exception that the R/W bit
of the slave address is set HIGH. There are three basic
read operations: current address read, random read
and sequential read.

It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read op­eration, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.

6686 ILL F09.1

6

X24F064/032/016

BUS ACTIVITY:
MASTER

SDA LINE

BUS ACTIVITY:
X24F016/032/064

S
T
A
R

T

SLAVE

ADDRESS

S

S
T
O
P

P

A
C
K

DATA

6686 ILL F11.1

Current Address Read

Internally, the X24F064/032/016 contains an ad­dress counter that maintains the address of the last
byte read, incremented by one byte. Therefore, if the
last read was from address n, the next read opera­tion accesses data from address n + 1. Upon receipt
of the slave address with the R/W

set HIGH, the
X24F064/032/016 issues an acknowledge and trans­mits the eight-bit word. The read operation is termi­nated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer
to Figure 6 for the sequence of address, acknowl­edge and data transfer.

Figure 6. Current Address Read

Random Read

Random read operations allow the master to access
any memory location in a random manner. Prior to is­suing the slave address with the R/W

bit set HIGH, the
master must first perform a “dummy” write operation.
The master issues the start condition, and the slave ad­dress with the R/W bit set LOW, followed by the byte
address it is to read. After the byte address acknowl­edge, the master immediately reissues the start condi­tion and the slave address with the R/W bit set HIGH.
This will be followed by an acknowledge from the
X24F064/032/016 and then by the eight-bit byte. The
read operation is terminated by the master; by not re­sponding with an acknowledge and by issuing a stop
condition. Refer to Figure 7 for the address, acknowl­edge and data transfer sequence.

Figure 7. Random Read

BUS ACTIVITY:
MASTER

SDA LINE

BUS ACTIVITY:
X24F016/032/064

S

T
A
R

T

S

SLAVE

ADDRESS

ADDRESS n

A
C
K

BYTE

7

S

T
A
R

T

S

A
C
K

SLAVE

ADDRESS

S
T
O
P

P

A
C

DATA n

K

6686 ILL F12.3

X24F064/032/016

Sequential Read

Sequential reads can be initiated as either a current
address read or random access read. The first byte is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24F064/032/016
continues to output data for each acknowledge
received. The read operation is terminated by the
master; by not responding with an acknowledge and
then issuing a stop condition.

Figure 8. Sequential Read

BUS ACTIVITY:
MASTER

SDA LINE

BUS ACTIVITY:
X24F016/032/064

SLAVE

ADDRESS

A
C

DATA n

K

A
C
K

DATA n+1

The data output is sequential, with the data from
address n followed by the data from n + 1. The
address counter for read operations increments all
address bits, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space, the counter “rolls over” to 0 and the
X24F064/032/016 continues to output data for each
acknowledge received. Refer to Figure 8 for the
address, acknowledge and data transfer sequence.

S
A
C
K

DATA n+2

A
C
K

DATA n+x

T

O

P

P

6686 ILL F13.1

Figure 9. Typical System Configuration

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

V

CC

PULL-UP
RESISTORS

6686 ILL F14

8

X24F064/032/016

PROGRAM PROTECT REGISTER

The Program Protect Register (PPR) is accessed at the
highest address of each device:

X24F064 = 1FFF
X24F032 = 0FFF
X24F016 = 07FF

Figure 10. Program Protect Register

7 6 5 4 3

PPEN 0 0 BL1 BL0

2

RWEL

WEL

1

0

0

6686 ILL F15

PPR.1 = WEL
– Write Enable Latch (Volatile)

0 = Write enable latch reset, programming disabled

1 = Write enable latch set, programming enabled
If WEL = 0 then “no ACK” after first b yte of input data.
PPR.2 = RWEL

– Register Write Enable Latch (Volatile)

0 = Register write enable latch reset, programming

disabled

1 = Register write enable latch set, programming

enabled
PPR.3, PPR.4 = BL0, BL1

– Block Lock Bits (Nonvolatile)
(See Block Lock Bits section for definition)

PPR.7 = PPEN
– Programming Protect Enable Bit (Nonvolatile)
(See Programmable Hardware Program Protect sec­tion for definition)

other address than the highest address location is
performed, the contents of the byte in the array at the
highest address location is read out instead of the
Program Protect Register .

WEL and RWEL are volatile latches that power-up in
the LOW (disabled) state. A write to any address other
than the highest address location, where the Program
Protect Register is located, will be ignored (no ACK)
until the WEL bit is set HIGH. The WEL bit is set by
writing 0000001x to the highest address location.
Once set, WEL remains HIGH until either reset (by
writing 00000000 to the highest address location) or
until the part powers-up again. The RWEL bit controls
writes to the Block Lock bits. RWEL is set by first
setting WEL = 1 and then writing 0000011x to the
highest address location. RWEL must be set in order
to change the Block Lock bits (BL0 and BL1) or the
PPEN bit. RWEL is reset when the Block Lock or
PPEN bits are changed, or when the part powers-up
again.

Programming the BL or PPEN Bits

A three step sequence is required to change the
nonvolatile Block Loc k or Prog ram Protect Enab le:

1) Set WEL = 1 (write 00000010 to the highest
address location, volatile write cycle)

(Start)

2) Set RWEL = 1 (write 00000110 to the highest
address location, volatile write cycle)

(Start)

3) Set BL1, BL0, and/or PPEN bits (Write w00yz010 to
the highest address location)

w = PPEN, y = BL1, Z = BL0,

Writing to the Program Protect Register

The Program Protect Register is written by performing
a write of one byte directly to the highest address loca­tion. During normal Sector Programming, the byte in
the array at the highest address will be written instead
of the Program Protect Register (assuming program­ming is not disabled by the Block Loc k register).

The state of the Program Protect Register can be read
by performing a random read at the highest address
location at any time. If a sequential read starting at any

(Stop)
Step 3 is a nonvolatile program cycle, requiring 10ms

to complete. RWEL is reset (0) by this program cycle,
requiring another program cycle to set RWEL again
before the Block Lock bits can be changed. RWEL
must be 0 in step 3; if w00yz110 is written to the
highest address location, RWEL is set but PPEN,
BL1 and BL0 are not changed (the device remains at
step 2).

9

X24F064/032/016

Block Lock Bits

The Block Lock Bits BL0 and BL1 determine which
blocks of the memory are write-protected:

Table 1. Block Lock Bits

BL1 BL0 Array Locked

0 0 None
0 1 Upper 1/4
1 0 Upper 1/2
1 1 Full Array (WPR not included)

6686 FRM T02

Programmable Hardware Program Protect

The Program Protect (PP) pin and the Program Protect
Enable (PPEN) bit in the Program Protect Register
control the programmable hardware program protect
feature. Hardware program protection is enabled when
the PP pin and the PPEN bit are both
disabled when either the PP pin is LOW or the PPEN
bit is LOW. When the chip is hardware program­protected, nonvolatile programming is disabled,
including the Program Protect Register , the BL bits and
the PPEN bit itself, as well as to Block Locked sections
in the memory array. Only the sections of the memory
array that are not Block Locked can be written. Note
that since the PPEN bit is program-protected, it cannot
be changed back to a LOW state, and program protec­tion is disabled as long as the PP pin is held HIGH.
Table 2 defines the program protection status for each
state of PPEN and PP.

Table 2. Program Protect Status Table

Memory Array

PP PPEN

0 X Programmable Locked Programmable Programmable
X 0 Programmable Locked Programmable Programmable
1 1 Programmable Locked Locked Locked

(Not Block Locked)

Memory Array

(Block Locked) BL Bits PPEN Bit

HIGH

6686 FRM T03

, and

10

X24F064/032/016

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias

X24F064/032/016 ......................–65°C to +135°C

Storage Temperature........................–65°C to +150°C

Voltage on any Pin with

Respect to VSS.................................... –1V to +7V

D.C. Output Current..............................................5mA

Lead Temperature (Soldering, 10 Seconds)...... 300°C

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature Min. Max.

Commercial 0°C +70°C

Extended –20°C +85°C

Industrial –40°C +85°C

6686 FRM T04.2

Supply Voltage Limits

X24F064/032/016

X24F064/032/016–5

1.8V to 3.6V

4.5V to 5.5V

6686 FRM T05.2

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

I

CC1

I

CC2

I

SB1

I

SB2

I

LI

I

LO

V
V

V

lL

IH
OL

(1)

(1)

(2)

(2)

VCC Supply Current (Read) 1 mA SCL = VCC X 0.1/VCC X 0.9 Levels
VCC Supply Current (Write) 3 mA

@ 100KHz, SDA = Open, All Other
Inputs = VSS or VCC – 0.3V

VCC Standby Current 1 µA SCL = SDA = VCC, All Other

Inputs =
V

CC

V

= 3.6V

or VCC – 0.3V,

SS

VCC Standby Current 10 µA SCL = SDA = VCC, All Other

Input Leakage Current 10 µA
Output Leakage Current 10 µA

Inputs =
V

CC

V

IN

V

OUT

V

SS

= 5V ±10%

= VSS to V

= VSS to V

or VCC – 0.3V,

CC

CC

Input LOW Voltage –1 VCC x 0.3 V
Input HIGH Voltage VCC x 0.7 VCC + 0.5 V
Output LOW Voltage 0.4 V IOL = 3mA

6686 FRM T06.4

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 2.7V

Symbol Parameter Max. Units Test Conditions

(3)

C

I/O

(3)

C

IN

Notes: (1) Must perform a stop command prior to measurement.

(2) VIL min. and VIH max. are f or ref erence only and are not 100% tested.
(3) This parameter is periodically sampled and not 100% tested.

Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (S1, S2, SCL)

11

6 pF V

I/O

IN

= 0V

= 0V

6686 FRM T07

X24F064/032/016

A.C. CONDITIONS OF TEST

Input Pulse Levels VCC x 0.1 to VCC x 0.9

EQUIVALENT A.C. LOAD CIRCUIT

2.7V

5V

Input Rise and
Fall Times 10ns

Input and Output
Timing Levels

X 0.5

V

CC

6686 FRM T08

OUTPUT

1533Ω

OUTPUT

100pF

1533Ω

100pF

6686 ILL F16.1

A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Write Cycle Limits

Symbol Parameter Min. Max. Units

f

SCL

T

I

SCL Clock Frequency 0 100 KHz
Noise Suppression Time

100 ns

Constant at SCL, SDA Inputs

t

AA

t

BUF

SCL LOW to SDA Data Out Valid 0.3 3.5 µs
Time the Bus Must Be Free Before a

4.7 µs

New Transmission Can Start

t

HD:STA

t

LOW

t

HIGH

t

SU:STA

Start Condition Hold Time 4 µs
Clock LOW Period 4.7 µs
Clock HIGH Period 4 µs
Start Condition Setup Time

4.7 µs

(for a Repeated Start Condition)

t

HD:DAT

t

SU:DAT

t

R

t

F

t

SU:STO

t

DH

Data In Hold Time 0 µs
Data In Setup Time 250 ns
SDA and SCL Rise Time 1 µs
SDA and SCL Fall Time 300 ns
Stop Condition Setup Time 4.7 µs
Data Out Hold Time 300 ns

6686 FRM T09.1

POWER-UP TIMING

(4)

Symbol Parameter Max. Units

t

PUR

t

PUW

Notes: (4) t

and t

PUR

are periodically sampled and not 100% tested.

Power-up to Read Operation 1 ms

Power-up to Write Operation 5 ms

are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters

PUW

12

6686 FRM T10

X24F064/032/016

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

6686 ILL F18

SCL

SDA 8th BIT

WORD n

ACK

t

WR

STOP

CONDITION

START

CONDITION

Bus Timing

t

LOW

SCL

SDA IN

SDA OUT

t

SU:STA

t

F

t

HD:STAtHD:DAT

t

HIGH

t

AA

Program Cycle Limits

Symbol Parameter Min. Typ.

(6)

t

PR

The program cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the program cycle, the

Program Cycle Time 5 10 ms

X24F064/032/016 bus interface circuits are disabled,
SDA is allowed to remain HIGH, and the device does
not respond to its slave address.

Bus Timing

t

DH

t

SU:DAT

(5)

t

R

t

SU:STO

t

BUF

6686 ILL F17

Max. Units

6686 FRM T11.1

Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (2.7V).

(6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum

time the device requires to automatically complete the internal program operation.

Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors

120
100

80
60

40

RESISTANCE (KΩ)

20

0

0

V

R

R

MIN.
RESISTANCE

20 40 60 80

BUS CAPACITANCE (pF)

CC MAX

=

MIN

I

OL MIN

t

R

=

MAX

C

MAX.
RESISTANCE

BUS

=1.2KΩ

100

120

6686 ILL F19.1

SYMBOL TABLE

13

X24F064/032/016

PACKAGING INFORMATION

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

PIN 1 INDEX

PIN 1

0.300

(7.62) REF.

0.060 (1.52)

0.020 (0.51)

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

SEATING

PLANE

0.150 (3.81)

0.125 (3.18)

0.015 (0.38)
MAX.

TYP. 0.010 (0.25)

0.110 (2.79)

0.090 (2.29)

0.325 (8.25)

0.300 (7.62)

0.065 (1.65)

0.045 (1.14)

0.020 (0.51)

0.016 (0.41)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.145 (3.68)

0.128 (3.25)

0.025 (0.64)

0.015 (0.38)

0°

15°

14

3926 FHD F01

X24F064/032/016

PACKAGING INFORMATION

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

PIN 1 INDEX

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

X 45°

PIN 1

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050" TYPICAL

0° – 8°

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

0.250"

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F22.1

15

0.050"
TYPICAL

0.030"

TYPICAL

8 PLACES

X24F064/032/016

PACKAGING INFORMATION

14-LEAD PLASTIC, TSSOP PACKAGE TYPE V

.025 (.65) BSC

0° – 8°

.0075 (.19)

.0118 (.30)

.193 (4.9)
.200 (5.1)

.019 (.50)
.029 (.75)

Detail A (20X)

.169 (4.3)
.177 (4.5)

.047 (1.20)

.002 (.05)
.006 (.15)

.010 (.25)

Gage Plane
Seating Plane

.252 (6.4) BSC

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

16

3926 FHD F32

X24F064/032/016

PACKAGING INFORMATION

20-LEAD PLASTIC, TSSOP PACKAGE TYPE V

.025 (.65) BSC

0° – 8°

.0075 (.19)
.0118 (.30)

.252 (6.4)
.300 (6.6)

.019 (.50)
.029 (.75)

Detail A (20X)

.169 (4.3)
.177 (4.5)

.047 (1.20)

.002 (.05)
.006 (.15)

.010 (.25)

Gage Plane
Seating Plane

.252 (6.4) BSC

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

17

3926 FHD F45

X24F064/032/016

ORDERING INFORMATION

Device

X24F064
X24F032
X24F016

Part Mark Convention

X24F064
X24F032
X24F016

X24FXXX X X

X24FXXX X

X

–X

Range

V

CC

Blank = 1.8V to 3.6V
5 = 4.5V to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C
E = Extended = –20°C to +85°C

I = Industrial = –40°C to +85°C

Package
X24F064

P = 8-Lead Plastic DIP

S = 8-Lead SOIC (JEDEC)
V = 20-Lead TSSOP

P = 8-Lead Plastic DIP
Blank = 8-Lead SOIC (JEDEC)

V = 14/20-Lead TSSOP

Blank = 1.8V to 3.6V, 0°C to +70°C
E = 1.8V to 3.6V, –20°C to +85°C
5 = 4.5V to 5.5V, 0°C to +70°C
I5 = 4.5V to 5.5V, –40°C to +85°C

X24F032
X24F016

P = 8-Lead Plastic DIP
S = 8-Lead SOIC (JEDEC)

V = 14-Lead TSSOP

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents ,
licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.

LIFE RELA TED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prev ent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) suppor t or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably e xpected to cause the
failure of the life support device or system, or to affect its saf ety or effectiveness.

18