XICOR X24F064VI-5, X24F064VI, X24F064VE-5, X24F032PE, X24F032P-5 Datasheet



A

PPLICATION NOTE

A V A I L A B L E

AN76 • AN78 • AN81 • AN87

64K/32K/16K

SerialFlash

X24F064/032/016

TM

Memory with Block Lock

FEATURES

1.8V to 3.6V or 5V “Univolt” Read and

•

Program Power Supply Versions
Low Power CMOS

•

—Active Read Current Less Than 1mA
—Active Program Current Less Than 3mA
—Standby Current Less Than 1 µ A

•

Internally Organized 8K/4K/2K x 8

•

New Programmable Block Lock Protection
—Software Write Protection
—Programmable hardware Write Protect

•

Block Lock (0, 1/4, 1/2, or all of the Flash
Memory array)
2 Wire Serial Interface

•

Bidirectional Data Transfer Protocol

•

32 Byte Sector Programming

•

Self Timed Program Cycle

•

—Typical Programming Time of 5ms

Per Sector

•

High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years

•

Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead TSSOP (X24F032/016)
—20-Lead TSSOP (X24F064)

8K/4K/2K x 8 Bit

TM

Protection

DESCRIPTION

The X24F064/032/016 is a CMOS SerialFlash
Memory Family, internally organized 8K/4K/2K x 8.
The family features a serial interface and software
protocol allowing operation on a simple two wire bus .

Device select inputs (S
devices to share a common two wire bus .

A Program Protect Register accessed at the highest
address location, provides three new programming
protection features: Software Programming Protection,
Block Lock Protection, and Hardware Programming
Protection. The Software Programming Protection
feature prevents any nonvolatile writes to the device
until the WEL bit in the program protect register is set.
The Block Lock

TM

Protection feature allows the user to
individually protect four bloc ks of the arra y b y prog ram­ming two bits in the programming protect register. The
Programmable Hardware Program Protect feature
allows the user to install each device with PP tied to
V

, program the entire memory array in place, and

CC

then enable the hardware programming protection by
programming a PPEN bit in the program protect
register. After this, selected blocks of the array,
including the program protect register itself, are
permanently protected from being programmed.

,

S

,

S

0

) allow up to eight

1

2

FUNCTIONAL DIAGRAM



SerialFlash
Protection are trademarks of Xicor, Inc.

6686-3.8 8/29/96 T3/C0/D0 SH

Memory and Block Lock

Xicor, 1995, 1996 Patents Pending



SDA

SCL

S0/S

S1/S

S2/S

PP

DATA REGISTER

SECTOR DECODE LOGIC

32 8

X

COMMAND

0

1

2

DECODE

AND CONTROL

LOGIC

PROGRAMMING

CONTROL LOGIC

1

DECODE

LOGIC

PROGRAM

PROTECT

REGISTER

SECTORED

MEMORY

ARRAY

HIGH VOLTAGE

CONTROL

6686 ILL F01.5

Characteristics subject to change without notice

X24F064/032/016

)

).

Xicor SerialFlash Memories are designed and tested for
applications requiring extended endurance. Inherent
data retention is greater than 100 years.

PIN DESCRIPTIONS
Serial Clock (SCL)

The SCL input is used to clock all data into and out of
the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.

An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the pull­up resistor selection graph at the end of this data
sheet.

Device Select (S

, S

, S

, S

, S

0

0

1

, S

1

2

2

The device select inputs are used to set the device
select bits of the 8-bit slave address. This allows
multiple devices to share a common bus. These inputs
can be static or actively driven. If used statically they
must be tied to V

SS

or V

as appropriate. If actively

CC

driven, they must be driven with CMOS levels (driven
to V

or V

CC

SS

Program Protect (PP)

The program protect input controls the hardware
program protect feature. When held LOW, hardware
program protection is disabled and the X24F064/
032/016 can be programmed normally. When this
input is held HIGH, and the PPEN bit in the
program protect register is set HIGH, program
protection is enabled, and nonvolatile writes are
disabled to the selected blocks as well as the
program protect register itself.

PIN CONFIGURATION

X24F016

8-LEAD DIP & SOIC

S0

1

S

2

1

3

S

2

4

VSS

8-LEAD DIP & SOIC

S0

1

S

2

1

S

3

2

VSS

4

8-LEAD DIP & SOIC

NC

1

S

2

1

S

3

2

VSS

4

X24F032

8
7
6
5

8
7
6
5

X24F064

8
7
6
5

VCC
PP
SCL
SDA

VCC
PP
SCL
SDA

VCC
PP
SCL
SDA

S

0

S

1

NC
NC
NC

S

2

V

SS

S

0

S

1

NC
NC
NC

S

2

V

SS

NC
NC

S

1

NC
NC
NC

S

2

V

SS
NC
NC

14-LEAD TSSOP

1
2
3
4
5
6
7

14-LEAD TSSOP

1
2
3
4
5
6
7

20-LEAD TSSOP

1
2
3
4
5
6
7
8
9
10

14
13
12
11
10

9
8

14
13
12

11

10

9
8

20
19
18
17
16
15
14
13
12

11

6686 ILL F02.4

V

CC

PP
NC
NC
NC
SCL
SDA

V
PP
NC
NC
NC
SCL
SDA

NC
V

CC

PP
NC
NC
NC
SCL
SDA
NC
NC

CC

PIN NAMES

Symbol Description

S

, S

, S

0

0

, S

, S

1

, S

1

2

2

Device Select Inputs

SDA Serial Data
SCL Serial Clock
PP Program Protect
V

SS

V

CC

Ground
Supply Voltage

NC No Connect

6686 FRM T01.1

2

X24F064/032/016

SCL

SDA

DATA STABLE DATA

CHANGE

6686 ILL F04

SCL

SDA

START BIT STOP BIT

6686 ILL F05

DEVICE OPERATION

The X24F064/032/016 supports a bidirectional bus ori­ented protocol. The protocol defines any device that
sends data onto the bus as a transmitter, and the re­ceiving device as the receiver. The device controlling
the transfer is a master and the device being controlled
is the slave. The master will always initiate data trans­fers, and provide the clock for both transmit and receive
operations. Therefore, the X24F064/032/016 will be
considered a slave in all applications.

Figure 1. Data Validity

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24F064/032/016 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition has
been met.

Notes: (5) Typical values are for T

(6) t

is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the

PR

device requires to perform the internal program operation.

= 25 ° C and nominal supply voltage (2.7V)

A

Figure 2. Definition of Start and Stop

3

X24F064/032/016

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus .

Acknowledge

Acknowledge is a software con v ention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans­mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Ref er to Figure 3.

Figure 3. Acknowledge Response From Receiver

SCL FROM

MASTER

DATA OUTPUT

FROM

TRANSMITTER

1

The X24F064/032/016 will respond with an acknowl­edge after recognition of a start condition and its slave
address. If both the device and a write operation have
been selected, the X24F064/032/016 will respond with
an acknowledge after the receipt of each subsequent
eight-bit word.

In the read mode the X24F064/032/016 will transmit
eight bits of data, release the SDA line and monitor
the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the
master, the X24F064/032/016 will continue to
transmit data. If an acknowledge is not detected, the
device will terminate further data transmissions. The
master must then issue a stop condition to return the
X24F064/032/016 to the standby power mode and
place the device into a known state.

8 9

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

6686 ILL F06

4

X24F064/032/016

BUS ACTIVITY:
MASTER

SDA LINE

BUS ACTIVITY:
X24F016/032/064

S
T
A
R
T

SLAVE

ADDRESS

S

S
T
O
P

P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

SECTOR ADDRESS DATA n DATA n+1 DATA n+31

6686 ILL F10.3

DEVICE ADDRESSING

Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next two bits are the device select bits. A system could
have up to eight X24F032/016’s on the bus or up to
four 24F064’s on the bus. The device addresses are
defined by the state of the S

0

, S

, and S

1

inputs. Note

2

some of the slave addresses must be the inverse of
the corresponding input pin.

Figure 4. Slave Address

X24F064

DEVICE
SELECT

S2

S2

DEVICE

TYPE

IDENTIFIER

1

S1 A12

DEVICE
SELECT

S1 S0

S2 S1

DEVICE

SELECT

HIGH ORDER

SECTOR ADDRESS

A10

A11

X24F032

HIGH ORDER

SECTOR ADDRESS

A10

A11

X24F016

HIGH ORDER

SECTOR ADDRESS

A10

S0

A9 A8 R/W

A9 A8 R/W

A9 A8 R/W

6686 ILL F07.4

Figure 5. Sector Programming

Also included in the slave address is an extension of
the array’s address which is concatenated with the
eight bits of address in the sector address field,
providing direct access to the entire SerialFlash
Memory array.

The last bit of the slave address defines the operation
to be performed. When set HIGH a read operation is
selected, when set LOW a program operation is
selected.

Following the start condition, the X24F064/032/016
monitors the SDA bus comparing the slave address
being transmitted with its slave address device type
identifier. Upon a correct comparison of the device
select inputs, the X24F064/032/016 outputs an
acknowledge on the SDA line. Depending on the state
of the R/W

bit, the X24F064/032/016 will execute a

read or program operation.

PROGRAMMING OPERATIONS

The X24F064/032/016 offers a 32-byte sector pro­gramming operation. For a program operation, the
X24F064/032/016 requires a second address field.
This field contains the address of the first byte in the
sector. Upon receipt of the address, comprised of
eight bits, the X24F064/032/016 responds with an ac­knowledge and awaits the next eight bits of data,
again responding with an acknowledge. The master
then transmits 31 more bytes. After the receipt of
each byte, the X24F064/032/016 will respond with an
acknowledge.

5

X24F064/032/016

Flow 1. ACK Polling Sequence

PROGRAM OPERATION

COMPLETED

ENTER ACK POLLING

ISSUE
START

ISSUE SLAVE

ADDRESS AND R/W = 0

ACK

RETURNED?

YES

NEXT

OPERATION

A WRITE?

YES

ISSUE SECTOR

ADDRESS

PROCEED

NO

NO

ISSUE STOP

ISSUE STOP

PROCEED

After the receipt of each byte, the five low order ad­dress bits are internally incremented by one. The high
order bits of the sector address remain constant. If the
master should transmit more or less than 32 bytes prior
to generating the stop condition, the contents of the
sector cannot be guaranteed. All inputs are disabled
until completion of the internal program cycle. Refer to
Figure 5 for the address, acknowledge and data trans­fer sequence.

Acknowledge Polling

The Max Write Cycle Time can be significantly reduced
using Acknowledge Polling. To initiate Acknowledge
Polling, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle, then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
Refer to Flow 1.

READ OPERATIONS

Read operations are initiated in the same manner as
program operations with the exception that the R/W bit
of the slave address is set HIGH. There are three basic
read operations: current address read, random read
and sequential read.

It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read op­eration, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.

6686 ILL F09.1

6