XICOR X24C01APM-3,5, X24C01APM-3, X24C01APM, X24C01API-3,5, X24C01API-3 Datasheet

X24C01A

1

DESCRIPTION

The X24C01A is a CMOS 1024 bit serial E2PROM,
internally organized 128 x 8. The X24C01A features a
serial interface and software protocol allowing operation
on a simple two wire bus. Three address inputs allow up
to eight devices to share a common two wire bus.

Xicor E2PROMs are designed and tested for applica­tions requiring extended endurance. Inherent data re­tention is greater than 100 years. Available in an eight
pin DIP and SOIC package.

FEATURES

• 2.7V to 5.5V Power Supply

• Low Power CMOS

—Active Current Less Than 1 mA
—Standby Current Less Than 50 µA

• Internally Organized 128 x 8

• Self Timed Write Cycle

—Typical Write Cycle Time of 5 ms

• 2 Wire Serial Interface

—Bidirectional Data Transfer Protocol

• Four Byte Page Write Operation

—Minimizes Total Write Time Per Byte

• High Reliability

—Endurance: 100,000 Cycles
—Data Retention: 100 Years

• New Hardwire – Write Control Function

© Xicor, 1991 Patents Pending Characteristics subject to change without notice

1K X24C01A 128 x 8 Bit

Serial E

2

PROM

Preliminary Information

FUNCTIONAL DIAGRAM

3841 FHD F01

START

STOP

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

REGISTER

+COMPARATOR

H.V. GENERATION

TIMING

& CONTROL

WORD
ADDRESS
COUNTER

XDEC

YDEC

D

OUT

ACK

E

2

PROM

32x32

DATA REGISTER

START CYCLE

(8) V

CC

R/W

PIN

(4) V

SS

(5) SDA

(6) SCL

(3) A

2

(2) A

1

(1) A

0

D

OUT

LOAD INC

CK

8

(7) WC

3841-1

X24C01A

2

PIN DESCRIPTIONS
Serial Clock (SCL)

The SCL input is used to clock all data into and out of the
device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs.

An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Guide­lines for Calculating Typical Values of Bus Pull-Up
Resistors graph.

Address (A0, A1, A2)

The address inputs are used to set the least significant
three bits of the seven bit slave address. These inputs
can be static or actively driven. If used statically they
must be tied to VSS or VCC as appropriate. If actively
driven, they must be driven to VSS or to VCC.

WRITE CONTROL (WC)

The Write Control input controls the ability to write to the
device. When WC is LOW (tied to VSS) the X24C01A will
be enabled to perform write operations. When WC is
HIGH (tied to VCC) the internal high voltage circuitry will
be disabled and all writes will be disabled.

DEVICE OPERATION

The X24C01A supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the trans­fer is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera­tions. Therefore, the X24C01A will be considered a
slave in all applications.

V

CC

WC
SCL
SDA

A

0

A

1

A

2

V

SS

1
2
3
4

8
7
6
5

X24C01A

PIN CONFIGURATION

3841 FHD F02

PIN NAMES

Symbol Description

A0–A

2

Address Inputs
SDA Serial Data
SCL Serial Clock
WC Write Control
V

SS

Ground
V

CC

+5V

3841 PGM T01

Clock and Data Conventions

Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re­served for indicating start and stop conditions. Refer to
Figures 1 and 2.

Start Condition

All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C01A continuously monitors the SDA
and SCL lines for the start condition and will not respond
to any command until this condition has been met.

DIP/SOIC

X24C01A

3

Figure 1. Data Validity

Figure 2. Definition of Start and Stop

Stop Condition

All communications must be terminated by a stop condi­tion, which is a LOW to HIGH transition of SDA when SCL
is HIGH. The stop condition is also used by the X24C01A
to place the device into the standby power mode after a
read sequence. A stop condition can only be issued after
the transmitting device has released the bus.

Acknowledge

Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device will
release the bus after transmitting eight bits. During the
ninth clock cycle the receiver will pull the SDA line LOW
to acknowledge that it received the eight bits of data.
Refer to Figure 3.

The X24C01A will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been se­lected, the X24C01A will respond with an acknowledge
after the receipt of each subsequent eight bit word.

In the read mode the X24C01A will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24C01A
will continue to transmit data. If an acknowledge is not
detected, the X24C01A will terminate further data trans­missions. The master must then issue a stop condition
to return the X24C01A to the standby power mode and
place the device into a known state.

Figure 3. Acknowledge Response From Receiver

SCL

SDA

DATA STABLE DATA

CHANGE

3841 FHD F05

3841 FHD F06

3841 FHD F07

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

1

89

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

SCL

SDA

START BIT STOP BIT

X24C01A

4

DEVICE ADDRESSING

Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24C01A this is fixed as
1010[B].

Following the start condition, the X24C01A monitors the
SDA bus comparing the slave address being transmit­ted with its slave address (device type and state of A0,
A1 and A2 inputs). Upon a correct compare the X24C01A
outputs an acknowledge on the SDA line. Depending on
the state of the R/W bit, the X24C01A will execute a read
or write operation.

WRITE OPERATIONS
Byte Write

For a write operation, the X24C01A requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 128 words of memory. Note: the most significant bit
is a don’t care. Upon receipt of the word address the
X24C01A responds with an acknowledge, and awaits
the next eight bits of data, again responding with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the X24C01A
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24C01A
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.

Figure 4. Slave Address

The next three significant bits address a particular
device. A system could have up to eight X24C01A
devices on the bus (see Figure 10). The eight addresses
are defined by the state of the A0, A1 and A2 inputs.

The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.

Figure 5. Byte Write

Figure 6. Page Write

101 0 A2 A1 A0 R/W

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESS

3841 FHD F08

3841 FHD F09

BUS ACTIVITY:
MASTER

SDA LINE

BUS ACTIVITY:
X24C01A

S
T
A
R
T

SLAVE

ADDRESS

S

S
T
O
P

P

A
C
K

A
C
K

A
C
K

WORD

ADDRESS DATA

3841 FHD F10

BUS ACTIVITY:
MASTER

SDA LINE

BUS ACTIVITY:
X24C01A

S
T
A
R
T

SLAVE

ADDRESS

S

S
T

O

P
P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

WORD ADDRESS n DATA n DATA n–1 DATA n+3

NOTE: In this example n = xxxx 0000 (B); x = 1 or 0