查询X24C00供应商
APPLICATION NOTES
AVAILABLE
AN4 • AN12 • AN22 • AN26 • AN32
X24C00
128 Bit X24C00 16 x 8 Bit
FEATURES
• 2.7V to 5.5V Power Supply
• 128 Bit Serial E
2
PROM
• Low Power CMOS
—Active Current Less Than 3mA
—Standby Current Less Than 50µA
• Internally Organized 16 x 8
• 2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
• Byte Mode Write
• Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
• Push/Pull Output
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• Available Packages
—8-Lead MSOP
—8-Lead PDIP
—8-Lead SOIC
Serial E
2
PROM
DESCRIPTION
The X24C00 is a CMOS 128 bit serial E2PROM, internally organized as 16 x 8. The X24C00 features a serial
interface and software protocol allowing operation on a
simple two wire bus.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
The X24C00 is fabricated with Xicor’s Advanced CMOS
Floating Gate technology.
FUNCTIONAL DIAGRAM
SCL
SDA
CONTROL
LOGIC
INPUT/
OUTPUT
BUFFER
COMMAND/ADDRESS
REGISTER
SHIFT REGISTER
MEMORY ARRA Y
3836 FHD F01
PIN CONFIGURATION
MSOP/DIP/SOIC
1
NC
NC
2
NC
3
V
SS
4
X24C00
8
V
CC
7
NC
6
SCL
5
SDA
3836 FHD F02.1
© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
3836-1.5 6/10/96 T2/C1/D0 NS
1
X24C00
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is a push/pull output and does not
require the use of a pull-up resistor.
PIN NAMES
Symbol Description
NC No Connect
V
SS
V
CC
Ground
Supply Voltage
SDA Serial Data
SCL Serial Clock
3836 PGM T01
DEVICE OPERATION
The X24C00 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. Therefore, the X24C00 will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C00 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
A start may be issued to terminate the input of a control
word or the input of data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start
cannot be generated while the part is outputting data.
Starts are also inhibited while a write is in progress.
Stop Condition
The stop condition is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is used to reset
the device during a command or data input sequence
and will leave the device in the standby mode. As with
starts, stops are inhibited when outputting data and
while a write is in progress.
Write Operation
The byte write operation is initiated with a start condition.
The start condition is followed by an eight bit control byte
which consists of a two bit write command (0,1), four
address bits, and two “don’t care” bits (Figure 3).
2
X24C00
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
Figure 2. Definition of Start and Stop Conditions
SCL
SDA
START CONDITION STOP CONDITION
Figure 3. Control Byte
C1
START
C2 A3 A2 A1 A0 XX XX
CHANGE
3836 FHD F03
3836 FHD F04
3836 FHD F05
3
X24C00
After receipt of the control byte, the X24C00 will enter
the write mode and await the data to be written. This data
is shifted into the device on the next eight SCL clocks.
Once eight clocks have been received, the data in the
shift register will be written into the memory array. While
the write is in progress the X24C00 will not respond to
any inputs. At any time prior to clocking in the last data
bit, a stop command or a new start command will
terminate the operation. If a start command is given, the
X24C00 will reset all counters and will prepare to clock
in the next control byte. If a stop command is given, the
X24C00 will reset all counters and await the next start
command.
At the end of the write the X24C00 will automatically
reset all counters and enter the standby mode.
(Figure 4).
Figure 4. Write Sequence
0
START
1 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0
Read Operation
The byte read operation is initiated with a start condition.
The start condition is followed by an eight-bit control byte
which consists of a two-bit read command (1,0), four
address bits, and two “don’t care” bits. After receipt of
the control byte the X24C00 will enter the read mode and
transfer data into the shift register from the array. This
data is shifted out of the device on the next eight SCL
clocks. At the end of the read, all counters are reset and
the X24C00 will enter the standby mode. As with a write,
the read operation can be interrupted by a start or stop
condition while the command or address is being clocked
in. While clocking data out, starts or stops cannot be
generated.
During the second don’t care clock cycle, starts and
stops are ignored. The master must free the bus prior to
the end of this clock cycle to allow the X24C00 to begin
outputting data (Figures 5 and 6).
3836 FHD F06
Figure 5. Read Sequence
START
Figure 6. Read Cycle Timing
SCK
SDA IN
SDA OUT
6781
A0 XX XX
1
0 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0
SYMBOL TABLE
WAVEFORM
D7 D6
3836 FHD F08
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
3836 FHD F07
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
4
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