Datasheet X24320V14I, X24320V14-2,5, X24320V14-1,8, X24320V14, X24320S8I-2,5 Datasheet (XICOR)

400KHz 2-Wire Serial E

2

PROM with Block Lock

TM

32K

4K x 8 Bit



Xicor, 1995, 1996 Patents Pending Characteristics subject to change without notice

7035-1.2 4/25/97 T0/C2/D0 SH

1

X24320

FUNCTIONAL DIAGRAM

FEATURES

•

Save Critical Data with Programmable
Block Lock Protection
—Block Lock (0, 1/4, 1/2, or all of E

2

PROM Array)
—Software Write Protection
—Programmable Hardware Write Protect

•

In Circuit Programmable ROM Mode

•

400KHz 2-Wire Serial Interface
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce

Noise Elimination

•

Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1 µ A

•

1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Versions

•

32 Wor d Page Write Mode
—Minimizes T otal Write Time Per W ord

•

Internally Organized 4K x 8

•

Bidirectional Data Transfer Protocol

•

Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms

•

High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years

•

8-Lead SOIC

•

14-Lead TSSOP

•

8-Lead PDIP

DESCRIPTION

The X24320 is a CMOS Serial E

2

PROM, internally
organized 4K x 8. The device features a serial inter­face and software protocol allowing operation on a
simple two wire bus. The bus operates at 400 KHz all
the way down to 1.8V.

Three device select inputs (S

0

–S

2

) allow up to eight

devices to share a common two wire bus .
A Write Protect Register at the highest address loca-

tion, FFFFh, provides three write protection features:
Software Write Protect, Block Lock Protect, and
Programmable Hardware Write Protect. The Software
Write Protect feature prev ents any nonvolatile writes to
the device until the WEL bit in the Write Protect
Register is set. The Block Lock Protection feature
gives the user four array block protect options, set by
programming two bits in the Write Protect Register.
The Programmable Hardware Write Protect feature
allows the user to install the device with WP tied to
V

CC

, write to and Block Lock the desired portions of
the memory array in circuit, and then enable the In
Circuit Programmable ROM Mode b y prog r amming the
WPEN bit HIGH in the Write Protect Register. After
this, the Block Locked portions of the array, including
the Write Protect Register itself, are permanently
protected from being erased.

SERIAL E2PROM DATA
AND ADDRESS (SDA)

SCL

S2
S1
S0

WP

COMMAND

DECODE

AND

CONTROL

LOGIC

BLOCK LOCK AND

WRITE PROTECT
CONTROL LOGIC

DEVICE

SELECT

LOGIC

WRITE

PROTECT

REGISTER

PAGE

DECODE

LOGIC

DATA REGISTER

Y DECODE LOGIC

1K x 8

1K x 8

2K x 8

WRITE VOLTAGE

CONTROL

SERIAL E

2

PROM

ARRAY

4K x 8

7035 FM 01

X24320

2

Xicor E

2

PROMs are designed and tested for applica­tions requiring extended endurance. Inherent data
retention is greater than 100 years.

PIN DESCRIPTIONS
Serial Clock (SCL)

The SCL input is used to clock all data into and out of
the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.

An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull­up resistor selection graph at the end of this data
sheet.

Device Select (S

0

, S

1

, S

2

)

The device select inputs (S

0

, S

1

, S

2

) are used to set
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to V

SS

or V

CC

as appro­priate. If actively driven, they must be driven with
CMOS levels (driven to V

CC

or V

SS

).

Write Protect (WP)

The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write
Protection is disabled. When this input is held HIGH,
and the WPEN bit in the Wr ite Protect Register is set
HIGH, the Write Protect Register is protected,
preventing changes to the Block Lock Protection and
WPEN bits.

PIN NAMES

7035 FM T01

PIN CONFIGURATION

Symbol Description

S

0

, S

1

, S

2

Device Select Inputs

SDA Serial Data
SCL Serial Clock
WP Write Protect
V

SS

Ground

V

CC

Supply Voltage

NC No Connect

V

CC

WP
SCL
SDA

S

0

S

1

S

2

VSS

1
2
3
4

8
7
6
5

X24320

8-Lead DIP/SOIC

7035 FM 02

V

CC

WP

SCL

S

0

S

1

NC

1
2
3
4

8

7

6

5

V

SS

SDA

NC
NC

NC

NC

NC

S

2

* .244”

.252”

* .197”

.200”

9

10

11

12

13

14

Not to scale

X24320

* SOIC Measurement

14-Lead TSSOP

X24320

3

DEVICE OPERATION

The device supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data trans­fers, and provide the clock for both transmit and
receive operations. Therefore, the device will be
considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.

Start Condition

All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SCL

SDA

DATA STABLE DATA

CHANGE

7035 FM 03

SCL

SDA

START BIT STOP BIT

7035 FM 04

Figure 1. Data Validity

Figure 2. Definition of Start and Stop

X24320

4

Figure 3. Acknowledge Response From Receiver

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus .

Acknowledge

Acknowledge is a software con v ention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans­mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Ref er to Figure 3.

The device will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.

In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans­missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.

SCL FROM

MASTER

DATA OUTPUT

FROM

TRANSMITTER

1

8 9

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

7035 FM 05

X24320

5

Figure 4. Device Addressing

1

S1S

0

R/W

DEVICE

SELECT

0 1 0 S

2

DEVICE TYPE

IDENTIFIER

SLAVE ADDRESS BYTE

D7 D2 D1D6 D5 D4 D3

DATA BYTE

A2 A1 A0

A5

LOW ORDER WORD ADDRESS

A4 A3

WORD ADDRESS BYTE 0

0 A10 A9 A80

HIGH ORDER WORD ADDRESS

A11

X24320WORD ADDRESS BYTE 1

0 0

A7 A6

D0

7035 FM 06

DEVICE ADDRESSING

Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the de vice type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S

0

, S

1

, and S

2

. This allows up to 8
devices to share a single bus. These bits are
compared to the S

0

, S

1

, and S

2

device select input
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a read operation is selected. When it is zero then
a write operation is selected. Refer to figure 4. After
loading the Slave Address Byte from the SDA bus, the
device compares the device type bits with the value
“1010” and the device select bits with the status of the

device select input pins. If the compare is not successful,
no acknowledge is output during the ninth clock cycle
and the device returns to the standby mode.

The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in figure 4.

The internal organization of the E

2

array is 128 pages by
32 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 5 of the Word Address Byte 0. The byte
address is contained in bits 4 through 0 of the Word
Address Byte 0. See figure 4.

X24320

6

Figure 6. Page Write Sequence

WRITE OPERATIONS
Byte Write

For a write operation, the device requires the Slave
Address Byte, the Word Address Byte 1, and the Word
Address Byte 0, which gives the master access to any
one of the words in the array. Upon receipt of the Word
Address Byte 0, the device responds with an acknowl­edge, and waits for the first eight bits of data. After
receiving the 8 bits of the data byte, the device again
responds with an acknowledge. The master then
terminates the transfer by generating a stop condition,
at which time the device begins the internal write cycle
to the nonvolatile memory. While the internal write
cycle is in progress the device inputs are disabled
and the device will not respond to any requests from
the master. The SDA pin is at high impedance. See
figure 5.

Page Write

The device is capable of a thirty-two byte page write
operation. It is initiated in the same manner as the byte
write operation; but instead of terminating the write
operation after the first data word is transferred, the

master can transmit up to thirty-one more words. The
device will respond with an acknowledge after the
receipt of each word, and then the byte address is
internally incremented by one. The page address
remains constant. When the counter reaches the end
of the page, it “rolls over” and goes back to the first
byte of the current page. This means that the master
can write 32 words to the page beginning at any byte.
If the master begins writing at byte 16, and loads 32
words, then the first 16 words are written to bytes 16
through 31, and the last 16 words are written to bytes
0 through 15. Afterwards, the address counter would
point to byte 16. If the master writes more than 32
words, then the previously loaded data is overwritten
by the new data, one byte at a time .

The master terminates the data byte loading by
issuing a stop condition, which causes the device to
begin the nonvolatile write cycle. As with the byte write
operation, all inputs are disabled until completion of
the internal write cycle. Refer to figure 6 for the
address, acknowledge, and data tr ansf er sequence.

S
T
A
R
T

SLAVE

ADDRESS

S
T
O
P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

DATA

(0)

SIGNALS
FROMTHE
MASTER

SDA BUS

SIGNALS
FROMTHE
SLAVE

(n)

WORDADDRESS

BYTE 1

WORDADDRESS

BYTE 0

0S P

DATA

1 0 1 0

(0≤n≤31)

7035 FM 08

Figure 5. Byte Write Sequence

SIGNALS
FROMTHE
MASTER

SDA BUS

SIGNALS
FROMTHE
SLAVE

S

T
A
R

T

SLAVE

ADDRESS

S

T
O
P

A
C
K

A
C
K

A
C
K

A
C
K

WORDADDRESS

BYTE 1

DATA

1 0 1 0 0

WORDADDRESS

BYTE 0

S P

7035 FM 07

X24320

7

Acknowledge Polling

The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a star t condi­tion followed by the Slave Address Byte for a wr ite or
read operation. If the device is still busy with the
internal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned and the host can then proceed
with the read or write operation. Ref er to figure 7 .

BYTE LOAD COMPLETED

BY ISSUING STOP.

ENTER ACK POLLING

ISSUE
START

ISSUE SLAVE

ADDRESS BYTE

(READ OR WRITE)

ACK

RETURNED?

HIGH

VOLTAGE

CYCLE COMPLETE.

CONTINUE

SEQUENCE?

CONTINUE NORMAL

READ ORWRITE

COMMAND SEQUENCE

PROCEED

ISSUE STOP

NO

YES

YES

ISSUE STOP

NO

7035 FM 09

READ OPERATIONS

Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads,
Random Reads, and Sequential Reads.

Current Address Read

Internally, the device contains an address counter that
maintains the address of the last word read or written
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address on the same page.

Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to figure 8 for
the address, acknowledge, and data transfer
sequence.

It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi­tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.

FROM THE

S
T
A
R
T

SLAVE

ADDRESS

S
T
O
P

A
C
K

DATA

SIGNALS
FROM THE
MASTER

SDA BUS

SIGNALS
SLAVE

1S P0 1 0 1

7035 FM 10

Figure 7. Acknowledge Polling Sequence

Figure 8. Current Address Read Sequence

X24320

8

Random Read

Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W

bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
Address Byte 0. After the device acknowledges receipt
of the W ord Address Byte 0, the master issues another
start condition and the Slave Address Byte with the
R/W

bit set to one. This is followed by an acknowledge
and then eight bits of data from the device. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
Refer to figure 9 for the address, acknowledge, and
data transfer sequence.

The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the
second start shown in figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper­ation is that the new address is loaded into the
address counter, b ut no data is output by the de vice .

The next Current Address Read operation will read
from the newly loaded address.

Sequential Read

Sequential reads can be initiated as either a current
address read or random read. The first Data Byte is
transmitted as with the other modes; however, the
master now responds with an acknowledge, indicating
it requires additional data. The device continues to
output data for each acknowledge received. The
master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition.

The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all byte
addresses, allowing the entire memory contents to be
read during one operation. At the end of the address
space the counter “rolls over” to address 0000h and the
device continues to output data for each acknowledge
received. Refer to figure 10 for the acknowledge and
data transfer sequence.

SLAVE

ADDRESS

S

S
T
O
P

A
C
K

A
C
K

A
C
K

A
C
K

DATA

(1)

DATA

(2)

SIGNALS
FROM THE
MASTER

SDA BUS

SIGNALS
FROM THE
SLAVE

DATA

(n–1)

DATA

(n)

1

(n is any integer greater than 1)

P

7035 FM 12

SIGNALS
FROMTHE
MASTER

SDA BUS

SIGNALS
FROMTHE
SLAVE

S
T
A

R

T

SLAVE

ADDRESS

S
T
O
P

A
C
K

A
C
K

A
C
K

WORDADDRESS

BYTE 1

SLAVE

ADDRESS

0

WORDADDRESS

BYTE 0

S
T
A

R

T

1

DATA

A
C
K

S PS1 0 1 0

7035 FM 11

Figure 9. Random Read Sequence

Figure 10. Sequential Read Sequence

X24320

9

WRITE PROTECT REGISTER (WPR)

Writing to the Write Protect Register

The Write Protect Register can only be modified by

performing a “Byte Write” operation directly to the

address FFFFh as described below.

The Data Byte must contain zeroes where indicated in

the procedural descriptions below; otherwise the oper-

ation will not be performed. Only one Data Byte is

allowed for each register write operation. The part will

not acknowledge any data bytes after the first byte is

entered. The user then has to issue a stop to initiate

the nonvolatile write cycle that writes BL0, BL1, and

WPEN to the nonvolatile bits. A stop must also be

issued after volatile register write operations to put the

device into Standby.

The state of the Write Protect Register can be read by

performing a random byte read at FFFFh at any time.

The part will reset itself after the first byte is read. The

master should supply a stop condition to be consistent

with the protocol, but a stop is not required to end this

operation. After the read, the address counter contains

0000h.

Write Protect Register: WPR (ADDR = FFFF

h

)

WEL: Write Enable Latch (Volatile)

0 = Write Enable Latch reset, writes disabled.

1 = Write Enable Latch set, writes enabled.

RWEL: Register Write Enable Latch (Volatile)

0 = Register Write Enable Latch reset, writes to the

Write Protect Register disabled.

1 = Register Write Enable Latch set, writes to the Write

Protect Register enabled.

BL0, BL1: Block Lock Protect Bits (Nonvolatile)

The Block Lock Protect Bits, BL0 and BL1, determine

which blocks of the array are protected. A write to a

protected block of memory is ignored, but will receive

an acknowledge. The master must issue a stop to put

the part into standby, just as it would for a valid write;

but the stop will not initiate an internal nonvolatile write

cycle. See figure 11.

WPEN: Write Protect Enable Bit (Nonvolatile)

The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Write Protect Register
control the Programmable Hardware Write Protection
feature. Hardware Write Protection is enabled when
the WP pin is HIGH and the WPEN bit is HIGH, and
disabled when either the WP pin is LOW or the WPEN
bit is LOW. Figure 12 defines the write protect status
for each combination of WPEN and WP. When the
chip is Hardware Write Protected, nonvolatile writes
are disabled to the Write Protect Register, including
the Block Lock Protect bits and the WPEN bit itself, as
well as to the Block Lock protected sections in the
memory array. Only the sections of the memory array
that are not Block Lock protected, and the volatile bits
WEL and RWEL, can be written.

In Circuit Programmable ROM Mode

Note that when the WPEN bit is write protected, it
cannot be changed back to a LOW state; so write
protection is enabled as long as the WP pin is held
HIGH. Thus an In Circuit Programmable ROM function
can be implemented by hardwiring the WP pin to V

CC

,
writing to and Block Locking the desired portion of the
array to be ROM, and then progr amming the WPEN bit
HIGH.

Unused Bit Positions

Bits 0, 5 & 6 are not used. All writes to the WPR must
have zeros in these bit positions. The data byte output
during a WPR read will contain zeros in these bits.

Writing to the WEL and RWEL bits

WEL and RWEL are volatile latches that power up in
the LOW (disabled) state. While the WEL bit is LOW,
writes to any address other than FFFFh will be ignored
(no acknowledge will be issued after the Data Byte).
The WEL bit is set by writing 00000010 to address
FFFFh. Once set, WEL remains HIGH until either it is
reset to 0 (by writing 00000000 to FFFFh) or until the
part powers up again. Writes to WEL and RWEL do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.

The RWEL bit controls writes to the Block Lock Protect
bits, BL0 and BL1, and the WPEN bit. If RWEL is 0
then no writes can be performed on BL0, BL1, or
WPEN. RWEL is reset when the device powers up or
after any nonvolatile write, including writes to the Block
Lock Protect bits, WPEN bit, or any bytes in the
memory array. When RWEL is set, WEL cannot be

7 6 5 4 3 2 1 0

WPEN 0 0 BL1 BL0 RWEL WEL 0

X24320

10

reset, nor can RWEL and WEL be reset in one write
operation. RWEL can be reset by writing 00000010 to
FFFFh; but this is the same operation as in step 3
described below, and will result in programing BL0,
BL1, and WPEN.

Writing to the BL and WPEN Bits

A 3 step sequence is required to change the nonvola­tile Block Lock Protect or Write Protect Enable bits:

1) Set WEL=1, Write 00000010 to address FFFFh
(Volatile Write Cycle.)

2) Set RWEL=1, Write 00000110 to address FFFFh
(Volatile Write Cycle.)

3) Set BL1, BL0, and/or WPEN bits, Write u00xy010 to
address FFFFh, where u=WPEN, x=BL1, and y=BL0.
(Nonvolatile Wr ite Cycle.)

The three step sequence was created to make it diffi­cult to change the contents of the Write Protect
Register accidentally. If WEL was set to one by a
previous register write operation, the user may start at

step 2. RWEL is reset to zero in step 3 so that user is
required to perform steps 2 and 3 to make another
change. RWEL must be 0 in step 3. If the RWEL bit in
the data byte for step 3 is a one, then no changes are
made to the Write Protect Register and the device
remains at step 2.

The WP pin must be LOW or the WPEN bit must be
LOW before a nonvolatile register write operation is
initiated. Otherwise, the write operation will abort and
the device will go into standby mode after the master
issues the stop condition in step 3.

Step 3 is a nonvolatile write operation, requiring t

WC

to
complete (acknowledge polling may be used to reduce
this time requirement). It should be noted that step 3
MUST end with a stop condition. If a start condition is
issued during or at the end of step 3 (instead of a stop
condition) the device will abort the nonvolatile register
write and remain at step 2. If the operation is aborted
with a start condition, the master must issue a stop to
put the device into standby mode.

ABSOLUTE MAXIMUM RATINGS*

Figure 11. Block Lock Protect Bits and Protected Addresses

7003 FRM T02

Figure 12. WP Pin and WPEN Bit Functionality

7003 FRM T03

BL1 BL0 Protected Addresses Array Location

0 0

None

No Protect

0 1

C00h - FFFh

Upper 1/4

1 0

800h - FFFh

Upper 1/2

1 1

000h - FFFh

Full Array

WP WPEN

Memory Array Not

Lock Block Protected

Memory Array Block

Lock Protected

Block Lock Bits

WPEN

Bit

0 X Writable Protected Unprotected Unprotected

X 0 Writable Protected Unprotected Unprotected

1 1 Writable Protected Protected Protected

X24320

11

Temperature under Bias

X24320.......................................–65°C to +135°C

Storage Temperature........................–65°C to +150°C

Voltage on any Pin with

Respect to VSS....................................–1V to +7V

D.C. Output Current..............................................5mA

Lead Temperature

(Soldering, 10 seconds) ..............................300°C

D.C. OPERATING CHARACTERISTICS

7003 FRM T06

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

7003 FRM T07

Notes: (1) Must perform a stop command prior to measurement.

(2) V

IL

min. and VIH max. are f or ref erence only and are not 100% tested.

(3) This par ameter is periodically sampled and not 100% tested.

Limits

Symbol Parameter Min. Max. Units Test Conditions

I

CC1

VCC Supply Current (Read) 1 mA SCL = VCC X 0.1/VCC X 0.9 Levels

@ 400KHz, SDA = Open, All Other
Inputs =

V

SS

or VCC – 0.3V

I

CC2

VCC Supply Current (Write) 3 mA

I

SB1

(1)

VCC Standby Current 5 µA SCL = SDA = VCC, All Other

Inputs =

V

SS

or VCC – 0.3V,

V

CC

= 5V ± 10%

I

SB2

(1)

VCC Standby Current 1 µA SCL = SDA = VCC, All Other

Inputs =

V

SS

or VCC – 0.3V,

V

CC

= 2.5V

I

LI

Input Leakage Current 10 µA

V

IN

= VSS to V

CC

I

LO

Output Leakage Current 10 µA

V

OUT

= VSS to V

CC

V

lL

(2)

Input LOW Voltage –0.5 VCC x 0.3 V

V

IH

(2)

Input HIGH Voltage VCC x 0.7 VCC + 0.5 V

V

OL

Output LOW Voltage 0.4 V IOL = 3mA

V

hys

(3)

Hysteresis of Schmitt
Trigger Inputs

V

CC

x 0.05 V

Symbol Parameter Max. Units Test Conditions

C

I/O

(3)

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

C

IN

(3)

Input Capacitance (S0, S1, S2, SCL, WP) 6 pF VIN = 0V

RECOMMENDED OPERATING CONDITIONS

7003 FRM T04

Temperature Min. Max.

Commercial 0°C +70°C

Industrial –40°C +85°C

7003 FRM T05

Supply Voltage Limits

X24320 4.5V to 5.5V
X24320–2.5 2.5V to 5.5V
X24320–1.8 1.8V to 3.6V

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended per iods may
affect device reliability.

X24320

12

A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Write Cycle Limits

7003 FRM T09

POWER-UP TIMING

(4)

7003 FRM T10

Notes: (4) t

PUR

and t

PUW

are the delays required from the time VCC is stable until the specified operation can be initiated. These par ameters

are periodically sampled and not 100% tested.

Symbol Parameter Min. Max. Units

f

SCL

SCL Clock Frequency 0 400 KHz

t

I

Noise Suppression Time
Constant at SCL, SDA Inputs

50 ns

t

AA

SCL LOW to SDA Data Out Valid 0.1 0.9 µs

t

BUF

Time the Bus Must Be Free Before a
New Transmission Can Start

1.2 µs

t

HD:STA

Start Condition Hold Time 0.6 µs

t

LOW

Clock LOW Period 1.2 µs

t

HIGH

Clock HIGH Period 0.6 µs

t

SU:STA

Start Condition Setup Time
(for a Repeated Start Condition)

0.6 µs

t

HD:DAT

Data In Hold Time 0 µs

t

SU:DAT

Data In Setup Time 100 ns

t

R

SDA and SCL Rise Time 300 ns

t

F

SDA and SCL Fall Time 300 ns

t

SU:STO

Stop Condition Setup Time 0.6 µs

t

DH

Data Out Hold Time 50 300 ns

t

OF

Output Fall Time

20+0.1C

b

(5)

Symbol Parameter Max. Units

t

PUR

Power-up to Read Operation 1 ms

t

PUW

Power-up to Write Operation 5 ms

A.C. CONDITIONS OF TEST

7003 FRM T08

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and

Fall Times 10ns
Input and Output

Timing Levels

V

CC

X 0.5

EQUIVALENT A.C. LOAD CIRCUIT

5V

1.53KΩ

100pF

OUTPUT

7035 FM 13

X24320

13

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

Must be
steady

Will be
steady

May change
from Low to
High

Will change
from Low to
High

May change
from High to
Low

Will change
from High to
Low

Don’t Care:
Changes
Allowed

Changing:
State Not
Known

N/A Center Line

is High
Impedance

7035 FM 17

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24320 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slav e address.

Bus Timing

t

SU:STA

t

HD:STAtHD:DAT

t

SU:DAT

t

LOW

t

SU:STO

t

R

t

BUF

SCL

SDA IN

SDA OUT

t

DH

t

AA

t

F

t

HIGH

7035 FM 14

Write Cycle Limits

7003 FRM T11

Symbol Parameter Min. Typ.

(5)

Max. Units

t

WC

(6)

Write Cycle Time 5 10 ms

SCL

SDA 8th BIT

WORD n

ACK

t

WC

STOP

CONDITION

START

CONDITION

7035 FM 15

Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors

120
100

80

40

60

20

20 40 60 80

100 120

0

0

RESISTANCE (KΩ)

BUS CAPACITANCE (pF)

MIN.
RESISTANCE

MAX.
RESISTANCE

R

MAX

=

C

BUS

t

R

R

MIN

=

I

OL MIN

V

CC MAX

=1.8KΩ

7035 FM 16

Bus Timing

Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V).

(6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum

time the device requires to automatically complete the internal write operation.

X24320

14

PACKAGING INFORMATION

0.150 (3.80)

0.158 (4.00)

0.228 (5.80)

0.244 (6.20)

0.014 (0.35)

0.019 (0.49)

PIN 1

PIN 1 INDEX

0.010 (0.25)

0.020 (0.50)

0.050 (1.27)

0.188 (4.78)

0.197 (5.00)

0.004 (0.19)

0.010 (0.25)

0.053 (1.35)

0.069 (1.75)

(4X) 7°

0.016 (0.410)

0.037 (0.937)

0.0075 (0.19)

0.010 (0.25)

0° – 8°

X 45°

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

NOTE:ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

0.050" TYPICAL

0.050"
TYPICAL

0.030"

TYPICAL

8 PLACESFOOTPRINT

7035 FM 19

X24320

15

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V

See Detail “A”

.031 (.80)

.041 (1.05)

.169 (4.3)
.177 (4.5)

.252 (6.4) BSC

.025 (.65) BSC

.193 (4.9)
.200 (5.1)

.002 (.05)
.006 (.15)

.047 (1.20)

.0075 (.19)

.0118 (.30)

0° – 8°

.010 (.25)

.019 (.50)
.029 (.75)

Gage Plane

Seating Plane

DetailA (20X)

7035 FM 20

PACKAGING INFORMATION

X24320

16

PACKAGING INFORMATION

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.020 (0.51)

0.016 (0.41)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.430 (10.92)

0.360 (9.14)

0.300

(7.62) REF.

PIN 1 INDEX

0.145 (3.68)

0.128 (3.25)

0.025 (0.64)

0.015 (0.38)

PIN 1

SEATING

PLANE

0.065 (1.65)

0.045 (1.14)

0.260 (6.60)

0.240 (6.10)

0.060 (1.52)

0.020 (0.51)

TYP.0.010 (0.25)

0°

15°

8-LEAD PLASTIC DUAL IN-LINE PACKAGETYPE P

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

0.015 (0.38)
MAX.

0.325 (8.25)

0.300 (7.62)

7040 FM 18

X24320

17

ORDERING INFORMATION

Part Mark Convention

Device

X24320 X X -X

VCC Range

Blank = 5V ±10%

2.5 = 2.5V to 5.5V

Temperature Range

Blank = 0°C to +70°C
I = –40°C to +85°C

Package
X24320

Blank = 8-Lead SOIC

Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
AE = 2.5V to 5.5V, 0°C to +70°C
AF = 2.5V to 5.5V, –40°C to +85°C

X24320 X

X

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by descr iption regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the

right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,

licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;

4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.

LIFE RELA TED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prev ent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) suppor t or sustain
life, and whose failure to perfor m, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its saf ety or eff ectiv eness .

S8 = 8-Lead SOIC

1.8 = 1.8V to 3.6V

AG = 1.8V to 3.6V, 0°C to +70°C
AH = 1.8V to 3.6V, –40°C to +85°C

V14 = 14-Lead TSSOP

V = 14-Lead TSSOP

P = 8-Lead PDIP

P = 8-Lead PDIP