Xerox Data Systems Sigma 9 Reference Manual

Xerox

Data

Systems

XIDlS

SIGMA 9 COMPUTER

Reference Manual

XoS

SIGMA

9

INSTRUCTION

LIST

(MNEMONICS)

Mnemonic Code

AD 10 AH AI AIO AND ANLZ AW AWM

BAL BCR BCS BDR BIR

CAll CAL2 05 CAL3 CAL4 CB CBS CD CH CI CLM 19 CLR CS CVA CVS CW

DA DC 7D DD DH

•

DL DM DS DSA DST' DW

EBS EOR EXU

FAL FAS FDL FDS FML FMS FSL FSS

HIO

lNT

LAD LAH LAS LAW LB LCD

Instruction

Add Add Halfword

50

Add Immediate

20 6E

Acknowledge

4B

AND

44

Analyze Add Word

30 66

Add Word

6A

Branch Branch

68 69

Branch Branch

64

65 Branch

Call

04

Call

06

Call

07

Call

71

Compare Byte Compare Byte String

60

11

Compare Doubleword 51 Compare Halfword 21

Compare Immediate

Compare 39

Compare 45

Compare 29

Convert

28

Compare Word

31

79

Decimal

Decimal Compare

Decimal

7A

Divide

56

Decimal Load

7E

Decimal

7B

Decimal

78

Decimal Shift

7C 7F

Decimal

Divide

36

Edit Byte String

63 48

Exclusive OR Word

Execute

67

ID

Floating 3D

Floating

IE

3E

Floating

IF

Floating

3F

lC

Floating

3C

4F

Halt

Interpret

6B

Load Absolute Doubleword

1B

5B

Load 26

Load

Load Absolute Word

3B

Load Byte

72

Load Complement Doubleword

lA

Name

Doubleward

Input/Output

Word

to

Memory

and

link

on

Conditions

on

Conditions

on

Decrementing

on

Incrementing

1 102 2 102

3 102

4

with

Limits in Memory

with

Limits in Register

Selective

by

Addition

by

Subtraction

Add

Divide

Halfword

Multiply Subtract

Arithmetic

Store

Word

Add Lang Add Short 77 Divide Long Divide Multlply Multiply SiJbtract Long Subtract

Input/Output

Absolute

Halfword

and

Set

Interrupt

Reset Set

Register

Short

Long Short 77

Short

~age

60

'

60 59

120

68 57 60 64

101 100 100 101

JOO

102

66 87 67 66 66 68 67 67 72 73 67

81 82 82 63 80 81 81 82 81 63

89 68 99

77

78 78 77

77 77

119

58

50 48 51 49 47 49

Mnemonic

LCF LCFI LCH LCW

LD

LH

LI

LM LMS LPSD LRA LRP LS LW

MBS MH MI MMC 6F MSP MTB MTH MTW MW

OR

PACK PLM PLW POLP POLR PSM PSW

RD RIO 4F

S SD SF SH SIO STB STCF STD STH STM STS STW SW

TBS TDV TIO HBS

UNPK 77 Unpack Decimal Digits

WAIT WD

XPSD

XW

~ode

70 02 5A 3A 12 52 22 2A 2D OE 2C 2F Load Register 4A Load 32

61 57 23

13 73 Modify 53 33 37

49

76 OA 08 4F Poll Processor 4F Poll OB 09

6C

25 Shift 18 24 58 4C 75 74 15 Store Doubleword 55 2B 47

~5

38

41 4E 4D Test 40

2E 6D

OF 46

Instruction

Load Load Load Load Load'Doubleword Load Halfword Load Immediate Lood Load Memory Load Program Status Doubleword 103 Load Rea I Address

Load Word

Move Byte String Multiply Multiply Move Modify

Modify Modify

,

M~ltiply

OR Word

Pack Decimal Digits Pull Pull Word

Push Push Word

Read Reset

Subtract Shift Subtract Start Store Byte Store

Store Ha I fword Store Store Store Word Subtract

Translate Test

Translate

Wait Write

Exchange Program Status Doubleword Exchange Word

Name

Conditions Conditions Complement Complement

Multiple

Selective

Multiple

and

Multiple

Direct

Input/Output

Floating

Input/Output

Conditions

Multiple

,Selective

Device Input/Output

ond and

Halfword Word

Status 51

Pointer

Halfword Immedi-ate

to

Memory Control 106

Stack

Pointer

and

Test Byte

and

Test Halfword

and

Test Word

Word

Reset Processor

Doubleword

Ralfword

and

Word

Byte String

and

Test Byte String

Direct

Floating Floating

Floating

Control Control

Control

Immediate

Page

55 54 48 48 48 47 47 54

50

106

53 47

86 62 62

98 64 64

65

63

68

83 97

96 120 120

96

95

108 120

69

61

71

61 114

55

56

55

56

55

61

87 118 117

88

84

108 110

103

55

Price:

$6.50

XDS

SIGMA

REFERENCE

FIRST

October

9

COMPUTER

MANUAL

EDITION

90 17 33A

1970

Xerox

Data

Systems/701 South Aviation Boulevard/EI Segundo,

California

Printed

90245

in U.S.A.

Title

XDS

Sigma Glossary of Computer Terminology

XDS

Symbol/Meta-Symbol Reference Manual (Sigma

XDS

Macro-Symbol Reference Manual (Sigma

5/7

Computers)

5/7

Computers)

Publ

ication No.

90 09

90

57

0952

15

78

ii

CONTENTS

SIGMA

l.

Introduction General General-Purpose Input/Output Time-Sharing RealMultiusage Multiprocessor

Multiprocessor Homespace Multiport Manual Multiprocessor Shared

SIGMA

2.

Central

General Memory Computer Information Information Instruction

Main

Memory

Virtual

Homespace Memory Types Address Memory Address Control Program

Interrupt

Internal Externa I States Control Time Single-Instruction

Trap System

Trap T

rap Trap Masks Trap Trap Addressing Nonallowed Unimplemented Push-Down Fixed-Point Floating-Point Decimal CALL Processor Trap Register

9 SYSTEM

Characteristics

Capabi I ities Features

Time

Features

Memory System

Partitioning

Input/Output

9 SYSTEM

Processing

Registers

Control

Modes

Memory

Unit

and

Reference

of

Addressing

Modification

Status

System

Interrupts

of

an

of

the

of

Interrupt

Entry

Sequence

Condition

Arithmetic

Instruction

Detected

ConditIons

Altered

Features

Interlock

Capabi

Control

ORGANIZA

Un

Format

Boundaries

Register

Real Memory

Doubleword

Interrupt

Code

Operation

Instruction

Stack

Overflow

Arithmetic

During HAnti cipateJl

Function

it

Storage

Address

Examples

Level

System

Occurrences_

Interrupts

Trap

Limit Trap

Trap

Fault

Trap

Fau Its

Bit

lity

nON

Trap

Fault

Trap

Operations

3 4 4 5 6 6 6 6 6 7 7 7

8

8 8 8

11 11

12 12 13 13 14 14 14

17 20 22 26 28 29 30 30 32 32 32

__

33 33

_______

33 33

33 33 35 36 37 37 38 39 39 39

_ 42

42

3.

INSTRUCTION

1

Load/Store Analyze/Interpret Fixed-Point Comparison Logical Shift

Byte-String Push-Down

Execute/Branch

CALL Control

Input/Output

Instructions

Instructions~

Floating-Point

Zoned Decimal Decimal Illegal Overflow Decimal Condition

Stack Push-Down

Branches in

Mode

Nonallowed

of

Instructions

Instructions Program Status Loading Loading Loading

Locks

Interruption Read

(Mode 0)

Read

(Mode

Write

(Mode

Write

(Mode

I/O

Addresses

Processor Addresses

(Bits

Device

(Bits

I/O

Unit

I/O

Status Response 114

Status General

REPERTOIRE

Instructions

Arithmetic

Instructions

Decimal

Accumulator Instruction

Digit

Detection

Instruction

Code

Instructions

Pointer

Condition

Real

______________

Branch

the

Memory

the

Access

the

Memory

_______________

of

Direct -Internal

__________

Instructions

____________

Shift

__________

Numbers

Format

and

Sign

__________ Nomenclature

Settings

__________

Doubleword

Instructions

Extended

Operation

Instruction

Doubleword

Protection

MMC

____________

Direct,

Interrupt

1)

_________________

Direct -Internal

0)

____________

Direct,

Interrupt

1)

____________________

Instructions

19-23)

___________

Controller

Addresses

24-31)---

Address Assignment

Information

Registers

for

_____________

________ Instructions __________

________

__________

________

Detection

_________

(SPD)

Code

Settings

________

Addressing

Trap During

_________

Map

Write

Protection

Computer

Control

Computer

Control

__________

SIO

_____

____

Execution

Controls

Control

_

_ _

_

__

_________

______

_

__

44

99

101

102

106

107 107

108

109

110

112 113

113

113 113

114

116

iii

INPUT/OUTPUT OPERATIONS

4.

Operational Command Doublewords

Order Memory Flags Byte

Control Command Doublewords

OPERATOR

5.

Processor Contro I Pane I

Contro I Mode POWER MEMORY SYS I/O LOAD UNIT SENSE

NOT HALT WAIT RUN Program Status Doubleword INSERT CPU INTERRUPT ADDRESS SELECT

DISPLA INSTR

DISPLAY

DISPLAY FORMAT

DATA STORE

COMPUTE

Maintenance Controls

Alarm Margins

PHASES

CLOCK SNAP MEMORY OVERRIDE SCAN EXT

Operating Procedures

Loading Operation

Fetchi

Byte

Address 123 (USASCII)

Count

CONTROLS 127

CLEAR

RESET

ADDRESS

NORMAL

RESET

STOP

ADDRESS

Y (switch)

ADDR

(Indicator) 132 FORMAT SEL

MODE

DIO

ng

and Storing Procedure 137

APPENDIXES

REFERE

NCE

A.

XDS XDS

TABLES

Standard Standard Character Sets

Symbols

and Codes

122

123 123

123 125 125

127 Hexadecimal-Decimal Fraction Conversion 127

·128 128 128 128 128 128 128 128 128 129 Timing Considerations 129 Effects of Memory Interference 129 Effects of Indexing 130 Effects of Indi rect Addressi 130 130 130 131 131 131

132 132 132 132 132 133 133 133 133 133 133 134 134 134 135 135 135

138

138 138

Contro I Codes Special Code Properties XDS

Standard 8-Bit Computer· Codes

XDS

Standard 7-Bit

XDS

Standard Symbol-Code Correspondences

Hexadecimal Arithmetic 144

Addition Table Multiplication Table Table of Powers Table of Powers

Hexadecimal-Decimal Integer Conversion

Table of Powers Mathematical

SIGMA 9 INSTRUCTION

B.

INSTRUCTION TIMING

C.

SYSTEM

D.

System Maintainabi I ity Features

GLOSSARY OF

E.

RELIABILITY

CPU

Features 167 Main Memory Features Multiplexor

(MIOP)

High-Speed

Features

Communi

of of

of

Two

Constants 156

Input/Output

Features

RAD

I/O

SYMBOLIC

cation Codes

Sixteen Ten16

AND MAINTAINABILITY 166

10

LIST

Processor

Processor (HSRIOP)

TERMS

(EBCDIC)

ng

ILLUSTRATIONS

SIGMA 9 Computer System A Typical SIGMA 9 System 9

l.

Central Processing Unit

2. Information Boundaries

3. Addressing Logic

4. Index Displacement

5.

Virtual Addressing Modes)

Displacement

Index

6.

Addressing}

Generation of

7.

Virtual Addressing (SIGMA 9 Mode)

Generation of Effective

8.

Extended Addressi

Interrupt

9. Operational

10. Processor Control Panel 127

11.

Priority Chain

AI

ignment (Real and

AI

ignment

Actual Memory Addresses,

ng

States of an Interrupt Level

{Real

Extended

Virtual Address,

__

Table_146

Table_152

Real

138 138 139

139 140

144 144 145 145

156

157

158

158 158 158 158

166

169

170

171

vi

10 12 16

21

22

23

24 29 31

iv

Homespace Layout

1.

Computer

2. SIGMA 9 Interrupt Locations

3.

Summary

4.

TCe

5.

Registers Changed

6.

Status Word 0

7.

Operating

of

SIGMA 9 Trap Locations

Setting for Instruction Exception

(XI4D')

Trap

an

Operand

Access

TABLES

and

Addressing Modes

at

Time

of

a Trap

Due

to

___

Status Word 1

8. Status Word 2

9.

15 28 29 34

41

42 Indi 52

ANAL

10.

11.

12.

13.

14.

C-l.

YZE

Codes Floating-Point Condition Code Settings for

Instructions Status Response for Program Status Doubleword

Basic Instruction Timing

Table for

cation

SIGMA 9

Number Representation

I/O

Operation

Floating-Point

Instructions

(PSD)

53 53

58 74

76

115

129

J58

v

1.

SIGMA 9 SYSTEM

INTRODUCTION

The

XDS

SIGMA 9 Computer System

general-purpose

variety

for a time-sharing central

and system other

The basic system can be the

for four million words. Memory access paths

creased

Input/output

input/output devices.

The CPU has a large instruction point

1I100k-ahead cution execution

(512K) words

16 of independent CPUs or lOPs. Each bank address banks. This multibanK, multiaccess memory subsystem with interleaving

single clude

port expansion processors

transfer concurrent

The SIGMA 9 computer design SIGMA 7 computer, so on SIGMA 9. Therefore, comprehensive, modular ware, operating and

Reliabi lity, significantly A an lOP, tem for diagnosis continues

This manual describes features, system organ ations,

prbcessing unit (CPU), a main memory subsystem,

an

independent

element

elements.

user1s requirements. Main memory has addressing

from

and

with memory

modular units

ports

in

interleaving

memory bank designs. The SIGMA 9 system

up

to

data

requiring no reprogramming

uti I ity routines.

partitioning

entire

and

operator

digital

computer system. It

of

scientific,

applications.

performs asynchronously with

the

basic two ports to a maximum capability processors (lOPs),

decimal instructions. A

ll

enables

time.

and

systems, assemblers, compilers,

subsystem, consisting

attached

operation.

A large main memory

is

provided. The memory consists

of

each

memory unit

access to memory by

achieves

11

independent capability)

high-speed

at

rates

with CPU instruction

maintainabi

improved

feature,

peripherals to be isolated

and

controls,

business

A basic system includes a

input/output

readi

Iy

can

be increased

device

set

the

CPU

to

accessing,

32,768 (32K) words

can

system performance far

up

to

lity,

over

for

repair

the

ization,

thereby

can

operates

be provided between

I/O

of

two types - multiplexor

RAD

I/O

three

that

SIGMA 7 programs will run

and

previous SIGMA computers.

example,

whi Ie

general

instruction

and

timing

is a high-speed,

is

designed

data

processing,

subsystem

expanded

that

special

overlap

be

up

to

processors (limited only by

processors - which

mill ion bytes per

execution.

is

compatible

is

avai

of

a CPU, memory

the

characteristics

..

Each major respect

to accommodate

by

controllers,

includes

feature

instruction

reducing program

of

up

each.

expanded

12

processors -

asynchronously,

avai

lable,

mathematical

labi lity have been

permits faulty units or

from

primary system

set,

of

the

system.

and

to

space

can

be

of

12

ports.

adding more

and

I/O

floating-

called

exe-

to 524,288

of

up

to

The number

to

allow

either

and

adjacent

in

excess

can

I/O

can

second,

with

the

soft-

including

un

it,

the

sys-

and

I/O

oper-

in-

of in-

GENERAL

A SIGMA 9 computer system has characteristics purpose, multiprocessing, multiusage environments:

•

Word-oriented which halfword

(8-byte)

• Memory (512K) words in blocks

and

blocks

256K to 512K (where K

• Direct addressing

entire

• Indirect addressing with or without

• Displacement index registers, automati

adjusting for

• Immediate

effi

•

16

general-purpose

blocks

isters

• Hardware memory mapping, which

nates memory fragmentation program

• Four modes

and

• Memory

destruction

• Watchdog timer

•

Real-time identification time, armed,

• Instructions with long

terrupted

• Automatic traps for error or fault

masking under program contro

• Power

event

that

can

be addressed

(2-byte),

quantities.

expandable

65,536 (64K) words. Expansion proceeds in 32K

from

128K to 256K,

memory.

all

operand

ciency

and

of

16)

in

a multiusage environment.

relocation.

of

information

write

of

priority

and

up to 238 levels

enabled,

to

guarantee

capabi

fail-safe

of

power fai lure.

CHARACTERISTICS

features

permit

efficient

time-sharing,

memory

increased

reduce

memory

security

protection critical

to

and

lity

for

(32-bit

and

word

from

of

= 1024 words).

capability

data

sizes.

instructions, for

registers,

data

access

areas

assure nonstop

interrupt system with priority

and

triggered

execution

response

and

maximum

I.

automatic,

functioning

word plus

a Itered as

(4-byte),

131,072 (l28K) to 16,384 (16K),

and

in 64K blocks from

(real

speed.

expandable

transfer to

and

protection

and

protection.

preventing

of

memory.

assignment, fast response

that

can by program

to

safe

real-time,

and

extended

post-indexing.

greater

and

virtually

provides dynamic

inadvertent

operation.

be

times

interrupts.

conditions, recoverabi

shutdown

and

operating

in

general-

parity

bit)

byte

(8-bit),

doubleword

524,288

32,768

(32K),

mode)

ca

lIy

self-

storage

to

64

(in

from

reg-

elimi-

for system

automatic

individually

control.

can

be

in-

with

lity,

in

and

of

SIGMA 9 System

Multiple

•

for

Privi

•

in

multi usage

Complete

•

• Byte,

• Use

•

• Decimal

• Push-down

•

• Shift

interval

independent

leged

operations.

of register-to-register out

indirect

within

Multiple

Fixed-point

halfword,

Floating-point

and

long formats normalization un

der

Full

complement

OR,

exclusive

Comparison

between

registers).

Call amically and

allow system functions

intervention.

metic,

plemented) automatic allocation, recursive

Automatic binary/BCD systems.

Analyze address

Interpret interpretive

doubleword, arithmetic, point

timers with a

time

instruction

environments.

instruction

halfword,

all

memory-referencing

addressing

normal instruction format.

register

integer

word,

fu

II

program

operations,

limits (with limits

instructions

variable,

a program

hardware

edit,

and

stack

of

single

limit

subroutine

routine

conversion

and

instruction

computati

instruction

programs.

operations

including

searching

modes.

choice

bases.

logic for program

set

that

includes:

word,

and

operations,

and

operations.

arithmetic

and

doubleword modes.

hardware

with

control

of

OR).

without

pack/unpack.

operations

checking,

capabi

any

on.

(left

operations

significance,

and

contro

I.

logical

including

that

permit up

user-defined

access

operating

operations,

or

multiple

for

communication,

lity.

operations,

other

that

facilitates

that

increases

and

right)

logical,

shift,

of

resolutions

integrity

doubleword

instructions for

with or

post-indexing,

operations

checking,

operations

in

memory or

to

operating

including

(hardware

words, with

dynamic

weighted-number

of

circular,

and

with-

and

in

in short

zero,

and

all

(AND,

compare

to

64

dyn-

instructions,

system

arith-

im-

space

and

including

effective

speed

of

word or

floating-

Built-in

•

that

•

• Extensive

• Full

• Address stop

in

• Programmable "snapshot" registers

• CPU

•

Independently

•

lowing features:

•

reliabi

lity

and

include:

Diagnostic tem faulty mine faulty; what

tected, available subsequent

communicated tween

It

fau mit

the

quickly

to

maintenance

diagnostic snapshot tion, conditions.

variety designed recoverability.

Partitioning figuration. from from subsystem, consisting input/output peripherals, ational of a faulty tinues

Direct

of a channel.

use

Up

to

by port limitations).

Multiplexor channel

programs with

verification

unit; unit

the

and

physical component

system status and

parity

memory units

detection

operating

Stop on Stop on Stop when

of

register

thus

traps,

of

the

system by

busses. Thus,

system

operation.

input/output

eleven

capability,

and

functional

specific

memory

accurately

to

function

fault

location

error

logging.

for program

analysis.

checking

in

either

and

system or

determine a faulty

feature personnel to:

any

instruction address.

any

memory

any

is

routines to

with

which

provide

CPU

and

enable

unit

operating

a high

features SIGMA 9

selectively

processor

can

be

to

enable

while

I/O

processors

I/O

processors (MIOP) with dual

maintainabi

testing

retrieval

on

all direction

and

processors, providing

location

that

word in a

referenced.

compare known

determining

system

that

un

faulty

of

a CPU, memory

(lOP),

isolated

the

I/O

of

a full word, without

providing forsimultaneous

lity

capabilities

to

determine

testing

of

diagnosing

is

When a

fault

data

diagnostic

permits

reference

for

fault

degree

enable

its

units or an

diagnosis

primary system

system with

to

a unit

malfunctioning.

information

and logging for

and

on busses

capabi

lity

unit.

operator

address.

selected

that

contents

correct

system

detection

conditions,

of

system

can

be

partitioned

disabling

and

attached

from

the

and

(restricted

features

for:

sys-

the

deter-

that

is

to

analyze

fault

is

addresses

to

per-

program

page

enable

of

informa-

fault

of

system

recon-

them

entire

unit,

oper-

repair

con-

the

only

de-

are

be-

or

a

fol-

2

General

Characteristics

operation and

concurrently,

eight

devices

of

up

to 24 devices on one

simultaneous

on

the

other

operation

channel.

channel,

of

with transfer rates

and

at

rates

37.5

up

second transfer

up

to

60,000

inches per second with

to

20,800

bytes

bytes per

per

second.

• High-speed Rapid Access Data (HSRIOP) for use with

•

Comprehensive

•

program

computers:

• Expands in

•

storage units, up

to

three

Both

data

read

and

Up

to

32,000

put

test

compatible

grows.

Operating (BPM), Batch Time-Sharing Monitor Real-Time Batch Monitor Time-Sharing System (UTS), ating

System (XOS).

General-Purpose FORTRAN IV, and

FLAG.

allowing

million bytes

and

command

scatter-write

output

signals.

array

of

with

capability

systems: Batch Processing Monitor

Compilers: Extended

XDS

I/O

processor

XDS

high-speed

data

transfer

per

second.

chaining,

operations.

control signals

modular software

XDS

SIGMA

and

speed

(RBM),

and

FORTRAN IV-H, BASIC,

RAD

rates

for

gather-

and

that

5,

6,

and

as system

(BTM),

Universal

Xerox

Oper-

XDS

in-

of

is

• Displays: acter ups, as well as iight function keyboard.

• Card equipment: Reading speeds up cards cards EBCDIC

Line printers: Fully buffered with. speeds up

•

7

• Keyboard/printers:

• Paper

•

1,500 lines per minute; 132 print positions

to with

also acters per second).

to

300

speeds

Graph ing 300 steps per meters

Graphic

generator,

per

minute; punching speeds

per

minute; intermixed binary

card

64

characters.

available

per second)

tape

equipment; Readers characters up

to 120

plotters: Digital

drift-free

to

3 inches per second.

display has

vector

codes.

with

and

per

characters

plotting

second

pen,

10

paper

second; punches with

in

at

standard

generator,

and

alphanumeric/

characters

tape

reader

punch

(l0

with

per

incremental,

two axes

speeds

from

char-

and c lose-

to

1500

up

to 300

and

per second;

(20char-

characters

speeds

second.

provid-

in

up

30

milli-

up

to

• Assemblers: Symbol, Macro-Symbol, Meta-Symbo

• Library:

output programs.

• Business software: Data Management System (DMS-l), ANS COBOL, Manage,

•

Application

cal

Programming System (FMPS),

Matrix

Simulation Language

Systems (CIRC-AC, CIRC-DC),

Display Library

Standard

•

ment including:

• Rapid Access Data

•

and

6.2

million bytes per unit; transfer three times from 17

Magnetic systems, IBM-compatible; operating

fer rates

other

I.

Mathematical,

Generalized

Manage,

and

1401

software: Functional

Generator/Report

(GDL-l).

special-purpose

mill ion bytes per second;

mi

IIiseconds.

tape

units:

at

150 inches per

up

to 120,000 bytes per second;

units

operating

utility,

Sort

and

Terminal-Oriented

Simulator.

Writer (GAMMA 3),

(S

L-1),

peripheral

(RAD)

files:

7-track

high-speed

second

at

75

inches per

Circuit

average

and

input/

Merge,

and

Capacities

XDS

Mathemati-

FMPS

Analysis

Graphic

equip-

rates

of

access

9-track

units

with

trans-

and

second

to

• Data communications equipment: Complete of

character-oriented

line

oriented

terminals (including remote batch) to computer system

and

equipment

via

local terminals

GENERAL-PURPOSE

General-purpose by emphasis Many operations

on strings

include number conversion (for printing or display),

able

puter

features.

Floating-Point

available

Under program checking, causes a hexadecimal point number).

short storage economy sign ifi

decimal

input/output

system includes

trap

floating-point

cance

computing

on

computation

are

performed

of

characters.

arithmetic

at

standard speeds. The SIGMA 9

the

Hardware.

in

both short

control,

normalization,

when a

places

is

post-operation

occurs in

Significance

format

and

of

detected.

applications

Other

operations,

following

Floating-point

J32-bit)

the

user may

and

for

the

and

message-

to

connect

common

directly.

remote user

carrier

FEATURES

are

and

internal

in

floating-point typical

binary to decimal

general-purpose

and

long (64-bit) formats.

select

significance

shift of more than two

the

fraction

checking

high processing

long format when

permits use

the

lines

characterized

data

handling.

format

characteristics

and

consider-

com-

instructions

optional

checking

of a f/oating-

of

speed

loss

zero

(which

of

and

are

the

and

Genera

I-Purpose Features 3

Decimal instructions

struction

verting

and a genera

check display

Indirect linkages

separate

Displacement displacement without ca register For word, may be using register cesses word, or doubleword. Incrementing by various according is the

Instruction short, rapidly execution

Translate rapid from a variety verted

Arithmetic

operate

set

to/from

protection,

or

print

Addressing. and from

considering

lIy al ign themselves

may

example,

single-precision,

stored

the

same

contains

the

kth

to

always

by units

size

of

data

Set.

highly

assembled

time.

Instruction. The

translation

easi

Iy

on up

includes

the

packed

Ii

zed

edit

and

it.

permits

procedure

indexing.

permits

be

used on arrays with

in a matrix multipl

in a

second

index

the

element,

data

size in a continuous

element

More

optimized

and

between

of

input sources

for

output.

Hardware. Decimal

to

31

digits plus

pack/unpack

format

instruction for

formatting, with

Indirect

keeping

accessing

its

quantity

value

data

sections

Indexing by means

size.

appropriately;

fixed-point

array

of

whether

is

not

required;

used.

than

100 major instructions permit

programs

minimize both program

Translate

any

instructions for

of

two digits per

zero

addressing faci

sections

for

ease

a desired unit

The

index

thus,

different

ication

numbers,

as

double-precision

for both arrays.

k,

then

the

it is a

byte,

instead,

array

table

to

be

written,

instruction permits

two

8-bit

can

be

handled

arithmetic

sign.

suppression,

punctuation

of

maintenance.

of a "floating"

registers

the

of

any

user always

codes; thus

This

conbyte,

to

litates

table

a program

of

data

automati-

same

index

data

sizes.

array

of

the

results

numbers,

If

an

index

ac-

halfword,

quantities

incrementing

regardless

which

are

space

and

data

and

recon-

in-

full

of

INPUT

jOUTPUT

Multiplexing initialized, CPU, needs. The CPU by using mit both command tervening

slow rates involving human

example) to transfer up to

one

operated

Direct Data program control With this or

from

need

not be used for

High-Speed

feature one

RAD

This

high-speed

logic

sufficient

bytes per this

enables

less

than

Input/Output

I/o processors

leaving

it free

to

MIOP requires minimal

channel

chaining

CPU

control.

rates

million bytes per

simultaneous Iy.

Input/Output

of

asynchronous or

feature

general-purpose

is

simi lar to

per

second.

40

information

relatively

RAD

Input/Output

multiplexing

channel

to sustain transfer rates up

In a typical a program swap into milliseconds.

provide faster response to system

command doublewords, which

I/O

registers so

controller

contains

TIME-SHARING

Time-sharing capacities can

be performing a

share

of interactive, Other requires on

is

the

among many users

the

available

"conversational"

users may be

Iy

final

ability

different

resources)

entering

output.

CAPABILITIES

Processor (MIOP).

operate

and

interaction

of

second.

(DIO). DIO

independently

interaction

data

chaining

equipment

rotating

can

infrequent

Processor (HSRIOP). This

is

time-sharing

or

speeds

(teletypewriter,

memory

Many

devices

facilitates

special-purpose

be transmitted

that

an

I/O

transmissions.

input/output

operating

the

buffering

to

out

of

main memory

FEATURES

of

a system

at

the

task (requiring a

and

mode with

work

to

same time. Each user

may be

the

to

be processed

Once

of

the

with

the

per-

without

range

from

devices

at

three

application,

share

on-line

of

can

in-line

devices.

directly

channel

except

that

a time.

and

priority

million

its

total

different

in an

computer.

that

in-

for

be

to

in

Conversion Instructions. Two structions internal cluding

Call up machine erating

Interpret and thus other

Four-Bit results by every

flow, underflow, without

4

provide

binary

BCD.

Instructions. These four instructions permit

to

64

user-defined instructions,

system

Instruction. The

speeds

reducing

interpretive

Condition

automatically

instruction

requiring

Input/Output

for

and

any

services

interpretive

space

and

systems.

Code.

execution,

zero, an

extra

Capabi

bidirectional

other

subroutines,

and

without

operations

minus,

generalized

conversions

weighted

as if

gaining

time

This simpl ifies

providing information on almost

instruction

lities/fime-Sharing

access

requiring

Interpret

such as

requirements for compi lers

including

and

pi

conversion

between

number system,

they

were

to

specified

its

intervention.

instruction simplifies

compilation,

the

checking

indicators for

us, as

appropriate,

execution.

Features

in-

handling

built-in

op-

and

over-

in-

of

The SIGMA 9 system provides

features

Rapid

another,

quickly mit storing registers by a automatically when program status doubleword (PSD), which description operation, PSD

Multiple to sponse time by blocks. A tions as cally

described

Context

and

needed

loaded,

four blocks

needed;

selects

Saving. When

the

operating

easily.

in

a push-down single

and

(also, by a

of

the

can

be

all

Register Blocks. The

of reducing

distinct

the

below.

Stack-manipulating

instruction.

information in

current

stored

with a

16

general-purpose

block

the

program status doubleword

applicable

the

time-sharing

changing

environment

stack

single

user's environment

anywhere

single

the

need

can

register block.

can

of

1 to 16

Stack

the

stack

instruction). The

in

instruction.

optional

to

store

be assigned for

computer

from

one

user to

be

switched

instructions

general-purpose

status

is

updated

can

be

retrieved

current

contains

memory

avai

registers improves

and

labi lity

and

load register

different

automati-

the

mode

a new

entire

of

per-

of

up

re-

func-

User Protection. The user to his own

set operating system tions

that

could destroy correctly. vents a user

Also, a memory

From

those assigned to him. It permits areas for

reading routines, while preventing accessing instructions-in areas

Storage Management. SIGMA 9 memory

from

128K

sizes

provide the for expansion. the

memory map hardware permits storing a user's program

in

fragments as small as a

space

is

avai

(l31,072)words

capacity

To

lable; contiguous block map also

so at

in

automatically

that

the

program appears

execution

time,

a different set

memory. The memory map

compatible SIGMA 7 mode in addition to providing

ability

words. Thus, memory

output

to

locate

in

the

SIGMA 9's logical addressing

the

of

128K words regardless

Input/Output quirements

Capabi I ity. Time-sharing

are

handled by

capabilities

Features

Nonstop

II.

Operation. system continues to due to failure

of

slave

mode feature restricts

of

instructions whi

certain

"privileged"

another

accessing

only,

such as those

access-protection

any

him

Ie

reserving

{master mode)

user's program

system

storage areas other than

him

to access

certain

containing

from

reading,

set

aside for other users.

writing, or

is

available

to 512K (524,288) words

make

yet

of

needed

storage

while assuring

efficient

page

a

II

fragments

at

use

of

available

of

512 words wherever

appear

execution

time.

the

as a sing Ie,

The memory

handles dynamic program

to

be stored in a standard way

even though it may

of

locations

any

128K-word (131,072) virtual program

system

each

for

SIGMA 9 can

can

always address a virtual

actua

time it

of

is

space

of

physical memory

lIy be stored

brought into

operate

four million

input/output

the

same

general-purpose

described under

A IIwatchdog

operate

special

even

I/O

"General-purpose

II

timer assures

in

case

devices.

of

halts or delays

Multiple

each

to

the

instruc-

if

used

pre-

public

sub-

in

potential

memory,

relocation

in a

the

size.

re-

input/

that

the

real-time

clocks with varying resolutions permit independent time

bases for flexible

allocation

of

time slices to

each

user.

to

in-

and

easy,

even

quick progress. each

group

In

establ ishing a con figuration

of

up

while a

to

16

interrupt levels ity assigned in different ways of

a problem;

not

affected

Programs

that

the

way interrupt levels

by

the

priority assignment.

deal

with interrupts equipment sometimes must be ment

is

actually

cia

I equipment,

IItriggered

struction. This

hierarchy high-priority pleted,

it may

ll

by

the

of

responses.

interrupt,

be

available. any

SIGMA 9 interrupt level

CPU through

capability

after

desirable

the remaining portion so

other

to respond to

critical

real-time

to

checked

To

permit simulating this

execution

is also useful in establishing a

For

example,

the

to assign a lower priority

that

the

stimuli. The interrupt can accomplish this by triggering a which processes rupts have been

Certain

instructions described in interrogate

to

restore

and

Nonstop

(on a ready/resume become respond

excessively quickly. A built-in

the SIGMA 9 computer

length

of

Real-Time

occur

to also

event up

at

needed

/ or

to four solution to meet easy handling

the

remaining

handled.

(READ

Chapter

the

condition

that

system

Operation.

basis), delayed

time.

Clocks. Many

specific

- for

the

instants.

example,

current

real-time

these

of

separate

data

DIRECT

3)

allow

the

of

the interrupt system

at a later

When

connected

the

computer

if

the

watchdog timer assures

cannot

be

real-time

Other

elapsed

time

of

day. SIGMA 9

clocks with varying degrees

needs. These clocks a

time bases

priorities.

meet

from

process for

can

the

specific

are

programmed

specially

out

before

the

system,

have its

designed

the

is

can

of a single

in responding to a

urgent processing

interrupt

routine

is

routine lower-priority only

after

and

WRITE

program

other

DIRECT,

to

completely

at

level,

any

time.

to

special

delayed

special

can

device

for

devices

sometimes

does not

an

excessive

functions must be timed

timing information

time

since

a given

can

contain

Iso

and

relative

time

in

prior-

needs

is

equip-

spe-

be

in-

is

com-

to

free

inter-

that

of

re-

allow

time

is

REAL-TIME

Real-time

(1)

environment, real-time

flexibi lity to handle a wide

applications

hardware

process itself,

that

(2)

provi des

speed

FEATURES

are

characterized

qu

i ck response to

great

enough to

and

(3)

varietyof speeds. The SIGMA 9 system includes provisions for following

Multilevel, oriented rupts by means source responded be programmed.)

individually

disabled

real-time

computing features.

True Priority Interrupt System. The

SIGMA 9 system provides quick response to

of

up

to 224 external interrupt levels. The

of

each

to

according

interrupt

For

is

automatically

to

its priority.

further flexibi lity,

disarmed (to discontinue input

(to

defer responses). Use

ture makes programmed dynamic reassignment

keep

sufficient

data

(This

each

of

the

disarm/disable

by a need

an

extern a I

up with

input/output

types

at

varying

real-time-

inter-

identified

function must

level

can

acceptance)

of

priorities

for

the

and

be

fea-

Context

Rapid interrupt-initiated preserve

later,

while

of

environments must be done

1I0verhead

of

up

to

can,

if relevant tion address,

protection

Switching. When responding to a new

circumstances, a computer system must

the

current

setting

ll

time costs.

four blocks

operating

up

of

desired, be assigned to a

"information

about

current

key/etc.)

is

doubleword (PSD). A

PSD

anywhere in memory

to establish a new

environment/which

identifying a new block

can

SIGMA 9 system environment

completely

thus preserve

instruction.

environment/for

the

new environment. This changing

quickly,

In

the

SIGMA 9 system/

with a minimum

general-purpose

specific

the

current environment (instruc-

general

single

register

kept

in a 64-bit

instruction stores

and

loads a new

block,

includes

of

general-purpose

and

change

through

the

execution

Rea 1-Ti

continuance

each

arithmetic

environment. All

memory-

program status

the

one

from

informatic:>n

registers. A

its

of a single

me

Features 5

set

of

one

registers

current memory

operating

SIGMA 9 Computer System

vi

Memory background system destruction operating feature tions

Variable tered this operations

arithmetic

included.

Direct a general-purpose

be

transm

because

prevents

of

in

real-time

data

Data

32-bit

occupied

iss

Protection.

programs

by

system

reading,

Precision

efficiently,

in

addition

operations

Input/Output.

word

with

ions.

Both foreground

can

be

run

concurrently

a foreground program

an

unchecked control,

accessing

writing,

Arithmetic.

systems

can

be

register

relatively

SIGMA

background

the

memory for

and

are

16 bits or less.

9provides

to

fullword

(for

extended

For

transferred

so

that

infrequent

memory

instruction

Much

handling

an

(real-time)

is

protected

program. Under

access-protection

specified

acquisition.

of

the

halfword

operations.

precision)

asynchronous

directly

I/O

to or from a

channel

and

in a SIGMA

against

combina-

data

encoun-

To

process

arithmetic

Doubleword

are

also

need

not

nonperiodic

I/O,

Instruction

9

provides

required each and

SIGMA 9 multiprocessor system. It processing units

(the maximum memory port

SIGMA

a

This wi" cessor system.

Set.

The

large

SIGMA 9

the

user

the

computational

for

widely

IS

program

speed

of

differing

obtaining

length

and

application

and

runn ing

results

MULTIPROCESSING

is

designed

sum

of

both

9 system address memory uniformly.

section allow

describes

growth from a monoprocessor

to function as a

can

and

up

to n input/output

types

of

processors

limitation

the

major

contain

instruction

data-handling

is

increased.

areas;

time

capabilities

therefore,

is

decreased,

FEATURES

shared-memory

up

to

four

processors

is

restricted

of

12). All processors in

features

of

SIGMA 9

to a multipro-

set

central

by

the

that

MULTI

As

implemented

bines two or more difficult cation the application

Because time tions in a that

useful capability

usage puter

Priority ments interrupt With it proper without lengthy

Quick duce a quick-response rapid fit able

Memory only guarantee real-time

general

because

most

the

base,

prove

in

applications.

features

Interrupt.

operate

system (as in

the

order,

the execution

Response. The many features

context

all

users

at

any

Protection.

protect

in

the

computer

computing

of

its

difficult

it

multiusage

valuable

others,

makes

computer system corresponds qui ck Iy,

the

appl

multiusage

that

includes

SIGMA 9 system has

is

uniquely

for

although

SIGMA 9 particularly

The

are

described

In a multiusage

asynchronously.

to

the

many demands

high

overhead

time,

saving,

because

instant

each

more

for useful work.

user from integrity ications.

USAGE

SIGMA

severe

environment.

SIGMA

system (multiple multiple

The memory

FEATURES

9 system, IImultiusage application problem

requirements.

problem

one

or more

been

qualified

certain

of

in

major

costs

and

of

every

programs

application

different

SIGMA

below.

Thus,

9)

is

of

extensive

push-pull

the

machine's

protection

other

areas.

is

the

real-time

is a time-sharing

real-time

designed

for a

mixtureof

Many

hardware features

areas

ways. This

effective

9 multi usage

environment,

having a true

especially

being

made

complicated

storage

that

combine

register

operations)

power

features not

user,

they

essential

ll

com-

The most

appli-

Similarly,

processes.

on a

real-

applica-

are

equally

multiple

in

mu

Iti-

com-

many

ele-

priority

important.

and

in

upon

it,

programming

allocations.

to

pro-

blocks,

bene-

is

avai

also

to

critical

MULTIPROCESSOR

In

a multiprocessor system,

often

need

(CPUs)

This

resource peripheral process.

required

LOAD

AND

position

store

cycle

previously

to

be

IIset"

On

the

other

a

zero,

the

and

simultaneously

processor.

device

SIGMA

multiprocessor

of

the

of

set

and

resource

exclusive

may be a region

or,

9 has a

SET,

unconditionally

referenced

the

memory

by

another

the

testing

hand,

in some

interlock.

if

the

is

allocated

the

interlock

INTERLOCK

the

central

control

of

memory, a

cases, a specific

special

instruction

memory

operation.

processor,

program

sign bit

to

The

sets a

proceeds

of

the

is

processing units

of

a system

particular

software

to

provide

special

111"

bit

location

If

the

set

during

this

bit

interlock

to

tested

testing

for

any

another

processor,

resource.

this

instruction,

in

the

sign

the

had

been

is

said

task.

location

other

re-

is

HOMESPACE

Since

all

processors in a multiprocessor system address

ina

un

i form

memory vate

memory

and

interrupt

This

private

1,024 words for

real

with tions,

1-

tions, ters,

occupy

remaining words in private,

that

memory

address interrupt plus

the

independent

manner,

is

un

locations,

is

each

CPU. Each Homespace

zero.

locations,

16

locations

first

the

storage

MUL

TIPORT

ique

320

it

is

necessary

to

each

processor for its

I/O

communication

called

Homespace region

The

implicitly

and

that

locations

by

MEMORY

Homespace

assigned

lOP

commun

are

reserved

of

Homespace. The

the

CPU.

SYSTEM

to

locations,

and

region

ica

ti on

for

can

be

reta

ina

trap

consists

trap

loca-

the

regis-

used as

pr

etc. of

begins

i-

Input/Output.

speeds,

needs both in terms

6

the

of

Multiusage/Multiprocessing

Because

SIGMA 9 I/O

many

different

of

equipment

of

its

wide

system

application

and

programming.

range

of

simultaneouslysatisfiesthe

areas

economically,

Features

capacities

and

SIGMA 9 has growth

unit. A basic

ory

16K

words

each,

in

operating

when

addressed

capabi

I ity

of

up

to 12 ports per mem-

memory unit consists

which

each

bank

can

by two

of

the

of

two banks of

be

concurrently

possible

12

ports.

This system and

provides large amounts

to multiprocessor systems.

SIGMA 9 has manual units. Thus, besides its primary throughput processor system can system busses. Faulty units ational units to be

A multiprocessor control function cessor systems. This function provides

1.

architecture

MANUAL

capabi

is

be

partitioned

system. Reenabling

returned

MULTIPROCESSOR

Control

(External DIO), used for

of

the

allows flexibi lity

of

PARTITIONING

partitioning

lity, a

secondary

its fai I-soft

by

selectively

are

to

service.

CONTROL

External Direct

memory bandwi

CAPABILITY

capability

advantage

abi

lity. Any SIGMA 9 unit

disabling,

thus isolated

the

connection

is

provided on a

controlling

in

growth patterns

dth,

for

all

of

increased

of a multi-

it

from

allows

FUNCTION

II

three

basic features:

Input/Output

system

essentia I

system

the

oper-

repaired

multipro-

bus

maintenance

AID

converters.

2.

Central

3. Interprocessor interrupt one

processor

cessor

control

that

an

and

of

to

action

special

system

directly

SHAREDINPUT/OUPUT

Provisions

system for

cessor. This is,

HIO instruction to

or cess. However,

process

This

uration action resolution problems.

have

been

made in a SIGMA 9

any

CPU

to

direct

any

CPU

can

begin,

the

end-action

is

directed

feature

control switches) allows

tasks to a single processor and avoids

at

one

(accomplished by

purpose units such as

partitioning.

connection,

signal

is

to be

I/O

issue an

stop, or

sequence

of

the possible four CPUs.

setting a pair

dedicating

another

taken.

actions

SIO,

test

a !lowing

mul

to

any

no,

any

of

I/O

pro-

tiprocessor

I/O TDV,

I/O

pro-

the

I/O

of

config-

end-

conflict

pro-

Multiprocessing Features 7

2.

SIGMA 9 SYSTEM

ORGANIZATION

The

primary system, as units, elements as a group cati

ng asynchronously overlapping greater system duction subsystem performs of

digital selected expanded to

16), cluding ber

of

elements

illustrated

memory

wi

primarily

central

units,

permit

of

program-control I ed

th a common memory. Each subsystem

and

the

operation

speed

(when

tasks

while

information

peripheral

by

increasing increasing MIOPs

and

processors (up

CENTRAL

This

section

SIGMA 9 central

and

data control. memory in Figure 2.

describes

formats, information

Basically, a SIGMA

and

an

arithmetic

of a basic in Figure and

input/output

the

total

computer

semi-independently,

of

the

circumstances

performs

overall

each

lOP

the

tasks

associated

between

devices.

the

number

the

number of lOPs (up

HSRIOPs), or by

to

PROCESSING

the

organization

processing

unit

processing,

and

SIGMA 9 computer

1,

are

central

processors. These

system

subsystems commun

other

permit).

control

(MIOP

the

main

A

basic

4).

to

automatically

subsystems for

and

or

HSRIOP)

wi

th

memory

system may be

of

memory units (up

to

increasing

UNIT

and

operation

in terms

9 CPU consists

control

unit

of

and

as

processor

be

viewed

i-

operates

A

CPU

data

re-

the

exchange

and

11,

in-

the

num-

of

instruction

program

of

a fast

illustrated

sub-

the

The

CPU

has

three

storage

for codes protection computer

Memory

standing

and

A

virtual

used by a the of

data,

It

may

addresses

through

loading during clude addresses, gram,

An

actual (memory address location

by

the addresses ware.

of

a memory

associated

codes.

is

in

Map.

of

the

actual

address.

address

machine-level

location

of

or

the

also

be

are

derived

an

assembly (or

process.

a program's

all

instruction

and

as

well as those addresses

address

for

storage

execution

are

fixed

(See

"Main

MEMORY

the

Two terms memory mapping

an

location

an

addresses used as

CONTROL

high-speed

map,

with

the

memory

This

storage

master or

is a value

instruction,

explicit

Virtual

execution.

addresses,

is a value

register)

or

sequence

and Memory" for

master-protected

are

pertaining

program,

of a data

quantity.

from programmer-suppl ied

compilation)

addresses may

used

to

retrieval

of

dependent

STORAGE

integrated-circuit

memory

essenti al

access a specific

an

access

map,

can

be

concept:

and

the

location

address

Normally,

process

Thus,

virtual

data

addresses,

counts

computed

within

of

information,

instruction.

on

the

further

protection

and

memory

changed

to a proper

virtual

to

the

which

of

(indirect

followed

also

addresses

within a stored

by

the

memory

wired-in

details.)

memories

write-

when

mode.

under-

address

logical

be

the

space

designates

an

element

address).

virtual

labels

computed

indirect

program.

unit

memory

as

required

Thus,

actual

hard-

the

by a

in-

pro-

GENERAL

An

integrated-circuit

general-purpose

CPU. These 16 reg i sters

register

a

register

4

ister

block

selects

are block master

fied (0 through 15 in decimal fixed-point temporary formation such General ters, accumulator 31 used when a

the

general

16

referred

pointer

or

master-protected

Each

general

by a 4-bit

notation).

registers

and regi sters 12 through 15 may be used as a

digits

plus

registers,

block. A SIGMA blocks. A 4-bit

pointer)

block

registers

to

accumulator,

data

in

currently

selected

as

the

can

be

register

code

in

decimal,

Any

storage

as a data

1 through 7 may

capable

sign.

Registers 12 through

dec

imal

REGISTERS

memory,

the

current

changed

in

the

location,

of

instruction

consisting

is

used

within

of

fast memory

9 system may

control

Program

mode.

the

or

general

floating-point

address,

containing a decimal

available

by

the

register

when

current

range

0000

X'O'

register

or

count,

is

field Status

register

the

register

through

to

be

executed.

of

sixteen

the

SIGMA

are

referred

contain

(called

to

block.

computer

through

accumulator,

contain

used as

the

Doubleword (PSD)

a program. The

block

The

is

block

1111

X'

F' in

may

be

used as a

control

pointer,

index

number

15

are

always

32-bit

9

to

as

up to

reg-

pointer register

in

the

is

identi-

hexa-

in-

etc.

regis-

decimal

of

The memory map relocation the

into whatever map program, system.

When the word, memory as

o

through addresses ple, address

general

in

of

in memory

When

addresses regi are order from cess

into

memory map

512-word

transforms

the

memory map

all

if

the

ster transformed into

portion

the

is

described

pages

into

actua

memory map

virtual

actual

15

are

rather

an

instruction

where a result

register 5 in

location

computer

in

the

addresses.

of

memory map. (The memory map

feature

discontinuous

is

of

space

virtual

control

address

addresses.

always

than

range

the

in

provides

in

effect,

and

distributed

are

addresses,

I addresses, as

is

not

bit

in

values

used by

as memory addresses. Thus, for

uses a

is

to

be

the

current

5.

is

operating

0 through 15

However,

actual

addresses,

virtual

address with a

the

section

for segments any

program may

throughout

available.

as

seen

in

effect,

the

program status

above

Virtual

all

addresses in

the

CPU

virtual

address

stored,

register

with memory

are

vi rtual addresses

by

"Memory Address Control

dynamic

of

memory. When

be

memory in

Thus

the

by

the

individual

by

the

memory

as

determined

15

are

used by

as

general

of

the

result

is

block

map,

still used as

replacing

value

obtained

replacement

program

broken

memory

by

double-

the

range register exam-

5 as

the

stored

instead

virtual

general

above

the

high-

pro-

15

II

• )

8

SIGMA

9 System

Organization

Memory

• .900

• Dual banks

•

32,768

ns

Up

to 1 2 ports

Unit

words

t Memory bus

Processor bus

Memory Unit

•

32,768

• 900

• Dual banks

•

Up

to

ns

words

12

ports

j

r---------,

I Memory

I I

I • I • 900

: • Dual banks : 1 •

L.

Memory bus

Unit

32,768

Up

________

j j J

to

ns

12

words I

ports 1

...I

I

1

MIOP

8

sub-

channels

'---r-----~-----

.--

•

Multi-

:

device

1

controller

Io

__ .-__

,..._.:.~

1

1/0

I 1 1

•

I a • I

..

-----1

8

sub-

channels I channels I channels

(option) I (option) I :

Channe

I/O

bus

1

~--1

1 1

•

J

j~

__

... . __

devicel• •

." " "I

I 8

sub-

I 1

t

I A

t 4 byte i nterfa

option

1

__

I/O

device

15

•

_____

.,

....

I 8

sub-

____

Channel B

--I'" - ..J

ce

j

..

__ 1 __

: Single I

device

~~j~~~

•

I/O

1

L-

_____

1

I

t

I/O

devi

I

i

1

1 I

bus

ce

~-....&.

• Decimal

• Memory

• Memory map

• Memory

•

2 register blocks

• 2 clocks

• Power

•

Floating-point

• External

• 8

interrupt

, .

__

.:

• 1

~:~I~~:~

I I

I/O

.I

....

,

,Ir

......

------....

fail-safe

~

__

Single :

device

Separate

CPU 1

arithmetic

protect

access

protect

arithmetic

interface

levels

....

•

..

____

devi

I Removable •

ce·1

....

•

disk

I I

I • 2 sp i

L.

memory bus

unit

__ i __

_____

unit

nd

...,

I

I es I

~

r-------,

1 1

1 1 1 1 1 1

1 I

1 I : 1

....

---r---

To

associated

device

r--~--'

• Disk I

control I

I •

I • 4

, 1

MIOP

controllers

If

unit

byte

er

.

I

" " .

J

I/O

I I

I

,

r

-HS"Ri'O'P'

l

I •

• •

•

RAD

• lOP I

1 1

• 1

1 1

L

_____

I/O

I

J

j~

bus

L-~Jte~~eJ

r--

I Removable I I disk

I I

I •

L

--...,

unit

2 spindles I

_____

r-----...,

17212

•

I

unit

..

-I

storage!

-----

...

•

....

Figure

1.

A Typical SIGMA 9 System

r-----'

I 7212

• I

L

Central

_____

Processing

~

..

.J

Unit

9

CPU

FAST

MEMORY

ARITHMETIC

AND

CONTROL

UNIT

GENERAL

REGISTER

BLOCK

(TYPICAL)

a I I

::::::::::::::::::::::

1 {:tttt,

2

3

4

5

6

7

8~1

9~1

10~1

.:.'

:::::::}::,:::::::::,::,,:::::,:

I

r::::I:::::

:{:'::::::.:.::::\::::::\/:?:

t·················

1:::::::::::::::::::1:11:::

1:::::::::::::::I:I:::::::::t:::::::::::

1:::::::::I::r:::I::::::::::::::::::::::::::::::::::::::::::

1:::::::::::::::::::tf:tII:::::::::::::::::::t:::::::::::::::::::::::::::::::::::::I::::::::::::::::::::::::::::II::::tl

II::::i::::::::I:I::::i:i(:::::it:t::i:::::i:::i{:::::::::i::t:t::I:::::

______________ ______________

________________

.:.:.:.::

... : ..

::.:)t::::::·

.::::::::::,.,:::;::,

:,,:,::::::':'

,:::::::::::}::::}}:::,::}

...

:::::::::'::::::::::::::;:;:;:;:;:;:;:;:;:;:;:::::

:-:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:-:.:.:.:-:.:

.':::':::::':::::::::::::::::::.

:':-'-:':-:"':""':'::':::',::':':::'::::':':':'

:::::::::::::::::::

:::::::,.:':'::r:::::::'::::;::.:?::::!:!:::!}

::::::::}~:::

f't:::t::}::::::'::::

.:.:':'::'::'::':::':::'::'::"::::"::':.:::·1

.

:tI::::::::It·::1

':':':':':':':""1

':::r:::r::;

:::::I::::::I

i:::::::

J:::::::j::::!j@t::::::::::::1

Index

Registers

I:::::]

~

........

--

INSTRUCTION

o

Indirect

o

III

1 7

DIIJ

8

OJ]

12

14

Reference Address Field

I1111111111111111111

15

...

.------------,1

IIII

General

11

Index

Priority

Address Flag

I

Operation

Register Designator

Interrupt

REGISTER

Code

Register Designator

System I

I

PROGRAM

OJ]]

o 3

[ill

5 7

Floating-point

Condition

STATUS

Code

Mode

DOUBLEWORD

Field

Memory

31

I

I/O

I I

Read/Write

I •

Interrupts

I

Write

I

Control

Processors I

Direct

I

11

~I

________________

12~1

________________

13~1

________________

14

~I

__________________

15

MEMORY

Memory

1-256

Memory Access Protection

II I I

III

1--

256

Memory

It

IllllllllllllsffiIIJ

1-----

256

Map

13-bit

1IIIIII1

2-bit

Write

Protection

2-bit

CONTROL

page

addresses

access

write

~

STORAGE

-I

~

~"'-+-'-II"""""""I

codes

--I

locks

--I

~

II

31-digit

Decimal

Accumu-

lator

o

Master/Slave

8

o Memory

9

[I]

Arithmetic

1011

Map

Trap Masks

Mode

Control

D ASCII Control

\I

I I

Instruction

or

31

Extended Displacement

12

r-r-,...,...,...,..-r-r""T"'"'1I'"""T'"",....,...,...,..-r-r-, Add r e

IJ

I I I

II

15

OJ

3435

OJ]

37 39

o

40

III I II

42 47

II I II "

Write

Key

Interrupt

Mode

Altered

I Extension Address

Inhibits

Control

IIIIIIII1 Trapped Status Field

48

IllJJ

56 59

o Register

60

55

Register Block Pointer

Altered

ss

10

Central

Processing

Unit

Figure

2.

Central

Processing

Unit

Memory Access in

the

slave

the

access-protecti program may into

specific tual memory). If gram

attempts

protected, a trap

so

are

described

Memory feature access

Write

operates

protection.

includes

Protection.

or

master-protected

access regions

to

access

in

the

Protection.

independently

the

necessary

When

on codes determ i ne

instructions

of

the

virtual

the

slave

or

master-protected

a region occurs. section

(The

"Memory Address Control

The memory

integrated-circuit memory write locks. These locks with a

2-bit

field,

called

the

write

doubleword.

status whether

any

program may first 128K words changed protected described

when

mode. (The functions in

the

The locks and

alter

of

main memory. The

the

computer

section

"Memory Address

is

the

computer

mode with

the

whether

from,

read

from,

address continuum

of

virtual

memory

access-protecti

write-protection

of

the

memory map and

write-protec'tion

memory for

operate

any

key,

the

word

in

conjunction

in

the

key

located

write

in

the

master

of

the

locks

Control".)

is

operating memory or not

or

write

mode

that

on

codes

feature

program

determine

within

key

can

or

master-

and

key

the

(virpro-

".)

the

are

map,

is

the be

without

operations

I ished

requi

by

ri

ng

available

the

resident

executive

MASTER-PROTECTED

The

master-protected

the

master mode for programs protected

in

the

master mode with

mode, a trap

trap

(Homespace

all

mapped

in

to a virtual

rent

setti

ng

that

mode

will

page of

designed

operate

can

occur

location

slave

to whi ch

the

access

INFORMATION

through

operating

program

CALL

intervention.

instructions

system.

are

MODE

mode

of

only

operation

to

provide

in

the

master mode. The

occur

when

the

memory map in

to

the

memory

1

X140

,

is a

modification

additional

the

CPU

protection

is

effect.

protection

with CC4 = 1), as

programs, if a program makes a

access

is

protection

prohibited

codes.

by

FORMAT

The

estab-

master-

operating

In

this

violation

it

does

reference

the

cur-

of

A

SIGMA 9 computer master-protected mined by word.

MASTER

In this tions and strictions that

of

sition in a there mode)

three

control

(See"

Program Status

MODE

mode,

the

can

modify

placed

imposed by

memory. The Mode

40) must

SIGMA

7-compatible

is a resident

that

controls grams (which may protected

SLAVE

The the to

"privileged" tions the operations mode a program computer is in slave is in slave ecutive

mode).

MODE

slave

mode

computer.

the

slave

are

those

basic

control

are

by

a group

to

mode control

the

master or

mode program

program

In

mode program

operations

relating

performed in

execute a privileged

the

COMPUTER

operates

MODES

in

mode. The mode of

bits

in

the

Doubleword".)

cpu.

can

perform all

any

part

of

upon

the

CPUls

the

write

locks on

Altered

also

be

zero

for

master mode. It

operating

and

be

of

operation

this

state

of

privileged

slave

bit

system

supports

in

the

master,

is

the

mode,

access

if

mapping

are

prohibited.

to

input/output

of

the

computer.

the

master

instructions. Any

mode results in a

can

be

changed

master-protected

can

gain

direct

operations

by

means

either

master,

operation

program

the

operation

certain

control

the

status

of

its control

system. The

in this mode

protected

bit

computer

is

(operating

the

operation

slave,

or

problem-solving

protection

is

in

effect,

Privileged

and

to

All

or

master-protected

instruction

trap.

when mode. access

of

However,

to

CALL

slave,

is

deter-

double-

func-

only

parts

(PSD

bit

to

operate

assumed

in

the

master

of

other

master-

mode

codes

apply

and

opera-

changes

privileged

attempt

while

the

The

master/

the

computer

certain

instructions

or

re-

is

po-

that

pro-

all

in

a ex-

of

by

Nomenclature SIGMA 9 computer physical be

either

The

basic

in which

associated

attributes.

an

instruction

element

the

bit

positions

with

digital

system is based on

A "word"

word

of

or a data

of SIGMA 9 information is a

are

numbered from 0 through

as follows:

SIGMA

A (halfwords) in which

9 word

can

the

be

divided

bit

positions

o through 15, as follows: '

A

SIGMA

(bytes) in which

o through

Two element numbered from 0 through

9 word

can

also

the

bit

7,

as follows:

Byte 1 Byte 2

234567012345

SIGMA

9 words

can

(a doubleword) in which

be

divided

positions

be combined

63,

as follows:

information

functional

digital

word.

into

are

into

are

numbered from

the

bit

within

and/or

information

32-bit

two

16-bit

numbered from

four

8-bit

to

form a

positions

the

may

word,

31,

parts

64-bit

are

Central

Processing

Unit

11

For

fixed-point information (bit 0 represents nitude, right values formats are

and

of

the

are

required

described

binary

represents

the

binary

least

significant

represented

for

in

Chapter

INFORMATION

SIGMA 9 instructions doublewords following

1. A 8 word.

boundary

byte

is

through

are

located 15,

located

16 through

arithmetic,

numerical

sign,

remaining

point

is

or

in

two's

floating-point

3.

BOUNDARIES

assume

that

in

main

conventions:

in

bit

positions 0 through

23,

each

data

as a signed

bits

represent

assumed

rightmost

complement

and

bytes,

memory

or

24

to

bit).

decimal

halfwords, according

through

element

be

just

Negative

form.

instructions

integer the

to

Other

7,

31

of

to

of

the

and

a

mag-

the

Bits

o

1-7

8-11

Description

This

bit

position

dressing

(one contains tion

Operation code See Append

R

ignates register tion,

level

contains

the

field.

that

inside

ix B for

one

block

or

both.

is

a 1

to

be

only)

and

a

O.

Code.

des

ignates

front complete

For most

of

16

as

indicates

performed.

is

This

whether

performed if this

not

performed

7-bit

the

operation

and

back

I istings

instructions

general

an

operand

registers

source,

Indirect

if

field

contains

covers

of

operation

this

4-bit

of

indirect

addressing

bit

position

this

bit

to

be

performed.

as well

field

the

result

ad-

posi-

the

as

codes.

des-

current

destina-

2. A halfword or

16

3. A doubleword contained

through (odd-numbered)

The

various

Figure

3.

The

instruction

rently

be

of

the

two

and

memory-reference)

MEMORY-REFERENCING INSTRUCTIONS

Most

SIGMA operand of

located

instruction

through

within

63

information

register

ing

executed

general

9 CPU

is

located 31

is

are

in

of a word.

located

an

even-numbered

contained

word.

boundaries

INSTRUCTION

contains

by

the

types

of

instructions

are

described

instructions

in

main

memory. The

bit

positions

so

that

bits

0 through word,

with

in

the

illustrated

REGISTER

the

instruction

CPU. The format

(immediate

below.

make

reference

format

0 through 15

31

and

bits

consecutive

in

that

is

and

fields

operand

to

an

for this

are

32

cur-

type

12-14

15-31

IMMEDIATE OPERAND INSTRUCTIONS

Some

operand

required Hence,

ing

X general as will used as cation of

Reference contains operand. (real, fication the tive Addresses" for

SIGMA

type,

operand

memory

are

not

field.

Th

is

3-bit

registers

an

index

register.

not

be

performed;

an

index

Exampl es

the

SIGMA 9 indexing

Address. This

the

reference

Depending

real

extended,

(direct/indirect

reference

virtual

9 CPU

which

required.

address

address.

instructions

is

particularly

is

contained

reference,

field

1-7

register.

II

for a more

further

indirect

designates

of

the

If X is

hence,

(See

process.)

17-bit

address of

on

the

or

virtual)

or

is

transl

(See

"Memory

details.)

are

efficient

within

addressing,

current

complete

type

indexing)

of

the

anyone

register

equal

to

0,

indexing

register 0 cannot

"Address

field

the

of

and

ated

the

instruction

description

normally

instruction

addressing

address

required,

into

an

Reference

immediate

because

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Modifi-

of

block

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the

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be

i-

i

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•

I

Word

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!

i

Halfword 0

I

! Byte 01 Byte 1

Central

12

address) Word (odd address)

Byte

Processing

Doubleword

Halfword 1 Halfword 0 Halfword 1

21

Byte 3 Byte 0 I Byte 1 Byte

Figure

Unit

Word

Halfword 0

21

Byte 3

3.

Information Boundaries

Byte 0 1 Byte 1

(even

address)

Halfword

2\

Byte

Doubleword

1

Halfword

Byte 3

Byte

Word (odd address)

0

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0 I Byte 1

Byte

21

Byte

3!

1

I

.

I

:

I

Bits

o

1-7

8-11

12-31

The

similar

not of ment modification tion

instruction

Description

This bit preted

Operation that formed. When code tents operand. as follows:

Operation Code

X'02'

X'20'

X'21'

X'22'

X'23'

R eral register

designated

th

Operand.

ate

in tions, cated)

32-bit

byte

string instructions

to

immediate

be modified by

byte

string

(or a

is

indirectly

bit

is

coded

as

designates

is

encountered,

of

field.

registers

may

is

operation

operand.

two's

bit

to operand.

instructions

byte

address)

by

the

addressed,

by

the

position

bits 12-31

This

complement

computer.

must

with a

being

nonexistent.

Code.

the any

Immed

iate

Instruction Name

Load

Floating

Immediate

Add Immediate

Compare

Load Immed

Multiply

4-bit

of

the

contain

as

the

register

will

This

20-bit

Negative

12

(the

sign

the

left

through position 0

(described

operand

indexing.

contains a byte

that

memory

be

coded

1,

the

instruction

This

7-bit

operation

immediate

the

CPU

of

the

instruction

operand

Conditions

Control

Immediate

iate

Immediate

field

designates

current

another

in

be

stored

field

numbers

form. For

bit)

instructions

However,

is a virtual

map.

If a byte

it

is

treated

with a

(See

"Trap

field

contains a code

that

will

operand

interprets

operation

and

register

operand which or

accumulated.

contains

are

arithmetic

is

extended

in

Chapter

in

that

the

address

string

as a

O.

If

is

inter-

System".)

be

per-

operation

the

word

as

codes

Mnemonic

LCFI

AI

CI

LI

MI

one

of

16

block.

and/or

the

results

the

immedi-

represented

opera-

(dupli-

to

form a

3)

are

they

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displace-

subject

instruc-

nonexistent

this

con-

an

are

gen-

Th

is

be

of

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field

to

complete be A memory Both memory operating. "ports" within provide

MEMORY BANK

A memory ment elements,

data

Each or location

MEMORY INTERLEAVING

Memory distributes memory banks. a processor out

Both banks example, assigned to

interleaving respective

MEMORY UNIT STARTING

Each memory individual These un it responds when

dresses,

the

given access

boundary

a the starting ary assembly.

part

of

logically

of

registers. A bank

data),

encountering

same for

event

equal

isolated

unit

always

banks

Each memory

or

access

the

unit;

access

to both banks

bank

the

memory system. It consists

drive

location

switches

word remains

the

stores a 32-bit

plus a

(or word)

interleaving

sequential

can

gain

within a unit

in

two-way

bank A and

(the

bank)

unit

identity

define

including

all

word. The

equal

that

the

address for

to a multiple

the

system,

from

consists

may

be

points

that

is,

all

is

the

basic

and

sense

consists

parity

bit.

is

an

"actual

is a built-in

addresses into

Interleaving

access

interference

may be

interleaving,

odd

assignment

may

occur

in

the

SIGMA

by

means

the

servicing

the

starting

ports

in

that

the

same

starting

to a multiple

unit

is

the

combined

of

and

the

rest

of

two concurrently unit

has a

are

common

ports

in a given

within

functionally

electronics,

of

16,384

information

Associated

address".

hardware

increases

to a given

from

interleaved

addresses

of

every

between

ADDRESS

9 system

of

starting

range

of

memory

address,

unit;

that

regardless

address

of

the

interleaved

un its must

the

total

smallest

of

the

memory system.

physical

and

asynchronously

set

of

to

both

memory

that

unit.

independent

of

magnetic

control

memory

word

with

feature

independently

the

probabil

memory

other

processors.

two ways. For

even

addresses

to

bank

fourth address

two

adjacent

is

provided

address

addresses

size

requests.

for a

is,

the

of

the

of a un

size

of

with

another

be

of

the

to

given

part

that

can

memory banks.

from 2

each

B.

port it the

to

banks

unit

ele-

storage

timing,

locations.

(instruction

memory

that

operating

ity

that

location

are

Four-way

to

its

units.

its

switches.

which

the

All

ad-

unit

address

on a

of

used

must

be

unit.

unit,

bound-

interleaved

and

with-

are

to

on

In

the

12

a

MAIN

MEMORY

This

section main memory including

describes

and

indexing.

the

organization

various

modes

MEMORY

The main memory for group

of

"un

its".

SIGMA 9 is

A memory un

and

UNIT

physically

it

is

the

and

operation

types

organized

smallest,

of

addressing,

logically

of

as

the

a

MEMORY PORTS

The memory ports

between they memory ports. all make busses a examine

processors (IOPs

permit

unit

A memory

the

busses

up

the

connected

port

structure

incoming addresses

the

may

entering

unit.

of

a memory

processors

have

unit

port

that

As

an

to

it

and

designated

unit

are

and

CPUs)

and

to

access

memory

from 2

to

12

is

effectively a switch

un

it

and

the

example, a unit

two banks

as a 4 x 2

to

within

switch.

determine

the

connecting

memory

locations.

independent

two

banks

that

has four

it

would

The ports

if

the

Main

Memory 13

banks,

access

between

that

request

points

and

Each

have

is

for a

bank

the

priority

The minimum one

for

the

be

may

PORT PRIORITY

The

each processed ceived bank taneous memory

Normally, chain, port connected nected are has

In ports,

(a normal usually certain access

_

priority

has

quests a high rece higher than nC?,rmal on

CPU PORT

expanded,

multiport

unit)

on

is

busy.

requests port

with

number

to

received

access

addition

as

request conditions a processor

to a given

memory

been

ives a

than

one

sequence

high

priority.

within

of

memory

number

CPU

structure

allow

immed

iately,

different

If

are

logic

all

ports

port

"n"

to

the

lower

for a

to

the

to

the

described

priority

the

request

filled

on

priority

high

priority

the

normal

port

is

on a high

the

memory

of

and

one

in

increments

two

simultaneous

ports,

a

requested

received

selects

in a memory un it

number 0 having

having

higher

pr

iority

single

memory

normal

above,

and a high

normal

port

input

memory

of

priority

unit.

requests

ports for a

for

an

and

the

providing

for

different

bank

for

the

highest

the

lowest.

priority

ports.

bank

on

bank

priority

each

priority). A processor

priority

may

(e.

g.,

an

until

half

or

emptied

reference).

request,

priority

will

They

received

SIGMA

lOP.

of

one,

dual-bank

requests

that

is busy,

the

same

priority

operate

the

highest

In

ports

and

If simul

port 2 and

fj rst.

that

prevails

port

has

level; request

lOP

will

of

its

on

that

portis

of

all

other

at

the

prevail

also

determine

simultaneously.

9 system

The

number

to a maximum

memory

for memory

the

requests

banks,

output;

or

bank,

request

on a priority

general,

lOPs

taneous

port

two

priority

however,

high

wait

available

If

priority

ports.

same

among

and

if siml!l-

the

CPUs

are

4,

among

priority

with a low

it

then

one

time,

those

is

two,

of

ports

of

(within

to

are

re-

neither

first.

priority

and

are

con-

requests

port

2

the

levels

will

under

buffering

re-

port

is

then

If

more

the

ports

12.

be

all

memory minimum of 128K words to 512K words. The 512K maximum size length addressing

units.

limitation

considerations)

space

The

is

physical

rather

is

over 4 million

size

(i.

of

e.,

than

real

based

memory

logical.

(222) words.

ranges

on maximum

Real memory

from a

cable

HOMESPACE

In a

SIGMA 9 multiprocessing memory in not to

provide

and

general

Determining

second-level

bias. region the address

i ust

are

Homespace

of

the any of

real

the

The

in a move the

When the mal memory

to

this is memory CPU.

location CPUs.

the

share

the

same

private

interrupt

first

before tested.

time

Homespace

6-bit

SIGMA

the

64

multiprocessors

Homespace

locations,

registers.

the

mapping.

The

Homespace

of

the

first 1

1,024

is

generated

it is

If

bias

most

significant

the

CPU makes a

memory

Homespace

9 CPU. They

Homespace

possible

addresses

that

location

However,

zero

the

may

same

storage

This

location

words is

sent

all plus two

that bias.

areas.

region

Homespace

zero,

the

manner.

interrupt

private

bias

million

in

the

to

memory,

bits

eight

reference

bias

region

are

of

for

cannot

CPU

reference

system,

However,

or

trap

for

each

I/O

communication

storage

of

Homespace

Each

CPU

is

the

actual

words

of

Homespace.

CPU

by

the

are

equal

leading

used, a given

other

that

of

these

reference

may

is

supplied

can

from

processors

region.

of

a CPU

be

that

has its

the

zeros

be

one

referenced

all

processors

since

systems,

CPU

contains a Homespace

main After

whatever

most

to

bits.

to

be

changed

Homespace

it

to

contain

locations,

is

called

for a CPU is

address

memory,

an

si

gn i fi

zero,

are

inserted

This means

the

first

relocated

by a

set

area

to

CPU may

by

using

The

only

that

is

by

Homespace

address

the

CPUs do

is

necessary

its

Homespace.

like

of

a 16K

of

effective

method,

then a 6-bit

of manually

another

cant

1,024

by

means of

six

switches

reference

the

exception

set

at

any

at

of

all

and

12

in

within

real

other

real

other

trap

and

which

real

bits

place

that words

to

nor-

When

the

memory

set

to a condition elimination timing

preferential

This is

particularly

tem

where

the

of

each

memory un

Virtual

program.

(131,072)

consist

throughout

Real memory

size

14

memory is

of up

is

equal

Main

The maximum words. A

is that

of

switching

CPU would

it.

VIRTUAL

logical

to

256

the

avai

corresponds to

the

Memory

quiescent,

automatically

time

(to

for

the

processor

advantageous

normally

AND

REAL

memory as

size

of

virtual

pages

lable

total

memory for a

of

512

pages

to

the

number

the

port

selection

selects

select a port)

connected

for a

monoprocessing

be

connected

MEMORY

seen

virtual

memory is 128K

words

each

of

real

memory.

physi

cal

memory,

of

words

port

by

given

contained

logic

O.

The results to

port

to

port

an

individual

program may

distributed

and

within

is

in a

O. sys-

its

Each

Homespace

interrupt a ory

0

general space. be

Homespace accessibl are operations. of main memory. to for

locations,

given

CPU (see

locations

registers, The

used as pri

e to

reserved

the

current

hold

an

execution

region

contains

and

lOP

Table

1). These

plus

the

16

locations

occupy

remaining

vate,

MEMORY

memory 10cationsO through 15

the as

register

However,

register

instruction

just as if

words in

independent

REFERENCE

programmer

designators

an

block

Furthermore,

(or c series

the

all

communication

implicitly that

the

first

320

the

Homespace

storage

because

for

instruction

as if

it

were a location

the

register

of

instruction

the

ADDRESS

thei

can

up to 16

trap

locations,

locations

assigned

are

reserved

locations

by

the

are

not

r memory

"register-to-register

treat

block

instructions)

(or

instructions)

for

of

Homeregion CPU.

normally

addresses

any

register

in

can

be

mem-

can

used

for

the

ll

were

Dec.

Hex.

000

OOF

015

016

010

031 01F

032 020 033

021

022

034

063 03F

040

064

079

04F

Table 1. Homespace Layout

Function

Addresses

Reserved for future use

CPU/lOP

Load routine

T rap

of

general

communication

or

locations

reset

registers

recovery

locations

routine

in main memory. The register

Description SIGMA 9 are

References

trol flow and

Instruction Address. This is

tion

17-bit

the

ing, concatenated doubleword.

block

for instruction

If

an instruction

the

R field

instruction would designated, used as operation

would

to

program

the

be

unpredictable.

of

the

based upon terms and

are

data

be

executed.

instruction address is

status doubleword.

22-bit

with bits

only

accessed

of

the

instruction

alter

the

contents

of

the

instruction in

various types

made to Figure

flow during address

For real and

instruction address is comPrised

42-47

restriction

storage

from a

word

register,

the

contents

of

that

sequence

of

addressing used in concepts

4,

which illustrates

the

address of

virtual

contained

For real

of

the

upon

the

use

is:

general

and

register

the

generation.

register

to

designate execution of

the

register

should

because

affected

defined

the

within bits 15-31

extended

of

program

status

of

the

uses

the

of

the

so

not

be

the

register

the

below.

the

con-

instruc-

the

of

address-

bits 16-31

080 050

085 055

086 056

057

087

058

088

091

05B

092

05C

095

05F

096 060

111

06F

Override

Processor fau

Memory fau

Counter group

I/O

External Interrupts, group X'2

group

I t

Internal Interrupts, group

Reference Address. This is

associated

instruction Reference Address, the bits 15-31 dressing, of

the gram status doubleword. The modified by using

X

11

'

1

ory mapping. A virtual

indexing

20-Bit

interrupt are address may A

20-bit

Direct

nor position 0 and

reference comes

be

used during all addressing modes,

interrupt addressing does

with

any

instruction

that

has

bit below.)

reference

instruction

Reference Address.

used as a

indexing

the

address is

of

the

instruction

the

reference

concatenated

indirect

reference

address

Reference Address. If

after

the

(if required) is performed. (See Figure

instruction is a

20-bit

reference

be

modified

reference

address of the instruction (as

effective

operations.

address

is

called the X field

virtual address.

not

preclude

the

except a trap

position 10

For real and

the

address

itself.

address

for by

Direct

is with bits

reference

addressing,

address becomes

indirect

If

bit

0,

bits 12-31

address. A

only

by using

can

not be

neither

the

of

the

addressing during

memory mapping.

17-

or

22-bit

equal

to

O.

virtual

contai

For real

comprised of

42-47

address may

indexing,

addressing

position 10

of

that

20-bit

indirect

indexed

indirect

instruction

defined

Direct

addressing may

including

address

or

interrupt

(See

addressing,

ned

wi

thi n

extended

bits

16-31

of

the

and

an

effective

and/or

4.

)

of

any

instruction

reference

addressing.

or mapped.

addressing

(i.

e.,

if

are

0),

above)

trap

virtual

20-Bit

ad-

pro-

be

mem-

post-

trap

bit

the

be-

and

or

130

304

External

319 13F

320

140

Unassigned

1023

3FF

Interrupts, group

locations

XI

Indirect

F'

of

128

use string instructions). If

the

ence

location

positions

Reference' Address. The

the

SIGMA 9 instruction word format provides up

instruction

indirect

instruction (when

address (as

addressing

that

contains

15-31,

operation

(except

indirect

bit

position 0

defined

the

or

bit

positions 10-31 for

7-bit

operation

codes,

nearly

all

immediate operand and

addressing

contains

above)

direct

is used

reference

to

Main

is

access

certain

code

of which

called

for by

1)

the

refer-

a word

address in

real

Memory

field

to

can

byte

bit

15

CONTROL

FLOW

DATA

FLOW

yes

Reference} Address

Instruction

Word

Address

Write locks (lst

128K

words only)

Add

Homespace

(if required)

B

Figure 4. Addressing Logic

Actual} Address - - - -

r----'-----.

Memory Address

Register

Main Memory

16

Main Memory

extended operation not the of

ing;

instruction

order

initial according II

Address

proceed word

the

instruction.

that

bits

reference

addressing

is

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to

further

location

pointed

Indirect

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the

17-bit

is

used

to

of

the

word thus

address

to

the

operation

Modification

operations.

levels,

obtain

Index Reference Address. instruction instruction), modified by eral

scaling

This final indexing,

dress of

called

is

ll

ples

(a

register

the

displacement

reference

or

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postindexing.

for

further

nonzero

the

direct

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called

address

both)

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defined

instruction.

details.)

value

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one

level.

regardless

to by

the

addressing

reference

a word, and

obtained

field;

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code

of

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or

the

ll

.)

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bit

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the

Indexing

(See IIAddress

indirect

Indirect

of

reference

occurs

address

effectively

indexing

the

instruction.

ca positions reference

the

instruction

to

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(after

indirect

effective

after

indirect

Modification

addressing addressing does the

contents

address

before

field

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17

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replace

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ed

for by

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of

address is

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(after

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addressing

Exam-

of

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low-

the

out

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type).

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do

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system (as in a

Effective

the ter referencing effective either of transformation

Effective contents current

the

of

the

address of

instruction),

Location.

actual

location

block)

that

address. Because

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actual

an

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Operand.

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effective

instruction

READ

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instruction,

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location

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an

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also

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address. This

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an

input/output

or to

designate a specific

DIRECT

An

or

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shift

device

WRITE

location

to

instruction),

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receive

An

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address

effective

address,

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is

to

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used as

and

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the

transformation

address.

reference;

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to

(as in

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is

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current

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applicable,

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as

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as

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by

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Displacements. Displacements used in generate halfword, word,

Register Address. If

dress or the memory. address eral this address is used as tion. rent of a direct usage is

Actual actually memory address virtual is

ing

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Effective Address. The final

from

address location

index

registers and

effective

that

is a memory

indexed

CPU

reference

does

not

Instead,

are

used

as a general

register

Thus,

(of

the

instruction

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address,

referred

to as a

Address.

used by

register

address

addressed.

mode,

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If

all

virtual

into

addresses in a

map,

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the

computer

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mode, no transformation

All

actual

to address a

virtual

the

address computed for

address

is

or

generator

usually

result

addresses

or

doubleword).

any

instruction

reference

address) in

attempt

the

to

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current

the

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source

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the

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II

reg

An

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(see

XIQI

- XIFI,

computer

addresses

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then

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addresses

doubleword,

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in Figure

used

as

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low-order

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different

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the

16-

byte

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of

th e

appropriate

produces a virtual

(i.

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the

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h

its-

register

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block)

location

use

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operand, of a result.

ister-to-register

address access Figure

is

main memory

4). If

one

of

operating

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15

the

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memory

become

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in

either

via

the

21, 22,

word,

23,

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address is

an

instruction

4).

virtual

address

However,

to

24-bit

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instructions

size

to

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indirect,

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write

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into

reference

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main

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corresponding

or

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destina-

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cur-

the

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Such

ll

operation.

address

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general

in

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virtual

value

the

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by

the

addresses. How-

real

or

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memory map

or

defined

24

bits,

or

as

takes

as

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the

(output

The

effective

of

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opercmd

some instructions

to

TYPES

Except for only within

REAL

Real addressing relationship of

each

main memory.

1. Each

2.

3.

4.

5.

6.

the

by some

the

computer

special

interrupt

type

and

system

ADDRESSING

is a type

prevails

instruction

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and

Characteristics

reference

The

reference

of

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ically

aligned,

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is

address,

address is a

address may

postindexing.

associated

as

required,

or

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either a 16-bit

18-bit

address.

Memory mapping and memory never

invoked.

Memory cause the outside cessible

Leading tive required

write

protection

the

reference

first 128K words

the

first 128K words

with real addressing.

zeros

are

automatically

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the

generate

main memory.

OF

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of

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addressing

instructions,

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of

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17-bit

be

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extended,

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word address.

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doubleword,

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doubleword

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access

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real memory. Memory

of

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effective

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protection

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within

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Main

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17

7.

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Status

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VIRTUAL ADDRESSING

Virtual map particular addressing

normally address addressing

1. Each

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4.

5.

6.

7.

addressing

to

determine

reference

differs

no

exact

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the

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reference

The

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Displacements ically

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Virtual

If

tion

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Memory mapping of a nated address. actual permits tual

throughout words (8192

physically

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8

lated patibility on structure

If

real also

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specified

REAL

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address,

address.

memory

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aborts

"Trap

the

effective

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with

address

anyone

memory

addition, a special

is

with

bits

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into

SIGMA 9 computers

the

actual memory, invoked.

addressing

EXTENDED ADDRESSING

may

when

is a type

the

actual

address

from

relationship

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address is a

address may

postindexing.

associated

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or

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access

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Systems".)

virtual

page

address. This

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The

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user

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up

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or

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address

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when

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and

PSD

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of

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address.

required,

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at

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page

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9 is a 1.

Characteristics

17-bit

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for

and

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significant

access

128K words (256

SIGMA 7 compatible

this

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address,

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Homespace

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8 most

address

22-bit

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logically

addresses.

with

within

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word address

memory. This

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all

SIGMA

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used in

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40

of

the

Program

40)

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that

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the

address.

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doubleword,

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address,

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always

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id,

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page

address

bits

of

time

of

up

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it

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contiguous.

the

memory map is

The most

are

address.

7 programs to run

change

first 128K words of

protection

all

modes

Virtual

that

there

effective

of

indirect,

are

automat-

word,

or a 19-bit

invoked.

the

instruc-

X'40'.

significant

portion)

is

concqte-

the

reference

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the

feature

to

have a vir-

pages)

located

to

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memory

mapping

significant

then

This

to

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mapping

feature

and

mode

O.

with

is

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with

virtual l7-bit

bits

into

million

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trans-

com-

is

system to ory

it channel Characteristics

1.

a

2.

3.

Further

in

1.

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3.

Note:

Instruction

General

The

address field tion

displacement.

a direct the

is

If

address

If

addresses a word

by bits When formed by address

communicate

rather

than

through a

provides

three

addressed

the

a method for

control word

of Memory mapping Memory

address Real

is

Instruction Other

Branching

instruction

15

Extension

write

is

extended

a 0

and

descriptions

parts:

addresses

The

extended described extended

and

Instruction

PSD

field

of

in

both

places

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resolution

by

Extension

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to a word

Extension

42-47

bit

position

concatenating

field.

within

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address

as a flag

Selector

of

with

part

the

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addressing

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access

protection

the

first 128K words

addressing

40

is

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of

real

and

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and

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branch

address

below

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addressing

Reference

each

The

to

the

Selector

within

the

15

Addresses

Format:

field

instruction

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divided

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displacement

64K words. The

and

16-bit

equals 0 then

within

equals

the

PSD,

equals

PSD

any

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the

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addresses in

addresses.

fields

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indicates

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the

64K

call

ed

1,

42-47

system

work in

are:

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invoked

specified

icable

the

is

into

positions 16-31

first 64K

1,

region

the

a full memory addresst is

real

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addressing is

instructions.

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displacements

only

--

in

Instructions.

PSD

and

17

bits.

two

parts.

field

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flag

(bit

which

of

the

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of

real

then

the

that

Extension Address.

with

bit"s

via

real

mem-

In

addition,

to

control

memory

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if

real memory.

when real

the

The address

bits

15) two regions

displacement is

identified

16-31

invoked.

the

actual

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provided

reference

Bit

posi-

are

used as

allowing

is

called

memory.

of

space.

9

the

Real

extended

that

there

virtual

extended

Real

ories

larger

18

Main

is a direct

address

than

Memory

addressing is

of

each

addressing

128K words. It permits

similar

relationship

instruction

faci I itates

between

to

real

and

the

operating

addressing in

the actual

the

effective

address.

wi

th

mem-

operating

t

memory address consists

Ful1 address, address,

22

bits

and 24 bits for a

for a word

of

address,

byte

address.

21

bits for a

23 bits for a halfword

doubleword

The

logic

treats

bits

The Extension Address

ciated

count

logic. program flag struction instruction cause change effect. the

Other address address and

(previously

The

is

in

the

real

bit

in position 15 is a 1 and if

presently

executed

the

count

bit

15 to a 0

The Extension Address

value

X'021.

Addresses

fields

places

affected

being

logic

and

the

displacement

undefined)

16-31 of

This means, for

extended

will

on bits 16-31

and

Displacements.

instruction address

fields

are

the

(PSD

bits

addressing mode and

executed

be

X'020000'. This

the

Extension Address

(PSD

fields

are

to

address

as follows:

PSD

42-47)

as a

does not

example,

the

location

is

X'02FFFF',

of

the

bits

42-47)

Except for

of

extended

all

memory

16-bit

occurs

PSD

the

into

counter.

have

that

if

the

of

the

next be-

does

not

is

still

remained

reference

PSD,

all

adjacent

directly.

asso-

the

in-

in

at

4.

The sign in extended tination describe byte byte

Register Formats for Byte String Instructions:

bit

position

before

address.

the

source address for a addresses.

12 of

the

displacement

In

addition,

byte

stri ng

byte

the

address

instruction

string

is

added

registers

and

instructions

to

the

that

the

destination

are

24-b

is

des-

it

1. An

Indirect

2.

Index Register Formats:

3.

Stack

indirect word address or a sion

Selector

Address Location Formats:

An

index

of from

unit

being

The

stack

a

22-bit

Pointer Format for Push/Pull Instructions:

address

register

21

to

referenced.

~

pointer

word address for

location

16-bit

(ES)

flag.

contains

24

bits,

~

Doubleword }

Word

Halfword DIsplacement Byte

for

region address and

an

depending

push/pull

the

contains

extended

on

instructions

top

of

either a 22-bit

an

displacement

the

size

of

•

contains

stack

address

Exten-

the

field.

When

any

of

the

addresses

reference address word address used for

Branching and Branch Addresses. The Extension Address field be

LPSD branch

If

the the full field branch

In

addition,

Sel

the

If first 64K of memory, will the and that

is

either

actual

A BRANCH

ing stores register. BRANCH

stored in displacement be

Extension

stored

16-31)

42-47)

I ink

register

memory

field

of

the

loaded

at

instruction.

instructions.

effective

first 64K of real memory,

effective

of

the

address

ector,

is

effective

not

be

f6low-order

the

Extension

once

the

changed

branching

the If

AND

the

placed

in

Selector

will

plus which will

register.

are

fully

in

the

program

the

time a new

This

address

PSD. The remaining

is

loaded

bit

position

set

to

1.

branch

modified. The

positions of

Selector

Extension Address

by

into

AND

LINK instruction in real

full address of

the

Extension

LINK

link

register

from positions 16-31 of

the

high-order

is

be

the

incremented

the

contents

be

In

both

set

to

OIS.

mentioned

without

PSD. The

indirect

status

doubleword

field

of a branch

are

loaded

into

15 of

address

the

extension

effective

(bit

the

loading

another

Selector

is

executed

will

address positions.

equal

to 1

of

the

placed

cases,

above

are

the

use

of

the

extended

only

exception

addressing.

(PSD

PSD

is

loaded

is

modified

instruction

the

high-order

into

the

part

of

positions 16-31

the

PSD,

is

to a

location

address

the

instruction

15)

is

set

is

set

it

of a new

64K word

the

in

the

is

equal

be

the

incremented the

in

the

PSD,

16-bit

displacement

Extension Address (PSD

into

bit

positions

bit

positions

is

bits

by

an

automatically

6 bits of this

ExtelltiQJJ Address

the

effective

of

the

Extension

field

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address

to

O.

remains

PSD

region

extended

PSD

at

to

0,

PSD.

the

10-15

0-9

of

used,

the

22-bit

42-47)

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is

outside

the

PSD.

within

the

of

the

loaded

field

This means

set

until

or by

of memory.

address-

the

time

the

address

16-bit

Zeros

will

If

the

address

(PSD

of

the

I ink

they

may

by

PSD

into

it

the

link

the

Main

Memory 19

INTERRUPT

interrupt

An interrupt

an

interrupt. satisfied An

instruction

it

may executed interrupt a

trap and valid MTB.

Interrupt

The address of interrupt

If

bit

a

real mode bit)

of instruction permits memory. addressing tion

point address in must containing This

AND

instruction

location

Both

simultaneously

is

be

in

an

as

the

location

instruction

is

executed

interrupt

The

instructions

only

valid

and

Trap Instructi on Format:

the

or

trap

10

of

the

XPSD

address

specified

the

be

22-bit

is

by

XPSD

are

used as a

direct

addressing

If

bit 0 of

is

invoked,

to

a word in memory

bit

positions

programmed with

the

reference

TRAP

ENTRY

is

and

is

elements

for

not

an

interrupt

result

of

under

normal program

is

defined

as

the

direct

trap

instruction

depends

in

an

generated

the

current

instruction

20-bit

the

XPSD

and

10-31.

address

defined executed

of

it

to

interrupt

location

the

as

are

instruction

executed

on

bit

interrupt

independently

PSD.

is a

of

the

bits

bit 0 containing

address (so

allows

word memory.

If

bit

10

of

the

XPSD

in a

trap

the

address will

PSD

(i.

e.,

Any modify location ner

as

described

uses

real,

and

the

be

generated

real

test

instruction

20-bit

above

as

extended,

reference

for the XPSD.

Any XPSD, MTW, MTH, orMTB cuted

as a normal struction, manner has no

effect

is

executed

as

uses any

instruction,

the

17-bit

other

memory

on

the

execution

as a normal

reference

instruction.

ADDRESSING

as

one

that

is

as

the

direct

the

definition

be

an

interrupt

instruction

if,

program

even

for

example, branching control.

one

that

is

in a

trap

result

of a trap.

XPSD, MTW, MTH,

is XPSD.

as a

result

10

of

the

XPSD

or

trap

location

of

the

addressing

If

bit 0 (the

0,

bits 12-31 reference first

one

instruction

12-31

of

that

contains

Note

that

called addressing

or

interrupt

prescribed

or

virtual

encountered

address in

instruction

not

an

interrupt

address

of

address,

mi

II

ion words of

is

a 1,

the

XPSD

the

indirect

a 0

and

long form).

a 4 mill ion

location

by

the

addressing).

in

an

the

that

or

in

the

instruction.

of

an

XPSD

instruction

in

an

result

of

must

be

instruction.

though

it

is

to

the

Similarly,

location

The

only

and

of

an

is a 0,

indirect

the

XPSD

which

indirect

instruc-

reference

word

bits

10-31

is a 1,

current

interrupt

same

man-

is

exe-

trap

in-

same

Bit

10

that

low-order from register the placement with

ister. The this positi for a word word

bit

the

index

(as

an

instruction;

is I

the

least

displacement

on

for a

operation,

operation.

positions

register

integer)

that

ined

significant

develop a 19-bit tive

address 32-bit of

this ignored ignored ignored ment val the

initial displacement order in

two's

The

effective 19-bit matically conventions. bit

of tions, are

O'S;

bits of

If

no byte if

no tive

halfword word word the

next odd-numbered operation,

tion

trap

If

the address is 24-bit

the

8 most

address

13-bit

the

11

address

of

the displacement effective

address (i. for word for

shift

operations, for

doubleword

ue

can

cause

reference

value

lis

(i.

e.,

if

complement

virtual

byte

address

adjusted

Thus, for

the

effective

the

two

low-order

and

for

doubleword

the

effective

indexing

is

indexing

the

first

is

byte

the location. A doubleword at

an

even-numbered

sequential

word

the

computer

(see

liT

rap System

addressing mode

concatentated

actual

address.

significant

(SIGMA 7 page SIGMA 9 page least

significant

are

combined

(32

and

33). The

is

then

aligned

according

is, if

it

is a byte

up so

that

its

bit

of

the

is

shifted

halfword

An address,

and

three

addition

which

operation,

bits

process

instruction.

fi

eld

are

ignored

e.,

the

operations,

the

and

operations).

the

effective

address

within

contains a sufficient

the

displacement

form.

address of

value.

to

the

an

However,

SIGMA 9 information

halfword

bits

address

of

the

operations,

doubleword

used

with a byte

(bit

positions

used

with

a halfword

first halfword

operation

word address

(odd-numbered)

location

is

If

bits

will

II

).

real,

with 5

the

of

is

specified

trap

the

leading

addressing

the

address)

address. The new

bits

.of

the

to

form a

24-bit

displacement

with

to

the

addressing

operation,

low-order

34-bit

one

bit

two

to

the

then

is

referred

High-order

in

the

15

high-order

25

high-order

the

16

high-order

However,

address

the

instruction

number of

is a

negative

instruction

this

operations,

is

0; for word

effective

the 3 low-order

address

are

operation,

0-7)

of

operation,

(bit

positions

always

and

word address.

for a

to

the

instruction

19-bit

zeros

mode

19-bit

effective

are

transformed

page

19-bit

effective

actual

the

instruction

the

bit

is

al

instruction

to

the

bits

to

left

for a

takes

place

to

as

the

bits

of

development

bits

the

to

be

I ess

integer

is

always

value

is

boundary

the

low-order

word address

O's.

the

effective

a word

location; the

0-15)

involves

the

word

doubleword

effective

to

form a

is

virtual,

virtual

into

address

address.

value

type

dis-

igned

reg-

left

of

the

left

double-

to

effec-

the

are

bits

are

displace-

than

if

the

high-

a

auto-

opera-

effec-

of a

at

If

an

excep-

virtual

a

and

virtual

of

a

ADDRESS

INDEXING

(REAL

Figure 5 shows how

during

real

and

struction

instruction

is

brought register

MODIFICATION

AND

the

indexing

virtual

addressing from memory, that

initially

EXAMPLES

VIRTUAL ADDRESSING)

operation

takes

operations.

it

is

loaded

contains

O's

20 Mai n Memory

place

As

the into a in

the

in-

34-bit

two

INDEXING

Figure 6 tended virtual

illustrates

addressing

addressing.

1. Bit 15 ence a 1 r

the

of

the

struction

(REAL

of

the

address.

contents

PSD)

register

EXTENDED ADDRESSING)

that

the

is

simi

The

instruction

It

is

of

are

concatenated

to form a

indexing

lar

to

differences

word

used as a control

the

Extension Register (bits

process for

that

performed for real

are:

is

not a part

to bits 16-31 of

22-bit

reference

flag.

real

of

the

If

bit

42-47

the

address.

ex-

and

refer-

15

in-

is

Instruction in memory:

Instruction

Byte

operation

Halfword

Word

Shift

Doubleword

Effective

operation

virtual address:

in

instruction

indexing

operation

register:

alignment:

indexing

alignment:

indexing

al ignment:

alignment:

I

IIII

5.

Index

Figure

If

bit

15 is a

zero,

six

leading

to

the

16 bits of

the

22-bit

byte

address

2.

Displacement

24

bits for

displacements,

21

bits for doubleword

INDIRECT, INDEXED HALFWORD (VIRTUAL ADDRESSING SIGMA

Figure 7 process for operation. content stored in memory. The tion

9 MODE)

illustrates

of

the

register,

an

As

and

the

instruction

word address is

by

appending

values

have

byte

displacements,

22 bits for word

the

address

indirectly

the reference

figure

if

the

addressed,

shows, address

instruction

value

converted

two

an

displacements.

modification

reference

of

the

Displacement

zeros

are

word.

into

zeros

on

extended

23

bits

displacements,

indexed,

address 1

field

in

the

is brought

reference

concatenated

In

either

an

the

number of

for halfword

and

halfword

instruction

into

address

AI

case,

equival

right.

bits,

and

mapping

is

the

instruc-

field

ent

ignment

(Real

and

Virtual Addressing Modes)

is

greater

address

17 by replaces The tion address by address memory map into

memoryaddress,

is

then

and for

Note

tions requ ired for are and

leading

5 memory map.

than

to a 24-bit low-order the

actual

reference

index

register

is

then

level.

the

address

is

greater

used

the

that

exactly

the

final

zeros

bits of

address,

aligned

to

instruction.

for

the

15,

it

actual

the

address 1 in

designated

for

The final

generator

than

an

actual

which

access

the

real

indirect,

same

effective

rather

is

converted

address by

main memory

labeled

incrementing

effective

and

15,

it

automatically

the

halfword to be used

addressing mode,

except

address

than

from a

reference

the

instruction

in

the X field

virtual

if

the

value

is transformed through

address. The final

indexed

that

the

are

being

19-bit

reference

the

memory map. The

location

at

contains a 10w-orderO,

halfword

concatenated

transformed

pointed

address

the

of

reference

2,

then

register.

of

the

instruc-

halfword-

address is formed

the

reference

the

24-bit

as

the

oper-

the

modifica-

operation

address 1

with

by

the

to

main

Main Memory

21

Instruction

in

memory:

Information used by address

generator:

Byte

operation

Halfword

Word

operation

Shift

operation

Doubleword

24-bit

effective

indexing

operation

indexing alignment:

address:

alignment:.

indexing alignment:

Bit 15 Bit 15

= 1 = 0

24-bi~

displacement

;alue

I

IIII

I I

INDIRECT, INDEX ADDRESSING)

Figure 8 real

Bit

When

instruction within the Extension Register equals

is

concatenated

the

The word in memory pointed

address may

and

If

bit 0 is a 0, address. are

illustrates

extended,

15 of

the

bit

15

is

0,

the

Extension Register

be

bi t 15

of

If

concatenated

HALFWORD

the

address modification process for

indirect,

instruction word

equals

concatenated

16-bit

with 6 leading zeros and

one of

the

direct

bits 10 to

bit 0 is

indexed addressing.

1, the

16-bit

reference

are

not used nor

three

address.

31

a 1 and bit

with 6 leading zeros to

Figure

6.

Index Displacement Alignment (Real Extended Addressing)

(REAL

EXTENDED

is

used as a control

reference

with

the

6 bits

(PSD

42-47).

address

changed.

to

by

the

types,

differentiated

are

used as the

15

is

a 0, then bits 16-31

address of

contained

When

of

the

instruction

the

contents

indirect

reference

22-bit

form a 22-bit

by

flag.

bit

direct

the

15

of

direct

address. When are

23-bit

least not

concatenated

to

form a

case,

displacement

significant

subjected

to

the

16-31

Register

In

either by to

produce a 24-bit the are equivalent

MEMORY

In a

SIGMA 9 computer,

0

controlling the

memory map and provides for dynamic access master-protected vides memory write within the first 131,

the

protection

bit 0 is

22-bit

the

22-bit

effective

position. Since real

to

mapping,

actual

use of main memory by a program;

the

relocatability

through inhibitions imposed on

mode programs. The memory lock

protection

072 words of memory.

a 1

and

bit

with

the

contents

direct

address.

direct

address is

value

(halfword virtual address

the

final

address.

ADDRESS

two methods

memory

CONTROL

are

lock.

of

programs and for

for all modes of programs

15

is

a 1, bits

of

the

then

alignment

that

extended

effective

available

The memory map

Extension

modified

of index)

has a 0

addresses

address is

for

they

slave

or

pro-

in

are

22 Mai n Memory

Xerox Data Systems Sigma 9 Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual