XDS 910 Reference Manual

Xerox

Data

Systems

Reference

Manual

XDS

910

BASIC

INSTRUCTIONS

ICentral

Processorsj

Vlnemonic Code

Name

Page

Mnemonic Code Name

Page

LOAD/STORE

TEST/SKIP

LDA

A,

T

76

Load A

from

Memory

SKG

A,

T

73 Skip if A

Greater

Than Memory

13

STA

A,

T

35

Store A

in

Memory

SKM

A, T

70

Skip if A = Memory on B Mask

13

LDB

A,

T

75

Load B

from

Memory

SKA

A, T

72 Skip if A and M

Do

Not

STB

A,

T

36 Store B in Memory Compare

Ones

13

LDX

A, T

71

Load Index

from

Memory

SKN

A,

T

53 Skip if Memory

Negative

14

STX

A,

T 37

Store Index

in

Memory

EAX

A, T

77

Copy Effective Address into Index

SHIFT

ARITHMETIC

RSH

N, T

066

OOOXX

Right Shift

AB

14

RCY

N, T

066

200XX

Right

Cycle

AB

14

ADD

A,

T 55

Add

Memory to A

LSH

N, T

067

OOOXX

Left Shift

AB

15

MIN

A,

T

61

Memory Increment

LCY

N, T

067200XX

Left

Cycle

AB

15

MDE

A,

T 60

Memory Decrement

NOD

N, T

067

100XX Normalize, Decrement X

15

SUB

A,

T

54

Subtract Memory

from

A

MUS

A,

T 64

Multiply Step

CONTROL

DIS

A,

T 65 Divide Step

10

HLT

00 Halt

15

NOP

20 No

Operation

16

LOGICAL

EXU

A, T 23 Execute Instruction

in

Memory

16

ETR

A,

T

14

Extract

10

BREA

KPOINT

TESTS

MRG A, T

16

Merge

10

EOR

A,

T

17

Exclusive

OR

11

BPT

1

04020400

Breakpoint No. 1 Test

16

BPT

2

04020200

Breakpoint

No.2

Test

16

BPT

3

04020100

Breakpoint

No.3

Test

16

REGISTER

CHANGE

BPT

4

04020040

Breakpoint

No.4

Test

16

RCH

46

Register

Change

11

XAB

04600000

Exchange A and B

11

OVERFLOW

BAC

046

10000 Copy B into

A,

Clear

B

11

OVT

o 40 20001 Overflow Test; Reset

16

ABC

046

20000

Copy A into

B,

Clear

A

11

ROV

o 0220001 Reset Overflow

16

CLR

046

30000

Clear

AB

11

BRANCH

INTERRUPT

EIR

002

20002 Enable Interrupts 20

BRU

A,

T

01

Branch Unconditionally

12

DIR

00220004

Di

sabl e Interrupts 20

BRX

A,

T

41

Increment Index and Branch

12

lET

04020004

Interrupt Enabled Test

20

BRM

A, T 43 Mark Place and Branch

12

!DT

040

20002

Interrupt Disabled Test

20

BRR

A,

T

51

Retu

rn

Bronc

h

12

AIR

002

20020

Arm

Interrupts

21

Legend: A = address,

*A = indirect

address; T = tag field; N = number

of

shifts

Price: $3.25

XOS

910

COMPUTER

REFERENCE

90

00

080

February 1970

MANUAL

Xerox

:91963-1970,

Data

Systems/70i

Xerox

Data

Systems,

Inc

South

Aviation Bouievard/Ei Segundo, Caiifornia 90245

Printed

in

U.S.A

This

publication, Manual, cated

by a vertical

90

00

90

08C,

00

dated

line

08D,

in

the

is a minor

April

1966.

margin

REVISION

revision

Changes

of

the

of

to

affected

the XDS

the

page.

910

edition

Reference

are

indi-

Title

XDS SYMBOL XDS MONARCH Reference XDS

910/925

XDS

910/920

Manual XDS FORTRAN II Reference XDS

900

XDS

ALGOL

XDS

Project

XDS Business Language

XDS

Sort/Merge

XDS

900 Series

and

META-SYMBOL

Programmed Computer EXAMINER

Series

FORTRAN II

60

Reference

Management

Reference

Reference Manual

Utility

and Debug

Operators

System

Manual

Technical

Diagnostic

Manual

Operations

Manual

Reference

Manual

Package

PUBLICATIONS

Manual

Manual System

Manual

(AID)

Technical

Publication

90

05 06 900566 90 00 18

90

00 19 90

00 03 9005

87 90 06 99 90

08 18

90

1022 9009 01

20

No.

97 13

ii

CONTENTS

GENERAL DESCRIPTION

1.

Introduction XDS910 XDS910 Instruction Specia I Characteristics Programmed

MACHINE INSTRUCTIONS

2. Introduction

Load/Store Arithmetic Logical Regi Branch Test Shift Contro I Instructions Breakpoint Overflow Floating-Point

INTERRUPT SYSTEM

3. Priority

Interrupt Interrupt Interrupt

and

Special

Registers Memory

Word Format

Instructions

ster

Change

Instructions

and

Skip

Instructions

Tests 16

Instructions

Assignment 18

Level Arm/Enable Enable/Disable

Tests

Systems

Operators

Instructions

Operations

Interrupts

Response

Instructions

10 11 12 13 14 15

16 17

18 19

20 21

APPENDIXES

1 2 3 4 5 6

8 8 9

A.

CONVERSION

XDS Table Octal-Decimal

Octal-Decimal

B.

TWO'S

COMPUTER

C.

D.

DETAILED MACHINE

PROGRAMMED OPERATORS

E.

INSTRUCTION

F.

INDEX

COMPLEMENT ARITHMETIC

Instruction Typical

Buffered

Functional

Numerical

Alphabetical

TABLES

Character

of

Powers

OPERATING

Execution

Interrupt

Input/Output

LISTS Categories

Order

Codes

of

Two

IntegerConversion

Fraction

Order.

Conversion

PROCEDURES_

FUNCTIONS

Cycle

Table_

Table

Index-1

A-1 A-2 A-3 A-7

A-10

A-11

A-13 A-15 A-17

A-19

A-21 A-26 A-29

ILLUSTRATIONS

4.

INPUT/OUTPUT

Introduction. Primary Buffer

Standard Standard Single-Word Interlaced Direct Single-Bit

CONTROL

5. Controls

Displays

6.

PERIPHERAL

Input/Output Paper

Card

li

Moanetic

Input/Output

Control

Parallel

CONSOLE

EQUIPMENT

Tape

Input/Output

ne Pri

nter

v

SYSTEM

Instructions

EOM

Buffer

EOM

Instructions

Buffer SKS

Transmission

Block Transmission

Input/Output

Tone T

• - 1- . -

Instructions

Input/Output

Typewriter

nnut/Outnut

'.---,

- - - 1- - -

___

23 25 26 28

29 30 32 34 35

36 37

38 38 43 48

52

XDS910 XDS

l.

Basic Register Flow Diagram 3

2. Interrupt

3. XDS

4. Interlace

5.

6.

XDS910Controi Card

7.

8.

Printer

Switches

9.

Instruction

10.

Priority Buffer

1l.

Transmission

12.

Buffer

Transmission

Computer

910

Computer

Arm-Enable

910

W (Y) Buffer.

Input/Output

Read

into

Control

Interrupt

Operation,

(Frontispiece) Configuration

Panel Memory in Indicator

Execution

System Diagram

Single-Word

Interlaced

Response

Hollerith

lights

Diagram

and

TABLES

I

nte

l.

2.

3.

4=

rru pt Leve I s

Y Buffer Unit

Address

Format

Character

Codes

Control

Assembly

Characters

Options

iv

2

19 24 32 36 43

48

A-12 A-14

A-16

A-18

18 25 27 51

iii

XDS

910

Computer

iv

1.

GENERAL

DESCRIPTION

INTRODUCTION

The XDS 910, Figure 1,

general-purpose,

characteristi

24-bit

•

Bi

•

nary

Single-address

•

Index Register Indirect Programmed

• Basic

•

• Typical

core

able

to

dressable

2048-

and

indexing)

Fixed-Point

Add Multiply

digital

cs:

word, plus arithmetic

instructions

Addressing

memory

16,384

and

execution

words. All words

with

8-microsecond

4096-word

in microseconds:

Operations

16

248

Operators

is a high-speed,

computer

parity

bit

with

of

2048

or

4096

cycle

memory modules

times

(including

with

are

low-cost,

the

following

words,

di

rectly

time

available

memory

expand-

ad-

access

Buffered

•

characters/second Standard

•

Display Full-word The minimum

photoelectric board punch.

Optional

•

Input/output Keyboard pri

punch 300-character/second

character/second tape

MAGPAK Magnetic

and Card

reader/punch,

input/output

simultaneous

input/output

and

manual

input/output

910

printer

input/output

spoo I ers

BC

readers,

with

typewriters

nter

Magnetic

tape

D), disc

card

at

rates

control

buffer

system

paper

units

line

tape

paper

devices

with

paper

tape

Tape Systems

(IBM-compatible;

fi

les

punches, printers

in

excess

with

of

internal

includes

reader

tape

reader

tape

punches,

combination

of

60,000

computation

registers

either

reader

readers,

a

or a key-

and

paper

binary

card

60-

Floating-Point

Add Multiply

Add 896 Multiply

Program

•

Series Computers Parity

•

Priority

•

Two 38

Up

Memory

•

tional

tents

of programmable registers

Operations

24-bit 432

464

39-bit

1696

interchangeability

checking

Interrupt

standard

more,

to 896

nonvolatile

power

Fraction

of

memory

System

XDS

optional

fail-safe

hardware

special

in

event

feature

(plus

with

and

of

9-bit

other

I/O

operations

interrupts;

system

power

permits

exponent)

XDS 900

up to

interrupts

failure;

saving

con-

op-

Off-line punched

Communications display

A to D ment,

MONARCH

•

pi I

er,

and

complete All

•

silicon O Dimensions (inches):

Power:

. t 100 to

peratmg

Doubl e

mounting:

Single

mounting:

110v,

facility

cards

osci 1I0scopes,

converters,

and

other

Monitor

META-SYMBOL Assembl

software

semiconductors

emperature

rack

60

for

printing

or

magnetic

equi

pment, tel

graph

digital

special

Routine, FORTRAN

package

65-1/2 x 48-1/4 x 25-1/2

75-3/4 x 25-1/4 x 25-1/4

cps,

range:

17

amp

system

directly

tape

etype

plotters

multiplexer

equipment

er,

as

0

55

from

consol es,

equip-

II

Com-

part

of

C

Up

to

896

special

I I I I

I I I I I I , , I I I

I I I I I I I I I : I

system

interrupts

Items with

dotted

lines

are

optional.

Single-Bit

and

Sense

Word

Parallel

(24 lines) .....

Buffer

Interrupt

Character

(6

bits,

plus

Buffer

parity)

XDS

The

910

Central

control

the

The A,

are

ison,

The

metic

The register.

doubl

The address least provide

The memory address time

wise

registers.

programmer

REGISTERS AVAILABLE TO

B,

available

test,

24-bit A register

operations.

24-bit B register

e-prec

24-bit X register

modification.

significant

an

14-bit P register

the

instruction

specified

Processor

Four

and

four

X,

and P registers

to

the

branch,

It

contains

i sion numbers.

indexing

by

bits

of

and

an

is

the

programmer for

(address

capability

Control

to

Device

910

of

are

program

is

the

is used as an the

is used to

Indexing

(Program

instruction

being

program (with a

---l

.....

I/O

---

...

~~~,-----~~--~

Lines

----------------~

Full-word

I/O

33

(24 bits)

W Buffer

Figure 1.

XDS

Computer

31

Buffer

XDS

REGISTERS

contains

the

main

less

eight

registers

not.

THE

(see Figure 2,

significant

hold

operations

portion)

of

Counter)

executed.

are

PROGRAMMER

arithmetic,

control

accumulator

before

operations.

extension

the

of

up

to

16,384

contains and

Unless

branch,

arithmetic

available

heavy

lines)

compar-

for

arith-

of

the

portion

index

the X register,

with

during

skip, or

of

value

the

words.

the

other-

910

2048

4096

I I

I I I

~2~~

I

Full-word

___

Buffer I

I (24 bits) I

L------4-,

Y Buffer

910

Computer

and

to

A

in

14

the

Configuration

EXECUTE incremented

REGISTERS

The

S,

are

not

are

used by

struction

The

14-bit S register

location

The C

ter.

All

are

brought

modification

in

the C register.

are

routed

The

6-bit 0 register

instruction

The

25-bit M register

tains

each Whenever register destructive

Memory

or

__

..,

lJ

to

I/O

Device

instruction),

by 1

NOT

C,

0,

directly

the

execution.

to

be

register

instructions

into

and

through

being

computer

memory is

are

copied

readout

expandable

_

l~--------_v~--------~)

2048

Character

(6 to

24

bits,

the

contents

after

each

AVAILABLE TO

and M registers

available

910

accessed

is a 24-bit

the C register

parity

the C register.

executed.

back

to

Central

contains

for

instructions

arithmetic

and

data

generation/detection

Also,

all

contains

(24-bit

word as

accessed,

into memory, thus assuring

of

data

and

to

16,384

or

4096

Buffer

plus

parity)

of

the P register

instruction

THE

PROGRAMMER

(see Figure 2,

the

programmer,

Processor to

the

address

and

obtained

for

decoding.

input/output

the

operation

word, plus

it

is

accessed

the

contents

instructions.

words

r

-,

I I

L_..J

words

is

executed.

light

but

implement

of

the

memory

or

data.

control

from memory

parity

regis-

Address

take

operations

code

of

bit)

from memory.

of

the

are

lines) they

in-

place

the

con-

M

non-

2

A

(Main

Accumulator)

(Ins

P

(Program

S

Register

(Memory

Register

0

Reg.

true

tion)

Register

Counter)

Address)

B

Register

(Extended

1

.

C

Register

(Arithmetic

-----------------~

Accumulator)

II

and

Control)

X

Register

(Index)

•

,

M

~

Register

(Memory

Memory

Access)

The

basic

2048-

or

size

of

24

word

memory

cessor

and

all

memory.

octal

location through memory), memory memory An available

into eration, ecuted. termine

is

Before

the can

loss,

be

transient

The

checks

07777

in a 16K where

attempt

such a location

the

operating.

accessing a memory

power

be

successfu

the

inc I uded

computer

for

XDS

910

4096-word

bits,

plus

modules

the

input/output

Addresses

00000

(4K

or

00000

the

to

read

causes

with

the

Thus, a

memory

to

ensure

Ily

computer

that

power

failure

automatically

it

during

XDS

910

memory

magnetic parity.

are

through

memory),

through

system

zeros

to

essentially

program

size

that

compl

halts.

prevents

or

each

MEMORY

consists

core

Additional

available.

buffers

for

memory

03777

00000

37777

is a

IIwrap-aroundli

location

be

read.

can

use

of

the

word,

the

entire

eted.

Special

loss

of

manual

generates

read/write

Figure

of

one

module

The

can

directly

words

(2K

through

(16K

memory).

after

37777

whose

An

attempt

results

machine

in a IIno-opli

in

sequence

this

property

the

computer

read/write

If

it

detects a power

logic

information

power

even

cycle.

2.

random

with a word

2048-

or

Central

extend

memory),

17777

or

circular

is

00000.

address

to

being

to

within

shutoff.

which

checks

cycle

(optional)

due

pari

ty

Setting

Basic

access,

4096-

Pro-

address

from

00000

(8K The

is

not

store

op-

ex-

de-

may

to

or

a

Register

it

Flow

Diagram

control automatically

An XDS

long.

panel

910

pari

ty

in

case

MEMORY

Computer

swi

of

tch

parity

WORD

word

causes

error

FORMATS

is

24

the

computer

detection.

binary

digits

o I 2 3 4 5 6 7

IIIIIIIIIIIIIIIIIIJ

o

123

4 5

67 8 9101112131415161

These

bits

are

or

most

significant

least

significant positions bit 9 refers

For

ten the number,

lent are vidual and bits

or

simplicity

in

octal

absolute

000001010011100101110111,

to

the

also

numbered

bits,

octal 7 the

9,

10,

numbered

bit

numbers

to

bit

of

notation.

value

8-digit

with

least.

and

11.

end

description,

octal 0 being

end

of

the

position

Since

of

three

octal

in

the

Octal

(as

shown

of

the word.

use

this

9).

binary

number

same

above)

word,

All

numbering

computer

one

octal

digits,

01234567.

general

the

most

3,

for

example

II

18192

from

to

the

references

scheme

words digit

the

is

Octal

manner

significant

to

hal

(bits)

Jill

212223

the

left,

right,

or

to

(e.g.,

are

writ-

represents

24-bit

equiva-

digits

as

indi-

digit

refers

to

t

bit

3

The

computer

012

Bit

position

coding

INSTRUCTION WORD FORMAT

3

instruction

0 is

not

word format is:

8910

used

by

the

Address

centra

logic.

I I

I processor

Field

de-

23

Three-I

octal

note

etter

instruction

Programmed

combination

1,

3,

5,

and

are

discussed

acteristics,

Programmed

codes

Operators.

with tags

7,

respectively.

further

II

and in

FIXED-POINT

Operator

100-177)

of

0, 2, 4, 6, results in tags

mnemonics (they

are

usually used to

The

high-order

Programmed

in this

Appendix

section

E.

under

FORMAT

1-bit,

Operators

"Special

have

dein

of

Char-

Bit

position 1 contains

Bit positions 2 through 8 field

which

determines

The Programmed

position field

Bit position 9

2;

this

bit

(bit

positions 0 through

contains

Bit positions 10 through which

usually

called

for by

The following

represents

the

coding

the

contain

the

Operator

position

the

23

the

instruction

examples

index

operation

feature

is a

indirect

contain

SYMBOL format in expressing

LDA

A,

T

where:

LDA

is a

representative

A is a octal

To

express

indirect

address

asterisk to

LDA

interpretation

The

2)

integer,

representative

integer

that

indirect

position),

the

address

*A, T

of

T,

is

address,

represents

addressing

the

field:

the

tag

Tag Field Integer

T

Interpretation

register

the

in

Iso

bit

instruction

to

be

the

910

part

of

performed.

the

2).

address

the

location

address

of

the

bit

code.

use

standard

instructions.

mnemonic

This format is

instruction

and T is a 1-digit

the

tag

field.

(that

is, a

1-bit

programmer

field

(bit positions 0 through

prefixes

(X).

code

uses

bit

II

tag"

(I).

fie Id,

operand

META-

in

code,

the

an

Fixed-point

data

o 1

Numbers with position negative numbers

The memory holds with

1. A cision of a fixed-point

Programmers integers, tion to

When performing

the the

points

The memory holds complement cally system.

plement

held

the

sign

0, in

numbers

have

an

assumed

full-word

of

over

sometimesconsiderfixed-point

with

23.

The

+8,388,607

program must capacity

so

as to

form

on

these See

arithmetic.

in this format

incorporated

the

a 0 in

six

the

range

(-2

of

arrive

numbers using a

Appendix

words

have

the

format

are

8-digit

as

the

"Ieading

most

have

a 1 in

bit

fixed-point

binary

point

number has

decimal

significant

position

digits.

octal

bit

position 0 and

O.

numbers as

to

the

left

an

equivalent

The

number is from -1 to less

binary

23

computations scale

the

negative;

and

point

of

integer

to +223_1).

the

values

computer

at

correct

fixed-point

the

computer

to

the

right

values

with

is

fixed-point

to

keep

registers, and

results.

operates

two's

complement

B for a discussion

octal

bit,

digit.

23-bit

of

bit

range

of

than

numbers as of

from

-8,388,608

them

align

numbers in

arithmeti-

of

two's

numbers,

II

bit

Thus,

positive

fractions

position

pre-

values

+ 1.

bit

posi-

numbers,

within

binary

two's

number

com-

23

o (or

blank)

2

3

4

5

6

7

No

relative

address, no

no Programmed Programmed

Operator

Index

Programmed

Relative

Programmed

tive

address

Both

relative

Programmed

and

relative

Operator

address

Operator

Operator,

address

Operator

address

4

index,

and Index

and

rela-

and

index

index,

FLOA

XDS

offers

standard

for performing

point

arithmetic.

mats

are

double-

described

Double-Precision,

Most

significant

o 1

lING-POINT

Programmed

and

Standard

below.

Floating-Point

word

FORMAT

Operator

subrouti nes

single-precision,

floating-point

Format

floating-

number

for-

23

Least

significant

word

SPECIAL

CHARACTERISTICS

o

The

fractional

point

number

ing

bit

being

just

bit

(bit 1 of

nent

is a

sign.

Standard

exponent

contents

tents

of

x 2±E.

F

Double-precision,

decimal

exponent

Standard significant location the B register,

Single-Precision,

Fractional

is a 39-bit

being

the

to

the

9-bit

in

two's

of

the

exponent

digits

of

range

Programmed

word

M+

1,

word

portion

sign left

of

upper

integer,

routines

complement

fractional

field,

floating-point

precision

of

10-

Operators

is

in

the A register,

and

that

or

stored

Floating-Poi

141516

of a double-precision,

proper

bit

and

the

most

word).

with

77

The

the

operate

form.

fi

eld

and E represents

the

and a decimally

to

10+77•

the

less

in memory

nt

fraction,

assumed

significant

leading

on

number

numbers

assume

significant

Format

with

floating-point

bit

both

fraction

If

F

has

that

or

stored

location

floating-

the

binary

represents

have

point

magnitude

expo-

being

and

the

form

over

equivalent

the

more

in memory

word

M.

lead-

the

con-

is in

23

11

Certain vide program

Address and

In

performs

tion

tion of of

Indexing

The modification. address execution

If

computer X instruction retain

address

computer

significant

running

modification

indirect

both

indexing

address from remains

the

address

the

instruction

computer

in

bit

position 1 of

register

any

bi

memory

an time.

adds

t.

economi

time.

ADDRESS

addressing,

and

modification

in

memory

modification

contains

The

instruction

the

to

the

prior

to

overflow

features

es

MODIFICATION

is

accomplished

used

indirect

but

before

in

operand.

an

use

of

does

an

instruction

contents

execution.

or

carry

simplify

in

memory

singly addressing, after

executing

its

original

forms

index

this

register

not

of

bits

of

the

This

beyond

programming

uti I ization

through

or

in

bringing

it.

form. The

the

"effective

(X)

register

increase

contains

10

through

address

addition

the

and

indexing combination. the

computer

the

instruc-

The

instruc-

address"

for

address

to

modify

instruction

a 1,

23

of

field

of

does

most

significant

pro-

and

result

the

not

" 1

v I

Exponent

word

o

The

fractional

point

number

ing

bit ing just The

floating-point

leading

fraction

Single-precision, decimal exponent

Standard

tional

word

and

that

location Operator ignored.

is a 24-bit

being

the

to

the

sign

bit.

and

exponent

digits

range

Programmed

is

the

exponent

M. When

routine,

portion

sign

left

of

the

exponent

Standard

floating-point

of

precision

of

10-

Operators

in A,

or

enterina

bits

141516

of a single-precision,

proper

and

in

77

stored

word is in

0-14""

fraction,

the

assumed

most

significant

is a

9-bit

routines

two's

and a decimally

to 10+77•

of

operate

complement

numbers

assume

in memory

B,

or

a stcmcJrm1

the

ex~onen;:~;d··;r-e

.

binary

integer

that

stored

floating-

with

the

point

magnitude

with

on

both

form.

have

over

equivalent

the

frac-

location

in memory

Prnnrnmmpej

lead-

be-

a

M+

23

bit.

six

1,

The

computer's

modifying

information

Indirect

The struction. the tion

A 0 in puter tions requested posi X

A 1 in puter

as an

reinitiates by

For puter

contains accumulator

Addressing

indirect

computer

being

bit

to

use

10-23

tion

causes

register

bit

to

decode

described

instruction

the

instruction.

example,

to

obtain

00001005)

instruction

and

testing

between

address

This

uses

executed.

position 9 of

the

of

by

the

to

this

position 9 of

above,

code;

address

the

(A

the X register

bit

position

indirect

contents

the

instruction)

instruction.

the

computer

address

the

contents

as

that

decoding,

instruction

a

\AlOrd

and add

register).

set

provides

the X register

is in

bit

position 9 of

determines

addressing

an

instruction

of

the

address

as

A 1 in

to

add

to form

an

if

is,

from

it

the

instruction

of

the

were

an

the

computer's

using

ADD

location

it

to

However,

instructions

and

memory.

whether

with

causes

field

the

14-bit

the

contents

effective

causes

location,

instruction

the

word

01000

the

contents

if

the

for

transfering

the

instruc-

the (bit

index

address.

the

accessed

address

specified

causes

(assume

instruction

for

in-

or

not

com-

posi-

address

bit

of

the

com-

without

logic

the

com-

it

of

the

5

ADD

*01000

location

and

lator. indirect Indirect

one

level

If

the

01000,

adds

If

address addressing

cycle

of

indirect

instruction instruction) index

register struction

Exampl es:

The

octal

used in

tents

of.

the

"

Location

is

given,

decodes

the

contents

the

word in

bit,

time

to

addressing

also

calls

are

before

indirect

Indexing

instruction

examples

Contents

to

each

(or

any

added

and

the

computer

the

of

location

the

process

as

many

instruction

subsequent

for

indexing,

to

addressing

Indirect

code

for LOAD A

is

76.

Effect

address

01005

01000

of

decoding

levels

cycle

performed.

word

the

address

occurs.

Addressing

Parentheses

obtains

it

contains

to

also

has

as

specified

time,

treated

contents

field

register

denote

the

accumu-

a 1 in

is

reiterated.

for

of

the

word

in

(01005),

the

adds

each

as

an

of

the

in-

(L

DA),

"con-

A program anyone

can

time;

use up to

however, programmer-specified, nate

sets

or

subsets

of

program to program,

same program. The

tors

is

without

than

64

900

Series structions monic

designations

example, ADD) refers to a computer,

routine

to-one

900

puter A more

in

instruction

Series

in

detailed

Programmed

limit,

in

one

program.

maintain

through use

whi Ie

it

may

another.

Computer

the

series.

Operator

are

the

built-in

refer

relationship;

discussion

64

Programmed

since

Programmed

the

programmer

the

64

Programmed

or

from

section

total

number

but

it is

inconvenient

Other

compatibil

of

ity

Programmed

identical

designation

machine

to a Programmed

This

technique

can

be

executed

and

a list

subroutines

Operators

can

select

Operators

to

section

of

Programmed

to use more

computers

in

among symbolic

Operators.

in

all

computers.

"FLA"

(for FLOA TIN G

instruction

Operator

preserves

programs

are

written

on

any

of

standard

in

Appendix

of

Opera-

the

in

one

the

other

at

alter-

the

XDS

in-

Mne-

sub-

one-

for

com-

XDS

E.

are

from

For

one

X

register

01000

01001

01002 01003 02000 02001

02002

02003

00000001

00001001 00041002 00001003 00000002

076

276

07641000

27641000

PROGRAMMED OPERATORS

Programmed a program by the

some mnemonic form

The

computer instructions mined by address maintained.

location

address

Programmed letter,

built-in

Operators

giving a single

interprets

and

each

at

location

By

00000,

of

the

Operator

mnemonic

machine

01000 01000

transfers

code.

00000 means the

subroutine

call

ing

designations

instructions

(1000) = 00001001 ( 1

000 + 1) = (1

00041002

( ( 1 000)) =

00041002~A

( ( 1

000

----.A (1

+ 1)) =

001) =

((1

001 )) =

~A

(41002) = ((1002)) = (1003) =

00000002~A

permit

as

the

to a

The

of

so

indirect

subroutines

"calling"

built-in

codes

0100-0177

subroutine

computer

that

program

can

to be used in

instruction

machine

instructions.

as

uniquely

records

the

continuity

addressing through

gain

access

instruction.

subroutines

are

in

the

same

described

assigned

manner

in

Section

of

special

deter-

return

to

the

three-

as

2.

OVERFLOW

An

overflow

to

recognize

during

indicator the

following

1. The contained

2. A position 0 of

3.

The MULTIPLY

-1 in positions

contents

If

the

appropriate

contains

of

the

The

only FLOW skips

if

of

the

detector

erroneous

the

execution

on

the

control

conditions

result

of within

left-shift

the

of

operation

effective

21

through 23

the

OVERFLOW

reset

instructions

OVERFLOW

instruction

indicator

is

OVERFLOW is

OVERFLOW

in

the

computer

arithmetic

of

a program. The OVERFLOW

panel

is

makes

operations

set

whenever

occur:

an

addition

or

subtraction

the A register.

changes

the

the A register.

STEP

instruction

memory

A reg

ister

indicator

instruction

to

reset

of

is

or

is

location,

the B register,

divided

set,

it

remains

is

executed.

test

and

indicator.

affected

OVERFLOW

indicator

reset.

by

the

TEST

Thus, if

can

be

state

(OVT),

desired,

ignored.

it

that

cannot

contents

executed

100 in

by 2 is

reset

of

the

which

possible

occur

any

of

bit

with

bit

and

the

zero.

set

untii

Section

the

state

OVER-

the

state

be

2

is

To

determine causes executing dicator.

is

RETURN

(where $ is

whether a particular

overflow,

the

An

reset

instruction;

instruction

BRANCH

the

location

and

sets

the

then

that

(BRR).

of

the

OVERFLOW

program

OVERFLOW

test

the

may

be

used to

The

instruction

the

BRR)

"branches" to

instruction

indicator

before

OVERFLOW i

set

overflow

BRR

$, 4

the

indicator.

n-

6

The

execution interrupt of med places position a of

indicator.

(BRM) bit not

The merges

the

location cator.

instructions.

The XDS

three

1.

2.

3.

A program

MARK

automatically

subroutines

the

OVERFLOW

Operator

the

places

position a of

disturb

instruction

the

contents

and

Section 2 contains a description

910

kinds

Normal eters

are

the A register Interrupt

an

interrupt

Programmed

enters

PLACE

of

Programmed

automatically

indicator.

instruction,

status

of

the

location

The

the

OVERFLOW

contents

of

places

SUBROUTI·NE EXECUTION

Computer

of

subroutines:

closed

specified

subroutine

AND stores

00000

instruction

status

the

effective

RETURN

of

bit

position a of

the

subroutine

Operator

a normal

BRANCH

the

Operator,

In

the

computer

OVERFLOW

and

MARK

of

the

OVERFLOW memory

indicator.

BRANCH

the

OVERFLOW

the

result

in

makes

it

possible

where

in

appropriate

that

is

entered

subroutine

closed

(BRM)

contents

executing a Program-

resets

the

subroutine

of

closed,

preserves

automatically

indicator

the

PLACE

(BRR)

AND

location

automatically

indicator

effective

OVERFLOW

of

to

the

input

registers

as

instruction;

the

program

and

the

status

in

bit

OVERFLOW

BRANCH

indicator

memory

the

execute

the

via

and

with

indi-

branch

param-

such

result

a

BRM

counter

in

does

as

of

(P

register)

in

the

branch-to

mally

the

location

BRANCH the ister

Section

i

nstruc

Interrupt by automatically to

be ecution a

fixed

location

address

BRM tents the

to

the the ferred value struction the

BRANCH indirect the the clears this uses

(BRR)

main

program;

value

2, Branch

ti

ons.

subroutines

the

detection

entered.

to

be

location

normally

of

the

is

executed,

of

the P register

branch-to

instruction

to

the

stored

to

interrupt

UNCONDITIONALLY

addressing subroutine) completion

the

interrupt

differs

the

BRR

and

the

status

location.

of

the

instruction

the

BRR

and

transfers

Group,

are

of

program-controlling

cause

the

An

interrupt

suspended

corresponding

contains a BRM

interrupt

it

automatically

and

location.

location

process

appropriate

from

P,

therefore,

which

program

is

serviced

(through

returns

of

the

subroutine.

from

the

norma I

(stored P value

of

the

The P

BRM

accompl adds

control

for a

closed

appropriate

causes

and

control

servicing

the

OVERFLOW

The

BRM

+ 1. (When

is

completed,

BRM

without

control

by

the

control

the

to

active

closed

+ 1

OVERFLOW

register

instruction. A RETURN

ishes

one

to

that

description

subroutines,

interrupt

normal program

to

that

interrupt.

instruction

subroutine.

stores

then

an

and

disturbing

is

the

address

should

interrupt

(BRU)

branch-to

the

main

BRU

state.

subroutine

---..

P).

indicator

value

the

return

the

stored P reg-

location.

of

the

initiated

interrupts,

subroutine

be

transferred

with

When

the

current

indicator,

transfers

interrupt

control

of

return

subroutine).

instruction

location

program

indirect

Note

return

is

nor-

to

See

branch

that

ex-

The

the

the con-

control

occurs,

is

trans-

P.

The

the

in-

after

with

of

at

also

that

to

in

A

7

This

section groups. and A-21,

A companies

ing identifies ter used indicates instruction, cates ory.

If

indexing tion 9 of addressing instructions field; memory, tion

The

criptions:

Lists

alphabetical

A-26,

diagram

each

diagram

X in

bit

with

that

bit

position 1 of

cannot

the

these

but

code

following

INTRODUCTION

describes

of

and

representing the

description

the

instruction.

position 1 indicates

the

instruction,

that

indirect

and

the

instruction

cannot

are instructions

use

of

the

statements

XDS

instructions

order

are

A-29

respectively.

the

is

the

mnemonic

addressing

the

letter

the

instruction

be

used with

diagram

be

used

shown

with

do

the

address

instruction.

apply

910

in

given

format

of

each

Within

the

letter

M in

obtains

the

with

octal

not

field

instructions

functional,

in

Appendix

of

the

instruction.

code

and

the

diagram,

that

indexing

I in

bit

can

be

the

address

an

operand

diagram

instruction;

contains

the

instruction.

numbers in

require

to

an

to

extend

the

instruction

2.

MACHINE

in

functional

numerical,

F,

pages

instruction

Preced-

name

that

the

can

be

position

used

with

the

field

indi-

from

mem-

contains a 0,

if

bit

a 0,

indirect

Some

the

address

operand

the

from

opera-

de-

ac-

let-

9

posi-

INSTRUCTIONS

The

interrupt

of

any

BRANCH Instruction

where required Indexing but

each

ditional

LOA

o 1 2 3

LOA

loads

into

the A register;

location

Affected:

STA

o 1 2 3

system

instruction,

(BRX)

timing

each

cycle

for

fetching

does

level

memory

except

and

is is 8 microseconds,

not

change

of

indi

cycle

LOAD/STORE

LOAD A

76

I

the

contents

are

not

affected.

(A) Timing: 2

STORE A

8 9

can

interrupt

INCREMENT INDEX

ENERGIZE OUTPUT M (EOM). given

in terms of memory

the

instruction

the

rect

addressing

to

the

program

including

and

timing

instruction

of

used

all

operands.

any

instruction,

adds

timing

at

the

AND

cycles,

the

one

given.

INSTRUCTIONS

M

of

the

contents

10

effective

of

the

M

memory

effective

location

memory

end

time

ad-

23

Parentheses

"(A)"

means

Subscripted tions. tents ter.

The expressed octal ing 2008 and

The term

cation conclusion term is sometimes is

the

The term

effective

The term

a

computer

means

or

IIturn

For

of

bit

contents

as

numbers used in this

zero,

but

200 = 200

"effective

in memory from

of

all

location

"effective

memory

"set"

means

word,

"place

off"

a z.ero

an

denote

characters

example,

positions 18 through

whose

indicator,

"contents

"(Bh8-23"

of

computer

octal-coded

decimal

memory

indirect

shortened

operand

location.

or

numbers do

,

10

which

addressing

address

"place a l-bit

"turn

in

the

or

of

the A register."

identify

words binary

manual

location"

the

operand

to

"effective

is

ll

means

on"

an

contents

"clear

of".

For

example,

inclusive

means

"the

23

of

the B regis-

and

registers

numbers;

contain a leadnot.

refers

to

is

taken

and

indexing.

location."

the

effective

the

contents

in

the

contents

indicator.

of" a computer

to

zeroll.

bit

all

Thus,

the

address.

II

posicon-

are

other

0200

lo-

at

the

This

of

the

of"

Reset"

word,

It

STA

stores

the

contents memory affected.

Affected:

LOB

location;

(M)

LOAD B

75

,

o 1 2 3

=

LOB

loads

into

the B register;

location

Affected:

STB

o 1 2 3

STB

stores

memory

affected:

Affected:

the

contents

are

not

affected.

(B)

STORE B

36

I

the

contents

location;

(M) Timing: 3

the

8 9

the

8910

the

of

the A register

contents

10

of

the

contents

of

the B register

contents

of

the A register

M

effective

of

the

M

of

the B register

in

the

Timing: 3

memory

effective

Timing: 2

in

the

effective

are

not

23

location

memory

23

effective

are

not

8

LOX

LOAD

INDEX

MIN

MEMORY INCREMENT

o 1 2 3

L

DX

loads memory the

effective

Affected:

STX

o 1 2 3

STX

stores

ter

in

the

index

register

Affected:

EAX

o 1 2 3

EAX

copies

into

bit

ten

most

tents

of

71

I

the

entire

location

memory

(X)

STORE INDEX

37

I

the

entire

effective

are

(M)

COpy

REGISTER

77

I

the

address

positions

significant

the

effective

8 9 10

24-bit

into

the

index

location

contents

register;

are

8910

24-bit

contents

memory

not

EFFECTIVE ADDRESS

8 9

10

- 23 bits

affected.

10

of

the

of

the

of

the X register

memory

location;

effective

index

location

M

of

not

M

of

the

M

(X)

the

effective

the

contents

affected.

the

index

contents

INTO

memory

register;

and

are

not

23

of

Timing: 2

23

regis-

of

the

Timing: 3

INDEX

23

location

the

con-

affected.

o 1 2 3

MIN

increases

cation

Overflow 37777777 the

Affected:

by

location.

result

MOE

o 1 2 3

MDE

decreases cation same change.

An

40000000.

Affected:

SUB

by

location.

overflow

61

I

8 9 10

the

contents

one,

and

places

The

contents

occurs before in

only

execution.

M.

(M),

Of

MEMORY DECREMENT

of

the

resulting

of

the A register

when

the In

contents

this

60

I

8910

the

contents

one

and

places

The

contents

occurs

The

(M),

if

result

Of

SUBTRACT MEMORY FROM A

of

the

resulting

of

the A register

the

initial

contents

inmemoryinthiscaseis37777777.

M

effective

sum

do

case,

M

effective

difference

memory in

the

not

change.

of

Mare

40000000

Timing: 3

memory

do

of

memory

Timing: 3

same

in not

23

lo-

is

23

lo-

the

are

The

addressing

a

load

instruction, contents memory executed bit into

Affected:

of

address

with

configuration

bit

positions

ADD

101+1

o 1 2 3

This

instruction

ory

location

the

result

in

the

sign

of

flow has

FLOW

Affected:

occurred

indicator.

(A),

process for this

except

the

effective

is

the

zeros

in

10

(X)

10-23

ARITHMETIC

ADD MEMORY TO A

55

I

that

.memory

operand.

in

bit

positions 1 and

the

address

-23

of

1 I I

the X register.

INSTRUCTIONS

8910

adds

the

contents

to

the

A.

If

result

and

Of

contents

both

in

of

numbers

the A register

the

computer

instruction

instead

location,

For

field

of

the A register

are

of

exampl

of

EAX

M

the

effective

of

the

is

opposite,

has

set

operates obtaining

9,

the

effective

e,

if

EAX

the

actual

is

copied

Timing: 2

mem-

and

places

same

sign

the

OVER-

Timing: 2

as in

the

23

but

over-

54

I

the

contents

are

address

the

sign

overflow

Of

MUL

64

I

indicator

the

contents

8 9 10

of

and

of

the

same

have

of

the

has

occurred

indicator.

TIPL Y STEP

8910

extends

is

set,

of

the

places

been

result

indicator

the

is

o 1 2 3

SUB

subtracts

tion

from

reg i

ster.

If

both

of

the

effective addition opposite, has

set

Affected:

the A register

numbers

but

an

the

OVERFLOW

(A),

MUS

1 2 3

The sign

the

OVERFLOW zeros.

of A temporarily

left

if

the OVERFLOW

Then

effective

sign

in

two

the

compl

and

memory

M

memory

result

in

after

the

contents

emented

the A register

the

computer

Timing: 2

M

bit

positions

is

reset.

bits

extended

location

the

for

If

23

loca-

A

is

23

to

the

are

9

determined

tracted three

operation

ing

from

low-order

table:

B21

by

the

A reg ister,

bits

performed

B22

effective

of

the B register.

takes

place

B

23

address based

Arithmetic

are

on

according

added

the

contents

The

arithmetic

to

Operation

to

the

or

sub-

of

the

follow-

ETR

012

LOGICAL

EXTRACT

14

3

INSTRUCTIONS

M

23

0 0 0 0 0 1 0 0

1 1 1 1 1

The

computer

AB

register

The OVERFLOW tents

of zero. Various erators) can

be

the

form (M) x

first

step,

A

register

left

one,

Affected:

The Programmed

requires

DIS

1 0 0

1

then

two

B21-23

Otherwise,

multiply use

this

repeated

the

multipl

cleared,

and

the

(AB),

248

fJsec for a full

DIVIDE

65

o 1 2 3

DIS

shifts

the

contents

left

one

bit

position

into

B23.

If

(AO) location tracted

tents address

of

determ

from

the A register.

the

memory

are

added

0

1 (A) + 2(M)

1

0

1

0

1

shifts

bit

positions

indicator

were

the

subroutines

instruction.

to

provide a complete

(B)

--+-

the

OVERFLOW

Of

Operator

8 9

and

= (MO),

ined

by

location

to

the A register.

None (A) + 2(M)

(A) + (A) - 4(M) (A) - 2(M) (A) - 2(M) None

the

is

100,

and

OVERFLOW

AB. Prior to

ier

must

double-length

subroutine

multiplication.

STEP

10

of

the

copies

the

effective

---.

A

----.

A

4(M)

----.

A

---.

A

---.

A

---.

A

result

in

the

double-length

to

the

right.

set

if

(M) is

-1,

the

(A)/2

was

originally

indicator

(such as Programmed

Twelve

be

double-length

If

determined

MUS

execution

in

the B register,

AB

indicator

MULTIPLY (MUL)

M

the

complement

contents

address

(AO)

-I

(MO),

is

instructions

multiplication

register

turned

off.

Timing: 2

AB

of

the

memory are the

by

the

con-

reset.

Op-

of

the

shifted

23

register

of

AO

subcon-

effective

ETR

performs a

bits

of

the A register

and

places

operation

lowing:

the

bit

by

(A)

o o

1 1

Affected:

Example:

MRG

o 1 2 3

MRG performs a ponding iocation performs follows:

(A) (M)

bits

and

the

(A)

ETR

MERGE

16

I

of

piaces

operation,

(A)

0 0

1

logical

result

"AND"

and

the

in A. This

corresponding

(M)

o

1

o

1

M

Before Execution

64231567 00777600

89

10

logical

the A register

"Inclusive

the

result

bit

(M) 0

1

0 1

1

between

effective

instruction

bit

according

Result

in A

o

o o

1

After

Execution

00231400 00777600

M

OR"

and

the

in A. This

by

corresponding

Result in A

0

1

corresponding

memory

between

effective

location

performs

to

Timing: 2

memory

instruction

bit,

the

corres-

the

fol-

23

as

The Programmed i nstruc

tion.

Affected:

The Programmed quires

888 vides a corrected original A register.

10

Operator

(AB)

Operator

fJsec for a full

remainder

divide

subroutine

division.

of

the

subroutines

DIVIDE (DIV)

The

subroutine

same

use this

Timing: 2

sign

as

reprothe

Affected:

Example:

(A) (M)

(A)

MRGM

Before Execution

06446254 02340712

Timing: 2

After Execution

06746756 02340712

EOR

EXCLUSIVE

OR

Indirect change

addressing

instructions.

and

indexing

do

not

apply

to

register

I

IOIXIOI

17

o 1 2 3 8 9

EOR performs a

sponding location performs follows:

Affected:

Example:

The selected appear resu

proper

in

Its.

bits

of

and

places

the

operation

(A)

0 0

1 1

(A)

EORM

(A) (M)

memory word

bit

positions

the

memory word, a

I I I

10

logical

the A register

II

Exc lusive

the

result

bit

(M)

0

1

0

Before Execution

34165031

70077021

configuration

of

the A register.

by

M

OR"

between

and

the

effective

in

A.

This

corresponding

Result in A

o

1

o

After Execution

44112010 70077021

logically

If

one's

complement

corre-

memory

instruction

bit,

as

Timing:

inverts

all

"ones"

of

A

23

2

Affected:

XAB

RCH

0

o 2 3

XAB

copies

ister

and

ister

into

Affected:

BAC

RCH

010000

o 2 3

BAC

copies register zero.

Affected:

(A),

(B)

EXCHANGE A AND

46

I

8 9

the

contents

si

mul

taneously

the A register.

(A),

(B)

COpy B INTO

46

I

8 9

the

contents

and

simultaneously

(A),

(B)

of

the A register

copies

the

A, CLEAR B

of

the B register

clears

B

00000

I

into

contents

10000

I

the B register

Timing: 1

the B reg-

of

the B reg-

Timing: 1

into

the

to

Timing: 1

23

A

Example:

RCH

023

RCH

performs

of

the A and

positions

10

o 0 o 1

1 1 1 C

EOR M

Before Execution

(A)

(M)

10357211

77777777

REGISTER

46

I

89101112

the

following

B regi sters,

10

and

11

Function

Exchange A and

Copy B into

0

Copy A into

lear A and

CHANGE

depending

of

the

instruction

A,

B, c lear B (CLR)

After Execution

67420566 77777777

INSTRUCTIONS

0000

I

operations

B (XAB)

clear

upon

on

the

word:

B (BAC)

A (ABC)

va

the

lues

23

contents

of

bit

ABC

RCH

020000

023

ABC

copies

register

zero.

Affected:

CLR

RCH

030000

o 2 3

CLR

clears

zero.

Affected:

COpy A INTO

46

I

the

and

simultaneously

(A),

(B)

CLEAR

46

I

the

contents

(A),

(B)

8 9

contents

AB

B,

of

the A register

clears

of

both

CLEAR A

20000

I

into

the

the A register

to

Timing: 1

30000

the A and B registers

Timing:

23

B

23

to

11

Branch change tents mer

should tions that

the

and

indexed

instructions the

course

of

the

program

note

determined

branch

addressing.

BRANCH

that

by

can

INSTRUCTIONS

conditionally

of

the

program by a

counter

these

the

effective

operate

or

(P

reg

ister).

instructions

address;

with

all

unconditionally

Itering

levels

The

branch

this

of

the

con-

program-

to

loca-

means

indirect

The

order,

BRM

execution

as

given

00777 01000 01006 01007

of

these

by

MARK

instructions

their

PLACE

locations:

AND

is

in

the

BRANCH

following

BRU

o 1 2 3

BRU

takes mined an ority

Affected:

indirect

ing to

by

interrupt

the

BRX

o 1 2 3

BRX

increments by

1.

If

in

bit

position effective in

sequence.

If

a

BRX

is

to

the

index

for

transfer

X

register;

indexed.

BRANCH

01

the

effective

address

level

effective

(P) Timing:

INCREMENT INDEX

41

I

the

resultant X register

9,

location;

instruction

effective

before

is

based

just

UNCONDITIONALLY

8910

instruction

address. A BRU

bit

equal

to 1

then

active,

location.

8 9

10

I

contents

the

computer

if

not,

is

indexed,

address

it

is

incremented.

on

as

if

it

determined

the

BRX

of

takes

incremented

M

from

the

location

instruction

clears

the

in

addition

AND

M

the

entire X register

value

contains a 1-bit

transfers

any

instruction

control

the

by

However,

highest

to

BRANCH

,

instruction

of

the

value

were

deter-

with

pri-

branch-

to

the

control

of

the

test

of

the

not

23

o 1 2 3

BRM

is

normally

turn

to

the

main

has

been

completed.

BRM

stores

the address memory fers subroutine).

indicator tents to

When a BRM (as the cuted

II

is rupt

Affected:

Exampl

control

zeros.

the

turn

stored

system is

of

location

of

bits

result

program

if

location

in this

e:

the

in

the

(M),

BRM

43

I

used program

contents

BRM

(subroutine

to

that

BRM

also

bit 0 of

1-9

of

stored

of

an

instruction

interrupt

ll

instead

instance.

given

(P)

0522

Location

M

to

enter

subroutines

is

desired

of

the P register

instruction

location

the

in

interrupt) P contains

in

stores

effective

an

interrupt

had

of

Section

plus

the

not the

Information

itself)

entry

location)

one

status

location.

that

would

intervened.

BRM's own

3.

Contents

after

in

(first

of

location

where a re-

the

subroutine

(normally

the

effective

and

instruction

the

OVERFLOW

The are

is

the

location

have

been

It

location

about

the

Timing: 2

the

trans-

concleared

executed

exe-

is

this

that

inter-

23

of

The 9 most through instruction,

If

a

branch

the

execution

Affected:

Example:

Location 00777

01000 01001 2 01006 01007

12

significant

8)

have

but

occurs,

(X),

Contents

2 35 041

041 2

of

76

no

may

an

this

(P)

01500

01006 02000 01001

02100

bi ts

of

effect

on

be

affected

interrupt

instruction.

Instruction STA

BRX LDA BRX LDA

the

X regi

the

execution

by

it.

cannot

Timing: 1

01500,2 01006 02000,2 01001

02100/2

occur

2

ster

(bits 0

of

the

following

if

branch

if

no

branch

(X

register)

77777776 77777777 77777777 00000000 00000000

Before After

execution:

BRR

o 1 2 3

BRR

is

normally

completion

PLACE

tines

AND

(see

01517

OVERFLOW Indicator

1 (on)

RETURN

51

I

8

910

used to

of a subroutine

BRANCH

Section

3).

BRANCH

return

in

conjunction

(BRM)

except

o

to

43

0522

40001517

the

00522

Location

M

mai n program

with MARK

in

interrupt

P

Register

01517 00523

23

after

subrou-

BRR

copies (subroutine increments stores

the

least register. instruction

OR the OVERFLOW

tents

(The P

between OVERFLOW

of

the

contents

entry

location)

the

contents

significant

register

to

be

executed.)

bit 0 of

indicator

indicator.

effective

of

the

by

one.

14

contains

the

effective

and

There is no

memory

effective

into

an

bits

It also performs a

places

location.

internal

The

instruction

of

the

address

memory

the

change

memory

register

result

location

result

in

location

then

in

of

the

logical

in

the

and

the

and the con-

P

of

B.

SKM

considers

location

and Affected:

Example:

does

to

be

not

(P)

SKM M

and

the

contents

unsigned,

al

ter

them.

O-bits in

24-bit,

of

the

A,

remaining

B,

and

the

nonnumeric

Tim

ing: 2

bit

posi-

effective quantities,

if

no

skip

3

if

skip

Affected:

e:

Exampl

If

the

computer 02100, Location

it

SKG

o 1 2 3

SKG

algebraically

gister

with

tion.

If

of

the

effective

instruction

struction.

the

contents

cutes

the

neither

Affected:

SKM

A nor memory.

Of,

(P)

BRR

02000

Location

02100

02000

executes

takes

the

02000

sti II

contains 0 00

TEST

AND

SKIP

IF A GREATER

73

I

8 9

10

compares

the

contents

the

contents

location,

in

sequence

If

the

of

the

(P) Timing: 2

SKIPIFAEQUALSMEMORYON

of

of A are

and

contents

effective

Contents

o

51

02000

o

00

03220

the

instruction

from

03220.

INSTRUCTIONS

THAN MEMORY

M

the

contents

the

effective

greater

the

computer

executes

of A are

location,

in

sequence.

the

less

than

the

Timing: 2

in

location

of

the A re-

memory

the

skips

the

following

or

computer

SKG

alters

if

3

if

03221.

loca-

contents

equal

exe-

no

skip

BMASK

23

to

(A)

00043007

Since

SKM

compares

mined

by (B), and (A) = (M) in occurs. of

(A)

and

Note

(M).

SKA

o 1 2 3

SKA

compares

with

the

contents the A register have

1-bits

puter

skips

the

and

executes

and

the

effective

1-bits

in

corresponding

cutes

the

instruction

and

memory, based on

(A)

0 0

1 1

that

SKIP

COMPARE

72

I

the

contents

of

and

the

in

any

corresponding

following

location

instruction

logically

(B)

00177000

bit

positions

if

(B) = 0,

IF A AND

ONES

of

the

effective

instruction

instruction.

do

bit

positions,

in

sequence

ANDs

the

following

(M)

0

1 0

0

1

(M)

57643240

8-14

only

these

positions, a skip

a skip

occurs

MEMORY DO

M

the A register,

memory

location

bit

in

sequence

have

corresponding

Result

0

0 1

do

positions,

If

at

least

the

computer

after

table:

(as

deter-

regardless

NOT

23

bit

by

bit,

location.

not

after

the A register

one

SKA.

bits

both

the

pair

If

com-

SKA

of

exe-

in A

70

o 1 2 3

SKM

compares

with

corresponding

location.

the

effective

in the

following

identical,

sequence

The programmer

by

placing

I

designated

If

the

specified

memory

instruction

instruction.

the

computer

after S KM.

selects

1-bits

in

bit

positions

bits

location,

in

sequence

executes

the

corresponding

positions

If

the

bit

M

of

in

the

effective

in A

are

identical

the

computer

after

SKM

specified

the

bit

23

the A register

memory to those skips

and

executes

bits

are

not

instruction

be

compared

positions

in

of

If

the

result

produces a 1-bit

does

not

occur.

Affected:

Different

wide

the

programmer. Some

(P)

configurations

variety

of

Memory

Configuration

40000000 77777777

00000001

of

conditional

examples

in

any

the

memory word

skip

instructions

are:

Effect

Skip

if

Skip

if

Skip

if A is

bit

position,

Timing: 2

A is Positive

A = 0

Even

if

3

if

result for use by

a skip

no

skip

in a

13

Contents

A Register

40000000

77777777 00000001

SKN

o 1 2 3

If

the

contents negative, instruction

lowing cation next

instruction.

are

instruction

of

SKIP

53

I

of

i.e.,

if

in

sequence

positive

Effect

Skip

if

Skip

if

Skip

if

IF

MEMORY NEGATIVE

8 9 10

the

effective

(MO)

= 1,

the

after

SKN

If

the

contents

or

zero,

the

in

sequence

after

Memory is Memory = 0 Memory is Even

memory

computer

and

of

computer

SKN.

M

location

skips

executes

the

effective

executes

Positive

the

are

fol-

lo-

23

11,

which

direct

addressing,

are

used in

shift

instructions addressed, determining

When

the sitions struction computer the Once each C in

places

Shift

ber

18

initial

the

position

the

to

timing

of

places

determine

treats

following

be

control

the

address

RSH

with

bits

the

method

computer through

these

count

is

shift

begins,

shifted

shifted.

is

calculated

shifted.

the

method

the

full 14

computation;

and

LSH

10

and

of

shifti

interprets

23

of

the

amount

six

bits

equal

to

the

count

unti I

it

instructions

as follows,

of

shifting.

bits

of

should

11

of

the

ng.

a shift

effective

of

as

an

zero,

no

is

reaches

indicates

During

the

address

thus,

only

be

indirectly

effective

instruction,

address

the

shift.

unsigned

shifting

reduced

zero.

the

where

N is

in-

field

the

address

bit

of

the

in-

The

count.

occurs.

by

one

for

The

count

number of

the

num-

po-

If

Affected:

The and B registers and of

these bination, length

This

When from

tion 0 of bits from

sition

Two AB

register

tents

one

the

other

Shift the

direction

11

of

shifting

Octal

Position

3

Indexing bits

index

(P) Timing: 2

shift

instructions

left

shifting, two registers. The A and B

form a

contents

double-length

the

contents

bit

position

the B register. bit

position 0 of

23

of

the A register.

shift

instructions

to

of

the

AB

end

of

the

register.

instructions

the

effective

as

follows:

(Bits

00

10 2

01

of a direct

18-23

of

the

number

SHIFT

operate

and

offer a complete

cyc

ling,

double-length

can

be

register

of

the

23

of

allow

be

"cycled"

register

one

regi

use

the

of

shift

(66

address

10, 11)

address

the

address

of

shifts

INSTRUCTIONS

on

the

contents faci I ity

and

normal

izing

registers,

register

shifted,

the A register

cycle,

ster

= right;

Octal Value

0

1

cycled,

is named "AB".

AB

register

When

the

AB

the B register

the

48-bit

right

or

left.

the

bits

copy

into

instruction

67=

determine

Function

AB AB Normalize

shift

instruction

field.

It

without

is

affecting

shift shift

register

contents

that

the

code

left); bits 10

the

Shift Cycle

thus

if

3

if

of

for

the

in

whose

double-

or

normalized.

right, into

shift

into

When

shift

other

to

determine

method

(left

affects

possible

bits

no

skip

the

A

right

contents

com-

bits

bit

posi-

shifts

left,

bit

of

the

con-

from

end

of

and

of

only)

only

to

10

and

po-

Timing in

2+N

RSH

o 1 2 3

RSH

shifts

ber

of

places fective not tions

of shifting

This point of

Affected:

Example:

RCY

lolxlo

address. The

shift; its

of

the

B shifts. Bits

past

instruction

numbers by use

exponents

I

o 1 2 3

RCY

shifts

ber

of

places

Cycles

RIGHT SHIFT

66

I

the

contents

specified

value

shifted

position

may be used

is in

(AB)

RS

H 18 (0

(A) (B)

RIGHT eye

66

I

the

contents

specified

Number

N

=0,

AB

89101112

of

the

AB

in bits 18 through 23

bit

in

the

sign

is

copied

number. The

shifted

B

of

the X register

66

Before Execution

45261237 27651260

1011

89

into

out

of

A

are

23

lost.

to

perform

indexing,

00022)

LE

AB

10

I

10

1112

of

the

AB

in bits 18 through 23 of

of

0,

1,

o

I

register

position

the

bit

in

shift

23

scaling

where

as a

After

Execution

77777745 26123727

0

,

register

Places

2,

3,

right

vacated

the

sign

into

the

positive

Timing:

17118

right

Shifted

...

48

C

I

the

num-

of

the

ef-

of A does

bit

posi-

position

BO'

Bits

of

floating-

difference

quantity.

2+N

C

I

the

num-

the

23

1

23

14

effective

like

shifts shift

into

puter

treats

cular

and

Affected:

address. The

any

other

bit

BO;

bits from B

the

double-length

cycles

(AB)

it

onto

bit

in

B. go

23

itself

in

the

Bits

into

register

so

sign shifting AO.

that

position

out

of

Thus,

the

as

if

it

were

no

bits

are

Timing: 2 + N

of A

23

com-

cir-

lost.

B

Example: LCY 9

(A) (B)

(067

20011)

Before Execution

76543210 01234567

After

Execution

43210012 34567765

Example: RCY 15 (0 66 20017)

Before Execution

(A) (B)

LSH

IoIxIol

o 1 2 3

LSH

shifts

ber

of

places fective of inal the into Zeros the B register.

Affected:

Example:

address. Bits

A,

but

when a

sign,

OVERFLOW

A23. Bits

fi

II

the

LEFT

67

I

the

contents

specified

shifts

vacated

(AB),

LSH

76543210 01234567

SHIFT

8 9

shift

bit,

into

the

indicator.

shifting

Of

18 (0

67

AB

101112

of

the

in bits 18 through 23

left

different

sign

Bits

past

position

bi t

positions

00022)

After

Execution

34567765

43210012

o

I

AB

register

through

in

value

position,

shifting

on

left

the

of

the

sign

from

the

computer

out

of

0 in A

are

the

right

Timing: 2 + N

C

I

num-

the

ef-

position

orig-

sets

BO

go

lost.

end

of

23

NOD

10Ho

1

o 1 2 3

NOD

shifts

(1) a

bit

appears

to

the

bit

in

occur.

shifts ber

of

places

the X register

attempt

contents this shift positions

The number

of of sufficiently

Affected:

Example:

to

normalize,

of

case,

the

count C reduces

of

the

instruction,

left

shifts.

(A

NOD

NORMALIZE

67

I

the

AB.

C,

large

B)

101

8 9

contents

in

the

sign

The

computer

shifted

each

AB

register

computer

in

address

is

The programmer must ensure

to

, (X)

24 (0

AND

DECREMENT

0

1

10

11

of

position 1 of A that

position

by

decrementing

time

shifting

continues

to

zero.

an

permit a complete

67

10030)

00

1

12

the

AB

of

A,

keeps

a shi ft

upper

occurs.

exceeds

were

initio

Zeros

bit

positions 18 through

limit for

Timing: 2 + R

)18

register

or

count

the

48

Ily

shifting

fill

norma

the ber

C

I

left

unti I

is not (2) unti I C of

If,

zero.

the

resultant of

equa

the

num-

contents

in

the

places,

until

the

vacated

number

that

C is

Ii

zation.

where

shifts

In

R is

num-

23

I

of

the

23

(A)

(B)

Ley

11+/01

o 1 2 3

LCY shifts

ber

of fective shift of

BO The were

Affected:

the

places

address. Bits in

like

any

shift

into

computer

circular

(AB)

Before Execution

46712370 64132711

LEFT

67

I

contents

specified

other

A23; bits treats and

cycles

CYC

LE

I

1010

89101112

of

the

in bits

the

bits in

shifting

the

double-length

it

After

Execution

70641327

11000000

AB

JoI

the

onto

o

I

AB

register

18

through 23

sign positions

number. Bits

out

of

itself.

C

left

the

num-

of

the

of

A and B

shifting

AO

shift

into

register

as

if

It

loses no bits.

Timing: 2 + N

ef-

out

B23.

it

23

(A) (B)

(X)

CONTROL

HLT

lolxlol

o 1 2 3 8

When

the computation sole.

Before register ter

to

be

the

operator

then

back

HALT

00

I

computer

and

halting,

and

brings

displayed.

must

to RUN.

Before Execution

00004632 76124035 00000000

1 I I

910

executes

lights

the

resume

set

the

After

Execution

23153705 20164000 77777765

INSTRUCTIONS

M

this

instruction,

HALT

indicator

computer

instruction

RUN-IDLE-STEP switch to

increments

automatic

it

in

the

into

the C regis-

computation,

halts

con-

the

23

P

IDLE,

15

The

computer

cording Indirect

instruction,

When putation

ing it resumes the

and The

is

to

addressing

the

ceases

executed.

continues

with

RUN-IDLE-STEP

the

interrupt

HALT

set

to

IDLE,

then

executes

the P register.

and

nor

does

the

computer

until

the

light

at

the

If

an

input/output

completed.

occurrence

system

turns

or

when

executes

switch

off

indexing

instruction

end

of

is

enabled.

when an

interrupt

the

do

not

access

HLT,

all

the

present

operation

Computation

of a program

still

in

the

RUN-IDLE-S

occurs.

apply

to

memory.

internal

instruction

is

in

progress,

automatically

interrupt,

RUN

position

TEP

ac-

this

com-

be-

if

switch

This

instruction switches BREAKPOINT the

lowing

is

set

in

Mnemonic

BPT

(S

KS

singly

instruction.

(on),

sequence.

1

020400)

the

BREAKPOINT

tests

the

status

or

in

any

switch

is

reset

in

sequence

If

the

tested

computer

Name

BREAKPOINT 1

executes

of

Instruction

TESTS

of

the

combination.

(off),

the

and

executes

BREAKPOINT

the

Test

BREAKPOINT

If

a

tested

computer

the

switch

Octal Configuration

04020400

skips

fol-

Affected:

NOP

o 1 2 3

Executing X

register,

do

not

apply

access Affected:

EXU

sequence

If

branch address sequence

If

skip

If

cade Affected:

o 1 2 3

EXU

causes

tion

to

the

contents location tion,

the

tive

location

the

contents

the

contents

instruction, program next

instruction

the

contents

EXU,

the

ing

the

indefinitely.

memory.

initial

Halt

flip-flop

NO

20

I

NOP

does

or

memory.

to

this

None

EXECUTE

23

I

the

contents

be

executed

of

the

is

not a branch,

computer

and

following

of

instruction,

of

the

branch

following

of

control

above

returns plus

of

the

process

EXU

Determined

cuted

Timing: 1

OPERATION

M

not

affect

Indirect

instruction,

8

910

of

as

an

program

executes

then

executes

the

EXU.

the

effective

program

and

the

EXU.

the

effective

then,

depending

to

one,

effective

repeats,

location

(See

Figure 9 in

by

instruction instruction

the A register, B register,

addressing

nor

does

the

M

the

effective

instruction

counter.

skip,

or

another

the

contents

the

memory

control

not

to

the

memory

on

the

memory

wi th

plus

one.

exe-

Timing: 1 +

memory

without

If

the

EXU

of

location

goes

to

location

the

skip

instruction,

the

EXU.

location

the

norma I return

This

process

Appendix

and

indexing

instruction

Timing:

loca-

altering

effective

instruc-

the

effec-

are

the

effective

are

deci

or

are

another

can

D.)

executed

sion,

the

23

in

a

in

a

be-

cas-

BPT

2

(S

KS

020200)

BPT

3

(SKS

020100)

BPT4

(S

KS

020040)

If

more

than

the

test,

the

any

of

the

1

skip

the

are

set. causes switches 1 and 3 are case).

Affected:

the

OVT

(SKS

020001)

This

instruction cator. next (clears skips following

Affected:

ROV

(EOM

ROV (clears

Affected:

If

the

instruction

to

zero).

the

020001)

unconditionally

to

zero).

BREAKPOINT 2

BREAKPOINT 3

BREAKPOINT 4 Test

one

BREAKPOINT

computer

specified

instruction

Thus,

computer

(P)

OVERFLOW

OVERFLOVI INDICATOR

RESET

tests

indicator

in

instruction

(P),

Of

RESET

Of

ski ps

switches

the

instruction

to

skip

both

the

status

is

sequence,

If

the

indicator

OVERFLOW

resets

the

are

if

all

the

set

(2

INSTRUCTIONS

of

on,

the

and

in

sequence

the

Test

switch

next i nstructi

of

the

computer

turns

is

OVERFLOW

040

is

specified

reset,

BPT

Timing: 1

but

the

specified

1,3

instruction

ignored

(040

TEST

OVERFLOW

executes

the

indicator

off,

the

and

executes

Timing: 1

20200

20100

20040

on

if

does

switch-

20500)

unless

in

if

no

skip

2

if

skip

AND

o

40

20001

indi-

computer

the

if

no

skip

2ifskip

o

02

20001

indicator

Timing: 1

in

not

this

the off

16

FLOATING-POINT

XDS Programmed single

or

double

eration

11

faster mal

The mostsignificantword whi tion

permits

decimal

execution

digits

standard

Ie

the

M;

see

less

Operator

precision

resul ts

digits.

times,

of

accuracy.

XDS Programmed

significant

Section

DOUBLE-PRECISION,

FLOATING-POINT

subroutines

modes.

with

an

Single

precision

with

is

inA,

word is in

1,

Floating-Point

OPERATIONS

perform

D~uble

accuracy

approximately

Operators

or

stored

OPERATIONS

precision

of

approxi

operation

assume

in

location

B,

or

memory

Format.

seven

in

either

permits

that

op-

matel

deci-

the

M + 1,

loca-

SINGLE

FLOATING-POINT

Programmed

y

floating-point bits

(23 (eight to

six

as

10±77.

The Programmed precision,

Mnemonic

Operators

bits

plus

bits

plus

decimal

floating-point

Name

operations

sign)

sign).

digits

Operator

Function

that

and

Numbers

plus

sign

subrouti operations

use a

PRECISION,

OPERATIONS

perform si ng I e

fractional

an

exponent

have

and

the

nes

that

are:

number

of

nine

the

fraction

exponent

perform

Approxi Execution Time

prec i si

bits

as

si

on,

of

24

equal

high

ng I e

mate

Programmed

floating-point

(38

bits sign). plussign

The Programmed precision,

Mnemonic

FLA

FLS

FLM

FLD

Operators

operations

plus

sign)

Numbershave

and

the

floating-point

Name

Floating

Add

Floating Floating

Subtract

Floating Floating Multiply

Floating Divide

that

use a fractional

and

an

exponent

the

fraction

multiplier

Operator

Function

Floating

+ (M + 1, M)

- (M +

x (M + 1, M)

Floating

(M +

perform

of

equal

as

high

subroutines

operations

(A,

B)

----.

(A,

B)

1!

M)

----.

(A,

B)

----.

(A,

B)

1,

M)

----.

double-precision,

nine

as

are:

number

to

lo±77.

that

bits

(eight

11

decimal

perform

Approxi

Execution

Time

of

double-

896 !-,sec

A,

B

1016 !-,sec

A,

B

1696 !-,sec

A, B

1872 !-,sec

A,

B

39

plus

digits

mate

bits

FSA

FSS

FSM

FSD

See grammed

Floating Add, Single-

Precision

Floating Subtract, SinglePrecision

Floating Multiply, SinglePrecision

Floating Divide, Single Precision

Appendix E for a detailed

Operator

Floating

Exponent

Floating

---.A

Exponent

loati

ng (A) - (M +

F

---.A Exponent

Floating

--.A Exponent

--.A

feature.

(A) + (M +

in

B,

M

in

B,

M

(A) x (M +

in

B,

M

(A)

+(M

+

in

B,

M

discussion

1)

432

472 !-,sec

464 !-,sec

792 !-,sec

of

the

!-,sec

Pro-

17

XDS

900

Series

system

output

input/output immediate the rupt

provisions such can

by

end-of-word

in

portion

All

stallation

(see

through

priority

cept

which

077

normally

devices,

End-of-Word 031 all according

The

rupt 896,

that operations,

basis

of

system is

as

the W buffer,

cause

the

computer

the

computer.

of

interrupt

Table

077

interrupt

for

the

have

are

XDS

reserved and

and

033)

other

optional

levels,

for

general-purpose

Computers

provides

aids

and

compute

recognition

predetermined

essentially a combination

and

programming

the

interruption

by

transmitting

signals

the

or

Appendix D contains a diagram

XDS

910

PRIORITY

devices

are

assigned

1)

identified

and

0200

levels

optional

the

highest

optional

for up to

are

always

and

End-of-

are a standard

interrupt

to

levels0200-01

which

levels

the

requirementsof

may

contain a priority

added

program

in programming

operations,

of

special

priority.

techniques.

real-time

of

programs

clock

pulses) to

Interrupt

ASSIGNMENT

used

with a specific

unique,

by

octal

through

having a smaller

power

hardware

fail-safe

priority).

40

added

Transmission

feature

are

777

be

added

interrupts.

control

simultaneous

and

also

external

clock,

interrupt

System.

numbered

01777,

interrupt

special-purpose

in

pairs.

optional,

individual

are

in

conditions

The

priority

of

Various

power

being

pulses

interrupt

computer

priority

numbers from

wi

th

number

interrupt

Interrupt

levels,

The W

interrupts

of

the

910

and

installations.

special

any

systems

number

3.

INTERRUPT

interrupt

of

input!

allows

on

inter-

hardware

devices

fail-safe

executed

(such as

levels

of

a

in-

levels

030

the h igher-

(ex-

levels,

levels

030-

are

interrupt

buffer (levels

Computer;

are

added

inter-

up

to

SYSTEM

INTERRUPT

Each

interrupt operating In

the

inactive

its

from

ceived

is

unconditionally waiting active terrupt struction knowledged memory terrupt affecting struction Active

ff

terrupt allows their

If

struction AND routine

cation the the struction)

is

the

(BRU)

current next

state,

also

interrupt

importance

interrupt

MARK

instruction,

of

level

states -INACTIVE,

state,

assigned

and

the

level

state

begins.

the

ff.

At

the

currently

by

the

location

level

(e.

the

program

in

the

interrupt

ff is

set;

cleared

levels

are

SUBROUTINE INTERRUPT

level

in

the

interrupt

PLACE

which

ends

the

subroutine.

contents

instruction

in

the

LEVEL

(as shown in

the

level

interrupt

is

armed,

set

to

produce a steady

If

no

signal

from

end

of

being

executed,

computer,

with

the

g.,

location

counter.

address

the

active

at

this

time,

prevented

levels

to

and/or

first

need

is a

address is

(BRM) in a BRANCH indirectly

of

the

in

sequence

location

OPERATION

Figure

WAITING,

has

not

device.

higher-priority

the

same

state

from

be

"subroutine"

instruction

The

program

When

the

Waiting

the

Waiting

execution

the

and

the

octal

036) is Normally,

is

executed,

begins.

and

all

becoming arranged for

servicing.

normally

UNCONDITIONALLY

addressed,

BRM

instruction counter

after

of

the

3) has

three

and

ACTIVE.

received

the

pu Ise is

flip-flop(ff)

signal;

level

ff sets

cycle

of

interrupt

instruction

number as

executed

lower-priority

in

interrupt,

to a

the

servicing

when

The

active.

the

)

a BRANCH

servicing

to

the

(address

interrupt

without

the

Interrupt

order

first places

subroutine.

distinct

a pulse

the

is in

the

in-

the

in-

is

ac-

in

the

in-

the

level

(This

of

the

sub-

lo-

of

in-

re-

the

in-

Table

1.

Interrupt

Address

030-077

036

037

030

031 W

032

033

Description

XDS

HARDWARE

POWER

and

POWER

and Y

Armed

Armed Y

(Optional) W

(Standard)

ON

always

OFF

always

BUFFER

if

BUFFER

if

BUFFER

INTERRUPT

(Optional)

enabled

(Optional)

enabled

END-OF-WORD

enabled

END-OF-WORD

enabled

END-OF-TRANSMISSION

Armed

END-OF-TRANSMISSION

Armed

by

EIR

by

EIR

if

enabled

if

enabled

Always

18

Levels

LEVELS

armed

(Optional)

(Standard)

by

EIR

by

EIR

(Arranged

Address

034-035 040-077

0200-01777

0200-0217 0220-0237

01760-01777

in

Order

of

Priority)

Description

Other

optional,

interrupts SPECIAL SYSTEM INTERRUPTS

(Optional) armed, AIR

(provided Control computer)

Group Group 2 (01

Group56

or

may

Unit

1 (00

(67in

Enabled

be

that

is

present

in

control

in

control

Special-purpose

by EIR.

armed

the

Always

selectively

Arm

Interrupts

as a part

word

address

word

address

word

address

of

by

the

field) field)

field)

INACTIVE

Proceed

WAITING

~

if

ARMED

~

Some

of

the

optional

of

the

interrupt

or

"single-instruction"

instruction

ory

location

the

interrupt turn of

the

is

executed.

to

the

contents

in a

is a

is

interrupted

interrupt

levels

0200-01777

interrupts,

single-instruction

branch

cleared

of

the

and

but

program,

program

levels

may

as

interrupt

the

branch

there

is no automati<;:

and

counter,

030-077

be

"subroutine"

required.

should

no

record

wh

en

and

level

the

any

If

the

mem-

occur,

re-

is

kept

branch

Proceed

Figure

The

BRU

gram

control

interrupted

sets

both

The

interrupt

An

interrupt-servicing whenever a higher-priority active. as

each

cleared,

interrupted TURN BRANC H an

interrupt-servicing

not

cleared proper within

clears

If

level,

cuted

(provided

or

instruction the

nected

line

real-time

level

MIN each main necessary, elapsed

location.

an

the

interrupt the

and

more

interrupt

to

at

specified

076

02050), time program

3.

instruction,

to

the

program,

the

level

This process may

subroutine

program

by

the

(BRR)

and

program

interrupt-servicing

interrupt

SINGLE-INSTRUCTION

level instruction the

interrupt

that

the

cyc

I es),

in

sequence

occurred.

the

computer

clock.

(and

location

the

clock

can

to

determine

since

the

if

Proceed

ACTIVE

Interrupt

indirectly

and

Waiting H and

is now

subroutine

is

processed

control

higher-priority

instruction

subroutine,

control

Also, a

level.

is a single-instruction in

level

instruction

and

the

after For so

intervals,

If

the

clock

computer

pulse

examine

how

clock

was

~

Proper

Priority

~

if

ENABLED

~

Arm-Enable

addressed,

clears

the

back

in

is

interrupt

be

repeated

and

is

returned

interrupt.

is used

the

is

not

BRU

with

subroutine

INTERRUPT

the

interrupt

is

automatically

requires a timing

computer

the

instruction

example,

that

it

pulses

the

program

is

connected

076

contains

adds 1 to

causes

location

started.

many

an

time

Response

in

sequence

interrupt

level

the

inactive

also

level indefinitely

its

interrupt

to

the

at

interrupt

returned

indirect

prematurely

address

executes

if a

an

can

the

location

interrupt.

02050,

increments

returns

interrupted

subroutine

the

clock

to instruction

pro-

in

level

Active

state.

becomes

and,

level

If

a RE-

end

level to

the

addressing

interrupt

is

exe-

cleared

of

two

the

which

is

interrupt

maintain

interrupt

02050

The

whenever

have

the (re-

H).

of

con-

NON·INTERRUPTABLE

If

an

INCREMENT INDEX

tion

is

being

executed computer struction if

an executed, rupt

ecuted

can

not

to

which

ENERGIZED OUTPUT M(EOM)

the

computer

until

the

instruction

.•

INTERRUPT

Two

control concerning shown in to

the

rupt

pulse pulse

does interrupt the

interrupt

terrupt

higher-priority state. state

only

is

a

"disabled,

not

pass

Some

computer

tions

always

by

the

els

are always pulses

considered or

disabled,

the

XDS such

as

interrupts

pending All

other

077

are

means

of

gram

being

terrupts

interrupt

These INTERRUPT ENABLED

console

features

the

interrupt

Figures 3 and

waiting

level

Also,

through

computer.

subject cause

its

power

(0200-01777)

XDS

is

sent

not

level,

level. remains

an

if

it

II

the

be

a program

interrupt

armed

except

optional

fail-safe,

(levels

on

the

XDS

optional

armed,

the

computer

executed.

OPTIONAL

(see

Section

state

pass

interrupt

is

steady

theANDgate

appl

immediately

only

requirements

disarmed,

levels

and

acknowledge

the

BRX

can

following

ARM/ENABLE

are

avai

system - Arm

11,

only

if

to

it.

If

through

the

pulse

Once

in

the

level

interrupt

"enabled.

signal

ications

For

this

to

priority

interrupt

line.

This

and

enabled,

by

rewiring

hardware

and

0200-01777)

hardware

control

The

is

discussed

HARDWARE

are

both

indicator

5)

is

INSTRUCTIONS

AND

BRANCH

the

branch

an

interrupt

branches

not

is

instruction

acknowledge

the

RESPONSE

labl

e to

an

interrupt

it

is

"armed"

the

level

is

the

AN D gate

is

not

II

remembered

in

the

waiting

level

II

require

recognized

reason,

interrupts

any

of a particular

enabled,

control

turned

state

is

already

proceeds

If

the

interrupt

from

the

in

front

of

that

certain

consideration,

if

an

type

of

interrupt

and

cannot

the

computer.

(levels

of

the

may

be

interrupt

and

consol e

of

special

separately.

INTERRUPTS

armed

and

on

the

on,

(BRX)

should

executed.

and

"disarmed",

Waiting

interrupt

of

and/or

computer

until

EOM

is

the

programmer

Enable.

level

when

in

front

state,

as

long

in

the

to

the

Interrupt

certain

and

acted

interrupt

be

030-077)

special

this

type,

installation.

levels

disabled

enabled

and

are

occur,

the

proceeds

and

is

disarmed

the

system

instruc-

the

Also,

is

being

inter-

also

ex-

As

the

inter-

the

of

II

by

the

in-

as

any active active

level

ff

does

H.

condi-

upon

lev-

will

device

always

Some

systems

de-

(030-

by

pro-

if

the controi both

the

in-

the

is

of

in-

19

disarmed terrupt not button interrupt

INTERRUPT ENABLED after, with

being

Whenever position, ditionally

receiving proceed proceed

lows.

turns

If

any

ENABLE able the rupt terrupt

interrupt cleared.

leased, els

and

disabled

levels

considered

affected

the

to

ff is in

INTERRUPT ENABLED

levels

remain

by

this

on

the

computer

levels

and

the

indicator

INTERRUPT ENABLE

executed.

INTERRUPT ENABLE SWITCH

this

switch

the

INTERRUPT ENABLED

turned

an to to

When

the

interrupts

switch

levels

If

the

on.

interrupt

the

waiting

the

active

the

switch

COMPUTER

occur

is in

the

reset

030-077

0200-01777

in the

the

Enable

indicator

armed

and

INTERRUPT

INSTRUCTIONS

Two

mach

ine

instructions Enable of

EIR

EOM

EIR INTERRUPT ENABLED

are

ity Interrupt interrupt

the

INTERRUPT ENABLE

Affected:

OIR

EOM

DIR

INTERRUPT ENABLE

ff,

and

two

the

INTERRUPT ENABLED

E!"~ABLE

020002

unconditionally

in

the

waiting

is

acknowledged,

levels levels

Enable

unconditionally

ff is

INTERRUPT ENABLED

020004

state,

030-077 0200-01777

set,

DISABLE

if

the

indicator

always

indicator.)

control

the

Interrupt

indicator

may

be

is

manually

Any pulse

state.

state

is

position.

during

the

ENABLE

state

are

disarmed

active

ff remains enabled.

armed Whenever

console

ff

is

controlled

switch

held

controllable

while

Any

in

as

soon as

released,

the

time position,

when

the

indicator

and

are

disabled.

state

is

set

when

on

and

ENABLE/DISABLE

AND

are

used

instructions

INTERRUPTS

sets

the

indicator.

and

regardless

switch.

INTERRUPTS

resets switch

indicator.

Enable

the

one

proceeds

remain

the

is in

are

If

with

armed

of

the

Enable

the

is

turned

and

enabled

the

is

pressed,

are

cleared,

turned

the

off.

by

the

and/or

in

the

indicator

interrupt

indicator

the

waiting

their

it

automatically

the

switch

is

turned

disabled,

However,

are

processed

the

switch

the

interrupt

the

priority

INTERRUPT

and

is

TESTS

to

set

and

used to

ff

to

enabled)

COMPUTER

test

and

turns

any

interrupt

the

higher

the

active

and

enabled

position

ff. Also,

002

as

002

off.

(In-

are

START

all

and

the

There-

operator

program

ENABLE

is

uncon-

levels

is

on

state

al-

re-

the

En-

released,

off,

inter-

and

in-

any

unti I

is

re-

lev-

reset

the

status

20002

on

the

levels

prior-

state.

(and

long

as

of

the

Timing: 1

20004

if

the

position,

the

INTERRUPT ENABLED

rupt

levels

030-077 terrupt interrupt

unti I the by

the tion

cator

Thus, never has rupt rupt in

Affected:

lET

S

If

puter cutes

Affected:

lOT

S

If

instruction puter the

Affected:

Note:

levels

0200-01777

pulses

to

indicator

execution

ENABLE

resets

and

the on

been

levels levels

the

KS

020004

the

INTERRUPT ENABLED

skips

the

KS

020002

the

indicator

skips

following

of

position

the

Enable

does

not

switch

EIR.

When

executed,

030-077 0200-01777

active

state

INTERRUPT ENABLED Timing:

INTERRUPT ENABLED (Skip

the

(P) Timing: 1

INTERRUPT DISABLED (Skip

in

sequence.

the

(P)

EIR

and

DIR mode, nal Test Output

and

mode

Instructions).

END·OF·WORD/END·OF·

INTERRUPT

A program direct,

ial

input/output trol In

the interrupts buffer

as

the

input).

can

use

program-controlled,

mode,

buffer

occur

to

the

buffer

This is

see

Section

control

peripheral is

filled

the

are

disarmed

levels

is

again

an

EIR.

when

H,

disarm

may

be

the

indicator

are

disarmed

are

processed

if

Interrupt

instruction

instruction.

if

Interrupt

is

on,

the

If

instruction

are

EOM's

lET

and

(see

the

Wand

instructions

4)

mode,

as

each

word is

device

from

end-of-word

indicator

are

030-077

turned

However,

DIR

but

or

disable

used to

swi

tch

disabled,

indicator

computer

the

IDT

Section

is

turned

and

disabled,

disabled.

are

not

on

by

if

the

is

executed,

does

not

turn

the

override a DIR,

is

released

is

turned

and

disabled,

but

until

cleared.

System

is

in

sequence

TEST

System

executes indicator in

sequence

Tim

ing:

in

the

Internal

are

SKS's in

4,

Primary

TRANSMISSION

OPERATIONS

Y buffers

input/output

(EOM's

control

the

in

this

type

program

transmitted

(on

output),

peripheral

interrupt.

off,

and

Any

subsequent

IIrememberedll

the

switch

the

off

the

interrupt

after a DIR

off,

interinter-

any

interrupts

Enabled)

0

40

on,

the

and

exe-

if

2

if

Disabled)

0

40

the

is

off,

the

and

executes

1 if no

" • r

L

IT

SKiP

Control

the

Inter-

Input/

as

single-word,

buffers.

the

buffer

of

operation.

can

specify

from

or

as soon

device

The program

inter-

in-

or

is in

instruc-

indi-

levels.

but

20004

com-

no

skip

20002

skip

~ I .~_

Spec-

con-

that

the

(on

20

can

also

specify

input)

when end-of-record paper

tape operations, device the

output

.

End-of-word control

operating

(optional interrupt fied (or into the buffer laced ated See

minal

being

buffer.

operation

input/output

in the

feature).

also

number

when

the

memory from a

buffer

automatically

mode,

while

Section

input/output

SPECIAL

Interrupt

interrupts quirements

any instruction Control these except pulse the rupts

dicator

(see

levels

that

desired

Unit is

interrupts

by

entering

level

are

enabled

is

Interrupt

to

on,

that

an

end-of-transmission

the

buffer

detects a terminal

from a

reader,

this

used in

The

and

occurs

of

buffer

detects

the

4,

magnetic

etc.

During

interrupt

buffer

• end-of-transm

block

words from memory to a

an

end-of-word

buffer

Interlaced

occurs

the

transmission

is

then

transmission

In

this

mode,

when

the

has

read a specified

peripheral

end-of-record

con-trois

is in

this

Block Transm ission, for

conditions

SYSTEMS

0200-0

are

of a particular

combination

interrupts.

rewiring

the

and

Arm-Enable

added

not

present

are

always

interrupt

waiting

only

are

1777

in

If

the

computer)

state.

if

disabled

are

groups

computer

of

the

as a part

armed

the

Response).

occurs

signal

tape

unit,

card

both

input

and

when

the

peripheral

disconnects

ready

for

another

ission

interrupts

when

the

program is

or

lIinteriaced

an

end-of-transmission

buffer

has

sent a speci-

peripheral

number

device,

input/output

interrupts

mode

during

as

well

signal).

in

are

of

transmission.

interlace

as Since the

not

control.

INTERRUPTS

optiona

subroutine

optional

level

INTERRUPT ENABLED

if

I,

genera

of

16

according

system,

and/or

Arm

of

the

computer,

(cannot

unconditionally

However,

the

and

any

indicator

be

these

I-purpose

and

Interrupt

disarmed,

interrupt

(on

such

reader,

output

from

input/

can

also

li

mode

device

of

words

when

the

inter-

gener-

ter-

to

the

may

single-

sets

inter-

in-

is

off

as

re-

be

control

instruction

The group operation the and the

Affected:

The has

word is

(POT

instruction

of

interrupt

occurs.

INTERRUPT ENABLED

the

Control

Enabl e ff.

Arm

control

the

word

following

o

Address

I

o

The Address interrupts

of

octal

C

fi

eld

levels

be

armed Word interrupt (e.

g., the

highest-numbered

group.

The C

Bit Positions

6 7

o

567

field

is

being

00

identifi

(bits 6 and

selected

and/or

represents

with

in

0200,

0220,

field

control

o

transmitted

instructions

sequence

levels;

Unit

Interrupt

CONTROL

which

format:

2

AIR, POT must

These

instructions

is

not

Control

the

3

8

(bits

0-5)

addressed

es

interrupt

7)

spec

by

bits

8-23

disarmed.

the

lowest-numbered

the

group

etc.)e

(lowest-priority)

functions

Octal

Value

o

to

the

Control

are

discussed

otherwise,

indicator

affected

instruction

Interrupt

I I I

identifies

ifies

of

Bit

identifi

Bit

are:

an

and

by

Unit

WORD

4

Select

(e.g.,

levels

whether

the

Control

position 8 of

ed

by

position

Function

Not

used

Unit

by a POT

in

Section

be

used for

unpredictable

have

no

effect

the

Enabl,e ff,

the

indicator

Timing: 1

POT

addresses

6

5

Bits

which an 0200-0217).

(highest

level

Address

the

interrupt

Word

the

Address

23

represents

within

group

priority)

4).

each

on

or

7

23

of

field

The

are

to

Control

fi

eld

the

ARM

INTERRUPTS

If

the

optional

a

part

of

be

armed interrupt by a

specific

INTERRUPTS (AIR)

control

INTERRUPT ENABLED the

disarmed computer

AIR

EOM

AIR

Interrupt

word.

indicator

020020

is

an

Arm

the

computer,

(and/or

levels

combination

is

and

disabled

control

ARM

internal

Control

Interrupt

interruptlevels0200-01777must

disarmed)

0200-0217,

and

PARALLEL

These

interrupt

indicator

off.

Also,

when

console

INTERRUPTS

control

Unit to

Control

in

0220-0237,

of

the

these

the

is

pressed.

EOM

receive a control

(OPTIONAL)

Unit

groups

of

sixteen

etc.),

two

instructions

OUTPUT (POT)

levels

are

enabled

is

on,

and

interrupts

START

button

that

prepares

is

present

(i.

and

disabled are

initially

on

o

02

the

word.

as

e.,

only

ARM

and

if

the if

the

20020

Arm

The

o

a

o

2

4

6

Arm

only

I

evels

that

by

a 1 in 8-23. represented bit

affected.

Disarm rupt lected 8-23. represented posi

affected. Arm

sel arm

by

(Interrupt

position

only

levels

by a

(Interrupt

tions

all

ected

those

a

zero.

interrupt

by a 1

those

are

bit

positions

by a zero 8-23

)

those

that

zero

by

8-23

)

levels

interrupt

selected

level

are

not

inter-

are

se-

in

bits

levels

ali n bit

are

not

levels

and

dis-

selected

s

in

21

Example:

The

following

levels

0230-0237,

partial

but

program

does

not

enables

change

the

entire

current

interrupt

state

system,

(armed or

arms

interrupt

disarmed)

of

levels

0210-0227,

0200-0207.

disarms

Location

CW1

CW2

Instruction

EIR

AIR POT

AIR

POT

00200377

01777400

Address

CW1

CW2

Comments

Enable

entire

on) • Prepare

the

Transmit Control

An

AIR

Unit.

must

Transmit Control

Other

This are

This 0237,

Unit.

instructions

control

already

control

regardless

Arm

the

control

precede

the

control

word arms

armed

word arms

interrupt

Interrupt

word in

in

or

of

their

system (turns INTERRUPT ENABLED

each

Control

POT.

Unit to

location

receive a control

CW1

to

the

CW2 to

the

Arm

program.

level

disarmed

levels

they

0220-0227

state.

remain

and

If

any

so.

disarms

of

levels

Interrupt

0200-0207

levels

indicator

word.

0230-

22

4.

INPUT/OUTPUT

SYSTEM

The

XDS

910 has a

complement

to versatile word, puter output the vices, trol to

This system is

output:

1. Buffered

2.

3.

4.

instructions.

character,

at

the

system assumes

individual

yet

it

the

programmer.

direct

program

Input/output shared tion

using

Direct formation to der

program

Single-bit status, spec ial

INTRODUCTION

comprehensive

its high

or

single-bit

speed

of

internal

characteristics

leaves a high

capable

input/output

control.

of

blocks

with

memory

"interlaced"

parallel

sense

devices.

input/output

and

from

control.

input/output,

switches,

internal

This system

control

degree

of

the

following

of

data

of

and

multiplexed

buffers.

external

and pulsing

input/output

processing

can

form to and from computation. of

conditions

of a wide

of

words,

characters

of

up to

static

such as

speed

transmit

imposed by

variety

input/output

types

each

or words

with

24

registers

equipment

and

system

data

the

The

input/

of

input/

under

computa-

bits

of

on/off

sensing

and

in

com-

decon-

time-

in-

un-

of

the

program

contained

Each

buffer

Interlace

with

buffer-to-memory

transmission

with

computation.

When in use, a the

data

supplies

ing to memory

the

number controls eration.

An

interlaced

tral

processor to transfer

The requires tation priority

output

the

central

specifies

in

each

may

allows

being

words

the

memory

of

input/output

of

two memory

stops in

over

the W buffer

logic.

processor for memory

WAND Y BUFFER

word

have

input/output

completely

buffer

going

through

address

and

maintains

words

transferred.

buffer

uses

faci I itate

each

word

cycles.

the

central

Any

interlaced

the

number

during

an

"interlace"

and

interlace

termination

the

input

between a buffer

processor. The Y buffer for

REGISTERS

of

characters

the

transmission.

associated

of

blocks

memory-to-buffer

automatic

controls

the

associated

of

data

coming from

the

word

count

The

interlace

during

memory

During this time,

the

buffer

and

output

use

access.

logic

of

has

DESCRIPTION

with

of

data

word

and

multiplexed

the

transfer

buffer.

determining

itself

interlaced

of

the

of

data

and memory

compu-

the

word

priority

to

be

words

or

go-

op-

cen-

words.

has

input/

over

it.

of

It

A

buffer

assembles

are

transmitted equipment. such as peripheral reverse).

The W buffer, forms gram 6-bit

1, 2, 3, 4 - bei

the

number

trol.

in

buffer.

cil

assembly/disassembly).

Each buffer vices bly and

Both 6-bit bits for

characters

operation

input/output

control.

characters,

buffer

receives

of

characters

The system may

function

ity

and disassembly, and

generation.

to

Additionally,

for

input/output

and

automatically

buffers

character

the

Y buffer). For

and

between

The

buffer

per

standard

of

On

output,

the

ng

under words in

the W buffer,

can

control

are

bidirectional

devices

disassembles

core

memory

maintains

word

transmitted

(as in

magnetic

equipment

data

words,

the

buffer

number

per

include

of

program

6-bit

word bei ng

the

as a the Y buffer of

24-bit

as many as

handles

input/output

and

(and word

character-oriented

data

words as

and

the

control

in each

characters

control. characters

Y buffer,

second

words (no

character,

can

of

and

tape

the

computer,

under

transmits words in

under

input/output

may

contain

character

30

input/output

parity

communicate

devices

of

they

peripheral

operations

direction

forward/

direct

per

word -

On

input,

with

the

program

identical

the

word

assem-

detection

up to

devices,

of

per-

pro-

con-

fa-

de-

with

24

Figure 4 contai functional the

memory,

D for a

Each has a chosen peripheral address address function

UAR er tai tial "inactive, not

The Word Assembly Register

acter

buffer.

sized

transmitted input,

character at a time,

functional

of

the

unique,

for

into

selects

"connects"

and

the

ns a zero

condition

connected

Register (SCR)

buffer,

6-bit

ns a

block

control

an

device,

to

buffer

II

The word assembly

during

register

into

of

and

the

flow

30

devices

two-digit,

input/output

the

6-bit

both

the

be

performed.

the

peripheral

becomes

address, or

clears

it

is

"ready"

to a

peripheral

comprise

contains

an

characters

where

the

WAR.

information

external

diagram

that

program loads

Unit Address Register (UAR). This

device

any

the

contents

the

input

(plus

the

diagram

octal

Placing a unit

"active.

to

word

or

Depending

of a buffer

between

devices.

of

the W buffer.

can

be

attached

address

operation.

the

and,

if

appropriate,

unit

addressed

II

When

time

that

a term inal

of

UAR,

buffer

ready

unit.

(WAR)

and

the

active

register, a 24-bit,

of

data

actively

output

parity)

buffer assembles

operation.

come

on the number

and

the

buffer,

See

Appendix

to a

by

which

To

choose

proper

address

to

the

buffer is

tests, and

Single

portion

into

the

them,

the

buffer

it

the

unit

in

buff-

UAR

or i ni-

it

Char-

of

a wordbeing

During

single

is

the the

con-

is

one

of

23

,------

------1

I

I r -

__

~~~_~h~~~~

IL

___________

I \ T

I 1

Optional,

I I Word

:~~t:.r

L____

for Y Buffer C t

__

-.-

____

..,

~

Parity

_________

Co~nt

Register Memory

Character

;::i~;er

Character

0:

_______ 1

Unit Address I

Register I

IIIIII

~ddress

Register I

I

II

I Word Assembly Register "

I

r-I-H-i

"'II--W-o-r-d-C-o-un-t---.----S-t-a-rt-i

lO

....

-_-_-=~-5~6~-=~-U.-.....1-2~~-~_1-7~1-~8-----~23-10-1

characters

ing

input

unfilled

One

character

per

word

has

the

character

per

To/from

form shown

positions

word

memory

specified,

contain

the

word assembled

below.

unpredictable

In

Figure

each

case,

4.

XDS 910 W(Y) Buffer

dur-

the

data.

2

__

During

where

the

6-bit

character

per

word mode

characters

~terl~~~2RegiS~

output,

words

buffer

disassembles them

at a time.

specified,

(with

generated

come

from memory into

the

parity)

n-g-A-d-d-re-s-s--"'" I

____

into

the

Depending

buffer

on

the

transmits

as follows:

2_5_J

the

WAR

SeR,

one

characters

the

6-bit

o

Two

characters

o

Three

characters

o 5 6

Four

characters

1 st

o 5 6

A word placed

lace the

assembled

into

memory by a WIM

control,

word, when

per

word

1112

per

word

1 st

I

per

word

2nd

I

during a single-word

the

interlaced

assembled,

buffer

into

1718

1 st

I

2nd

3rd

I

1718

instruction.

automatically

memory.

1 st

2nd

3rd

I

4th

operation

Under

I

is

inter-

places

23

Function

Output

from

Output

from through

Output

from

12-17

Output

from

12-17,

After

shifts those required, comes

The Y specified character according

one

bits

bits 0 -5

each left characters

to

Y

BUFFER

buffer

Mode

ready

from

to 24

option

One

Two

Three

Four

the

for

.each

character

0 through 5

two

characters

0 through

11

three

0-5,

four

18-23

character

six

a new word

the

size assembly, a Y buffer inputs

to

5,6

characters

6-11,

characters

, 6 - 1

1,

transfer,

bits

to

be

needed

containing

WAR.

CHARACTER ASSEMBLY

can

have a single

from 6

the

bits

available

character

characters

word in

the

are

the

bits

in

length.

and

shown in

per

word

per

word

per

word

per

word

the

WAR

transfer

character(s)

register

outputs

until

used. When

of

Using

words

Table

2.

one

24

XDS 910 Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual