AbbreviationDescription
ASICApplication Specific Integrated Circuit
BDUBlock Data Update
DRDYData ready
ESDElectrostatic Discharge
FIFOFirst-In First-Out
HBMHuman Body Model
I2CInter Integrated Circuit
LGALand Grid Array
LSBLeast Significant Bit
MEMSMicro-Electro Mechanical System
MISOMaster In Slabe Out
MOSIMaster Out Slave In
MSBMost Significant Bit
NVMNon Volatile Memory
ODROutput Data Rate
PCBPrinted Circuit Board
SPISerial Peripheral Interface
This device is a MEMS based piezo-resistive absolute pressure sensor. The sensor comprises of a pressure sensing cell and an analog and digital signal processing unit. The
integrated ASIC with digital I2C interface provides a digital signal to the host controller. The
sensor has an embedded temperature sensor. A 128 level embedded FIFO buffer is available to store the pressure and temperature data. The sensor comes in fully molded holed
land grid array package (LGA) having a form factor of 2.0 x 2.0 x 0.8 mm.
1.1 Application
• Altimeters and barometers
• Weather stations
• GPS navigation enhancement
• Indoor navigation
• White goods
• Wearable devices
1.2 Key features
• Absolute pressure range: 26 to 126 kPa
• Output data rate: 1 Hz to 200 Hz
• Integrated temperature sensor
• Pressure data: 24-bits and temperature data: 16-bits
WE order codeDimensionsDescription
25110202133012.0 x 2.0 x 0.8 mmTape & reel packaging
25110202133812.0 x 2.0 x 0.8 mm5 pcs. cut tape packaging
251122301330133 x 20 mmEvaluation board
The MEMS cell is the primary pressure sensing element. It contains piezo-resistors embedded on a suspended silicon membrane. The piezo-resistors are connected in a Wheatstone
bridge configuration. When pressure is applied, the membrane is deflected and the bridge
resistance changes. This change leads to a change of the Wheatstone output voltage proportional to the applied pressure. This analog signal is fed to the ASIC.
1.5.2 ASIC
The ASIC comprises of low-noise amplifier, analog-to-digital converter and other signal conditioning blocks that converts an uncompensated analog voltage equivalent to a 24-bit digital
pressure value.
The ASIC embeds a high-resolution temperature sensor which is used for internal compensation of the pressure signal. The temperature information can also be read as a 16-bit
digital value.
1.5.3 Calibration
The sensor is factory calibrated for both pressure and temperature measurements. The
trimming parameters are stored on-chip in the non volatile memory (NVM). Every-time the
sensor is powered on, these trimming parameters are copied from the NVM to the registers.
In normal use, no further calibration is required from the user.
The sensor has on-chip signal conditioning and embeds two digital low pass filters. The first
filter LPF1 is applied to both pressure and temperature data. The second filter LPF2 can be
optionally applied only to the pressure data. User can turn on or off this filter, depending on
his requirements.
1.5.5 FIFO memory
The sensor has embedded FIFO buffer that can store up to 128 levels of pressure and
temperature data. This can save host controller power, since the controller doesn’t have to
poll for data continuously.
1.6 Filtering chain and data path
Figure2shows detailed information about the functionality of the sensor. The sensor can be
operated in various operating modes and filter setting which determines the pressure and
temperature data path.
ParameterValue
Operating temperature-40 up to +85°C
Storage conditions< 40 °C; < 90% RH
Communication interfaceI2C
Moisture sensitivity level (MSL)3
Electrostatic discharge protection (HBM)2.5 kV
Table 2: General information
2.2 Absolute maximum ratings
Absolute maximum ratings are the limits, the device can be exposed to without causing
permanent damage. Exposure to absolute maximum conditions for extended periods may
affect device reliability.
ParameterSymbol
Input voltage VDD pinV
Input voltage VDD_IO pinV
Input voltage SDA, SCL, CS & SAO pinsV
OverpressureP
DD_MAX
DD_IO_MAX
IN_MAX
OVER
Table 3: Absolute maximum ratings
Supply voltage on any pin should never exceed 4.8 V.
The device is susceptible to be damaged by electrostatic discharge (ESD).
Always use proper ESD precautions when handling. Improper handling of the
device can cause performance degradation or permanent damage.
The sensor supports standard I2C (Inter-IC) bus protocol. Further information about the I2C
interface can be found at https://www.nxp.com/docs/en/user-guide/UM10204.pdf. I2C is a
serial 8-bit protocol with two-wire interface that supports communication between different
ICs, for example, between microcontrollers and other peripheral devices.
4.1 General characteristics
A serial data line (SDA) and a serial clock line (SCL) are required for the communication
between the devices connected via I2C bus. Both SDA and SCL lines are bidirectional. The
output stages of devices connected to the bus must have an open-drain or open-collector.
Hence, the SDA and SCL lines are connected to a positive supply voltage via pull-up resistors. In I2C protocol, the communication is realized through master-slave principle. A master
device generates the clock pulse, a start command and a stop command for the data transfer. Each connected device on the bus is addressable via a unique address. Master and
slave can act as a transmitter or a receiver depending upon whether the data needs to be
sent or received.
This sensor behaves like a slave device on the I2C bus
The positive supply voltage to which SDA and SCL lines are pulled up (through pull-up
resistors), in turn determines the high level input for the slave devices. The sensor has
separate supply voltage VDD_IO for the SDA and SCL lines. The logic high ’1’ and logic
low ’0’ levels for the SDA and SCL lines then depend on the VDD_IO. Input reference levels
for this sensor are set as 0.8 * VDD_IO (for logic high) and 0.2 * VDD_IO (for logic low).
Explained in the figure5.
Figure 5: SDA and SCL logic levels
4.3 Communication phase
4.3.1 Idle state
During the idle state, the bus is free and both SDA and SCL lines are in logic high ’1’ state.
4.3.2 START(S) and STOP(P) condition
Data transfer on the bus starts with a START command, which is generated by the master.
A start condition is defined as a high-to-low transition on the SDA line while the SCL line is
held high. The bus is considered busy after the start condition.
Data transfer on the bus is terminated with a STOP command, which is also generated by
the master. A low-to-high transition on the SDA line, while the SCL line being high is defined
as a STOP condition. After the stop condition, the bus is again considered free and is in idle
state. Figure6shows the I2C bus START and STOP conditions.
Master can also send a REPEATED START (SR) command instead of STOP command.
REPEATED START condition is the same as the START condition.
After the start condition, one data bit is transferred with each clock pulse. The transmitted
data is only valid when the SDA line data is stable (high or low) during the high period of the
clock pulse. High or low state of the data line can only change when clock pulse is in low
state.
Figure 6: Data validity, START and STOP condition
4.3.4 Byte format
Data transmission on the SDA line is always done in bytes, with each byte being 8-bits long.
Data is transferred with the most significant bit (MSB) followed by other bits.
If the slave cannot receive or transmit another complete byte of data, it can force the master
into a wait state by holding SCL low. Data transfer continues when the slave is ready which
is indicated by releasing the SCL line.
4.3.5 Acknowledge(ACK) and No-Acknowledge(NACK)
Each byte sent on the data line must be followed by an Acknowledge bit. The receiver (master or slave) generates an Acknowledge signal to indicate that the data byte was received
successfully and another data byte could be sent.
After one byte is transmitted, the master generates an additional Acknowledge clock pulse
to continue the data transfer. The transmitter releases the SDA line during this clock pulse
so that the receiver can pull the SDA line to low state in such a way that the SDA line
remains stable low during the entire high period of the clock pulse. This is considered as an
Acknowledge signal.
In case the receiver does not want to receive any further byte, it does not pull down the SDA
line and it remains in stable high state during the entire clock pulse. This is considered as
a No-Acknowledge signal and the master can generate either a stop condition to terminate
the data transfer or a repeated start condition to initiate a new data transfer.
The slave address is transmitted after the start condition. Each device on the I2C bus has a
unique address. Master selects the slave by sending corresponding address after the start
condition. A slave address is 7 bits long followed by a Read/Write bit.
Figure 7: Slave address format
The 7-bit slave address for this sensor is 101110xb. LSB of the 7-bit slave address can be
modified with the SAO pin. When SAO is connected to positive supply voltage, the LSB is
’1’, making 7-bit slave address 1011101b (0x5D). If SAO is connected to ground, the LSB is
’0’, making 7-bit address 1011100b (0x5C).
The R/W bit determines the data direction. A ’0’ indicates a write operation (transmission
from master to slave) and a ’1’ indicates a read operation (data request from slave).
Once the slave-address and data direction bit is sent, the slave acknowledges the master.
The next byte sent by the master must be a register-address of the sensor. This indicates
the address of the register where data needs to be written to or read from.
Figure 8: Complete data transfer
After receiving the register address, the slave sends an Acknowledgement (ACK). If the
master is still writing to the slave (R/W bit = 0), it will transmit the data to slave in the same
direction. If the master wants to read from the addressed register (R/W bit =1), a repeated
start (SR) condition must be sent to the slave. Master acknowledges the slave after receiving
each data byte. If the master no longer wants to receive further data from the slave, it would
send No-Acknowledge (NACK). Afterwards, Master can send a STOP condition to terminate
the data transfer. Figure9shows the writing and reading procedures between the master
and the slave device (sensor).
7-bit slave address of this device is 101110xb. LSB of the 7-bit slave address
depends on the SAO pin
Serial Peripheral Interface (SPI) is a synchronous serial communication bus system for the
communication between host microcontroller and other peripheral ICs such as ADCs, EEPROMs, sensors, etc. SPI is a full-duplex master-slave based interface allowing the communication to happen in both directions simultaneously. The data from the master or the slave
is synchronized either on the rising or falling edge of clock pulse. SPI can be either 4-wire or
3-wire interface. 4-wire interface consists of two signal lines and two data lines. All of these
bus lines are unidiretional.
1. Clock (SCL)
2. Chip select (CS)
3. Master out, slave in (MOSI)
4. Master in, slave out (MISO)
Figure 10: SPI Interface
Master generates the clock signal and is connected to all slave devices. Data transmission
between the master and salves is synchronized to the clock signal generated by the master.
One master can be connected to one or more slave devices. Each slave device is addressed
and controlled by the master via individual chip select (CS) signals. CS is controlled by the
master and is normally an active low signal.
MOSI and MISO are data lines. MOSI transmits data from the master to the slave. MISO
transmits data from the slave to the master.
Communication begins when the master selects a slave device by pulling the CS line to
LOW. The clock and data lines (MOSI/MISO) are available for the selected slave device.
Data stored in the specific shift registers are exchanged synchronously between master and
the slave through MISO and MOSI lines. The data transmission is over when the chip select
line is pulled up to the HIGH state. 4-wire SPI uses both data lines for the synchronous data
exchange in both the direction. 3-wire SPI shares a single data line for the data transfer,
where the master and slave alternate their transmitter and receiver roles synchronously.
5.2 Communcation modes
In SPI, the master can select the clock polarity (CPOL) and clock phase (CPHA). The CPOL
bit sets the polarity of the clock signal during the idle state. The CPHA bit selects the clock
phase. Depending on the CPHA bit, the rising or falling clock edge is used to sample and
shift the data. Depending on the CPOL and CPHA bit selection in the SPI control registers,
four SPI modes are available as per table10. In order to ensure proper communication,
master and the slave must be set to same communication modes.
CPOLCPHADesription
00Clock polarity LOW in idle state; Data sampled on the rising clock edge
01Clock polarity LOW in idle state; Data sampled on the falling clock edge
11Clock polarity HIGH in idle state; Data sampled on the falling clock edge
10Clock polarity HIGH in idle state; Data sampled on the rising clock edge
4-Wire SPI of this sensor uses following lines: SDA (data input, MOSI), SAO (data output,
MISO), SCL (serial clock) and CS (chip select). For more information, please refer to pin
description in the section
CS is pulled LOW by the master at the start of communication. The SCL polarity is HIGH in
the idle state (CPOL = 1). The data lines (SDA & SAO) are sampled at the falling clock edge
and latched at the rising clock edge (CPHA = 1). Data is transmitted with MSB first and the
LSB last.
SPI read and write operations are completed in 2 or more bytes (multiple of 16 or more clock
pulses). Each block consits of a register address byte and a data byte. The first byte is the
register address. In the SPI communication, the register address is specified in the 7-bits
and the the MSB of the register address is used as an SPI read/write bit (Figure11). When
R/W is ’0’, the data is written on to the sensor. When ’1’, the data is read from the sensor.
3.2
Figure 11: SPI register address
The next bytes of data, depending on the R/W bit, is either written to or read from the indexed
register. Figure12shows the complete SPI data transfer protocol.
The sensor also supports 3-wire SPI communication. SDA is used for both
data read and write operations. Communication protocol remains the same.
Figure 12: 4-wire SPI data transfer (CPOL = 1, CPHA = 1)
The write operation starts with the CS = LOW and sending the 7-bit register address with
R/W bit = ’0’ (write command). Next byte is the data byte that is the data to be written to the
indexed register. Several write command pairs can be sent without raising the CS back to
HIGH. The operation is ended with CS = HIGH. The SPI write protocol is shown in the figure
13
.
Figure 13: SPI write protocol
5.3.2 SPI read operation
The read operation starts with the CS = LOW and sending the 7-bit register address with
R/W bit = ’1’ (read command). Data is sent out from the sensor through the SAO line. The
SPI read protocol is shown in the figure14.
If 3-wire SPI is used, the data is sent out through the SDA line.
Figure 14: SPI read protocol
During multiple read/write operation, the register address is automatically incremented after each block. This feature is enabled by default with the bit
IF_ADD_INC set to ’1’ in the CTRL_2 register.
Figure 15: Application circuit with I2C interface (top view)
The sensor has two separate supply pins: VDD and VDD_IO. VDD pin is the central supply pin for the MEMS cell and internal circuits. VDD_IO provides the supply to the digital
interface.
VDD_IO voltage level must be equal to or lower than VDD+0.1 V.
In order to prevent ripple from the power supply, a decoupling capacitor of 100 nF must be
placed as close to the VDD pad of the sensor as possible. An optional decoupling capacitor
(4.7 µF) could placed as shown in the figure15. If VDD_IO is not connected to the VDD line,
a separate decoupling capacitor of 10nF should be added on the VDD_IO line.
Figure15shows a typical application circuit for I2C communication. For proper I2C functionality, the CS pin must be connected to VDD. Least significant bit of the 7-bit slave address
can be modified based on the status of the SAO pin. In order to optimize the power consumption, it is recommended to connect SAO pin to VDD (SAO = 1) if only one sensor is
used on the I2C line. This sets the 7 bit slave address as 0x5D (1011101b). SCL and SDA
must be connected to VDD_IO through the pull-up resistors. Proper value of the pull-up
resistors must be chosen depending on the I2C bus speed and load.
Pins SDA and SCL have internal pull up resistors. By default they are disabled and can
be enabled through bits SDA_PU_EN and SAO_PU_EN in InNTERFACE_CTRL register
(0x0E). Value of the internal pull up varies between 30kΩ 50kΩ, depending on VDD_IO.
Sensor communication with the master controller remains active even if VDD is disconnected
while VDD_IO is maintained. However, in this situation, the internal measurement cycle is
turned off.