WJ Communications AH103 Technical data

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AH103

High Gain, High Linearity ½ Watt Amplifier Product Information

Product Features

• 60 – 2700 MHz

• +27 dBm P1dB

• +46 dBm Output IP3

• 28.5 dB Gain @ 900 MHz

• Excellent ACPR

• MTTF > 100 Years

• SOIC-8 Pkg w/ heat slug

Applications

•

Mobile Infrastructure

•

W-LAN / ISM / RFID

•

MDS / MMDS Infrastructure

Specifications

Product Description

The AH103 is a high gain, high linearity ½-Watt
amplifier. This device is comprised of two individual
MMIC amplifiers internally and can be used with an
external interstage match for any of the mobile
infrastructure frequency bands. The dual-stage
amplifier achieves up to +46 dBm IP3 performance
with 28.5 dB gain.

The device conforms to WJ Communications’ long
history of producing high reliability and quality
components. The AH103 has an associated MTTF of
a minimum of 100 years at a mounting temperature
of 85°C. All devices are 100% RF & DC tested.

The product is targeted for use as driver amplifiers
for wireless infrastructure where high performance
and high linearity are required.

Typical Performance

The Communications Edge TM

Functional Diagram

1

2

AMP 1

3

4

Function Pin No.

Amp2 in 1

Amp1 out / Bias 1 2

Ground

RF in (Amp1 in) 4

RF out (Amp2 out) 6

Bias 2 7

AMP 2

3, 5, 8,

Backside copper

8

7

6

5

Parameter Units Min Typ Max

Frequency Range (2) MHz 60 800 2700
Gain dB 26.5
Input Return Loss dB
Output Return Loss dB
Output P1dB dBm +26
Output IP3 (3)

IS-95 Channel Power (4)

@ -45 dBc ACPR

Noise Figure dB 2.9
Supply Voltage (Amp1) V
Supply Voltage (Amp2) V
Operating Current (Amp1) mA 55
Operating Curre n t ( A mp2 ) mA 170
Thermal Resistance (5) °C / W
Junction Temperature (6) °C

Test conditio ns unles s otherwise noted.

1. T = 25ºC, Vdd1 = +4.5 V, Vdd2 = +9 V, Frequency = 800 MHz in a tuned application circuit.

2. The frequency of operation & bandwidth is determined by the external interstage match.

3. 3OIP measured with two tones at an out put power of +10 dBm/tone separated by 10 MHz. T he
suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule.

4. IS-95, 9 Channels Forward, Pk/Avg Ratio = 11.5 dB at a .001% probability

±750 kHz offset, 30 kHz BW, Channel BW = 1.23 MHz, frequency = 880 MHz.

5. The worst-case junction temperature for a g iven ground tab temperature can be calculated by
multiplying the thermal resistance with the tot al package power d issipation and adding it to the t ab
temperature. ie. At 85°C case temperature for a typ ical device, the worst-case junction temperature
would be = 85°C + (9 V * 0.2 A + 4.5 V * 0.075 A) = 129°C.

6. The junction temperature ensures a minimum MTTF rating of 1 million hours of usage.

dBm +43
dBm

28.5
20
11

+27
+46

+21

+4.5

+9
75

200

100
230

20.6
160

Parameter Units Typical

Frequency MHz 900 1900 2140 2400
S21 dB
S11 dB
S22 dB
Output P1dB dBm
Output IP3 dBm

Channel Power

@ -45 dBc ACPR / ACLR

Noise Figure dB
Supply Bias 1
Supply Bias 2 +9 V @ 200 mA

7. Typical parameters reflect performance in an application circuit.

8. An IS-95 signal is used for 915 / 1960 MHz. A 3GPP W-CDMA signal is used for 2140 MHz.

dBm

28.5 26 25

-15 -12 -11

-11 -11 -14
+27 +26.5 +26.5
+46 +45 +45

+21 +20 +17.2

2.9 3.7 3.5 3.6

+4.5 V @ 75 mA

24.7

-12

-17

+26

+43.3

Absolute Maximum Rating Ordering Information

Parameter Rating Part No. Description

Operating Case Temperature
Storage Temperature
DC Voltage (pin 2) +6 V
DC Voltage (pin 6, 7) +11 V
RF Input Power (continuous) 4 dB above Input P1dB
Junction Temperature

Operation of this device above any of these parameters may cause permanent damage.

WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: [phone] • e-mail: [e-mail] • Web site: www.wj.com November 2003

-40 to +85 °C

-55 to +125 °C

+220°C

AH103 High Gain ½ Watt Amplifier

AH103-PCB900 0.7 – 1.0 GHz Evaluation Circuit
AH103-PCB1750 1.7 – 1.8 GHz Evaluation Circuit
AH103-PCB1900 1.8 – 2.0 GHz Evaluation Circuit
AH103-PCB2140 2.1 – 2.2 GHz Evaluation Circuit

(available in tape and reel)

Specifications and information are subject to change without notice

AH103

The Communications Edge TM

High Gain, High Linearity ½ Watt Amplifier Product Information

Application Circuit

Ref. Desig. Component

R1
L2, L3 18 nH chip inductor
C6, C10, C12
U1 WJ AH103 Amplifier

U2

5. All components are of size 0603.

6.

Ref. Desig. Component

L1 10 nH chip inductor
L4 5.6 nH chi p inductor
C1
C5, C11 5.6 pF chip capacitor

Notes:

1. DNP = Do not place this component.

2. Distance “D1” measured from U1, pin 4 to edge of Cx (where x = 2, 3, or 4).

3. A voltage regulator is used in this circuit (U2) to drop the +9 V to a +5 V usable supply for the first

4. A +4.5 V supply can also be used to bypass the 6.8 Ω and can be applied to Test Point 2 (TP2).

a. D1 = 0.620” to C2 (for use with AH103-PCB1750)

The 2.0 pF input tuning capacitor is placed .045” to the left of “C2” shown on the silk
screen. The s hunt capacitor is placed direc tly on the right and adjacent t o the input

blocking capacitor C1.
b. D1 = 0.450” to C3 (for use with AH103-PCB1900)
c. D1 = 0.310” to C4 (for use with AH103-PCB2140)

st

internal amplifier. It is permissible to remove the regulator and operate the 1
directly off of +5 V supply onto Test Point 1 (TP1). The use of a +5 V supply on the 1
stage requires a dropping resistor of 6.8 Ω.

amplifier stage

st

amplifier

Evaluation Board PCB Layout

Circuit Board Material: .014” FR-4, 4 layers, .062” total thickness

WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: [phone] • e-mail: [e-mail] • Web site: www.wj.com November 2003

Specifications and information are subject to change without notice

C7 10 pF chip capacitor
C9 1.5 pF chip capacitor
C2, C3, C4, C8 DNP

1700 – 1800 MHz App. Circuit

Ref. Desig. Component

C1, C11 47 pF chip capacitor
C2 2.0 pF chip capaci to r
C5
C8 10 pF chip capacitor
C3, C4, C7
C9, L1, L4

See note (2a) f or the proper placement of C2.

1800 – 2000 MHz App. Circuit

Ref. Desig. Component

C1, C11 47 pF chip capacitor
C3 1.5 pF chip capaci to r
C5
C8 10 pF chip capacitor
C2, C4, C7
C9, L1, L4

2110 – 2140 MHz App. Circuit

Ref. Desig. Component

C1, C11 47 pF chip capacitor
C4 1.2 pF chip capaci to r
C5
C8 10 pF chip capacitor
C2, C3. C7
C9, L1, L4

2.4 – 2.7 GHz Reference Circuit

Ref. Desig. Component

L1 1 pF chip capacitor
C1
C5 22 pF chip capacitor
C8 10 pF chip capacitor
C11 47 pF chip capacitor
C2, C3. C4
C7, C9, L4

Bill of Materials

All Application Circuits

6.8 Ω chip resistor

.018 µF chip capacitor

+5V Regulator,
National Semico nducto r
NJM78L05

Other components not shown above are specific
for the frequency band of interest.

AH103-PCB900

700 – 1000 MHz App. Circuit

0 Ω chip resistor

AH103-PCB1750

0 Ω chip resistor

DNP

AH103-PCB1900

0 Ω chip resistor

DNP

AH103-PCB2140

0 Ω chip resistor

DNP

0 Ω chip resistor

DNP