Wiznet W7500, W7500P Reference Manual

W7500x

Reference Manual

Version 1.1.0

http://www.wiznet.io

© Copyright 2018 WIZnet Co., Ltd. All rights reserved.

1 Table of Contents

1 Table of Contents ....................................................................................... 2

2 List of table ............................................................................................. 19

3 List of figures........................................................................................... 21

4 Documentation conventions ........................................................................ 23

4.1 Glossary ...................................................................................... 23

4.2 Register Bit Conventions .................................................................. 25

5 System and memory overview ..................................................................... 26

5.1 System architecture ....................................................................... 26

5.2 Memory organization ...................................................................... 27

Introduction ....................................................................................... 27

Memory map ...................................................................................... 28

6 System configuration controller (SYSCFG) ....................................................... 29

7 Interrupt and events ................................................................................. 29

7.1 Nested vectored interrupt controller (NVIC) .......................................... 29

NVIC main features .............................................................................. 29

SysTick calibration value register ............................................................. 29

Interrupt and exception vectors............................................................... 29

7.2 Event ......................................................................................... 30

8 Power supply ........................................................................................... 31

8.1 Introduction ................................................................................. 31

8.2 Voltage regulator ........................................................................... 31

8.3 Low-power modes .......................................................................... 31

Sleep mode ........................................................................................ 32

Peripheral clock gating .......................................................................... 32

9 System tick timer ..................................................................................... 33

9.1 Introduction ................................................................................. 33

9.2 Features ..................................................................................... 33

9.3 Functional description .................................................................... 33

9.4 Registers (Base : 0xE000_E000) .......................................................... 34

System Timer control and status register (SYST_CSR) ..................................... 34

SysTick Reload Value Register (SYST_RVR) ................................................... 34

SysTick Current Value Register (SYST_CVR) ................................................. 35

SysTick Calibration Value Register (SYST_CALIB) ........................................... 35

10 Booting Sequence ..................................................................................... 36

11 Embedded Flash memory ............................................................................ 37

11.1 Flash main features ........................................................................ 37

11.2 Flash memory organization ............................................................... 37

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12 Clock Reset generator (CRG) ........................................................................ 39

12.1 Introduction ................................................................................. 39

12.2 Features ..................................................................................... 39

Reset....... ........................................................................................ 39

Clock....... ........................................................................................ 40

12.3 Functional description .................................................................... 41

External Oscillator Clock ....................................................................... 41

RC oscillator clock ............................................................................... 42

PLL......... ......................................................................................... 42

Generated clock .................................................................................. 42

12.4 Registers (Base address : 0x4100_1000) ................................................ 44

OSC power down register (OSC_PDR) ......................................................... 44

PLL power down register (PLL_PDR) .......................................................... 44

PLL frequency calculating register (PLL_FCR) .............................................. 44

PLL output enable register (PLL_OER) ....................................................... 45

PLL bypass register (PLL_BPR) ................................................................. 45

PLL input clock source select register (PLL_IFSR) .......................................... 46

FCLK source select register (FCLK_SSR) ...................................................... 46

FCLK prescale value select register (FCLK_PVSR) .......................................... 47

SSPCLK source select register (SSPCLK_SSR) ................................................ 47

SSPCLK prescale value select register (SSPCLK_PVSR) .................................... 48

ADCCLK source select register (ADCCLK_SSR) .............................................. 48

ADCCLK prescale value select register (ADCCLK_PVSR) ................................... 48

TIMER0CLK source select register (TIMER0CLK_SSR) ....................................... 49

TIMER0CLK prescale value select register (TIMER0CLK_PVSR) ........................... 49

TIMER1CLK source select register (TIMER1CLK_SSR) ....................................... 50

TIMER1CLK prescale value select register (TIMER1CLK_PVSR) ........................... 50

PWM0CLK source select register (PWM0CLK_SSR) .......................................... 51

PWM0CLK prescale value select register (PWM0CLK_PVSR) .............................. 51

PWM1CLK source select register (PWM1CLK_SSR) .......................................... 52

PWM1CLK prescale value select register (PWM1CLK_PVSR) .............................. 52

PWM2CLK source select register (PWM2CLK_SSR) .......................................... 53

PWM2CLK prescale value select register (PWM2CLK_PVSR) .............................. 53

PWM3CLK source select register (PWM3CLK_SSR) .......................................... 54

PWM3CLK prescale value select register (PWM3CLK_PVSR) .............................. 55

PWM4CLK source select register (PWM4CLK_SSR) .......................................... 55

PWM4CLK prescale value select register (PWM4CLK_PVSR) .............................. 56

PWM5CLK source select register (PWM5CLK_SSR) .......................................... 56

PWM5CLK prescale value select register (PWM5CLK_PVSR) .............................. 57

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PWM6CLK source select register (PWM6CLK_SSR) .......................................... 57

PWM6CLK prescale value select register (PWM6CLK_PVSR) .............................. 58

PWM7CLK source select register (PWM7CLK_SSR) .......................................... 58

PWM7CLK prescale value select register (PWM7CLK_PVSR) .............................. 59

RTC High Speed source select register (RTC_HS_SSR) ..................................... 59

RTC High Speed prescale value select register (RTC_HS_PVSR) ......................... 60

RTC source select register (RTC_SSR) ........................................................ 60

WDOGCLK High Speed source select register (WDOGCLK_HS_SSR) ...................... 61

WDOGCLK High Speed prescale value select register (WDOGCLK_HS_PVSR) .......... 61

WDOGCLK clock source select register (WDOGCLK_SSR).................................. 62

UARTCLK source select register (UARTCLK_SSR) ........................................... 62

UARTCLK prescale value select register (UARTCLK_PVSR) ................................ 63

MIICLK enable control register (MIICLK_ECR) ............................................... 63

Monitoring Clock source select register (MONCLK_SSR) ................................... 64

12.5 Register map ................................................................................ 65

13 Tcp/ip core Offload Engine (TOE) .................................................................. 67

13.1 Introduction ................................................................................. 67

13.2 Features ..................................................................................... 67

13.3 Functional description .................................................................... 68

13.4 TOE Memory map ........................................................................... 68

Common register map ........................................................................... 70

Socket register map ............................................................................. 70

Memory............................................................................................. 71

13.5 Common register (Base : 0x4600_0000) ................................................ 73

VERSIONR (TOE Version Register) .............................................................. 73

TCKCNTR (Ticker Counter Register) .......................................................... 73

IR (Interrupt Register) ........................................................................... 74

IMR (Interrupt Mask Register) .................................................................. 74

IRCR (Interrupt Clear Register) ................................................................ 75

SIR (Socket Interrupt Register) ................................................................ 76

SIMR (Socket Interrupt Mask Register) ........................................................ 76

MR (Mode Register) .............................................................................. 77

PTIMER (PPP Link Control Protocol Request Timer Register) ............................. 78

PMAGICR (PPP Link Control Protocol Magic number Register) ........................... 78

PHAR (Destination Hardware Address Register in PPPoE) ................................. 78

PSIDR (Session ID Register in PPPoE) .......................................................... 79

PMRUR (Maximum Receive Unit Register in PPPoE) ........................................ 80

SHAR (Source Hardware Address Register)................................................... 80

GAR (Gateway Address) ......................................................................... 81

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SUBR ( Subnet Mask Register) .................................................................. 81

SIPR (Source IP address Register) ............................................................. 82

NCONFLR ( Network Configuration Lock Register) ......................................... 82

RTR (Retry Time Register) ...................................................................... 83

RCR (Retry Counter Register) .................................................................. 84

UIPR (Unreachable IP address Register) ...................................................... 85

UPORTR (Unreachable Port Register) ......................................................... 86

13.6 Socket register (Base : 0x4601_0000 + 0x0004_000 x n)[n=0,…7, where n is

socket number] ......................................................................................... 86

Sn_MR (Socket n Mode Register)............................................................... 86

Sn_CR (Socket n Command Register) ......................................................... 89

Sn_IR (Socket n Interrupt Register) ........................................................... 91

Sn_IMR (Socket n Interrupt Mask Register) .................................................. 91

Sn_ICR (Socket n Interrupt Clear Register) .................................................. 92

Sn_SR (Socket n Status Register) .............................................................. 93

Sn_PNR (Socket n Protocol Number Register) ............................................... 95

Sn_TOSR (Socket n IP Type of Service Register) ............................................ 96

Sn_TTLR (Socket n TTL Register) .............................................................. 96

Sn_FRAGR (Socket n Fragment offset Register) ............................................ 97

Sn_MSSR (Socket n Maximum Segment Register) ........................................... 97

Sn_PORTR (Socket n Source Port Register) .................................................. 98

Sn_DHAR (Socket n Destination Hardware address Register) ............................. 98

Sn_DPORTR (Socket n Destination Port Number Register) ................................ 99

Sn_DIPR (Socket n Destination IP address Register)....................................... 100

Sn_KATMR (Socket n Keep Alive Timer Register) ........................................... 101

Sn_RTR (Socket n Retry Time Register) ................................................... 101

Sn_RCR (Socket n Retry Counter Register) ................................................. 102

Sn_TXBUF_SIZE (Socket n TX Buffer Size Register) ........................................ 102

Sn_TX_FSR (Socket n TX Free Size Register) ............................................... 103

Sn_TX_RD (Socket n TX Read Pointer Register) ............................................ 104

Sn_TX_WR (Socket n TX Write Pointer Register) ........................................... 105

Sn_RXBUF_SIZE (Socket n RX Buffer Size Register)........................................ 105

Sn_RX_RSR (Socket n RX Received Size Register) ......................................... 106

Sn_RX_RD (Socket n RX Read Pointer Register) ............................................ 107

Sn_RX_WR (Socket n RX Write Pointer Register) ........................................... 108

14 Random number generator (RNG) ............................................................... 109

14.1 Introduction ................................................................................ 109

14.2 Features .................................................................................... 109

14.3 Functional description ................................................................... 109

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Operation RNG ................................................................................... 110

14.4 Registers (Base address : 0x4000_7000) ............................................... 111

RNG run register (RNG_RUN) .................................................................. 111

RNG SEED register (RNG_SEED) ............................................................... 111

RNG clock select register (RNG_CLKSEL) ................................................... 111

RNG manual mode select register (RNG_MODE) ........................................... 112

RNG random number value register (RNG_RN) ............................................ 112

RNG polynomial register (RNG_POLY) ....................................................... 113

14.5 Register map ............................................................................... 114

15 Alternate Function Controller (AFC) ............................................................ 114

15.1 Introduction ................................................................................ 114

15.2 Features .................................................................................... 114

15.3 Functional description ................................................................... 114

15.4 Registers (Base address : 0x4100_2000) ............................................... 117

PA_00 pad alternate function select register (PA_00_AFR) .............................. 117

PA_01 pad alternate function select register (PA_01_AFR) .............................. 117

PA_02 pad alternate function select register (PA_02_AFR) .............................. 118

PA_03 pad alternate function select register (PA_03_AFR) .............................. 118

PA_04 pad alternate function select register (PA_04_AFR) .............................. 119

PA_05 pad alternate function select register (PA_05_AFR) .............................. 119

PA_06 pad alternate function select register (PA_06_AFR) .............................. 120

PA_07 pad alternate function select register (PA_07_AFR) .............................. 120

PA_08 pad alternate function select register (PA_08_AFR) .............................. 121

PA_09 pad alternate function select register (PA_09_AFR) .............................. 121

PA_10 pad alternate function select register (PA_10_AFR) .............................. 122

PA_11 pad alternate function select register (PA_11_AFR) .............................. 122

PA_12 pad alternate function select register (PA_12_AFR) .............................. 123

PA_13 pad alternate function select register (PA_13_AFR) .............................. 123

PA_14 pad alternate function select register (PA_14_AFR) .............................. 124

PA_15 pad alternate function select register (PA_15_AFR) .............................. 124

PB_00 pad alternate function select register (PB_00_AFR) ............................. 125

PB_01 pad alternate function select register (PB_01_AFR) ............................. 125

PB_02 pad alternate function select register (PB_02_AFR) ............................. 126

PB_03 pad alternate function select register (PB_03_AFR) ............................. 126

PB_04 pad alternate function select register (PB_04_AFR) ............................. 127

PB_05 pad alternate function select register (PB_05_AFR) ............................. 127

PB_06 pad alternate function select register (PB_06_AFR) ............................. 128

PB_07 pad alternate function select register (PB_07_AFR) ............................. 128

PB_08 pad alternate function select register (PB_08_AFR) ............................. 129

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PB_09 pad alternate function select register (PB_09_AFR) ............................. 129

PB_10 pad alternate function select register (PB_10_AFR) ............................. 130

PB_11 pad alternate function select register (PB_11_AFR) ............................. 130

PB_12 pad alternate function select register (PB_12_AFR) ............................. 131

PB_13 pad alternate function select register (PB_13_AFR) ............................. 131

PB_14 pad alternate function select register (PB_14_AFR) ............................. 132

PB_15 pad alternate function select register (PB_15_AFR) ............................. 132

PC_00 pad alternate function select register (PC_00_AFR) ............................. 133

PC_01 pad alternate function select register (PC_01_AFR) ............................. 133

PC_02 pad alternate function select register (PC_02_AFR) ............................. 134

PC_03 pad alternate function select register (PC_03_AFR) ............................. 134

PC_04 pad alternate function select register (PC_04_AFR) ............................. 135

PC_05 pad alternate function select register (PC_05_AFR) ............................. 135

PC_06 pad alternate function select register (PC_06_AFR) ............................. 136

PC_07 pad alternate function select register (PC_07_AFR) ............................. 136

PC_08 pad alternate function select register (PC_08_AFR) ............................. 137

PC_09 pad alternate function select register (PC_09_AFR) ............................. 137

PC_10 pad alternate function select register (PC_10_AFR) ............................. 138

PC_11 pad alternate function select register (PC_11_AFR) ............................. 138

PC_12 pad alternate function select register (PC_12_AFR) ............................. 139

PC_13 pad alternate function select register (PC_13_AFR) ............................. 139

PC_14 pad alternate function select register (PC_14_AFR) ............................. 140

PC_15 pad alternate function select register (PC_15_AFR) ............................. 140

PD_00 pad alternate function select register (PD_00_AFR) ............................. 141

PD_01 pad alternate function select register (PD_01_AFR) ............................. 141

PD_02 pad alternate function select register (PD_02_AFR) ............................. 142

PD_03 pad alternate function select register (PD_03_AFR) ............................. 142

PD_04 pad alternate function select register (PD_04_AFR) ............................. 143

15.5 Register map ............................................................................... 144

16 External Interrupt (EXTI) .......................................................................... 147

16.1 Introduction ................................................................................ 147

16.2 Features .................................................................................... 147

16.3 Functional description ................................................................... 147

16.4 Registers (Base address : 0x4100_2000) ............................................... 149

External interrupt enable register (Px_y EXTINT) ......................................... 149

16.5 Register map ............................................................................... 149

17 Pad Controller (PADCON) .......................................................................... 150

17.1 Introduction ................................................................................ 150

17.2 Features .................................................................................... 150

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17.3 Functional description ................................................................... 150

17.4 Registers (Base address : 0x4100_3000) ............................................... 152

PAD Control register (Px_y PCR)(x=A..D, y=0..15) ........................................ 152

17.5 Register map ............................................................................... 152

18 General-purpose I/Os(GPIO) ....................................................................... 153

18.1 Introduction ................................................................................ 153

18.2 Features .................................................................................... 153

18.3 Functional description ................................................................... 153

Masked access ................................................................................... 154

18.4 GPIO Registers(Address Base: 0x4200_0000) ......................................... 156

GPIO Data Register(GPIOx_DATA) (x=A..D) ................................................. 156

GPIO Output Latch Register(GPIOx_DATAOUT) (x=A..D) .................................. 156

GPIO Enable Set Register(GPIOx_OUTENSET) (x=A..D) ................................... 156

GPIO Enable Clear Register(GPIOx_OUTENCLR) (x=A..D) ................................ 157

GPIO Interrupt Enable Set Register(GPIOx_ INTENSET) (x=A..D) ....................... 157

GPIO Interrupt Enable Clear Register(GPIOx_ INTENCLR) (x=A..D)..................... 158

GPIO Interrupt Type Set Register(GPIOx_ INTTYPESET) (x=A..D) ....................... 158

GPIO Interrupt Type Clear Register(GPIOx_ INTTYPECLR) (x=A..D) .................... 159

GPIO Interrupt Polarity Set Register(GPIOx_ INTPOLSET) (x=A..D) ..................... 159

GPIO Interrupt Polarity Clear Register(GPIOx_ INTPOLCLR) (x=A..D) .................. 160

GPIO Interrupt Status/Clear Register(GPIO_ INTSTATUS/INTCLEAR) (x=A..D) ........ 161

GPIO Lower Byte Masked Access Register(GPIOx_ LB_MASKED) (x=A..D) .............. 161

GPIO Upper Byte Masked Access Register(GPIOx_ UB_MASKED) (x=A..D) ............. 162

18.5 Register map ............................................................................... 163

19 Direct memory access controller (DMA) ........................................................ 164

19.1 Introduction ................................................................................ 164

19.2 Features .................................................................................... 164

19.3 Functional description ................................................................... 164

DMA request mapping .......................................................................... 165

DMA arbitration .................................................................................. 165

DMA cycle types ................................................................................. 165

19.4 Registers (Base address : 0x4100_4000) ............................................... 168

DMA status register (DMA_STATUS) ........................................................... 168

DMA configuration register (DMA_CFG) ..................................................... 169

DMA control data base pointer register (DMA_CTRL_BASE_PTR) ....................... 170

DMA channel alternate control data base pointer register

(DMA_ALT_CTRL_BASE_PTR) .......................................................................... 170

DMA channel wait on request status register (DMA_WAITONREQ_STATUS) ............ 171

DMA channel software request register (DMA_CHNL_SW_REQUEST) ................... 171

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DMA channel useburst set register (DMA_CHNL_USEBURST_SET) ....................... 172

DMA channel useburst clear register (DMA_CHNL_USEBURST_CLR) .................... 172

DMA channel request mask set register (DMA_CHNL_REQ_MASK_SET) ................ 173

DMA channel request mask clear register (DMA_CHNL_REQ_MASK_CLR) .............. 174

DMA channel enable set register (DMA_CHNL_ENABLE_SET) ............................ 174

DMA channel enable clear register (DMA_CHNL_ENABLE_CLR) ......................... 175

DMA channel primary-alternate set register (DMA_CHNL_PRI_ALT_SET) .............. 175

DMA channel primary-alternate clear register (DMA_CHNL_PRI_ALT _CLR) .......... 176

DMA channel priority set register (DMA_CHNL_PRIORITY_SET) ......................... 176

DMA channel priority clear register (DMA_CHNL_PRIORITY_CLR) ...................... 177

DMA bus error clear register (DMA_ERR_CLR) .............................................. 177

19.5 Register map ............................................................................... 179

20 Analog-to-digital converter (ADC) ............................................................... 180

20.1 Introduction ................................................................................ 180

20.2 Features .................................................................................... 180

20.3 Functional description ................................................................... 181

Operation ADC with non-interrupt ........................................................... 181

Operation ADC with interrupt ................................................................. 183

20.4 Registers (Base address : 0x4100_0000) ............................................... 183

ADC control register (ADC_CTR) .............................................................. 183

ADC channel select register (ADC_CHSEL) .................................................. 184

ADC start register (ADC_START) .............................................................. 185

ADC conversion data register (ADC_DATA) .................................................. 185

ADC Interrupt register (ADC_INT) ............................................................ 185

ADC Interrupt Clear register (ADC_INTCLR) ................................................ 186

20.5 Register map ............................................................................... 187

21 Pulse-Width Modulation (PWM) ................................................................... 188

21.1 Introduction ................................................................................ 188

21.2 Features .................................................................................... 188

21.3 Functional description ................................................................... 189

Timer/Counter control ......................................................................... 189

Timer/Counter ................................................................................... 189

PWM mode ....................................................................................... 193

Interrupt.... ...................................................................................... 194

Dead zone generation .......................................................................... 195

Capture event ................................................................................... 196

How to set the PWM ............................................................................ 198

21.4 PWM Channel-0 Registers (Base address : 0x4000_5000) ........................... 198

Channel-0 interrupt register(PWMCH0IR) ................................................... 198

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Channel-0 interrupt enable register(PWMCH0IER) ........................................ 199

Channel-0 interrupt clear register(PWMCH0ICR) .......................................... 200

Channel-0 Timer/Counter Register (PWMCH0TCR) ........................................ 200

Channel-0 Prescale Counter Register (PWMCH0PCR) ..................................... 201

Channel-0 Prescale Register (PWMCH0PR) .................................................. 201

Channel-0 Match Register (PWMCH0MR) .................................................... 201

Channel-0 Limit Register (PWMCH0LR) ...................................................... 202

Channel-0 Up-Down Mode Register (PWMCH0UDMR) ...................................... 202

Channel-0 Timer/Counter Mode Register (PWMCH0TCMR)............................... 203

Channel-0 PWM output Enable and External input Enable Register (PWMCH0PEEER)

203

Channel-0 Capture Mode Register (PWMCH0CMR) ......................................... 204

Channel-0 Capture Register (PWMCH0CR) .................................................. 204

Channel-0 Periodic Mode Register (PWMCH0PDMR) ....................................... 204

Channel-0 Dead Zone Enable Register (PWMCH0DZER) ................................... 205

Channel-0 Dead Zone Counter Register (PWMCH0DZCR) ................................. 205

21.5 Register map ............................................................................... 206

21.6 PWM Channel-1 Registers (Base address : 0x4000_5100) ........................... 208

Channel-1 interrupt register(PWMCH1IR) ................................................... 208

Channel-1 interrupt enable register(PWMCH1IER) ........................................ 208

Channel-1 interrupt clear register(PWMCH1ICR) .......................................... 209

Channel-1 Timer/Counter Register (PWMCH1TCR) ........................................ 209

Channel-1 Prescale Counter Register (PWMCH1PCR) ..................................... 210

Channel-1 Prescale Register (PWMCH1PR) .................................................. 210

Channel-1 Match Register (PWMCH1MR) .................................................... 211

Channel-1 Limit Register (PWMCH1LR) ...................................................... 211

Channel-1 Up-Down Mode Register (PWMCH1UDMR) ...................................... 212

Channel-1 Timer/Counter Mode Register (PWMCH1TCMR)............................... 212

Channel-1 PWM output Enable and External input Enable Register (PWMCH1PEEER)

213

Channel-1 Capture Mode Register (PWMCH1CMR) ......................................... 213

Channel-1 Capture Register (PWMCH1CR) .................................................. 213

Channel-1 Periodic Mode Register (PWMCH1PDMR) ....................................... 214

Channel-1 Dead Zone Enable Register (PWMCH1DZER) ................................... 214

Channel-1 Dead Zone Counter Register (PWMCH1DZCR) ................................. 215

21.7 Register map ............................................................................... 216

21.8 PWM Channel-2 Registers (Base address : 0x4000_5200) ........................... 217

Channel-2 interrupt register(PWMCH2IR) ................................................... 217

Channel-2 interrupt enable register(PWMCH2IER) ........................................ 217

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Channel-2 interrupt clear register(PWMCH2ICR) .......................................... 218

Channel-2 Timer/Counter Register (PWMCH2TCR) ........................................ 218

Channel-2 Prescale Counter Register (PWMCH2PCR) ..................................... 219

Channel-2 Prescale Register (PWMCH2PR) .................................................. 219

Channel-2 Match Register (PWMCH2MR) .................................................... 220

Channel-2 Limit Register (PWMCH2LR) ...................................................... 220

Channel-2 Up-Down Mode Register (PWMCH2UDMR) ...................................... 220

Channel-2 Timer/Counter Mode Register (PWMCH2TCMR)............................... 221

Channel-2 PWM output Enable and External input Enable Register (PWMCH2PEEER)

221

Channel-2 Capture Mode Register (PWMCH2CMR) ......................................... 222

Channel-2 Capture Register (PWMCH2CR) .................................................. 222

Channel-2 Periodic Mode Register (PWMCH2PDMR) ....................................... 223

Channel-2 Dead Zone Enable Register (PWMCH2DZER) ................................... 223

Channel-2 Dead Zone Counter Register (PWMCH2DZCR) ................................. 224

21.9 Register map ............................................................................... 225

21.10 PWM Channel-3 Registers (Base address : 0x4000_5300) ........................... 226

Channel-3 interrupt register(PWMCH3IR) ................................................... 226

Channel-3 interrupt enable register(PWMCH3IER) ........................................ 226

Channel-3 interrupt clear register(PWMCH3ICR) .......................................... 227

Channel-3 Timer/Counter Register (PWMCH3TCR) ........................................ 227

Channel-3 Prescale Counter Register (PWMCH3PCR) ..................................... 228

Channel-3 Prescale Register (PWMCH3PR) .................................................. 228

Channel-3 Match Register (PWMCH3MR) .................................................... 229

Channel-3 Limit Register (PWMCH3LR) ...................................................... 229

Channel-3 Up-Down Mode Register (PWMCH3UDMR) ...................................... 230

Channel-3 Timer/Counter Mode Register (PWMCH3TCMR)............................... 230

Channel-3 PWM output Enable and External input Enable Register (PWMCH3PEEER)

231

Channel-3 Capture Mode Register (PWMCH3CMR) ......................................... 231

Channel-3 Capture Register (PWMCH3CR) .................................................. 231

Channel-3 Periodic Mode Register (PWMCH3PDMR) ....................................... 232

Channel-3 Dead Zone Enable Register (PWMCH3DZER) ................................... 232

Channel-3 Dead Zone Counter Register (PWMCH3DZCR) ................................. 233

21.11 Register map ............................................................................... 234

21.12 PWM Channel-4 Registers (Base address : 0x4000_5400) ........................... 235

Channel-4 interrupt register(PWMCH4IR) ................................................... 235

Channel-4 interrupt enable register(PWMCH4IER) ........................................ 235

Channel-4 interrupt clear register(PWMCH4ICR) .......................................... 236

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Channel-4 Timer/Counter Register (PWMCH4TCR) ........................................ 236

Channel-4 Prescale Counter Register (PWMCH4PCR) ..................................... 237

Channel-4 Prescale Register (PWMCH4PR) .................................................. 237

Channel-4 Match Register (PWMCH4MR) .................................................... 238

Channel-4 Limit Register (PWMCH4LR) ...................................................... 238

Channel-4 Up-Down Mode Register (PWMCH4UDMR) ...................................... 238

Channel-4 Timer/Counter Mode Register (PWMCH4TCMR)............................... 239

Channel-4 PWM output Enable and External input Enable Register (PWMCH4PEEER)

239

Channel-4 Capture Mode Register (PWMCH4CMR) ......................................... 240

Channel-4 Capture Register (PWMCH4CR) .................................................. 240

Channel-4 Periodic Mode Register (PWMCH4PDMR) ....................................... 241

Channel-4 Dead Zone Enable Register (PWMCH4DZER) ................................... 241

Channel-4 Dead Zone Counter Register (PWMCH4DZCR) ................................. 242

21.13 Register map ............................................................................... 243

21.14 PWM Channel-5 Registers (Base address : 0x4000_5500) ........................... 244

Channel-5 interrupt register(PWMCH5IR) ................................................... 244

Channel-5 interrupt enable register(PWMCH5IER) ........................................ 244

Channel-5 interrupt clear register(PWMCH5ICR) .......................................... 245

Channel-5 Timer/Counter Register (PWMCH5TCR) ........................................ 245

Channel-5 Prescale Counter Register (PWMCH5PCR) ..................................... 246

Channel-5 Prescale Register (PWMCH5PR) .................................................. 246

Channel-5 Match Register (PWMCH5MR) .................................................... 247

Channel-5 Limit Register (PWMCH5LR) ...................................................... 247

Channel-5 Up-Down Mode Register (PWMCH5UDMR) ...................................... 247

Channel-5 Timer/Counter Mode Register (PWMCH5TCMR)............................... 248

Channel-5 PWM output Enable and External input Enable Register (PWMCH5PEEER)

248

Channel-5 Capture Mode Register (PWMCH5CMR) ......................................... 249

Channel-5 Capture Register (PWMCH5CR) .................................................. 249

Channel-5 Periodic Mode Register (PWMCH5PDMR) ....................................... 250

Channel-5 Dead Zone Enable Register (PWMCH5DZER) ................................... 250

Channel-5 Dead Zone Counter Register (PWMCH5DZCR) ................................. 251

21.15 Register map ............................................................................... 252

21.16 PWM Channel-6 Registers (Base address : 0x4000_5600) ........................... 253

Channel-6 interrupt register(PWMCH6IR) ................................................... 253

Channel-6 interrupt enable register(PWMCH6IER) ........................................ 253

Channel-6 interrupt clear register(PWMCH6ICR) .......................................... 254

Channel-6 Timer/Counter Register (PWMCH6TCR) ........................................ 254

W7500x Reference Manual Version1.1.0 12 / 399

Channel-6 Prescale Counter Register (PWMCH6PCR) ..................................... 255

Channel-6 Prescale Register (PWMCH6PR) .................................................. 255

Channel-6 Match Register (PWMCH6MR) .................................................... 256

Channel-6 Limit Register (PWMCH6LR) ...................................................... 256

Channel-6 Up-Down Mode Register (PWMCH6UDMR) ...................................... 257

Channel-6 Timer/Counter Mode Register (PWMCH6TCMR)............................... 257

Channel-6 PWM output Enable and External input Enable Register (PWMCH6PEEER)

258

Channel-6 Capture Mode Register (PWMCH6CMR) ......................................... 258

Channel-6 Capture Register (PWMCH6CR) .................................................. 258

Channel-6 Periodic Mode Register (PWMCH6PDMR) ....................................... 259

Channel-6 Dead Zone Enable Register (PWMCH6DZER) ................................... 259

Channel-6 Dead Zone Counter Register (PWMCH6DZCR) ................................. 260

21.17 Register map ............................................................................... 261

21.18 PWM Channel-7 Registers (Base address : 0x4000_5700) ........................... 262

Channel-7 interrupt register(PWMCH7IR) ................................................... 262

Channel-7 interrupt enable register(PWMCH7IER) ........................................ 262

Channel-7 interrupt clear register(PWMCH7ICR) .......................................... 263

Channel-7 Timer/Counter Register (PWMCH7TCR) ........................................ 263

Channel-7 Prescale Counter Register (PWMCH7PCR) ..................................... 264

Channel-7 Prescale Register (PWMCH7PR) .................................................. 264

Channel-7 Match Register (PWMCH7MR) .................................................... 265

Channel-7 Limit Register (PWMCH7LR) ...................................................... 265

Channel-7 Up-Down Mode Register (PWMCH7UDMR) ...................................... 266

Channel-7 Timer/Counter Mode Register (PWMCH7TCMR)............................... 266

Channel-7 PWM output Enable and External input Enable Register (PWMCH7PEEER)

267

Channel-7 Capture Mode Register (PWMCH7CMR) ......................................... 267

Channel-7 Capture Register (PWMCH7CR) .................................................. 267

Channel-7 Periodic Mode Register (PWMCH7PDMR) ....................................... 268

Channel-7 Dead Zone Enable Register (PWMCH7DZER) ................................... 268

Channel-7 Dead Zone Counter Register (PWMCH7DZCR) ................................. 269

21.19 Register map ............................................................................... 270

21.20 PWM Common Registers (Base address : 0x4000_5800) ............................ 271

Interrupt Enable Register (IER) ............................................................... 271

Start/Stop Register (SSR) ...................................................................... 272

Pause Register (PSR) ............................................................................ 273

21.21 Register map ............................................................................... 274

22 Dual timers ........................................................................................... 275

W7500x Reference Manual Version1.1.0 13 / 399

22.1 Introduction ................................................................................ 275

22.2 Features .................................................................................... 275

22.3 Functional description ................................................................... 276

Clock and clock enable ........................................................................ 276

Timer size.... .................................................................................... 276

Prescaler.... ...................................................................................... 276

Repetition mode................................................................................. 276

Interrupt.... ...................................................................................... 277

Operation.... ..................................................................................... 277

How to set the dual timers .................................................................... 278

22.4 Dual timer0_0 Registers (Base address : 0x4000_1000) ............................ 279

Timer0_0 Load Register(DUALTIMER0_0TimerLoad) ....................................... 279

Timer0_0 Value Register(DUALTIMER0_0TimerValue) ..................................... 279

Timer0_0 Control Register(DUALTIMER0_0TimerControl) ................................ 279

Timer0_0 Interrupt Clear Register (DUALTIMER0_0TimerIntClr) ........................ 280

Timer0_0 Raw Interrupt Status Register (DUALTIMER0_0TimerRIS) .................... 280

Timer0_0 Masked Interrupt Status Register (DUALTIMER0_0TimerMIS) ................ 281

Timer0_0 Background Load Register (DUALTIMER0_0TimerBGLoad) ................... 281

22.5 Register map ............................................................................... 283

22.6 Dual timer0_1 Registers (Base address : 0x4000_1020) ............................ 284

Timer0_1 Load Register(DUALTIMER0_1TimerLoad) ....................................... 284

Timer0_1 Value Register(DUALTIMER0_1TimerValue) ..................................... 284

Timer0_1 Control Register(DUALTIMER0_1TimerControl) ................................ 284

Timer0_1 Interrupt Clear Register (DUALTIMER0_1TimerIntClr) ........................ 285

Timer0_1 Raw Interrupt Status Register (DUALTIMER0_1TimerRIS) .................... 285

Timer0_1 Masked Interrupt Status Register (DUALTIMER0_1TimerMIS) ................ 286

Timer0_1 Background Load Register (DUALTIMER0_1TimerBGLoad) ................... 286

22.7 Register map ............................................................................... 288

22.8 Dual Timer 0 Clock Enable Register (Base address : 0x4000_1080) .............. 289

Timer0_0 Clock Enable Register (TIMCLKEN0_0) .......................................... 289

Timer0_1 Clock Enable Register (TIMCLKEN0_1) .......................................... 289

22.9 Register map ............................................................................... 290

22.10 Dual timer1_0 Registers (Base address : 0x4000_2000) ............................ 291

Timer1_0 Load Register(DUALTIMER1_0TimerLoad) ....................................... 291

Timer1_0 Value Register(DUALTIMER1_0TimerValue) ..................................... 291

Timer1_0 Control Register(DUALTIMER1_0TimerControl) ................................ 291

Timer1_0 Interrupt Clear Register (DUALTIMER1_0TimerIntClr) ........................ 292

Timer1_0 Raw Interrupt Status Register (DUALTIMER1_0TimerRIS) .................... 292

Timer1_0 Masked Interrupt Status Register (DUALTIMER1_0TimerMIS) ................ 293

W7500x Reference Manual Version1.1.0 14 / 399

Timer1_0 Background Load Register (DUALTIMER1_0TimerBGLoad) ................... 293

22.11 Register map ............................................................................... 295

22.12 Dual timer1_1 Registers (Base address : 0x4000_2020) ............................ 296

Timer1_1 Load Register(DUALTIMER1_1TimerLoad) ....................................... 296

Timer1_1 Value Register(DUALTIMER1_1TimerValue) ..................................... 296

Timer1_1 Control Register(DUALTIMER1_1TimerControl) ................................ 296

Timer1_1 Interrupt Clear Register (DUALTIMER1_1TimerIntClr) ........................ 297

Timer1_1 Raw Interrupt Status Register (DUALTIMER1_1TimerRIS) .................... 297

Timer1_1 Masked Interrupt Status Register (DUALTIMER1_1TimerMIS) ................ 298

Timer1_1 Background Load Register (DUALTIMER1_1TimerBGLoad) ................... 298

22.13 Register map ............................................................................... 300

22.14 Dual Timer 1 Clock Enable Register (Base address : 0x4000_2080) .............. 301

Timer1_0 Clock Enable Register (TIMCLKEN1_0) .......................................... 301

Timer1_1 Clock Enable Register (TIMCLKEN1_1) .......................................... 301

22.15 Register map ............................................................................... 302

23 Watchdog timer ...................................................................................... 302

23.1 Introduction ................................................................................ 302

23.2 Features .................................................................................... 302

23.3 Functional description ................................................................... 302

Clock........ ...................................................................................... 302

Interrupt and reset request ................................................................... 303

23.4 Watchdog timer Registers (Base address : 0x4000_0000) .......................... 303

Watchdog timer Load Register(WDTLoad) .................................................. 303

Watchdog timer Value Register(WDTValue) ................................................ 304

Watchdog timer Control Register(WDTControl) ............................................ 304

Watchdog timer Interrupt Clear Register (WDTIntClr) .................................... 304

Watchdog timer Raw Interrupt Status Register (WDTRIS) ................................ 305

Watchdog timer Masked Interrupt Status Register (WDTMIS) ........................... 305

Watchdog timer Lock Register(WDTLock) ................................................... 306

23.5 Register map ............................................................................... 307

24 Real-time Clock(RTC) ............................................................................... 307

24.1 Introduction ................................................................................ 307

24.2 Features .................................................................................... 307

24.3 Functional description ................................................................... 307

RTC clock.... ..................................................................................... 308

RTC interrupt .................................................................................... 308

RTC Counter and Calendar .................................................................... 308

RTC Setting flow ................................................................................ 309

24.4 RTC Registers (Base Address : 0x4000_E000) ......................................... 310

W7500x Reference Manual Version1.1.0 15 / 399

RTC control register (RTCCON) ............................................................... 310

RTC Interrupt Mask register (RTCINTE) ...................................................... 311

RTC Interrupt Pending register (RTCINTP) .................................................. 313

RTC Alarm Mask register (RTCAMR) .......................................................... 314

RTC BCD Second register (BCDSEC) .......................................................... 315

RTC BCD Minute register (BCDMIN)........................................................... 315

RTC BCD Hour register (BCDHOUR) .......................................................... 315

RTC BCD Day register (BCDDAY) .............................................................. 316

RTC BCD Date register (BCDDATE) ........................................................... 316

RTC BCD Month register (BCDMON) .......................................................... 316

RTC BCD Year register (BCDYEAR) ............................................................ 317

RTC Predetermining Second register (PRESEC) ............................................ 317

RTC Predetermining Minute register (PREMIN) ............................................. 317

RTC Predetermining Hour register (PREHOUR) ............................................. 318

RTC Predetermining Day register (PREDAY) ................................................ 318

RTC Predetermining Date register (PREDATE) .............................................. 318

RTC Predetermining Month register (PREMON) ............................................ 319

RTC Predetermining Year register (PREYEAR) .............................................. 319

RTC Consolidated Time0 register (RTCTIME0) .............................................. 319

RTC Consolidated Time1 register (RTCTIME1) .............................................. 320

24.5 Register map ............................................................................... 321

25 UART(Universal Asynchronous Receive Transmit) ............................................ 322

25.1 Introduction ................................................................................ 322

25.2 Features .................................................................................... 322

25.3 Functional description ................................................................... 323

Baud rate calculation .......................................................................... 325

Data transmission ............................................................................... 326

Data receive ..................................................................................... 326

Hardware flow control ......................................................................... 327

25.4 UART0 Registers(Base address: 0x4000_C000) ....................................... 328

UART0DR (UART0 Data Register) ............................................................. 328

UART0RSR/ECR (UART0 Receive Status Register/Error Clear Register) ................ 329

UART0FR (UART0 Flag Register) .............................................................. 330

UART0ILPR (UART0 IrDA Low-Power Counter Register) ................................... 331

UART0IBRD (UART0 Integer Baud Rate Register) .......................................... 332

UART0FBRD (UART0 Fractional Baud Rate Register) ...................................... 332

UART0LCR_H (UART0 Line Control Register) ............................................... 333

UART0CR (UART0 Control register) .......................................................... 334

UART0IFLS (UART0 Interrupt FIFO Level Select Register) ................................ 336

W7500x Reference Manual Version1.1.0 16 / 399

UART0IMSC (UART0 Interrupt Mask Set/Clear Register) .................................. 336

UART0RIS (UART0 Raw Interrupt Status Register) ......................................... 338

UART0MIS (UART0 Masked Interrupt Status Register) ..................................... 339

UART0ICR (UART0 Interrupt Clear Register) ................................................ 340

25.5 Register map ............................................................................... 341

25.6 UART1 Registers(Base address: 0x4000_D000) ....................................... 342

UART1DR (UART1 Data Register) ............................................................. 342

UART1RSR/ECR (UART1 Receive Status Register/Error Clear Register) ................ 342

UART1FR (UART1 Flag Register) .............................................................. 343

UART1ILPR (UART1 IrDA Low-Power Counter Register) ................................... 344

UART1IBRD (UART1 Integer Baud Rate Register) .......................................... 345

UART1FBRD (UART1 Fractional Baud Rate Register) ...................................... 345

UART1LCR_H (UART1 Line Control Register) ............................................... 346

UART1CR (UART1 Control register) .......................................................... 347

UART1IFLS (UART1 Interrupt FIFO Level Select Register) ................................ 349

UART1IMSC (UART1 Interrupt Mask Set/Clear Register) .................................. 349

UART1RIS (UART1 Raw Interrupt Status Register) ......................................... 351

UART1MIS (UART1 Masked Interrupt Status Register) ..................................... 352

UART1ICR (UART1 Interrupt Clear Register) ................................................ 353

25.7 Register map ............................................................................... 354

26 Universal Asynchronous Receive Transmit(UART2) .......................................... 355

26.1 Introduction ................................................................................ 355

26.2 Feature ...................................................................................... 355

26.3 Functional description ................................................................... 355

Baud rate calculation .......................................................................... 355

26.4 UART2 Registers(Base address: 0x4000_6000) ....................................... 357

UART2DR (UART2 Data Register) ............................................................. 357

UART2SR (UART2 Status Register) ............................................................ 357

UART2CR (UART2 Control Register) .......................................................... 358

UART2ISR/ICR (UART2 Interrupt Status/Interrupt Clear Register) ..................... 358

UART2BDR (UART2 Baud Rate Divider Register) ........................................... 359

26.5 Register map ............................................................................... 360

27 Synchronous Serial Port (SSP) .................................................................... 361

27.1 Introduction ................................................................................ 361

27.2 Features .................................................................................... 361

27.3 Functional description ................................................................... 362

Clock prescaler .................................................................................. 362

Transmit FIFO .................................................................................... 362

Receive FIFO ..................................................................................... 363

W7500x Reference Manual Version1.1.0 17 / 399

Interrupt generation logic ..................................................................... 363

DMA interface .................................................................................... 363

Interface reset ................................................................................... 365

Configuring the SSP ............................................................................. 365

Enable PrimeCell SSP operation .............................................................. 366

Clock ratios ...................................................................................... 366

Programming the SSPCR0 Control Register ................................................. 367

Programming the SSPCR1 Control Register ................................................. 367

Frame format .................................................................................... 368

Texas Instruments synchronous serial frame format ...................................... 369

Motorola SPI frame format .................................................................... 370

National Semiconductor Microwire frame format ......................................... 376

Master and Slave configurations .............................................................. 378

SSP Flow chart ................................................................................... 379

27.4 SSP0 Registers (Base Address : 0x4000_A000) ........................................ 380

SSP0 Control register 0 (SSP0CR0) ........................................................... 380

SSP0 Control register 1 (SSP0CR1) ........................................................... 382

SSP0 Data register (SSP0DR)................................................................... 382

SSP0 Status register (SSP0SR) ................................................................. 383

SSP0 Clock prescale register (SSP0CPSR) ................................................... 384

SSP0 Interrupt mask set or clear register (SSP0IMSC) .................................... 384

SSP0 Raw interrupt status register (SSP0RIS) .............................................. 385

SSP0 Masked interrupt status register, (SSP0MIS).......................................... 385

SSP0 Interrupt clear register (SSP0ICR) ..................................................... 386

SSP0 DMA control register, (SSP0DMACR) ................................................... 386

27.5 Register map ............................................................................... 388

27.6 SSP1 Registers (Base Address : 0x4000_B000) ........................................ 389

SSP1 Control register 0 (SSP1CR0) ........................................................... 389

SSP1 Control register 1 (SSP1CR1) ........................................................... 390

SSP1 Data register (SSP1DR)................................................................... 392

SSP1 Status register (SSP1SR) ................................................................. 392

SSP1 Clock prescale register (SSP1CPSR) ................................................... 393

SSP1 Interrupt mask set or clear register (SSP1IMSC) .................................... 393

SSP1 Raw interrupt status register (SSP1RIS) .............................................. 394

SSP1 Masked interrupt status register, (SSP1MIS).......................................... 394

SSP1 Interrupt clear register (SSP1ICR) ..................................................... 395

SSP1 DMA control register, (SSP1DMACR) ................................................... 395

27.7 Register map ............................................................................... 397

Document History Information ....................................................................... 398

W7500x Reference Manual Version1.1.0 18 / 399

2 List of table

Table 1 W7500x interrupt vector table ....................................................... 29

Table 2 W7500x sleep mode summary ........................................................ 32

Table 3 operation of mode selection .......................................................... 36

Table 4 description of Flash memory .......................................................... 37

Table 5 CRG register map and reset values .................................................. 67

Table 6. Offset Address for Common Register ............................................... 70

Table 7. Offset Address in Socket n Register Block ......................................... 71

Table 8 RNG register map and reset values ............................................... 114

Table 9 functional description table ......................................................... 114

Table 10 AFC register map and reset values ................................................ 144

Table 11 EXTINT register map and reset values ............................................ 149

Table 12 PAD controller register map and reset values ................................... 152

Table 13 GPIO register map and reset values ............................................... 163

Table 14 Summary of the DMA requests for each channel ................................ 165

Table 15 DMA register map and reset values ................................................ 179

Table 16 ADC register map and reset values ................................................ 187

Table 17 PWM channel 0 register map and reset values .................................. 207

Table 18 PWM channel 1 register map and reset values .................................. 216

Table 19 PWM channel 2 register map and reset values .................................. 225

Table 20 PWM channel 3 register map and reset values .................................. 234

Table 21 PWM channel 4 register map and reset values .................................. 243

Table 22 PWM channel 5 register map and reset values .................................. 252

Table 23 PWM channel 6 register map and reset values .................................. 261

Table 24 PWM channel 7 register map and reset values .................................. 270

Table 25 PWM common register map and reset values .................................... 274

Table 26 Dual timer 0_0 register map and reset values .................................. 283

Table 27 Dual timer 0_1 register map and reset values .................................. 288

Table 28 Dual timer 0 clock enable register map and reset values ..................... 290

Table 29 Dual timer 1_0 register map and reset values .................................. 295

Table 30 Dual timer 1_1 register map and reset values .................................. 300

Table 31 Dual timer 1 clock enable register map and reset values ..................... 302

Table 32 Watchdog Timer register map and reset values ................................. 307

Table 33 RTC register map and reset values ................................................ 321

Table 34 UART0 register map and reset values ............................................. 341

Table 35 UART1 register map and reset values ............................................. 354

Table 36 UART2 register map and reset values ............................................. 360

Table 37 DMA trigger points for the transmit and receive FIFOs. ....................... 364

W7500x Reference Manual Version1.1.0 19 / 399

Table 38 SSP0 register map and reset values ............................................... 388

Table 39 SSP1 register map and reset values ............................................... 397

W7500x Reference Manual Version1.1.0 20 / 399

3 List of figures

Figure 1. W7500x System Architecture ....................................................... 26

Figure 2 W7500x memory map ................................................................. 28

Figure 3. operation of boot code .............................................................. 36

Figure 4 CRG block diagram .................................................................... 41

Figure 5 Typical application with an 8 MHz crystal ......................................... 42

Figure 6 TOE block diagram ..................................................................... 68

Figure 7. Register & Memory Organization ................................................... 69

Figure 8. Random Number Generator block diagram...................................... 109

Figure 9. Flow chart of RNG operation ...................................................... 110

Figure 10. External Interrupt diagram ....................................................... 148

Figure 11. function schematic of digital I/O pad .......................................... 150

Figure 12. function schematic of digital/analog mux IO pad ............................ 150

Figure 13. GPIO block diagram ................................................................ 153

Figure 17. GPIO Flow chart .................................................................... 154

Figure 18. MASK LOWBYTE access ............................................................ 155

Figure 19 MASK HIGHBYTE access ............................................................. 155

Figure 17. DMA Block diagram ................................................................. 164

Figure 18. DMA ping pong cycle ............................................................... 168

Figure 19. ADC block diagram ................................................................. 181

Figure 20. The ADC operation flowchart with non-interrupt ............................. 182

Figure 21. The ADC operation flowchart with interrupt .................................. 183

Figure 22 PWM block diagram ................................................................. 189

Figure 23 Periodic mode ........................................................................ 190

Figure 24 one-shot mode ....................................................................... 190

Figure 25 Up-count mode ...................................................................... 190

Figure 26 Down-count mode ................................................................... 190

Figure 27 Counter mode with rising edge ................................................... 191

Figure 28 Counter mode with falling edge .................................................. 191

Figure 29 Counter mode with rising and falling edge ..................................... 192

Figure 30 Timer/Counter timing diagram with match interrupt ........................ 192

Figure 31 Timer/Counter timing diagram with overflow interrupt ..................... 193

Figure 32 The PWM output up to match register ........................................... 194

Figure 33 The PWM output up to limit register ............................................. 194

Figure 34 PWM waveform with dead zone time ............................................ 195

Figure 35 PWM waveform with dead zone counter ........................................ 196

Figure 36 Capture event with no interrupt clear .......................................... 196

Figure 37 Capture event with interrupt clear .............................................. 197

W7500x Reference Manual Version1.1.0 21 / 399

Figure 38 The PWM setting flow .............................................................. 198

Figure 39 Block diagram of Dualtimer ....................................................... 275

Figure 40 The Dual timer setting flow ....................................................... 278

Figure 41 Watchdog timer operation flow diagram ........................................ 303

Figure 42. RTC block diagram ................................................................. 308

Figure 43. RTC setting flow for Counter Function ......................................... 309

Figure 44. RTC setting flow for Alarm function ............................................ 310

Figure 45. UART0,1 Block diagram ............................................................ 323

Figure 46. UART character frame ............................................................. 324

Figure 47. UART divider flow chart ........................................................... 325

Figure 48. UART Initial setting flow chart ................................................... 325

Figure 49. Transmit and Receive data flow chart .......................................... 326

Figure 50. Hardware flow control description .............................................. 327

Figure 51. CTS Functional Timing ............................................................. 327

Figure 52. Algorithm for setting CTS/RTS flowchart ...................................... 328

Figure 53. UART2 divider flow chart ......................................................... 355

Figure 54. UART2 Initial setting flow chart ................................................. 356

Figure 55. SSP block diagram .................................................................. 362

Figure 56. DMA transfer waveforms .......................................................... 365

Figure 57. Texas Instruments synchronous serial, single transfer ....................... 369

Figure 58. Texas Instruments synchronous serial, continuous transfers ............... 370

Figure 59 Motorola SPI, single transfer, SPO=0 and SPH=0 ............................... 371

Figure 60 Motorola SPI, continuous transfers, SPO=0 and SPH=0 ....................... 371

Figure 61 Motorola SPI, single & continuous transfers, SPO=0 and SPH=1 ............. 372

Figure 62 Motorola SPI, single transfer, with SPO=1 and SPH=0 ......................... 373

Figure 63. Motorola SPI, continuous transfers, SPO=1 and SPH=0....................... 374

Figure 64. Motorola SPI, single & continuous transfers, SPO=1 and SPH=1 ............ 375

Figure 65. National Semiconductor Microwire, single transfer .......................... 376

Figure 66. National Semiconductor Microwire, continuous transfers ................... 378

Figure 67. PrimeCell SSP master coupled to an SPI slave ................................. 378

Figure 68. SPI master coupled to a PrimeCell SSP slave .................................. 379

Figure 69. how to setting TI or Microwire mode flow chart .............................. 379

Figure 70. how to setting SPI mode flow chart ............................................. 380

W7500x Reference Manual Version1.1.0 22 / 399

4 Documentation conventions

ARP

Address Resolution Protocol

AHB

Advanced High-performance Bus

AMBA

Advanced Microcontroller Bus Architecture

APB

Advanced Peripheral Bus

AFC

Alternate Function Controller

ADC

Analog-to-Digital Converter

BOD

BrownOut Detection

CPU

Central Processing Unit

CRG

Clock Reset generator

DMA

Direct Memory Access

EOP

End Of Packet

EXTINT

External Interrupt

GPIO

General Purpose Input/Output

IrDA

Infrared Data Association

I/O

Input/Output

ICMP

Internet Control Message Protocol

IGMP

Internet Group Management Protocol

IPv4

Internet Protocol version 4

IRQ

interrupt request

NMI

NonMaskable Interrupt

PADCON

Pad Controller

PLL

Phase-Locked Loop

PHY

Physical Layer

PPPoE

Point-to-Point Protocol over Ethernet

POR

Power Of Reset

PWM

Pulse Width Modulator

RAM

Random Access Memory

RNG

Random number generator

SR

Status Register

SSP

Synchronous Serial Port

4.1 Glossary

W7500x Reference Manual Version1.1.0 23 / 399

SYSCFG

System configuration controller

TOE

TCPIPCore Offload Engine

TTL

Transistor-Transistor Logic

TCP

Transmission Control Protocol

UART

Universal Asynchronous Receiver/Transmitter

USB

Universal Serial Bus

UDP

User Datagram Protocol

WOL

Wake On Lan

WDT

Watchdog Timer

W7500x Reference Manual Version1.1.0 24 / 399

Key

Bit Accessibility

rw

Read/Write

r

Read Only

r0

Read as 0

r1

Read as 1

W

Write Only

4.2 Register Bit Conventions

Each register is shown with a key indicating the accessibility of the each individual bit, and the

initial condition:

W7500x Reference Manual Version1.1.0 25 / 399

5 System and memory overview

5.1 System architecture

Main system consists of :

 Three masters :

- Cortex-M0 core

- TCP/IP Offload Engine

- uDMAC (PL230, 6channel)

 Ten slaves :

- Internal BOOT ROM

- Internal SRAM

- Internal Flash memory

- Two AHB2APB bridge which connects all APB peripherals

- Four AHB dedicated to 16bit GPIOs

- TCPIP Hardware core

 Ethernet :

- IP101G

System architecture and AHB-Lite bus architecture shown in Figure 1.

Figure 1. W7500x System Architecture

W7500x Reference Manual Version1.1.0 26 / 399

AHB-Lite BUS

- This bus connects the Three masters (Cortex-M0 and uDMAC and TCP/IP

Offload Engine) and ten AHB slaves.

Two APB BUSs

- These buses connect Seventeen APB peripherals (Watchdog, two Dual timers,

PWM, two UARTs, simple UART, two I2Cs, two SSPs, Random Number Generator,

Real Time Clock, 12bits Analog Digital Converter, Clock Controller, IO

Configuration, PAD MUX controller)

5.2 Memory organization

Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear

4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word

is considered the word’s least significant byte and the highest numbered byte the most

significant.

W7500x Reference Manual Version1.1.0 27 / 399

Memory map

Figure 2 W7500x memory map

W7500x Reference Manual Version1.1.0 28 / 399

6 System configuration controller (SYSCFG)

Priority

Type of

priority

Exception

type

Device

Description

Address

-3

fixed

Reset

CM0

Reset

0x0000_0004

-2

fixed

NMI

Watchdog

Watchdog interrupt

0x0000_0008

-1

Fixed

HardFault

CM0

All class of fault

0x0000_000C

3

Settable

SVCall

CM0

System service call via SWI instruction

0x0000_002C

5

settable

PendSV

CM0

Pendable request for system service

0x0000_0038

6

settable

SysTick

CM0

System tick timer

0x0000_003C

Main purposes of the system configuration controller are the following

 Control of the memory remap feature
 The ability to enable an automatic reset if the system locks up
 Information about the cause of the last reset

7 Interrupt and events

7.1 Nested vectored interrupt controller (NVIC)

NVIC main features

 32 maskable interrupt channels (not including the sixteen Cortex® -M0 interrupt lines)
 4 programmable priority levels (2 bits of interrupt priority are used)
 Low-latency exception and interrupt handling
 Power management control
 Implementation of System Control Registers

The NVIC and the processor core interface are closely coupled, which enables low latency

interrupt processing and efficient processing of late arriving interrupts. All interrupts including

the core exceptions are managed by the NVIC.

SysTick calibration value register

The SysTick calibration value is set to 6000, which gives a reference time base of 1 ms with

the SysTick clock set to 6 MHz (max f

HCLK

/8).

Interrupt and exception vectors

Table 1 describes the W7500x interrupt vector table.

Table 1 W7500x interrupt vector table

W7500x Reference Manual Version1.1.0 29 / 399

7

settable

IRQ[0]

SSP0

SSP0 global interrupt

0x0000_0040

8

Settable

IRQ[1]

SSP1

SSP1 global interrupt

0x0000_0044

9

Settable

IRQ[2]

UART0

UART0 global interrupt

0x0000_0048

10

Settable

IRQ[3]

UART1

UART1 global interrupt

0x0000_004C

11

Settable

IRQ[4]

UART2

UART2 global interrupt

0x0000_0050

12

Settable

IRQ[5]

reserved

0x0000_0054

13

Settable

IRQ[6]

reserved

0x0000_0058

14

Settable

IRQ[7]

GPIO0

GPIOA global interrupt

0x0000_005C

15

Settable

IRQ[8]

GPIO1

GPIOB global interrupt

0x0000_0060

16

Settable

IRQ[9]

GPIO2

GPIOC global interrupt

0x0000_0064

17

Settable

IRQ[10]

GPIO3

GPIOD global interrupt

0x0000_0068

18

Settable

IRQ[11]

DMA

DMA interrupt

0x0000_006C

19

Settable

IRQ[12]

Dualtimer0

Dualtimer0 global interrupt

0x0000_0070

20

Settable

IRQ[13]

Dualtimer1

Dualtimer1 global interrupt

0x0000_0074

21

Settable

IRQ[14]

PWM0

PWM0 global interrupt

0x0000_0078

22

Settable

IRQ[15]

PWM1

PWM1 global interrupt

0x0000_007C

23

Settable

IRQ[16]

PWM2

PWM2 global interrupt

0x0000_0080

24

Settable

IRQ[17]

PWM3

PWM3 global interrupt

0x0000_0084

25

Settable

IRQ[18]

PWM4

PWM4 global interrupt

0x0000_0088

26

Settable

IRQ[19]

PWM5

PWM5 global interrupt

0x0000_008C

27

Settable

IRQ[20]

PWM6

PWM6 global interrupt

0x0000_0090

28

Settable

IRQ[21]

PWM7

PWM7 global interrupt

0x0000_0094

29

Settable

IRQ[22]

RTC

RTC interrupt

0x0000_0098

30

Settable

IRQ[23]

ADC

ADC acquisition end interrupt

0x0000_009C

31

Settable

IRQ[24]

TCPIP

TCPIP global interrupt

0x0000_00A0

32

Settable

IRQ[25]

EXT_INT

External pin interrupt

0x0000_00A4

33

Settable

IRQ[26]

reserved

0x0000_00A8

34

Settable

IRQ[27]

reserved

0x0000_00AC

35

Settable

IRQ[28]

reserved

0x0000_00B0

36

Settable

IRQ[29]

reserved

0x0000_00B4

37

Settable

IRQ[30]

reserved

0x0000_00B8

38

Settable

IRQ[31]

reserved

0x0000_00BC

7.2 Event

W7500x is able to handle internal events in order to wake up the core(WFE). The wakeup event

can be generated by

W7500x Reference Manual Version1.1.0 30 / 399

 When after DMA process finished (DMA_DONE)

8 Power supply

8.1 Introduction

W7500x embeds a voltage regulator in order to supply the internal 1.5V digital power domain.

 Require a 2.7V ~ 5.5V operating supply voltage (VDD)
 ADC ref voltage is same as VDD

8.2 Voltage regulator

The voltage regulator is always enabled after Reset and works in only one mode.

 In Run mode, the regulator supplies full power to the 1.5V domain.
 There is no power down or sleep mode

8.3 Low-power modes

W7500x is in RUN mode after a system or power reset. There are two low power modes to save

power when the CPU does not need to be kept running. These modes are useful for instances

like when the CPU is waiting for an external interrupt. Please note that there is no power-off

mode for W7500x.

The device features two low-power modes:

 Sleep mode
 Deep Sleep mode

Additionally, the power consumption can be reducing by following method:

 User can slow down the system clocks
 User can gate the clocks to the peripherals when they are unused.

W7500x Reference Manual Version1.1.0 31 / 399

Sleep mode

Mode

Entry

Wakeup

Effect on clocks

Sleep mode

DEEPSLEEP = 0

Enable WFI

Any interrupt

CPU clock OFF

APB Bus Clock ON

AHB Bus clock ON

Memory clocks ON

DEEPSLEEP = 0

Enable WFE

Wakeup event

Deep Sleep mode
DEEPSLEEP = 1

Enable WFI

Any interrupt

CPU clock OFF

APB Bus Clock OFF

AHB Bus clock OFF

Memory clocks OFF

DEEPSLEEP = 1

Enable WFE

Wakeup event

W7500x has two kinds of sleep modes. One is Sleep mode and the other is Deep sleep mode.

Two of them are almost the same except the clock gated peripherals kinds. Table 2 shows the

Sleep mode summary.

Table 2 W7500x sleep mode summary

Peripheral clock gating

In Run mode, individual clocks can be stopped at any time to reduce power.

Peripheral clock gating is controlled by the CRG block.

Below is the list of clocks which can be gating in CRG block.

 ADC clock (ADCCLK)
 SSP0, SSP1 clock (SSPCLK)
 UART0, UART1 clock (UARTCLK)
 Two Timer clocks (TIMCLK0, TIMCLK1)
 8ea PWM clocks (PWMCLK0 ~ PWMCLK7)
 WDOG clock (WDOGCLK)
 Random number generator clock (RNGCLK)

W7500x Reference Manual Version1.1.0 32 / 399

9 System tick timer

9.1 Introduction

System tick timer(SysTick) is part of the ARM Cortex-M0 core

9.2 Features

Simple 24bit timer. Clocked internally by the system clock.

9.3 Functional description

The SysTick timer is an integral part of Cortex-M0. The SysTick timer is intended to generated

a fixed 10 millisecond interrupt for use by an operating system or other system management

software.

Since the SysTick timer is a part of the Cortex-M0, it facilitates porting of software by

providing a standard timer that is available on Cortex-M0 based devices. The SysTick

timer can be used for :

 An RTOS tick timer which fires at a programmable rate (for example 100 Hz) and

invokes a SysTick routine.

 A high-speed alarm timer using the core clock.
 A simple counter. Software can use this to measure time to completion and time used.
 An internal clock source control based on missing/meeting durations. The

COUNTFLAG bit-field in the control and status register can be used to determine if

an action completed within a set duration, as part of a dynamic clock management

control loop.

W7500x Reference Manual Version1.1.0 33 / 399

9.4 Registers (Base : 0xE000_E000)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

CNTFLAG

R

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

res

res

res

res

res

res

TICKINT

ENABLE

R/W

R/W

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

RELOAD[23:16]

R

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

RELOAD[15:0]

R

System Timer control and status register (SYST_CSR)

Address Offset : 0x010

Reset value : 0x0000_0000

[0] ENABLE – Enables the counter

0 : Counter disabled

1 : Counter enabled

[1] TICKINT – Enables SysTick exception request

O : Counting down to zero does not assert the SysTick exception request

1 : Counting down to zero to asserts the SysTick exception request

[16] COUNTFLAG – Returns 1 if timer counted to 0 since the last read of this register.

SysTick Reload Value Register (SYST_RVR)

Address Offset : 0x014

Reset value : 0x0000_0000

[23:0] RELOAD – Value to load into the SYST_CVR when the counter is enabled and

when it reaches 0

- The RELOAD value can be any value in the range 0x0000_0001 –

0x00FFFFFF. You can program a value of 0, but this has no effect because

the SysTick exception request and COUNTFLAG are activated when count

from 1 to 0.

W7500x Reference Manual Version1.1.0 34 / 399

- To generate a multi-short timer with a period of N processor clock cycles,

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

CURRENT[23:16]

R/W

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

CURRENT [15:0]

R/W

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

NORF

SKEW

res

res

res

res

res

res

TENMS[23:16]

R R

R

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

TENMS [15:0]

R

use a RELOAD value of N-1. For example, if the SysTick interrupt is

required every 100 clock pulses, set RELOAD to 99.

SysTick Current Value Register (SYST_CVR)

Address Offset : 0x018

Reset value : 0x0000_0000

[23:0] CURRENT – Reads return the current value of the SysTick counter.

A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG

bit to 0.

SysTick Calibration Value Register (SYST_CALIB)

Address Offset : 0x01C

Reset value : 0x0000_0000

[23:0] TENMS - Reads as zero. Indicates calibration value is not known.

[30] SKEW - Reads as one. Calibration value for the 10ms inexact timing is not known

because TENMS is not known. This can affect the suitability of SysTick as a software

real time clock.

[31] NOREF - Reads as one. Indicates that no separate reference clock is provided.

W7500x Reference Manual Version1.1.0 35 / 399

10 Booting Sequence

Mode

selection

Mode

Aliasing

TEST

BOOT 0 0

APP

User code execute in Main Flash memory.

0 1 ISP

In this mode,W7500x can support ISP function in order to control

flash using serial interface.

H/W reset

Boot

Mode Run ISP

ISP

Run Application

APP

W7500x has three different boot modes that can be selected through the BOOT pin and TEST

pin as shown in Table 3.

Table 3 operation of mode selection

When W7500x is reset by hardware, it will be operated as below in embedded boot code.

Figure 3. operation of boot code

W7500x Reference Manual Version1.1.0 36 / 399

11 Embedded Flash memory

Flash area

Flash memory address

Size

(bytes)

Name

Description

Main Flash

memory

0x0000 0000 ~ 0x0000 00FF

256

Sector 0

Block 0

0x0000 0100 ~ 0x0000 01FF

256

Sector 1

0x0000 0200 ~ 0x0000 02FF

256

Sector 2

0x0000 0300 ~ 0x0000 03FF

256

Sector 3

. . .

. . . . . . . . .

0x0000 7000 ~ 0x0000 70FF

256

Sector112

Block 7

0x0000 7100 ~ 0x0000 71FF

256

Sector113

0x0000 7200 ~ 0x0000 72FF

256

Sector114

0x0000 7300 ~ 0x0000 73FF

256

Sector115

. . .

. . . . . . . . .

0x0001 FC00 ~ 0x0001 FCFF

256

Sector509

Block 32

11.1 Flash main features

 Up to 128Kbytes of Flash memory
 Memory organization:

 Main Flash memory block:

Up to 128Kbytes

 Information block:

Up to 512bytes

Information block is read only

 Data block:

Up to 512bytes

 Flash memory interface features:

 Read interface with prefetch buffer( 1 x 32-bit words )
 Flash Program / Erase operation

11.2 Flash memory organization

The Flash memory is organized of 32-bit wide memory cells that can be used for storing both

code and data constants.

The memory organization is based on a main Flash memory block containing 512 sectors of

256byte or 32 blocks of 4Kbyte.

Table 4 description of Flash memory

W7500x Reference Manual Version1.1.0 37 / 399

0x0001 FD00 ~ 0x0001 FDFF

256

Sector510

0x0001 FE00 ~ 0x0001 FEFF

256

Sector511

0x0001 FF00 ~ 0x0001 FFFF

256

Sector512

Information

block

0x0003 FC00 ~ 0x0003 FCFF

256

Lock info

0x0003 FD00 ~ 0x0003 FDFF

Reserved

Data block

0x0003 FE00 ~ 0x0003 FEFF

256 Data0

0x0003 FF00 ~ 0x0003 FFFF

256 Data1

The W7500 embedded Flash memory can be programmed using in-application programming.

IAP allows the user to re-program the Flash memory while the application is running. The

program and erase operations can be performed over the whole product voltage range.

In

W7500x_Library_Examples(https://github.com/Wiznet/W7500/tree/master/W7500x_Library

_Examples/Projects/Peripheral_Examples/Flash/IAP_Example), there is the IAP Example

Project and the below function is supported to use IAP.

void DO_IAP( uint32_t id, uint32_t dst_addr, uint8_t* src_addr, uint32_t size);

This function requests those parameters, id, dst_addr, src_addr and size. 'id' is already defined

in 'main.c'. 'dst_addr' is the flash memory address in the upper table. 'src_addr' is the buffer

pointer user want to program. 'size' is the flash size user chooses. Please refer flash address

and size mentioned in the upper table.

// IAP 'id' paremeter define

#define IAP_ENTRY 0x1FFF1001 // Because Thum code

#define IAP_ERAS 0x010

#define IAP_ERAS_DAT0 (IAP_ERAS + 0) // Erase Data 0 block

#define IAP_ERAS_DAT1 (IAP_ERAS + 1) // Erase Data 1 block

#define IAP_ERAS_SECT (IAP_ERAS + 2) // Erase a Sector in Main Flash Memory

#define IAP_ERAS_BLCK (IAP_ERAS + 3) // Erase a Block in Main Flash Memory

#define IAP_ERAS_CHIP (IAP_ERAS + 4) // Erase all code

W7500x Reference Manual Version1.1.0 38 / 399

#define IAP_ERAS_MASS (IAP_ERAS + 5) // Erase all code & data

#define IAP_PROG 0x022

This is how to Erase and Program flash memory. Especially, with IAP_ERAS_DAT0 and

IAP_ERAS_DAT1, there is no need to put other parameters (there are default values).

// Step 1 DATA0 Erase, Read, Write Test

DO_IAP(IAP_ERAS_DAT0,0,0,0);

DO_IAP(IAP_PROG,DAT0_START_ADDR,buffer,SECT_SIZE);

Operating program can be deleted when user use 'IAP_ERAS_CHIP' or 'IAP_ERAS_MASS'.

// Using IAP_ERAS_CHIP or IAP_ERAS_MASS

DO_IAP(IAP_ERAS_CHIP,0,0,0);

DO_IAP(IAP_ERAS_MASS,0,0,0);

12 Clock Reset generator (CRG)

12.1 Introduction

CRG is clock reset generator block for W7500x System. It provides every clock/reset for all

other block include CPU and peripherals. CRG includes PLL and POR.

12.2 Features

Reset

• Three types of reset – external reset, Power reset, system reset

• External reset is generated by low level on the RSTn pin (external reset)

• Power reset is generated by Power-on reset (POR)

• Power on reset is generated by POR

• System reset is generated when one of the following events occurs

 Watchdog event

W7500x Reference Manual Version1.1.0 39 / 399

 After remapping
 Software reset (SYSRESETREQ bit in Cortex-M0. Refer to the Cortex-M0 technical

reference manual for more detail)

• Power reset sets all registers to their reset values.

• System reset sets all registers to their reset values except the CRG block registers and

remap register to protect remap value

Clock

Two clock sources can be used to drive the system clock.

 External oscillator clock (8MHz ~ 24MHz) (OCLK)
 Internal 8MHz RC oscillator clock (RCLK)

One additional clock source

 32.768KHz low speed external crystal which derives the real time clock.

There is a PLL

One PLL is integrated

 Input clock range is from 8MHz to 24MHz
 Frequency can be generated by M/N/OD registers. (refer register description)
 Bypass option enabled

There are many generated clocks for independent operating with system clock

 System clock (FCLK)
 ADC clock (ADCCLK)
 SSP0, SSP1 clock (SSPCLK)
 UART0, UART1 clock (UARTCLK)
 Two Timer clocks (TIMCLK0, TIMCLK1)
 8ea PWM clocks (PWMCLK0 - PWMCLK7)
 Real time clock (RTCCLK)
 WDOG clock (WDOGCLK)
 Random number generator clock (RNGCLK)

RNGCLK have only one source (pll output) and no prescaler

Some of the generated clocks turn off automatically when CPU enters sleep mode.

 ADCCLK, RNGCLK

Generate two Hardware TCPIP Clocks (MII_RXC, MII_TXC) are from external PADs.

Hardware TCPIP Clocks can be gated by register control.

All clocks generated from CRG can be monitored.

W7500x Reference Manual Version1.1.0 40 / 399

12.3 Functional description

Figure 4 shows the CRG block diagram.

Figure 4 CRG block diagram

External Oscillator Clock

The External oscillator clock (OCLK) can be supplied with a 8 to 24 MHz crystal/ceramic

resonator oscillator. In the Typical application, Figure 5, 
oscillator clock circuit. In W7500x, there is no supported 

Figure 5).

W7500x Reference Manual Version1.1.0 41 / 399

must be inserted in External



for External oscillator clock (see



1

1

For 



and 

, it is recommended to use external ceramic capacitors in the 5 pF to 25



pF range(typ.) and are usually the same size, designed for application, and selected to match

the requirements of the crystal or resonator (see Figure 5).

Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).



value depends on the crystal characteristics



Figure 5 Typical application with an 8 MHz crystal

RC oscillator clock

RC oscillator clock (RCLK) signal is generated from an internal 8MHz RC oscillator.

RC oscillator has the advantage of providing a clock source at low cost (no external

components). However the RC oscillator is less accurate than the external crystal or ceramic

resonator.

 Accuracy : 1% at T

= 25oC (User don’t need to calibration)

A

PLL

The internal PLL can be used to multiply the External Oscillator Clock (OCLK) or RC Oscillator

Clock (RCLK). PLL input can be selected by register.

PLL output clock can be generated by following the equations below.

 FOUT = FIN x M / N x 1 / OD
 Where:
 M = M[5] x 2
 N = N[5] x 2
 OD = 2

5

+ M[4] x 24 + M[3] x 23 + M[2] x 22 + M[1] x 2 + M[0] x 1

5

+ N[4] x 24 + N[3] x 23 + N[2] x 22 + N[1] x 2 + N[0] x 1

(2 x OD[1])

x 2

(1 x OD[0])

Generated clock

Each generated clock source can be selected among 3 clock source as independent by each

clock source select register.



value depends on the crystal characteristics



W7500x Reference Manual Version1.1.0 42 / 399

 PLL output clock (MCLK)
 Internal 8MHz RC oscillator clock (RCLK)
 External oscillator clock (8MHz ~ 24MHz) (OCLK)

Each generated clock has own prescaler which can be selected individually by each prescale

value register.

 FCLK, ADCCLK, SSPCLK, UARTCLK : 1/1, 1/2, 1/4, 1/8

 TIMCLK0, TIMCLK1, PWMCLK0 – PWMCLK7, RTCCLK, WDOGCLK : 1/1, 1/2,

1/4, 1/8, 1/16, 1/32, 1/64, 1/128

W7500x Reference Manual Version1.1.0 43 / 399

12.4 Registers (Base address : 0x4100_1000)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

OSCPD

R/W

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

PLLPD

R/W

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

M

OSC power down register (OSC_PDR)

Address offset : 0x000

Reset value : 0x0000_0000

[0] OSCPD – Internal 8MHz RC oscillator power down register

This bit written by S/W to RCOSC enter sleep mode or not

0 : normal operation

1 : power down (enter sleep mode)

PLL power down register (PLL_PDR)

Address offset : 0x010

Reset value : 0x0000_0001

[0] PLLPD – PLL power down register

This bit written by S/W to PLL power down or not

0 : power down

1 : normal operation

PLL frequency calculating register (PLL_FCR)

Address offset : 0x014

Reset value : 0x0005_0200

W7500x Reference Manual Version1.1.0 44 / 399

R/W

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res N res

res

res

res

res

res

OD

R/W

R/W

[1:0] OD

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

PLLOEN

R/W

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

[13:8] N

[21:16] M

These bits are written by S/W to set frequency of PLL output.

PLL output frequency FOUT is calculated by the following equations:

FOUT = FIN x M / N x 1 / OD

Where:

M = M[5] x 32 + M[4] x 16 + M[3] x 8 + M[2] x 4 + M[1] x 2 + M[0] x 1 (2 ~ 63)

N = N[5] x 32 + N[4] x 16 + N[3] x 8 + N[2] x 4 + N[1] x 2 + N[0] x 1 (1 ~ 63)

OD = 2 ^ (2 x OD[1]) x 2 ^ (1 x OD[0])

PLL output enable register (PLL_OER)

Address offset : 0x018

Reset value : 0x0000_0001

[0] PLLOEN – output enable register of PLL

This bit written by S/W to control output enable of PLL

0 : Clock out is disable. VCO is working but FOUT is low only.

1 : Clock out is enable.

PLL bypass register (PLL_BPR)

Address offset : 0x01c

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 45 / 399

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

PLLBP

R/W

[0] PLLBP – bypass register of PLL

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

PLLIS

R/W

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

res

res

res

res

res

res

FCKSRC

R/W

This bit written by S/W to control bypass or not of PLL

0 : bypass disable. Normal operation

1 : bypass enable. Clock out is clock input

PLL input clock source select register (PLL_IFSR)

Address offset : 0x020

Reset value : 0x0000_0000

[0] PLLIS – select register of PLL input clock source

This bit written by S/W to select

0 : Internal 8MHz RC oscillator clock (RCLK)

1 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

FCLK source select register (FCLK_SSR)

Address offset : 0x030

Reset value : 0x0000_0001

[1:0] FCKSRC – select register of FCLK clock source

These bits are written by S/W to select

W7500x Reference Manual Version1.1.0 46 / 399

00, 01 : output clock of PLL (MCLK)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

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FCKPRE

R/W

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SSPCSS

R/W

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

FCLK prescale value select register (FCLK_PVSR)

Address offset : 0x034

Reset value : 0x0000_0000

[1:0] FCKPRE – select prescale value of FCLK clock

These bits are written by S/W to select

00 : 1/1 (bypass)

01 : 1/2

10 : 1/4

11 : 1/8

SSPCLK source select register (SSPCLK_SSR)

Address offset : 0x040

Reset value : 0x0000_0001

[1:0] SSPCSS – SSPCLK clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

W7500x Reference Manual Version1.1.0 47 / 399

SSPCLK prescale value select register (SSPCLK_PVSR)

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SSPCP

R/W

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ADCSS

R/W

Address offset : 0x044

Reset value : 0x0000_0000

[1:0] SSPCP – select prescale value of SSPCLK clock

These bits are written by S/W to select

00 : 1/1 (bypass)

01 : 1/2

10 : 1/4

11 : 1/8

ADCCLK source select register (ADCCLK_SSR)

Address offset : 0x060

Reset value : 0x0000_0001

[1:0] ADCSS – ADCCLK clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

ADCCLK prescale value select register (ADCCLK_PVSR)

Address offset : 0x064

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 48 / 399

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ADCCP

R/W

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T0CSS

R/W

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[1:0] ADCCP – select prescale value of ADCCLK clock

These bits are written by S/W to select

00 : 1/1 (bypass)

01 : 1/2

10 : 1/4

11 : 1/8

TIMER0CLK source select register (TIMER0CLK_SSR)

Address offset : 0x070

Reset value : 0x0000_0001

[1:0] T0CSS – TIMCLK0 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

TIMER0CLK prescale value select register (TIMER0CLK_PVSR)

Address offset : 0x074

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 49 / 399

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T0CPS

R/W

[2:0] T0CPS – select prescale value of TIM0CLK clock

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T1CSS

R/W

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These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

TIMER1CLK source select register (TIMER1CLK_SSR)

Address offset : 0x080

Reset value : 0x0000_0001

[1:0] T1CSS – TIMCLK1 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

TIMER1CLK prescale value select register (TIMER1CLK_PVSR)

Address offset : 0x084

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 50 / 399

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T1CPS

R/W

[2:0] T1CPS – select prescale value of TIM1CLK clock

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P0CSS

R/W

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These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

PWM0CLK source select register (PWM0CLK_SSR)

Address offset : 0x0b0

Reset value : 0x0000_0001

[1:0] P0CPS – PWMCLK0 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

PWM0CLK prescale value select register (PWM0CLK_PVSR)

Address offset : 0x0b4

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 51 / 399

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P0CPS

R/W

[2:0] P0CPS – select prescale value of PWM0CLK clock

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P1CSS

R/W

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

PWM1CLK source select register (PWM1CLK_SSR)

Address offset : 0x0c0

Reset value : 0x0000_0001

[1:0] P1CSS – PWMCLK1 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

PWM1CLK prescale value select register (PWM1CLK_PVSR)

Address offset : 0x0c4

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 52 / 399

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P1CPS

R/W

[2:0] P1CPS – select prescale value of PWM1CLK clock

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P2CSS

R/W

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

PWM2CLK source select register (PWM2CLK_SSR)

Address offset : 0x0d0

Reset value : 0x0000_0001

[1:0] P2CSS – PWMCLK2 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

PWM2CLK prescale value select register (PWM2CLK_PVSR)

Address offset : 0x0d4

W7500x Reference Manual Version1.1.0 53 / 399

Reset value : 0x0000_0000

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P2CPS

R/W

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P3CSS

R/W

[2:0] PWM2CLK_PRE – select prescale value of PWM2CLK clock

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

PWM3CLK source select register (PWM3CLK_SSR)

Address offset : 0x0e0

Reset value : 0x0000_0001

[1:0] P3CSS – PWMCLK3 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

W7500x Reference Manual Version1.1.0 54 / 399

PWM3CLK prescale value select register (PWM3CLK_PVSR)

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P3CPS

R/W

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P4CSS

R/W

Address offset : 0x0e4

Reset value : 0x0000_0000

[2:0] P3CPS – select prescale value of PWM3CLK clock

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

PWM4CLK source select register (PWM4CLK_SSR)

Address offset : 0x0f0

Reset value : 0x0000_0001

[1:0] P4CSS – PWMCLK4 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

W7500x Reference Manual Version1.1.0 55 / 399

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P4CPS

R/W

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P5CSS

R/W

PWM4CLK prescale value select register (PWM4CLK_PVSR)

Address offset : 0x0f4

Reset value : 0x0000_0000

[2:0] P4CPS – select prescale value of PWM4CLK clock

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

PWM5CLK source select register (PWM5CLK_SSR)

Address offset : 0x100

Reset value : 0x0000_0001

[1:0] P5CSS – PWMCLK5 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

W7500x Reference Manual Version1.1.0 56 / 399

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

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P5CPS

R/W

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P6CSS

R/W

PWM5CLK prescale value select register (PWM5CLK_PVSR)

Address offset : 0x104

Reset value : 0x0000_0000

[2:0] P5CPS – select prescale value of PWM5CLK clock

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

PWM6CLK source select register (PWM6CLK_SSR)

Address offset : 0x110

Reset value : 0x0000_0001

[1:0] P6CSS – PWMCLK6 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

W7500x Reference Manual Version1.1.0 57 / 399

10 : Internal 8MHz RC oscillator clock (RCLK)

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P6CPS

R/W

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P7CSS

R/W

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

PWM6CLK prescale value select register (PWM6CLK_PVSR)

Address offset : 0x114

Reset value : 0x0000_0000

[2:0] P6CPS – select prescale value of PWM6CLK clock

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

PWM7CLK source select register (PWM7CLK_SSR)

Address offset : 0x120

Reset value : 0x0000_0001

[1:0] P7CSS – PWMCLK7 clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

W7500x Reference Manual Version1.1.0 58 / 399

01 : PLL output clock (MCLK)

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P7CPS

R/W

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RTCHS

R/W

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

PWM7CLK prescale value select register (PWM7CLK_PVSR)

Address offset : 0x124

Reset value : 0x0000_0000

[2:0] P7CPS – select prescale value of PWM7CLK clock

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

RTC High Speed source select register (RTC_HS_SSR)

Address offset : 0x130

Reset value : 0x0000_0001

[1:0] RTCHS – RTCCLK_hs clock source select register.

These bits are written by S/W to select clock source

W7500x Reference Manual Version1.1.0 59 / 399

00 : disable clock

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RTCPRE

R/W

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RTCSEL

R/W

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

RTC High Speed prescale value select register (RTC_HS_PVSR)

Address offset : 0x134

Reset value : 0x0000_0000

[2:0] RTCPRE – select prescale value of RTCCLK_hs clock

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

011 : 1/8

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

RTC source select register (RTC_SSR)

Address offset : 0x13c

Reset value : 0x0000_0000

[0] RTCSEL – RTCCLK clock source select register.

W7500x Reference Manual Version1.1.0 60 / 399

These bits are written by S/W to select clock source

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11

10 9 8 7 6 5 4 3 2 1 0

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WDHS

R/W

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24

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22

21

20

19

18

17

16

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14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

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WDPRE

R/W

0 : RTCCLK_hs

1 : 32K_OSC_CLK (Low speed external oscillator clock)

WDOGCLK High Speed source select register (WDOGCLK_HS_SSR)

Address offset : 0x140

Reset value : 0x0000_0001

[1:0] WDHS – WDOGCLK_hs clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

WDOGCLK High Speed prescale value select register
(WDOGCLK_HS_PVSR)

Address offset : 0x144

Reset value : 0x0000_0000

[2:0] WDPRE – select prescale value of WDOGCLK_hs clock

These bits are written by S/W to select

000 : 1/1 (bypass)

001 : 1/2

010 : 1/4

W7500x Reference Manual Version1.1.0 61 / 399

011 : 1/8

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16

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13

12

11

10 9 8 7 6 5 4 3 2 1 0

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WDSEL

R/W

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18

17

16

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13

12

11

10 9 8 7 6 5 4 3 2 1 0

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UCSS

R/W

100 : 1/16

101 : 1/32

110 : 1/64

111 : 1/128

WDOGCLK clock source select register (WDOGCLK_SSR)

Address offset : 0x14c

Reset value : 0x0000_0000

[0] WDSEL – WDOGCLK clock source select register.

These bits are written by S/W to select clock source

0 : WDOGCLK_hs

1 : 32K_OSC_CLK (Low speed external oscillator clock)

UARTCLK source select register (UARTCLK_SSR)

Address offset : 0x150

Reset value : 0x0000_0001

[1:0] UCSS – UARTCLK clock source select register.

These bits are written by S/W to select clock source

00 : disable clock

01 : PLL output clock (MCLK)

10 : Internal 8MHz RC oscillator clock (RCLK)

11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

W7500x Reference Manual Version1.1.0 62 / 399

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16

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14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

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UCP

R/W

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22

21

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18

17

16

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15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

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MIITEN

MIIREN

R/W

R/W

UARTCLK prescale value select register (UARTCLK_PVSR)

Address offset : 0x154

Reset value : 0x0000_0000

[1:0] UCP – select prescale value of UARTCLK clock

These bits are written by S/W to select

00 : 1/1 (bypass)

01 : 1/2

10 : 1/4

11 : 1/8

MIICLK enable control register (MIICLK_ECR)

Address offset : 0x160

Reset value : 0x0000_0003

[0] MIIREN – MII RX Clock source enable register

This bit is written by S/W to set enable or disable

0 : Disable MII_RCK and MII_RCK_N

1 : Enable MII_RCK and MII_RCK_N

[1] MIITEN – MII TX Clock source enable register

This bit is written by S/W to set enable or disable

0 : Disable MII_TCK and MII_TCK_N

1 : Enable MII_TCK and MII_TCK_N

W7500x Reference Manual Version1.1.0 63 / 399

Monitoring Clock source select register (MONCLK_SSR)

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17

16

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15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

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CLKMON_SEL

R/W

Address offset : 0x170

Reset value : 0x0000_0000

[4:0] CLKMON_SEL – Select clock source for monitoring (monitoring pin : PA_02)

This bit is written by S/W to set enable or disable

00000 : PLL output clock (MCLK)

00001 : FCLK

00010 : Internal 8MHz RC oscillator clock (RCLK)

00011 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

00100 : ADCCLK

00101 : SSPCLK

00110 : TIMCLK0

00111 : TIMCLK1

01000 : PWMCLK0

01001 : PWMCLK1

01010 : PWMCLK2

01011 : PWMCLK3

01100 : PWMCLK4

01101 : PWMCLK5

01110 : PWMCLK6

01111 : PWMCLK7

10000 : UARTCLK

10001 : MII_RCK

10010 : MII_TCK

W7500x Reference Manual Version1.1.0 64 / 399

10011 : RTCCLK

Offset Register

313029282726252423222120191817161514131211

10

987654321

0

OSC_PDR

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OSCPD

reset value 0

PLL_PDR

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PLLPD

reset value 0

PLL_FCR

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reset value 0 0 0 1 0 1 0 0 0 0 1 0 0 0

PLL_OER

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PLLOEN

reset value 1

PLL_BPR

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PLLBP

reset value 0

PLL_IFSR

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PLLIS

reset value 0

FCLK_SSR

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reset value 0 1

FCLK_PVSR

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reset value 0 0

SSPCLK_SSR

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reset value 0 1

SSPCLK_PVSR

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reset value 0 0

ADCCLK_SSR

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reset value 0 1

ADCCLK_PVSR

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reset value 0 0

TIMER0CLK_SSR

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reset value 0 1

TIMER0CLK_PVSR

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reset value 0 0 0

TIMER1CLK_SSR

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reset value 0 1

TIMER1CLK_PVSR

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reset value 0 0 0

PWM0CLK_SSR

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reset value 0 1

PWM0CLK_PVSR

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reset value 0 0 0

T1CPS

0x0b0

P0CSS

0x0b4

P0CPS

T0CSS

0x07 4

T0CPS

0x08 0

T1CSS

SSPCP

FCKSRC

SSPCSS

0x06 0

ADCSS

0x06 4

ADCCP

OD

0x01 c

0x03 0

0x03 4

FCKPRE

0x02 0

0x04 0

0x04 4

0x07 0

0x08 4

0x00 0

0x01 0

0x01 4

0x01 8

M

N

12.5 Register map

The following table summarizes the CRG registers.

W7500x Reference Manual Version1.1.0 65 / 399

PWM1CLK_SSR

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reset value 0 1

PWM1CLK_PVSR

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reset value 0 0 0

PWM2CLK_SSR

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reset value 0 1

PWM2CLK_PVSR

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reset value 0 0 0

PWM3CLK_SSR

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reset value 0 1

PWM3CLK_PVSR

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reset value 0 0 0

PWM4CLK_SSR

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reset value 0 1

PWM4CLK_PVSR

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reset value 0 0 0

PWM5CLK_SSR

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reset value 0 1

PWM5CLK_PVSR

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reset value 0 0 0

PWM6CLK_SSR

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res

reset value 0 1

PWM6CLK_PVSR

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reset value 0 0 0

PWM7CLK_SSR

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res

reset value 0 1

PWM7CLK_PVSR

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res

reset value 0 0 0

RTC_HS_SSR

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res

reset value 0 1

RTC_HS_PVSR

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res

reset value 0 0 0

RTC_SSR

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res

RTCSEL

reset value 1

WDOGCLK_HS_SSR

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res

reset value 0 1

WDOGCLK_HS_PVSR

res

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res

reset value 0 0 0

WDOGCLK_SSR

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res

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res

res

WDSEL

reset value 1

0x13 c

0x14 0

WDHS

0x14 4

WDPRE

0x14 c

0x12 4

P7CPS

0x13 0

RTCHS

0x13 4

RTCPRE

0x11 0

P6CSS

0x11 4

P6CPS

0x12 0

P7CSS

0x0f4

P4CPS

0x10 0

P5CSS

0x10 4

P5CPS

0x0e0

P3CSS

0x0e4

P3CPS

0x0f0

P4CSS

0x0c4

P1CPS

0x0d0

P2CSS

0x0d4

P2CPS

0x0c0

P1CSS

W7500x Reference Manual Version1.1.0 66 / 399

UARTCLK_SSR

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res

reset value 0 1

UARTCLK_PVSR

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res

reset value 0 0

MIICLK_ECR

res

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res

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res

MIITEN

MIIREN

reset value 1 1

MONCLK_SSR

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res

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res

res

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res

res

res

res

res

res

reset value 0 0 0 0 0

0x150

UCSS

0x154

UCP

0x160

0x170

CLKMON_SEL

Table 5 CRG register map and reset values

13 Tcp/ip core Offload Engine (TOE)

13.1 Introduction

The TCP/IP Core Offload Engine (TOE) is a Hardwired TCP/IP embedded Ethernet controller

that provides easier Internet connection to embedded systems. TOE enables users to have

Internet connectivity in their applications by using the TCP/IP stack.

WIZnet’s Hardwired TCP/IP is the market-proven technology that supports TCP, UDP, IPv4, ICMP,

ARP, IGMP, and PPPoE protocols. TOE embeds the 32Kbyte internal memory buffer for the

Ethernet packet processing. Using TOE allows users to implement the Ethernet application by

adding the simple socket program. It’s faster and easier than using any other Embedded

Ethernet solutions. 8 independent hardware sockets can be used simultaneously.

TOE also provides WOL (Wake on LAN) to reduce power consumption of the system.

13.2 Features

 Supports Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
 Supports 8 independent sockets simultaneously
 Supports Power down mode
 Supports Wake on LAN over UDP
 Internal 32Kbytes Memory for TX/RX Buffers
 Not supports IP Fragmentation

W7500x Reference Manual Version1.1.0 67 / 399

13.3 Functional description

RXC
TXC

RXC_N
TXC_N

COL
DUP
CRS
RXDV
RXD[3:0]

TXE
TXD[3:0]

MDC

MDO
MDI

Common

Register

Socket

Register

Register Controller

Memory Controller

TX

Memory

RX

Memory

TCPIPCore

MDC

Controller

INT

MII

Controller

AHB

Figure 6 shows the TOE block diagram.

Figure 6 TOE block diagram

13.4 TOE Memory map

TOE has one Common Register Block, eight Socket Register Blocks, and TX/RX Buffer Blocks

allocated to each Socket. Figure 7 shows the selected block by the base address and the

available offset address range of Socket TX/RX Buffer Blocks. Each Socket’s TX Buffer Block

physically exists in one 16KB TX memory and is initially allocated with 2KB. Also, Each Socket’s

RX Buffer Block physically exists in one 16KB RX Memory and is initially allocated with 2KB.

Regardless of the allocated size of each Socket TX/RX Buffer, it can be accessible within the

16 bits offset address range (From 0x0000 to 0xFFFF).

W7500x Reference Manual Version1.1.0 68 / 399

Base address

Blocks

Physical

16KB RX Memory

Valid Range:

16bits Offset Address[15:0]

...

0x461F_0000

0x461E_0000

0x461D_0000

0x461C_0000

0x461B_0000

0x461A_0000

0x4619_0000

0x4618_0000

0x4617_0000

0x4616_0000

0x4615_0000

0x4613_0000

0x4612_0000

0x4611_0000

0x4610_0000

0x460F_0000

0x460E_0000

0x460D_0000

0x460C_0000

0x460B_0000

0x460A_0000

0x4609_0000

0x4608_0000

0x4607_0000

0x4606_0000)

0x4605_0000

0x4603_0000

0x4602_0000

0x4601_0000

0x4604_0000

0x4614_0000

0x4600_0000

Reserved

Reserved

Socket 1 TX Buffer

......

Socket 7 RX Buffer

... ...

...

...

0x0000

0x1000

0x0800

0x1800

0x2000

0x2800

0x3000

0x3800

0x3FFF

Socket 0

TX Bufer (2KB)

Socket 1

TX Buffer (2KB)

Socket 2

TX Buffer (2KB)

Socket 3

TX Buffer (2KB)

Socket 4

TX Buffer (2KB)

Socket 5

TX Buffer (2KB)

Socket 6

TX Buffer (2KB)

Socket 7

TX Buffer (2KB)

0x093C

0x0FFF

...

0x0000

0x1000

0x0800

0x1800

0x2000

0x2800

0x3000

0x3800

0x3FFF

Socket 0

RX Buffer (2KB)

Socket 1

RX Buffer (2KB)

Socket 2

RX Buffer (2KB)

Socket 3

RX Buffer (2KB)

Socket 4

RX Buffer (2KB)

Socket 5

RX Buffer (2KB)

Socket 6

RX Buffer (2KB)

Socket 7

RX Buffer (2KB)

0x3E2C

0x0FFF

Physical

16KB TX Memory

Socket 7 RX Buffer

Socket 7 TX Buffer

Socket 7 Register

Reserved

Socket 6 RX Buffer

Socket 6 TX Buffer

Socket 6 Register

Reserved

Socket 5 RX Buffer

Socket 5 TX Buffer

Socket 5 Register

Reserved

Socket 4 RX Buffer

Socket 4 TX Buffer

Socket 4 Register

Reserved

Socket 3 RX Buffer

Socket 3 TX Buffer

Socket 3 Register

Reserved

Socket 2 RX Buffer

Socket 2 TX Buffer

Socket 2 Register

Reserved

Socket 1 RX Buffer

Socket 1 TX Buffer

Socket 1 Register

Reserved

Socket 0 RX Buffer

Socket 0 TX Buffer

Socket 0 Register

Common Register

0x0000

0x6054

0x6055

0xFFFF

0x0000

0x022C

0x022D

0xFFFF

0x0000

0x07FF

0x0800

0xFFFF

0x0FFF

0x1000

0xEFFF

0xF000

0xF7FF

0xF800

0x0000

0x07FF

0x0800

0xFFFF

0x0FFF

0x1000

0xEFFF

0xF000

0xF7FF

0xF800

0x413C

0x9E2C

Socket 0 Register

Common Register

W7500x Reference Manual Version1.1.0 69 / 399

Figure 7. Register & Memory Organization

Common register map

Address

Register

0x0000

TOE Version (VERSIONR)

0x2000

TICKCLOK (TCLKR)

0x2100

Interrupt (IR)

0x2104

Interrupt Mask (IMR)

0x2108

Interrupt Clear (IRCR)

0x2110

Socket Interrupt (SIR)

0x2114

Socket Mask (SIMR)

0x2300

Mode (MR)

0x2400

PPP Timer (PTIMER)

0x2404

PPP Magic (PMAGIC)

0x2408

PPP Destination MAC Address (PHAR1)

0x240C

PPP Destination MAC address (PHAR0)

0x2410

PPP Session Identification (PSIDR)

0x2414

PPP Maximum Segment Size (PMSS)

0x6000

Source Hardware Address (SHAR1)

0x6004

Source Hardware Address (SHAR0)

0x6008

Gateway Address (GA)

0x600C

Subnet Mask (SUB)

0x6010

Source IP Address (SIP)

0x6020

Network Configuration Lock (NCONFL)

0x6040

Retry Time (RTR)

0x6044

Retry Counter (RCR)

0x6050

Unreachable IP Address (UIP)

0x6054

Unreachable Port Address (UPORT)

Common Register Block configures the general information of TOE such as IP and MAC address.

<Table 6> defines the offset address of registers in this block.

Table 6. Offset Address for Common Register

Socket register map

TOE supports 8 Sockets for communication channel. Each Socket is controlled by Socket n

Register (n = 0,…,7 ,where n is socket number). <Table 2> defines the 16bits Offset Address

of registers in Socket n Register Block.

W7500x Reference Manual Version1.1.0 70 / 399

Table 7. Offset Address in Socket n Register Block (n = 0,…,7, where n is Socket number)

Offset

Register

0x0000

Socket Mode (Sn_MR)

0x0010

Socket Command (Sn_CR)

0x0020

Socket Interrupt (Sn_IR)

0x0024

Socket Interrupt Mask (Sn_IMR)

0x0028

Socket Interrupt Clear (Sn_ICR)

0x0030

Socket Status (Sn_SR)

0x0100

Socket Protocol Number (Sn_PNR)

0x0104

Socket IP Type of Service (Sn_TOS)

0x0108

Socket TTL (Sn_TTLR)

0x010C

Socket Fragment Offset (Sn_FRAG)

0x0110

Socket Maximum Segment (Sn_MSSR)

0x0114

Socket Port Number (Sn_PORTR)

0x0118

Socket Destination Hardware address0 (Sn_DHAR0)

0x011C

Socket Destination Hardware address1 (Sn_DHAR1)

0x0120

Socket Destination Port Number (Sn_DPORTR)

0x0124

Socket Destination IP Address (Sn_DIPR)

0x0180

Socket Keep Alive Timer (Sn_KATMR)

0x0184

Socket Retry Time (Sn_RTR)

0x0188

Socket Retry Counter (Sn_RCR)

0x0200

Socket TX Memory Size (Sn_TXBUF_SIZE)

0x0204

Socket TX Free Size (Sn_TX_FSR)

0x0208

Socket TX Read Pointer (Sn_TX_RD)

0x020C

Socket TX Write Pointer (Sn_TX_WR)

0x0220

Socket RX Memory Size (Sn_RXBUF_SIZE)

0x0224

Socket RX Received Size (Sn_RX_RSR)

0x0228

Socket RX Read Pointer (Sn_RX_RD)

0x022C

Socket RX Write Pointer (Sn_RX_WR)

Memory

TOE has one 16KB TX memory for Socket n TX Buffer Blocks and one 16KB RX memory for

Socket n RX buffer Blocks.

16KB TX memory is initially allocated in 2KB size for each Socket TX Buffer Block (2KB X 8 =

16KB). The initial allocated 2KB size of Socket n TX Buffer can be re-allocated by using ‘Socket

n TX Buffer Size Register (Sn_TXBUF_SIZE)’.

W7500x Reference Manual Version1.1.0 71 / 399

Once all Sn_TXBUF_SIZE registers have been configured, Socket TX Buffer is allocated with the

configured size of 16KB TX Memory and is assigned sequentially from Socket 0 to Socket 7. Its

physical memory address is automatically determined in 16KB TX memory. Therefore, the total

sum of Sn_TXBUF_SIZE should not exceed 16 in case of error in data transmission.

The 16KB RX memory allocation method is the same as the 16KB TX memory allocation method.

16KB RX memory is initially allocated into 2KB size for each Socket RX Buffer Block (2KB X 8 =

16KB). The initial allocated 2KB size of Socket n RX Buffer can be re-allocated by using ‘Socket

n RX Buffer Size Register (Sn_RXBUF_SIZE)’.

When all Sn_RXBUF_SIZE registers have been configured, the Socket RX Buffer is allocated

with the configured size in 16KB RX Memory and is assigned sequentially from Socket 0 to

Socket 7. The physical memory address of the Socket RX Buffer is automatically determined

in 16KB RX memory. Therefore, the total sum of Sn_RXBUF_SIZE should not exceed 16 or data

reception error will occur.

For 16KB TX/RX memory allocation, refer to Sn_TXBUF_SIZE & Sn_RXBUF_SIZE in ‘Chapter 0’.

The Socket n TX Buffer Block allocated in 16KB TX memory is buffer for saving data to be

transmitted by host. The 16bits Offset Address of Socket n TX Buffer Block has 64KB address

space ranged from 0x0000 to 0xFFFF, and is configured with reference to ‘Socket n TX Write

Pointer Register (Sn_TX_WR)’ & ‘Socket n TX Read Pointer Register(Sn_RX_RD)’. However, the

16bits Offset Address automatically converts into the physical address to be accessible in 16KB

TX memory such as Figure 7.

The Socket n RX Buffer Block allocated in 16KB RX memory is buffer for saving the received

data through the Ethernet. The 16bits Offset Address of Socket n RX Buffer Block has 64KB

address space ranged from 0x0000 to 0xFFFF, and is configured with reference to ‘Socket n RX

RD Pointer Register (Sn_RX_RD)’ & ‘Socket n RX Write Pointer Register (Sn_RX_WR)’. However,

the 16bits Offset Address automatically converts into the physical address to be accessible in

16KB RX memory such as Figure 7.

W7500x Reference Manual Version1.1.0 72 / 399

13.5 Common register (Base : 0x4600_0000)

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22

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20

19

18

17

16

res

res

Res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

Res

res

res

res

res

res

VERSION[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

31

30

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26

25

24

23

22

21

20

19

18

17

16

res

res

Res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

TCKCNT[15:0]

R/W

VERSIONR (TOE Version Register)

Address Offset : 0x0000

Reset value : 0x0000_0005

[7:0] VERSION - indicates the TOE version as 0x05.

TCKCNTR (Ticker Counter Register)

Address Offset : 0x2000

Reset value : 0x0000_07D0

[15:0] TCKCNT – Ticker counter register is used Tick counter of 100usec. for internal timer of

TOE. The unit of tick is HCLK. RTR, Sn_RTR, Sn_KATMR operates on the value of this register.



  



Ex) When the reference time of TOE is set to 100us, and when  = 20MHz,



  



   

TCKCNT = 2000 = 0x07D0

W7500x Reference Manual Version1.1.0 73 / 399

IR (Interrupt Register)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

Res

res

res

res

res

res

res

res

res

res

es

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

IR[7:4]

res

res

res

res R R R R

31

30

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24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

IMR[7:4]

res

res

res

res

R/W

Address Offset : 0x2100

Reset value : 0x0000_0000

IR indicates the interrupt status. If IR is not equal to ‘0x00’, INTn PIN is asserted low until it

is ‘0x00’.

[4] WOL – Magic Packet

When WOL mode is enabled and receives the magic packet over UDP, this bit is set.

[5] PPPoE – PPPoE Close

When PPPoE is disconnected during PPPoE mode, this bit is set.

[6] UNREACH – Destination unreachable

When receiving the ICMP (Destination port unreachable) packet, this bit is set as ‘1’.

When this bit is ‘1’, Destination Information such as IP address and Port number may

be checked with the corresponding UIPR & UPORTR.

[7] Conflict – IP Conflict

Bit is set as ‘1’ when own source IP address is same with the sender IP address in the

received ARP request.

IMR (Interrupt Mask Register)

Address Offset : 0x2104

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 74 / 399

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24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

IRC[8:4]

res

res

res

res

*R/C_W1

IMR is used to mask interrupts. Each bit of IMR corresponds to each bit of IR. When a bit of

IMR is ‘1’ and the corresponding bit of IR is ‘1’, an interrupt will be issued. In other words, if

a bit of IMR is ‘0’, an interrupt will not be issued even if the corresponding bit of IR is ‘1’.

[4] Magic Packet

0: Disable Magic Packet Interrupt

1: Enable Magic Packet Interrupt

[5] PPPoE Close Interrupt Mask

0: Disable PPPoE Close Interrupt

1: Enable PPPoE Close Interrupt

[6] Destination unreachable Interrupt Mask

0: Disable Destination unreachable Interrupt

1: Enable Destination unreachable Interrupt

[7] IP Conflict Interrupt Mask

0: Disable IP Conflict Interrupt

1: Enable IP Conflict Interrupt

IRCR (Interrupt Clear Register)

Address Offset : 0x2108

Reset value : 0x0000_0000

IRCR is used to clear interrupts. Each bit of IR can be cleared when the host writes ‘1’ value

to each bit of IRCR corresponding to each bit of IR.

* ReadClearWrite1 (R/C_W1) : Software can read as well as clear this bit by writing

‘1’. Writing ‘0’ has no effect on the bit value.

[4] Magic Packet Interrupt Clear

[5] PPPoE Close Interrupt Clear

[6] Destination unreachable Interrupt Clear

[7] IP Conflict Interrupt Clear

W7500x Reference Manual Version1.1.0 75 / 399

SIR (Socket Interrupt Register)

31

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29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

S7

S6

S5

S4

S3

S2

S1

S0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

res

res

S7

S6

S5

S4

S3

S2

S1

S0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Address Offset : 0x2110

Reset value : 0x0000_0000

SIR indicates the interrupt status of Socket. Each bit of SIR be still ‘1’ until Sn_IR is cleared by

the host. If Sn_IR is not equal to ‘0x00’, the n-th bit of SIR is ‘1’ and INTn PIN is asserted until

SIR is ‘0x00’

[7:0] SIR - When the interrupt of Socket n occurs, the n-th bit of SIR becomes ‘1’.

SIMR (Socket Interrupt Mask Register)

Address Offset : 0x2114

Reset value : 0x0000_0000

Each bit of SIMR corresponds to each bit of SIR. When a bit of SIMR is ‘1’ and the corresponding

bit of SIR is ‘1’, Interrupt will be issued. In other words, if a bit of SIMR is ‘0’, an interrupt will

be not issued even if the corresponding bit of SIR is ‘1’.

[7:0] SIR - Socket n Interrupt Mast

0: Disable Socket n Interrupt

1: Enable Socket n Interrupt

W7500x Reference Manual Version1.1.0 76 / 399

MR (Mode Register)

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24

23

22

21

20

19

18

17

16

res

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res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

res

res

res

NTR

res

RST

res

WOL

PB

res

NSC

FA

res

R/W

R/W

R/W

R/W

R/W

R/W

Address Offset : 0x2300

Reset value : 0x0000_0000

MR is used for S/W reset, ping block mode and PPPoE mode

[2] NSC – MACRAW No Size Check

If this bit is ‘1’, it does not check packet size In MACRAW mode.

0 : Enable Check Packet Size

1 : Disable Check Packet Size

[4] PB – Ping Block

If the bit is ‘1’, it blocks the response to a ping request.

0: Disable Ping block

1: Enable Ping block

[5] WOL – Wake on Lan

If WOL mode is enabled and the received magic packet over UDP has been normally

processed, the Interrupt PIN (INTn) asserts to low. When using WOL mode, the UDP

Socket should be opened with any source port number. (Refer to Socket n Mode

Register (Sn_MR) for opening Socket.)

Notice: The magic packet over UDP supported by TOE consists of 6 bytes

synchronization stream (‘0xFFFFFFFFFFFF’) and 16 times Target MAC address stream

in UDP payload. The options such like password are ignored. You can use any UDP

source port number for WOL mode.

0: Disable WOL mode

1: Enable WOL mode

[7] RST – Software Reset

If this bit is ‘1’, All internal registers will be initialized. It will be automatically cleared

as ‘0’ after S/W reset.

[10] NTR – No Send TCP Reset Packet

If this bit is ‘1’, in TCP mode, Socket does not send Reset Packet.

0 : Send Reset Pakcet

1 : No Send Reset Packet

W7500x Reference Manual Version1.1.0 77 / 399

PTIMER (PPP Link Control Protocol Request Timer Register)

31

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18

17

16

res

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15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

Res

res

res

res

res

PTIME[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

31

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25

24

23

22

21

20

19

18

17

16

res

res

res

Res

res

res

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res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

res

Res

res

res

res

res

PMAGIC[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x001D

0x01

Address Offset : 0x2400

Reset value : 0x0000_0028

[7:0] PTIME configures the time for sending LCP echo request. The unit of time is 25ms

Ex) in case that PTIMER is 200,

200 * 25(ms) = 5000(ms) = 5 seconds

PMAGICR (PPP Link Control Protocol Magic number Register)

Address Offset : 0x2404

Reset value : 0x0000_0000

PMAGICR configures the 4bytes magic number to be used in LCP echo request.

[7:0] PMAGIC

Ex) PMAGIC = 0x01

LCP Magic number = 0x01010101

PHAR (Destination Hardware Address Register in PPPoE)

Address Offset : 0x2408

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 78 / 399

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23

22

21

20

19

18

17

16

PHAR[31:24]

PHAR1[23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

PHAR[15:8]

PHAR[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

PHAR[31:24]

PHAR[23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

PHAR0[32:24]

PHAR0[23:16]

PHAR0[15:8]

PHAR0[32:24]

PHAR1[32:24]

PHAR1[23:16]

0x00

0x08

0xDC

0x12

0x34

0x56

31

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23

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21

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19

18

17

16

res

res

res

res

res

Res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

PSID[15:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Address Offset : 0x240C

Reset value : 0x0000_0000

PHAR should be written to the PPPoE server hardware address acquired in PPPoE connection

process.

PHAR0 and PHAR1 – configures Destination hardware address

Ex) In case that destination hardware address is 00:08:DC:12:34:56

PSIDR (Session ID Register in PPPoE)

Address Offset : 0x2410

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 79 / 399

[15:0] PSID - should be written to the PPPoE sever session ID acquired in PPPoE connection

31

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16

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res

res

res

Res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

PMSS[15:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

PMSS[15:8]

PMSS[7:0]

0x12

0x34

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

SHAR0[31:24]

SHAR0[23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

SHAR0[15:8]

SPHAR0[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

31

30

29

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26

25

24

23

22

21

20

19

18

17

16

SHA1[31:24]

SHAR1[23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

process.

PMRUR (Maximum Receive Unit Register in PPPoE)

Address Offset : 0x2414

Reset value : 0x0000_FFFF

[15:0] PMRUR configures the maximum receive unit of PPPoE.

Ex) in case that maximum receive unit in PPPoE is 0x1234

SHAR (Source Hardware Address Register)

Address Offset : 0x6000

Reset value : 0x0000_0000

Address Offset : 0x6004

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 80 / 399

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

res

SHAR0[32:24]

SHAR0[23:16]

SHAR0 [15:8]

SHAR0 [32:24]

SHAR1 [32:24]

SHAR2 [23:16]

0x00

0x08

0xDC

0x12

0x34

0x56

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

GA[31:24]

GA[23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

GA[15:8]

GA[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

GA[31:24]

GA[23:16]

GA[15:8]

GA[7:0]

192 (0xC0)

168 (0xA8)

0 (0x00)

1 (0x01)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

SUB[31:24]

SUB[23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SHAR configures the source hardware address.

Ex) In case of “00.08.DC.12.34.56”

GAR (Gateway Address)

Address Offset : 0x6008

Reset value : 0x0000_0000

GAR[31:0] – configures the default gateway address

Ex) In case of “192.168.0.1”

SUBR ( Subnet Mask Register)

Address Offset : 0x600C

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 81 / 399

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

SUBR[15:8]

SUBR[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SUB[31:24]

SUB[23:16]

SUB[15:8]

SUB[7:0]

255 (0xFF)

255 (0xFF)

255 (0xFF)

0 (0x00)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

SIPR[31:24]

SIPR[23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

SIPR[15:8]

SIPR[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SIPR[31:24]

SIPR[23:16]

SIPR[15:8]

SPIR[7:0]

192 (0xC0)

168 (0xA8)

0 (0x00)

2 (0x02)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

NCONFL[31:24]

NCONFL [23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SUBR configures the subnet mask address.

Ex) In case of “255.255.255.0”

SIPR (Source IP address Register)

Address Offset : 0x6010

Reset value : 0x0000_0000

SIPR configures the source IP address.

Ex) In case of “192.168.0.2”

NCONFLR ( Network Configuration Lock Register)

Address Offset : 0x6020

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 82 / 399

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

NCONFL [15:8]

NCONFL [7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

NCONFL[31:24]

NCONFL [23:16]

NCONFL [15:8]

NCONFL [7:0]

1 (0x01)

172 (0xAC)

206 (0xCE)

85 (0x55)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

RTR[15:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

NCONFLR is used to unlock and lock the network configuration registers which are SIR, SUBR,

GAR and SHAR. When LOCK is ‘ON’, the protected registers are not able to access. In this case

a value of 0x01ACCE55 is written to NCONFLR. When LOCK is ‘OFF’, the protected registers

are allowed to access. In this case any value except 0x01ACCE55 is written.

Ex) In case of ‘LOOK is ON’

RTR (Retry Time Register)

Address Offset : 0x6040

Reset value : 0x0000_07D0

RTR configures the retransmission timeout period. The unit of timeout period is 100us(Refer

to TCKCNTR) and the default of RTR is ‘0x07D0’ or ‘2000’. And so the default timeout period

is 200ms(100us X 2000).

During the time configured by RTR, WZTOE waits for the peer response to the packet that is

transmitted by Sn_CR(CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If

the peer does not respond within the RTR time, WZTOE retransmits the packet or issues

timeout.

When RTR is not ‘0x0000_0000, RTR is used to configure the timeout period of all socket. When

RTR is ‘0x0000_0000’, the timeout period of each socket could set by using Socket n Retry

Time Register (Sn_RTR).

Ex) When timeout-period is set as 400ms, RTR = (400ms / 1ms) X 10 = 4000(0x0FA0)

W7500x Reference Manual Version1.1.0 83 / 399

RTR[15:8]

0x0F

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

RC[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

RC[7:0]

0x07

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󰇜

RCR (Retry Counter Register)

Address Offset : 0x6044

Reset value : 0x0000_0008

RCR configures the number of time of retransmission. When retransmission occurs as many as

‘RCR+1’, Timeout interrupt is issued (Sn_IR[TIMEOUT] = ‘1’).

When RCR is not ‘0x0000_0000, RCR is used to configure the timeout period of all socket.

When RCR is ‘0x0000_0000’, the timeout period of each socket could set by using Socket n

Retry Counter Register (Sn_RCR).

Ex) RCR = 0x0007

The timeout of WZTOE can be configurable with RTR and RCR. WZTOE has two kind timeout

such as Address Resolution Protocol (ARP) and TCP retransmission.

At the ARP (Refer to RFC 826, http://www.ietf.org/rfc.html) retransmission timeout, WZTOE

automatically sends ARP-request to the peer’s IP address in order to acquire MAC address

information (used for communication of IP, UDP, or TCP). While waiting for ARP-response from

the peer, if there is no response during the configured RTR time, a temporary timeout is

occurred and ARP-request is retransmitted. It is repeated as many as ‘RCR + 1’ times. Even

after the ARP-request retransmissions are repeated as ‘RCR+1’ and there is no response to the

ARP-request, the final timeout is occurred and Sn_IR(TIMEOUT) becomes ‘1’. The time of final

timeout (ARPTO) of ARP-request is as below.

W7500x Reference Manual Version1.1.0 84 / 399

󰇛  



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







  

N : Retransmission count, 0≤N ≤ M

M : Minimum value when RTR x 2

(M+1)

> 65535 and 0 ≤ M ≤ RCR

RTRMAX : RTR x 2

M

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

UIP[31:24]

UIPR[23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

UIPR[15:8]

UIPR[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

At the TCP packet retransmission timeout, WZTOE transmits TCP packets (SYN, FIN, RST, DATA

packets) and waits for the acknowledgement (ACK) during the configured RTR time and RCR.

If there is no ACK from the peer, a temporary timeout occurs and the TCP packet is

retransmitted. The retransmission is repeated as many as ‘RCR+1’. Even after TCP

retransmission is repeated as ‘RCR+1’ and there is no response to the TCP retransmission, the

final timeout is occurred and Sn_IR(TIMEOUT) becomes ‘1’. The time of final timeout (TCPTO)

of TCP retransmission is as below.

Ex) When RTR = 2000(0x07D0), RCR = 8(0x0008),

ARPTO = 2000 X 0.1ms X 9 = 1800ms = 1.8s

TCP

= (0x07D0+0x0FA0+0x1F40+0x3E80+0x7D00+0xFA00+0xFA00+0xFA00+0xFA00) X 0.1ms

TO

= (2000 + 4000 + 8000 + 16000 + 32000 + ((8 - 4) X 64000)) X 0.1ms

= 318000 X 0.1ms = 31.8s

UIPR (Unreachable IP address Register)

Address Offset : 0x6050

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 85 / 399

TOE receives an ICMP packet(Destination port unreachable) when data is sent to a port number

UIP[31:24]

UIP[23:16]

UIP[15:8]

UIP[7:0]

192 (0xC0)

168 (0xA8)

0 (0x00)

11 (0x0E)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

UPORT[15:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

UPORT[15:8]

UPORT[7:0]

18 (0x12)

52(0x34)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

which socket is not open and UNREACH bit of IR becomes ‘1’ and UIPR indicates the destination

IP address.

Ex) In case of “192.168.0.11”

UPORTR (Unreachable Port Register)

Address Offset : 0x6054

Reset value : 0x0000_0000

TOE receives an ICMP packet(Destination port unreachable) when data is sent to a port number

which socket is not open and UNREACH bit of IR becomes ‘1’ and UPORTR indicates the

destination port number.

[15 :0] UPORT – Destination port number bits

Ex) In case of “0x1234”

13.6 Socket register (Base : 0x4601_0000 + 0x0004_000 x

n)[n=0,…7, where n is socket number]

Sn_MR (Socket n Mode Register)

Address Offset : 0x0000

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 86 / 399

res

res

Res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

Res

Res

res

res

res

res

res

Sn_MR[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Sn_MR[3:0]

Meaning

0 0 0

0

Closed

0 0 0

1

TCP

0 0 1

0

UDP

0 1 0

0

MACRAW

Sn_MR configures the option or protocol type of Socket n.

[3:0] These bits configures the protocol mode of Socket n as follows

 MACRAW mode should be only used in Socket 0.

[4] UNICAST Blocking and IPv6 packet Blocking

UNICAST Blocking in UDP mode

0 : disable Unicast Blocking

1 : enable Unicast Blocking

This bit blocks receiving the unicast packet during UDP mode(P[3:0] = ‘0010’) and MULTI = ‘1’.

IPv6 packet Blocking in MACRAW mode

0 : disable IPv6 Blocking

1 : enable IPv6 Blocking

This bit is applied only during MACRAW mode (P[3:0] = ‘0100’). It blocks to receiving the IPv6

packet.

[5] Use No Delayed ACK, Multicast and Multicast Blocking mode

Use No Delayed ACK

0 : Disable No Delayed ACK option

1 : Enable No Delayed ACK option

This bit is applied only during TCP mode (P[3:0] = ‘0001’).When this bit is ‘1’, It sends the ACK

packet without delay as soon as a

W7500x Reference Manual Version1.1.0 87 / 399

Multicast

0 : using IGMP version 2

1 : using IGMP version 1

This bit is applied only during UDP mode(P[3:0] = ‘0010’) and MULTI = ‘1’. It configures the

version for IGMP messages (Join/Leave/Report).

Multicast Blocking in MACRAW mode

0 : disable Multicast Blocking

1 : enable Multicast Blocking

This bit is applied only when MACRAW mode(P[3:0] = ‘0100’). It blocks to receive the packet

with multicast MAC address.

[6] Broadcast Blocking in MACRAW and UDP mode

0 : disable Broadcast Blocking

1 : enable Broadcast Blocking

This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = ‘0010’). In addition,

This bit does when MACRAW mode(P[3:0] = ‘0100’) Data packet is received from a peer. When

this bit is ‘0’, It sends the ACK packet after waiting for the timeout time configured by RTR.

[7] Multicasting and MAC Filter Enable mode

Multicasting in UDP mode

0 : disable Multicasting

1 : enable Multicasting

This bit is applied only during UDP mode(P[3:0] = ‘0010’).To use multicasting, Sn_DIPR &

Sn_DPORT should be respectively configured with the multicast group IP address & port number

before Socket n is opened by OPEN command of Sn_CR

MAC Filter Enable in MACRAW mode

0 : disable MAC Filtering

1 : enable MAC Filtering

This bit is applied only during MACRAW mode(P[3:0] = ‘0100’).When set as ‘1’, WZTOE can only

receive broadcasting packet or packet sent to itself. When this bit is ‘0’, WZTOE can receive

all packets on Ethernet. If user wants to implement Hybrid TCP/IP stack, it is recommended

that this bit is set as ‘1’ for reducing host overhead to process the all received packets.

W7500x Reference Manual Version1.1.0 88 / 399

Sn_CR (Socket n Command Register)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

res

Res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10

9

8

7

6

5

4 3 2 1 0

res

Res

Res

res

res

res

res

res

Sn_CR[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Value

Symbol

Description

0x01

OPEN

Socket n is initialized and opened according to the protocol

selected in Sn_MR (P3:P0). The table below shows the value of

Sn_SR corresponding to Sn_MR.

Sn_MR (P[3:0])

Sn_SR

Sn_MR_CLOSE (‘0000’)

-

Sn_MR_TCP (‘0001’)

SOCK_INIT (0x13)

Sn_MR_UDP (‘0010’)

SOCK_UDP (0x22)

S0_MR_MACRAW (‘0100’)

SOCK_MACRAW (0x02)

.

0x02

LISTEN

This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP). In this

mode, Socket n operates as a ‘TCP server’ and waits for

connection-request (SYN packet) from any ‘TCP client’.

The Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN.

When a ‘TCP client’ connection request is successfully

established, the Sn_SR changes from SOCK_LISTEN to

SOCK_ESTABLISHED and the Sn_IR(0) becomes ‘1’. But when a ‘TCP

client’ connection request is failed, Sn_IR(3) becomes ‘1’ and the

status of Sn_SR changes to SOCK_CLOSED.

0x04

CONNECT

This is valid only in TCP mode and operates when Socket n acts as

‘TCP client’. To connect, a connect-request (SYN packet) is sent

Address Offset : 0x0010

Reset value : 0x0000_0000

This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND,

and RECEIVE. After WZTOE accepts the command, the Sn_CR register is automatically cleared

to 0x00. Even though Sn_CR is cleared to 0x00, the command is still being processed. To check

whether the command is completed or not, please check the Sn_IR or Sn_SR.

W7500x Reference Manual Version1.1.0 89 / 399

to ‘TCP server’ configured by Sn_DIPR & Sn_DPORT(destination

address & port). If the connect-request is successful, the Sn_SR is

changed to SOCK_ESTABLISHED and the Sn_IR(0) becomes ‘1’.

The connect-request fails in the following three cases.

1. When a ARPTO occurs (Sn_IR(3)=‘1’) because the

destination hardware address is not acquired through the

ARP-process.

2. When a SYN/ACK packet is not received and TCPTO

(Sn_IR(3) = ‘1 )

3. When a RST packet is received instead of a SYN/ACK

packet.

In these cases, Sn_SR is changed to SOCK_CLOSED.

0x08

DISCON

Valid only in TCP mode.

Regardless of ‘TCP server’ or ‘TCP client’, the DISCON command

processes the disconnect-process (‘Active close’ or ‘Passive

close’).

Active close: it transmits disconnect-request(FIN packet) to the

connected peer

Passive close: When FIN packet is received from peer,

a FIN packet is replied back to the peer.

When the disconnect-process is successful (that is, FIN/ACK

packet is received successfully), Sn_SR is changed to

SOCK_CLOSED. Otherwise, TCPTO occurs (Sn_IR(3)=‘1)= and then

Sn_SR is changed to SOCK_CLOSED.

cf> If CLOSE is used instead of DISCON, only Sn_SR is changed to

SOCK_CLOSED without disconnect-process.

If a RST packet is received from a peer during communication,

Sn_SR is unconditionally changed to SOCK_CLOSED.

0x10

CLOSE

Close Socket n.

Sn_SR is changed to SOCK_CLOSED.

0x20

SEND

SEND transmits all the data in the Socket n TX buffer. For more

details, please refer to Socket n TX Free Size Register

(Sn_TX_FSR), Socket n, TX Write Pointer Register (Sn_TX_WR), and

Socket n TX Read Pointer Register(Sn_TX_RD).

0x21

SEND_MAC

Valid only in UDP mode.

The basic operation is same as SEND. Normally SEND transmits

data after destination hardware address is acquired by the

W7500x Reference Manual Version1.1.0 90 / 399

automatic ARP-process(Address Resolution Protocol). But

SEND_MAC transmits data without the automatic ARP-process. In

this case, the destination hardware address is acquired from

Sn_DHAR configured by host, instead of APR-process.

0x22

SEND_KEEP

Valid only in TCP mode.

It checks the connection status by sending 1byte keep-alive

packet. If the peer cannot respond to the keep-alive packet during

timeout time, the connection is terminated and the timeout

interrupt will occur.

0x40

RECV

RECV completes the processing of the received data in Socket n

RX Buffer by using a RX read pointer register (Sn_RX_RD).

For more details, refer to Socket n RX Received Size Register

(Sn_RX_RSR), Socket n RX Write Pointer Register (Sn_RX_WR), and

Socket n RX Read Pointer Register (Sn_RX_RD).

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

Res

Res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

Res

Res

res

res

Res

res

res

res

res

res

Sn_IR[4:0]

R R R R

R

Sn_IR (Socket n Interrupt Register)

Address Offset : 0x0020

Reset value : 0x0000_0000

Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving

data, timeout). When an interrupt occurs and the corresponding bit of Sn_IMR is ‘1’, the

corresponding bit of Sn_IR becomes ‘1’.

[0] CONNECT Interrupt - This is issued one time when the connection with peer is successful

and then Sn_SR is changed to SOCK_ESTABLISHED

[1] DISCONNECT Interrupt - This is issued when FIN or FIN/ACK packet is received.

[2] RECV Interrupt - This is issued whenever data is received from a peer.

[3] TIMEOUT Interrupt - This is issued when ARPTO or TCPTO occurs.

[4] SENDOK Interrupt - This is issued when SEND command is completed

Sn_IMR (Socket n Interrupt Mask Register)

Address Offset : 0x0024

W7500x Reference Manual Version1.1.0 91 / 399

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

Res

Res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

Res

Res

res

res

res

res

res

res

res

res

Sn_IMR[4:0]

R/W

R/W

R/W

R/W

R/W

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

res

Res

Res

res

res

res

res

res

res

res

res

res

res

res

res

res

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1 0

res

Res

Res

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Sn_ICR[4:0]

Reset value: 0x0000_00FF

Sn_IMR is used to mask interrupts. Each bit of Sn_IMR corresponds to each bit of Sn_IR. When

a bit of Sn_IMR is ‘1’ and the corresponding bit of Sn_IR is ‘1’, an interrupt will be issued. In

other words, if a bit of Sn_IMR is ‘0’, an interrupt will not be issued even if the corresponding

bit of Sn_IR is ‘1’.

[0] CONNECT Interrupt Mask

0: Disable CONNECT Interrupt

1: Enable CONNECT Interrupt

[1] DISCONNECT Interrupt Mask

0: Disable DISCONNECT Interrupt

1: Enable DISCONNECT Interrupt

[2] RECV Interrupt Mask

0: Disable RECV Interrupt

1: Enable RECV Interrupt

[3] TIMEOUT Interrupt Mask

0: Disable TIMEOUT Interrupt

1: Enable TIMEOUT Interrupt

[4] SENDOK Interrupt Mask

0: Disable SENDOK Interrupt

1: Enable SENDOK Interrupt

Sn_ICR (Socket n Interrupt Clear Register)

Address Offset : 0x0028

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 92 / 399

R/W

R/W

R/W

R/W

R/W

R/W

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Sn_SR[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Value

Symbol

Description

0x00

SOCK_CLOSED

This indicates that Socket n is released.

When DISCON, CLOSE command is ordered, or when a timeout

occurs, it is changed to SOCK_CLOSED regardless of previous

status.

0x13

SOCK_INIT

This indicates Socket n is opened with TCP mode.

It is changed to SOCK_INIT when Sn_MR (P[3:0]) = ‘0001’ and

OPEN command is ordered.

After SOCK_INIT, user can use LISTEN /CONNECT command.

Sn_ICR is used to clear interrupts. Each bit of Sn_IR can be cleared when the host writes ‘1’

value to each bit of Sn_ICR corresponding to each bit of Sn_IR.

[0] CONNECT Interrupt Clear

[1] DISCONNECT Interrupt Clear

[2] RECV Interrupt Mask

[3] TIMEOUT Interrupt Mask

[4] SENDOK Interrupt Mask

* ReadClearWrite1 (R/C_W1) : Software can read as well as clear this bit by writing

1. Writing ‘0’ has no effect on the bit value.

Sn_SR (Socket n Status Register)

Address Offset : 0x0030

Reset value : 0x0000_0000

Sn_SR indicates the status of Socket n. The status of Socket n is changed by Sn_CR or some

special control packet as SYN, FIN packet in TCP.

W7500x Reference Manual Version1.1.0 93 / 399

0x14

SOCK_LISTEN

This indicates Socket n is operating as ‘TCP server’ mode and

waiting for connection-request (SYN packet) from a peer (‘TCP

client’).

It will change to SOCK_ESTALBLISHED when the connection-

request is successfully accepted.

Otherwise it will change to SOCK_CLOSED after TCPTO

occurred (Sn_IR(TIMEOUT) = ‘1’).

0x17

SOCK_ESTABLISHED

This indicates the status of the connection of Socket n.

It changes to SOCK_ESTABLISHED when the ‘TCP SERVER’

processed the SYN packet from the ‘TCP CLIENT’ during

SOCK_LISTEN, or when the CONNECT command is successful.

During SOCK_ESTABLISHED, DATA packet can be transferred

using SEND or RECV command.

0x1C

SOCK_CLOSE_WAIT

This indicates Socket n received the disconnect-request (FIN

packet) from the connected peer. This is half-closing status,

and data can be transferred. For full-closing, DISCON command

is used. But For just-closing, CLOSE command is used.

0x22

SOCK_UDP

This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0])

= ‘0010’).

It changes to SOCK_UDP when Sn_MR(P[3:0]) = ‘0010’) and

OPEN command is ordered.

Unlike TCP mode, data can be transfered without the

connection-process.

0x42

SOCK_MACRAW

This indicates Socket 0 is opened in MACRAW mode

(S0_MR(P[3:0]) = ‘0100’)and is valid only in Socket 0.

It changes to SOCK_MACRAW when S0_MR(P[3:0] = ‘0100’ and

OPEN command is ordered.

Like UDP mode socket, MACRAW mode Socket 0 can transfer a

MAC packet (Ethernet frame) without the connection-process.

Value

Symbol

Description

0x15

SOCK_SYNSENT

This indicates Socket n sent the connect-request packet

(SYN packet) to a peer.

The following table shows a temporary status indicated during changing the status of Socket

n.

W7500x Reference Manual Version1.1.0 94 / 399

It is temporarily shown when Sn_SR is changed from

SOCK_INIT to SOCK_ESTABLISHED by CONNECT command.

If connect-accept(SYN/ACK packet) is received from the

peer at SOCK_SYNSENT, it changes to SOCK_ESTABLISHED.

Otherwise, it changes to SOCK_CLOSED after TCPTO

(Sn_IR[TIMEOUT] = ‘1’) is occurred.

0x16

SOCK_SYNRECV

It indicates Socket n successfully received the connect-

request packet (SYN packet) from a peer.

If socket n sends the response (SYN/ACK packet) to the

peer successfully, it changes to SOCK_ESTABLISHED. If not,

it changes to SOCK_CLOSED after timeout occurs

(Sn_IR[TIMEOUT] = ‘1’).

0x18

SOCK_FIN_WAIT

These indicate Socket n is closing.

These are shown in disconnect-process such as active-close

and passive-close.

When Disconnect-process is successfully completed, or

when timeout occurs, these change to SOCK_CLOSED.

0x1A

SOCK_CLOSING

0X1B

SOCK_TIME_WAIT

0X1D

SOCK_LAST_ACK

This indicates Socket n is waiting for the response (FIN/ACK

packet) to the disconnect-request (FIN packet) by passive-

close.

It changes to SOCK_CLOSED when Socket n received the

response successfully, or when timeout occurs

(Sn_IR[TIMEOUT] = ‘1’).

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Sn_PNR[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Sn_PNR (Socket n Protocol Number Register)

Address Offset : 0x0100

Reset value : 0x0000_0000

This IP Protocol Register is user to set up the Protocol Field of IP Header at the IP layer RAW

mode. There are several protocol number defined in advance by registering to IANA. For the

W7500x Reference Manual Version1.1.0 95 / 399

overall list of upper level protocol identification number that IP is using, refer to online

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Sn_ROS[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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Sn_TTL[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

documents of IANA (http://www.iana.org/assignments/protocol-numbers).

Ex) Internet Control Message Protocol (ICMP) = 0x01, Internet Group Management Protocol =

0x02

Sn_TOSR (Socket n IP Type of Service Register)

Address Offset : 0x0104

Reset value : 0x0000_0000

Sn_TOSR configures the TOS(Type Of Service field in IP Header) of Socket n. It is set before

OPEN command.

For more the details, refer to http://www.iana.org/assignments/ip-parameters.

Sn_TTLR (Socket n TTL Register)

Address Offset : 0x0108

Reset value : 0x0000_0080

Sn_TTL configures the TTL(Time To Live field in IP Header) of Socket n. It is set before OPEN

command.

For more the details, refer to http://www.iana.org/assignments/ip-parameters.

W7500x Reference Manual Version1.1.0 96 / 399

Sn_FRAGR (Socket n Fragment offset Register)

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Sn_FRAG[15:0]

R/W

R/W

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R/W

R/W

R/W

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R/W

R/W

R/W

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R/W

R/W

Sn_FRAG[15:8]

Sn_FRAG[7:0]

0x00

0x00

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Sn_MSS[15:0]

R/W

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0x4101_0110

0x05B4

Address Offset : 0x010C

Reset value : 0x0000_4000

[15:0] Sn_FRAG configures the FRAG(Fragment field in IP header)

Ex) Sn_FRAGR = 0x0000 (Don’t Fragment)

Sn_MSSR (Socket n Maximum Segment Register)

Address Offset : 0x0110

Reset value : 0x0000_0000

This register is used for MSS (Maximum Segment Size) of TCP, and the register displays MSS set

by the other party when TCP is activated in Passive Mode.

Ex) In case of Socket 0 MSS = 1460 (0x05B4), configure as below,

W7500x Reference Manual Version1.1.0 97 / 399

Sn_PORTR (Socket n Source Port Register)

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Sn_PORT[15:0]

R/W

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R/W

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R/W

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R/W

0x4101_0114

0x1388

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16

Sn_DHAR0[31:24]

Sn_DHAR0 [23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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R/W

R/W

R/W

R/W

R/W

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Sn_DHAR0 [15:8]

Sn_DHAR0 [7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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Sn_DHAR1 [31:24]

Sn_DHAR1 [23:16]

R R R R R R R R R R R R R R R R

Address Offset : 0x0114

Reset value : 0x0000_0000

Sn_PORTR configures the source port number of Socket n. It is valid when Socket n is used in

TCP/UDP mode. It should be set before OPEN command is ordered.

Ex) In case of Socket 0 Port = 5000(0x1388), configure as below,

Sn_DHAR (Socket n Destination Hardware address Register)

Address Offset : 0x0118

Reset value : 0x0000_0000

Address Offset : 0x011E

Reset value : 0x0000_0000

Address Offset : 0x011C

Reset value : 0x0000_0000

W7500x Reference Manual Version1.1.0 98 / 399

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Sn_DHAR1 [15:8]

Sn_DHAR1 [7:0]

W W W W W W W W W W W W W W W

W

Sn_DHAR0

[31:24]

Sn_DHAR0

[23:16]

Sn_DHAR0

[15:8]

Sn_DHAR0

[7:0]

Sn_DHAR1

[15:8]

Sn_DHAR1

[7:0]

0x00

0x08

0xDC

0x12

0x34

0x56

Sn_DHAR0

[31:24]

Sn_DHAR0

[23:16]

Sn_DHAR0

[15:8]

Sn_DHAR0

[7:0]

Sn_DHAR1

[31:24]

Sn_DHAR1

[23:16]

0x00

0x08

0xDC

0x12

0x34

0x56

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Sn_DPROT[15:0]

R/W

R/W

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R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC

command in UDP mode or it indicates that it is acquired in ARP-process by CONNECT/SEND

command.

Ex) In case of writing MAC address “00.08.DC.12.34.56”

Ex) In case of reading MAC address “00.08.DC.12.34.56”

Sn_DPORTR (Socket n Destination Port Number Register)

Address Offset : 0x0120

Reset value : 0x0000_0000

Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when

Socket n is used in TCP/UDP mode.

W7500x Reference Manual Version1.1.0 99 / 399

In TCP client mode, it configures the listen port number of ‘TCP server’ before CONNECT

0x4101_0120

0x1388

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Sn_DIPR[31:24]

Sn_DIPR [23:16]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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Sn_DIPR [15:8]

Sn_DIPR [7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Sn_DIPR[31:24]

Sn_DIPR [23:16]

Sn_DIPR [15:8]

Sn_DIPR [7:0]

192 (0xC0)

168 (0xA8)

0 (0x00)

2 (0x02)

command.

In TCP server mode, it indicates the port number of ‘TCP client’ after successfully establishing

connection.

In UDP mode, it configures the port number of peer to be transmitted the UDP packet by

SEND/SEND_MAC command.

Ex) In case of Socket 0 Destination Port = 5000(0x1388), configure as below,

Sn_DIPR (Socket n Destination IP address Register)

Address Offset : 0x0124

Reset value : 0x0000_0000

Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket

n is used in TCP/UDP mode.

In TCP client mode, it configures an IP address of ‘TCP server’ before CONNECT command.

In TCP server mode, it indicates an IP address of ‘TCP client’ after successfully establishing

connection.

In UDP mode, it configures an IP address of peer to be received the UDP packet by S END or

SEND_MAC command.

Ex) In case of “192.168.0.2”

W7500x Reference Manual Version1.1.0 100 / 399