Wistron NeWeb SWA51 User Manual

SWA51, 5GHz Module Datasheet

General Description

The SWA51 module is a member of a family of
products representing a new level of system
integration offering customers fast time to
market with a point-to-point mono, or stereo,
wireless connection. These modules are
optimized for low-cost, high-quality and ease-of­use.

The module incorporates Avnera’s proprietary
5GHz wireless audio protocol, designed from the
ground up specifically for audio. It features low
fixed latency, uncompressed CD quality mono or
stereo audio, superior interference immunity,
and inherent coexistence with WiFi.

The SWA51 module integrates all features
necessary to complete a wireless stereo or
mono link, including AV5100 Wireless Audio
Chip, printed diversity antennas, PA, shield can,
flash memory, interface connector and all
passive components. Just provide power and an
I2S interface and you are ready to create a
wireless audio link.

The module measures 26 x 47 x 3.3 mm and is
provided with a 24 pin FPC connector.

The module is certified to FCC and CE
standards.

Extended Range Mono/Stereo Wireless Audio System, based on the Avnera AV5100 IC

Features

 Audio Interfaces

 I2S Digital Input / Output interface with

>93dB end-to-end digit al audio path

 Wireless Range (Typ)

 > 50m Non Line Of Sight (NLOS) range
 > 160m Line Of Sight (LOS) range

 Frequency range: 5.15-5.25&5.725-5.825 GHz,

continuous dynamic channel selection

 Forward error correction coding, error

detection, and audio-specific error
concealment

 Dual printed PCB diversity antennas for

multipath and fading mitigation

 Auto-search/synch and dynamic channel

selection

 Low, fixed latency
 24 pin FPC or pin header connector
 Sample rate converter: Support for 32 - 96kHz

input sample rates

 Customizable firmware for simple, low-cost,

sub-woofer amplifier implementations

Applications

 Wireless Subwoofers
 Stereo Wireless Rear Speakers
 Soundbar / Audio Video Receiver / BluRay
 Mono/Stereo Audio Channel Transmission

Ordering Options

SWA51 TX: Transmit module with digital audio
input

SWA51 RX: Receive module with digital audio
output

 RF parts can-shielded, module meets FCC

part 15 rules for emissions and susceptibility.

 General purpose over-the-air (OTA) serial

interface:

 11 kbps, bi-directional, full duplex
 Support for amplifier control data, meta-

data, and remote control commands

Different labels and P/Ns are used to
distinguish between TX and RX.

CONFIDENTIAL | PROVIDED UNDER NDA

SWA51 Module Datasheet Rev 1.1

1 Functional Description

The SWA51 module is available in 2 variations; digital input transmitter module or digital output receiver
module.

There are three available I2S digital audio data inputs/outputs, each of these can be configured to operate as
either a master or a slave - depending on the application, the I2S ports can oper ate simultaneously as either
inputs or outputs. When configured as slaves, the I2S inputs/outputs can be inde pendently clocked by up to
two external masters. In addition, MCLK can be output from the module to provide a reference clock source to
an external ADC or DAC. MCLK can also be input to the module to provide a reference clock from an
external source.

The hardware for the audio input (transmit) a nd audio output (re ceive) versions of the module is id entical and
only the firmware loaded onto the module determines its function.

The highly integrated nature of the AV5100 transceiver IC results in few external components being required
for the SWA51 module design. 2 pr inted PCB antennas are u sed to achieve increased range, a nd to achieve
antenna spatial diversity. The extended-range RF path consists of the antennas, associated tuning
components, shield can, the RF switch, and two baluns, one connected to each of the RF input/output ports
on the AV5100 IC.

A 16MHz crystal oscillator generates the AV5100 fundamental system clock used as the basis for all RF and
digital audio clocks.

A 2Mb flash memory chip is used to store the module’s application firmware. The AV5100 is able to boot from
internal ROM upon first power up, which enables programming the flash chip with the application fir m ware . In
addition, Over-the-air Firmware upgrade capability can be enabled through the application firmware. The
module can be controlled from an external host device via the I2C Slave or the SPI Slave data interfaces. The
I2C master port allows the module to control other system audio devices such as a sub-woofer amplifier
system without having to add another MCU to the product design. Up to 9 additional GPIOs are available on
the SWA51 module (not including I2C and I2S signals) fo r implementing different UI features on the target
application. The resources mentioned above can be lever aged to implement low cost sub-woofer d esigns as
outlined below.

CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 2 CONFIDENTIAL

SWA51 Module Datasheet Rev 1.1

1.1 SWA51 Module Connections and Interfaces

Signal Type Description

+3.3V Supply
Reset

I2S In Port

I2S Out Port

I2C Slave Port

I2C Master Port

The SWA51 hardware is configured to accept a nominal +3.3V supply.
Active low reset input. This pin is driven from an open collector/drain device such

that it can be pulled to ground for the active r eset state b ut, when r eleased , mu st
go to a high impedance state. This pin should not be actively driven high, as the
AV5100 internal reset circuit will not operate correctly.

The I2S input port can be co nfigured as a master or slave. Conse quently BCLK
and LRCK can be either inputs or outputs. In addition, MCLK can be sourced by
the module on pin 16. Since the AV5100 IC contains a sample rate converter,
MCLK is not required to be supplied to the module when it is an I2S slave.
CMOS 3.3V logic levels are used for all I2S signals.

The I2S output port can be configured as a master or slave. Conseq uently BCLK
and LRCK can be either inputs or outputs. In addition, MCLK can be sourced by
the module on pin 16. Since the AV5100 IC contains a sample rate converter,
MCLK is not required to be supplied to the module when it is an I2S slave.
CMOS 3.3V logic levels are used for all I2S signals.

The I2C slave port can be used for external host com munication and for module
testing. It is assumed that external pull up resistors are connected at the I2C
master communicating with the module.

The I2C master port is used to communicate with external audio devices such as
a sub-woofer amplifier. It is assumed that external pull up resistors are included
on the application board.

GPIOs

3.3V CMOS logic level GPIOs available to connect to other devices, or to use as
UI supporting GPIOs for LED and button support. All supported GPIOs can be
configured as outputs or inputs with configurable pull-ups/pull-downs.

CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 3 CONFIDENTIAL

SWA51 Module Datasheet Rev 1.1

2 SWA51 Connector Information

Table 1: SWA51 Connector Information

No Pin Name

Pin

AV5100 Pin

Type

1 GPIO2/S_SSB

Digital

12

I/O

2 GPIO3/S_SCLK

Digital

11

I/O

3 GPIO4/S_SDA/S_MOSI

Digital

10

I/O

4

GPIO5/S_SCL/S_MISO

Digital

9

I/O

5 GPIO16/M_SDA

Digital

4

I/O

6 GPIO17/M_SCL

Digital

3

I/O

7 GPIO20/LINK_LED

Digital

56

I/O

8 GPIO21/PAIR

Digital

55

I/O

9 GPIO18/BCLK1

Digital

2

I/O

10 GPIO19/WCLK1

Digital

1

I/O

11 GPIO10/MCLK

Digital

53

I/O
12 GND GND Paddle (57) GND GND
13 GPIO11/BCLK0

Digital

52

I/O
14 GPIO12/WCLK0

Digital

51

I/O

15 GPIO13/ADAT0

Digital

50

I/O

16 GPIO14/ADAT1

Digital

49

I/O

17 GPIO15/ADAT2/CEN

Digital

48 or 38
I/O or
Digital
Input

SWA51-TX Pin
Description

GPIO or SPI
Slave Chip
Select

GPIO or SPI
Slave Serial
Clock

GPIO, I2C
Slave Serial
Data or SPI
Slave Data In

GPIO, I2C
Slave Serial
Clock or SPI
Slave Data Out

GPIO, I2C
Master Serial
Data

GPIO, I2C
Master Serial
Clock

GPIO, or
LINK_LED
Output

GPIO, or input
from PAIR
Button

GPIO or I2S
Port 1 Bit Clock

GPIO or I2S
Port 1 Word
Clock

GPIO or Master
Clock Out

GPIO or I2S
Port 0 Bit Clock

GPIO or I2S
Port 0 Word
Clock

GPIO or I2S
Port 0 Audio
Data

GPIO or I2S
Port 1 Audio
Data

GPIO, I2S Port
2 Audio Data or
chip enable

1)

(

SWA51-RX Pin
Description

GPIO or SPI
Slave Chip
Select

GPIO or SPI
Slave Serial
Clock

GPIO, I2C
Slave Serial
Data or SPI
Slave Data In

GPIO, I2C
Slave Serial
Clock or SPI
Slave Data Out

GPIO, I2C
Master Serial
Data

GPIO, I2C
Master Serial
Clock

GPIO, or
LINK_LED
Output

GPIO, or input
from PAIR
Button

GPIO or I2S
Port 1 Bit Clock

GPIO or I2S
Port 1 Word
Clock

GPIO or Master
Clock Out

GPIO or I2S
Port 0 Bit Clock

GPIO or I2S
Port 0 Word
Clock

GPIO or I2S
Port 0 Audio
Data

GPIO or I2S
Port 1 Audio
Data

GPIO, I2S Port
2 Audio Data or
chip enable

1)

(

CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 4 CONFIDENTIAL

SWA51 Module Datasheet Rev 1.1

18 GPIO22/D+

19 GPIO23/D-

20 GPIO24

Digital
I/O

Digital
I/O

Digital

47 or 43

46 or 42

41

GPIO or USB
Data Plus

)

(2

GPIO or USB
Data Minus

)

(3

GPIO

GPIO

)

(2

GPIO or USB
Data Plus

)

(2

GPIO or USB
Data Minus

)

(3

)

(2

I/O

21 RESETN_EXT

Digital
Input

37

RESET signal
active low

)

(4

RESET signal
active low

)

(4

22 GND GND Paddle (57) GND GND
23 VDD

24 VDD

Supply
Input

Supply
Input

31, 45, 54

31, 45, 54

+3.3Vinput

supplyvoltage

+3.3Vinput

supplyvoltage

+3.3Vinput

supplyvoltage

+3.3Vinput

supplyvoltage

Notes:

(1) Pin 17 is hardware configured as GPIO15/ADAT2 by default; utilizing this pin as a CEN requires a

different stuffing option.
(2) Utilizing pins 18 and 19 as USB D+ and D- requires the firmware to Tri-stat e GPIOs 22 and 23.
(3) Pin 20 (GPIO24) can be utilized to implement a “Data Waiting” interrupt signal for I2C and SPI Slave

data communication.
(4) Pin 21 (RESET_EXT) can be pulled to GND with a switch or an open drain/collector type device to

provide a hard reset signal to the AV5100. This pin is pulled up to VDDIO (3.3V) internally in the

AV5100 and should not be actively driven high.

CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 5 CONFIDENTIAL

SWA51 Module Datasheet Rev 1.1

3 Electrical, Audio and Timing Specifications

3.1 Absolute Maximum Ratings

Absolute Maximum Ratings (AMR) are stress ratings only. AMR corresponds to the maximum value that can be applied without leading to
instantaneous or very short-term unrecoverable hard failure (destructive breakdown). Stresses beyond those listed under AMR may
cause permanent damage to the device.

Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Range” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may adversely affect device reliability.

Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test
conditions specified.

CONDITION MIN MAX

+3.3V Supply Voltage Input -0.3V 4.0V
Input Voltage Range – Digital

Inputs
Input Voltage Range – Analog

Inputs
Operating Temperature -40ºC +60ºC
Storage Temperature -40ºC +70ºC
Static Discharge Voltage1 2kV ----

-0.3V 3.6V

-0.3V 3.6V

Notes:

1)HBM=ESDHumanBodyModel;C=100pF,R=1kΩ

3.2 Recommended Operating Range

PARAMETER MIN TYP MAX UNIT

VDD, +3.3V Supply pin voltage 3.0 3.3 3.6 V
Ambient Temperature (TA) 0 55 ºC
RESET pin hold time 10 msec
Power Supply Rise Time (to 3.0V) 0 10 msec

3.3 Electrical Characteristics – DC Characteristics

OperatingConditions:VDD=3.3V,TA=0°Cto+55°C,RFFreq=5150‐5250;5725‐5825MHz,measuredrelativetotheRFbalun

single‐endedI/O.TypicalspecificationsatT

A=25°C,VDD=3.3V

PARAMETER CONDITIONS MIN TYP MAX UNIT

Supply Current (IVDDA)

Shutdown (chip disabled)
Standby (also USB suspend)
RX mode (continuous RX)
Link mode ( for SWA51 TX)

TBD
TBD

89
110*a

1

2.5

uA

mA
mA
mA

CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 6 CONFIDENTIAL