Wistron Winery13 Calpella Dis N11M-GE1 Schematic

5

D D

4

3

2

1

Winery13 CALPELLA DIS N11M-GE1 Schematics

uFCPGA Mobile Arrandale

Intel Ibex Peak-M

C C

2010-01-13

REV : A00

B B

DY : Nopop Component

UMA : Pop when schematic is UMA DIS : Pop when schematic is DIS

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

1

1 88Wednesday, January 13, 2010

A00

5

inery CALPELLA Block Diagram

W

P

CB LAYER

L1: Top L2: GND L

D D

3: Signal L4: Signal L5: VCC L6: Signal L7: GND

Clock Generator

SLG8SP585

4

7

3

P

roject code : 91.4EX01.001 Part Number : 48.4EX01.001 PCB P/N : 09288 Revision : A00

2

1

PU DC/DC

C

SL62883

I

R

T8205B

O

+

+15V_ALW +3.3V_RTC_LDO +5V_ALW +3.3V_ALW

I

NPUTS

+

PWR_SRC

S

YSTEM DC/DC

NPUTS

I

+PWR_SRC

UTPUTS

VCC_CORE

UTPUTS

O

4

7,48

4

6

L8: Bottom

100MHz/

74

2.5Gbps

Bandwidth :8GB

RGB CRT

LVDS

PCIe x 16

2.5 GT/s 2.7 GT/s

RGB CRT

LVDS

VRAM(gDDR3)

64Mbx16x4 (512MB)

C C

LCD (Single Chanel)

CRT

4

84,85

RGB CRT

55

LVDS

54

Nvidia

VRAM

N11M-GE1(40nm)

Switchable

LVDS

80,81,82,83

RGB CRT

Intel CPU

Arrandale

8,9,10,11,12,13,14

DMIx4 FDI(UMA)

Intel

PCH

CardReader

(3 in 1) SD/MMC/MMC+

B B

CAMERA

73

33

REALTEK RTS5138

USB2.0 x 1

USB 2.0

480Mbps

32

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6)

PCIE ports (8)

LPC I/F

ACPI 1.1

PCI/PCI BRIDGE

DDRIII 1066 Channel A

800/1066MHz

DDR III 1066 Channel B

800/1066MHz

PCIE x 1

100MHz

2.5Gbps

PCIE

USB 2.0

480Mbps

SM Bus

400KHz

LPC Bus

DDRIII 1066

PCIE x 1 & USB 2.0 x 1

10/100/1000LOM

RTL8111DL

(On daughter board)

Free fall sensor

33MHz

Digital Mic Array

Azalia CODEC

MIC IN

OP AMP

HP OUT

A A

1CH SPEAKER

60

5

IDT 92HD81UA

30

AZALIA

24MHz

4

USB,ESATA Multi-Port x1

20,21,22,23,24 ,25,26,27,28

SATA

SATA,USB

ODD HDD

63

59

3Gbps

SPI

Flash ROM

4MB

62

SPI

Flash ROM

256kB

3

KBC

NUVOTON

NPCE781BA0DX

Touch PAD

62 68

Int. KB

68

37

USB 2.0 x 2

SM Bus

Slot 0

18

Slot 1

19

35

USB 2.0 x 1

40

Thermal & Fan

EMC2102

Capacity Board

2

(FPC Cable to Connect)

PCIE x 1

USB 2.0 x 1

PCIE x 1

USB 2.0 x 1

39,58

78

SYSTEM DC/DC

Power SW

TPS2231R

New Card

RJ45 CONN

Mini-Card

WWAN/ WiMAX?

Left Side: USB x 1

34

TPS51116

OUTPUTSINPUTS

+PWR_SRC

+1.5V_SUS +0.75V_DDR_VTT +V_DDR_REF

SYSTEM DC/DC

ADP3211

OUTPUTSINPUTS

+PWR_SRC +CPU_GFXCORE

SYSTEM DC/DC

TPS51218

INPUTS

+PWR_SRC

OUTPUTS

+VCC_GFX_CORE

CHARGER

Mini-Card

WLAN 802.11a/b/g/n

Right Side: USB x 1

Bluetooth

Biometric

64

63

73

78

BQ24745

INPUTS

+DC_IN +PBATT

OUTPUTS

+PWR_SRC

SYSTEM DC/DC

TPS51218

OUTPUTSINPUTS

+PWR_SRC

+1.05V_VTT

LDO

APL5930

INPUTS

OUTPUTS

+1.8V_RUN+3.3V_ALW

LDO

RT9025

2 88Wednesday, January 13, 2010

OUTPUTS

+1.8V_RUN_GPU+3.3V_ALW

INPUTS

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

1

50

53

86

45

49

51

A00

5

D D

PWR_SRC

A

dapter

AO4407A

45

+

Charger

BQ24745

Battery

+PBATT

45

RT8205B

C C

+5V_ALW

+15V_ALW

+5V_ALW2

+3.3V_ALW_2

+3.3V_RTC_LDO

4

ISL62883

+VCC_CORE

46

+5V_ALW

3

47、48 86

ADP3211

53

+CPU_GFXCORE

TPS51218

+VCC_GFX_CORE

For NVIDIA GPUFor Intel GPU

+3.3V_ALW

2

TPS51218DSCR

+1.05V_VTT

Arrandale : 1.05V

FDS8880

+1.05V_GFX_PCIE

87

1

PS51116PWPRG4

T

49

FDS8880

50

+0.75V_DDR_VTT+V_DDR_REF

87

+1.5V_SUS

+1.5V_RUN_GPU

AO3420

52

AO4468

42

+1.5V_CPU

+1.5V_RUN

TPS2062AD

+5V_USB2

B B

For USB2 For USB1 & ESATA1

AO4468

+5V_RUN

42I/O BD

TPS2062AD

+5V_USB1

63

AO3403

+3.3V_LAN

RTL8111DL

I/O BD

+1.2V_LOM

TPS2231R

34

SI3456BDV

+LCDVDD

AO4468

+3.3V_RUN+3.3V_CARDAUX

54

APL5930

42

+1.8V_RUN

TPS2231R

+3.3V_CARD

RT9025

51

+1.8V_RUN_GPU

34

51I/O BD

AO3434

+3.3V_RUN_GPU

87

TPS2231R

+1.5V_CARD

34

Power Shape

Regulator LDO Switch

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

Power Block Diagram

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

3 88Wednesday, January 13, 2010

1

A00

5

CH SMBus Block Diagram

P

3.3V_ALW

+

‧

S

RN2K2J-1-GP

P

CH

D D

MBCLK

S

SMBDATA

MB_CLK

S

SMB_DATA

23

‧

2N7002SPT

+

3.3V_RUN

‧

3.3V_RUN

+

‧

S

PCH_SMBCLK

PCH_SMBDATA

PCH_SMBCLK PCH_SMBDATA

Express Card

SMB_CLK

SMB_DATA

C C

PCH_SMBCLK

‧

PCH_SMBDATA

‧

34

PCH_SMBCLK

‧

PCH_SMBDATA

‧

PCH_SMBCLK

‧

PCH_SMBDATA

‧

KBC SMBus Block Diagram

+5V_RUN

‧

SRN10KJ-5-GP

TPDATA

PSDAT1

TPCLK

B B

PSCLK1

+3.3V_RTC_LDO

‧

SRN4K7J-8-GP

BAT_SCL

SCL1

SDA1

BAT_SDA

‧

SRN100J-3-GP

TouchPad Conn.

TPDATA

TPCLK

SMBus address:12

PBAT_SMBCLK1

PBAT_SMBDAT1

Battery Conn.

CLK_SMB

DAT_SMB

SMBus address:16

4

RN2K2J-1-GP

D

IMM 1

S

CL

SDA

MBus Address:A0

S

DIMM 2

SCL

SDA

SMBus Address:A2

Clock Generator

SMBCLK SMBDATA

SMBus address:D2

Minicard WLAN

SMB_CLK

SMB_DATA

Minicard WWAN

SMB_CLK SMB_DATA

Free fall sensor

SCL/SPC SDA/SDI/SDO

BQ24745

SCL SDA

3

witchable Graphic SMBus Block Diagram

S

+

3.3V_RUN

P

CH

RN2K2J-1-GP

S

L_DDC_CLK

L

DDC_CLK

L_DDC_DATA

LDDC_DATA

SRN2K2J-1-GP

GMCH_DDCCLK CRT_CLK_DDC

I/O BD

18

19

07

64

40

L_DDC_CLK

L_DDC_DATA

CRT_DDC_CLK

CRT_DDC_DATA

N11M-GE1

I2CC_SCL

I2CC_SDA

68

45

44

I2CA_SCL

I2CA_SDA

GMCH_DDCDATA CRT_DAT_DDC

‧

+3.3V_RUN

‧

3.3V_RUN

‧

+3.3V_RUN

‧

S

RN2K2J-1-GP

B

1

B0

GND

NC7SB3157P6X-1GP

B1

B0

GND

NC7SB3157P6X-1GP

‧

B1

B0

GND

NC7SB3157P6X-1GP

B1

B0

‧

GND

NC7SB3157P6X-1GP

+

3.3V_RUN

VCC

A

S

+3.3V_RUN

VCC

A

S

SRN2K2J-1-GP

+3.3V_RUN

VCC

DDC_CLK_CON2

A

S

+3.3V_RUN

VCC

DDC_DATA_CON2

A

S

2

+

3.3V_RUN

‧

SRN2K2J-1-GP

LDDC_CLK_CON

LDDC_DATA_CON

+3.3V_RUN

‧

DY

‧

Remove HDMI

LCD Conn.

+3.3V_RUN_GPU

2N7002DW-1-GP

54

‧

DDC_CLK_CON

DDC_DATA_CON

+5V_CRT_RUN

‧

SRN2K2J-1-GP

‧

1

CRT CONN

55

KBC

KBC_SCL1

KBC_SDA1

+3.3V_RTC_LDO

‧

SRN4K7J-8-GP

‧

5

2N7002DW-1-GP

NPCE781

A A

GPIO73/SCL2

GPIO74/SDA2

+3.3V_RUN

‧

+3.3V_RUN

‧

SRN4K7J-8-GP

THERM_SCL

THERM_SDA

THERM_SCL

THERM_SDA

Thermal

SMCLK

SMDATA

SMBus address:7A

39

Capacity Board

SCL

(On daughter board)

SDA

SMBus address:0A

4

IFPC_AUX_I2CW_SCL

IFPC_AUX_I2CW_SDA#

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

Date: Sheet of

3

2

Date: Sheet of

SMBUS Block Diagram

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

4 88Wednesday, January 13, 2010

1

A00

A

B

C

D

E

T

hermal Block Diagram

1 1

A

udio Block Diagram

SPEAKER

SPKR_PORT_D_L-

SPKR_PORT_D_L+

DP1

EMC2102_DP1

2 2

DN1

EMC2102_DN1

Thermal

SC470P50V3JN-2GP

Close to PCH

EMC2102

DP2

VGA_THERMDA

SC470P50V3JN-2GP

DN2

VGA_THERMDC

3 3

DPLUS

DMINUS

Q3905

GPU

MMBT3904-3-GP

54

DIS

HP1_PORT_B_L

HP1_PORT_B_R

Codec 92HD81

HP0_PORT_A_L

HP0_PORT_A_R

VREFOUT_A_OR_F

AUD_SPK_L-

AUD_SPK_L+

0R3-0-U-V-GP

AUD_HP1_JACK_L

AUD_HP1_JACK_R

AUD_EXT_MIC_L

AUD_EXT_MIC_R

AUD_VREFOUT_B

AUD_SPK_L-_C

AUD_SPK_L+_C

60

HP

OUT

60

MIC

IN

60

DP3

T8_THERMDC

DN3

T8_THERMDA

39

4 4

A

SC470P50V3JN-2GP

HW T8 sensor

B

MMBT3904-3-GP

Q3901

C

DMIC_CLK/GPIO1

DMIC0/GPIO2

AUD_DMIC_CLK

AUD_DMIC_IN0

30

33R2J-2-GP

33R2J-2-GP AUD_DMIC_IN0_R

D

AUD_DMIC_CLK_G

1st Samsung

Title

Thermal/Audio Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Digital MIC Array

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

73

5 88Wednesday, January 13, 2010

A00

A

CH Strapping

P

N

ame

S

PKR

4 4

GNT3#/ GPIO55

INTVRMEN

GNT0#, GNT1#

GNT2#/ GPIO53

3 3

SPI_MOSI

NV_ALE

HAD_DOCK_EN# /GPIO[33]

2 2

HDA_SDO

HDA_SYNC

GPIO15

S

chematics Notes

Reboot option at power-up

Internal weak P ull-down.

Default Mode:

Connect to Vcc3_3 with 8. 2-kΩ

No Reboot Mode with TCO Disab led:

- 10-kΩ weak pull-up resistor.

nternal pull-up. Leave as "No Connect"INIT3_3V#

I

Internal pull-u p.

Default Mode: Low (0) = Top Block Swap Mode

Note: Connect to ground with 4.7-k CRB uses a 1 k

High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is d isabled Note:

CRB uses a 330-kΩ resistor.

Leave both GNT 0# and GNT1# floating. No pull up

Default (SPI):

required.

Boot from PCI:

Connect both G NT0# and GNT1# to ground with 1-kΩ

Boot from LPC:

pull-down resistor.

Default - Internal pull-up.

= Configures DMI for E SI compatible operation (for s ervers

Low (0)

only. Not for mobile/desktops ).

Connect to Vcc3_3

Enable Intel Anti-Theft Techn ology:

with 8.2-kΩ weak pull-up resis tor. Left floating, no pull- down

Disable Intel Anti-Theft Tech nology:

required.

Connect to +NVRAM_Vccq w ith

Enable Intel Anti-Theft Techn ology:

8.2-kΩ weak pull-up resistor.[ CRB has it pulled up with 1-kΩ no-stuff resistor] Leave floating (interna l pull-down)

Disable Intel Anti-Theft Tech nology:

DMI termination voltage. Weak internal pull-up. Do not pull low.NC_CLE

Flash Descriptor Sec urity will be overridden. Also , when

Low (0)-

this signals is sampled on th e rising edge of PWROK then it will also disable Intel ME and its feat ures. Security measure de fined in the Flash Descriptor

High (1)-:

will be enabled.

Platform design should provid e appropriate pull-up or pull- down depending on the desired sett ings. If a jumper option is us ed to tie this signal to GND as req uired by the functional strap, the signal should be pulled l ow through a weak pull-down in order to avoid asserting HDA_DOCK_E N# inadvertently.

Note:

CRB recommends 1-kΩ pull- down for FD Override. There is an internal pull-up of 20 kΩ for HDA_DOCK_EN# which is only enabled at boot/reset for str apping functions.

Weak internal pull-down. Do n ot pull high. Sampled at rising edge of RSM RST#.

Intel ME Crypto Trans port Layer Security (TLS) ciph er suite

Low (0)-

with no confidentiality Intel ME Crypto Tra nsport Layer Security (TLS) ci pher suite

High (1)-:

with confidentiality

Note:

This is an unmuxed signal. This signal has a weak intern al pull-down of 20 KΩ which is enabled when PWROK is low. Sampled at rising edge of RSM RST#. CRB has a 1-kΩ pull-up on this signal to +3.3VA rail.

Calpella Schematic Checklist Rev1.6

I

ntel suggest 1K resistor (Fon seca)

Ω; do not stuff resistor.

Connect GNT1# to ground with 1-kΩ pull-down resistor. Leave GNT0# Floatin g.

Ω weak pull-down resistor.

B

C

rocessor Strapping

P

in Name

P

C

FG[4]

FG[3]

C

CFG[0]

trap Description

S

Embedded DisplayPort Presence

PCI-Express Static Lane Reversal

PCI-Express Configuration Select

D

alpella Schematic Checklist Rev1.6

C

onfiguration (Default value for each bit is

C 1 unless specified otherwise)

Disabled - No Physical Dis play Port attached to

1:

Embedded DisplayPort.

Enabled - An external Disp lay Port device is

0:

connected to the Embedded Dis play Port.

Normal Operation.

1:

Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Single PCI-Express Graphic s

1:

Bifurcation enabled

0:

efault

D Value

1

E

PCIE Routing

LANE1

LANE2

LANE3 LAN

Card reader

MiniCard WLAN

MiniCard WWANLANE4

New CardLANE5

USB Table

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

USB

Device

USB1

USB for ESATA

USB2

RESERVE

WLAN

WWAN

RESERVED

(Not available for HM55)

RESERVED

(Not available for HM55)

BlUETOOTH

Card Reader

Biometric

CAMERA

New Card

RESERVED

1st Samsung

1 1

GPIO8

GPIO27

Weak internal pull-up. Do not pull low. Sampled at rising edge of RSM RST#.

Default = Do not connect (flo ating). Internal pull-up.

High(1) = Enables the interna l VccVRM to have a clean suppl y for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM . Need to use on-board filter circuits for analog rails.

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

6 88Wednesday, January 13, 2010

A00

5

S

SID = Clock GEN

D D

4

3

2

1

+3.3V_RU N +3.3V_RU N_SL585

R708

1 2

0R0603-P AD-2-GP

12

C701

SC4D7P5 0V2CN-1GP

SC-1130-1 change C701 to 4 .7pF for RF

C C

C701

DY

12

C702

SC10U10V5ZY-1GP

12

C703

SCD1U10V2KX-5GP

A00-0104-1

RN701

DREFCLK #[23]

DREFCLK[23]

CLKIN_DMI#[23]

CLKIN_DMI[23]

CLK_PCIE_ SATA#[23]

CLK_PCIE_ SATA[23]

CLK_CPU _BCLK#[23]

CLK_CPU _BCLK[23]

B B

RN701 0R4P2R-P AD

0R4P2R-P AD

RN702

RN702 0R4P2R-P AD

0R4P2R-P AD

RN703

RN703 0R4P2R-P AD

0R4P2R-P AD

RN704

RN704 0R4P2R-P AD

0R4P2R-P AD

2 3 1

1 2 3

TP701TPA D14-GP T P701TPAD14-GP TP702TPA D14-GP T P702TPAD14-GP

CLK_MCH _DREFCLK1# CLK_MCH _DREFCLK1

4

CLK_IN_DM I#

RN

CLK_IN_DM I

4

CLK_PCIE_ SATA1#

RN

CLK_PCIE_ SATA1

4

CLK_CPU _BCLK1#

4

RN

CLK_CPU _BCLK1

TP_CPU_ 1#

1

TP_CPU_ 1

1

12

C704

SCD1U10V2KX-5GP

12

C705

SCD1U10V2KX-5GP

U701

4

DOT_96#

3

DOT_96

14

SRC_2#

13

SRC_2

11

SRC_1/SATA#

10

SRC_1/SATA

22

CPU_0#

23

CPU_0

19

CPU_1#

20

CPU_1

SLG8SP5 85VTR-GP

12

C708

C707

C708

SCD1U10V2KX-5GP

+3.3V_RU N_SL585 +1.05V_RUN _SL585_IO

24

VDD_CPU

GND

33

1st Silego 71.08585.003 2nd ICS 71.93197.003

+1.05V_V TT

R709

1 2

0R0603-P AD-2-GP

12

DY

SCD1U10V2KX-5GP

1

17

29

15

5

A00-0104-1A00-0104-1

C709

C709 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

18

12

C710

C710 SC10U10 V5ZY-1GP

SC10U10 V5ZY-1GP

12

VGA 27M

SS

VDD_27

VDD_REF

VDD_DOT

VDD_SRC

VSS_REF

21

26

VDD_SRC_IO

VDD_CPU_IO

27MHZ

27MHZ_SS

CPU_STOP#

CKPWRGD/PD#

REF_0/CPU_SEL

XTAL_IN

XTAL_OUT

SDA

SCL

VSS_DOT

VSS_278VSS_SATA

VSS_SRC

VSS_CPU

2

12

9

+1.05V_V TT

6 7

16 25 30

28 27

31 32

12

CLK_27M CLK_27M _SS

CPU_STO P# CK_PW RGD FSC

CLK_XTA L_IN CLK_XTA L_OUT

1 2

X-14D318 18M-37GP

C714

C714 SC12P50 V2JN-3GP

SC12P50 V2JN-3GP

NON-SS Mount DY

R706 33R2 J-2-GP

DY

R710 33R2 J-2-GP

DY

R701 2K2R 2J-2-GPR701 2K2R 2J-2-GP

R703 33R2 J-2-GPR703 33R2 J-2-GP

PCH_SMB DATA [18,19,23,40,6 4,76] PCH_SMB CLK [18,19,23,40 ,64,76]

X701

CLK_XTA L_IN

CLK_XTA L_OUT

12

C715

C715 SC12P50 V2JN-3GP

SC12P50 V2JN-3GP

1st: HARMONY 82.30005.901

R704

R704 4K7R2J-2 -GP

4K7R2J-2 -GP

R707

R707 10KR2J-3 -GP

10KR2J-3 -GP

DY

1 2

FSC

1 2

2nd: ITTI 82.30005.C51 3rd: TXC 82.30005.B81

FSC 0 1

SPEED

133MHz

(Default)

+1.05V_R UN_SL585_IO

C711

C711 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY Mount

12 12

12

100MHz

R710R706

+3.3V_RU N

12

DY

12

C712

C712 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

CLK_VGA _27M [81]

CLK_PCH _14M [23]

EC701

EC701 SC4D7P5 0V2CN-1GP

SC4D7P5 0V2CN-1GP

R705

R705 10KR2J-3 -GP

10KR2J-3 -GP

CK_PW RGD

CLK_VGA _27M

R749

DY

0R2J-2-GP

1 2

CLK_VGA_27M_RC

C718

DY

SC4D7P5 0V2CN-1GP

1 2

+3.3V_RU N_SL585

1 2

G

SD

Q701

Q701 2N7002A -7-GP

2N7002A -7-GP

1ST: 84.2N702.E31 2ND: 84.2N702.D31

VR_CLKE N# [47]

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Clock Generator SLG8SP585

Size Document N umber Rev

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

7 88Wednesd ay, January 13, 2010

1

A00

5

S

SID = CPU

4

3

2

1

D D

1

OF 9

C

PU1A

DMI_PTX_C RXN0[22] DMI_PTX_C RXN1[22] DMI_PTX_C RXN2[22] DMI_PTX_C RXN3[22]

DMI_PTX_C RXP0[22] DMI_PTX_C RXP1[22] DMI_PTX_C RXP2[22] DMI_PTX_C RXP3[22]

DMI_CTX_P RXN0[22] DMI_CTX_P RXN1[22] DMI_CTX_P RXN2[22] DMI_CTX_P RXN3[22]

DMI_CTX_P RXP0[22 ] DMI_CTX_P RXP1[22 ] DMI_CTX_P RXP2[22 ] DMI_CTX_P RXP3[22 ]

C C

B B

Calpella Platform Design Guide Revision 1.6

2.4 Arrandale Graphics Disable Guideline

FDI_FSYNC0[22] FDI_FSYNC1[22]

FDI_INT[22]

FDI_LSYNC0[22] FDI_LSYNC1[22]

Page 89

FDI_TXN0[22] FDI_TXN1[22] FDI_TXN2[22] FDI_TXN3[22] FDI_TXN4[22] FDI_TXN5[22] FDI_TXN6[22] FDI_TXN7[22]

FDI_TXP0[22] FDI_TXP1[22] FDI_TXP2[22] FDI_TXP3[22] FDI_TXP4[22] FDI_TXP5[22] FDI_TXP6[22] FDI_TXP7[22]

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

It applies to Arrandale and Clarksfield discrete graphic designs.

FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors).

A24 C23 B22 A21

B24 D23 B23 A22

D24 G24 F23 H23

D25 F24 E23 G23

E22 D21 D19 D18 G21 E19 F21 G18

D22 C21 D20 C18 G22 E20 F20 G19

F17 E17

C17

F18 D17

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI_TX#0 FDI_TX#1 FDI_TX#2 FDI_TX#3 FDI_TX#4 FDI_TX#5 FDI_TX#6 FDI_TX#7

FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

CLARKSFIELD

PCI EXPRESS -- GRAPHICS

OF 9

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

DMI

PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

Intel(R) FDI

PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_IRCOMP _R

EXP_RBIAS

PCIE_MRX_ GTX_N15 PCIE_MRX_ GTX_N14 PCIE_MRX_ GTX_N13 PCIE_MRX_ GTX_N12 PCIE_MRX_ GTX_N11 PCIE_MRX_ GTX_N10 PCIE_MRX_ GTX_N9 PCIE_MRX_ GTX_N8 PCIE_MRX_ GTX_N7 PCIE_MRX_ GTX_N6 PCIE_MRX_ GTX_N5 PCIE_MRX_ GTX_N4 PCIE_MRX_ GTX_N3 PCIE_MRX_ GTX_N2 PCIE_MRX_ GTX_N1 PCIE_MRX_ GTX_N0

PCIE_MRX_ GTX_P15 PCIE_MRX_ GTX_P14 PCIE_MRX_ GTX_P13 PCIE_MRX_ GTX_P12 PCIE_MRX_ GTX_P11 PCIE_MRX_ GTX_P10 PCIE_MRX_ GTX_P9 PCIE_MRX_ GTX_P8 PCIE_MRX_ GTX_P7 PCIE_MRX_ GTX_P6 PCIE_MRX_ GTX_P5 PCIE_MRX_ GTX_P4 PCIE_MRX_ GTX_P3 PCIE_MRX_ GTX_P2 PCIE_MRX_ GTX_P1 PCIE_MRX_ GTX_P0

PCIE_MTX_ GRX_C_N15 PCIE_MTX_ GRX_C_N14 PCIE_MTX_ GRX_C_N13 PCIE_MTX_ GRX_C_N12 PCIE_MTX_ GRX_C_N11 PCIE_MTX_ GRX_C_N10 PCIE_MTX_ GRX_C_N9 PCIE_MTX_ GRX_C_N8 PCIE_MTX_ GRX_C_N7 PCIE_MTX_ GRX_C_N6 PCIE_MTX_ GRX_C_N5 PCIE_MTX_ GRX_C_N4 PCIE_MTX_ GRX_C_N3 PCIE_MTX_ GRX_C_N2 PCIE_MTX_ GRX_C_N1 PCIE_MTX_ GRX_C_N0

PCIE_MTX_ GRX_C_P15 PCIE_MTX_ GRX_C_P14 PCIE_MTX_ GRX_C_P13 PCIE_MTX_ GRX_C_P12 PCIE_MTX_ GRX_C_P11 PCIE_MTX_ GRX_C_P10 PCIE_MTX_ GRX_C_P9 PCIE_MTX_ GRX_C_P8 PCIE_MTX_ GRX_C_P7 PCIE_MTX_ GRX_C_P6 PCIE_MTX_ GRX_C_P5 PCIE_MTX_ GRX_C_P4 PCIE_MTX_ GRX_C_P3 PCIE_MTX_ GRX_C_P2 PCIE_MTX_ GRX_C_P1 PCIE_MTX_ GRX_C_P0

R801 49D9 R2F-GPR801 49D9 R2F-GP

1 2

R802 750R 2F-GPR802 750R 2F-GP

1 2

PCIE_MRX_G TX_N[0..15]

PCIE_MRX_G TX_P[0..15]

C829 SCD1U10 V2KX-5GPC829 SCD1U10 V2KX-5GP

1 2

C827 SCD1U10 V2KX-5GPC827 SCD1U10 V2KX-5GP

1 2

C832 SCD1U10 V2KX-5GPC832 SCD1U10 V2KX-5GP

1 2

C812 SCD1U10 V2KX-5GPC812 SCD1U10 V2KX-5GP

1 2

C803 SCD1U10 V2KX-5GPC803 SCD1U10 V2KX-5GP

1 2

C811 SCD1U10 V2KX-5GPC811 SCD1U10 V2KX-5GP

1 2

C828 SCD1U10 V2KX-5GPC828 SCD1U10 V2KX-5GP

1 2

C810 SCD1U10 V2KX-5GPC810 SCD1U10 V2KX-5GP

1 2

C823 SCD1U10 V2KX-5GPC823 SCD1U10 V2KX-5GP

1 2

C804 SCD1U10 V2KX-5GPC804 SCD1U10 V2KX-5GP

1 2

C831 SCD1U10 V2KX-5GPC831 SCD1U10 V2KX-5GP

1 2

C825 SCD1U10 V2KX-5GPC825 SCD1U10 V2KX-5GP

1 2

C821 SCD1U10 V2KX-5GPC821 SCD1U10 V2KX-5GP

1 2

C813 SCD1U10 V2KX-5GPC813 SCD1U10 V2KX-5GP

1 2

C806 SCD1U10 V2KX-5GPC806 SCD1U10 V2KX-5GP

1 2

C816 SCD1U10 V2KX-5GPC816 SCD1U10 V2KX-5GP

1 2

C826 SCD1U10 V2KX-5GPC826 SCD1U10 V2KX-5GP

1 2

C822 SCD1U10 V2KX-5GPC822 SCD1U10 V2KX-5GP

1 2

C818 SCD1U10 V2KX-5GPC818 SCD1U10 V2KX-5GP

1 2

C815 SCD1U10 V2KX-5GPC815 SCD1U10 V2KX-5GP

1 2

C808 SCD1U10 V2KX-5GPC808 SCD1U10 V2KX-5GP

1 2

C802 SCD1U10 V2KX-5GPC802 SCD1U10 V2KX-5GP

1 2

C820 SCD1U10 V2KX-5GPC820 SCD1U10 V2KX-5GP

1 2

C805 SCD1U10 V2KX-5GPC805 SCD1U10 V2KX-5GP

1 2

C817 SCD1U10 V2KX-5GPC817 SCD1U10 V2KX-5GP

1 2

C801 SCD1U10 V2KX-5GPC801 SCD1U10 V2KX-5GP

1 2

C814 SCD1U10 V2KX-5GPC814 SCD1U10 V2KX-5GP

1 2

C824 SCD1U10 V2KX-5GPC824 SCD1U10 V2KX-5GP

1 2

C830 SCD1U10 V2KX-5GPC830 SCD1U10 V2KX-5GP

1 2

C809 SCD1U10 V2KX-5GPC809 SCD1U10 V2KX-5GP

1 2

C807 SCD1U10 V2KX-5GPC807 SCD1U10 V2KX-5GP

1 2

C819 SCD1U10 V2KX-5GPC819 SCD1U10 V2KX-5GP

1 2

PCIE_MRX_G TX_N[0..15] [80]

PCIE_MRX_G TX_P[0..15] [8 0]

PCIE_MTX_ GRX_N15 PCIE_MTX_ GRX_N14 PCIE_MTX_ GRX_N13 PCIE_MTX_ GRX_N12 PCIE_MTX_ GRX_N11 PCIE_MTX_ GRX_N10 PCIE_MTX_ GRX_N9 PCIE_MTX_ GRX_N8 PCIE_MTX_ GRX_N7 PCIE_MTX_ GRX_N6 PCIE_MTX_ GRX_N5 PCIE_MTX_ GRX_N4 PCIE_MTX_ GRX_N3 PCIE_MTX_ GRX_N2 PCIE_MTX_ GRX_N1 PCIE_MTX_ GRX_N0

PCIE_MTX_ GRX_P15 PCIE_MTX_ GRX_P14 PCIE_MTX_ GRX_P13 PCIE_MTX_ GRX_P12 PCIE_MTX_ GRX_P11 PCIE_MTX_ GRX_P10 PCIE_MTX_ GRX_P9 PCIE_MTX_ GRX_P8 PCIE_MTX_ GRX_P7 PCIE_MTX_ GRX_P6 PCIE_MTX_ GRX_P5 PCIE_MTX_ GRX_P4 PCIE_MTX_ GRX_P3 PCIE_MTX_ GRX_P2 PCIE_MTX_ GRX_P1 PCIE_MTX_ GRX_P0

PCIE_MTX_ GRX_N[0..15]

PCIE_MTX_ GRX_P[0..15]

PCIE_MTX_G RX_N[0..15] [80]

PCIE_MTX_G RX_P[0..15] [8 0]

CLARKUN F

1st Samsung

A A

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PCIE/DMI/FDI)

Size Document N umber Rev

Date: Sheet of

CPU (PCIE/DMI/FDI)

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

8 88Wednesd ay, January 13, 2010

A00

0

RN

A

4

1 2 3

4

00-0104-1

N903

R

R 0

0

R4P2R-PAD

4

RN905

SRN10KJ-5-GP

RN906

RN906 0R4P2R-PAD

0R4P2R-PAD

A00-0104-1

S

A

R

R SRN22J-7-GP

SRN22J-7-GP

SRN1KJ-7-GP

SRN1KJ-7-GP R

R

XDP_DBRESET# [22]

7/01 Check

1.assign GPIO EC_GPIO91 ??

N901

N904

RN

4

2

1.05V_VTT

+

1 23

Calpella Platform S3 Power Reduction Platform S3 Power Reduction CRB Implementation Design Details Revision 0.1

B

CLK_CPU_P [25]

B

CLK_CPU_N [25]

C

LK_EXP_P [23]

C

LK_EXP_N [23]

PM_EXTTS#0 [18] PM_EXTTS#1 [19]

S

B-1020-1

DY R935, POP C915,R934, Q901

DR_RST_GATE# [25]

D

C

915

12

SCD047U10V2KX-2GP

+

1.5V_SUS

12

R

934

1KR2J-1-GP

Q

901

BSS138-7-F-GP

G

Vgs(th)<=1.5V

R935

1 2

DY

0R2J-2-GP

DDR3 Compensation Signals

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

XDP_TDO_R

1KR2J-1-GP

DS

R907 100R2F-L1-GP-UR9 07 100R2F-L1-GP-U

1 2

R910 24D9R2F-L-GPR910 24D9R2F-L-GP

1 2

R911 130R2F-1-GPR911 130R2F-1-GP

1 2

R928

51R2J-2-GP

D

1ST: 84.00138.E31 2ND:

+1.05V_VTT

12

1

3.3V_ALW

+

DR_RST_GATE#

D

SB-1103 change Q901 to 84.00138.F31

DR3_DRAMRST# [18,19]

1 2

R

937 10KR2J-3-GP

SM_DRAMRST#

1 2

R988

R988 100KR2J-1-GP

100KR2J-1-GP

SB-1023 pop R988 for S3 reduce function

5

rocessor Compensation Signals

1.05V_VTT

+

Processor Pullups

902 49D9R2F-GP

R

1 2

R

933 68R2-GP

1 2

H

_CATERR#

_PROCHOT_R#

H

D D

SSID = CPU

H_PROCHOT#[47]

C C

H_PWRGOOD[25,42]

PM_DRAM_PWR GD[22]

H_VTTPWRGD[49]

P

1 2

R

901 20R2F-GP

1 2

903 20R2F-GP

R

1 2

R

905 49D9R2F-GP

1 2

906 49D9R2F-GP

R

T

P901TPAD14-GPTP901TPAD14-GP

R936

R936 0R2J-2-GP

0R2J-2-GP

1 2

DY

SB-1026

1. remove 1K ohm for remove XDP

PLT_RST#[21,34,36,37,64,70,76,80]

1

H_PECI[25]

H_THRMTRIP#[25,37,42]

TP902

TPAD14-GP

H_PM_SYNC[22]

TP903TPAD14-GP TP903TPAD14-GP

R913

1 2

1K6R2F-GP

S

H

H_PROCHOT_R#

TP_RESET_OBS#

1

TP_TAPPWRGOOD

1

H

KTOCC#_R

_CATERR#

H_PWRGOOD

12

4

_COMP3

_COMP2

_COMP1

_COMP0

PLT_RST#_R

R915

R915 750R2F-GP

750R2F-GP

AT23

AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

PU1B

C

OMP3

C

OMP2

C

OMP1

C

OMP0

S

KTOCC#

ATERR#

C

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPW RGOOD_1

VCCPW RGOOD_0

SM_DRAMPW ROK

VTTPWR GOOD

TAPPWR GOOD

RSTIN#

CLARKUNF

Check

MISC THERMAL

B

CLK_ITP#

P

EG_CLK#

D

PLL_REF_SSCLK

D

PLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP0

MISC

SM_RCOMP1 SM_RCOMP2

PM_EXT_TS#0 PM_EXT_TS#1

CLARKSFIELD

DDR3

PWR MANAGEMENT

JTAG & BPM

3

OF 9

2

B

CLK

B

CLK#

CLK_ITP

EG_CLK

PRDY# PREQ#

TCK

TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

TDI

A16 B16

AR30 AT30

E16 D16

A18 A17

F6

AL1 AM1 AN1

AN15 AP15

Check

AT28 AP27

AN28 AP28 AT27

AT29 AR27 AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

B

CLK_CPU_P_R

B

CLK_CPU_N_R

Check

P

EG_CLK_R EG_CLK#_R

P

D

PLL_REF_SSCLK_R

D

PLL_REF_SSCLK#_R

SM_DRAMRST#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PM_EXTTS#0_C PM_EXTTS#1_C

XDP_TRST#

XDP_TDO_R

TDI_M TDO_M

0R0402-PAD-2-GP

H_DBR#_R

0R0402-PAD-2-GP

B-1022

S RN901 change to 22 ohm

2 3 1

1 2 3

2 3 1

R923

1 2

51R2J-2-GP

R908

1 2

R909

1 2

+3.3V_ALW

B B

VTT_PWRGD[37,49,52]

A A

Remove XDP function for layout concern

5

R989 10KR2J-3-GPR989 10KR2J-3-GP

1 2

U927

U927_B

U927

1

B

VCC

2

A

3

GND

74LVC1G08GW-1-GP

1ST: 73.01G08.L04 2ND:

4

Y

5

VTT_PWRGD_R3

4

R977

PM_DRAM_PWR GDPM_DRAM_PWR GD

12

1K6R2F-GP

SB-1020-1 POP R977 for S3 redution DY R919, change R920 to 0.75K

R919

1K27R2F-L-GP

R920

R920 750R2F-GP

750R2F-GP

+1.5V_CPU

12

DY

12

3

Normal

R920R919

AUB

1.27k

CFD

1.1k 3k

3k

S3 Power Reduction circuit

R920R919

AUB

1.1k(DY)

CFD

1.1k(DY) 0.75k

0.75k

R977

1.6k(DY)

1.5k(DY)

R977

1.6k

1.5k

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/CLOCK/PM )

Size Document Number Rev

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

9 88Wednesday, January 13, 2010

1

A00

5

S

SID = CPU

C

PU1C

4

OF 9

3

C

PU1D

2

OF 9

4

1

W8

S

M

AA6

S

A_CK0

AA7

S

M

_A_DQ[63 ..0][18]

D D

C C

B B

_A_DQ[63 ..0]

M_A_BS0[18] M_A_BS1[18] M_A_BS2[18]

M_A_CAS #[18] M_A_RAS #[18] M_A_W E#[18]

M

_A_DQ0

M

_A_DQ1 _A_DQ2

M M

_A_DQ3 _A_DQ4

M M

_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ1 0 M_A_DQ1 1 M_A_DQ1 2 M_A_DQ1 3 M_A_DQ1 4 M_A_DQ1 5 M_A_DQ1 6 M_A_DQ1 7 M_A_DQ1 8 M_A_DQ1 9 M_A_DQ2 0 M_A_DQ2 1 M_A_DQ2 2 M_A_DQ2 3 M_A_DQ2 4 M_A_DQ2 5 M_A_DQ2 6 M_A_DQ2 7 M_A_DQ2 8 M_A_DQ2 9 M_A_DQ3 0 M_A_DQ3 1 M_A_DQ3 2 M_A_DQ3 3 M_A_DQ3 4 M_A_DQ3 5 M_A_DQ3 6 M_A_DQ3 7 M_A_DQ3 8 M_A_DQ3 9 M_A_DQ4 0 M_A_DQ4 1 M_A_DQ4 2 M_A_DQ4 3 M_A_DQ4 4 M_A_DQ4 5 M_A_DQ4 6 M_A_DQ4 7 M_A_DQ4 8 M_A_DQ4 9 M_A_DQ5 0 M_A_DQ5 1 M_A_DQ5 2 M_A_DQ5 3 M_A_DQ5 4 M_A_DQ5 5 M_A_DQ5 6 M_A_DQ5 7 M_A_DQ5 8 M_A_DQ5 9 M_A_DQ6 0 M_A_DQ6 1 M_A_DQ6 2 M_A_DQ6 3

C10

D10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5

AJ10

AL10 AK12

AK8

AK11

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

A10

B10

E10

F10

J10

AJ7 AJ6

AJ9

AL7

AL8

S

A_DQ0

S

A_DQ1

C7

A_DQ2

S

A7

S

A_DQ3 A_DQ4

S SA_DQ5 SA_DQ6

A8

SA_DQ7

D8

SA_DQ8 SA_DQ9

E6

SA_DQ10

F7

SA_DQ11

E9

SA_DQ12

B7

SA_DQ13

E7

SA_DQ14

C6

SA_DQ15 SA_DQ16

G8

SA_DQ17

K7

SA_DQ18

J8

SA_DQ19

G7

SA_DQ20 SA_DQ21

J7

SA_DQ22 SA_DQ23

L7

SA_DQ24

M6

SA_DQ25

M8

SA_DQ26

L9

SA_DQ27

L6

SA_DQ28

K8

SA_DQ29

N8

SA_DQ30

P9

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1

U7

SA_BS2

SA_CAS# SA_RAS# SA_WE#

CLARKSFIELD

DDR SYSTEM MEMORY A

A_CK#0

S

A_CKE0

S

A_CK1

A_CK#1

S SA_CKE1

SA_CS#0 SA_CS#1

SA_ODT0 SA_ODT1

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS #0 M_A_DQS #1 M_A_DQS #2 M_A_DQS #3 M_A_DQS #4 M_A_DQS #5 M_A_DQS #6 M_A_DQS #7

M_A_DQS 0 M_A_DQS 1 M_A_DQS 2 M_A_DQS 3 M_A_DQS 4 M_A_DQS 5 M_A_DQS 6 M_A_DQS 7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M

_CLK_DD R0 [18]

M

_CLK_DD R#0 [18]

M

_CKE0 [18]

_CLK_DD R1 [18]

M M

_CLK_DD R#1 [18]

M_CKE1 [18]

M_CS0# [18] M_CS1# [18]

M_ODT0 [1 8] M_ODT1 [1 8]

_B_DQ[63 ..0][19]

M_A_DM[7 ..0] [18]

M_A_DQS #[7..0] [18 ]

M_A_DQS [7..0] [18]

M_A_A[15 ..0] [18]

_B_DQ[63 ..0]

M_B_BS0[19] M_B_BS1[19] M_B_BS2[19]

M_B_CAS #[19] M_B_RAS #[19] M_B_W E#[19]

M

_B_DQ0

M

_B_DQ1

M

_B_DQ2

M

_B_DQ3

M

_B_DQ4 _B_DQ5

M M

_B_DQ6 _B_DQ7

M M

_B_DQ8 M_B_DQ9 M_B_DQ1 0 M_B_DQ1 1 M_B_DQ1 2 M_B_DQ1 3 M_B_DQ1 4 M_B_DQ1 5 M_B_DQ1 6 M_B_DQ1 7 M_B_DQ1 8 M_B_DQ1 9 M_B_DQ2 0 M_B_DQ2 1 M_B_DQ2 2 M_B_DQ2 3 M_B_DQ2 4 M_B_DQ2 5 M_B_DQ2 6 M_B_DQ2 7 M_B_DQ2 8 M_B_DQ2 9 M_B_DQ3 0 M_B_DQ3 1 M_B_DQ3 2 M_B_DQ3 3 M_B_DQ3 4 M_B_DQ3 5 M_B_DQ3 6 M_B_DQ3 7 M_B_DQ3 8 M_B_DQ3 9 M_B_DQ4 0 M_B_DQ4 1 M_B_DQ4 2 M_B_DQ4 3 M_B_DQ4 4 M_B_DQ4 5 M_B_DQ4 6 M_B_DQ4 7 M_B_DQ4 8 M_B_DQ4 9 M_B_DQ5 0 M_B_DQ5 1 M_B_DQ5 2 M_B_DQ5 3 M_B_DQ5 4 M_B_DQ5 5 M_B_DQ5 6 M_B_DQ5 7 M_B_DQ5 8 M_B_DQ5 9 M_B_DQ6 0 M_B_DQ6 1 M_B_DQ6 2 M_B_DQ6 3

AG1

AK1 AG4 AG3

AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5

AN6 AN4 AN3

AN7 AP6 AP8

AP9

AR10

AT10

AF3

AJ3

AJ4

AT4

AT5 AT6

AT9 AT7

AB1

W5

AC5

AC6

G4

G2

G1 G5

M1

M4

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3

H6

K2

L3

K5 K4

N5

R7

Y7

J6 J3

J2 J1 J5

S

B_DQ0

S

B_DQ1

S

B_DQ2

S

B_DQ3

S

B_DQ4 B_DQ5

S S

B_DQ6 B_DQ7

S SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

CLARKSFIELD

DDR SYSTEM MEMORY - B

B_CK0

S

B_CK#0

S

B_CKE0

S

B_CK1

S

B_CK#1

B_CKE1

S

SB_CS#0 SB_CS#1

SB_ODT0 SB_ODT1

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS #0 M_B_DQS #1 M_B_DQS #2 M_B_DQS #3 M_B_DQS #4 M_B_DQS #5 M_B_DQS #6 M_B_DQS #7

M_B_DQS 0 M_B_DQS 1 M_B_DQS 2 M_B_DQS 3 M_B_DQS 4 M_B_DQS 5 M_B_DQS 6 M_B_DQS 7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M

_CLK_DD R2 [19]

M

_CLK_DD R#2 [19]

M

_CKE2 [19]

M

_CLK_DD R3 [19] _CLK_DD R#3 [19]

M M

_CKE3 [19]

M_CS2# [19] M_CS3# [19]

M_ODT2 [1 9] M_ODT3 [1 9]

M_B_DM[7 ..0] [19]

M_B_DQS #[7..0] [19 ]

M_B_DQS [7..0] [19]

M_B_A[15 ..0] [19]

CLARKUN F

A A

5

4

3

CLARKUN F

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDR)

Winery13 MB DIS

1

A00

10 88Wednesd ay, January 13, 2010

A00

5

S

SID = CPU

D D

CFG0

CFG3

C C

CFG4

B B

DIS

12

R1101

R1101 3KR2F-GP

3KR2F-GP

DY

改改改改

5%

12

R1102

R1102 3KR2F-GP

3KR2F-GP

DW

07/10 Reversal

1.PCI-Express Static Lane Reversal

12

R1103

R1103 3KR2F-GP

3KR2F-GP

DY

PCI-Express Configuration Select

1:Single PEG

CFG0

0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

1 :Normal Operation

CFG3

0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

CFG4 - Display Port Presence

1:Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

Calpella Platform Design Guide Revision 1.6

4.8.3.1 LVDS Switching

Switchable GFX, just like integrated GFX only, to enable LVDS it is required that the OEM set the LDVS (L_DDC_DATA) strap to present (pulled up) and the eDP strap (CFG[4]) to disabled (not pulled down).

4.8.3.2 eDP Switching

eDP for Switchable GFX can only be driven out of Port D of PCH. To configure Port D for embedded DP it is required to set the DDPD_CTRLDATA strap high to 3.3V Core rail through 2.2 kΩ ±5% resistor, LVDS (L_DDC_DATA) strap as no connect and the eDP strap CFG[4] as no connect.

CFG7(Reserved) - Temporarily used for early Clarksfield sampl es.

CFG7 Clarksfield (only for early samples pre-ES1) -

Connect to GND with 3.01K Ohm/5% resistor.

Note: Only temporary for early CFD sample (rPGA/BGA) [For details please refer to the WW33 MoW and sightin g report]. For a common M/B design (for AUB and CFD),

A A

DW30 Only support Arrandale, CFG7 no need pull down

5

the pull-down resistor shouble be used. Does not impact AUB functionality.

4

Page 482,486

DW

07/02 Added

1.Added display Switchable strap commentariat

4

3

AP25 AL25 AL24 AL22 AJ33

AG9

M27

CFG0

CFG3 CFG4

AM30 AM28

AP31 AL32

AL30 AM31 AN29 AM32

AK32

AK31

AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30

AK30

L28

J17 H17 G25 G17 E31 E30

H16

B19 A19

A20 B20

U9 T9

AC9 AB9

J29

J28

TP1116TP1116 TP1117TP1117

TP1119TPAD14 -GP TP1119TPAD14-GP TP1120TPAD14 -GP TP1120TPAD14-GP

3

SA_DIMM_VREF#

1

SB_DIMM_VREF#

1

1 1

TP_H_RSVD17_R TP_H_RSVD18_R

C

PU1E

R

SVD#AP25

R

SVD#AL25

R

SVD#AL24 RSVD#AL22 RSVD#AJ33 RSVD#AG9 RSVD#M27 RSVD#L28 SA_DIMM_VREF SB_DIMM_VREF RSVD#G25 RSVD#G17 RSVD#E31 RSVD#E30

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD_TP_86

RSVD#B19 RSVD#A19

RSVD#A20 RSVD#B20

RSVD#U9 RSVD#T9

RSVD#AC9 RSVD#AB9

RSVD#J29 RSVD#J28

CLARKUNF

2

OF 9

5

R

SVD#AJ13

R

SVD#AJ12

R

SVD#AH25

R

SVD#AK26

RSVD#AL26

RSVD_NCTF_37

RSVD#AJ26 RSVD#AJ27

CLARKSFIELD

RSVD#AL28

RSVD#AL29 RSVD#AP30 RSVD#AP32

RSVD#AL27 RSVD#AT31 RSVD#AT32 RSVD#AP33 RSVD#AR33

RSVD#AR32

RSVD_TP#E15 RSVD_TP#F15

RESERVED

RSVD#D15 RSVD#C15

RSVD#AJ15 RSVD#AH15

SA_CK2 SA_CK#2 SA_CKE2 SA_CS#2 SA_ODT2

SA_CK3 SA_CK#3 SA_CKE3 SA_CS#3 SA_ODT3

SB_CK2 SB_CK#2 SB_CKE2 SB_CS#2 SB_ODT2

SB_CK3 SB_CK#3 SB_CKE3 SB_CS#3 SB_ODT3

KEY

VSS

1

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33

AR32

E15 F15 A2 D15 C15

TP_RSVD64_R

AJ15

TP_RSVD65_R

AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

1st Samsung

Title

Size Document Num ber Rev

Date: Sheet of

TP1121 TPAD14-GPTP1121 TPAD14-G P

1

TP1122 TPAD14-GPTP1122 TPAD14-G P

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (RESERVED)

Winery13 MB DIS

11 88Wednesday, January 13, 2010

1

A00

5

S

SID = CPU

P

ROCESSOR CORE POWER

VCC_CORE

+

D D

C C

B B

C

DY

C

1207

1208

12

S

C10U6D3V5KX-1GP

C1214

C1213

12

C1226

C1236

S

C10U6D3V5KX-1GP

C1227

12

S

C22U6D3V5MX-2GP

C10U6D3V5KX-1GP

C1237

12

S

C10U6D3V5KX-1GP

C10U6D3V5MX-3GP

DY

1206

12

S

S C10U6D3V5KX-1GP

C10U6D3V5KX-1GP

D

Y

C1212

12

S

S C10U6D3V5KX-1GP

C10U6D3V5KX-1GP

DY

C1225

12

S

S C22U6D3V5MX-2GP

C22U6D3V5MX-2GP

C1235

12

S

S C10U6D3V5MX-3GP

C10U6D3V5MX-3GP

DY

12

C1243

C1243 SCD1U50V3KX-GP

SCD1U50V3KX-GP

SC-1207-1 pop C1243 and change size to 0603 for EMI

C

1220

1209

12

SC10U6D3V5KX-1GP

C1215

C1223

12

SC10U6D3V5KX-1GP

C1228

C1229

12

SC10U6D3V5KX-1GP

C1239

C1238

12

SC22U6D3V5MX-2GP

4

8A (Arburdale)

C

1210

12

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

D

Y

C1224

12

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

DY

C1231

C1230

12

SC10U6D3V5KX-1GP

DY

C1240

12

SC10U6D3V5KX-1GP

DY

C1232

12

SC10U6D3V5KX-1GP

DY

C1242

C1241

12

SC22U6D3V5MX-2GP

DY

4

PU1F

C

+

VCC_CORE

AG35

CC

V

AG34

V

CC

AG33

CC

V

AG32

V

CC

AG31

V

CC

AG30

V

CC

AG29

CC

V

AG28

V

CC

AG27

V

CC

AG26

V

CC

AF35

VCC

AF34

VCC

AF33

VCC

AF32

VCC

AF31

VCC

AF30

VCC

AF29

VCC

AF28

VCC

AF27

VCC

AF26

VCC

AD35

VCC

AD34

VCC

AD33

VCC

AD32

VCC

AD31

VCC

AD30

VCC

AD29

VCC

AD28

VCC

AD27

VCC

AD26

VCC

AC35

VCC

AC34

VCC

AC33

VCC

AC32

VCC

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

AC31 AC30 AC29 AC28 AC27 AC26

AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

CLARKSFIELD

CPU CORE SUPPLY

POWER

SENSE LINES

3

6

1.1V RAIL POWER

PROC_DPRSLPVR

CPU VIDS

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

OF 9

TT0

V V

TT0 TT0

V V

TT0

V

TT0

V

TT0 TT0

V V

TT0

V

TT0

V

TT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

PSI#

VID VID VID VID VID VID VID

1

8A

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

CPU_VID0

AK35

CPU_VID1

AK33

CPU_VID2

AK34

CPU_VID3

AL35

CPU_VID4

AL33

CPU_VID5

AM33

CPU_VID6

AM35 AM34

TP_H_VTTVID1

G15

AN35

VCC_SENSE

AJ34

VSS_SENSE

AJ35

B15

TP_VSS_SENSE_VTT

A15

C

1201

12

SC10U6D3V5KX-1GP

1

12

C

1202

SC10U6D3V5KX-1GP

12

DY

PSI# [47]

CPU_VID[6..0] [47]

PM_DPRSLPVR [47]

TP1203

IMVP_IMON [47]

VTT_SENSE [49]

1

TP1202

TP1202 TPAD14-GP

TPAD14-GP

C

1203

SC10U6D3V5KX-1GP

C1233

SC10U6D3V5MX-3GP

TPAD14-GP

2

SC10U6D3V5KX-1GP

C1211

12

C

1217

1218

SC10U6D3V5KX-1GP

C1221

12

SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

DY

+1.05V_VTT

12

C

1216

12

DY

C1234

12

SC10U6D3V5KX-1GP

C1222

12

C

1219

1204

SC10U6D3V5KX-1GP

+1.05V_VTT

SC22U6D3V5MX-2GP

12

C

1205

SC22U6D3V5MX-2GP

SC1U6D3V2KX-GP

D

Y

The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide.

+

1.05V_VTT

1

Please note that the VTT Rail Values are Arrandale VTT=1.05V; Clarksfield VTT=1.1V

H_VTTVID1 = Low, 1.1V H_VTTVID1 = High, 1.05V

SA

07/01 Check

1.DPRSLPVR ??

+VCC_CORE

12

R1201

R1201 100R2F-L1-GP-U

100R2F-L1-GP-U

VCC_SENSE [47]

12

R1204

R1204 100R2F-L1-GP-U

100R2F-L1-GP-U

VSS_SENSE [47]

A A

CLARKUNF

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

CPU (VCC_CORE)

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

12 88Wednesday, January 13, 2010

1

A00

5

4

3

2

1

1.5V_CPU

+

S

SID = CPU

+

CPU_GFX CORE

7

OF 9

C

PU1G

AT21 AT19 AT18

AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16

AM21 AM19 AM18 AM16

AL21

AL19

AL18

AL16 AK21 AK19 AK18 AK16

AJ21

AJ19

AJ18

AJ16 AH21 AH19 AH18 AH16

G28 G27 G26

E26 E25

J24 J23 H25

K26 J27 J26 J25 H27

F26

PU1G

V

AXG

V

AXG AXG

V V

AXG AXG

V VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

VTT1 VTT1 VTT1

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

GRAPHICS

CLARKSFIELD

FDI PEG & DMI

POWER

SENSE

GRAPHICS VIDs

LINES

22A

D D

C C

B B

T

C1303

C

1324

1327

12

SC22U6D3V5MX-2GP

SE330U2VDM-L-GP

DY

SC22U6D3V5MX-2GP

+1.05V_V TT

12

C

1329

1326

SC10U6D3V5MX-3GP

DY

12

SC10U6D3V5MX-3GP

DY

SC10U6D 3V5MX-3GP

12

18A

12

C1312

C

1328

12

SC10U6D3V5MX-3GP

C1308

12

C1313

SC10U6D3V5KX-1GP

1325

SC1U6D3V2KX-GP

DY

12

DY

12

C

1323

SC10U6D3V5MX-3GP

12

C1309

C1309 SC10U6D 3V5KX-1GP

SC10U6D 3V5KX-1GP

12

C1314

SC10U6D3V5MX-3GP

12

C1315

C

1330

12

SCD1U16V2KX-3GP

SC10U6D3V5KX-1GP

OF 9

GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID

GFX_IMON

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VTT0 VTT0 VTT0 VTT0

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

VCCPLL VCCPLL VCCPLL

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25

TP_GFX_ DPRSLPVR

AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

SC10U6D 3V5MX-3GP

SC10U6D 3V5KX-1GP

V

AXG_SENSE

SSAXG_SENSE

V

GFX_VR_EN

GFX_DPRSLPVR

DDR3 - 1.5V RAILS

1.1V1.8V

12

D

Y

1376

C

C SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

+

1.5V_SUS

F

ollow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.pdf"

document.

CC_AXG_ SENSE [5 3]

V V

SS_AXG_ SENSE [53]

GFX_VID0 [53 ] GFX_VID1 [53 ] GFX_VID2 [53 ] GFX_VID3 [53 ] GFX_VID4 [53 ] GFX_VID5 [53 ] GFX_VID6 [53 ]

GFX_VR_ EN [53]

TP1303TPAD14-GPTP 1303TPAD14-GP

1

12

SC1U10V2KX-1GP

C1310

C1316

C1302

DY

12

C1318

12

C1303

SCD1U16V2KX-3GP

12

DY

12

C1319

SC1U25V5KX-1GP

C1301

1.5V_CPU

+

12

D

Y

1377

C

C SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

+

1.5V_SUS

GFX_IMON [53]

For no use switch graphic function

3A

12

C1304

SCD1U10V2KX-4GP

12

C1311

C1311 SC10U6D 3V5KX-1GP

SC10U6D 3V5KX-1GP

12

C1317

C1317 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

12

C1306

C1305

SC10U6D3V5KX-1GP

SCD1U10V2KX-4GP

+1.05V_V TT

SC10U6D3V5KX-1GP

SCD1U16V2KX-3GP

1.35A

12

C1320

SC1U25V5KX-1GP

12

C1321

C1322

SC2D2U6D3V3KX-GP

SC4D7U6D3V5KX-3GP

SC10U6D 3V5MX-3GP

12

+1.5V_CP U

C1307

SC10U6D3V5KX-1GP

1.5V_CPU

+

D

+

1.5V_SUS

12

DY

+1.8V_RU N

12

Y

1378

C

C SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

TC1301

TC1301 SE330U2 D5VDM-2GP

SE330U2 D5VDM-2GP

1.5V_CPU

+

D

+

1.5V_SUS

12

Y

1379

C

C SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

CLARKUN F

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_GFXCORE)

Size Document N umber Rev

Date: Sheet of

CPU (VCC_GFXCORE)

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

13 88Wednesd ay, January 13, 2010

1

A00

5

PU1H

C

S

SID = CPU

D D

C C

B B

AT20

AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2

AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8 AM5

AM2 AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8

AF4

AF2 AE35

C

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS SS

V V

SS SS

V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ8

VSS

AJ5

VSS

AJ2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

4

CLARKSFIELD

VSS

8

OF 9

V V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

3

PU1I

C

AE34

SS

AE33

SS

AE32

SS

AE31

SS

AE30

SS

AE29

SS

AE28

SS

AE27

SS

AE26

SS

AE6

SS

AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

K27

H35 H32 H28 H26 H24 H22 H18 H15 H13 H11

G34 G31 G20

E35 E32 E29 E24 E21 E18 E13 E11

D33 D30 D26

C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11

A29 A27 A23

V

SS

K9

V

SS

K6

V

SS

K3

V

SS

J32

V

SS

J30

SS

V

J21

V

SS

J19

SS

V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H8

VSS

H5

VSS

H2

VSS VSS VSS VSS

G9

VSS

G6

VSS

G3

VSS

F30

VSS

F27

VSS

F25

VSS

F22

VSS

F19

VSS

F16

VSS VSS VSS VSS VSS VSS VSS VSS VSS

E8

VSS

E5

VSS

E2

VSS VSS VSS VSS

D9

VSS

D6

VSS

D3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

B8

VSS

B6

VSS

B4

VSS VSS VSS VSS

A9

VSS

2

9

OF 9

CLARKSFIELD

VSS

VSS_NCTF VSS_NCTF VSS_NCTF

NCTF

VSS_NCTF#A35 VSS_NCTF#AT1

VSS_NCTF#AT35

VSS_NCTF#B1

RSVD_NCTF#A3 RSVD_NCTF#A33 RSVD_NCTF#A34 RSVD_NCTF#AP1

RSVD_NCTF#AP35

RSVD_NCTF#AR1

RSVD_NCTF#AR35

RSVD_NCTF#AT2

RSVD_NCTF#AT3 RSVD_NCTF#AT33 RSVD_NCTF#AT34

RSVD_NCTF#C1

RSVD_NCTF#C35

A35,AT1,AT35,B1,A3,A33,A34,

NCYF TEST PIN:

RSVD_NCTF#B35

AP1,AP35,AR1,AR35,AT2,AT3,

AT33,AT34,C1,C35,B35

AP1,AP35,AR1,AR35,AT2,AT3,

AT33,AT34,C1,C35,B35

AR34 B34 B2

TP_MCP_ VSS_NCTF2

A35

TP_MCP_ VSS_NCTF3

AT1

TP_MCP_ VSS_NCTF4

AT35

TP_MCP_ VSS_NCTF1

B1 A3 A33 A34 AP1 AP35 AR1 AR35 AT2 AT3 AT33 AT34 C1 C35 B35

For layout request

1

TP1402TP 1402

1

TP1406TP 1406

1

TP1405TP 1405

1

TP1401TP 1401

1

CLARKUN F

A A

5

4

3

CLARKUN F

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VSS)

Winery13 MB DIS

1

A00

14 88Wednesd ay, January 13, 2010

A00

5

D D

S

SID = MEMORY

M_A_DQS#[7..0][10]

M_A_DQ[63..0][10]

M_A_DM[7..0][10]

M_A_DQS[7..0][10]

M_A_A[15..0][10]

Layout Note:

12

1803

1803 C

C

C1804

SC10U6D3V5KX-1GP

+0.75V_DDR_VTT

12

1801

DY

C

SC1U6D3V2KX-GP

12

1873

C1874

C

SCD1U10V2KX-4GP

Place near DM1

12

C1811

SC10U6D3V5KX-1GP

12

C1813

C1814

SC1U6D3V2KX-GP

12

C1875

SCD1U10V2KX-4GP

+V_DDR_REF

C1810

SCD1U10V2KX-5GP

12

C1812

SC10U6D3V5KX-1GP

12

DY

C1815

SC1U6D3V2KX-GP

12

SCD1U10V2KX-5GP

12

C1816

SC10U6D3V5KX-1GP

Layout Note: Put between two SO-DIMM

DY

C1823

SC10U6D3V5MX-3GP

12

C1817

C C

B B

A A

+1.5V_SUS

12

1802

1802 C

C

SC10U6D3V5KX-1GP

Layout Note: Put close to VTT1,VTT2.

DG: 1uF*4 (per SO-DIMM) 10uF*3 (two close to VR and one between the two SO-DIMM)

+1.5V_SUS

12

1872

1872 C

C

SCD1U10V2KX-4GP

Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. pdf" document.

5

12

SC2D2U6D3V3KX-GP

4

_A_A0

M M

_A_A1

M

_A_A2

M

_A_A3

M

_A_A4 _A_A5

M M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_BS2[10]

M_A_BS0[10] M_A_BS1[10]

12

DY

TC1803

ST330U2D5VBM-1-GP

M_ODT0[10] M_ODT1[10]

12

C1809

DY

+0.75V_DDR_VTT

4

M_A_BS2

M_A_BS0 M_A_BS1

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_ODT0 M_ODT1

DDR3_DRAMRST#[9,19]

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78 79

109 108

5

7 15 17

4

6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10 27 45 62

135 152 169 186

12 29 47 64

137 154 171 188

116 120

126

1

30

203 204

3

D

M1

0

A A

1 2

A A

3 4

A A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32

Height 5.2mm

DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA VREF_DQ

RESET#

VTT1 VTT2

DDR3-204P-25-GP

3

R

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

2

NP1

P1

N

NP2

N

P2

110

AS#

113

E#

W

115

114 121

73 74

M_CLK_DDR0

101

CK0

CK1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M_CLK_DDR#0

103

M_CLK_DDR1

102

M_CLK_DDR#1

104

M_A_DM0

11

M_A_DM1

28

M_A_DM2

46

M_A_DM3

63

M_A_DM4

136

M_A_DM5

153

M_A_DM6

170

M_A_DM7

187

PCH_SMBDATA

200

PCH_SMBCLK

202

198

199

SA0_DM1

197

SA0

SA1_DM1

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

+1.5V_SUS

M

_A_RAS# [10]

_A_WE# [10]

M

_A_CAS# [10]

M_CS0# [10]

M_CS1# [10]

M_CKE0 [10]

M_CKE1 [10]

M_CLK_DDR0 [10] M_CLK_DDR#0 [10]

M_CLK_DDR1 [10] M_CLK_DDR#1 [10]

PCH_SMBDATA [7,19,23,40,64,76] PCH_SMBCLK [7,19,23,40,64,76]

PM_EXTTS#0 [9]

C1806

SCD1U10V2KX-5GP

M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1

12

2

SA0_DM1 SA1_DM1

SMBUS address:A0

+3.3V_RUN

12

C1807

C1807 SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

DY

put near connector

12

C1821

C1819

DUMMY-C2

12

R1801

R1802

R1802 10KR2J-3-GP

10KR2J-3-GP

12

C1820

DUMMY-C2

1st Samsung

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

R1801 10KR2J-3-GP

10KR2J-3-GP

DW

07/02 Reserve

1.Added SA0_DM1 pull-up resis tor 07/07

2.Reserve pull- hi,lo resistor

C1818

DUMMY-C2

DDRIII-SODIMM SLOT1

Winery13 MB DIS

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsic hih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsic hih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

18 88Wednesday, January 13, 2010

1

A00

5

S

SID = MEMORY

M

D D

C C

B B

Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. pdf" document.

A A

_B_DQS#[7..0][10]

M

_B_DQ[63..0][10]

M

_B_DM[7..0][10]

M_B_DQS[7..0][10]

M_B_A[15..0][ 10]

Layout Note:

+1.5V_SUS

12

1905

1905 C

C

C1911

SC10U6D3V5KX-1GP

+0.75V_DDR_VTT

12

1908

1908 C

C

C1917

SC1U6D3V2KX-GP

DG: 1uF*4 (per SO-DIMM) 10uF*3 (two close to VR and one between the two SO-DIMM)

+1.5V_SUS

12

1976

1976 C

C

C1977

SCD1U10V2KX-4GP

5

Place near DM2

12

C1913

SC10U6D3V5KX-1GP

Layout Note: Put close to VTT1,VTT2.

12

SC1U6D3V2KX-GP

12

C1978

SCD1U10V2KX-4GP

+V_DDR_REF

SCD1U10V2KX-5GP

12

C1916

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

12

DY

C1918

SC1U6D3V2KX-GP

12

C1979

SCD1U10V2KX-4GP

12

C1907

SCD1U10V2KX-5GP

12

C1920

C1919

SC10U6D3V5KX-1GP

12

DY

C1909

SC1U6D3V2KX-GP

C1910

12

SC2D2U6D3V3KX-GP

4

M

_B_A0

M

_B_A1

M

_B_A2

M

_B_A3

M

_B_A4

M

_B_A5 _B_A6

M M

_B_A7

M

_B_A8

M

_B_A9

M

_B_A10

M

_B_A11

M

_B_A12 _B_A13

M

_B_A14

M M_B_A15

M_B_BS2[10]

M_B_BS0[10] M_B_BS1[10]

12

DY

TC1903

ST330U2D5VBM-1-GP

M_ODT2[10]

M_ODT3[10]

12

C1914

DY

4

DDR3_DRAMRST#[9,18]

M_B_BS2

M_B_BS0 M_B_BS1

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_ODT2 M_ODT3

+0.75V_DDR_VTT

3

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78 79

109 108

5

7 15 17

4

6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10 27 45 62

135 152 169 186

12 29 47 64

137 154 171 188

116 120

126

1

30

203 204

M2

D

A

0

A

1

A

2

A

3 4

A

5

A A

6 7

A A

8

A

9

A

10/AP 11

A A

12

A

13

A

14 A15 A16/BA2

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA VREF_DQ

RESET#

VTT1 VTT2

DDR3-204P-24-GP

NP1

N

P1

NP2

N

P2

110

R

AS#

113

E#

W

115

AS#

C

114

S0#

C

121

C

S1#

73

C

KE0

74

KE1

C

K0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

Height 9.2mm

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M

101

K0

M

103

M_CLK_DDR3

102

M_CLK_DDR#3

104

M_B_DM0

11

M_B_DM1

28

M_B_DM2

46

M_B_DM3

63

M_B_DM4

136

M_B_DM5

153

M_B_DM6

170

M_B_DM7

187

PCH_SMBDATA

200

PCH_SMBCLK

202

198

199

SA0_DM2

197

SA1_DM2

201

77 122

+1.5V_SUS

125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

hange CONN

C 2009/06/01

_CLK_DDR2 _CLK_DDR#2

2

M

_B_RAS# [10]

M

_B_WE# [10] M

_B_CAS# [10]

_CS2# [10]

M

_CS3# [10]

M

_CKE2 [10]

_CKE3 [10]

M

_CLK_DDR2 [1 0]

M

_CLK_DDR#2 [ 10]

M_CLK_DDR3 [10] M_CLK_DDR#3 [10]

PCH_SMBDATA [7,18,23,40 ,64,76] PCH_SMBCLK [7,18,23 ,40,64,76]

PM_EXTTS#1 [9]

SCD1U10V2KX-5GP

12

2

put near connector

C1901

DUMMY-C2

M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR3 M_CLK_DDR#3

C1906

12

1

+

3.3V_RUN+3.3V_RUN

12

R

1903

10KR2J-3-GP

A1_DM2

S SA0_DM2

R1901

R1901 10KR2J-3-GP

10KR2J-3-GP

R

1904

10KR2J-3-GP

Y

D

12

R1902

R1902 10KR2J-3-GP

10KR2J-3-GP

DY

SMBUS address:A4

+3.3V_RUN

12

C1921

C1921 SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

DY

Note: If SA0_DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 If SA0_DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 If SA0_DIM0 = 0, SA1_DIM0 = 1 SO-DIMMA SPD Address is 0xA4

12

C1904

DUMMY-C2

1st Samsung

Title

Size Document Number Rev

Date: Sheet of

C1902

Custom

C1903

DUMMY-C2

DDRIII-SODIMM SLOT2

Winery13 MB DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

12

D

Y

19 88Wednesday, January 13, 2010

C1901

E

E SCD1U25V3KX-GP

SCD1U25V3KX-GP

A00

5

W

D

0

7/05

S

SID = PCH

D D

C C

1. LCD brightness control are separated by GPU,PCH,EC

2. LCD Power Enable control a re separated by GPU,PCH,EC

3. LCD Backlight On/Off Statu s are separated by GPU,PCH,E C 07/07

4. Dummy R2003

12

R2002

R2002 2K37R2F -GP

2K37R2F -GP

50 ohm trace to filter

MCH_BLU E[74] MCH_GRE EN[74] MCH_RED[74 ]

R2007

R2007 150R2F-1 -GP

150R2F-1 -GP

B B

MCH_BLU E MCH_GRE EN MCH_RED

R2006

R2006 150R2F-1 -GP

150R2F-1 -GP

4

Place near PCH

1 2

Place near PCH

P

ANEL_BK EN_PCH[37]

L

CDVDD_E N_PCH[54]

L

BKLT_CT L_PCH[5 4]

L

_DDC_CL K[54]

L_DDC_D ATA[54]

+3.3V_RU N

MCH_LVD SA_CLK#[74] MCH_LVD SA_CLK[7 4]

MCH_LVD SA_DAT0#[74] MCH_LVD SA_DAT1#[74] MCH_LVD SA_DAT2#[74]

MCH_LVD SA_DAT0[74] MCH_LVD SA_DAT1[74] MCH_LVD SA_DAT2[74]

1 2

RN2001

1 2 3

SRN10KJ -5-GP

TP2001T PAD14-GP TP2001TP AD14-GP

1

37.5 ohm trace to 150R resistor

R2005

R2005 150R2F-1 -GP

150R2F-1 -GP

1 2

GMCH_DD CCLK[55] GMCH_DD CDATA[55 ]

GMCH_HS YNC[74] GMCH_VS YNC[74]

1 2

R2004

R2004 1KR2J-1-G P

1KR2J-1-G P

SB-1023 change R2004 from 0.5% to 5%.

L

CDVDD_E N_PCH

A00-0104-1

R

2011

0R0402-P AD-2-GP

P

ANEL_BK EN_PCHR

L

CDVDD_E N_PCH

LCTLA_C LK

4

LCTLB_D ATA

LIBG TP_LVDS _VBG

CRT_IREF

3

1 2

R

2003

100KR2J -1-GP

U

2001D

T48

L

T47

L

Y48

L

AB48

L

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M -GP-NF

Y

D

_BKLTEN _VDD_EN

_BKLTCTL

_DDC_CLK

4

OF 10

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

S

DVO_TVCLKINN

S

DVO_TVCLKINP

DVO_STALLN

S S

DVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

CRT

2

1

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

PCH (LVDS/CRT/DDI)

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

20 88Wednesd ay, January 13, 2010

1

A00

5

R

N2101

CI_DEVSEL #

P

CI_IRDY#

P

CI_SERR#

P I

+

3.3V_RUN

D D

+

3.3V_RUN

C C

NT_PIRQC#

P

CI_PERR#

P

CI_REQ0# CI_REQ3#

P P

CI_FRAME#

+3.3V_RU N

EDID_SELE CT#[54,55]

N2101

1 2 3 4 5 6

SRN8K2J -2-GP-U

R

N2102

1 2 3 4 5 6

SRN8K2J -2-GP-U

1 2 3 4 5

RN2103

RN2103 SRN10KJ -7GP

SRN10KJ -7GP

DGPU_PW M_SELECT#

8

EDID_SELE CT_R#

7

PCH_GPIO4

6

INT_PIRQE#

+3.3V_RU N

12

DY

0

1

GPU_SEL ECT#

D

9

NT_PIRQD#

I

8

P

CI_STOP#

7

NT_PIRQA#

I

1

0

I

NT_PIRQB#

9

CI_PLOCK#

P

8

P

CI_REQ1#

7

CI_TRDY#

P

SB-1022 DY U2102; POP R2105

U2102

5

4

R2105 0R2 J-2-GPR2105 0R2 J-2-GP

C2112

C2112 SC220P5 0V2KX-3GP

SC220P5 0V2KX-3GP

B

VCC

A

Y

DY

GND

74LVC1G 08GW-1-GP

1 2

+

3.3V_RUN

1

EDID_SELE CT_R#

2

3

3.3V_RUN

+

BOOT BIOS Strap

PCI_GNT#1 BO OT BIOS Locatio nPCI_GNT#0

0 0 LPC

0 1 Reserved

01

B B

A16 swap overrid e Strap/Top-Blo ck Swap Override ju mper

PCI_GNT#3 Low = A16 swap

A A

PCI_GNT3#

11

override/Top-Blo ck Swap Override en abled High = Default

R2109

1 2

DY

4K7R2J-2 -GP

5

PCI

SPI(Default)

4

C

2101

SCD1U10 V2KX-4GP

P

SB-1022 DY U2101; POP R2104

W

D

7/02 Added

0

1. using the single buffers f or 4 device with equivalent capability.

2.Rename PCI_PLTRST#

12

LT_RST#[9,34,36,37 ,64,70,76,80]

DGPU_PW M_SELECT#[54]

PCLK_FW H[70] CLK_PCI_F B[23] PCLK_KB C[37] PCLK_TP M[36]

Calpella Platform Design Guide Revision 1.6

Table 111. Overcurrent Pin Example Configuration

These OC7# pins are not used for USB overcurrent protection and should be configured as GPIOs. The unused USB ports can be left as no connect.

4

+

3.3V_RUN

U

2101

5

V

CC

4

Y

74LVC1G 08GW-1-GP

1 2

R2104 0R2 J-2-GPR2104 0R2 J-2-GP

DGPU_SE LECT#[37,54,74]

TP2116TPAD14-GPTP 2116TPA D14-GP

HDD_FAL L_INT1[4 0]

WW AN_RF_EN[76]

R2110 22R2J-2-G P

1 2

DY

R2108 22R2J-2-G PR2108 22R2J-2-GP

1 2

R2111 22R2J-2-G PR2111 22R2J-2-GP

1 2

R2112 22R2J-2-G P

1 2

DY

3

5

2001E

U

H40

D0

A

N34

A

D1

C44

A

D2

A38

D3

A

C36

A

D4

J34

A

D5

A40

A

D6

D45

A

D7

E36

A

D8

H48

A

1

B

LTRST#_ PCH

P

2

A

D

Y

3

ND

G

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCI_REQ0# PCI_REQ1#

DGPU_SE LECT#

PCI_REQ3#

1

R2121

R2121 0R2J-2-GP

0R2J-2-GP

1 2

TP2108TPAD14-GPTP 2108TPA D14-GP

TP2115TPAD14-GPTP 2115TPA D14-GP

PCI_GNT0#

DGPU_PW M_SELECT#

PCI_GNT3#

INT_PIRQE# WW AN_RF_EN PCH_GPIO4

EDID_SELE CT_R#

PCIRST#

1

PCI_SERR# PCI_PERR#

PCI_IRDY#

PCI_DEVSE L# PCI_FRAME #

PCI_PLOCK #

PCI_STOP# PCI_TRDY#

PCH_PME #

1

PLTRST# _PCH

PCLK_FW H_R CLK_PCI_F B_R PCLK_KB C_R PCLK_TP M_R

D9

E40

A

D10

C40

A

D11

M48

D12

A

M45

A

D13

F53

D14

A

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1#/GPIO50

B45

REQ2#/GPIO52

M53

REQ3#/GPIO54

F48

GNT0#

K45

GNT1#/GPIO51

F36

GNT2#/GPIO53

H53

GNT3#/GPIO55

B41

PIRQE#/GPIO2

K53

PIRQF#/GPIO3

A36

PIRQG#/GPIO4

A48

PIRQH#/GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M -GP-NF

PCI

N N N N

N N

N

V_DQ0/NV_IO0

N

V_DQ1/NV_IO1

N

V_DQ2/NV_IO2

N

V_DQ3/NV_IO3 V_DQ4/NV_IO4

N N

V_DQ5/NV_IO5 V_DQ6/NV_IO6

N NV_DQ7/NV_IO7 NV_DQ8/NV_IO8

NV_DQ9/NV_IO9 NV_DQ10/NV_IO10 NV_DQ11/NV_IO11

NVRAM

NV_DQ12/NV_IO12 NV_DQ13/NV_IO13 NV_DQ14/NV_IO14 NV_DQ15/NV_IO15

NV_RCOMP

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USB

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

5

V_CE#0 V_CE#1 V_CE#2 V_CE#3

V_DQS0 V_DQS1

NV_ALE

NV_CLE

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

OF 10

2

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

TP_NV_A LE

BD3

TP_NV_C LE

AY6

TP_NV_R COMP

AU2

AV7

AY8 AY5

AV11 BF5

Port 0 for debug port

H18 J18 A18 C18 N20 P20

TP_USB_ PN3

J20

TP_USB_ PP3

L20 F20 G20 A20 C20

TP_USB_ PN6

M22

TP_USB_ PP6

N22

TP_USB_ PN7

B21

TP_USB_ PP7

D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24

TP_USB_ PN13

A24

TP_USB_ PP13

C24

USB_RBIAS _PN

B25

D25

USB_OC# 0_1

N16

USB_OC# 2_3

J16

USB_OC# 4_5

F16

USB_OC# 6_7

L16

USB_OC# 8_9

E14

USB_OC# 10_11

G16

USB_OC# 12_13

F12

PCH_OC7 #

T15

TP2124 TPAD14-GPTP2124 TPAD14-GP

1

TP2125 TPAD14-GPTP2125 TPAD14-GP

1

TP2130 TPAD14-GPTP2130 TPAD14-GP

1

USB_PN0 [63] USB_PP0 [63] USB_PN1 [63] USB_PP1 [63] USB_PN2 [76]

USB_PP2 [76]

TP2122TP 2122 TP2123TP 2123

USB_PN4 [64]

USB_PP4 [64]

USB_PN5 [76]

USB_PP5 [76]

TP2118TP 2118 TP2119TP 2119 TP2120TP 2120 TP2121TP 2121

USB_PN8 [73]

USB_PP8 [73]

USB_PN9 [32]

USB_PP9 [32]

USB_PN1 0 [78]

USB_PP1 0 [78]

USB_PN1 1 [73]

USB_PP1 1[73]

USB_PN1 2 [34]

USB_PP1 2 [34]

TP2128TP 2128 TP2129TP 2129

1 2

S

SID = PCH

D

MI Termination V oltage

NV_CLE Set t o Vss when low.

Set to Vcc when high. Low = Default

unused NV_SLE st rap

R2106

R2106 22D6R2F -L1-GP

22D6R2F -L1-GP

USB_OC# 0_1 [22 ,63] USB_OC# 2_3 [76 ]

Pull up in page 22 for layout convenience

USB_OC# 12_13 [23]

1

USB

Pair

Device

USB1

0

USB for ESATA

1

USB2

2

RESERVE

3

WLAN

4

WWAN

5

RESERVED

6

(Not available f or HM55)

RESERVED

7

(Not available f or HM55)

BlUETOOTH

8

Card Reader

9

Biometric

10

CAMERA

11

New Card

12

RESERVED

13

SB swap net for layout

Pull up in page 23 for layout convenience

Page 233

RP2101

+3.3V_AL W

3

PCH_OC7 # USB_OC# 2_3

USB_OC# 4_5

RP2101

1 2 3 4 5 6

SRN10KJ -L3-GP

10

PM_RI#

9

USB_OC# 8_9USB_OC# 6_7

8

PEG_B_C LKRQ#

7

USB_OC# 10_11

SB swap net for layout

+3.3V_AL W

PM_RI# [22]

PEG_B_C LKRQ# [23]

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

PCH (PCI/USB/NVRAM)

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

21 88Wednesd ay, January 13, 2010

1

A00

5

S

SID = PCH

D D

+1.05V_V TT

R2204

1 2

49D9R2F -GP

D

MI_CTX_PR XN0[8]

D

MI_CTX_PR XN1[8]

D

MI_CTX_PR XN2[8]

D

MI_CTX_PR XN3[8]

D

MI_CTX_PR XP0[8]

D

MI_CTX_PR XP1[8] MI_CTX_PR XP2[8]

D D

MI_CTX_PR XP3[8]

D

MI_PTX_CR XN0[8] DMI_PTX_C RXN1[8] DMI_PTX_C RXN2[8] DMI_PTX_C RXN3[8]

DMI_PTX_C RXP0[8 ] DMI_PTX_C RXP1[8 ] DMI_PTX_C RXP2[8 ] DMI_PTX_C RXP3[8 ]

DMI_IRCOMP_R

+3.3V_RU N

12

Remove XDP pull-up ?

C C

B B

XDP_DBR ESET#[9]

A00-0104-1

R2207 0R0402-P AD-2-GPR2207 0R0402-P AD-2-GP

PM_PW ROK[37]

PM_DRAM _PWRGD[9]

RSMRST# _KBC[37 ] PM_SLP_ S4# [3 4,37,50]

SUS_PW R_DN_ACK[37]

PM_PW RBTN#[3 7]

AC_PRES ENT_EC[37]

PM_RI#[21]

1 2

R2208

1 2

R2209 10KR2J-3 -GPR2 209 10KR2J-3 -GP

1 2

A00-0104-1

AC_PRESENT_EC

10KR2J-3 -GP

1 2

R2210 0R2 J-2-GPR2210 0R2J-2-GP

1 2

R2218 0R0 402-PAD-2-GPR221 8 0R0 402-PAD-2-GP

1 2

R2213 0R0 402-PAD-2-GPR221 3 0R0 402-PAD-2-GP

1 2

R2216 0R0 402-PAD-2-GPR221 6 0R0 402-PAD-2-GP

4

R2205

R2205 10KR2J-3 -GP

10KR2J-3 -GP

XDP_DBR ESET#

PM_PW RGD

LAN_RST #1

PM_DRAM _PWRGD

PM_RSMR ST#_R

SUS_PW R_ACK

PM_PW RBTN#_R

AC_PRESENT

PM_BATL OW#_R

PM_RI#

U

2001C

BC24

D

MI0RXN

BJ22

D

MI1RXN

AW20

D

MI2RXN

BJ20

D

MI3RXN

BD24

D

MI0RXP

BG22

D

MI1RXP

BA20

D

MI2RXP

BG20

MI3RXP

D

BE22

MI0TXN

D

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK/GPIO30

P5

PWRBTN#

P7

ACPRESENT/GPIO31

A6

BATLOW#/GPIO72

F14

RI#

IBEXPEAK-M -GP-NF

3

OF 10

3

DI_RXN0

F F

DI_RXN1

F

DI_RXN2

F

DI_RXN3

F

DI_RXN4

F

DI_RXN5

F

DI_RXN6

F

DI_RXN7

DI_RXP0

F F

DI_RXP1 DI_RXP2

F FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

DMI

FDI

DMI

FDI

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_M#

System Power Management

TP23

PMSYNCH

SLP_LAN#/GPIO29

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

DI_TXN0

F F

DI_TXN1

F

DI_TXN2

F

DI_TXN3

F

DI_TXN4

F

DI_TXN5

F

DI_TXN6

F

DI_TXN7

DI_TXP0

F F

DI_TXP1 DI_TXP2

F F

DI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

PM_CLKR UN#

TP_SUS_ STAT#

PCH_SUS CLK

PCH_SLP _S5#

PM_SLP_ S4#_R

PM_SLP_ S3#_R

SIO_SLP_M# _R

PM_SLP_ DSW#

H_PM_SYNC

F

DI_TXN0 [8]

F

DI_TXN1 [8]

F

DI_TXN2 [8]

F

DI_TXN3 [8]

F

DI_TXN4 [8]

F

DI_TXN5 [8]

F

DI_TXN6 [8]

F

DI_TXN7 [8]

F

DI_TXP0 [8] DI_TXP1 [8]

F F

DI_TXP2 [8] FDI_TXP3 [8] FDI_TXP4 [8] FDI_TXP5 [8] FDI_TXP6 [8] FDI_TXP7 [8]

FDI_INT [8]

FDI_FSYNC0 [8 ]

FDI_FSYNC1 [8 ]

FDI_LSYNC0 [8]

FDI_LSYNC1 [8]

1

TP2205TPAD14-GPTP 2205TPAD14-GP

1

TP2202TPAD14-GPTP 2202TPAD14-GP

1 2

R2211 0R04 02-PAD-2-GPR221 1 0R0 402-PAD-2-GP

1 2

R2212 0R04 02-PAD-2-GPR221 2 0R0 402-PAD-2-GP

1

TP2203TPAD14-GPTP 2203TPAD14-GP

1

TP2204TPAD14-GPTP 2204TPAD14-GP

PCIE_W AKE# [34,76]

PM_CLKR UN# [37]

A00-0104-1

2

U

SB_OC#0 _1[21 ,63]

Close to PCH

1 2

R2219 0R04 02-PAD-2-GPR221 9 0R0 402-PAD-2-GP

A00-0104-1

1 2

R2220 0R04 02-PAD-2-GPR222 0 0R0 402-PAD-2-GP

PM_SLP_ S3# [34,37,42,50,5 1,86]

H_PM_SYNC [9]

1

+

3.3V_ALW

R

N2201

U

SB_OC#0 _1

S

US_PW R_ACK

M_BATLO W#_R

P

CIE_WA KE#

P

AC_PRES ENT_EC

Option to " Disable " clkrun. Pulling it down will keep the clks running.

PM_CLKR UN#

10KR2J-3 -GP

PCH_SUS CLK_2102 [39]

PCH_SUS CLK_KBC [37]

N2201

23 1

4

SRN10KJ -5-GP

1 2

R

2201 1 0KR2J-3-GP

1 2

R

2202 1 KR2J-1-GP

1 2

R2217 10KR2J-3 -GPR2 217 10KR2J-3 -GP

+3.3V_RU N

R2214

R2214 10KR2J-3 -GP

10KR2J-3 -GP

1 2

12

R2215

DY

Pull up in page 23 for layout convenience

KBC_PW R

R2221

R2221 10KR2J-3 -GP

10KR2J-3 -GP

DY

1 2

U2213

34

2

5

DY

2213_56 U

A A

PM_RSMR ST#_R

5

1

6

DMN66D0 LDW-7-GP

R2203

1 2

10KR2J-3 -GP

PM_RSMR ST#_R

3V_5V_P OK [37,46]

SB-31

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

4

3

2

Date: Sheet of

PCH (DM I/FDI/PM)

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

22 88Wednesd ay, January 13, 2010

1

A00

5

S

SID = PCH

BG30

BJ30 BF29 BH29

D D

P

CIE_IRXN2_MTXN2[64]

P

CIE_IRXP2_MTXP2[64]

P

CIE_ITXN2_MRXN2[64]

P

CIE_ITXP2_MRXP2[64]

PCIE_IRXN3_LRTXN3[76] PCIE_IRXP3_LRTXP3[76]

PCIE_ITXN3_LRXN3[76] PCIE_ITXP3_LRXP3[76]

PCIE_IRXN4_MTXN4[76]

PCIE_IRXP4_MTXP4[76] PCIE_ITXN4_MRXN4[76] PCIE_ITXP4_MRXP4[76]

PCIE_IRXN5_NTXN5[34]

PCIE_IRXP5_NTXP5[34] PCIE_ITXN5_NRXN5[34] PCIE_ITXP5_NRXP5[34]

C C

PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN

2318 SCD1U10V2KX-5GP

C

C C

C

C2303 SCD1U10V2KX-5GPC2303 SCD1U10V2K X-5GP C2309 SCD1U10V2KX-5GPC2309 SCD1U10V2K X-5GP

C2302 SCD1U10V2KX-5GPC2302 SCD1U10V2K X-5GP C2311 SCD1U10V2KX-5GPC2311 SCD1U10V2K X-5GP

C2308 SCD1U10V2KX-5GPC2308 SCD1U10V2K X-5GP C2304 SCD1U10V2KX-5GPC2304 SCD1U10V2K X-5GP

12

2310 SCD1U10V2KX-5GP

12

12 12

A00-0104-1

RN2311

CLK_PCIE_NEW #[34] CLK_PCIE_NEW[34]

NEWCA RD_CLKREQ#[34]

CLK_PCIE_MINI1#[64] CLK_PCIE_MINI1[ 64]

MINI1_CLKREQ#[64]

CLK_PCIE_LAN#[76] CLK_PCIE_LAN[76]

CLKREQ#_LAN[76]

CLK_PCIE_MINI2#[76]

B B

CLK_PCIE_MINI2[ 76]

RN2311 0R4P2R-PAD

0R4P2R-PAD

RN2305

RN2305 0R4P2R-PAD

0R4P2R-PAD

RN2304

RN2304 0R4P2R-PAD

0R4P2R-PAD

RN2309

RN2309 0R4P2R-PAD

0R4P2R-PAD

PEG_B_CLKRQ#[21]

1 2 3

2 3 1

P P

PCIE_ITXN3_LRXN3_C PCIE_ITXP3_LRXP3_C

PCIE_ITXN4_MRXN4_C PCIE_ITXP4_MRXP4_C

PCIE_ITXN5_NRXN5_C PCIE_ITXP5_NRXP5_C

RN

CLK_PCIE_NEW 1#

4

CLK_PCIE_NEW 1

RN

CLK_PCIE_MINI1_1#

4

CLK_PCIE_MINI1_1

RN

CLK_PCIE_LAN1#

4

CLK_PCIE_LAN1

CLK_PCIE_MINI2_1# CLK_PCIE_MINI2_1

4

RN

PCIECLKRQ5#

PEG_B_CLKRQ#

CIE_ITXN2_MRXN2_C CIE_ITXP2_MRXP2_C

NEWCA RD_CLKREQ#

MINI1_CLKREQ#

CLKREQ#_LAN

MINI2_CLKREQ#

AW30

BA30 BC30 BD30

AU30 AT30 AU32 AV32

BA32 BB32 BD32 BE32

BF33 BH33 BG32

BJ32

BA34

AW34

BC34 BD34

AT34 AU34 AU36 AV36

BG34

BJ34

BG36

BJ36

AK48 AK47

AM43 AM45

AM47 AM48

AH42 AH41

AM51 AM53

AJ50 AJ52

AK53 AK51

P13

Pull up in page 21 for layout convenience

+3.3V_RUN

12

R2333

R2333 10KR2J-3-GP

10KR2J-3-GP

A A

MINI2_CLKREQ_R#[76]

1ST: 84.03904.H11 2ND: 84.03904.L06

5

Q2306_1

1

Q2306

Q2306 MMBT3904-7-F-GP

MMBT3904-7-F-GP

MINI2_CLKREQ#

3

2

R2309 0R2J-2-GP

1 2

DY

4

U

2001B

P

ERN1

P

ERP1 ETN1

P P

ETP1

P

ERN2 ERP2

P

WLAN

P

ETN2 ETP2

P

PERN3 PERP3

LAN

PETN3 PETP3

PERN4 PERP4

WWAN

PETN4 PETP4

PERN5

New

PERP5 PETN5

Card

PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

P9

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

U4

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

N4

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

M9

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

H6

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

IBEXPEAK-M-GP- NF

+3.3V_ALW

+3.3V_RUN

4

RN2307

8 7 6

SRN10KJ-7GP

RN2308

8 7 6

SRN10KJ-6-GP

S

MBALERT#/GPIO11

S

ML0ALERT#/GPIO60

SML1ALERT#/GPIO74

SMBus

PCI-E*

Controller

PEG

CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P

From CLK BUFFER

Clock Flex

PCIECLKRQ5#

1

USB_OC#12_13

2

CLKREQ#_LAN

3

MINI2_CLKREQ#

45

NEWCA RD_CLKREQ#

1

KB_DET_R#

2

GPO_DSM

3

MINI1_CLKREQ#

45

SB-1023 RN2308 change to 2*1 size

SML1CLK/GPIO58

SML1DATA/GPIO75

Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N/CKSSCD_N

CLKIN_SATA_P/CKSSCD_P

CLKIN_PCILOOPBACK

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

SB swap net for layout

SB-1026 swap net for layout

2

OF 10

MBCLK

S

MBDATA

S

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

USB_OC#12_13 [21]

S

B9

P

H14

P

C8

S

J14

S

C6

SML0_DATA

G8

SML1ALERT#

M14

KBC_SCL1

E10

KBC_SDA1

G12

CL_CLK

T13

CL_DATA

T11

CL_RST#

T9

PEG_CLKREQ#

H1

CLK_PCIE_VGA1#

AD43

CLK_PCIE_VGA1

AD45

CLK_EXP_N

AN4

CLK_EXP_P

AN2

AT1 AT3

CLKIN_DMI#

AW24

CLKIN_DMI

BA24

CLK_CPU_BCLK#

AP3

CLK_CPU_BCLK

AP1

DREFCLK#

F18

DREFCLK

E18

CLK_PCIE_SATA#

AH13

CLK_PCIE_SATA

AH12

CLK_PCH_14M

P41

CLK_PCI_FB

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

XCLK_RCOMP

AF38

TP_CLK_OUTFLEX0

T45

TP_CLK_PCI_LPC

P43

TP_CLK_PCH_REF14

T42

CLK48M/EDID_SEL

N50

KB_DET_R# [25] GPO_DSM [2 4,76]

3

ML0ALERT#

S

ML1ALERT#

MBALERT#

CH_SMB_CLK

CH_SMB_DATA

ML0ALERT#

ML0_CLK

S

R

12

2301 10KR2J-3-GP

R

SRN10KJ-5-GP

+

emove XDP

pull-up

1

TP2301 TPAD14-GPT P2301 TPAD14-G P

1

TP2302 TPAD14-GPT P2302 TPAD14-G P

1

TP2303 TPAD14-GPT P2303 TPAD14-G P

RN2327

RN2327 0R4P2R-PAD

0R4P2R-PAD

1 2

R2307 0R0402- PAD-2-GPR2307 0R0402-PAD-2-G P

SB-1020 move EDID_SELECT# from GPIO66 to GPIO5

3

1 2 3

CLK_EXP_N [ 9] CLK_EXP_P [9]

CLKIN_DMI# [7] CLKIN_DMI [7]

CLK_CPU_BCLK# [7] CLK_CPU_BCLK [7]

DREFCLK# [7] DREFCLK [7]

CLK_PCIE_SATA# [7] CLK_PCIE_SATA [7]

CLK_PCH_14M [7]

CLK_PCI_FB [21]

1 2

R2306 90D9R2F -1-GPR2306 90D9R2F -1-GP

TP2307

1

TPAD14-GP

TP2305

1

TPAD14-GP

TP2306

1

TPAD14-GP

A00-0104-1

N2301

R

1 2 3

3.3V_ALW

CH_SMB_CLK [34]

P

CH_SMB_DATA [34]

P

KBC_SCL1 [37]

KBC_SDA1 [37]

+3.3V_ALW

12

R2304

R2304 10KR2J-3-GP

10KR2J-3-GP

RN

A00-0104-1

4

+1.05V_VTT

+

3.3V_ALW

4

SB-1020

CLK_PCIE_VGA# [80] CLK_PCIE_VGA [80]

CLK_PCH_48M [32]

2

+

3.3V_ALW

1

23

R

N2313

SRN2K2J-1-GP

4

PCH_SMB_DATA

PCH_SMB_CLK

DGPU_1D8V_PGOOD[25,51]

+3.3V_RUN

3.3V_ALW

P

CH_SMB_CLK

PCH_SMB_DATA

RN2303

2 3 1

SRN2K2J-1-GP

6

5

1

23

R

N2302

SRN2K2J-1-GP

4

1

2

34

Q2301

Q2301 DMN66D0LDW -7-GP

DMN66D0LDW -7-GP

PEG_CLKREQ#

G

S D

Q2305

Q2305 2N7002A-7-GP

2N7002A-7-GP

1

SB-1020

PCH_SMBDATA [7,18,1 9,40,64,76]

1ST: 84.DMN66.03F 2ND: 84.27002.F3F

PCH_SMBCLK [ 7,18,19,40,64,76]

1ST: 84.2N702.E31 2ND: 84.2N702.D31

un-stuff 25M X'tal without HDMI/eDP/DP

SC-1125-1 C2313 pop 0 ohm if no use 25MHz XTAL

C2313

XTAL25_IN

12

DY

R2380

1MR2J-1-GP

XTAL25_OUT

SB-1104 pop for 25MHz

1st Samsung

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

C2313

12

0R2J-2-GP

12

DY

X2301

12

XTAL-25MHZ-67GP

DY

C2307

C2307 SC18P50V2JN-1-G P

SC18P50V2JN-1-G P

Wistron Corporation

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

1

A00

23 88Wednesday, January 13, 2010

A00

5

CH_RTCX 1

P

CH_RTCX 2

1 2

2401

R

R 10MR2J-L -GP

10MR2J-L -GP

X

2401

1

4

12

C

2402

SC12P50 V2JN-3GP

D D

S

B-18

1st: EPSON 82.30001.861 2nd: QUARTECH 82.30001.A81

DW

07/23 Added

1.Added "ME in Manufacturing Mode" strap

2.Added CardReader_Wake# to s ent Card detect signal for P CH . ( Only For JMB380 )

3rd: KDS 82.30001.691

Flash Descriptor Security Override/ ME Debug Mode

ME_UNLOCK#

C C

1 2

R2419 1KR2J-1-GP

+3.3V_RU N

B B

SB-1026

1. remove R2411 pull high INT_SERIRQ to RN2501.1

NO REBOOT STRAP

1 2

DY

R2410 1KR2J-1-GP

DW

07/02 Change

1.Change R2410 to dummy

2 3

X-32D768 KHZ-46GP

This strap should only be asserted low via external pull down in manufacturing/debug environments ONLY.

DY

SB_SPKR

ME_UNLO CK_R#

P

12

C

2403

SC12P50 V2JN-3GP

No Reboot Strap R23

HDA_SPKR

Low = Default High = No Reboot

RTC_CEL L

+

RTC_CEL L

+

1 2

C

2401

SC1U6D3 V3KX-2GP

1 2

C2404

SC1U6D3 V3KX-2GP

2402

R

R 20KR2J-L 2-GP

20KR2J-L 2-GP

R

2403

20KR2J-L 2-GP

4

I

NTVRMEN- Integrated SUS

12

21

12

G2401

G2401 GAP-OPEN

GAP-OPEN

+RTC_CE LL

PCH_AZ_ CODEC_BITCLK[30]

PCH_AZ_ CODEC_SYNC[30]

PCH_AZ_ CODEC_RST#[30]

PCH_SDIN_ CODEC[30]

SB_SPKR[30]

PCH_SDO UT_CODEC[30]

ME_UNLO CK#[37]

PCH_SPI_C LK[62]

PCH_SPI_C S0#[62]

PCH_SPI_D O[62]

PCH_SPI_D I[62]

SC-1208-1 change R2413,R2414,R2415 from 15ohm to 0 ohm

1.1V VRM Enable High - Enable internal VRs

1 2

R2406 1MR 2J-1-GPR2406 1MR2J-1 -GP

1 2

R2404 33 0KR2F-L-GPR2404 330 KR2F-L-GP

1 2

R2417

1 2

0R0402-P AD-2-GP

A00-0104-1

R2413 0R2J-2-GPR2413 0R2J-2-GP

R2414 0R2J-2-GPR2414 0R2J-2-GP

R2415 0R2J-2-GPR2415 0R2J-2-GP

33R2J-2-G PR24 05 33R2J-2-GPR2 405

33R2J-2-G PR24 07 33R2J-2-GPR2 407

33R2J-2-G PR24 08 33R2J-2-GPR2 408

33R2J-2-G PR24 09 33R2J-2-GPR2 409

TP2404TP 2404

TP2405TP 2405

TP2406TP 2406

TP2407TP 2407

TP2408TP 2408

1 2

3

CH_RTCX 1

P

CH_RTCX 2

P

PCH_RTC RST#

SRTCRST #

SM_INTRUD ER#

PCH_INTVR MEN

ACZ_BIT_C LK

ACZ_SYNC_ R

ACZ_RST #_R

ACZ_SDA TAOUT_R

ME_UNLO CK_R#

PCH_JTA G_TCK

1

PCH_JTA G_TMS

1

PCH_JTA G_TDI

1

PCH_JTA G_TDO

1

PCH_JTA G_RST#

1

SPI_CLK_R

SPI_CS#0_ R

SPI_MOSI_R

U

2001A

B13

TCX1

R

D13

TCX2

R

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN#/GPIO33

J30

HDA_DOCK_RST#/GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M -GP-NF

RTCIHDA

SPI JTAG

WH0/LAD0

F

WH1/LAD1

F FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

LPC

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

1

OF 10

LDRQ0#

SERIRQ

2

PC_LAD0

D33 B33 C32 A32

C34

A34 F34

AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16

AF15

T3

Y9

V1

L

PC_LAD1

L L

PC_LAD2

LPC_LAD 3

SATA_ITXN 0_HRXN0_C SATA_ITXP 0_HRXP0_C

SATA_ITXN 1_ORXN1_C SATA_ITXP 1_ORXP1_C

SATAICOMP

GPO_DSM

PCH_GPIO19

DW

07/10 assign GPIO

1.assign GPIO GPIO_DSM,Felic_ DETECT#

S

SID = PCH

L

PC_LAD[0 ..3]

LPC_LFR AME# [36,37,70 ]

INT_SERIRQ [25,36,37 ]

C2405 SC D01U25V2KX-3G PC2405 SC D01U25V2KX-3G P

1 2

C2406 SC D01U25V2KX-3G PC2406 SC D01U25V2KX-3G P

1 2

C2407 SC D01U25V2KX-3G PC2407 SC D01U25V2KX-3G P

1 2

C2408 SC D01U25V2KX-3G PC2408 SC D01U25V2KX-3G P

1 2

R2412 37D4R2F-G PR24 12 37D4R2F -GP

SATA_LE D# [66]

GPO_DSM [2 3,76]

PCH_GPIO19 [25]

PC_LAD[0 ..3] [36,37 ,70]

L

+1.05V_V TT

1

HDD

SATA_IRXN 0_HTXN0_C [59] SATA_IRXP 0_HTXP0_C [59 ] SATA_ITXN 0_HRXN0 [59] SATA_ITXP 0_HRXP0 [59]

ODD

SATA_IRXN 1_OTXN1_C [59] SATA_IRXP 1_OTXP1_C [59] SATA_ITXN 1_ORXN1 [59] SATA_ITXP 1_ORXP1 [59]

ESATA

ESATA_IRX _DTX_N4_C [63] ESATA_IRX _DTX_P4_C [63 ]

ESATA_ITX _DRX_N4 [63] ESATA_ITX _DRX_P4 [63]

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Do cument Number Rev

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

24 88Wednesd ay, January 13, 2010

1

A00

5

R

2555

2K2R2J-2 -GP

2515_1

Q

2515

B-32

S

R2525

R2525 10KR2J-3 -GP

10KR2J-3 -GP

1 2

+3.3V_AL W

+3.3V_RU N

3.3V_RUN

+

12

R

2503

10KR2J-3 -GP

B

IO_DET#[78]

E

CSMI#[37]

A00-0104-1

R2505 0R0 402-PAD-2-GPR2 505 0R04 02-PAD-2-GP R2506 0R0 402-PAD-2-GPR2 506 0R04 02-PAD-2-GP

R3749 100 R2J-2-GPR3749 100 R2J-2-GP

KB_DET#[68]

KB_DET_ R#[2 3]

DGPU_HO LD_RST#[80]

1 2 1 2

1 2

PCH_GPIO3 5

DGPU_PW R_EN#[37]

R2548 100 R2J-2-GPR2548 100R2J -2-GP

DDR_RST _GATE#[9]

TURBO_B OOST_ALERT#[37]

For layout request

3.3V_RUN _GPU+3.3V_RUN _GPU

+

2552

R

R 10KR2J-3 -GP

10KR2J-3 -GP

D

EEPIDLE_W AKE_INT_R#[81]

D D

+3.3V_RU N

R2507

R2507 10KR2J-3 -GP

10KR2J-3 -GP

DGPU_PW ROK

1 2

C C

R2526

R2526 10KR2J-3 -GP

10KR2J-3 -GP

1 2

B B

PCH_GPIO2 7

DY

07/10 Added

1.Changed PCH GPIO DDR_RST_GA TE from GPIO57 to GPIO46 , B ason on design guide 07/23 Added

1.Added Finger Printer Detect Pin, control by PCH

2.Change KB_DET signal from E C to PCH control

3.Change LCD_CBL_DET signal f rom EC to PCH control

PCH_GPIO2 8

PCH_GPIO1 5

PCIECLKRQ 6#

SBswap net for layout

ECSMI# PCH_GPIO5 7

E

CSWI#[3 7]

C2501

C2501 SC47P50 V2JN-3GP

SC47P50 V2JN-3GP

GFX_COR E_PGOOD[86]

DGPU_1D 8V_PGOOD[23,51]

LCD_CBL _DET#[5 4]

1 2

R2530 10K R2J-3-GPR2530 1 0KR2J-3-GP

1 2

R2532 1KR 2J-1-GPR2532 1KR2J-1-G P

1 2

R2521 10K R2J-3-GPR2521 1 0KR2J-3-GP

RN2504

1 2 3

SRN10KJ -5-GP

12

Q

1 2

312

MMBT390 4-7-F-GP

12

DY

DW

07/02 Change

1.Change CLK_SATA_OE# to pull -down

4

SB-1023

LCD_CBL _DET_R#

DGPU_HO LD_RST#

STP_PCI#

A A

PCH_GPIO1 9[24]

R2520 10KR2J-3 -GPR2 520 10KR2J-3 -GP

R2516 10KR2J-3 -GP

1 2

DY

R2517 10KR2J-3 -GPR2 517 10KR2J-3 -GP

1 2

SRN10KJ -5-GP

PCH_GPIO1 9 PCH_GPIO3 8

2 3 1

RN2503

SB-1026 swap net for layout

RN2503

5

12

+3.3V_RU N

4

INT_SERIRQ[24,36,37]

BIO_DET#[78]

INT_SERIRQ FFS_INT2_ R DGPU_PW R_EN# BIO_DET#

E

CSCI#[37]

TP2508T PAD14-GP TP2508TP AD14-GP

1 2

FFS_INT2_ R[40]

TP2511T PAD14-GP TP2511TP AD14-GP

TP2512T PAD14-GP TP2512TP AD14-GP

TP2510T PAD14-GP TP2510TP AD14-GP TP2509T PAD14-GP TP2509TP AD14-GP

ECSW I# ECSCI#

4

D

EEP_IDLE#

E

CSCI#

B

IO_DET#

CSWI#

E

CSMI#

E

PCH_GPIO1 5

DGPU_HO LD_RST#

LCD_CBL _DET_R#

PCH_GPIO2 7

PCH_GPIO2 8

1

STP_PCI#

DGPU_PW R_EN#

DGPU_PR SNT#

PCH_GPIO3 8

PCIECLKRQ 6#

DDR_RST _GATE#

FFS_INT2_ R

TURBO_B OOST_ALERT#

PCH_GPIO5 7

PCH_NCT F_2

1

PCH_NCT F_3

1

PCH_NCT F_1

1

PCH_NCT F_4

1

SRN10KJ -5-GP

2 3 1

RN2502

RN2501

1 2 3 4 5

SRN10KJ -6-GP

4

U

2001F

Y3

B

MBUSY#/GPIO0

C38

T

ACH1/GPIO1

D37

T

ACH2/GPIO6

J32

ACH3/GPIO7

T

F10

PIO8

G

K9

LAN_PHY_PWR_CTRL/GPIO12

T7

GPIO15

AA2

DGPU_PW ROK

KB_DET_ R#

+3.3V_RU N

4

+3.3V_RU N

8 7 6

SB-1023 RN2501 change to 2*1 size

SATA4GP/GPIO16

F38

TACH0/GPIO17

Y7

SCLOCK/GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI#/GPIO34

V6

SATACLKREQ#/GPIO35

AB7

SATA2GP/GPIO36

AB13

SATA3GP/GPIO37

V3

SLOAD/GPIO38

P3

SDATAOUT0/GPIO39

H3

PCIECLKRQ6#/GPIO45

F1

PCIECLKRQ7#/GPIO46

AB6

SDATAOUT1/GPIO48

AA4

SATA5GP/GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M -GP-NF

GPIO

NCTF

DGPU_PR SNT#

3

C C

C

R2528

R2528 10KR2J-3 -GP

10KR2J-3 -GP

C

MISC

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

CPU

RSVD

+3.3V_RU N

12

R2527

DY

10KR2J-3 -GP

12

3

6

OF 10

LKOUT_PCIE6N

LKOUT_PCIE6P

LKOUT_PCIE7N

LKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

INIT3_3V#

TP24

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

AH45 AH46

AF48 AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

AW22

BB22

AY45

AY46

AV43

AV45

AF13

M18

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

INIT3_3V#

2

KA20GAT E [37 ]

BCLK_CP U_N [9]

BCLK_CP U_P [9]

H_PECI [9]

H_PW RGOOD [9,42 ]

PCH_THE RMTRIP_R

TP2506TPAD14-GPTP 2506TPAD14-GP

1

2

S

SID = PCH

KBRCIN# [37]

1 2

R2511

56R2J-4-G P

1st Samsung

Title

Size Document N umber Rev

Date: Sheet of

1

+1.05V_V TT

R2509

R2509 56R2J-4-G P

56R2J-4-G P

1 2

H_THRMT RIP# [9 ,37,42]

Placed Within 2" from PCH

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (GPIO/CPU)

Winery13 MB DIS

1

A00

25 88Wednesd ay, January 13, 2010

A00

5

SID = PCH

S

+

1.05V_VT T

1

.432A

SC10U6D 3V5KX-1GP

D D

+1.05V_V TT

C C

B B

3.062A

+1.05V_V TT

SC10U6D 3V5KX-1GP

12

C2608

SC10U6D3V5KX-1GP

12

C2609

TP2601

12

C

2601

TP2602 T PAD14-GPTP2602 TPAD 14-GP

12

C2610

SC1U10V3KX-3GP

SCD1U10 V2KX-4GP

+1.8V_RU N

1

TPAD14-G P

4

12

C

D

Y

SC1U6D3 V2KX-GP

1

12

C2611

SC1U10V3KX-3GP

12

C2614

A00-0104-1

R2606

0R0402-P AD-2-GP

2602

+1.05V_V TT

SB-21

12

C2612

SC1U10V3KX-3GP

+3.3V_RU N

357mA

+VCC_VR M

12

VCCFDIPLL

SB-20

VCCAPLL EXP

U

AB24

V

AB26

V

AB28

V

AD26

V

AD28

V

AF26

V

AF28

V

AF30

V

AF31

VCCCORE

AH26

VCCCORE

AH28

VCCCORE

AH30

VCCCORE

AH31

VCCCORE

AJ30

VCCCORE

AJ31

VCCCORE

AK24

VCCIO

BJ24

VCCAPLLEXP

AN20

VCCIO

AN22

VCCIO

AN23

VCCIO

AN24

VCCIO

AN26

VCCIO

AN28

VCCIO

BJ26

VCCIO

BJ28

VCCIO

AT26

VCCIO

AT28

VCCIO

AU26

VCCIO

AU28

VCCIO

AV26

VCCIO

AV28

VCCIO

AW26

VCCIO

AW28

VCCIO

BA26

VCCIO

BA28

VCCIO

BB26

VCCIO

BB28

VCCIO

BC26

VCCIO

BC28

VCCIO

BD26

VCCIO

BD28

VCCIO

BE26

VCCIO

BE28

VCCIO

BG26

VCCIO

BG28

VCCIO

BH27

VCCIO

AN30

VCCIO

AN31

VCCIO

AN35

VCC3_3

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO

IBEXPEAK-M -GP-NF

2001G

CCCORE CCCORE CCCORE CCCORE CCCORE CCCORE CCCORE CCCORE

1

.432A

3.062A

OWER

P

VCC CORE

PCI E*

FDI

3

7

V

CCADAC

V

CCADAC

V

<1mA

59mA

357mA

85mA

SSA_DAC

V

SSA_DAC

VCCALVDS

VSSA_LVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

VCC3_3

VCCVRM

VCCDMI

VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND

VCCME3_3 VCCME3_3 VCCME3_3 VCCME3_3

CRTLVDS

HVCMOS

DMI

156mA

NAND / SPI

OF 10

2

L

2603

+

AE50

AE52

AF53

AF51

AH38

AH39

AP43 AP45 AT46 AT45

AB34

AB35

AD35

AT24

AT16

AU16

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AM8 AM9 AP11 AP9

VCCA_DA C_1_2

12

C

2604

SCD01U16V2KX-3GP

+3VS_VC CA_LVD +3.3V_RU N

C2623

1 2

DY

SCD1U10 V2KX-5GP

SCD01U16V2KX-3GP

12

C2625

12

+1.8VS_V CCTX_LVDS

SCD01U16V2KX-3GP

12

C2624

357mA

C2607

C2607 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

+VCC_VR M

12

C

2605

DY

12

C

SCD1U10V2KX-5GP

SC10U6D 3V5MX-3GP

12

C2626

C2626 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

+3.3V_RU N

2603

35mA

R2601

1 2

0R0402-P AD-2-GP

12

C2613

C2613 SC1U10V 3KX-3GP

SC1U10V 3KX-3GP

156mA

12

C2615

C2615 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

85mA

PCH_VCC ME3_3

12

C2622

C2622 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

0R0402-P AD-2-GP

A00-0104-1

+3.3V_RU N

A00-0104-1

R2605

0R0402-P AD-2-GP

2603

1 2

BLM18PG 181SN1D-GP

R2609

0R0603-P AD-2-GP

A00-0104-1

1 2

L2604

L2604 IND-D1UH-21-G P

IND-D1UH-21-G P

SC10U6D 3V5MX-3GP

58mA

+3.3V_RU N

12

<1mA

12

59mA

+1.05V_V TT+1.05VS _VCC_DMI

C2628

+

3.3V_CRT _LDO

+1.8V_RU N

12

DY

69mA

R

2602

1 2

0R0402-P AD-2-GP

A00-0104-1

U2601

5

OUT

GND

DY

4

SHDN#

NC#4

MAX8511 EXK33-T-GP

IN

1

2

3

+

3.3V_RUN

+5V_RUN+3.3V_CR T_LDO

C2629

SC1U10V 3KX-3GP

DY

12

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

PCH (POWER1)

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

26 88Wednesd ay, January 13, 2010

1

A00

5

P2701

T

S

SID = PCH

S

D D

B-15

+1.05V_V TT

T

1.849A

C2705

SC10U6D 3V5KX-1GP

SB-17

+1.05V_V TT

C C

L2702

1 2

IND-10UH-218 -GP

SC10U6D 3V5MX-3GP

L2703

1 2

IND-10UH-218 -GP

SC10U6D 3V5MX-3GP

+1.05VS_ VCCA_A_DPL

12

C2734

DY

+1.05VS_ VCCA_B_DPL

12

C2735

DY

SC10U6D 3V5KX-1GP

12

C2711

C2711 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

12

C2714

C2714 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

C2705

C2704

SCD1U10 V2KX-4GP

68mA 69mA

+1.05V_V TT

12

C2718

SC1U6D3 V2KX-GP

B B

+3.3V_AL W

C2726

C2726 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

+1.05V_V TT

12

C2728

SC10U6D 3V5KX-1GP

A A

C2728

C2723

SCD1U10 V2KX-4GP

163mA

12

<1mA

SCD1U16 V2KX-3GP

+RTC_CE LL

C2719

SC1U6D3 V2KX-GP

12

SCD1U10 V2KX-4GP

12

C2729

SCD1U16 V2KX-3GP

2mA

5

4

CCACLK

V

1

TPAD14-G P

C

2707

SCD1U10 V2KX-4GP

12

C2713

+VCCSST

SCD1U10V2KX-4GP

2707

SC1U6D3 V2KX-GP

12

+VCC_VR M

+1.05VS_ VCCA_A_DPL

+1.05VS_ VCCA_B_DPL

12

SC1U6D3 V2KX-GP

+1.05VAL W_INT_VCCSU S

12

C2724

C2724 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

+3.3V_RU N

C2727

C2730

SCD1U10V2KX-4GP

12

C2732

4

D

CPSUSBYP

12

C2708

DY

C2710

DY

+VCCRTC EXT

C2720

12

C2733

3

0 OF 10

1

163mA

<1mA

196mA

6mA

HDA

V V V V V V V VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCSUS3_3

V5REF_SUS

<1mA

VCCSATAPLL VCCSATAPLL

VCCSUSHDA

1

CCIO

V V

CCIO

V

CCIO

V

CCIO

CCSUS3_3 CCSUS3_3 CCSUS3_3 CCSUS3_3 CCSUS3_3 CCSUS3_3 CCSUS3_3

VCCIO

V5REF

VCC3_3

VCCIO

VCCVRM

VCCIO

VCCIO VCCIO VCCIO VCCIO

VCCME VCCME VCCME VCCME

3

V24 V26 Y24 Y26

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23

V23

+5VALW _PCH_VCC5R EFSUS

F24

+5VS_PC H_VCC5REF

K49

J38

L38

M36

N36

P36

U35

AD13

VCCSATA PLL

AK3 AK1

AH22

AT20

AH19

AD20

AF22

AD19 AF20 AF19 AH20

AB19 AB20 AB22 AD22

AA34 Y34 Y35 AA35

6mA

L30

+3VS_+1 .5VS_HDA_IO

+3.3V_AL W

12

+3.3V_RU N

12

+VCC_VR M

12

C2731

C2731 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

12

C

2706

SC1U10V 2KX-1GP

D

Y

12

2703

C

C SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

C2709

C2709 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

+1.05V_V TT

C2716

C2716 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

1

TPAD14-G P

R2707

1 2

0R0402-P AD-2-GP

P

OWER

2001J

U

AP51

CCACLK

V

AP53

V

CCACLK

AF23

V

CCLAN

AF24

V

CCLAN

Y20

D

CPSUSBYP

AD38

VCCME

AD39

VCCME

AD41

VCCME

AF43

VCCME

AF41

12

VCCME

AF42

VCCME

V39

VCCME

V41

VCCME

V42

VCCME

Y39

VCCME

Y41

VCCME

Y42

VCCME

V9

DCPRTC

AU24

VCCVRM

BB51

VCCADPLLA

BB53

VCCADPLLA

BD51

VCCADPLLB

BD53

VCCADPLLB

AH23

VCCIO

AJ35

VCCIO

AH35

VCCIO

AF34

VCCIO

AH34

VCCIO

AF32

VCCIO

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3

U19

VCCSUS3_3

U20

VCCSUS3_3

U22

VCCSUS3_3

V15

VCC3_3

V16

VCC3_3

Y16

VCC3_3

AT18

V_CPU_IO

AU18

V_CPU_IO

A12

VCCRTC

IBEXPEAK-M -GP-NF

OWER

52mA

320mA

USB

1.849A

68mA

Clock and Miscellaneous

69mA

PCI/GPIO/LPC

SATA

<1mA

CPU

2mA

RTC PCI/GPIO/LPC

TP2702

2

+3.3V_AL W

21

12

+3.3V_RU N

SB-16

SC1U6D3 V2KX-GP

+1.05V_V TT

A00-0104-1

2

+

1.05V_VT T

+

3.3V_ALW

D2701

D2701 CH751H-4 0PT-GP

CH751H-4 0PT-GP

1 2

R2701

R2701 100R2J-2 -GP

100R2J-2 -GP

C2712

C2712 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

12

C2717

C2717 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

C2725

+3.3V_AL W

1

DW

07/10 Change resistor Value

1.R2701,R2702 value corrected to 100 Ohms following PDG d oc

+5V_ALW

+3.3V_RU N

21

D2702

D2702 CH751H-4 0PT-GP

CH751H-4 0PT-GP

1 2

R2702

12

+1.05V_V TT

12

1st Samsung

Title

PCH (POWER2)

Size Document N umber Rev

Date: Sheet of

PCH (POWER2)

R2702 100R2J-2 -GP

100R2J-2 -GP

C2715

SC1U6D3 V2KX-GP

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

+5V_RUN

27 88Wednesd ay, January 13, 2010

1

A00

5

S

SID = PCH

D D

C C

B B

A A

5

2001H

U

AB16

V

AA19

VSS

AA20

VSS

AA22

VSS

AM19

VSS

AA24

VSS

AA26

VSS

AA28

VSS

AA30

VSS

AA31

VSS

AA32

VSS

AB11

VSS

AB15

VSS

AB23

VSS

AB30

VSS

AB31

VSS

AB32

VSS

AB39

VSS

AB43

VSS

AB47

VSS

AB5

VSS

AB8

VSS

AC2

VSS

AC52

VSS

AD11

VSS

AD12

VSS

AD16

VSS

AD23

VSS

AD30

VSS

AD31

VSS

AD32

VSS

AD34

VSS

AU22

VSS

AD42

VSS

AD46

VSS

AD49

VSS

AD7

VSS

AE2

VSS

AE4

VSS

AF12

VSS

Y13

VSS

AH49

VSS

AU4

VSS

AF35

VSS

AP13

VSS

AN34

VSS

AF45

VSS

AF46

VSS

AF49

VSS

AF5

VSS

AF8

VSS

AG2

VSS

AG52

VSS

AH11

VSS

AH15

VSS

AH16

VSS

AH24

VSS

AH32

VSS

AV18

VSS

AH43

VSS

AH47

VSS

AH7

VSS

AJ19

VSS

AJ2

VSS

AJ20

VSS

AJ22

VSS

AJ23

VSS

AJ26

VSS

AJ28

VSS

AJ32

VSS

AJ34

VSS

AT5

VSS

AJ4

VSS

AK12

VSS

AM41

VSS

AN19

VSS

AK26

VSS

AK22

VSS

AK23

VSS

AK28

VSS

IBEXPEAK-M -GP-NF

SS

4

8

OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

2001I

U

AY7

V

B11

V

B15

V

B19

V

B23

V

B31

V

B35

V

B39

V

B43

V

B47

V

B7

V

BG12

V

BB12

V

BB16

V

BB20

VSS

BB24

VSS

BB30

VSS

BB34

VSS

BB38

VSS

BB42

VSS

BB49

VSS

BB5

VSS

BC10

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC32

VSS

BC36

VSS

BC40

VSS

BC44

VSS

BC52

VSS

BH9

VSS

BD48

VSS

BD49

VSS

BD5

VSS

BE12

VSS

BE16

VSS

BE20

VSS

BE24

VSS

BE30

VSS

BE34

VSS

BE38

VSS

BE42

VSS

BE46

VSS

BE48

VSS

BE50

VSS

BE6

VSS

BE8

VSS

BF3

VSS

BF49

VSS

BF51

VSS

BG18

VSS

BG24

VSS

BG4

VSS

BG50

VSS

BH11

VSS

BH15

VSS

BH19

VSS

BH23

VSS

BH31

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH47

VSS

BH7

VSS

C12

VSS

C50

VSS

D51

VSS

E12

VSS

E16

VSS

E20

VSS

E24

VSS

E30

VSS

E34

VSS

E38

VSS

E42

VSS

E46

VSS

E48

VSS

E6

VSS

E8

VSS

F49

VSS

F5

VSS

G10

VSS

G14

VSS

G18

VSS

G2

VSS

G22

VSS

G32

VSS

G36

VSS

G40

VSS

G44

VSS

G52

VSS

AF39

VSS

H16

VSS

H20

VSS

H30

VSS

H34

VSS

H38

VSS

H42

VSS

IBEXPEAK-M -GP-NF

3

9

OF 10

H49

SS SS SS SS SS SS SS SS SS SS SS SS SS SS

3

V V V V V V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SS

H5

SS

J24

SS

K11

SS

K43

SS

K47

SS

K7

SS

L14

SS

L18

SS

L2

SS

L22

SS

L32

SS

L36

SS

L40

SS

L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

2

1st Samsung

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

PCH (VSS)

1

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

28 88Wednesd ay, January 13, 2010

1

A00

5

SID = AUDIO

S

+

3.3V_RUN

A

00-0104-1

0R0402-P AD-2-GP

3011

R

D D

C C

R

1 2

C3027

C3027 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

1 2

PCH_AZ_ CODEC_BITCLK

12

C3012

DY

SC4D7P5 0V2CN-1GP

+3.3V_RU N

12

R3020

R3020 10KR2J-3 -GP

10KR2J-3 -GP

AMP_MUT E#

+

3.3V_RUN

C

lose to codec

12

C

C SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

PCH_AZ_ CODEC_BITCLK[24]

PCH_SDIN_ CODEC[24]

PCH_SDO UT_CODEC[2 4]

PCH_AZ_ CODEC_SYNC[24]

PCH_AZ_ CODEC_RST#[24]

AUD_DMIC_ IN0[73]

3009

12

Internal pull up 60K check external pull up??

+3.3V_RU N

AUD_DMIC_ CLK_Y

12

0R2J-2-GP

DY

R3017

B B

AUD_DMIC_ CLK_G[73]

EC3001

SC22P50 V2JN-4GP

EC3001

DY

12

5

4

1 2

U3002

OE#

VCC

DY

GND

Y

74LVC1G 125DC-GP

R3014

33R2J-2-G P

4

C

3019

SCD1U10 V2KX-4GP

1 2

AMP_MUT E#[37]

SC2D2U2 5V5KX-1GP

1 2

A

3

33R2J-2-G PR3013 33R2 J-2-GPR3013

12

C3024

AUD_DMIC_ CLK

C

lose to codec

A

UD_DVDD CORE

12

C

3016

SC10U6D 3V5MX-3GP

DVDDIO

PCH_AZ_ CODEC_BITCLK

PCH_SDIN_ CODEC_C0

PCH_SDO UT_CODEC

PCH_AZ_ CODEC_SYNC

PCH_AZ_ CODEC_RST#

AUD_DMIC_ CLK AUD_DMIC_ IN0

AMP_MUT E#

PUMP_CA PN

PUMP_CA PP

3001

U

1

DVDD_CORE

9

DVDD

3

DVDD_IO

6

HDA_BITCLK

8

HDA_SDI

5

HDA_SDO

10

HDA_SYNC

11

HDA_RST#

2

DMIC_CLK/GPIO1

4

DMIC0/GPIO2

46

DMIC1/GPIO0/SPDIF_OUT_1

48

SPDIF_OUT_0

47

EAPD

35

CAP-

36

CAP+

7

DVSS

33

AVSS

30

AVSS

26

AVSS

42

PVSS

49

GND

92HD79B 1A5NLGXTAX-GP

3

AVDD AVDD

PVDD PVDD

SENSE_A SENSE_B

HP0_PORT_A_L HP0_PORT_A_R

VREFOUT_A_OR_F

HP1_PORT_B_L HP1_PORT_B_R

PORT_C_L

PORT_C_R

VREFOUT_C

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R-

SPKR_PORT_D_R+

PORT_E_L

PORT_E_R

PORT_F_L

PORT_F_R

PC_BEEP

MONO_OUT

CAP2

VREFFILT

VREG

27 38

39 45

AUD_SEN SE_A

13

AUD_SEN SE_B

14

AUD_EXT _MIC_L

28

AUD_EXT _MIC_R

29

AUD_VRE FOUT_B

23

AUD_HP1 _JACK_L_C

31

AUD_HP1 _JACK_R_C

32

19 20 24

AUD_SPK _L+

40

AUD_SPK _L-

41

43 44

15 16

17 18

12

25

22

21

34

V-

37

SC-1204-5 connect U3001 pi n17, pin18 to p in12 net and ch ange R3016 to 12 0K for vendor r equest

AUD_PC_BEEP Trace width>15 mils

AUD_CAP 2

AUD_VRE FFLT

AUD_V_B

AUD_VRE G

12

C

3015

SCD1U10 V2KX-4GP

AUD_SPK _L+ [60]

AUD_SPK _L- [60]

AUD_PC_ BEEP

12

C3023

SC4D7U6D3V3KX-GP

2

A00-0104-1

AVDD

+

L

3004

1 2

0R0805-P AD-2-GP

12

AUD_EXT _MIC_L [60] AUD_EXT _MIC_R [60]

R3023 60D4R2F -GPR3023 60D4R2 F-GP

1 2

R3019 60D4R2F -GPR3019 60D4R2 F-GP

1 2

12

C3025

SC10U6D3V5MX-3GP

0R0805-P AD-2-GP

C

3022

SC1U10V 3KX-3GP

12

C3014

C3014 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

C3010

C3018

12

C3021

SC10U6D3V5MX-3GP

12

SCD1U10 V2KX-4GP

12

SCD1U10 V2KX-4GP

12

5V_RUN

+

12

C3017

C3017 SC1U10V 3KX-3GP

SC1U10V 3KX-3GP

AUD_VRE FOUT_B [60]

AUD_HP1 _JACK_L AUD_HP1 _JACK_R

SB_SPKR _R

KBC_BEE P_R

C3013

SC1U6D3V2KX-GP

PVDD

+

12

R3016

1 2

120KR2F -L-GP

1 2

R3024

499KR2F -1-GP

1

C3011

C3011 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

AUD_HP1 _JACK_L [60]

AUD_HP1 _JACK_R [60]

From SB

SB_SPKR [24 ]

KBC_BEE P [37]

From EC

A

00-0104-1

1 2

5V_RUN

+

L

3005

0R0805-P AD-2-GP

L3003

0R0805-P AD-2-GP

Close to codec

Azalia I/F EMI

PCH_SDO UT_CODEC

12

R3012

R3012 47R2J-2-G P

47R2J-2-G P

DY

PCH_AZ_ CODEC_SDOUT1

12

C3020

DY

SCD1U10 V2KX-4GP

A A

5

SCD1U10 V2KX-4GP

4

+AVDD

12

R3018

R3018 2K49R2F -GP

2K49R2F -GP

12

C3026

SC1KP50 V2KX-1GP

Place this block close to Audio Codec Pin13

AUD_SEN SE_A

12

R3022

R3022 20KR2F-L -GP

20KR2F-L -GP

12

R3021

R3021 39K2R2F -L-GP

39K2R2F -L-GP

EXT_MIC_J D# [60]

AUD_HP1 _JD# [60]

Revised HP/MIC detect circuit 2009/06/03

3

+AVDD

12

R3015

R3015 100KR2J -1-GP

100KR2J -1-GP

AUD_SEN SE_B

Close to Pin14

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

AUDIO CODEC_92HD81

30 88Wedn esday, January 13, 2010

1

A00

5

4

3

2

1

D D

C C

S

SID = SDIO

SCD1U10 V2KX-4GP

C3203

+3.3V_RU N

090721-1

1 2

+3.3V_RU N_CARD

12

C3204

DY

SC4D7U6 D3V3KX-GP

CLK_PCH _48M[23]

PCH GPIO67(48M) confirm with SW

RREF trace =15mils

090721-1

C3201

1 2

DY

SC100P5 0V2JN-3GP

R3201

1 2

6K2R2F-G P

USB_PN9[21 ] USB_PP9[21]

V18

12

C3202

C3202 SC1U10V 2KX-1GP

SC1U10V 2KX-1GP

RREF

1 2 3 4 5 6

25

RREF DM DP 3V3_IN CARD_3V3 V18

GND

22

23

24

XD_D7

CLK_IN

XD_CD#7SP18SP29SP310SP411SP5

SD_D2 SD_D3

SP1119SP1220SP1321SP14

GPIO0

12

SP10

SP9 SP8 SP7 SP6

U3201

U3201 RTS5138 -GR-GP

RTS5138 -GR-GP

SD_CMD

18 17 16 15 14 13

SD_D2 [33] SD_D3 [33]

SD_CLK

SD_CD#

SD_CMD [33]

SD_CLK [33 ]

SD_CD# [33]

+3.3V_RU N_CARD

+3.3V_RUN_CARD trace = 40mil

12

C3206

C3206 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

12

C3207

C3207 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

Close to chip

V18 trace =15mils

SD_D0 SD_D1

SD_W P

B B

SD_D0 [33] SD_D1 [33]

SD_W P [33]

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CardReader/RTS5138

Size Document N umber Rev

Custom

Date: Sheet of

CardReader/RTS5138

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

32 88Wedn esday, January 13, 2010

1

A00

5

SID = SDIO

S

D D

+

1ST: 20.I0045.001 2ND:

3.3V_RUN _CARD

SD_D0_R SD_D1_R SD_D2_R

S

D/MMC/MMC+ Card Reader

CARD1

4

VDD

CD/DAT3

CD/WP/GND

7

DAT0

8

DAT1

9

DAT2

NP1

NP2

CARD-PUS H-9P-1-GP-U

CLK

CMD

EMPTY

VSS1 VSS2

GND

WP

4

10

CD

1 11 12 5 2 14

3 6 13

SD_D3_R

SD_CLK_ R SD_CMD_ R

SD_CD# [32]

SD_W P [32]

3

+

3.3V_RUN _CARD

12

C3301

C3301 SCD1U16 V2KX-3GP

SCD1U16 V2KX-3GP

DY

Close to +3.3V_RUN_CARD

12

C3302

C3302 SCD1U16 V2KX-3GP

SCD1U16 V2KX-3GP

DY

12

C3303

SCD01U1 6V2KX-3GP

2

12

C3304

C3304 SC2D2U1 0V3KX-1GP

SC2D2U1 0V3KX-1GP

12

C3305

C3305 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

1

C C

SD_D0

R3301 33R2J-2-G PR3301 33R2 J-2-GP

SD_D0[32] SD_D1[32] SD_D2[32]

SD_D3[32]

SD_CLK[32]

SD_CMD[32]

SD_D1 SD_D2 SD_D3

SD_CLK

SD_CMD

1 2

R3302 33R2J-2-G PR3302 33R2 J-2-GP

1 2

R3303 33R2J-2-G PR3303 33R2 J-2-GP

1 2

R3304 33R2J-2-G PR3304 33R2 J-2-GP

1 2

R3305 33R2J-2-G PR3305 33R2 J-2-GP

1 2

R3306

1 2

33R2J-2-G P

SD_D0_R SD_D1_R SD_D2_R SD_D3_R SD_W P SD_CLK_ R SD_CD# SD_CMD_ R

12

EC3301

EC3301 SC6D8P5 0V2CN-GP

SC6D8P5 0V2CN-GP

SC-1207-1 pop EC3301,EC330 2,EC3303,EC3305 ,EC3306,EC3307, EC3308 and chang e from 100p to 6.8p for EMI

12

EC3302

EC3302 SC6D8P5 0V2CN-GP

SC6D8P5 0V2CN-GP

Close to CARD1

12

EC3303

EC3303 SC6D8P5 0V2CN-GP

SC6D8P5 0V2CN-GP

12

EC3304

EC3304 SC220P5 0V2KX-3GP

SC220P5 0V2KX-3GP

DY

12

EC3305

EC3305 SC6D8P5 0V2CN-GP

SC6D8P5 0V2CN-GP

12

EC3306

EC3306 SC6D8P5 0V2CN-GP

SC6D8P5 0V2CN-GP

12

EC3307

EC3307 SC6D8P5 0V2CN-GP

SC6D8P5 0V2CN-GP

12

EC3308

EC3308 SC6D8P5 0V2CN-GP

SC6D8P5 0V2CN-GP

SSID = 1394

B B

Remove 1394

A A

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CARD READER CONN

Size Document N umber Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

CARD READER CONN

A3

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

33 88Wedn esday, January 13, 2010

1

A00

5

S

D D

SID = ExpressCard

4

3

2

1.5V_CARD Max. 650mA, Average 500mA.

+ +3.3V_CARD Max. 1300mA, Average 1000mA +3.3V_CARDAUX Max. 275mA

1

SB-26

NEW1

27

USB12_N

NEWC ARD_OC#

19

21

OC#

GND

THERMAL_PAD

1.5VOUT111.5VIN12AUXOUT15AUXIN

17

12

C3405

C3405 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

1

18

STBY#

RCLKEN

SHDN#

PERST#

CPUSB#

CPPE#

SYSRST#

3.3VIN23.3VOUT

TPS2231 RGP-GP-U

3

+3.3V_RU N

+3.3V_CA RD

+1.5V_RU N

7

U3401

For 2nd Source 74.05538.073

C C

B B

+1.5V_RU N +1.5V_CA RD +3.3V_CA RD

+3.3V_RU N

Lay out close to Chip

12

C3401

C3401 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

16

NC#16

14

NC#14

13

NC#13

5

NC#5

4

NC#4

+3.3V_CA RDAUX

+3.3V_AL W

+1.5V_CA RD

+1.5V_CARD Max. 650mA, Average 500mA. +3.3V_CARD Max. 1300mA, Average 1000mA +3.3V_CARDAUX Max. 275mA

+1.5V_RU N+3.3V_ALW

12

C3402

C3402 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

TP3401TP 3401

PM_SLP_ S3# [22,37,42,50,5 1,86]

20

PERST#

8

CPUSB#

9

CPPE#

10

NRST

6

1ST: 74.02231 .073 2ND: 74.09716.073

12

C3406

C3406 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

RN3401

4

R3401 0R2J-2-GPR 3401 0R2J-2-G P

C3410 SC2 2P50V2JN-4GP

+3.3V_CA RDAUX+3.3V_CARD

1 23

DY

SRN100K J-6-GP

12

DY

12

C3409

C3409 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

+3.3V_AL W

PM_SLP_ S4# [22,37,50]

PLT_RST # [9,21 ,36,37,64,70,76,80]

PCH_SMB _CLK[23] PCH_SMB _DATA[23]

+1.5V_CA RD

PCIE_W AKE#[22,7 6]

+3.3V_CA RDAUX

+3.3V_CA RD

NEWC ARD_CLKREQ#[23]

CLK_PCIE_ NEW#[23] CLK_PCIE_ NEW[23]

PCIE_IRXN5_N TXN5[23]

PCIE_IRXP5_N TXP5[23]

PCIE_ITXN5_N RXN5[23]

PCIE_ITXP5_N RXP5[23]

SB-1021 pop and change L3401 to 120 ohm; DY R3402, R3403 for EMI

A00-0107-1

USB_PN1 2[21 ]

remove R3402, R3403 for no co-lay after XB

1

L3401

DLW2 1HN121SQ2L-1G P

L3401

2

3

4

1ST: 68.00201 .201 2ND:

USB12_N

PCIE_IRXN5_N TXN5 PCIE_IRXP5_N TXP5

PCIE_ITXN5_N RXN5 PCIE_ITXP5_N RXP5

USB12_P CPUSB#

PCH_SMB _CLK PCH_SMB _DATA

PCIE_W AKE#

PERST#

NEWC ARD_CLKREQ# CPPE# CLK_PCIE_ NEW# CLK_PCIE_ NEW

1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

28

PTW O-CON26-6-GP

1ST: 20.K0370.02 6 2ND: 20.K0315.026

+3.3V_RU N

12

C3403

C3403 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

A A

5

12

C3404

C3404 SC4D7U6 D3V5KX-3GP

SC4D7U6 D3V5KX-3GP

12

C3407

C3407 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

+1.5V_CA RD

12

C3408

C3408 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

4

3

USB_PP1 2[21]

0715 Add commom choke

2

USB12_P

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

ExpressCard

1

A00

34 88Wedn esday, January 13, 2010

A00

5

SID = User.Interface

S

D D

4

3

2

1

TPM board CONN

TPM1

+3.3V_RUN

LPC_LAD0[24,37,70] LPC_LAD1[24,37,70] LPC_LAD2[24,37,70] LPC_LAD3[24,37,70]

LPC_LFRAME#[24,37,70]

INT_SERIRQ[24,25,37]

PCLK_TPM[21]

PLT_RST#

SB-1022 Add R3601

R3601

1 2

0R2J-2-GP

DY

C C

PLT_RST#[9,21,34,37,64,70,76,80]

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PLT_RST#_TPM INT_SERIRQ PCLK_TPM

ACES-CON10-4-GP

TPM1

11

1

2 3 4 5

DY

6 7 8 9

10

12

SC-1125-1

B B

A A

5

4

remove TPM AFTP

3

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

TPM

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

36 88W ednesday, January 13, 2010

1

A00

D

CBBAA

KBC_PWR

12

R3716

C

DIS

2K2R2J-2-GP

12

R3729

UMA

2K2R2J-2-GP

Remove HDD_FALL_INT1

10KR2J-3-GP

PCB_VER0 PCB_VER1

10KR2J-3-GP

DW

07/07 Dummy

1.Dummy R3736

5

SID = KBC

S

+

3.3V_RTC_LDO

12

R

3747

0R0805-PAD-2-GP

K

BC_PWR

BC_PWR K

12

3702

3702 C

C

Pull High : Discrete internal Pull Low for UMA

+3.3V_RUN

12

R3701

12

R3708

DY

E51_TxD

R3736

DY

4K7R2J-2-GP

1 2

A

L

3701

BLM18AG601SN-3GP

1 2

1ST: 68.00084.881 2ND:

12

3712

DY

C

SCD1U10V2KX-4GP

SC2D2U6D3V3KX-GP

WD

07/23

1. Added R3712 100 Ohm dampin g resistor

2. Added R3713 100 Ohm dampin g resistor

3. Added R3751 100 Ohm dampin g resistor

SUS_PWR_DN_ACK[22] KB_BL_DET#[68]

SB-22

1D5V_VGA_ON[87]

PWRLED#[66]

PWR_BTN_LED#[66]

KB_BL_CTRL[68]

AD_OFF[43] RSMRST#_KBC[22] PM_SLP_S4#[22,34,50]

NUM_LOCK_LED#[66] 3V_5V_POK[22,46] PM_PWROK[22] EC_SPI_WP#_R[62]

BLON_OUT[54]

IMVP_VR_ON[47] PSID_DISABLE#[43]

GFX_CORE_EN[86] ME_UNLOCK#[24] USB_PWR_EN#[63,76]

10KR2J-3-GP

12

R

R 3732

3732

12

10KR2J-3-GP

R

R 3711

3711

DY

+

3.3V_RUN_GPU

R

3721

10KR2J-3-GP

T

00-0104-1

3711

3711 C

C

SCD1U10V2KX-4GP

DGPU_PWR_EN#[25]

12

HERMTRIP_VGA#[81]

P

ut 0.1uf close to VCC-GND pin pair.

12

C3706

SCD1U10V2KX-4GP

SC2D2U6D3V3KX-GP

AGND

AD_IA_KBC

1.8_GFX_ON

THERMTRIP_VGA_R#

TURBO_BOOST_ALERT# KBC_THERMTRIP#

KBC_PWRBTN_EC#

LID_CLOSE# PCB_VER0 SW_UMA_ID 1D5V_VGA_ON PCB_VER1 PWRLED# PWR_BTN_LED# KB_BL_CTRL AD_OFF RSMRST#_KBC PM_SLP_S4# NUM_LOCK_LED# 3V_5V_POK PM_PWROK_R EC_SPI_WP#_R EC_PWR_SHDN# BLON_OUT IMVP_VR_ON_R PSID_DISABLE# GFX_CORE_EN ME_UNLOCK# USB_PWR_EN#

12

C3715

SCD1U10V2KX-4GP

KB_BL_DET_R#

12

C3701

C3708

C3713

SCD1U10V2KX-4GP

AD_IA_KBC[45]

1.8_GFX_ON[51]

PS_ID_EC[43]

TURBO_BOOST_ALERT#[25]

SUS_PWR_DN_ACK

R3712 100R2J-2-GPR3712 100R2J- 2-GP

1 2

DGPU_PWR_EN# CAPA2_INT_R#

PM_SLP_S3#[22,34,42,50,51,86]

AC_IN_L# AC_IN_R#

R3751 100R2J-2-GPR3751 100R2J- 2-GP

1 2

LID_CLOSE#[69]

R3706

1 2

0R0402-PAD-2-GP

R3719

1 2

0R0402-PAD-2-GP

A00-0104-1

DW

07/10 assign GP IO

1.assign GPIO T UCHPANEL_STP#

MB VERSION ID

VER1

VER0

0

SA SB SC

-1

0

111

0 1 0

KBC CLK EMI

PCLK_KBC

R3726

DY

0R2J-2-GP

1 2

PCLK_KBC_RC

C3704

DY

SC4D7P50V2CN-1GP

1 2

V

104

97 98

99 100 108

96

101 105 106 107

64

95

93

94 119

109 120

65

66

16

17

20

21

22

23

24

25

26

27

28

73

74

75 110

+

3.3V_RUN_GPU

12

R

3748

2K2R2J-2-GP

3714_1

Q

3714

MMBT3904-7-F-GP

312

1ST: 84.03904.H11 2ND: 84.03904.L06

BAT

U3701A

VREF

GPI90/AD0 GPI91/AD1 GPI92/AD2 GPI93/AD3 GPIO05 GPIO04

GPI94 GPI95 GPI96 GPI97

GPIO01/TB2 GPIO03 GPIO06 GPIO07 GPIO23

6

GPIO24 GPIO30 GPIO31 GPIO32/D_PWM GPIO33/H_PWM GPIO40/F_PWM GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO45/E_PWM GPIO46/TRST# GPIO47 GPIO50/TDO GPIO51 GPIO52/RDY# GPIO53 GPIO70 GPIO71 GPIO72 GPO82/TRIS#

CAPA_INT#[78]

H_THRMTRIP#[9,25,42]

4

K

88

115

VCC

A/D

D/A

GPIO

116

1ST: 84.03904.H11 2ND: 84.03904.L06

BC_PWR

R

3722

10KR2J-3-GP

T

HERMTRIP_VGA_R#

1 2

D

W

7/10 Added

0

1.Added circuit , For prevent e lectric leakag e

80

4

102

VDD

VCC19VCC46VCC76VCC

AVCC

GPIO41

GPIO10/LPCPD#

LPC

GPIO11/CLKRUN#

ECSCI#/GPIO54

GPIO67/PWUREQ#

GPIO74/SDA2

SMB

GPIO22/SDA1

SP

GPIO66/G_PWM

SPI

GPIO76/SHBM

GPO83/SOUT_CR /BADDR1

GPIO87/SIN_CR

GPO84/BADDR0

SER/IR

GND5GND18GND45GND78GND89GND

AGND

NPCE781BA0DX-GP

103

AGND

12

R3730

R3730 0R0402-PAD-2-GP

0R0402-PAD-2-GP

+3.3V_RUN

12

R3738

R3738 2K2R2J-2-GP

2K2R2J-2-GP

Q3709_1

Q3709

MMBT3904-7-F-GP

+1.05V_VTT

12

THERMTRIP_GATE

Q3701

Q3701 CH3904PT-GP

CH3904PT-GP

312

R3737

R3737 2K2R2J-2-GP

2K2R2J-2-GP

CBE

SCD1U10V2KX-4GP

1 OF 2

LRESET#

LCLK

LFRAME#

LAD0 LAD1 LAD2 LAD3

SERIRQ

KBRST#

GA20

GPIO65/SMI#

GPIO73/SCL2

GPIO17/SCL1

GPIO77

GPIO75 GPIO81

GPIO16 GPIO34 GPIO36

VCORF

A00-0104-1

KBC_PWR

KBC_THERMTRIP#

1ST: 84.03904.P11 2ND: 84.03904.T11

+

3.3V_RUN

12

C3703

DY

1 2

CAP_LOCK_LED#

124

PLT_RST1#_1

7 2 3

LPC_LAD0

126

LPC_LAD1

127

LPC_LAD2

128

LPC_LAD3

1 125 8 122 121

ECSCI#_KBC

29

PANEL_BKEN

9

ECSWI#_KBC

123

KBC_SDA1

68

KBC_SCL1

67 69 70

BATT_WHITE_LED

81

ECSMI#_KBC

84 83 82 91

E51_TxD

111

E51_RxD

113 112

114

VTT_PWRGD_G34

14 15

KBC_VCORF

44

Pull High : Switch Board Pull Low : UnSwitch Board

R3727

R3727 4K7R2J-2-GP

4K7R2J-2-GP

1 2

CAPA2_INT_R#

C3716

12

SCD1U10V2KX-5GP

3

C3714

C3714 SC4D7U10V3KX-GP

SC4D7U10V3KX-GP

BAT_IN# [44]

CAP_LOCK_LED# [66]

PCLK_KBC [21]

LPC_LFRAME# [24,36,70]

LPC_LAD[0..3] [24,36,70]

INT_SERIRQ [24,25,36] PM_CLKRUN# [22] KBRCIN# [25] KA20GATE [25]

KBC_SDA1 [23] KBC_SCL1 [23] BAT_SDA [44,45] BAT_SCL [44,45]

BATT_WHITE_LED [66]

BLUETOOTH_EN [73] WIFI_RF_EN [64]

WIRELESS_ON#/OFF [64]

E51_TxD [64] E51_RxD [64] AC_PRESENT_EC [22]

PM_LAN_ENABLE [76]

1 2

S5_ENABLE [42]

R3723

R3723 0R0402-PAD-2-GP

0R0402-PAD-2-GP

12

C3710

C3710 SC1U10V3KX-3GP

SC1U10V3KX-3GP

C3710 need place near pin 44.

A00-0104-1

A

00-0104-1

R

3746

1 2

0R0402-PAD-2-GP

K

BC_PWRBTN#[78]

K

BC_PWR

R

3754

1 2

DY

10KR2J-3-GP

A

C_IN_L#

K

BC_PWR

G

EC_PWR_SHDN#

S D

DY

Q3706

Q3706 2N7002A-7-GP

2N7002A-7-GP

SB-1020

VTT_PWRGD [9,49,52]

KBC_PWR

R3733

R3733 2K2R2J-2-GP

2K2R2J-2-GP

DY

1 2

SW_UNSW_ID

R3756

R3756 2K2R2J-2-GP

2K2R2J-2-GP

1 2

SB-34

3.3V_RUN_GPU_EN[87]

1.05V_GFX_ON[87] SCR_LOCK_LED#[66] LCD_TST[54] TPDATA[68] TPCLK[68]

EC_SPI_DI[62]

SPI_DIO[62]

EC_SPI_CS#[62]

EC_SPI_CLK[62]

PURE_HW_SHUTDOW N#[39,42]

EC_SPI_DI

EC_SPI_CS# EC_SPI_CLK

A00-0105-1 Add reset IC U3704 to prevent SPI ROM data lost

BC_PWRBTN_EC#

K

BC_PWRBTN#

K

D

3704

BAT54C-U-GP

A

00-0104-1

R

3755

1 2

0R0402-PAD-2-GP

KBC_ON#

PLT_RST1#_1

PANEL_BKEN

DGPU_SELECT#[21,54,74]

1ST: 83.01621.01F 2ND:

PCH_SUSCLK_KBC[22]

SB-34

AMP_MUTE#[30]

IMVP_VR_PWRGD[47]

PM_PWRBTN#[22]

SHBM_LCDTST_EN[54]

KBC_BEEP[30] BATT_ORANGE_LED[66] LBKLT_CTL_EC[54]

R3707

R3707 0R0402-PAD-2-GP

0R0402-PAD-2-GP

A00-0104-1

R3753 0R2J-2-GPR3753 0R2J-2-G P

1 2

R3735 0R2J-2-GPR3735 0R2J-2-G P

1 2

U3704

1

GND

2

RESET#

G690L293T73UF-GP

2

S

C-1118-1

K

BC_PWR

change power ra il to KBC_PWR

3.3V_RTC_LDO

+

G

DY

D S

K

AC_IN# [45]

SI2301CDS-T1-GE3-GP

SI2301CDS-T1-GE3-GP Q

Q

3704

BC_PWR

12

DY

12

3

DY

3705

D

D BAT54C-U-GP

BAT54C-U-GP

3

3745

R

12

DY

100KR2J-1-GP

+

3.3V_RTC_LDO

DY

1 2

R

3744

10KR2J-3-GP

K

BC_ON#

SB-22

R3720

1 2

0R0402-PAD-2-GP

12

C3717

DY

SC470P50V2KX-3GP

SC-1125-2 add U3703 mux f or panel backl ight enable si gnal select

+3.3V_RUN

12

DY

ECSWI#_KBC

ECSCI#_KBC

ECSMI#_KBC

R3741

R3741 10R2J-2-GP

10R2J-2-GP

1 2

3.3V_RUN_GPU_EN

1.05V_GFX_ON SCR_LOCK_LED# LCD_TST_R TPDATA TPCLK

3

VCC

A00-0104-1

PLT_RST# [9,21,34,36,64,70,76,80]

D3712

2

3

DY

1

BAT54C-7-F-GP

U3703

4

B03A

GND

VCC

B1

S

D3702

BAS16XV2T1G-GP-U

D3703

BAS16XV2T1G-GP-U

D3701

BAS16XV2T1G-GP-U

KBC_XI

SW_UNSW_ID AMP_MUTE#

SHBM_LCDTST_EN

EC_SPI_DO

EC_SPI_CLK_C

1 2

R3724

R3724 10KR2J-3-GP

10KR2J-3-GP

1ST: 84.03906.H11 2ND: 84.03906.R11

2 1

AK

117

118

ECRST#_C

Q3702

Q3702 CH3906PT-GP

CH3906PT-GP

5 6

NC7SB3157P6X-1GP

KBC_PWR

1 2

R3702

R3702 0R2J-2-GP

0R2J-2-GP

PANEL_BKEN_GPU [81]

PANEL_BKEN_PCH [20]

1ST: 73.03157.C0H 2ND: 73.03157.E0J

U3701B

77

32KX1/32KCLKIN

79

32KX2

30

GPIO55/CLKOUT

63

GPIO14/TB1 GPIO20/TA2

31

GPIO56/TA1

32

GPIO15/A_PWM GPIO21/B_PWM

62

GPIO13/C_PWM

13

GPIO12/PSDAT3

12

GPIO25/PSCLK3

11

GPIO27/PSDAT2

10

GPIO26/PSCLK2

71

GPIO35/PSDAT1

72

GPIO37/PSCLK1

86

F_SDI

87

F_SDO

90

F_CS0#

92

F_SCK

ECRST#

B

PANEL_BKEN_GPU [81]

PANEL_BKEN_PCH [20]

ECSWI# [25]

ECSCI# [25]

ECSMI# [25]

PS/2

FIU

12

E

C3707

DY

SC1U10V3KX-3GP

C

KBC

KBSOUT15/GPIO61/XOR_OU T

HERM_SDA[39,78]

T

2 OF 2

KBSOUT0/JENK#

KBSOUT1/TCK

KBSOUT2/TMS

KBSOUT3/TDI

KBSOUT4/JEN0#

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT7 KBSOUT8

KBSOUT9 KBSOUT10 KBSOUT11

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

VCC_POR#

NPCE781BA0DX-GP

3702

U

34

2

5

1

6

DMN66D0LDW-7-GP

1 2

DY

RN3702

4

SRN4K7J-8-GP

RN3701

4

SRN4K7J-8-GP

1 2

DY

1 2

DY

1 2

TP3701TP3701

1

+

3.3V_RUN

K

BC_SDA1

THERM_SCL [39,78]

+3.3V_RUN

DW

07/07 Change

1.Change Power rail

+3.3V_ALW

23 1

KBC_PWR

23 1

+3.3V_RTC_LDO

KCOL[0..16] [68]

KROW[0..7] [68]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsic hih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsic hih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

+3.3V_RUN

37 88Wednesday, January 13, 2010

12

DY

EC3701

SCD1U16V2KX-3GP

SB-1020

KBC_SCL1

E51_RxD

R3725 10KR2J-3-GP

KBC_SCL1 KBC_SDA1

BAT_SDA BAT_SCL

KBC_THERMTRIP#

R3709 100KR2J-1-GPR3709 100KR2J-1-GP

KBC_PWRBTN#

R3734 100KR2J-1-GPR3734 100KR2J-1-GP

TURBO_BOOST_ALERT#

1st Samsung

Title

Size Document Number Rev

Date: Sheet of

R3752 10KR2J-3-GPR3752 10KR2J-3-GP

WIRELESS_ON#/OFF

R3740 100KR2J-1-GPR3740 100KR2J-1-GP

KB_BL_DET#

R3750 10KR2J-3-GPR3750 10KR2J-3-GP

KA20GATE

R3743 10KR2J-3-GPR3743 10KR2J-3-GP

KBRCIN#

R3742 10KR2J-3-GPR3742 10KR2J-3-GP

S5_ENABLE

R3728 10KR2J-3-GPR3728 10KR2J-3-GP

KCOL0

R3714 10KR2J-3-GP

SHBM_LCDTST_EN

R3717 10KR2J-3-GP

BLUETOOTH_EN

R3731 10KR2J-3-GPR3731 10KR2J-3-GP

PANEL_BKEN

R3739 100KR2J-1-GPR3739 100KR2J-1-GP

KCOL0

53

KCOL1

52

KCOL2

51

KCOL3

50

KCOL4

49

KCOL5

48

KCOL6

47

KCOL7

43

KCOL8

42

KCOL9

41

KCOL10

40

KCOL11

39

KCOL12

38

KCOL13

37

KCOL14

36

KCOL15

35

KCOL16

34

TP_KCOL17

33

KROW0

54

KROW1

55

KROW2

56

KROW3

57

KROW4

58

KROW5

59

KROW6

60

KROW7

61

ECRST#

85

KBC Nuvoton NPCE781BA0DX

Custom

Winery13 MB DIS

A00

5

5V_RUN

S

SID = Thermal

D D

1. WWAN

1ST: 84.03904.P11 2ND: 84.03904.T11

Q3905 must be near WWAN

+

12

C

C SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

DW

07/10 Del

1. Not reserve S5 power source rail for EMC2102 ??

+3.3V_RUN

C3912 must be near Q3905

CH3904PT-GP

C C

E

Q3905

C

Layout notice: H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

12

C3912

C3912 SC470P50V2JN-GP

B

SC470P50V2JN-GP

DY

C3914

C3914 SC470P50V2JN-GP

SC470P50V2JN-GP

1 2

C3914 must be near EMC2102

2. GPU Sensor

VGA_THERMDC[81]

VGA_THERMDA[81]

DW

07/23 Removed

1.Removed SYSTEM Sensor Critical

3. CPU Sensor

Layout notice :

B B

Both VGA_THERMDA and THERMDC routing 10 mil trace width and 10 mil spacing.

C3901 must be near Q3901

Q3901

E

B

C

C3901

DY

SC470P50V2JN-GP

1 2

CH3904PT-GP

1ST: 84.03904.P11 2ND: 84.03904.T11

12

C3906

C3906 SC470P50V2JN-GP

SC470P50V2JN-GP

C3906 must be near EMC2102

C3903

C3903 SC470P50V2JN-GP

SC470P50V2JN-GP

1 2

C3903 must be near EMC2102

3.HW T8 sensor ( CPU )

Layout notice : Both DN3 and DP3 routing 10 mil trace width and 10 mil spacing.

3910

4

2

5mil

12

C

3909

SCD1U10V2KX-5GP

EMC2102_VDD_3D3EMC2102_VDD_3D3

12

R3908

R3908 49D9R2F-GP

49D9R2F-GP

C3905

C3905 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2

EMC2102_DN1

EMC2102_DP1

VGA_THERMDC

VGA_THERMDA

T8_THERMDC

T8_THERMDA

GND = Channel 1 OPEN = Channel 3 +3.3V = Disabled

+3.3V_RUN

GND = Fan is OFF OPEN = Fan is at 60% full-scale +3.3V = Fan is at 75% full-scale

R3903

DY

10KR2J-3-GP

R3916

DY

0R2J-2-GP

R3914

1 2

10KR2J-3-GP

U3901

1

2

3

4

5

6

7

12

3.3V_RUN

+

29

GND

VDD_3V

DN1

DP1

DN2

DP2

DN3

DP3

EMC2102_SHDN

EMC2102_FAN_mode

12

R

3907

10KR2J-3-GP

26

27

28

TACH

VDD_5Va

EMC2102

SHDN_SEL9FAN_MODE10TRIP_SET11SYS_SHDN#12THERMTRIP#13POWER_OK#

NC#8

8

3

S

B-1023

E

MC2102_FAN_TACH_1

E

MC2102_FAN_DRIVE

22

23

24

FANb25FANa

SMCLK

SMDATA

VDD_5Vb

14

+3.3V_RUN

SYS_SHDN#

S D

RN3901

23 1

4

SRN4K7J-8-GP

THERM_SCL [37,78] THERM_SDA [37,78]

21

NC#21

20

GND

19

ALERT#

18

CLK_IN

17

CLK_SEL

16

RESET#

15

NC#15

EMC2102-DZK-GP

EMC2102_PWROK EMC2102_THERMTRIP#

12

R3910

R3910 10KR2J-3-GP

10KR2J-3-GP

SHDN#_G

G

Q3903

Q3903 2N7002A-7-GP

2N7002A-7-GP

1ST: 84.2N702.E31 2ND: 84.2N702.D31

+3.3V_RUN

TP_ALERT#

CLK_32K

EMC2102_CLK_SEL

TP_EM2102_RESET#

1ST: 74.02102.A73 2ND: 74.07922.0B3

RN3902

4

SRN10KJ-5-GP

KBC_PWR

12

R3917

R3917 10KR2J-3-GP

10KR2J-3-GP

25mil

TP3903 TPAD14-GPTP3903 TPAD14-GP

1

R3906

1 2

10KR2J-3-GP

1

TP3904 TPAD14-GPTP3904 TPAD14-GP

23 1

PURE_HW_SHUTDOWN# [37,42]

V_DEGREE

2

MC2102_FAN_TACH_1 [58]

E

MC2102_FAN_DRIVE [58]

E

+3.3V_RUN

1

GND = Internal Oscillator Selected +3.3V = External 32.768kHz Clock Selected

+3.3V_RUN

12

C3902

SCD1U10V2KX-5GP

C3904

SCD1U10V2KX-5GP

R3902

R3902 10KR2F-2-GP

10KR2F-2-GP

TRIP_SET Pin Voltage V_DEGREE=(((Degree-75)/21) T8 shutdown is set 86 deg-C.

12

R3904

R3904 2K37R2F-GP

2K37R2F-GP

SC-1204-1

32K suspend clock output

A A

PCH_SUSCLK_2102[22]

5

1ST: 84.2N702.E31 2ND: 84.2N702.D31

Q3902

Q3902 2N7002A-7-GP

2N7002A-7-GP

SD

G

RUN_POWER_ON [42,52]

4

R3913

1 2

10R2J-2-GP

CLK_32KCLK_32KCLK_32K_R

12

C3911

DY

SC4D7P50V2CN-1GP

1st Samsung

Title

Size Document Number Rev

Date: Sheet of

3

2

Date: Sheet of

DW

07/28 Removed

1. Removed U3902 AND gate.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Thermal/Fan Controllor EMC2102

Custom

Winery13 MB DIS

1

39 88W ednesday, January 13, 2010

A00

5

SID = User.Interface

S

D D

4

3

2

1

Free Fall Sensor

Note

- no via, trace, under the sensor (keep out area around 2mm)

- stay away from the screw hole or metal shield soldering joints

+3.3V_RUN

12

C4002

C4001

C4001 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C C

+3.3V_RUN

09/0422 (#1) Just pull +3.3V_RUN ~ Ref. Rothschild

B B

(#2) FAE/ DY is ok, chip internal pull-up resistors (#3) From spec, Slave ADdress(SAD) is 001110xb Pull HIGH SAD is 0011101b Pull GND SAD is 0011100b

PCH_SMBCLK[7,18,19,23,64,76]

PCH_SMBDATA[7,18,19,23,64,76]

1 2

R4001 0R2J-2-GP

DY

HDD_FALL_SDO

C4002 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

U4001

14

SCL/SPC

13

SDA/SDI/SDO

12

SDO

7

CS

3

RESERVE D#3

11

RESERVE D#11

DE351DLTR8-GP

+3.3V_RUN

1

6

VDD

VDD_IO

INT1

INT2

GND GND GND GND

12

DY

8

9

2 4 5 10

- design PCB pad based on our sensor LGA pad size (add 0.1mm)

- solder stencil opening to 90% of the PCB pad size

- mount the sensor near the center of mass of the NB as possible as you can

SA

R4004

R4004 100KR2J-1-GP

100KR2J-1-GP

HDD_FALL_INT1

FFS_INT2_R

06/25 Check

1.HDD_FALL_INT1 [ GPIO Table ]??

HDD_FALL_INT1 [21]

1ST: 84.2N702.E31

G

2ND: 84.2N702.D31

S D

Q4001

Q4001 2N7002A-7-GP

2N7002A-7-GP

FFS_INT2_L

FFS_INT2_R [25]

D4001

K A

SDM20U30-7-GP

1ST: 83.R2003.08M 2ND:

+5V_RUN+3.3V_RUN

12

R4008

R4008 100KR2J-1-GP

100KR2J-1-GP

FFS_INT2 [59]

SB-1023

A A

Note (1) Keep all signals are the same trace width. (included VDD, GND). (2) No VIA under IC bottom.

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

Free Fall Sensor

40 88W ednesday, January 13, 2010

1

A00

5

S

SID = Reset.Suspend

D D

R

4214

1 2

DY

1ST: 83.01621.01F 2ND:

12

R4209

DY

200KR2J-L1-GP

DY

1KR2J-1-GP

H_PWRGOOD[9,25]

3V_5V_EN[46]

C C

B B

H_PWRGD_R

12

C4208

C4208 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

D4201

A K

BAS16XV2T1G-GP-U

1 2

R4203 1KR2J-1-GPR4203 1KR2J-1-GP

PS_S3CNTRL[52]

PM_SLP_S3#[22,34,37,50,51,86]

DMN66D0LDW-7-GP

E

B

DY

C

PS_S3CNTRL

4

_THRMTRIP# [9,25,37]

H

Q4201

Q4201 CHT2222APT-GP

CHT2222APT-GP

PURE_HW_SHUTDOWN# [37,39]

S5_ENABLE [37]

+3.3V_RTC_LDO

12

R4201

R4201 100KR2J-1-GP

100KR2J-1-GP

1

2

34

Q4202

5

6

+15V_ALW

1 2

R4206

R4206 100KR2J-1-GP

100KR2J-1-GP

3

R

emove +3.3V_DELAY power rail 2009/05/25

+5V_RUN

R4205

RUN_POWER_ON RUN_ON_5V

RUN_POWER_ON [39,52]

R4205

1 2

SC6800P25V2KX-1GP

R4211

1 2

SCD01U25V2KX-3GP

10KR2J-3-GP

C4204

10KR2J-3-GP

C4203

12

+3.3V_RUN

RUN_ON_3D3V

12

2

Peak current:5.3A Design current: 3.7A

+5V_ALW

U4201

S

D

S

1 2 3 4 5

D

S

S S

S G D

G D

AO4468-GP

11.6A Rds=14m ohm

8

D

7

D

6

1ST: 84.04468.037 2ND: 84.08884.037

Peak current: 8191mA Design current: 5734.6mA

D

8

D

7

D

6

+3.3V_ALW

1ST: 84.04468.037 2ND: 84.08884.037

U4202

S

1

S

2

S

3

G D

4 5

AO4468-GP

11.6A Rds=14m ohm

1

SB-1023

Peak current: 1650mA

+1.5V_RUN

R4213

A A

5

4

3

R4213

1 2

SCD01U25V2KX-3GP

14K7R2F-L-GP

C4206

RUN_ON_1D5VR

12

Design current: 1155mA

U4204

S

1

S

2

S

3

G D

4 5

AO4468-GP

11.6A Rds=14m ohm

1ST: 84.04468.037 2ND: 84.08884.037

2

+1.5V_SUS

D

8

D

7

D

6

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Plane Enable

Size Document Number Rev

Custom

Date: Sheet of

Power Plane Enable

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

42 88W ednesday, January 13, 2010

1

A00

5

S

SID = DCIN

P

R4306

15KR2J-1-GP

D D

PS_ID_R2[76]

PS_ID_R2

1 2

P

SID_PRO

P

R4309

100KR2J-1-GP

1 2

D

4

E

B

C

G

PR4310

1 2

DY

33R2J-2-GP

P

Q4304

CH3904PT-GP

PQ4303

PQ4303 FDV301N-NL-GP

FDV301N-NL-GP

SD

+

5V_ALW

12

P

R4303

10KR2J-3-GP

P

SID_DISABLE#_R

PS_ID

2

D

Y

3

1

P

D4302

BAV99-4-GP

PR4302

1 2

33R2J-2-GP

R4301

P

1 2

Y

D

0R2J-2-GP

3

P

SID_DISABLE# [37]

3.3V_ALW

+

2

1

PD4301

PD4301 BAV99-4-GP

BAV99-4-GP

3

3.3V_ALW

+

12

PR4304

PR4304 2K2R2J-2-GP

2K2R2J-2-GP

2

1

PS_ID_EC [37]

SC-1130-1 pop PC4303 for RF

12

PC4303

OUT

3

GND

2

PC4303 SC1P50V2CN-1GP

SC1P50V2CN-1GP

AD_OFF_L

PQ4302

R2

DY

B

R1

PDTA124EU-1-GP

12

PC4302

PC4302 SC1U25V5KX-1GP

SC1U25V5KX-1GP

E

AD_OFF_R

C

C C

B B

This cap should be used only as last resort for EMI suppression.

PQ4301

DY

R1

AD_OFF[37]

1

IN

R2

DDTC124EUA-7F-GP

+DC_IN +DC_IN_SS

12

PR4308

PR4308 240KR3-GP

240KR3-GP

PR4307

PR4307 47KR3J-L-GP

47KR3J-L-GP

1 2

PU4301

S

D

S S

S G D

G D

AO4407A-GP

D

8

D

7

D

6

1 2 3 4 5

Id=-12A Qg=-25nC Rdson=10~38mohm

12

PC4304

PC4304 SCD01U25V2KX-3GP

SCD01U25V2KX-3GP

12

PC4305

PC4305 SCD01U25V2KX-3GP

SCD01U25V2KX-3GP

12

PC4306

PC4306 SCD01U25V2KX-3GP

SCD01U25V2KX-3GP

12

PC4301

PC4301 SC10U25V6KX-1GP

SC10U25V6KX-1GP

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

DCIN

43 88W ednesday, January 13, 2010

1

A00

5

S

SID = BATT

D D

BATT1

11

GND

10

GND

9

GND2

8

GND1

DAT_SMB CLK_SMB

BATT2+ BATT1+

1 1 1 1

7 6 5 4 3 2 1

AFTP440 1AFTP4401 AFTP440 2AFTP4402 AFTP440 4AFTP4404 AFTP440 5AFTP4405

BAT_ALERT

SYS_PRES#

BATT_PRS#

FOX-CON9 -5-GP

1ST: 20.80962 .009

C C

2ND: 20.81283.009

PBAT_PR ES1# PBAT_SM BDAT1 PBAT_SM BCLK1 +PBATT

B

PBAT_AL ARM#

PBAT_PR ES1# PBAT_SM BDAT1 PBAT_SM BCLK1

12

4

att Connecter

1

AFTP440 6AFTP4406

1

AFTP440 3AFTP4403

PR4402 100R2J -2-GPPR4402 100R2J -2-GP

1 2

PC4402

PC4402 SCD1U50 V3KX-GP

SCD1U50 V3KX-GP

12

PC4401

PC4401 SC2200P 50V2KX-2GP

SC2200P 50V2KX-2GP

BAT_IN# BAT_S DA BAT_SCL

4

PRN4401

PRN4401 SRN100J -3-GP

SRN100J -3-GP

PR4401

470KR2J -2-GP

1 23

12

PG4401

PG4401 GAP-CLOS E-PWR-3-GP

GAP-CLOS E-PWR-3-GP

3

12

+PBATT

KBC_PW R

BAT_IN# [37] BAT_SDA [37,45] BAT_SCL [37,45]

BATT_SE NSE [45]

2

1

3

PD4401

PD4401 BAV99-4-G P

BAV99-4-G P

1

2

B B

A A

5

4

3

PD4403

PD4403 BAV99-4-G P

BAV99-4-G P

1

2

3

PD4402

PD4402 BAV99-4-G P

BAV99-4-G P

1

2

+3.3V_RT C_LDO

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

3

2

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

Batt Connecter

44 88Wedn esday, January 13, 2010

1

A00

5

SID = Charger

S

P

U4501

S

D

S

D

+

DC_IN_SS

D D

DC_IN_SS

+

12

R4520

316KR3F-2-GP

P

BQ24745_LDO

C C

B B

12

R4502 48K7R3F-1-GPPR4502 48K7R3F-1-GP P

2009/08/04

CHG_AGND

AD_IA_KBC[37]

0R0402-PAD-2-GP

This Resistor must be 1% tolerance.

C4548

C4548 P

P

ACAV_IN

SCD01U50V2KX-1GP

PR4530

1 2

R4506

12

P

8K45R2F-2-GP

DY

R4528

R4528 P

P

R4504

R4504 P

P

C4516

C4516 P

P

12

SC220P50V2JN-3GP

SCD1U50V3KX-GP

BQ24745_REF

12

DY

10KR2F-2-GP

12

DY

15K8R3F-GP

12

4K7R2J-2-GP

PR4539

1 2

PC4518

PC4518 SC150P50V2JN-3GP

SC150P50V2JN-3GP

BQ24745_FBO1

12

DY

PC4515

A00-0104-1

PR4522

12

0R0402-PAD-2-GP

+3.3V_RTC_LDO

12

PR4511

10KR2F-2-GP

CHG_AGND

BAT_SCL[37,44]

BAT_SDA[37,44]

PC4540

SC2200P50V2KX-2GP

12

DY

PC4537

SCD01U50V2KX-1GP

+3.3V_RTC_LDO

12

PR4537

PR4537 200KR2F-L-GP

200KR2F-L-GP

1 2

12

PC4525

SC56P50V2JN-2GP

8

D

7

D

6

AO4407A-GP

Id=-12A Qg=-25nC Rdson=10~38mohm

PR4527

1 2

10KR2J-3-GP

PQ4502_03

PQ4502

BQ24745_ACOK

PC4513

SCD1U10V2KX-4GP

PR4526_01

1 2

SCD01U50V2KX-1GP

12

PR4523

PR4523 100KR2J-1-GP

100KR2J-1-GP

3 4

2

1

DMN66D0LDW-7-GP

PC4521

SCD1U50V3KX-GP

PR4515

0R0402-PAD-2-GP

1 2

PG4505 GAP-CLOSE-PWR-3-GPPG4505 GAP-CLOSE-PWR-3-GP

PG4508 GAP-CLOSE-PWR-3-GPPG4508 GAP-CLOSE-PWR-3-GP

PR4526

7K5R2F-1-GP

12

DY

PC4529

S

S S

S GD

GD

12

0R0402-PAD-2-GP

12

PC4534

PC4534 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1 2 3 45

5

6

BQ24745_DCIN

BQ24745_ACIN

BQ24745_ACOK

BAT_SCL_1

BAT_SDA_1

CHG_AGND

BQ24745_VICM BQ24745_FBO

BQ24745_EAI BQ24745_EAO BQ24745_REF

1 2

PR4510

4

R4513_03

P

1 2

PQ4502_05

BQ24745_CE

12

DY

PR4513

10KR2F-2-GP

PC4526

SCD1U10V2KX-4GP

CHG_AGND

12

PR4512

100KR2J-1-GP

CHG_AGND

22

DCIN

2

ACIN

11

VDDSMB

13

ACOK

10

SCL

9

SDA

14

NC#14

8

VICM

6

FBO

5

EAI

4

EAO

3

VREF

7

CE

12

GND

PU4504

BQ24745RHDR-GP

PC4519

PC4519 SCD1U50V3KX-GP

SCD1U50V3KX-GP

1

ICREF

GND

29

0R0402-PAD-2-GP

1 2

CSSP

CSSN

ICOUT

BOOT VDDP

UGATE

PHASE

LGATE

PGND

CSOP

CSON

NC#16

VFB

PR4509

1 2

SDC_IN

+

1 2

P

R4508

D01R2512F-4-GP

12

P

G4509

GAP-CLOSE-PWR-3-GP

PR4533_02

12

PR4533

0R0402-PAD-2-GP

BQ24745_CSSP

28

SCD1U50V3KX-GP

BQ24745_CSSN

27

BQ24745_ICOUT

26

BQ24745_BOOT_1

25

BQ24745_LDO

21

BQ24745_CHARGER_UGATE

24

23

20

19

18

17

16

15

BQ24745_PHASE_GND BQ24745_LGATE_1

BQ24745_CSOP_1

BAT_SENSE

DY

CHG_AGND

3

DY

12

PR4538

PR4538 0R2J-2-GP

0R2J-2-GP

PC4520

1 2

PR4534

0R0603-PAD-2-GP

1 2

PR4536

0R0603-PAD-2-GP

1 2

PR4531

PR4531 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

12

PC4544

SCD1U25V2ZY-1GP

PWR_SRC

+

12

P

G4501

GAP-CLOSE-PWR-3-GP

PR4524_03

12

PR4524

0R0402-PAD-2-GP

PC4545

1 2

DY

SCD1U50V3KX-GP

CHG_AGND

BQ24745_BST1

1 2

PC4536

PC4536 SC220P50V2JN-3GP

SC220P50V2JN-3GP

12

DY

PR4521

CHG_AGND

K A

SD103AWS-1-GP

PC4522

PC4522 SCD1U50V3KX-GP

SCD1U50V3KX-GP

BATT_SENSE [44]

PD4501

1 2

DY

PC4514

SCD1U50V3KX-GP

CHG_AGND

1K8R6J-GP

PR4503

DY

33R3J-2-GP

1 2

PC4541

12

DY

CHG_AGND

1 2

PC4531

PC4531 SCD1U50V3KX-GP

SCD1U50V3KX-GP

DY

SCD1U50V3KX-GP

1 2

PG4510

PG4503

GAP-CLOSE-PWR-3-GP

PC4528

SC1U6D3V2KX-GP

G D

4 5

12

PC4517

PC4517 SC3300P50V3KX-1GP

SC3300P50V3KX-1GP

G D

4 5

1 2

PR4532

PR4532 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

PG4506

GAP-CLOSE-PWR-3-GP

678

DDD

SSS

123

BQ24745_LX1

678

DDD

SSS

123

2

1 2

PG4512

GAP-CLOSE-PWR-3-GP

CHAGER_SRC

12

PU4503

SI4800BDY-T1-GP

2009/06/24

PU4505

SI4800BDY-T1-GP

BQ24745_CSON

12

PC4532

SC10U25V6KX-1GP

PL4501

1 2

L-5D6UH-GP

BQ24745_CSOP

1 2

DC_IN_SS

+

12

P

R4514

470KR2J-2-GP

12

PC4546

PC4512

SCD1U50V3KX-GP

SC10U25V6KX-1GP

SB-1103

1. change PL4501 to 68.5R610.201

+VCHGR1

1 2

D01R2512F-3-GP

1 2

PG4502

GAP-CLOSE-PWR-3-GP

3 4 5

I Qg=-25nC Rdson=10~38mohm

12

EC4502

DY

SC2200P50V2KX-2GP

Charger Current=1.4~3.6A

PR4519

1 2

PG4507

GAP-CLOSE-PWR-3-GP

BQ24745_PR4505

12

DY

1 2

CHG_AGND

P

U4502

AO4407A-GP

S

S S

S G

G

d=-12A

12

EC4501

DY

SCD1U25V2ZY-1GP

12

PC4511

SC10U25V6KX-1GP

PR4505

0R0402-PAD-2-GP

PC4543

SCD1U50V3KX-GP

1

+

PBATT

D

8

D

7

D

6

D

+PBATT

12

PC4533

PC4530

PC4524

SC10U25V6KX-1GP

SB-1103

KA

12

PC4523

DY

PD4502

1SMA18AT3G-GP

SC10U25V6KX-1GP

1SMA18AT3G-GP

SCD1U50V3KX-GP

AC_IN#[37]

A A

5

12

PC4527

2009/6/9

PQ4504

PQ4504 2N7002A-7-GP

2N7002A-7-GP

ACAV_IN

SCD1U25V3KX-GP

G

S D

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

CHARGER BQ24745

45 88W ednesday, January 13, 2010

1

A00

A

S

SID = PWR.Plane.Regulator_3V/5V

4 4

+3D3V_PWR

+3.3V_ALW

PG4602

12

GAP-CLOSE-PWR

PG4604

12

GAP-CLOSE-PWR

PG4606

12

GAP-CLOSE-PWR

PG4608

12

GAP-CLOSE-PWR

PG4611

12

DIS(Auburndale)

GAP-CLOSE-PWR

PG4613

GAP-CLOSE-PWR

PG4627

3 3

GAP-CLOSE-PWR

PG4626

GAP-CLOSE-PWR

PG4630

GAP-CLOSE-PWR

PG4634

GAP-CLOSE-PWR

2009/08/04

2 2

Design Current =8.08A

12.69A<OCP<15A

12

2009/08/24

+3D3V_PWR +5V_PWR

SB-1103 SB-1103

PC4619

DY

PC4619

12

S

S CD1U10V2KX-4GP

CD1U10V2KX-4GP

DY

PTC4603

12

S

S T100U6D3VBM-5GP

T100U6D3VBM-5GP

PTC4601

12

ST220U6D3VDM-15GP

PR4609

6K65R2F-GP

PR4613

10KR2F-2-GP

Close to VFB Pin (pin5)

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 3.3UH PCMB104T-3R3MS Cyntec 11.8mohm Isat =16Arms 68.3R310.20C O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 H/S: SiS412DN 24mohm/30mOhm@4.5Vgs/ 84.00412.037 L/S: Si7716ADN 13.5mOhm/16.5mOhm@4.5Vgs/ 84.06690.E37

1 1

A

+

PWR_SRC

+PWR_SRC_3D3V

PC4610

PC4627

SCD01U50V2KX-1GP

12

SC10U25V6KX-1GP

DY

2009/08/04

PL4601

1 2

IND-3D3UH-115-GP

PG4618

PR4606

2D2R5F-2-GP

GAP-CLOSE-PWR-3-GP

12

PC4620

SC330P50V3KX-GP

12

PR4610

PR4610 0R2J-2-GP

0R2J-2-GP

DY

51125_FB2_R

12

PC4624

PC4624 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

DY

12

A00-1218-1 pop PR4619; dummy PR4618 by power to improve +15V_Pump Power on issue

P

1 2

GAP-CLOSE-PWR

PG4605

1 2

GAP-CLOSE-PWR

PG4607

1 2

GAP-CLOSE-PWR

PG4609

1 2

GAP-CLOSE-PWR

PG4635

1 2

GAP-CLOSE-PWR

2009/08/04

PC4611

12

SC10U25V6KX-1GP

12

DY

51125_LL2_R

12

DY

+

PWR_SRC_3D3V

G4603

D

678

DDD

SSS

123

S G

D

678

DDD

SSS

123

S

2009/10/21 X01

51125_VREF

+3.3V_ALW_2

51125_VREF

+3.3V_ALW_2

PU4601

PU4601 SIS412DN-T1-GE3-GP

SIS412DN-T1-GE3-GP

PC4617

G D

SCD1U25V3KX-GP

4 5

PU4604

SI7716ADN-T1-GE3-GP

G D

4 5

G

TPS51125:DY RT8205B :ASM

12

B

+

3.3V_ALW_2

5

1125_ENTRIP

Q4601

P

2N7002A-7-GP

3

V_5V_EN[42]

2N7002A-7-GP

G

PR4622 DY

TPS51125

P

C4605

SC18P50V2JN-1-GP

S D

RT8205B

ASM

12

Y

D

1125_ENTIP1

5

12

P

R4602

180KR2F-GP

2009/08/18

DMN66D0LDW-7-GP

PQ4602

6

123 4

2009/10/21 X01

PR4622

51125_EN

1 2

820KR2F-GP

2009/10/21 X01 2009/10/21 X01

TPS51125:0R3J/63.00000.00L RT8205B :4R7/64.4R705.55L

51125_VBST2_1

51125_VREF

SCD22U10V2KX-1GP

PR4616

0R0402-PAD-2-GP

1 2

PR4617

12

DY

0R2J-2-GP

DY

PR4619

0R0402-PAD-2-GP

1 2

DY

TONSEL

GND

VREF

VREG3

VREG5

820KR2F-GP

PR4604

4D7R3F-L-GP

51125_VBST2

1 2

51125_DRVH2

51125_LL2

51125_DRVL2

51125_VO2

51125_FB2

51125_EN

1 2

DY

PR4608 820KR2F-GP

51125_ENTIP2

PC4622

12

51125_TONSEL

51125_SKIPSEL

+3.3V_ALW_2

GAP-CLOSE-PWR-3-GP

2009/10/21 X01

PR4618

12

0R2J-2-GP

TPS51125:ASM RT8205B :DY

PR4621

12

0R2J-2-GP

200kHz

245kHz

300kHz

365kHz

B

+PWR_SRC

PC4613

PC4612

SCD01U50V2KX-1GP

SC10U25V6KX-1GP

12

DY

16

PU4603

VIN

9

BOOT2

10

11

7

5

13

6

3

4

14

PG4623

1 2

CH2CH1 VREF(2V)

265kHz

305kHz

375kHz

460kHz

BOOT1

UGATE2

UGATE1

PHASE2

PHASE1

LGATE212LGATE1

VOUT2

VOUT1

FB2

EN

ENTRIP2

REF

TONSEL

SKIPSEL

FB1

PGOOD

ENTRIP1

PGND

GND

LG1_CP

VREG38VREG5

17

PC4625

3D3V_AUX_S5_5_51125

12

PC4626

SC4D7U10V5KX-4GP

SC10U10V5KX-2GP

SKIPSEL GNDVREG3 or VREG5

Operating Mode

TPS51125:0R3J/63.00000.00L RT8205B :4R7/64.4R705.55L

PR4605

4D7R3F-L-GP

51125_VBST1

51125_DRVH1

51125_LL1

51125_DRVL1

51125_VO1

51125_FB1

3V_5V_POK

51125_ENTIP1

51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK

SC22U6D3V5MX-2GP

PC4628

1 2

+3.3V_ALW_2

1 2

22

21

20

19

24

2

23

1

15

25

18

RT8205BGQW-GP

+5V_ALW2

12

OOA Auto Skip Auto Skip

OpenEN0 820kΩ to GND

enable both LDOs, VCLK on and ready to turn on switcher channels

enable both LDOs, VCLK off and ready to turn on switcher channels

PR4620

0R0402-PAD-2-GP

12

P

R4601

100KR2J-1-GP

5

51125_ENTIP2

PC4608

SC18P50V2JN-1-GP

51125_VBST1_1

+3.3V_RTC_LDO

C

12

DY

+3.3V_RTC_LDO

12

PWM only

C

12

PR4603

PR4603 180KR2F-GP

180KR2F-GP

2009/08/18

SIS412DN-T1-GE3-GP

SCD1U25V3KX-GP

SCD1U25V3KX-GP PC4618

PC4618

1 2

PR4614

PR4614 100KR2J-1-GP

100KR2J-1-GP

3V_5V_POK [22,37]

GND

disable all circuit

D

5

PU4602

PU4605

1125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK51125_VCLK

12

BAT54S-5-GP

PG4610

GAP-CLOSE-PWR-3-GP

1 2

+PWR_SRC_5V

PC4614

PC4615

PC4616

D

12

678

DDD

SC10U25V6KX-1GP

SSS

GD

SSS

GD

123

4 5

G

S

12

D

678

DDD

DY

SI7716ADN-T1-GE3-GP

DY

SSS

GD

SSS

GD

4 5

123

SG

51125_LL1_R

12

DY

SC18P50V2JN-1-GP

12

SC10U25V6KX-1GP

PL4602

1 2

IND-3D3UH-57GP

PR4607

PR4607 2D2R5F-2-GP

2D2R5F-2-GP

PC4621

PC4621 SC560P50V-GP

SC560P50V-GP

0R2J-2-GP

PC4623

PC4616

12

SCD01U50V2KX-1GP

DY

A00-1218-1 changePL4602 from 2.2U to 3.3U by power

PG4620

12

GAP-CLOSE-PWR-3-GP

12

PR4611

12

DY

PR4612

PR4612 33KR2F-GP

33KR2F-GP

51125_FB1_R

12

DY

12

PR4615

PR4615 21K5R2F-GP

21K5R2F-GP

SC1KP50V2KX-1GP

P

D4603

PC4603

PD3903_2

12

P

C4602

SCD1U25V3KX-GP

PD3903_1

3

1

2

12

PC4609

SC1U25V3KX-1-GP

DIS(Auburndale) Design Current =6.58A

10.34A<OCP< 12.22A

2009/08/24

PTC4602

12

P

C4604

SCD1U25V3KX-GP

PD3904_1

3

P

D4604

BAT54S-5-GP

1

2

+5V_PWR+15V_ALW

PD3903_04

12

PC4606

SCD1U25V3KX-GP

PTC4604

12

ST100U6D3VBM-5GP

ST220U6D3VDM-15GP

DY

SC-1130-1 change PC4601 pull up to +5V_ ALW for layout.

Close to VFB Pin (pin2)

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 2.2uH PCMC063T-2R2MN Cyntec 20 mohm Isat =14Arms 68.2R210.20B O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 H/S: SiS412DN 24mohm/30mOhm@4.5Vgs/ 84.00412.037 L/S: Si7716ADN 13.5mOhm/16.5mOhm@4.5Vgs/ 84.06690.E37

D

12

+5V_ALW

DY

12

PC4607

SCD1U25V3KX-GP

PC4601

SCD1U10V2KX-4GP

E

+5V_PWR

PG4614

+PWR_SRC

+PWR_SRC_5V

PG4612

1 2

GAP-CLOSE-PWR

PG4624

1 2

GAP-CLOSE-PWR

PG4625

1 2

GAP-CLOSE-PWR

PG4628

1 2

GAP-CLOSE-PWR

PG4629

1 2

GAP-CLOSE-PWR

PG4631

1 2

GAP-CLOSE-PWR

PG4633

1 2

GAP-CLOSE-PWR

1st Samsung

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

RT8205B_5V/3D3V

Winery13 MB DIS

E

1 2

GAP-CLOSE-PWR

PG4615

1 2

GAP-CLOSE-PWR

PG4616

1 2

GAP-CLOSE-PWR

PG4617

1 2

GAP-CLOSE-PWR

PG4619

1 2

GAP-CLOSE-PWR

PG4601

1 2

GAP-CLOSE-PWR

PG4621

1 2

GAP-CLOSE-PWR

PG4622

1 2

GAP-CLOSE-PWR

PG4632

1 2

GAP-CLOSE-PWR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu R d., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu R d., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

46 88Wednesday, January 13, 2010

+5V_ALW

A00

5

SID = PWR.Plane.Regulator_CPU Core

S

V

R_CLKEN#[7]

+

H_PROCHOT#[9]

PR4764

PR4764 0R2J-2-GP

0R2J-2-GP

1 2

PR4757

PR4757 4K02R2F-GP

4K02R2F-GP

1 2

DY

ISEN1[48]

ISEN2[48]

ISEN3[48]

PWR_SRC

12

T

C4702

S

DY

E100U25VM-10GP

+3.3V_RUN

12

PR4749

+1.05V_VTT

12

PR4751

PR4751 68R2-GP

68R2-GP

DY

IMVP_VR_PWRGD[37]

6266A_NTC_R 62883_NTC

1 2

NTC-470K-8-GP

1 2

DY

SCD01U25V2KX-3GP

SCD01U25V2KX-3GP PC4739

PC4739

62883_COMP_R

1 2

PC4748

PC4748 SC150P50V2JN-3GP

SC150P50V2JN-3GP

ISEN1

ISEN2

ISEN3

5

PR4749

1K91R2F-1-GP

PSI#[12]

62883_AGND

PR4758

2009/07/29

DY

1 2

PR4761

PR4761 8K06R2F-GP

8K06R2F-GP

1 2

PC4740

PC4740 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

1 2

PC4744

PC4744 SC33P50V2JN-3GP

SC33P50V2JN-3GP

1 2

PR4766

PR4766 324KR2F-GP

324KR2F-GP

1 2

PR4748 0R0402-PAD-2-GPPR4748 0R0402-PAD-2-GP

1 2

PR4752 0R0402-PAD-2-GPPR4752 0R0402-PAD-2-GP

1 2

PR4754 147KR2F-GPPR4754 147KR2F-GP

PR4779

PR4779 562R2F-GP

562R2F-GP

PR4780 1K91R2F-1-GPP R4780 1K91R2F-1-GP

VCC_SENSE[12]

VSS_SENSE[12]

62883_PGOOD

62883_PSI#

62883_RBIAS

62883_VW

62883_COMP

62883_FB

ISEN3

PC4743

SCD22U25V3KX-GP

1

SCD22U25V3KX-GP

2

VSUM-

2009/07/29

SCD22U25V3KX-GP

62883_FB_VSEN

1 2

VCC_SENSE_L

1 2

2009/07/29

PR4747

1K91R2F-1-GP

ISEN2

PC4745

62883_AGND

VSUM-

PC4751

SC390P50V2KX-GP

SC330P50V2KX-3GP

SC1000P50V3JN-GP-U

D D

SC-1204-4 remove TC4701 for layout

C C

NTC 470K close to H/S MOSFET of Phase1

62883_AGND

ISEN3

PC4747

PC4747 SC22P50V2JN-4GP

SC22P50V2JN-4GP

B B

A A

+

3.3V_RUN

12

PU4701

1

PGOOD

2

PSI#

3

RBIAS

4

VR_TT#

5

NTC

6

VW

7

COMP

8

FB

9

ISEN3/FB2

10

ISEN2

41

GND

ISL62883HRTZ-T-GP

ISEN1

1

PC4749

2

VSUM-

1 2

PC4754

62883_AGND

PC4759

4

M_DPRSLPVR [12]

P

I

MVP_VR_ON [37]

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

1 2

PR4744 0R0402-PAD-2-GPPR4744 0R0402-PAD-2-GP

PR4737 0R0402-PAD-2-GPPR4737 0R0402-PAD-2-GP

PR4745 0R0402-PAD-2-GPPR4745 0R0402-PAD-2-GP

62883_CLK_EN#

62883_VR_ON

62883_DPRSLPVR

40

39

38

VR_ON

CLK_EN#

DPRSLPVR

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD16VIN17IMON18BOOT119UGATE1

PR4797

PR4797 0R0402-PAD-2-GP

0R0402-PAD-2-GP

12

PC4760

62883_AGND

4

1 2

PR4738 0R0402-PAD-2-GPPR4738 0R0402-PAD-2-GP

PR4746 0R0402-PAD-2-GPPR4746 0R0402-PAD-2-GP

PR4739 0R0402-PAD-2-GPPR4739 0R0402-PAD-2-GP

62883_VID4

62883_VID3

62883_VID6

62883_VID5

VID637VID536VID435VID334VID233VID132VID0

VSUM+

62883_ISUM-

62883_VDD

12

PC4752

SC1U10V2KX-1GP

62883_AGND

12

PR4782

PR4782 82D5R2F-1-GP

82D5R2F-1-GP

VSUM_RC

PC4758

PC4758 SCD01U25V2KX-3GP

SCD01U25V2KX-3GP

1 2

PR4796 2K05R2F-GPPR4796 2K 05R2F-GP

CPU_VID2

CPU_VID1

CPU_VID0

1 2

PR4741 0R0402-PAD-2-GPPR4741 0R0402-PAD-2-GP

PR4743 0R0402-PAD-2-GPPR4743 0R0402-PAD-2-GP

PR4740 0R0402-PAD-2-GPPR4740 0R0402-PAD-2-GP

PR4742 0R0402-PAD-2-GPPR4742 0R0402-PAD-2-GP

62883_VID2

62883_VID1

62883_VID0

31

UGATE2

PHASE2

LGATE2

PWM3/ LGATE1#

LGATE1

PHASE1

20

UGATE1

62883_BOOT1

IMVP_IMON

62883_VIN

1 2

PR4768 0R0402-PAD-2-GPPR4768 0R0402-PAD-2-GP

1 2

12

PC4753

SCD22U25V3KX-GP

2009/07/29

62883_AGND

BOOT2

VSSP2

VCCP

VSSP1

C

+PWR_SRC

1R2F-GP

1R2F-GP PR4769

PR4769

PU_VID[6..0] [12]

BOOT2

30

UGATE2

29

PHASE2

28

27

LGATE2

26

62883_VCCP

25

62883_PWM3

24

LGATE1

23

22

PHASE1

21

PR4767

1 2

2D2R3J-2-GP

+5V_ALW

PR4781

12

6K65R2F-GP

PC4757

PC4756

SCD1U16V3KX-3GP

1 2

3

5V_ALW

+

P

R4736

0R0402-PAD-2-GP

1 2

SC1U10V2KX-1GP

1 2

PC4735

6208_FCCM

6208_PWM

12

PR4750

PR4750 0R0402-PAD-2-GP

0R0402-PAD-2-GP

BOOT2 [48]

UGATE2 [48]

PHASE2 [48]

LGATE2 [48]

LGATE1 [48]

PHASE1 [48]

PC4746

SCD22U16V3KX-1-GP

1 2

BOOT1_PHASE1

PR4794

1 2

DY

100KR2F-L1-GP

12

PC4750

PC4750 SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

VSS_SENSE [12]

12

PR4783

PR4783 1K5R2F-2-GP

SCD047U16V2KX-1-GP

62883_AGND

1K5R2F-2-GP

12

PR4784

11KR2F-L-GP

VSUM_RR

12

PR4795

PR4795 NTC-10K-26-GP

NTC-10K-26-GP

VSUM-

NTC 10K close to Choke of Phase1

12

PC4762

PC4762 SCD1U25V3KX-GP

SCD1U25V3KX-GP

PR4798

GAP-CLOSE-PWR-3-GP

1 2

3

5

2

PWM

6

FCCM

PU4705 ISL6208CRZ-TGP-UPU4705 ISL6208CRZ-TGP-U

9

+5V_ALW

PR4753

PR4753 0R2J-2-GP

0R2J-2-GP

12

DY

PC4741

SC1U10V2KX-1GP

12

VSUM+ [48]

SB-1103

1. change PR4783 to 64.15015.6DL

2. change PR4796 to 64.20515.6DL

3. change PC4756 to 78.10421.2BL

4. change PC4757 to 78.47321.2FL

VSUM- [48]

SC-1130-1 change PC4762 to 0603 size

62883_AGND

1

VCC

BOOT

PHASE UGATE

LGATE

GND

3

12

PR4755

PR4755 0R3J-0-U-GP

0R3J-0-U-GP

PC4742

12

SC1U10V2KX-1GP

UGATE1 [48]

IMVP_IMON [12]

+1.05V_VTT

OOT3

B

1 2

P

R4735

2D2R3J-2-GP

SCD22U16V3KX-1-GP

7 8 4

2009/07/29

PHASE3 UGATE3 LGATE3

208_PHASE3

6

P

C4736

UGATE3

PHASE3

2

1 2

LGATE3

ISEN3

VSUM+

VSUM-

ISEN1

ISEN2

2

C4737

P

12

SC10U25V6KX-1GP

678

DDD

D

DDD

D

U4702

P

SIS406DN-T1-GE3-GP

SSS

G

123

4 5

PU4703

SIS402DN-T1-GE3-GP

2009/07/29

12

SNUBBER3

12

678

DDD

D

DDD

D

SSS

G

123

4 5

1 2

PR4756 51KR2F-L-GPPR4756 51KR2F-L-GP

1 2

PR4759 3K65R3F-GPPR4759 3K65R3F-GP

1 2

PR4760 1R2F-GPPR4760 1R2F-GP

1 2

PR4762 51KR2F-L-GPPR4762 51KR2F-L-GP

1 2

PR4763 51KR2F-L-GPPR4763 51KR2F-L-GP

Intel support POC (power on current).

PR4770

1KR2J-1-GP

CPU_VID0CPU_VID0 CPU_VID1CPU_VID1 CPU_VID2CPU_VID2 CPU_VID3CPU_VID3 CPU_VID4CPU_VID4 CPU_VID5CPU_VID5 CPU_VID6CPU_VID6 PM_DPRSLPVRPM_DPRSLPVR PSI#PSI#

PR4785

1KR2J-1-GP

1

PWR_SRC

+

C4738

C4733

C4734

P

12

SC10U25V6KX-1GP

DY

PR4701

PR4701 2D2R5F-2-GP

2D2R5F-2-GP

2009/07/29

PC4701

PC4701 SC560P50V-GP

SC560P50V-GP

DY

+1.05V_VTT

PR4772

PR4771

12

1KR2J-1-GP

PR4787

PR4786

12

1KR2J-1-GP

DY

1st Samsung

Title

Size Document Number Rev

Custom

Date: Sheet of

C4734

P

12

SC10U25V6KX-1GP

SCD1U50V3KX-GP

L4701

1 2

IND-D36UH-24-GP-U

12

PG4713

GAP-CLOSE-PWR-3-GP

PHASE3_RPHASE3_RPHASE3_R

PR4774

PR4773

12

1KR2J-1-GP

DY

1KR2J-1-GP

DY

PR4788

PR4789

12

1KR2J-1-GP

ISL62883_CPU_CORE_1/2

Winery13 MB DIS

12

PG4714

GAP-CLOSE-PWR-3-GP

+VCC_CORE_PHASE3

PR4775

PR4776

12

1KR2J-1-GP

DY

1KR2J-1-GP

DY

PR4790

PR4791

12

1KR2J-1-GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

PTC4701

PR4777

1KR2J-1-GP

PR4792

1KR2J-1-GP

47 88W ednesday, January 13, 2010

12

DY

12

PR4778

PR4793

+VCC_CORE

PTC4702

ST330U2VDM-4-GP

12

1KR2J-1-GP

DY

12

1KR2J-1-GP

62883_AGND

12

ST330U2VDM-4-GP

A00

5

4

3

2

1

SSID = PWR.Plane.Regulator_CPU Core

+

PWR_SR C

P

C4864

C4863

12

D D

1 2

PR4812

2D2R3J-2-GP

UGATE2

PHASE2

B00T2_R

1 2

PC4867

PC4867 SCD22U16V3KX-1-GP

SCD22U16V3KX-1-GP

ISEN2

VSUM+

VSUM-

ISEN1

ISEN3

LGATE2

UGATE2[47]

PHASE2[47]

BOOT2[47]

C C

BOOT2

LGATE2[47]

ISEN2[47]

VSUM+[47]

VSUM-[ 47]

ISEN1[47]

ISEN3[47]

678

DDD

D

DDD

D

P

U4801

SIS406DN-T1-GE3-GP

SSS

G

123

4 5

678

DDD

D

DDD

D

PU4803

SIS402DN-T1-GE3-GP

SSS

G

123

4 5

1 2

PR4801 51KR2F-L-GPPR4801 51KR 2F-L-GP

1 2

D

PU4802

SIS406DN-T1-GE3-GP

2009/07/28

12

PR4802 3K65R3F-GPPR4802 3K65R3F-GP

PR4803 1R2F-GPPR480 3 1R2F-GP

PR4804 51KR2F-L-GPPR4804 51KR 2F-L-GP

PR4805 51KR2F-L-GPPR4805 51KR 2F-L-GP

678

DDD

SC10U25V6KX-1GP

PC4868

SC10U25V6KX-1GP

DY

SC10U25V6KX-1GP

12

PR4815

PR4815 2D2R5F-2-GP

2D2R5F-2-GP

SNUBBER2SNUBBER1

12

2009/07/28

PC4802

PC4802 SC560P50V-GP

SC560P50V-GP

12

PC4869

SC10U25V6KX-1GP

12

P

PC4870

C4865

SC10U25V6KX-1GP

+PWR_S RC

SC10U25V6KX-1GP

12

P

C4866

PC4871

SCD1U50V3KX-GP

L4801

1 2

IND-D36UH-24-GP- U

12

PG4801

GAP-CLOSE-PWR-3-GP

PHASE2_R

SCD1U50V3KX-GP

DIS(Auburndale) Design Current = 34A Peak Current=48A

57.6A<OCP< 67.2A

+VCC_CORE

PTC4801

ST330U2VDM-4-GP

12

PTC4802

ST330U2VDM-4-GP

12

PG4802

GAP-CLOSE-PWR-3-GP

+VCC_CORE_PHASE2

SSS

G

B B

UGATE1[47]

PHASE1[47]

LGATE1[47]

ISEN1[47]

A A

VSUM+[47]

VSUM-[ 47]

ISEN2[47]

ISEN3[47]

5

PHASE1

LGATE1

2009/07/28

ISEN1

VSUM+

VSUM-

ISEN2

ISEN3

G

123

4 5

UGATE1

678

DDD

D

DDD

D

SSS

G

123

4 5

1 2

PR4807 51KR2F-L-GPPR4807 51KR 2F-L-GP

1 2

PR4808 3K65R3F-GPPR4808 3K65R3F-GP

1 2

PR4809 1R2F-GPPR480 9 1R2F-GP

1 2

PR4810 51KR2F-L-GPPR4810 51KR 2F-L-GP

1 2

PR4811 51KR2F-L-GPPR4811 51KR 2F-L-GP

4

PU4804

SIS402DN-T1-GE3-GP

2009/07/28

12

DY

PR4816

PR4816 2D2R5F-2-GP

2D2R5F-2-GP

12

2009/07/28

PC4803

PC4803 SC560P50V-GP

SC560P50V-GP

DY

12

PG4803

PHASE1_R

L4802

1 2

IND-D36UH-24-GP- U

GAP-CLOSE-PWR-3-GP

+VCC_CORE

12

PTC4803

ST330U2VDM-4-GP

12

PG4804

GAP-CLOSE-PWR-3-GP

+VCC_CORE_PHASE1

3

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 0.36UH ETQP4LR36WFC PANASONIC 1.1mohm/ 68.R3610.20A O/P cap: 330U 2V EEFSX0D221E7 6mOhm 3.0Arms Panasonic/79.33719.20L

12

PTC4804

O/P cap: 220U 2V EEFSX0D331XE 7mOhm 3.4Arms Panasonic/79.22719.90L

SE220U2VDM-12GP

H/S: SiR474DP/ POWERPAK-8/ 10mOhm/12mOhm @4.5Vgs/ 84.00474.037 L/S: Si7170DP/ POWERPAK-8/ 3.6mOhm/4.3mohm@4.5Vgs/ 84.07170.037 Freq=300KHz@PER PHASE

1st Samsung

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

ISL62883_CPU_CORE_2/2

Winery13 MB DIS

Wistron Corporation

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

48 88Wednesday, January 13, 2010

1

A00

5

S

SID = PWR.Plane.Regulator_1D05V_VTT

+

PWR_SR C+PWR_SR C_1D05V

D D

C C

B B

G4902

P

1 2

GAP-CLOS E-PWR

G4903

P

1 2

GAP-CLOS E-PWR

PG4904

1 2

GAP-CLOS E-PWR

PG4905

1 2

GAP-CLOS E-PWR

PG4906

1 2

GAP-CLOS E-PWR

2009/08/18

RUNPWRO K[5 0,51]

VTT_PWRGD

SCD1U25V 3KX-GP

PC4912

SB-04

PR4902

1 2

80K6R2F-G P

PR4921

1 2

0R0402-P AD-2-GP

+3.3V_RUN

12

PR4907

PR4907 10KR2J-3-G P

10KR2J-3-G P

12

DY

VTT_PWRGD[9,37,52]

12

PC4907

SC1KP50V2KX-1GP

H_VTTPWRG DH_VTTPW RGDH_VTTPWRGDH_VTTPW RGDH_ VTTPWRGDH_VTTPWRGDH_VTTPW RGDH_VTTPWRGDH_VTTPWR GDH_V TTPWRGD

51218_ VTT_TRIP 51218_ VTT_EN 51218_ VTT_VFB 51218_ VTT_CCM

12

PR4903

PR4903 470KR2F-G P

470KR2F-G P

PQ4901

1

6

2

5

3 4

DMN66D0LD W-7-GP

T

PS51218 for +1.05V_VTT

PU4901

1

PGOOD

2

TRIP

3

EN

4

VFB

5

CCM

H_VTTPWRG D_R

11

GND

10

VBST

9

DRVH

8

SW

7

V5IN

6

DRVL

TPS51218 DSCR-GP-U1

+3.3V_AL W

12

PR4908

PR4908 100KR2J-1 -GP

100KR2J-1 -GP

+1.05V_V TT

12

PR4909

PR4909 1KR2J-1-GP

1KR2J-1-GP

4

51218_ VBST_VTT 51218_ DRVH_VTT 51218_ SW_VTT

51218_ DRVL_VTT

H_VTTPWRG D [9]

PR4901

2D2R3J-2-G P

1 2

51218_ VBST_VTT1

+5V_ALW

12

PC4908

SC1U10V2 KX-1GP

PC4906

SCD1U25V 3KX-GP

12

PWR_SR C_1D05V

+

678

DDD

G

4 5

678

DDD

G

4 5

3

SC10U25V6KX-1GP

PC4924

DY

SC10U25V6KX-1GP

PC4909

1 2

IND-D56UH-12 -GP

12

SB-24

51218_SW_GND_VTT

12

SC330P50V2KX-3GP

SC10U25V6KX-1GP

1 2

PL4901

PR4905

PR4905 10KR2F-2-G P

10KR2F-2-G P

PR4906

PR4906 19K6R2F-G P

19K6R2F-G P

SC10U25V6KX-1GP

D

PU4905

SIS406DN-T1-GE3-GP

SSS

D

PU4904

SIS402DN-T1-GE3-GP

SSS

51218_ VTT_VFB

1 2

PR4904 2D2 R5J-1-GP

PC4911

678

DDD

D

PU4902

SIS406DN-T1-GE3-GP

SSS

123

D

PU4903

SIS402DN-T1-GE3-GP

SSS

123

DDD

G

4 5

DDD

G

4 5

123

678

123

SCD1U50V3KX-GP

PC4904

PC4903

1 2

GAP-CLOSE-PWR-3-GP

12

PG4921

1 2

DY

PR4912

PR4912 10R2J-2-GP

10R2J-2-GP

+1.05V_VTT_VOUT

12

R1

12

R2

2

SC4D7U25V5KX-GP

PC4905

PC4902

DIS(Arrandale 1.05V_VTT) Design Current = 22.75A

1 2

31.28A<OCP<36.96A

2009/08/24

SCD1U10V2KX-4GP

SC4D7U6D3V5KX-3GP

12

PC4901

PC4910

12

VTT_SENSE [ 12]

12

PTC4902

SE330U2VDM-L-GP

+1.05V_V TT_P

Vout=0.704V*(R1+R2)/R2

PTC4901

12

SE330U2VDM-L-GP

2009/08/05

+1.05V_V TT_P +1.05V_VTT

SB-24

PTC4903

12

SE330U2VDM-L-GP

DY

PG4908

1 2

GAP-CLOS E-PWR

PG4910

1 2

GAP-CLOS E-PWR-3-GP

PG4911

1 2

GAP-CLOS E-PWR-3-GP

PG4913

1 2

GAP-CLOS E-PWR-3-GP

PG4915

1 2

GAP-CLOS E-PWR-3-GP

PG4917

1 2

GAP-CLOS E-PWR-3-GP

PG4919

1 2

GAP-CLOS E-PWR

PG4925

1 2

GAP-CLOS E-PWR

PG4926

1 2

GAP-CLOS E-PWR

PG4933

1 2

GAP-CLOS E-PWR

PG4934

1 2

GAP-CLOS E-PWR

PG4939

1 2

GAP-CLOS E-PWR

1

+1.05V_V TT_P +1.05V_VTT

PG4909

1 2

GAP-CLOS E-PWR

PG4901

1 2

GAP-CLOS E-PWR

PG4912

1 2

GAP-CLOS E-PWR-3-GP

PG4914

1 2

GAP-CLOS E-PWR-3-GP

PG4916

1 2

GAP-CLOS E-PWR-3-GP

PG4918

1 2

GAP-CLOS E-PWR-3-GP

PG4920

1 2

GAP-CLOS E-PWR

PG4927

1 2

GAP-CLOS E-PWR

PG4928

1 2

GAP-CLOS E-PWR

PG4923

1 2

GAP-CLOS E-PWR

PG4944

1 2

GAP-CLOS E-PWR

PG4930

1 2

GAP-CLOS E-PWR

SB-1104

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Frequency setting 470K -->290KHz 200K -->340KHz

Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01 H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037 L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037

100K -->380KHz

A A

5

4

39K -->430KHz

1st Samsu ng

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51218_+1.05V_VTT

Size Document Num ber Rev

Custom

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

1

49 88Wednesday, J anuary 13, 2010

A00

5

S

SID = PWR.Plane.Regulator_1D5V/0D75V

5V_ALW

+

P

R5006

12

5D1R3J-GP

S

D D

2

009/08/05

+

PWR_SRC_1D5V

RT: Non_ASM TI: ASM

C C

+

RUNPWROK[49,51]

PR5011 620KR2F-GP

+5V_ALW

+1.5V_SUS_P

PR5002 0R0402-PAD-2-GPPR5002 0R0402-PAD-2-GP

+0D75V_DDR_P

B-1103

P

R5007

13KR2F-GP

3.3V_ALW

1 2

PR5001 1M1R2J-GP

PR5004

PR5004 20KR2F-L-GP

20KR2F-L-GP

DY

1 2

SC1KP50V2KX-1GP

+1.5V_SUS_P

DY

SC1KP50V2KX-1GP

1 2

C5003

P

TPS51116_VDD_R

PC5002

SC1U10V3KX-3GP

PC5017

DY

1 2

PS51116_VDD

T

TPS51116_NC#12

1D5V_EN

0D75V_EN

12

TPS51116_TON

13

12

11

10

23

7

1

4

24

2

Design Current = 0.7A

+0D75V_DDR_P

B B

12

C5008

C5008 P

P

VDDQSET

A A

GND

V5IN

FB Resistors

12

SC10U6D3V5MX-3GP

Adjustable

C5010

C5010 P

P

SC10U6D3V5MX-3GP

Lo Hi

2.5

1.8

12

C5011

C5011 P

P

SC10U6D3V5MX-3GP

HiHi

On Off(Hi-Z)

LoLo

VVDDQSNS/2

5

12

C5009

C5009 P

P

SCD1U10V2KX-4GP

State S3 S5 VDDR VTTREF VTT

S0 On

S3

S4/S5

On

OffOff

PG5014

1 2

GAP-CLOSE-PWR

PG5015

1 2

GAP-CLOSE-PWR

On

Off

NOTEVTTREF and VTTVDDQ (V)

DDR

DDR2

1.5 V < VVDDQ < 3 V

5D1R3J-GP

12

SC1U10V3KX-3GP

C5018

P

15

16

14

PU5002

ILIM

VDDP

PGD

NC#12

EN/PSV

VTTEN

VTTIN

NC#7

TPS51116RGER-GP-U

PGND2

TON

VTT

VTTS

PGND1 PGND1

VDDQS

VCCA

REF

VSSA

GND

5

3

25

1 2

0R0603-PAD

TPS51116_REF

12

TPS51116_LGT

BST

DH

DL

FB

PR5013

PC5021

PC5021 SCD033U16V3KX-GP

SCD033U16V3KX-GP

TPS51116_UGT

TPS51116_VBST1

4

+

5V_ALW

+

5V_ALW

12

PC5019

SC1U10V3KX-3GP

PR5003

TPS51116_VBST

22

TPS51116_UGT

21

TPS51116_PHS

20

LX

TPS51116_LGT

19

18 17

TPS51116_VDDQSNS

8

TPS51116_VDDQSET

9

6

+V_DDR_REF

+5V_ALW

1 2

PC5012

SCD1U25V3KX-GP

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L0 H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037 L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037 Switching freq-->400KHz

4

1 2

0R3J-0-U-GP

0R2J-2-GP

12

PC5020

DY

SC1U10V3KX-3GP

TPS51116_VBST1

PR5005

1 2

DY

D

Y

2 1

P

D5001

CH551H-30PT-GP

2009/08/05

+PWR_SRC_1D5V

DDD

DY

G

4 5

DDD

DY

G

4 5

678

D

PU5003

SIS406DN-T1-GE3-GP

SSS

123

TPS51116_PHS

D

PU5001

SIS402DN-T1-GE3-GP

SSS

123

+PWR_SRC

3

GAP-CLOSE-PWR

3

D

0

1. Not reserve 1.5V_RUN_EN ??

2009/08/05

+PWR_SRC_1D5V

PG5002

12

PG5004

12

PG5006

12

PG5008

12

678

DDD

D

DDD

D

PU5009

SIS406DN-T1-GE3-GP

SSS

G

123

4 5

678

DDD

D

DDD

D

PU5008

SIS402DN-T1-GE3-GP

SSS

G

123

4 5

W

7/08 Del

P

M_SLP_S3#[22,34,37,42,51,86]

PM_SLP_S4#[22,34,37]

S

B-1020-1

DY PR5012

P

R5012 0R2J-2-GP

PR5014

PR5014 0R0402-PAD-2-GP

0R0402-PAD-2-GP

PC5035

1 2

SC10U25V6KX-1GP

IND-1D5UH-34-GP

12

PR5008

DY

2D2R5F-2-GP

TPS51116_PHS_SET

12

DY

PC5015

PC5015 SC330P50V3KX-GP

SC330P50V3KX-GP

1 2

D

1 2

PC5004

SC10U25V6KX-1GP

PL5001

1 2

TPS51116_VDDQSNS

TPS51116_VDDQSET

Y

1 2

PC5005

SC10U25V6KX-1GP

SB-1104

PR5009

PR5009 30K9R2F-GP

30K9R2F-GP

PR5010

30KR2F-GP

2

0

D75V_EN

D

Y

1D5V_EN

DY

PC5006

1 2

SCD1U50V3KX-GP

1 2

PG5016

GAP-CLOSE-PWR-3-GP

12

DY

12

P

C5001

SCD1U10V2KX-4GP

12

PC5022

PC5022 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

PC5007

SC4D7U25V5KX-GP

12

PC5016

PC5016 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

0

D75V_EN [52]

DIS(Auburndale) Design Current = 11.82A

18.57A<OCP<21.95A

+1.5V_SUS_P+0.75V_DDR_VTT+0D75V_DDR_P

PTC5001

12

SE220U2VDM-8GP

PC5014

PC5013

2009/08/18

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

DY

12

PTC5002

SE220U2VDM-8GP

1st Samsung

+1.5V_SUS_P

Close to VFB Pin (pin5)

Title

TPS51116_+1.5V_SUS

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

1

+1.5V_SUS

PG5001

1 2

GAP-CLOSE-PWR

PG5003

1 2

GAP-CLOSE-PWR

PG5005

1 2

GAP-CLOSE-PWR

PG5007

1 2

GAP-CLOSE-PWR

PG5009

1 2

GAP-CLOSE-PWR

PG5011

1 2

GAP-CLOSE-PWR

PG5012

1 2

GAP-CLOSE-PWR

PG5013

1 2

GAP-CLOSE-PWR

PG5019

1 2

GAP-CLOSE-PWR

PG5020

1 2

GAP-CLOSE-PWR

PG5021

1 2

GAP-CLOSE-PWR

PG5022

1 2

GAP-CLOSE-PWR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsic hih,

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

1

A00

of

50 88Wednesday, January 13, 2010

5

S

SID = PWR.Plane.Regulator_1D8V

D D

C C

4

A

PL5930 for +1.8V_RUN

RUNPW ROK[49,50]

PM_SLP_S3#[22,34,37,42,50,86]

A00-0107-3 change R5102 to short pad, PC5105 to 10K for power's suggestion To prevent PM_SLP_S3# signal rebound

R5102

1 2

0R0402-PAD-2-GP

1D8V_RUN_EN

APL5930KAI-TRG-GP

12

PC5105

PC5105 10KR2J-3-GP

10KR2J-3-GP

3

GAP-CLOSE-PW R

SC10U6D3V5MX-3GP

12

PR5104

15KR2F-GP

PR5105

PR5105 12KR2F-L-GP

12KR2F-L-GP

GAP-CLOSE-PW R

PC5106

SC68P50V2JN-1GP

12

+

5V_ALW

SC1U10V3KX-3GP

PC5102

12

6

PU5102

7

VIN#5

POK

VIN#9

VCNTL

8

VOUT#3

EN

VOUT#4

FB

GND

1

SO-8-P

SC10U6D3V5MX-3GP

PC5103

PC5104

12

DY

1D8V_VIN

5 9

3 4

2

12

5912_1.8V_RUN_FB

12

2

+

3.3V_ALW

G5102

P

12

G5103

P

12

DIS(Arrandale) Design Current =0.57A

PC5108

12

2009/07/29

+1.8V_RUN_P

SC22U6D3V5MX-2GP

PC5107

SC22U6D3V5MX-2GP

12

DY

Vout=0.8V*(R1+R2)/R2

1

+1.8V_RUN_P +1.8V_RUN

PG5104

1 2

GAP-CLOSE-PW R

PG5105

1 2

GAP-CLOSE-PW R

2009/07/29

RT9025 for +1.8V_RUN_GPU

1 2

+3D3V_1D8_LDO

12

DY

PC5111

B B

DGPU_1D8V_PGOOD[23,25]

1.8_GFX_ON[ 37]

A A

5

4

1 2

PR5106

0R0402-PAD-2-GP

DGPU_1D8V_PGOOD RT9025_EN

RT9025_EN

12

DY

+5V_ALW

SC1U16V3KX-2GP

PC5111

SC10U10V5KX-2GP

PC5115

PC5115 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

PC5112

DY

SC10U10V5KX-2GP

PU5103

1

PGOOD

2

EN

3

VIN VDD4NC#5

RT9025-25PSP-GP

3

PC5109

8

GND

7

ADJ

6

VOUT

5

GND

9

1 2

12

PG5109

GAP-CLOSE-PW R

GAP-CLOSE-PW R PG5106

PG5106

GAP-CLOSE-PW R

12

PR5107

PR5107 15KR2F-GP

15KR2F-GP

RT9025_FB

12

PR5108

PR5108 12KR2F-L-GP

12KR2F-L-GP

+3.3V_ALW

12

PC5113

SC100P50V2JN-3GP

12

Vo=0.8*(1+(R1/R2))

2

DIS: Peak current:300mA Design current:210mA

+1.8V_PW R

1 2

12

PC5114

PC5110

SC10U10V5KX-2GP

1st Samsung

Title

Size Document Number Rev

Custom

Date: Sheet of

1 2

SC10U10V5KX-2GP

+1.8V_RUN_GPU

PG5108

GAP-CLOSE-PW R

GAP-CLOSE-PW R PG5107

PG5107

GAP-CLOSE-PW R

Wistron Corporation

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

APL5930/RT9205

Winery13 MB DIS

1

51 88Wednesday, January 13, 2010

A00

5

S

SID = PWR.Plane.Switch_1D5V CPU

S

D D

B-1020-1

DY R5215, R5222, R5223; POP R5221, C5210, R5226, R5210, Q5203, R5211.

4

PS_S3CNTRL[42]

VTT_PWRGD[9,37,49]

3

R5210

1 2

100KR2J-1-GP

PS_S3CNTRL

G

1ST: 84.2N702.E31 2ND: 84.2N702.D31

0D75V_EN

Q5203

2N7002A-7-GP

S D

0D75V_EN [50]

PS_S3CNTRL

1ST: 84.2N702.E31 2ND: 84.2N702.D31

0.75V_DDR_VTT

+

G

2

12

Q5204_D

S D

R

5211

22R2J-2-GP

Q5204

Q5204 2N7002A-7-GP

2N7002A-7-GP

1

C C

MAX Current 3000 mA

+1.5V_CPU:

Design Current 2100 mA

+1.5V_CPU+1.5V_SUS

A00-1223-1 remove R5215, R5222, R5223 for cost down

Rds(on) = 4.7 mOhm (Max)

Q5205

S

D

S

D

8

D

B B

1ST: 84.00460.037

R5221

R5221 10KR2J-3-GP

RUN_POWER_ON[39,42]

RUN_POWER_ON

A00-1223-1 change R5221 to 10K; remove R5225 for cost down

10KR2J-3-GP

1 2

DW

07/20 corrected

1. Removed C5288

2. RemovedQ5207,R5225,R5220 to save more part counts

2ND:

1.5V_CPU_ENABLE

12

D

7

D

6

D

SIR460DP-T1-GE3-GP

C5209

C5209 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

1

S

2

S

3

G

45

A00-1223-1 change Q5205 from 84.03420.031 to 84.00460.037

12

C5210

C5210 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

Calpella Platform S3 Power Reduction Platform S3 Power Reduction CRB Implementation Design Details

DW

07/07 Added

1.Added discharge circuit

PS_S3CNTRL

1ST: 84.2N702.E31 2ND: 84.2N702.D31

+1.5V_CPU

G

12

Q5202_D

S D

Revision 0.1

R5226

R5226 221R2F-2-GP

221R2F-2-GP

Q5202

Q5202 2N7002A-7-GP

2N7002A-7-GP

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Custom

DC to DC 1D5V

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

52 88W ednesday, January 13, 2010

1

A00

5

S

SID = CPU.GFX.Regulator

D D

C C

B B

A A

12

C1KP50V2KX-1GP

C1KP50V2KX-1GP S

S

GND_3211 _I

PC5316

5

PWR_SR C

+

PWR_SR C_CPU_GFXCOR E

+

P

G5302

1 2

GAP-CLOS E-PWR

PG5303

1 2

GAP-CLOS E-PWR

PG5305

1 2

GAP-CLOS E-PWR

PG5307

1 2

GAP-CLOS E-PWR

PG5309

1 2

GAP-CLOS E-PWR

GFX_IMON[ 13]

A00-1218-1 change PR5314 from 5.9K to 6.2K by power

12

PC5309

PC5314

1 2

PC5314

3211_P C5314

1 2

SC470P5 0V2KX-3GP

1 2

SC220P50V2JN-3GP

1KR2F-3-GP

3211_FB_1

PR5331

PR5331 0R0402-P AD-2-GP

0R0402-P AD-2-GP

PR5332

PR5332 0R0402-P AD-2-GP

0R0402-P AD-2-GP

PR5318

G

FX_VID6[1 3]

G

FX_VID5[1 3]

GFX_VID4[13]

GFX_VID3[13]

GFX_VID2[13]

GFX_VID1[13]

GFX_VID0[13]

+1.05V_V TT

GFX_VR_E N[13]

12

PR5314

6K2R2F-GP

12

20KR2F-L-G P

SC47P50V2JN-3GP

1 2

PR5319

+PWR_S RC_CPU_GFXCO RE

PR5335

3211_V SENSE

1 2

100R2F-L1 -GP-U

VCC_AXG_ SENSE [13]

VSS_AXG _SENSE [ 13]

PR5336

3211_V SS_GND

1 2

100R2F-L1 -GP-U

4

P

R5302 0R0402-P AD-2-GP

1 2

P

R5303 0R0402-P AD-2-GP

1 2

PR5304 0R040 2-PAD-2-GPPR53 04 0R04 02-PAD-2-GP

1 2

PR5305 0R040 2-PAD-2-GPPR53 05 0R04 02-PAD-2-GP

1 2

PR5307 0R040 2-PAD-2-GPPR53 07 0R04 02-PAD-2-GP

1 2

PR5308 0R040 2-PAD-2-GPPR53 08 0R04 02-PAD-2-GP

1 2

PR5309 0R040 2-PAD-2-GPPR53 09 0R04 02-PAD-2-GP

1 2

PR5301 10KR2 J-3-GP

1 2

DY

PR5310 0R040 2-PAD-2-GPPR53 10 0R04 02-PAD-2-GP

1 2

+1.05V_V TT

12

PR5312

PR5312 10KR2J-3-G P

10KR2J-3-G P

DY

2009/08/28

PC5307

SCD068U1 0V2KX-1GP

1 2

+5V_ALW

PC5311

3211_CS COMP

1 2

PR5320 80K6R 2F-GPP R5320 80K6R2F-GP

1 2

PR5322 237KR 2F-GPP R5322 237KR2F-GP

1 2

PR5323 340KR 2F-1-GPPR5 323 340 KR2F-1-GP

GND_3211 _I

3211_RA MP_1

12

PR5324

1KR2F-3-GP

PG5319

1 2

GAP-CLOS E-PWR-3-GP

PG5320

1 2

GAP-CLOS E-PWR-3-GP

+CPU_GFXCO RE

4

S

C-1208-1

change PR5311 from 4D7K to 470R

3211_G FX_VR_EN

12

PR5311

PR5311 470R2J-2-G P

470R2J-2-G P

+3.3V_AL W

GND_3211 _I

PR5313

PR5313 10KR2J-3-G P

10KR2J-3-G P

1 2

3211_P WRGD

1 2

3211_IL IM

3 4 5 6 7 8

3211_FB RTN 3211_FB 3211_CO MP

1 2

PR5316 9K 09R2F-GPPR5 316 9K09R2F -GP

2009/08/05

ADP3211 MNR2G-GP

1 2

PR5325 42 2KR2F-1-GPPR5325 42 2KR2F-1-GP

12

PC5317

PC5317 SC1000P 100V3KX-GP

SC1000P 100V3KX-GP

GND_3211 _I

PR5333

PR5333 0R0402-P AD-2-GP

0R0402-P AD-2-GP

GND_3211 _I

3

211_VID6

3

211_VID5

3211_V ID4

3211_V ID3

3211_V ID2

3211_V ID1

3211_V ID0

PU5301

PWRGD IMON CLKEN# FBRTN FB COMP GPU ILIM

3211_IR EF

3211_RP M

3211_RT

31EN32

IREF9RPM10RT11RAMP12LLINE13CSREF14CSFB15CSCOMP

3211_LLINE

3211_CSFB

3211_CSREF

3211_RAMP

12

DY

PR5329

20KR2F-L-GP

12

PC5320

PC5320 SC1KP50 V2KX-1GP

SC1KP50 V2KX-1GP

3211_CSCOMP

GND_3211 _I

PG5325

1 2

GAP-CLOS E-PWR-3-GP

2009/08/03

16

3211_CSCOMP

12

VID625VID526VID427VID328VID229VID130VID0

PC5318

3

5V_ALW

+

12

PR5306

10R3J-3-GP

12

PC5301

SC1U10V2KX-1GP

GND_3211 _I

PC5308

PC5308 SCD22U16 V3KX-2-GP

3211_V CC

24

VCC

3211_B ST

PR5315 1R3J-L1-G PPR5315 1R3J-L1-G P

23

BST

22

DRVH

21

SW

20

PVCC

19

DRVL

18

PGND

17

GND

33

GND

PC5319

SC1KP50V2KX-1GP

SC470P50V2KX-3GP

12

1 2

3211_DRV H 3211_DRV H 3211_S W

3211_DRV L

GND_3211 _I

PR5326

3211_CS COMP_1

1 2

110KR2F-G P

PR5330

PR5330 NTC-220K-2-GP

NTC-220K-2-GP

1 2

3211_B ST_1

12

PC5310

SC3D3U10V5KX-2GP

3211_DR VL

PR5327

1 2

178KR3F-G P

SCD22U16 V3KX-2-GP

1 2

+5V_ALW

SB-1103

I/P cap: 10U 25V K1206 X5R/ 78. 10622.52L Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1. 8mohm Isat=25Ar ms 68.R5610.10D O/P cap: 330U 2 .5V EEFSX0D331E R 9mOhm 3Arms P ANASONIC/ 79.33 719.L01 H/S: SI7686DP/ P OWERPAK-8/11mOh m/14mOhm@4.5Vgs / 84.07686.037 L/S: SiR460DP/ P OWERPAK-8/ 4.9m Ohm/6.1mohm@4.5 Vgs/ 84.00460.0 37

3

PR5328

1 2

60K4R2F-G P

SB-1103

PU5302

SI7686DP -T1-GP

PU5303

2

+PWR_S RC_CPU_GFXCO RE

678

DDD S

SSGD

123

4 5

678

DDD

D

DDD

D

SIR460DP-T1-GE3-GP

SSS

G

123

4 5

2009/08/05

3211_S W_L

2

PC5305

12

DY

2D2R3J-2-GP

DY

SC470P50V2KX-3GP

SC10U25V6KX-1GP

12

PR5317

3211_SW_GND

12

PC5315

PG5323

PC5303

12

SC10U25V6KX-1GP

12

PC5304

12

PL5301

1 2

IND-D56UH-12 -GP

GAP-CLOSE-PWR-3-GP

1

PC5306

12

SC10U25V6KX-1GP

SCD01U25V2KX-3GP

UMA Thermal Design C urrent = 12A Max. Current = 2 2A

24.2A<OCP<28.6A

+CPU_GFXC ORE

12

PTC5302

PG5324

PTC5302

12

GAP-CLOSE-PWR-3-GP

1st Samsu ng

Title

ADP3211 CPU_GFXCORE

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

12

PTC5301

PC5312

PC5312 SE330U2VDM-L-GP

SE330U2VDM-L-GP

SCD01U25V2KX-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

1

12

PC5313

SC1U10V2KX-1GP

A00

of

53 88Wednesday, January 13, 2 010

SID = VIDEO

S

H=>B1 -iGPU PCH (UMA) L=>B0 -dGPU GPU (DIS)

LVDS CONNECTOR

JAE-CON30-5-GP-U

LCD1

32 NP2 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

1 NP1 31

37

36

35

34

33

1ST: 20.F1555.030 2ND:

+PWR_SRC_LCD

+3.3V_EEPROM LCD_BRIGHTNESS

BLON_OUT_R LCD_TST_L LDDC_CLK_CON LDDC_DATA_CON LCD_DET_G LCD_CBL_DET#

VGA_TXAOUT0VGA_TXAOUT0+

VGA_TXAOUT1VGA_TXAOUT1+

VGA_TXAOUT2VGA_TXAOUT2+

VGA_TXACLKVGA_TXACLK+

U

LDDC_DATA[81]

L_DDC_DATA[20]

EDID_SELECT#[21,55]

LDDC_CLK[81]

L_DDC_CLK[20]

EC5404

EC5404 SCD1U50V3KX-GP

SCD1U50V3KX-GP

1 2

+LCDVDD

1 2

R5404 33R2J-2-GPR5404 33R2J-2-GP

R5406 100R2J-2-GPR5406 100R2J-2-GP

1 2

R5413 100R2J-2-GPR5413 100R2J-2-GP

1 2

SB-06

LCD_CBL_DET# [25]

VGA_TXAOUT0- [74] VGA_TXAOUT0+ [74]

VGA_TXAOUT1- [74] VGA_TXAOUT1+ [74]

VGA_TXAOUT2- [74] VGA_TXAOUT2+ [74]

VGA_TXACLK- [74] VGA_TXACLK+ [74]

+

N5404

R

R SRN2K2J-1-GP

SRN2K2J-1-GP

3.3V_RUN

1

23

4

DDC_DATA[81]

L

DDC_CLK[81]

L

lose PCH Close GPU

C

_DDC_DATA[20]

L

_DDC_CLK[20]

L

+

N5409

R

R SRN2K2J-1-GP

SRN2K2J-1-GP

3.3V_RUN_GPU

1

23

4

D

W

0

7/07 Added

1.Added LVDS DDC CLK/DAT Pull Hi

MA/DIS LVDS DDC CLK/DAT select circuit

+

3.3V_RUN

U

5444

LDDC_DATA_CON

4

B03A

EDID_SELECT#

12

C5402

C5402 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+3.3V_RUN

1 2

2 1

+3.3V_RUN

R5408

R5408 100R2J-2-GP

100R2J-2-GP

NC7SB3157P6X-1GP

DY

GND

VCC

B1

U5445

B03A GND

VCC

B1

12

R5410

R5410 10KR2J-3-GP

10KR2J-3-GP

LCD_BRIGHTNESS

5 6

S

1ST: 73.03157.C0H 2ND: 73.03157.E0J

+3.3V_RUN

4 5 6

S

1ST: 73.03157.C0H 2ND: 73.03157.E0J

BLON_OUT [37]

LCD_TST [37]

EDID_SELECT#

LDDC_CLK_CON

EDID_SELECT#

LDDC_DATA_CON LDDC_CLK_CON

12

DY

C5414

SC22P50V2JN-4GP

DY

C5415

SC22P50V2JN-4GP

UMA/DIS LVDS PWM select circuit

R5438

R5438 0R2J-2-GP

0R2J-2-GP

LBKLT_CTL_EC[37]

LBKLT_CTL_GPU[81]

LBKLT_CTL_PCH[20]

1 2

DY

U5448

VCC

4 5 6

S

B03A

2

GND

1

B1

NC7SB3157P6X-1GP

H=>B1 -iGPU PCH (UMA) L=>B0 -dGPU GPU (DIS)

+3.3V_RUN

LCD_BRIGHTNESS

1ST: 73.03157.C0H 2ND: 73.03157.E0J

12

EV @ LVDS side

DGPU_PWM_SELECT# [21]

SID = Inverter

S

SSID = VIDEO

LCD POWER

SC-1125-2 add mux U5446 to select LCDVDD enable signal

D5409

D5409 BAT54C-7-F-GP

ENVDD_M

SHBM_LCDTST_EN[37]

A00-1223-1 modify LCD power schematic remove D5401

BAT54C-7-F-GP

1

3

2

1ST: 83.00054.X81 2ND: 83.BAT54.081

DGPU_SELECT# : H=>B1 -iGPU PCH (UMA) L=>B0 -dGPU GPU (DIS)

LCDVDD_EN_GPU[81]

LCDVDD_EN_PCH[20]

PWR_SRC_LCD

+

ENVDD_D

U5446

B03A

2

GND

VCC

1

B1

S

NC7SB3157P6X-1GP

INVERTER POWER

12

C5401

C5401 SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

R5409

R5409 0R2J-2-GP

0R2J-2-GP

1 2

12

R5411

R5411 49K9R2F-L-GP

49K9R2F-L-GP

+3.3V_RUN

ENVDD_M

4 5 6

1ST: 73.03157.C0H 2ND: 73.03157.E0J

C5405

C5405 SCD1U25V3KX-GP

SCD1U25V3KX-GP

1 2

ENVDD

12

C5408

C5408 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

DY

1ST: 69.50007.A41 2ND: 69.50007.A31

F

5401

POLYSW-1D1A24V-1-GP

12

+LCDVDD

12

C5403

C5403 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

U5403

IN#5

4

5

OUT3IN#4

2

GND

1

EN

G5285T11U-GP

1ST: 74.05285.07F 2ND:

DGPU_SELECT# [21,37,74]

PWR_SRC

+

12

EC5403

EC5403 SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SC-1207-1 pop EC5403 for EMI

12

C5406

C5406 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+3.3V_RUN+LCDVDD

12

C5407

C5407 SC1U10V3KX-3GP

SC1U10V3KX-3GP

SB-1023

LCD_BRIGHTNESS

LCD_TST

DY

12

EC5401

EC5402

DY

SC33P50V2JN-3GP

For EMI request

BLON_OUT_R

12

R5407

R5407 10KR2J-3-GP

10KR2J-3-GP

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD/Inverter Connector

Size Document Number Rev

Custom

Date: Sheet of

LCD/Inverter Connector

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

54 88W ednesday, January 13, 2010

A00

5

4

3

2

1

5V_CRT_ RUN

12

C5506

C5506 SC8P250 V2CC-GP

SC8P250 V2CC-GP

+

12

5504

D

D B0530W S-7-F-GP

B0530W S-7-F-GP

K A

C

5510

SCD01U1 6V2KX-3GP

+5V_CRT _RUN

AFTP550 3AFTP5503 AFTP550 1AFTP5501 AFTP550 9AFTP5509 AFTP550 7AFTP5507 AFTP550 6AFTP5506 AFTP550 8AFTP5508 AFTP550 4AFTP5504 AFTP550 5AFTP5505

SID = VIDEO

S

A00-1218-1 change R5504, R5505, R550 6 from 0R to 33R by EMI

R

5504

DY

12

1 2

R

5505

1 2

R5506

1 2

C5512

C5512 SC8P250 V2CC-GP

SC8P250 V2CC-GP

3

DY

1

M

D D

C C

_RED[74]

M

_GREEN[74]

M_BLUE[74 ]

R5502

R5502 150R2F-1 -GP

150R2F-1 -GP

CRT_R CRT_G CRT_B

3

DY

1

12

R5501

R5501 150R2F-1 -GP

150R2F-1 -GP

D5501

D5501 BAV99-4-G P

BAV99-4-G P

+3.3V_RU N_GPU +3 .3V_RUN_GPU +3.3V_RU N_GPU

2

12

R5503

R5503 150R2F-1 -GP

150R2F-1 -GP

12

DY

C5509

C5509 SC8P250 V2CC-GP

SC8P250 V2CC-GP

3

D5502

D5502 BAV99-4-G P

BAV99-4-G P

DY

1

2

12

DY

C5507

C5507 SC8P250 V2CC-GP

SC8P250 V2CC-GP

M

_RED_C

33R2J-2-G P

_GREEN_ C

M

33R2J-2-G P

M_BLUE_ C CRT_B

33R2J-2-G P

D5503

D5503 BAV99-4-G P

BAV99-4-G P

2

A00-1218-1 change L5501, L5502, L550 3 to 0R

L

5502

1 2

5502

0R3J-0-U-G P

5501

L

L 0R3J-0-U-G P

0R3J-0-U-G P

L5503

L5503 0R3J-0-U-G P

0R3J-0-U-G P

C5508

C5508 SC8P250 V2CC-GP

SC8P250 V2CC-GP

12

Layout Note:

*Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. * RGB signal will hit 75 Ohm first, then pi-filter, finally CRT CONN.

C

RT_R

RT_G

C

12

C5501

C5501 SC8P250 V2CC-GP

SC8P250 V2CC-GP

5V_RUN

+

RT_R

C

RT_G

CRT_B

AFTP550 2AFTP5502

+5V_CRT _RUN

1

DDC_DAT A_CON

1

DDC_CLK _CON

1

CRT_R

1

CRT_G

1

CRT_B

1

JVGA_HS

1

JVGA_VS

1

A00-0104-1 change CRT1 from 20.20431.015 to 20.20401.015

C

RT1

6

1

6 1

7 2 8 3 9 4

10

5

1

17

1

D

DC_DATA _CON

12

JVGA_HS

13

JVGA_VS

14

DDC_CLK _CON

15

VIDEO-15-127 -GP-U

C5502

1ST: 20.20401 .015 2ND: 20.20479.015

DW

07/14 Change

1.Change CRT1 CONN PN from

20.20431.015 to 20.20401.01 5 base on ME emm files.

C5502 SC33P50 V2JN-3GP

SC33P50 V2JN-3GP

12

DY

C5504

C5504 SC33P50 V2JN-3GP

SC33P50 V2JN-3GP

JVGA_HS [7 4]

JVGA_VS [74]

Close PCH Close GPU

B B

GMCH_DD CDATA[20] GMCH_DD CCLK[20]

+3.3V_RU N +3.3V_RU N_GPU

1

23

RN5510

RN5510 SRN2K2J -1-GP

SRN2K2J -1-GP

4

CRT_DAT _DDC[81] CRT_CLK _DDC[81]

RN5511

RN5511 SRN2K2J -1-GP

SRN2K2J -1-GP

23

UMA/DIS CRT DDC CLK/DAT select circuit

+3.3V_RU N

U5542

DDC_DAT A_CON2

CRT_DAT _DDC[81]

GMCH_DD CDATA[20 ]

EDID_SELE CT#[21,54]

A A

CRT_CLK _DDC[81]

GMCH_DD CCLK[20]

H=>B1 -iGPU PCH (UMA) L=>B0 -dGPU GPU (DIS)

5

EDID_SELE CT#

B03A

2

GND

1

B1

NC7SB31 57P6X-1GP

B03A

2

GND

1

B1

NC7SB31 57P6X-1GP

VCC

S

U5543

S

4 5

EDID_SELE CT#

6

+3.3V_RU N

DDC_CLK _CON2

4 5

EDID_SELE CT#

6

DW

07/07 Change

1.Change CRT DDC CLK/DAT Circ uit

1

4

DDC_DAT A_CON2

DDC_CLK _CON2

4

Q5517

34

2

5

1

6

DMN66D0 LDW-7-GP

C5519

SC22P50 V2JN-4GP

C5519

+3.3V_RU N

DDC_DAT A_CON

DDC_CLK _CON

RN5513

RN5513 SRN2K2J -1-GP

SRN2K2J -1-GP

DDC_DAT A_CON DDC_CLK _CON

12

DY

5V @ CRT side

3

+5V_CRT _RUN

1

23

4

12

C5520

C5520 SC10P50 V2JN-4GP

SC10P50 V2JN-4GP

A00-1218-1 change C5520 from 22p to 10p by EMI

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CRT Connector

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

CRT Connector

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

55 88Wedn esday, January 13, 2010

1

A00

5

D D

4

3

2

1

C C

(Blank)

B B

A A

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

HDMI Connector

57 88Wednesday, January 13, 2010

1

A00

5

D D

4

3

2

1

SSID = Thermal

C C

AFTP580 3AFTP5803

AFTP580 2AFTP5802

*Layout* 25 mil

B B

EMC2102 _FAN_TACH_1[39 ]

EMC2102 _FAN_DRIVE[39]

EMC2102 _FAN_TACH_1

1

EMC2102 _FAN_DRIVE

1

EMC2102 _FAN_TACH_1

EMC2102 _FAN_DRIVE

12

C5801

C5801 SC22U6D 3V5MX-2GP

SC22U6D 3V5MX-2GP

Fan Connector

5 3 2

1 4

1ST: 20.D0210.10 3 2ND: 20.F0714.003

KA

D5801

D5801 SDMK034 0L-7-F-GP

SDMK034 0L-7-F-GP

AFTP580 1AFTP5801

1

FAN1

FOX-CON3 -6-GP-U

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

FAN

1

58 88Wedn esday, January 13, 2010

A00

S

SID = SATA

S

ATA HDD Connector

H

DD1

2

3

1

S

2

S

ATA_ITXN0 _HRXN0[24 ]

S

ATA_IRXN0 _HTXN0_C[24]

ATA_IRXN0 _HTXN0

S

1 2

C5913

C5913 SCD01U2 5V2KX-3GP

SCD01U2 5V2KX-3GP

+3.3V_RU N

+5V_RUN

3

S

S7

P2

P4

P6

P8

P10

P12

P14

SKT-SATA 7P+15P-24-GP-U

4

5

S6

P1

P3

P5

P7

P9

P11

P13

P15 24

S

ATA_IRXP0 _HTXP0

+3.3V_RU N

+5V_RUN

FFS_INT2

12

C5914

C5914 SCD01U2 5V2KX-3GP

SCD01U2 5V2KX-3GP

Close to CONN

1ST: 22.10300 .451 2ND:

5V power pin

+5V_RUN +3 .3V_RUN

S

ATA_ITXP0 _HRXP0 [24]

SATA_IRXP 0_HTXP0_C [24]

FFS_INT2 [40]

Close to CONN

3.3V power pin

ATA HDD Interface comment ****************************** S1:GND S2:RX+ S3:RXS4:GND S5:TXS6:TX+ S7:GND ****************************** P1------------ 3.3V P2------------ 3.3V P3------------ 3.3V P4:GND P5:GND / Dell Detected Pin P6:GND P7------------ 5V P8------------ 5V P9------------ 5V P10--- GND P11:Dell: FFS_INT for supported HDD P12:GND P13------------ 12V P14------------ 12V P15------------ 12V ******************************

SSID = SATA

ODD Connector

SATA_ITXP 1_ORXP1[24] SATA_ITXN 1_ORXN1[24]

SATA_IRXN 1_OTXN1_C[24]

SATA_IRXP 1_OTXP1_C[24]

SATA_RX- and SATA_RX+ Trace Length match within 20 mil

C5911 SCD 01U25V2KX-3GPC5911 SCD 01U25V2KX-3GP C5912 SCD 01U25V2KX-3GPC5912 SCD 01U25V2KX-3GP

12

C5903

SC10U6D3V5MX-3GP

12 12

+5V_RUN

C5915

SC10U6D 3V5MX-3GP

C5915

12

C5907

SCD1U10V2KX-5GP

12

DY

SATA_IRXN 1_OTXN1 SATA_IRXP 1_OTXP1

12

C5908

C5908 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

12

C5901

C5902

DY

SCD1U10V2KX-5GP

SC10U6D3V5MX-3GP

ODD1

S1

GND

S2

A+

S3

A-

S4

GND

S5

B-

S6

B+

S7

GND

P1

DP

P2

+5V

P3

+5V

P4

MD

P5

GND

P6

GND

7

GND

8

GND

NP1

NP2

SKT-SATA 7P+6P-38-GP-U

1ST: 62.10065 .531 2ND: 62.10065.D21

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

HDD/ODD Connector

59 88Wedn esday, January 13, 2010

A00

5

4

3

2

1

SID = AUDIO

S

A

FTP6004AFTP6004

A

FTP6002AFTP6002

peaker Connector

S

D D

00-0104-1

AUD_SPK _L-[30]

AUD_SPK _L+[30]

C C

AUD_SPK _L-

AUD_SPK _L+

12

DY

EC6003

MLVG0402220NV05-GP

12

DY

EC6008

MLVG0402220NV05-GP

A

R6006

1 2

0R0603-P AD-2-GP

0R0603-P AD-2-GP R6007

R6007

1 2

0R0603-P AD-2-GP

c

heck cable pin define

AUD_SPK _L-_C

AUD_SPK _L+_C

1ST: 20.F0693.0 02 2ND: 20.F1165.002

A

UD_SPK_ L-_C

1

A

UD_SPK_ L+_C

1

AFTP600 5AFTP6005

S

PK1

3

1

2

4

MLX-CON2 -7-GP-U

1

SID = AUDIO

S

M

IC IN

A

UD_VREF OUT_B[30]

AUD_EXT _MIC_L[30]

AUD_EXT _MIC_R[30]

1 2

C6014 SC1U25V5KX-1G PC6014 SC1U25 V5KX-1GP

1 2

C6015 SC1U25V5KX-1G PC6015 SC1U25 V5KX-1GP

SB-02

12

6003

R

R 4K7R2J-2 -GP

4K7R2J-2 -GP

A

UD_VREF OUT_B

12

C

6001

12

6004

R

R 4K7R2J-2 -GP

4K7R2J-2 -GP

MIC_IN_L_2

L6002 BLM18BD60 1SN1D-GPL6002 BLM18BD60 1SN1D-GP

MIC_IN_R_2

L6003 BLM18BD60 1SN1D-GPL6003 BLM18BD60 1SN1D-GP

6001

SC1U6D3 V2KX-GP

E

1 2

600ohm 100MHz 200mA 0.5ohm DC

XT_MIC_JD #[30]

XT_MIC_JD #

E

MIC_IN_L_C

MIC_IN_R_C

12

EC6001

EC6001 SC100P5 0V2JN-3GP

SC100P5 0V2JN-3GP

SC-1207-1 pop EC6001 and E C6002 for EMI

12

EC6002

EC6002 SC100P5 0V2JN-3GP

SC100P5 0V2JN-3GP

AFTP600 9AFTP6009 AFTP602 0AFTP6020 AFTP601 8AFTP6018 AFTP601 9AFTP6019

1 1 1 1

1ST: 22.10265 .301 2ND:

LIN1

6 1 2 3 4 5

AUDIO-JK18 6-GP

EXT_MIC_J D# GND MIC_IN_L_C MIC_IN_R_C

Delete Audio De-pop Circuit 2009/07/24

SSID = AUDIO

Head Phone

AUD_HP1 _JD#[3 0]

AUD_HP1 _JACK_L[30]

B B

AUD_HP1 _JACK_R[30]

2009/06/03

AUD_HP1 _JD#

AUD_HP1 _JACK_L AUD_HP1 _JACK_R

C6002

SC1000P 50V3JN-GP-U

C6002

1ST: 22.10265 .301 2ND:

LOUT1

6

L6004

1 2

L6001

1 2

600ohm 100MHz

12

200mA 0.5ohm DC

12

C6003

C6003 SC1000P 50V3JN-GP-U

SC1000P 50V3JN-GP-U

BLM18BD 601SN1D-GP

BLM18BD 601SN1D-GP BLM18BD 601SN1D-GP

BLM18BD 601SN1D-GP

AUD_HP_ JACK_L_1

AUD_HP_ JACK_R_1

12

EC6004

EC6004 SCD01U1 6V2KX-3GP

SCD01U1 6V2KX-3GP

12

EC6005

EC6005 SCD01U1 6V2KX-3GP

SCD01U1 6V2KX-3GP

1 2 3 4 5

AUDIO-JK18 6-GP

SC-1208-1 change EC6004,EC 6005 from 0.1U to 0.01U

AFTP601 4AFTP6014 AFTP601 7AFTP6017 AFTP601 5AFTP6015 AFTP601 6AFTP6016

AUD_HP1 _JD#

1

GND

1

AUD_HP_ JACK_L_1

1

AUD_HP_ JACK_R_1

1

Added HP circuit 2009/05/26

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

SPEAKER/MIC/AUDIO JACK

Size Document N umber Rev

Date: Sheet of

SPEAKER/MIC/AUDIO JACK

A3

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

60 88Wedn esday, January 13, 2010

1

A00

5

4

3

2

1

S

SID = Flash.ROM

D D

S

SID = RBATT

SPI FLASH ROM (2M bits) for KBC

RN6201

RN6201 SRN100K J-6-GP

SRN100K J-6-GP

KBC_PW R

C C

EC_SPI_CS #[37]

EC_SPI_DI[37]

EC_SPI_W P#_R[37]

4

R6205 0R2J-2-GPR 6205 0R2J-2-G P

1 2

R6204 0R2J-2-GPR 6204 0R2J-2-G P

1 2

12

EC6202

SC4D7P5 0V2CN-1GP

1 23

EC_SPI_CS # EC_SPI_HO LD#

+3.3V_RT C_LDO

12

R6201

100KR2J -1-GP

EC_SPI_CS # SPI_DO EC_SPI_W P#

12

DY

C6201

C6201 SC4D7U1 0V3KX-GP

SC4D7U1 0V3KX-GP

U6203

1

CS#

2 3

1st 72.25021.001 2nd 72.25205.B01

VCC

SO

HOLD#

WP#

SCK

GND4SI

AT25DF0 21-SSH-T-GP

KBC_PW R

12

C6203

C6203 SCD1U16 V2KX-3GP

SCD1U16 V2KX-3GP

KBC_PW R

8

EC_SPI_HO LD#

7 6

SPI_DIO

5

12

EC6201

SC4D7P5 0V2CN-1GP

C6204

C6204 SCD1U16 V2KX-3GP

SCD1U16 V2KX-3GP

12

EC6203

EC6203 SC4D7P5 0V2CN-1GP

SC4D7P5 0V2CN-1GP

EC_SPI_CL K [37] SPI_DIO [37]

RTC Connector

+RTC_CE LL

12

C6202

C6202 SC1U10V 3KX-3GP

SC1U10V 3KX-3GP

1st 83.BAT54.B81 2nd 83.BAT54.A81

D6201

3

BAT54CW -1-GP

+3.3V_RT C_LDO

1

RTC_PW R

2

Width=20mils

R6202

1 2

1KR2J-1-G P

A00-0104-1 change RCT1 from 20.D0210.102 to 20. D0075.102

+RTC_VC C

AFTP620 2AFTP6202

AFTP620 1AFTP6201

1

RTC1

3 1

2 4

FOX-CON2 -7-GP

1st 20.D0075.102 2nd 20.F0714.002

+RTC_VC C

1

B B

SPI FLASH ROM (32M bits) for PCH

RN6202

RN6202 SRN4K7J -8-GP

SRN4K7J -8-GP

+3.3V_RU N

SC-1208-1 change R6206 fro m 15ohm to 0 oh m

PCH_SPI_C S0#[24]

PCH_SPI_D I[24]

A A

5

1 2 3

1 2

R6206

R6206 0R2J-2-GP

0R2J-2-GP

12

DY

EC6205

EC6205 SC4D7P5 0V2CN-1GP

SC4D7P5 0V2CN-1GP

4

+3.3V_RU N

R6207

R6207 4K7R2J-2 -GP

4K7R2J-2 -GP

PCH_SPI_D I_R PCH_SPI_W P#

PCH_SPI_W P# PCH_SPI_H OLD_0#

12

1

CS#

2

SO

3

WP#

4

GND

AT25DF3 21-SU-GP

1st 72.25321.001 2nd 72.25325.A01

U6202

VCC

HOLD#

SCK

8 7 6 5

SI

+3.3V_RU N

DY

C6205

C6205 SC4D7U1 0V3KX-GP

SC4D7U1 0V3KX-GP

+3.3V_RU N

PCH_SPI_H OLD_0#

12

DY

EC6204

EC6204 SC4D7P5 0V2CN-1GP

SC4D7P5 0V2CN-1GP

4

12

DY

C6206

C6206 SCD1U16 V2KX-3GP

SCD1U16 V2KX-3GP

12

EC6206

EC6206 SC4D7P5 0V2CN-1GP

SC4D7P5 0V2CN-1GP

PCH_SPI_C LK [24] PCH_SPI_D O [24]

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

EEPROM/RTC Connector

Size Document N umber Rev

A3

Date: Sheet of

3

2

Date: Sheet of

EEPROM/RTC Connector

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

62 88Wedn esday, January 13, 2010

1

A00

5

SID = USB

S

SB & ESATA Power SW

U

SB_OC#0 _1 [21,2 2]

5V_ALW

+

12

C

6302

D D

C C

6302

SCD1U50V 3KX-GP

SC-1207-1 change C6302 to D1U for EMI

a

t least 80 mil at least 80 mil

SB_PW R_EN#[37,76]

U

6303

U

1

G

O

ND

C1#

2

N

UT1

I

O

3

N1#

UT2

E

O

4

N2#

C2#

E

O

TPS2062A D-GP

1ST: 74.02062.B71 2ND: 74.00546.07D

8 7 6 5

5V_USB1

+

12

S

C-1207-1

pop R6307 for EMI

SSID = ESATA

4

B-1021

S

1. pop and change TR6304 to 90 ohm for EMI; DY R6302, R6308

12

R6307

100KR2J-1-GP

SCD1U10V2KX-4GP

TC6303

SC1U10V3KX-3GP

ST100U6D3VBML1GP

12

C6305

C6306

R6307

SB_PN0[21]

U

1ST: 68.00201.141 2ND: 68.02012.201

DLW21 HN900SQ2LG P-U

TR6304

USB_PP0[21]

A00-0106-1 remove R6302, R6308 for no co-lay after XB

3

SB_P0-

1

4

U

2

3

USB_P0+

Remove ESD diode, confirmed with EMI

2

5V_USB1

+

U

SB_P0-

USB_P0+

AFTP6317AFTP6317 AFTP6316AFTP6316 AFTP6321AFTP6321 AFTP6320AFTP6320

U

SB1

7 5 1

2 3 4 6 8

SKT-USB-257 -GP-U

1ST: 22.10321.001 2ND: 22.10321.181

USB_P0-

1

USB_P0+

1

+5V_USB1

1

GND

1

A00

R6301

ESATA Power

USB_PN1[21]

R6301

1 2

0R0603-P AD-2-GP

USB_P1-

Share one power SW with USB port 1

R6306

USB_PP1[21]

+3.3V_RUN+3.3V_RUN +3.3V_RUN

ASM

DY

R6318

R6318 0R2J-2-GP

0R2J-2-GP R6319

R6319 0R2J-2-GP

0R2J-2-GP

ASM

CAPS CLOSE TO ESATA1

ESATA_ITX_ DRX_PU_R

ESATA_ITX_ DRX_NU_R

1 2

C6311

C6311 SCD01U50 V2KX-1GP

SCD01U50 V2KX-1GP C6312

C6312 SCD01U50 V2KX-1GP

SCD01U50 V2KX-1GP C6313

C6313

DY

SCD01U16 V2KX-3GP

DY

C6314

C6314 SCD01U16 V2KX-3GP

SCD01U16 V2KX-3GP

ESATA_ITX_ DRX_PU_C

ESATA_ITX_ DRX_NU_C

ESATA_IRX _DTX_P4_C [24]

ESATA_IRX _DTX_N4_C [24]

12

DY

B B

DY

12

DY

ESATA_ITX_D RX_P4[24]

ESATA_ITX_D RX_N4[2 4]

ESATA_IRX _DTX_PU_L

ESATA_IRX _DTX_NU_L

R6314

R6314 4K7R2F-GP

4K7R2F-GP

DY

12

R6316

R6316 0R2J-2-GP

0R2J-2-GP

DY

C6315

SCD01U50 V2KX-1GP

C6316

SCD01U50 V2KX-1GP

R6315

R6315 4K7R2F-GP

4K7R2F-GP

R6317

R6317 0R2J-2-GP

0R2J-2-GP

12

D0 D1

1 2

DY

C6309 SCD01U5 0V2KX-1GP

1 2

DY

C6310 SCD01U5 0V2KX-1GP

ESATA_IRX _DTX_P4_L

ESATA_IRX _DTX_N4_L

CAPS CLOSE TO ESATA1

A A

12

C6317

DY

SCD1U10V2KX-4GP

ESATA_ITX_ DRX_P4_R

ESATA_ITX_ DRX_N4_R

1 2

DY

R6320 0R2J-2-GP

1 2

DY

R6321 0R2J-2-GP

C6318

12

DY

SC1U10V3KX-3GP

+3.3V_RUN

C6319

SCD01U50V2KX-1GP

RN6301

RN6301 0R4P2R-PA D

0R4P2R-PA D

ESATA_IRX _DTX_P4 ESATA_IRX _DTX_N4

D0 D1

RN6302

RN6302 0R4P2R-PA D

0R4P2R-PA D

2 3 1

12

DY

10R2J-2-GP

U6301

VCC6EN

10

VCC

20

VCC

16

VCC

1

RX_0P

2

RX_0N

DY

11

RX_1P RX_1N12GND

9

D0

8

D1

SN75LVCP 412RTJR-GP

RN

A00-0104-1

4

RN

U6301_RE PEATER_EN

R6313

7

15

TX_0P

14

TX_0N

5

TX_1P

4

TX_1N

3

GND

13 17

GND

18

GND

19

GND

21

GND

1234

ESATA_ITX_ DRX_PU_L

ESATA_ITX_ DRX_NU_L

ESATA_IRX _DTX_P4_C_L

ESATA_IRX _DTX_N4_C_L

1 2

DY

1 2

DY

1 2

0R0603-P AD-2-GP

A00-0106-1 remove TR6301 for no co-lay after XB

A00-0104-1

5

4

3

Remove ESD diode, confirmed with EMI

USB_P1+

R6304

2

R6304

1 2

0R0603-P AD-2-GP

R6310

1 2

0R0603-P AD-2-GP

R6311

1 2

0R0603-P AD-2-GP

R6312

1 2

0R0603-P AD-2-GP

ESATA_ITX_ DRX_PU_C

ESATA_ITX_ DRX_NU_C

ESATA_IRX _DTX_PU_L

ESATA_IRX _DTX_NU_L

A00-0106-1 remove TR6302, TR6303 for no co-lay after XB

ESATA_ITX_ DRX_PU

ESATA_ITX_ DRX_NU

ESATA_IRX _DTX_PU

ESATA_IRX _DTX_NU

+5V_USB1

ESATA_ITX_ DRX_PU ESATA_ITX_ DRX_NU

ESATA_IRX _DTX_PU ESATA_IRX _DTX_NU

USB_P1+ USB_P1-

AFTP6308AFTP6308 AFTP6309AFTP6309 AFTP6302AFTP6302

1st Samsu ng

Title

Size Document Numb er Rev

Custom

Date: Sheet of

ESATA1

1

VBUS

GND

6

GND

A+ A-7GND

GND

10

B+

GND

9

GND

B-

GND

3

GND

D+

2

D-

SKT-USB-ESA TA-1-GP

1ST: 22.10321.F71 2ND:

+5V_USB1

1

USB_P1-

1

USB_P1+

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

USB/ESATA Port

Winery13 MB DIS

1

4 5 8

AFTP6306AFTP6306

11

1

12 13 14 15

63 88Wednesday, J anuary 13, 2010

A00

5

SID = Wireless

S

D D

4

3

2

1

Mini Card Connector(802.11a/b/g/n)

+1.5V_RU N

WLAN 1

53

+5V_ALW

C C

SCD1U16 V2KX-3GP

12

DY

B B

12

C6401

DY

+3.3V_RU N +1.5V_RU N

12

6405

6405 C

C

6402

DY

C

SC10U6D3V5MX-3GP

SCD1U16V2KX-3GP

DY

WLAN _ACT

12

+3.3V_RU N

12

C6403

C6403 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

12

C6406

C6406 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

C6404

SC10U6D3V5MX-3GP

12

EC6401

EC6401 SC220P5 0V2KX-3GP

SC220P5 0V2KX-3GP

E51_RXD[37] E51_TXD[37]

AFTP640 2AFTP6402 AFTP640 3AFTP6403

MINI1_CLKREQ #[23 ]

CLK_PCIE_ MINI1#[2 3] CLK_PCIE_ MINI1[23]

R6404 0R2J-2-GP

1 2

R6403 0R2J-2-GP

1 2

PCIE_IRXN2_M TXN2[23] PCIE_IRXP2_M TXP2[23 ]

PCIE_ITXN2_M RXN2[23] PCIE_ITXP2_M RXP2[23 ]

+5V_ALW

1 2

E51_RXD

1

E51_TXD

1

WLAN _ACT[7 3]

BT_ACT[73]

DY

DY DY

DY

+3.3V_RU N

R6402

DY

0R3J-0-U-G P

E51_RXD _R E51_TXD _R

+5V_MINI_DEB UG

1

3 5 7

9 11 13 15

17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

54

NP1 2

4 6 8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 NP2

SKT-MINI52P-41 -GP

SB-09

1ST: 62.10043 .841 2ND: 20.F1519.052

+3.3V_RU N

PLT_RST #

PCH_SMB CLK PCH_SMB DATA

USB_P4USB_P4+

WIFI_RF_ EN [37]

PLT_RST # [9,21 ,34,36,37,70,76,80]

+3.3V_RU N

PCH_SMB CLK [7,1 8,19,23,40,76]

PCH_SMB DATA [7,1 8,19,23,40,76]

LED_W LAN_WIMAX_ OUT# [66 ,76]

R6406

USB_P4-

USB_P4+

A00-0107-1 remove L6401 for no co-lay after XB

R6406

1 2

0R0603-P AD-2-GP

R6405

1 2

0R0603-P AD-2-GP

USB_PN4 [21]

USB_PP4 [21]

SB-28

+3.3V_RU N

R6407

R6407 1KR2J-1-G P

SW1

1ST: 62.40083 .001 2ND: 62.40018.441

SW-SL IDE67-GP

ON OFF

A A

1 2 3

SW-SL IDE67-GP

TP6404

NP1

1

WIRELE SS_ON#/OFF_R

2 3 NP2

TPAD14-G P

R6408

1 2

10R2J-2-G P

1KR2J-1-G P

1 2

12

C6407

C6407 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

WIRELE SS_ON#/OFF [37]

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

TP6405

TPAD14-G P

5

4

WIRELE SS_ON#/OFF_R

1

3

Title

MINICARD(WLAN)/ITP CONN

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

MINICARD(WLAN)/ITP CONN

A3

Winery13 MB DIS

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

64 88Wedn esday, January 13, 2010

1

A00

5

D D

C C

4

3

2

1

(Blank)

B B

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

WWAN Connector

Size Document N umber Rev

A3

Date: Sheet of

WWAN Connector

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

65 88Wedn esday, January 13, 2010

1

A00

5

SID = LED

S

D D

4

3

2

1

PWR BTN LED

PWR_BTN _LED_R#PWR _BTN_LED#

For LED & Capacity board:

LED Type Color Power rail

BATTERY LED1

SCRL LED

CAP LED

NUM LED

Amber(Multi-color)

White

White ALWPWR BTN LED

SATA ACT LED1

C C

BT ACT LED

WLAN/WWAN ACT LED

White

ALW

RUN

PWR_BTN _LED#[37]

SCRLK LED

SCR_LOCK_LE D#[37]

CAPS LED

CAP_LOCK_LED #[37 ]

NUM LED

NUM_LOCK_LED #[37]

Bluetooth LED

BT_ACTIVE_K#[73]

SCR_LOCK_LE D#

CAP_LOCK_LED #

NUM_LOCK_LED #

BT_ACTIVE_K#

12

R6628 20KR2J-L2- GPR6628 20K R2J-L2-GP

SCRL_LED_R #

12

R6620 20KR2J-L2- GPR6620 20K R2J-L2-GP

CAP_LED_R#

12

R6621 20KR2J-L2- GPR6621 20K R2J-L2-GP

NUM_LED_R#

12

R6622 20KR2J-L2- GPR6622 20K R2J-L2-GP

12

R6623 20KR2J-L2- GPR6623 20K R2J-L2-GP

LED_BT_ACT_ K_R#

PWR_BTN _LED_R# [78]

SCRL_LED_R # [78]

CAP_LED_R# [78]

NUM_LED_R# [78]

LED_BT_ACT_ K_R# [78]

BAT_O_LED_R

BAT_W_LED _R

POWER_LE D_R#

SATA_ACT_C #

SB-1024

Orange

Q6607

R1

B

R2

PDTC124EU- 1-GP

1ST: 84.00124.H1K 2ND: 84.00124.S1K

White

Q6609

R1

B

R2

PDTC124EU- 1-GP

1ST: 84.00124.H1K 2ND: 84.00124.S1K

white

Q6608

B

R1

DDTA143ECA -7-F-GP

1ST: 84.00143.K11 2ND:

white

Q6606

B

R1

DDTA143ECA -7-F-GP

1ST: 84.00143.K11 2ND:

12

R6634 20KR2J-L2- GPR6634 20K R2J-L2-GP

R6617

A00-0104-1

R6617

1 2

0R0402-PAD-2- GP

R6629

1 2

0R0402-PAD-2- GP

R6619

1 2

0R0402-PAD-2- GP

R6626

1 2

0R2J-2-GP

BAT_O_LED BATT_LED_ORAN GE

C

E

BAT_W_LED BATT_LED_W HITE

C

E

+5V_ALW

R2

E

POWER_LE D_L PWR2_LED

C

SB-01

+5V_RUN

R2

E

HDD_LED

C

4

WLAN_W IMAX_LED_R# [78]

A00-0104-1

SATA1_ACT_LED

For LED&Capacity board:

SATA1_ACT_LED [78]

For LED & Capacity board

3

LED Location from left to right

BATTERYPOWER

R6611

BATT_LED_OR ANGE

PWR2_LED

1 2

330R2J-3-GP

R6612

1 2

560R2J-3-GP

R6608

1 2

330R2J-3-GP

SCD1U10V2KX- 4GP

BATT_LED_OR ANGE_R

BATT_LED_W HITE_RBATT_LED_W HITE

12

DY

EC6609

SCD1U10V2KX-4GP

PWR2_LED _R

EC6607

Remove HDD LED

+5V_ALW

LED6601

2

3

LED-OW -3-GP

12

DY

EC6610

12

DY

2

SB-03

SCD1U10V2KX-4GP

LED6602

3

A K

1 2

LED-Y-74-GP

BATTERY

1

Pin1(+) and Pin2(-)= orange Pin1(+) and Pin3(-)= white

1ST: 83.00326.G70 2ND: 83.01222.K70

BREATH POWER LED

white

1ST: 83.00110.J70 2ND: 83.01221.R70

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

LED

Winery13 MB DIS

1

66 88Wednesd ay, January 13, 2010

A00

WWAN LED

LED_WW AN_OUT#[64,76]

WLAN WIMAX_LED

LED_WLAN _WIMAX_OUT#[64 ,76]

B B

R6630

BATT_ORAN GE_LED[37]

BATT_WH ITE_LED[37]

PWRLED #[37]

A A

SATA_LED#[24]

5

1 2

0R0402-PAD-2- GP

1 2

0R0402-PAD-2- GP

R6631

R6631 20KR2J-L2-GP

20KR2J-L2-GP

1 2

HD LED

R6632

R6625

1 2

20KR2J-L2-GP

SID = KBC

S

5

4

3

S

SID = Touch.Pad

2

1

Internal KeyBoard Connector

D D

C C

K

B1

1

3

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

32

ACES-CON30-3-GP

1ST: 20.K0421.030 2ND: 20.K0259.030

K

B_DET#

KROW7 KROW6 KROW4 KROW2 KROW5 KROW1 KROW3 KROW0 KCOL5 KCOL4 KCOL7 KCOL6 KCOL8 KCOL3 KCOL1 KCOL2 KCOL0 KCOL12 KCOL16 KCOL15 KCOL13 KCOL14 KCOL9 KCOL11 KCOL10

A

FTP6862AFTP6862

1

K

AFTP6837AFTP6837

1

AFTP6836AFTP6836

1

AFTP6839AFTP6839

1

AFTP6838AFTP6838

1

AFTP6841AFTP6841

1

AFTP6840AFTP6840

1

AFTP6842AFTP6842

1

AFTP6843AFTP6843

1

AFTP6844AFTP6844

1

AFTP6845AFTP6845

1

AFTP6847AFTP6847

1

AFTP6846AFTP6846

1

AFTP6849AFTP6849

1

AFTP6848AFTP6848

1

AFTP6851AFTP6851

1

AFTP6850AFTP6850

1

AFTP6853AFTP6853

1

AFTP6852AFTP6852

1

AFTP6855AFTP6855

1

AFTP6854AFTP6854

1

AFTP6857AFTP6857

1

AFTP6856AFTP6856

1

AFTP6859AFTP6859

1

AFTP6858AFTP6858

1

AFTP6860AFTP6860

1

B_DET# [25]

KROW[0..7] [37]

KCOL[0..16] [37]

TPCLK[37]

TPDATA[37]

SC33P50V2JN-3GP

AFTP6815AFTP6815 AFTP6816AFTP6816 AFTP6817AFTP6817

C6804

+

1 1 1

5V_RUN

1

23

4

12

+5V_RUN TPCLK TPDATA

SCD1U10V2KX-5GP

RN6802

RN6802 SRN10KJ-5-GP

SRN10KJ-5-GP

C6806

C6806 SC33P50V2JN-3GP

SC33P50V2JN-3GP

+

5V_RUN

12

C6805

+5V_RUN

EC6805 SCD1U25V2ZY-1GP

TPCLK

EC6806 SCD1U25V2ZY-1GP

TPDATA

EC6807 SCD1U25V2ZY-1GP

TouchPad Connector

5

1

2 3 4

1

6

ACES-CON4-10-GP-U

1ST: 20.K0320.004 2ND: 20.K0382.004

1 2

DY

1 2

DY

1 2

DY

AFTP6835AFTP6835

TPAD1

KB Backlight CONN

B B

+5V_RUN

R6815

R6815 1KR2J-1-GP

1KR2J-1-GP

1 2

KB_BL_DET#[37]

1 2

KB_BL_CTRL[37]

R6803

R6803 100KR2J-1-GP

100KR2J-1-GP

3 4

1ST: 84.06402.B3D 2ND: 84.03456.D3D

1 2

KB_BL_DET# KB_BL_CTRL# KB_BL_CTRL#

Q6808

D

D G

G

AO6402A-GP

6

D

5

S

KBBL1

5

1

CN7_P2

2 3 4

6

ACES-CON4-10-GP-U

SC-1208-1 change Change Q6808 to 84.06402.B3D

AFTP6833AFTP6833 AFTP6832AFTP6832 AFTP6834AFTP6834 AFTP6861AFTP6861

1ST: 20.K0320.004 2ND: 20.K0382.004

+5V_RUN

1

CN7_P2

1

KB_BL_DET#

1 1

C6812

SCD1U10V2KX-5GP

+5V_RUN +5V_RUN

12

DY

12

For EMI

A A

5

+5V_RUN

CN7_P2

KB_BL_DET#

KB_BL_CTRL#

EC6801 SCD1U25V2ZY-1GP

1 2

DY

EC6802 SCD1U25V2ZY-1GP

1 2

DY

EC6803 SCD1U25V2ZY-1GP

1 2

DY

EC6804 SCD1U25V2ZY-1GP

1 2

DY

C6895

C6895 SC4D7U10V5KX-1GP

SC4D7U10V5KX-1GP

Place near CON5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Keyboard/Touch Pad

Size Document Number Rev

Custom

Date: Sheet of

Keyboard/Touch Pad

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

68 88W ednesday, January 13, 2010

1

A00

5

S

SID = User.Interface

H

all Sensor Connector

4

3

2

1

D D

+

3.3V_ALW

DY R6903 2009/05/28

+3.3V_ALW

12

R6903

R6903 100KR2J-1-GP

100KR2J-1-GP

DY

LID_CLOSE#[37]

C C

LID_CLOSE# LID_CLOSE#_1

12

C6901

SCD047U10V2KX-2GP

1 2

R6901 10R2J-2-GPR6901 10R2J-2-GP

SCD1U10V2KX-5GP

C6902

12

HALL1

1

VDD

3

OUTPUT

EM-6781-T30-GP

VSS

2

1ST: 74.06781.07B 2ND: 74.09132.A7B

B B

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

Hall sensor

1

69 88W ednesday, January 13, 2010

A00

5

S

SID = DEBUG PORT

D D

4

3

2

1

GOLDEN FINGER FOR DEBUG BOARD

+3.3V_RUN

LPC_LAD0[24,36,37] LPC_LAD1[24,36,37]

C C

PLT_RST#[9,21,34,36,37,64,76,80]

G7001

GAP-OPEN

PLT_RST#_GAP

21

SB-1021 DY DBT1 and add G7001

LPC_LAD2[24,36,37] LPC_LAD3[24,36,37] LPC_LFRAME#[24,36,37]

PCLK_FWH[21]

DBT1

1 2 3 4 5 6

DY

7 8

9 10 11 12

MLX-CON10-7-GP

B B

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Debug port

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

70 88W ednesday, January 13, 2010

1

A00

5

D D

C C

4

3

2

1

(Blank)

B B

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

Braidwood

72 88W ednesday, January 13, 2010

1

A00

5

4

3

2

1

SSID = User.Interface

F

or EMI

amera Connector

D D

Camera Power

R7301

1 2

0R3J-0-U-G P

EC7304

SCD1U16 V2KX-3GP

C C

DY

+3.3V_CA MERA+3.3V_RUN

12

C7305

C7305 SC4D7U6 D3V3KX-GP

SC4D7U6 D3V3KX-GP

C

AMERA1

9

1

2 3 4 5 6 7 8

10

ACES-CON 8-3-GP-U

1ST: 20.F0779.0 08 2ND: 20.F1261.008

AFTP730 2AFTP7302 AFTP730 3AFTP7303 AFTP730 4AFTP7304 AFTP730 5AFTP7305 AFTP730 6AFTP7306

AUD_DMIC_ CLK_G

1

AUD_DMIC_ IN0_R

1

+3.3V_CA MERA

1

CAMERA_ USB1-

1

CAMERA_ USB1+

1

C

AUD_DMIC_ IN0_R

AUD_DMIC_ CLK_G

1

AFTP730 7AFTP7307

+3.3V_CA MERA

DY

MLVG0402220NV05-GP

CAMERA_ USB1+ CAMERA_ USB1-

R7300

12

EC7302

For ESD

MLVG0402220NV05-GP

DY

12

33R2J-2-G P

EC7303

AUD_DMIC_ IN0 [30]

AUD_DMIC_ CLK_G [30]

A00-0107-1 remove R7302, R7303 for no co-lay after XB

3

4

1

2

SC-1208-1 pop L7301 for EM I

U

L7301

L7301 DLW2 1HN900SQ2LGP -U

DLW2 1HN900SQ2LGP -U

1ST: 68.02012 .20G 2ND:

USB_PN1 1 [21]

SB_PP11 [21]

Bluetooth cable conn.

SSID = User.Interface

BLUETOO TH_DET#

WLAN _ACT

12

EC7306

SC220P50V2KX-3GP

USB_PP8 USB_PN8 BT_ACT BLUETOO TH_EN WLAN _ACT

R7308

10KR2J-3-GP

AFTP603 1AFTP6031 AFTP603 2AFTP6032 AFTP603 3AFTP6033 AFTP603 4AFTP6034 AFTP603 5AFTP6035 AFTP603 6AFTP6036 AFTP603 7AFTP6037 AFTP603 8AFTP6038

BLUETOO TH_DET#

1

WLAN _ACT

1

BLUETOO TH_EN

1

BT_LED

1

BT_ACT

1

+3.3V_RU N

1

USB_PP8

1

USB_PN8

1

USB_PP8[2 1]

USB_PN8[21]

B B

BT_ACT[64 ]

BLUETOO TH_EN[37]

WLAN _ACT[64]

Assign BT_DET# GPIO 2009/06/09

DY

12

DY

R7307

100KR2J-1-GP

BT LED control signal 2009/05/26

+5V_RUN

12

R7309

R7309 100KR2J -1-GP

A A

BT_ACTIVE _K#[66]

Remove R7301 2009/06/09

5

100KR2J -1-GP

BT_ACTIVE _K#

Q7302

MMBT390 4-7-F-GP

3

1

2

1ST: 84.03904 .H11 2ND: 84.03904.L06

BT_LED

4

BLUETOO TH_EN BT_LED

3

ACES-CON N14D-GP

BT1

15 NP1 2

1

4

3

6

5

8

7

10

9 11 13

1ST: 20.F1500.0 14 2ND: 20.F0987.014

12 14 NP2 16

Close to BT1

+3.3V_RU N

12

C7303

C7304

SC2D2U6D3V3KX-GP

BT_ACT

USB_PP8 USB_PN8

SCD1U10V2KX-4GP

1

SB-25

AFTP603 9AFTP6039

+3.3V_RU N

C7302

12

SC2D2U1 0V3KX-1GP

pin define check

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Camera CONN

Size Document N umber Rev

A3

Date: Sheet of

Camera CONN

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

73 88Wedn esday, January 13, 2010

1

A00

5

S

SID = VIDEO

D D

SB-1026 modify DGPU SEL circuit

C C

4

U

MA/DIS LVDS signal select circuit

V

GA_LVDSA_DAT2[81]

V

GA_LVDSA_DAT2#[81]

V

GA_LVDSA_DAT1[81] VGA_LVDSA_DAT1#[81] VGA_LVDSA_DAT0[81] VGA_LVDSA_DAT0#[81] VGA_LVDSA_CLK[81] VGA_LVDSA_CLK#[81]

MCH_LVDSA_DAT2[20] MCH_LVDSA_DAT2#[20] MCH_LVDSA_DAT1[20] MCH_LVDSA_DAT1#[20] MCH_LVDSA_DAT0[20] MCH_LVDSA_DAT0#[20] MCH_LVDSA_CLK[20] MCH_LVDSA_CLK#[20]

DGPU_1D8V_SEL#

H=>BTMDS -iGPU PCH (UMA) L=>ATMDS -dGPU GPU (DIS)

U

7411

38

A

TMDS2+

37

A

TMDS2-

36

A

TMDS1+

35

ATMDS1-

34

ATMDS0+

33

ATMDS0-

32

ATMDSCL K+

31

ATMDSCL K-

29

BTMDS2+

28

BTMDS2-

27

BTMDS1+

26

BTMDS1-

25

BTMDS0+

24

BTMDS0-

23

BTMDSCL K+

22

BTMDSCL K-

9

SEL

TS3DV421RUAR-GP

71.03412.B0G

3

TMDS2+

TMDS2-

TMDS1+

TMDS1-

TMDS0+

TMDS0-

TMDSCLK +

TMDSCLK -

GND

43

V V V VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS

2

+

1.8V_RUN

2

DD

8

DD

16

DD

18 20 30 40 42

3 4 6 7 11 12 14 15

1 5 10 13 17 19 21 39 41

12

C

7401

SCD1U10V2KX-4GP

VGA_TXAOUT2+ [54] VGA_TXAOUT2- [54] VGA_TXAOUT1+ [54] VGA_TXAOUT1- [54] VGA_TXAOUT0+ [54] VGA_TXAOUT0- [54] VGA_TXACLK+ [54] VGA_TXACLK- [54]

12

C

7403

SCD1U10V2KX-4GP

12

C

7404

SCD1U10V2KX-4GP

1

+5V_CRT_RUN

12

C7407

C7407 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

B B

A A

Q7410

DMN66D0LDW-7-GP

DGPU_SELECT#[21,37,54]

+3.3V_RUN

12

EC7401

DY

SCD1U25V2ZY-1GP

+3.3V_RUN

SB-1026 modify DGPU SEL circuit

12

R7485

R7485 20KR2F-L-GP

20KR2F-L-GP

GPU_SELECT D

1

2

34

5

6

DGPU_1D8V_SEL#

5

DGPU_SELECT# H=> -iGPU PCH (UMA) L=> -dGPU GPU (DIS)

+1.8V_RUN

12

UMA/DIS CRT Hsync/Vsync select circuit

Hsync & Vsync level shift

14

1

U7408A

U7408A SSAHCT125PWR-GP

SSAHCT125PWR-GP

2 3

7

VSYNC_5 HSYNC_5

U7408C

14

10

SSAHCT125PWR-GP

9 8

7

R7487

R7487 20KR2F-L-GP

20KR2F-L-GP

DGPU_SELECT

DGPU_SELECT#

GMCH_VSYNC[20]

VGA_VSYNC[81]

GMCH_HSYNC[20]

VGA_HSYNC[81]

+5V_CRT_RUN

DGPU_SELECT

DGPU_SELECT#

+5V_CRT_RUN

4

+5V_CRT_RUN

14

4

5 6

U7408B

7

SSAHCT125PWR-GP

+5V_CRT_RUN

14

13

12 11

7

U7408D

U7408D SSAHCT125PWR-GP

SSAHCT125PWR-GP

VSYNC_5

RN7445

1 2 3

SRN33J-5-GP-U

HSYNC_5

UMA/DIS CRT signal select circuit

C7408

C7408 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

VGA_BLUE[81]

MCH_BLUE[20]

VGA_GREEN[81]

MCH_GREEN[20]

VGA_RED[81]

MCH_RED[20]

4

JVGA_VS [55] JVGA_HS [55]

3

12

DGPU_SELECT#

+5V_CRT_RUN

16

1 2 3 5

6 11 10 14 13

8

2ND = 73.03257.C0B

U7435

VCC S

YA IA0 IA1

YB IB0 IB1

YC IC0 IC1

YD ID0 ID1

OE#

GND

PI5C3257QE-GP

2

4

7

9

12

15

M_BLUE [55]

M_GREEN [55]

M_RED [55]

H=>IA1 -iGPU PCH (UMA) L=>IA0 -dGPU GPU (DIS)

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

PX Swith-1

1

74 88W ednesday, January 13, 2010

A00

5

D

D D

C_IN baord CON

4

P

lease reoute 300 mil at least.

3

+

DC_IN : 19.5V/85W +3.3V_RUN : 3300mA +5V_ALW : 1000mA +1.5V_RUN : 500mA +3.3V_ALW : 58mA

+

DC_IN

12

C

7620

SC4D7U25V5MX-1DLGP

D

Y

2

P

lace near BTB1

1

BTB1

52

LAN CLK

LAN PCIE

USB PORT2

C C

CLK_PCIE_LAN#[23] CLK_PCIE_LAN[23]

PCIE_ITXN3_LRXN3[23] PCIE_ITXP3_LRXP3[23]

PCIE_IRXN3_LRTXN3[23]

PCIE_IRXP3_LRTXP3[23]

USB_PP2[21] USB_PN2[21]

USB_PWR_EN#[37,63]

CLKREQ#_LAN[23]

PM_LAN_ENABLE[37]

GPO_DSM[23,24]

PS_ID_R2[43]

+3.3V_RUN

+1.5V_RUN

+3.3V_ALW

49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11

9 7 5 3

1

NP1

51

ACES-CONN50A-2-GP

Remove AFTP test point

NP2

50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4

2

1ST: 20.F1631.050 2ND:

PCIE_ITXP4_MRXP4 [23] PCIE_ITXN4_MRXN4 [23]

PCIE_IRXP4_MTXP4 [23]

PCIE_IRXN4_MTXN4 [23]

CLK_PCIE_MINI2# [23]

CLK_PCIE_MINI2 [23]

USB_PP5 [21]

USB_PN5 [21]

MINI2_CLKREQ_R# [23]USB_OC#2_3[21] PCH_SMBDATA [7,18,19,23,40,64] PCH_SMBCLK [7,18,19,23,40,64]

LED_WWAN_OUT# [64,66]

WWAN_RF_EN [21]

PLT_RST# [9,21,34,36,37,64,70,80] PCIE_WAKE# [22,34]

+DC_IN+5V_ALW

WWAN PCIE

WWAN CLK

WWAN USB

WWAN SMBUS

Confirmed with AFTE.

B B

+DC_IN

12

C7621

C7621 SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

+3.3V_RUN

12

C7601

DY

SC4D7U25V5KX-GP

+3.3V_RUN

12

C7602

C7602 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+5V_ALW

12

C7614

C7614 SC1P50V2CN-1GP

SC1P50V2CN-1GP

+5V_ALW

12

C7615

C7615 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+1.5V_RUN

SC-1130 pop C7614 for RF

12

C7618

C7618 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+3.3V_ALW

12

C7619

C7619 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

DC_IN Board BTB Connector

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

76 88W ednesday, January 13, 2010

1

A00

5

D D

C C

4

3

2

1

(Blank)

B B

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio BD/IO BD CONN

Size Document Number Rev

Date: Sheet of

Audio BD/IO BD CONN

Custom

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

77 88W ednesday, January 13, 2010

1

A00

5

S

SID = User.Interface

4

3

2

1

D D

inger Printer Connector

F

+3.3V_RUN

A00-0104-1

R7801

0R0603-PAD-2-GP

USB_PN10[21]

USB_PP10[21]

C C

A00-0107-1 remove EL7801 for no co-lay after XB

1 2 1 2

0R0603-PAD-2-GP

R7802

A00-1223-1

1. dummy FP1 pin6, pin7 for power pin short to GND when plug in cable issue

2. add damping resister R7804

12

C7801

C7801 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

BIO_DET#[25]

R7804

0R3J-0-U-GP

1 2

Biometric_USBPN Biometric_USBPP

AFTP7804AFTP7804 AFTP7805AFTP7805

FP_VDD

BIO_DET#

AFTP7802AFTP7802 AFTP7803AFTP7803

SB-1025

1. SWAP USB NET

FP1

7

5 4 3 2

1

6

ACES-CON5-10-GP

1ST: 20.K0315.005 2ND: 20.K0392.005

+3.3V_RUN

1

Biometric_USBPN

1

Biometric_USBPP

1

BIO_DET#

1

SB-14

LED&Capacity board CONN

MEDIA1

21

+5V_RUN

SB-1024

+5V_ALW

SB-33

+3.3V_RUN

KBC_PWRBTN#_L WLAN_WIMAX_LED_R# SCRL_LED_R# CAP_LED_R# NUM_LED_R# SATA1_ACT_LED LED_BT_ACT_K_R#

PWR_BTN_LED_R# CAPA_INT#

THERM_SDA THERM_SCL

SB-06

R7803 100R2J-2-GPR7803 100R2J-2-GP

KBC_PWRBTN#[37]

WLAN_WIMAX_LED_R#[66] SCRL_LED_R#[66] CAP_LED_R#[66] NUM_LED_R#[66] SATA1_ACT_LED[66] LED_BT_ACT_K_R#[66]

PWR_BTN_LED_R#[66] CAPA_INT#[37]

THERM_SDA[37,39] THERM_SCL[37,39]

1 2

1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 22

PTWO-CON20-2-GP-U

1ST: 20.K0392.020 2ND: 20.K0481.020

Close to MEDIA1

+5V_RUN +3.3V_RUN+5V_ALW

12

C7803

AFTP7806AFTP7806 AFTP7808AFTP7808 AFTP7809AFTP7809 AFTP7810AFTP7810 AFTP7811AFTP7811 AFTP7812AFTP7812

SB-1024

AFTP7814AFTP7814

AFTP7816AFTP7816 AFTP7817AFTP7817 AFTP7818AFTP7818 AFTP7819AFTP7819 AFTP7820AFTP7820 AFTP7821AFTP7821 AFTP7822AFTP7822

12

SCD1U10V2KX-4GP

1 1 1 1 1 1

1

1 1 1 1 1 1 1

12

C7805

C7804

SCD1U10V2KX-4GP

WLAN_WIMAX_LED_R# SCRL_LED_R# CAP_LED_R# NUM_LED_R# SATA1_ACT_LED LED_BT_ACT_K_R#

CAPA_INT#

THERM_SDA THERM_SCL +3.3V_RUN +5V_RUN +5V_ALW PWR_BTN_LED_R# KBC_PWRBTN#_L

B B

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Finger Printer/Felica/Capacity

Size Document Number Rev

Custom

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

78 88W ednesday, January 13, 2010

1

A00

5

S

SID = EMI

E

MI Request

+

D D

PWR_SRC

+

PWR_SRC+VCC_CORE+1.5V_SUS

+

5V_CRT_RUN

4

S add EMI caps

+

1.5V_RUN_GPU

C-1204-1

+

3.3V_RUN_CARD

3

H

16

HT85B85X925R29-S-GP

1

OLE:

H

1

HT85B85X925R29-S-GP

1

H

2

HOLE256R115-GP

1

2

H

6

HT925X85BE95R29-L-5-S-GP

1

H

7

HT85BE85R29-U-5-GP

1

H

8

HT85BE85R29-U-5-GP

1

H

10

HT85BE85R29-U-5-GP

1

12

DY

C7901

C7901 E

E

C C

DY

C7902

C7902 E

E

SCD1U25V2ZY-1GP

12

EC7903

EC7904

EC7905

SCD1U50V3KX-GP

12

EC7906

EC7907

SCD1U50V3KX-GP

+5V_USB1 CHAGER_SRC +PBATT

12

EC7913

EC7912

SCD1U50V3KX-GP

EC7909

EC7908

SCD1U50V3KX-GP

12

EC7914

SCD1U50V3KX-GP

12

EC7910

SCD1U50V3KX-GP

EC7915

SCD1U50V3KX-GP

12

EC7911

SCD1U25V2ZY-1GP

SC-1207-1 add H16 for ME

SC-1204-4 change H2 to ZZ.00PAD.D11

SSID = Mechanical

12

SC-1130-1 add H15 for ME

H15

H15 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

1

SB-12

H5

H5 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

1

H11

H11 HOLE197R166-GP

HOLE197R166-GP

DY

1

H3

HOLE256R115-GP

1

FOR CPU HOLE

H12

H12 HOLE197R166-GP

HOLE197R166-GP

DY

1

SB-13

H13

H13 HOLE197R166-GP

HOLE197R166-GP

DY

H14

HOLE256R115-GP

1

SSID = RF

FOR FAN BOSS

H4

H4 STF296R138H83-GP

SPR5

STF296R138H83-GP

1

SC-1130-1 add SPR6 for ME

SPR6

SB-23

SB-29 RF Request

+PWR_SRC

12

B B

12

DY

C7902

C7901

C7901 R

R

SC56P50V2JN-2GP

+PWR_SRC_3D3V +15V_ALW +5V_ALW +3.3V_ALW

C7903

R

SC1U6D3V2KX-GP

DY

12

DY

SC1U6D3V2KX-GP

12

DY

RC7906

RC7907

SC1U6D3V2KX-GP

12

DY

C7904

C7904 R

R

RC7905

SC1U6D3V2KX-GP

DY

12

DY

12

DY

RC7909

SC1U6D3V2KX-GP

12

RC7908

SC1U6D3V2KX-GP

+1.05V_VTT_P

12

DY

RC7928

RC7910

SC1U6D3V2KX-GP

12

RC7929

SC-1130-1 add RC7931 for RF

+1.5V_RUN_GPU

12

DY

RC7931

SC1U6D3V2KX-GP

12

A00-0105-1

SC56P50V2JN-2GP

SPR2

SPR1

SPR2

change SPR5 from 34.4F822.002 to 34.42T14.002 by ME

SPR4

SPR3

SPR4

1

SPRING-57-GP

1st Samsung

Title

Size Document Number Rev

Custom

Date: Sheet of

2

1

SPRING-31-GP

1

SPRING-24-GP-U

3

1

SPRING-24-GP-U

12

DY

C7911

C7911 R

R

SC1U6D3V2KX-GP

+1.5V_SUS +1.05V_VTT +VCC_GFX_COREP +1.05V_VTT

A A

12

DY

C7919

C7919 R

R

SC1U6D3V2KX-GP

12

DY

C7912

C7912 R

R

SC1U6D3V2KX-GP

12

DY

C7920

C7921

R

SC1U6D3V2KX-GP

SC56P50V2JN-2GP

12

DY

RC7913

RC7914

SC1U6D3V2KX-GP

SC56P50V2JN-2GP

12

5

12

RC7922

SC56P50V2JN-2GP

12

DY

RC7915

SC1U6D3V2KX-GP

12

RC7917

RC7916

SC1U6D3V2KX-GP

SC4D7P50V2CN-1GP

12

DY

RC7924

SC1U6D3V2KX-GP

+3.3V_ALW

DY

12

RC7918

SC56P50V2JN-2GP

+PWR_SRC

12

DY

RC7925

SC1U6D3V2KX-GP

+3.3V_ALW

12

DY

RC7930

SC1U6D3V2KX-GP

+PWR_SRC

12

DY

RC7926

RC7927

SC1U6D3V2KX-GP

SC56P50V2JN-2GP

4

1

SPRING-24-GP-U

1

SPRING-24-GP-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Miscellaneous Components

Winery13 MB DIS

79 88W ednesday, January 13, 2010

1

A00

5

SID = VIDEO

S

D D

C C

12

8069

8069 C

C

SC22U6D3V5MX-2GP

12

8064

8074

C

SC10U6D3V5KX-1GP

SC4D7U6D3V3KX-GP

12

C8068

C8067

SC1U10V2KX-1GP

SC1U6D3V2KX-GP

12

C8065

C8066

SCD1U16V2KX-3GP

Place near GPU Place under GPU

Revised decoupling C 2009/05/28

B B

4

P

CIE_MTX_G RX_P0

P

CIE_MTX_G RX_N0

P

CIE_MTX_G RX_P1

P

CIE_MTX_G RX_N1

P

CIE_MTX_G RX_P2 CIE_MTX_G RX_N2

P P

CIE_MTX_G RX_P3 CIE_MTX_G RX_N3

P P

CIE_MTX_G RX_P4 PCIE_MTX_ GRX_N4 PCIE_MTX_ GRX_P5 PCIE_MTX_ GRX_N5

PCIE_MTX_ GRX_P6 PCIE_MTX_ GRX_N6 PCIE_MTX_ GRX_P7 PCIE_MTX_ GRX_N7 PCIE_MTX_ GRX_P8 PCIE_MTX_ GRX_N8 PCIE_MTX_ GRX_P9

PCIE_MTX_ GRX_N9 PCIE_MTX_ GRX_P10 PCIE_MTX_ GRX_N10 PCIE_MTX_ GRX_P11 PCIE_MTX_ GRX_N11 PCIE_MTX_ GRX_P12 PCIE_MTX_ GRX_N12 PCIE_MTX_ GRX_P13 PCIE_MTX_ GRX_N13 PCIE_MTX_ GRX_P14 PCIE_MTX_ GRX_N14 PCIE_MTX_ GRX_P15 PCIE_MTX_ GRX_N15

U

AE12

AF12 AG12 AG13

AF13

AE13

AE15

AF15 AG15 AG16

AF16

AE16

AE18

AF18 AG18 AG19

AF19

AE19

AE21

AF21 AG21 AG22

AF22

AE22

AE24

AF24 AG24

AF25 AG25 AG26

AF27

AE27

AB13

AB16

AB17

AB7 AB8 AB9

AC13

AC7 AD6 AE6 AF6 AG6

GT218-ES -S-A1-GP

8001B

P

EX_RX0

P

EX_RX0#

P

EX_RX1

P

EX_RX1#

P

EX_RX2 EX_RX2#

P P

EX_RX3 EX_RX3#

P PEX_RX4 PEX_RX4# PEX_RX5 PEX_RX5# PEX_RX6 PEX_RX6# PEX_RX7 PEX_RX7# PEX_RX8 PEX_RX8# PEX_RX9 PEX_RX9# PEX_RX10 PEX_RX10# PEX_RX11 PEX_RX11# PEX_RX12 PEX_RX12# PEX_RX13 PEX_RX13# PEX_RX14 PEX_RX14# PEX_RX15 PEX_RX15#

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

2

OF 7

P

EX_TX0

P

EX_TX0# P

EX_TX1

P

EX_TX1# P

EX_TX2

EX_TX2#

P

EX_TX3

EX_TX3#

P

PEX_TX4

PEX_TX4#

PEX_TX5

PEX_TX5#

PEX_TX6

PEX_TX6#

PEX_TX7

PEX_TX7#

PEX_TX8

PEX_TX8#

PEX_TX9 PEX_TX9# PEX_TX10

PEX_TX10#

PEX_TX11

PEX_TX11#

PEX_TX12

PEX_TX12#

PEX_TX13

PEX_TX13#

PEX_TX14

PEX_TX14#

PEX_TX15

PEX_TX15#

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_REFCLK

PEX_REFCLK#

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT#

PEX_CLKREQ#

PEX_RST#

PEX_SVDD_3V3

PEX_TERMP

PEX_PLLVDD

PLLVDD

3

P

CIE_MRX_G TX_C_P0

AD10

P

CIE_MRX_G TX_C_N0

AD11

P

CIE_MRX_G TX_C_P1

AD12

P

CIE_MRX_G TX_C_N1

AC12

P

CIE_MRX_G TX_C_P2

AB11

CIE_MRX_G TX_C_N2

P

AB12

P

CIE_MRX_G TX_C_P3

AD13

CIE_MRX_G TX_C_N3

P

AD14

P

CIE_MRX_G TX_C_P4

AD15

PCIE_MRX_ GTX_C_N4

AC15

PCIE_MRX_ GTX_C_P5

AB14

PCIE_MRX_ GTX_C_N5

AB15

PCIE_MRX_ GTX_C_P6

AC16

PCIE_MRX_ GTX_C_N6

AD16

PCIE_MRX_ GTX_C_P7

AD17

PCIE_MRX_ GTX_C_N7

AD18

PCIE_MRX_ GTX_C_P8

AC18

PCIE_MRX_ GTX_C_N8

AB18

PCIE_MRX_ GTX_C_P9

AB19

PCIE_MRX_ GTX_C_N9

AB20

PCIE_MRX_ GTX_C_P10

AD19

PCIE_MRX_ GTX_C_N10

AD20

PCIE_MRX_ GTX_C_P11

AD21

PCIE_MRX_ GTX_C_N11

AC21

PCIE_MRX_ GTX_C_P12

AB21

PCIE_MRX_ GTX_C_N12

AB22

PCIE_MRX_ GTX_C_P13

AC22

PCIE_MRX_ GTX_C_N13

AD22

PCIE_MRX_ GTX_C_P14

AD23

PCIE_MRX_ GTX_C_N14

AD24

PCIE_MRX_ GTX_C_P15

AE25

PCIE_MRX_ GTX_C_N15

AE26

AC9 AD7 AD8 AE7 AF7 AG7

AB10 AC10

AF10 AE10

AE9 AD9

AG9

AG10

AF9

K5

C

8033 SCD1 U10V2KX-5GP

C

8034 SCD1 U10V2KX-5GP

C

8035 SCD1 U10V2KX-5GP

C

8036 SCD1 U10V2KX-5GP

C

8037 SCD1 U10V2KX-5GP

8037 SCD1 U10V2KX-5GP 8038 SCD1 U10V2KX-5GP

8038 SCD1 U10V2KX-5GP

C

C C

C

8039 SCD1 U10V2KX-5GP

8039 SCD1 U10V2KX-5GP 8040 SCD1 U10V2KX-5GP

8040 SCD1 U10V2KX-5GP

C

C C

C

8042 SCD1 U10V2KX-5GP

8042 SCD1 U10V2KX-5GP C8043 SCD 1U10V2KX-5GPC80 43 SCD 1U10V2KX-5GP C8044 SCD 1U10V2KX-5GPC80 44 SCD 1U10V2KX-5GP C8045 SCD 1U10V2KX-5GPC80 45 SCD 1U10V2KX-5GP C8047 SCD 1U10V2KX-5GPC80 47 SCD 1U10V2KX-5GP C8048 SCD 1U10V2KX-5GPC80 48 SCD 1U10V2KX-5GP C8050 SCD 1U10V2KX-5GPC80 50 SCD 1U10V2KX-5GP C8051 SCD 1U10V2KX-5GPC80 51 SCD 1U10V2KX-5GP C8052 SCD 1U10V2KX-5GPC80 52 SCD 1U10V2KX-5GP C8053 SCD 1U10V2KX-5GPC80 53 SCD 1U10V2KX-5GP C8054 SCD 1U10V2KX-5GPC80 54 SCD 1U10V2KX-5GP C8055 SCD 1U10V2KX-5GPC80 55 SCD 1U10V2KX-5GP C8056 SCD 1U10V2KX-5GPC80 56 SCD 1U10V2KX-5GP C8057 SCD 1U10V2KX-5GPC80 57 SCD 1U10V2KX-5GP C8058 SCD 1U10V2KX-5GPC80 58 SCD 1U10V2KX-5GP C8077 SCD 1U10V2KX-5GPC80 77 SCD 1U10V2KX-5GP C8078 SCD 1U10V2KX-5GPC80 78 SCD 1U10V2KX-5GP C8079 SCD 1U10V2KX-5GPC80 79 SCD 1U10V2KX-5GP C8080 SCD 1U10V2KX-5GPC80 80 SCD 1U10V2KX-5GP C8081 SCD 1U10V2KX-5GPC80 81 SCD 1U10V2KX-5GP C8082 SCD 1U10V2KX-5GPC80 82 SCD 1U10V2KX-5GP C8083 SCD 1U10V2KX-5GPC80 83 SCD 1U10V2KX-5GP C8084 SCD 1U10V2KX-5GPC80 84 SCD 1U10V2KX-5GP C8085 SCD 1U10V2KX-5GPC80 85 SCD 1U10V2KX-5GP

CLK_PCIE_ VGA CLK_PCIE_ VGA#

PEX_TES T_PLL_CLK_OU T PEX_TES T_PLL_CLK_OU T#

PEX_CLK REQ# PEX_RST #

PEX_TER MP

1 2

+PEX_PL LVDD

+GPU_PL LVDD

2009/05/28

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

CLK_PCIE_ VGA [23]

CLK_PCIE_ VGA# [23]

DY

R8001 2K49R 2F-GPR8001 2K4 9R2F-GP

P

CIE_MRX_G TX_P0

P

CIE_MRX_G TX_N0

P

CIE_MRX_G TX_P1

P

CIE_MRX_G TX_N1

P

CIE_MRX_G TX_P2 CIE_MRX_G TX_N2

P P

CIE_MRX_G TX_P3 CIE_MRX_G TX_N3

P P

CIE_MRX_G TX_P4 PCIE_MRX_G TX_N4 PCIE_MRX_G TX_P5 PCIE_MRX_G TX_N5 PCIE_MRX_G TX_P6 PCIE_MRX_G TX_N6 PCIE_MRX_G TX_P7 PCIE_MRX_G TX_N7 PCIE_MRX_G TX_P8 PCIE_MRX_G TX_N8 PCIE_MRX_G TX_P9 PCIE_MRX_G TX_N9 PCIE_MRX_G TX_P10 PCIE_MRX_G TX_N10 PCIE_MRX_G TX_P11 PCIE_MRX_G TX_N11 PCIE_MRX_G TX_P12 PCIE_MRX_G TX_N12 PCIE_MRX_G TX_P13 PCIE_MRX_G TX_N13 PCIE_MRX_G TX_P14 PCIE_MRX_G TX_N14 PCIE_MRX_G TX_P15 PCIE_MRX_G TX_N15

C8059

12

R800220 0R2F-L-GPDYR800220 0R2F-L-GP

2

P

CIE_MTX_G RX_P[0..15]

P

CIE_MTX_G RX_N[0..15]

P

CIE_MRX_G TX_P[0..15]

P

CIE_MRX_G TX_N[0..15]

Revised decoupling C 2009/05/28

Place near GPUPlace under GPU

12

C8060

SCD1U16V2KX-3GP

+3.3V_RU N_GPU

12

C8049

SCD1U10V2KX-4GP

12

C8063

C8062

SC1U6D3V2KX-GP

12

R8004

R8004 10KR2J-3 -GP

10KR2J-3 -GP

+3.3V_RU N_GPU

Place under GPU

12

C8073

C8061

SC1U10V3KX-3GP

SC10U6D3V5KX-1GP

Change R8004

SC10U6D3V5KX-1GP

resistor value 2009/06/05

DW

07/10 NO STUFF

1. R8002 made NO STUFF

+1.05V_G FX_PCIE+1.05V_G FX_PCIE

C8041

SC10U6D3V5KX-1GP

1

CIE_MTX_G RX_P[0..15] [8]

P

CIE_MTX_G RX_N[0..15] [8]

P

CIE_MRX_G TX_P[0..15] [8]

P

CIE_MRX_G TX_N[0..15] [8]

12

Remove 0.01u capacity C8039

Change power rail

2009/05/28

2009/05/26

U8028

DGPU_HO LD_RST#[25]

PLT_RST #[9,21,34 ,36,37,64,70,76]

A A

5

R8039

1 2

0R2J-2-GP

R8017

R8017 100KR2J -1-GP

100KR2J -1-GP

1 2

PLT_RST #_RC

12

C8086

DY

DW

07/10 Change

1. Change U8028 from Operatin g voltage Range 5 to 3 V . Add

2.Added Pull-down resistors o n GPU Reset [PEX_REST#] Pin

1

B

2

A

3

GND

74LVC1G 08GW-1-GP

SC1U6D3V2KX-GP

VCC

5

PEX_RST #PEX_RST#

4

Y

R8016

R8016 100KR2J -1-GP

100KR2J -1-GP

1 2

4

NV suggestion.

PEX_PLLVDD = 120mA

12

C8087

SCD1U16V2KX-3GP

C8070

SC1U10V2KX-1GP

Place near GPU

L8011

1 2

12

IND-D1UH-20-G P

C8046

100NH 0603

DCR= 0.13 ohm

SC4D7U6D3V3KX-GP

Revised decoupling C 2009/05/28

3

+1.05V_G FX_PCIE+PEX_PL LVDD

(Pre pin)

+GPU_PL LVDD

12

C8071

C8072

SCD1U16V2KX-3GP

Revised decoupling C 2009/05/28

2

Place near GPUPlace under GPU

12

C8076

SC1U10V2KX-1GP

1st Samsung

Title

Size Document N umber Rev

A3

Date: Sheet of

SB-30

+1.05V_G FX_PCIE+3.3V_RU N

L8005

1 2

BLM18SG 121TN1D-GP

I SP_PLLVDD=45mA

C8075

SC4D7U6D3V3KX-GP

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

VGA-PCIE/LVDS(1/4)

Winery13 MB DIS

1

A00

80 88Wedn esday, January 13, 2010

A00

5

SID = VIDEO

S

D D

VGA_BLUE[74] VGA_GREEN[74] VGA_RED[74]

D

W

0

7/05

1. LCD brightness control are s eparated by GPU,PCH,EC

2. LCD Power Enable control are separated by GPU,PCH,EC

3. LCD Backlight On/Off Status are separated by GPU,PCH,EC 07/10 Not Reserve

1. Shorted LBKLT_CTL_GPU,LCDVDD _EN_GPU,PANEL_BKEN_GPU Not Res erve R8134,R8135,R8136.

L

BKLT_CTL_GPU[54]

L

CDVDD_EN _GPU[54]

P

ANEL_BKEN_GP U[3 7]

P

WRCN TL_0[86]

P

WRCN TL_1[86]

T

HERMTRIP_VGA #[37]

DEEPIDLE_W AKE_INT_R#[25]

SC-1204-1 add EC8101,EC8102,EC8103 for EMI

12

EC8101

EC8102

SC15P50V2JN-2-GP

+DACA_VDD = 120mA

+3.3V_RUN_GP U

C C

L8106

1 2

BLM18SG331TN1D -GP

Spec 300 ohm, ESR<0.25 ohm

16mil

12

8153

8153 C

C

12

C8154

C8144

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

+DACA_VDD STRAP0

12

C8118

C8143

SCD1U10V2KX-4GP

Place under GPUPlace near GPU

+DACA_VDD

12

C8108

C8107

SCD1U10V2KX-4GP

SC470P50V2KX-3GP

SC4700P50V2KX-1GP

Revised decoupling C 2009/05/28

U8001C

+IFPAB_IOVDD

+IFPAB_PLLVDD

IFPAB_RSET

+IFPAB_IOVDD

IFPC_IOVDD IFPC_PLLVDD

AC4 AD4

V5

V4 AA5 AA4 W4

Y4 AB4 AB5

V3

AD5

AB6

AB3 AB2

W1

V1 W3 W2 AA2 AA3 AB1 AA1

V2

P4

N4

M5

M4

L4 K4 H4

J4

J6 P6

R5

G4 G5

GT218-ES-S-A 1-GP

VGA_LVDSA_CLK[74] VGA_LVDSA_CLK #[74]

VGA_LVDSA_DA T0[74] VGA_LVDSA_DA T0#[74] VGA_LVDSA_DA T1[74] VGA_LVDSA_DA T1#[74] VGA_LVDSA_DA T2[74] VGA_LVDSA_DA T2#[74]

1 2

DY

R8121

R8121 1KR2F-3-GP

1KR2F-3-GP

2009/05/28

B B

DW30 LVDS only 1 chanel Vendor confirm tie to +1.8V powe rail

DW30 not support HDMI NV DG: pull-down 10K

1 2

R8135 10KR2J-3-GPR 8135 10K R2J-3-GP

1 2

R8134 10KR2J-3-GPR 8134 10K R2J-3-GP

A A

4

12

EC8103

SC15P50V2JN-2-GP

IFPA_TXC IFPA_TXC#

IFPA_TXD0 IFPA_TXD0# IFPA_TXD1 IFPA_TXD1# IFPA_TXD2 IFPA_TXD2# IFPA_TXD3 IFPA_TXD3#

IFPA_IOVDD

IFPAB_PLLVDD

IFPAB_RSET

IFPB_TXC IFPB_TXC#

IFPB_TXD4 IFPB_TXD4# IFPB_TXD5 IFPB_TXD5# IFPB_TXD6 IFPB_TXD6# IFPB_TXD7 IFPB_TXD7#

IFPB_IOVDD

IFPC_L0 IFPC_L0# IFPC_L1 IFPC_L1# IFPC_L2 IFPC_L2# IFPC_L3 IFPC_L3#

IFPC_IOVDD IFPC_PLLVDD

IFPC_RSET

IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA#

12

R8116

R8118

150R2F-1-GP

12

R8111

10KR2F-2-GP

3 OF 7

IFPD_L0

IFPD_L0#

IFPD_L1

IFPD_L1#

IFPD_L2

IFPD_L2#

IFPD_L3

IFPD_L3#

IFPD_PLLVDD

IFPD_RSET

IFPD_AUX_I2CX_SCL

IFPD_AUX_I2CX_SDA#

IFPDE_IOVDD

IFPE_L0

IFPE_L0#

IFPE_L1

IFPE_L1#

IFPE_L2

IFPE_L2#

IFPE_L3

IFPE_L3#

IFPE_PLLVDD

IFPE_RSET

IFPE_AUX_I2CY_SCL

IFPE_AUX_I2CY_SDA#

P

WRCN TL_0

P

WRCN TL_1

T

HERMTRIP_VGA #

DEEPIDLE_W AKE_INT_R#

VGA_VSYNC[74]

VGA_HSYNC[74]

R8119

DACA_RSET

150R2F-1-GP

+DACA_VDD DACA_VREF

R8106

12

1 2

C8103

124R2F-U-GP

SCD1U10V2KX-5GP

STRAP0[83] STRAP1[83] STRAP2[83]

F5 F4 E4 D5 C3 C4 B3 B4

IFPD_PLLVDD

N6

M6

D3 D4

IFPDE_IOVDD

H6

D6 C6 A6 A7 B6 B7 E6 E7

IFPE_PLLVDD

D7 F8

F7 G6

Unused IFP Interfaces setting 2009/06/03

DACB_VDD

STRAP1 STRAP2

10KR2J-3-GP

U

N1 G1 C1 M2 M3

K3 K2

J2 C2 M1 D2 D1

J3

J1

K1

F3 G3 G2

F1

F2

AD3 AE3 AE2

AD1 AD2

AE1

AG2

AF1

R4

T4

T5

U4 U6

V6

W5

R6

C7

B9

A9

R8128

12

R8129

12

R8130

12

Change power rail 2009/05/28

3

4 OF 7

8001D

G

PIO0

G

PIO1

G

PIO2

G

PIO3

G

PIO4

G

PIO5

G

PIO6 PIO7

G G

PIO8

G

PIO9 PIO10

G G

PIO11 PIO12

G G

PIO13

G

PIO14 PIO15

G GPIO16 GPIO17 GPIO18 GPIO19

DACA_BLUE DACA_GREEN DACA_RED

DACA_VSYNC DACA_HSYNC

DACA_RSET DACA_VDD DACA_VREF

DACB_BLUE DACB_GREEN DACB_RED

DACB_VSYNC DACB_HSYNC

DACB_RSET DACB_VDD DACB_VREF

STRAP0 STRAP1 STRAP2

MULTI_STRAP_REF0_GND MULTI_STRAP_REF1_GND

4 OF 7

I

2CA_SCL

I

2CA_SDA

I

2CB_SCL

I

2CB_SDA

I

2CC_SCL 2CC_SDA

I

2CH_SCL 2CH_SDA

I

2CS_SCL

I I

2CS_SDA

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST#

JTAG_TCK

ROM_SO

ROM_SI

ROM_SCLK

ROM_CS#

XTAL_IN

XTAL_OUT

XTAL_OUTBUFF

XTAL_SSIN

THERMDN THERMDP

TESTMODE

SP_PLLVDD

SPDIF

BUFRST#

R1 T3

R2 R3

A2 B1

A3 A4

T1 T2

AG4 AE4

AF4 AG3 AF3

C10 A10

C9 B10

D10 E10

E9 D11

F11 F10

D8 D9

AD25 N2

CEC

L6 F9

N5

+IFPAB_IOVDD

+1.8V_RUN_GP U

Place near GPU

L8107

1 2

BLM18PG181SN1D- GP

Revised decoupling C 2009/05/28

+IFPAB_PLLVDD

Revised decoupling C 2009/05/28

+1.05V_GFX_PCIE

BLM18PG181SN1D- GP

Place near GPU

C

RT_CLK_DD C

C

RT_DAT_DD C

I

2CB_SCL 2CB_SDA

I

L

DDC_CLK

L

DDC_DAT A

T

P_JTAG_TDI_GPU

TP_JTAG_TD O_GPU

TP_JTAG_TMS_ GPU JTAG_RST#_G PU TP_JTAG_TC K_GPU

ROM_SO_GPU ROM_SI_GPU

ROM_SCLK_GPU

XTAL_IN GPU_XTALOU T_1

XTALBUFF

R8124 10KR2J-3-GPR8124 10KR2J-3- GP

XTAL_SSIN

STRAP_CAL_PU _GND0 STRAP_CAL_PU _GND1

12

DY

HDCP_TEST MODE CEC

R8127 10KR2J-3-GPR8127 10KR2J-3-GP

+SP_PLLVDD

2009/05/28

IFPAB_IOVDD = 300mA

12

L8108

1 2

C

RT_CLK_DD C [55] RT_DAT_DD C [55]

C

L

DDC_CLK [54]

L

DDC_DAT A [54]

P8102TP8102

T

1

TP8104TP8104

1

TP8101TP8101

1

12

R81201KR2J-1- GP R81201KR2J-1-G P

TP8103TP8103

1

ROM_SO_GPU [83] ROM_SI_GPU [83]

ROM_SCLK_GPU [83]

0R0402-PAD-2- GP

0R0402-PAD-2- GP R8114

R8114

1 2 1 2

R8113 0R0402-PAD-2-GPR8113 0R0402-PAD-2-GP

12

R8133

2009/06/03

1 2

40K2R2F-GP

1 2

R8126 40K2R2F-G PR8126 40K2R2F-GP

C8102

C8102 SC2200P50V2KX-2G P

SC2200P50V2KX-2G P

R8107 10KR2J-3-GPR8107 10KR2J-3- GP

12

2009/06/03

12

C8149

C8126

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

IFPAB_PLLVDD = 220mA

12

C8152

C8128

SC4D7U6D3V3KX-GP

GPU_XTAL_IN GPU_XTALOU T

A00-0104-1

+3.3V_RUN_GP U

+IFPAB_IOVDD

SC1U6D3V2KX-GP

2

3.3V_RUN_GPU

+

1

23

N8112

R

SRN2K2J-1-G P

4

I

2CB_SCL 2CB_SDA

I

LK GEN 27M select:

C

XTAL_IN

R8123 0R2J-2-GP

1 2

DY

XTAL_SSIN

R8132

10KR2J-3-GP

VGA 27M

SS

Added CLK GEN 27M select circuit 2009/06/15 Added R8132 (DY) 2009/06/17

VGA_THERMD C [39]

VGA_THERMD A [39]

12

DY

R8131 0R2J-2-GP

1 2

DY

12

R8125

DY

10KR2J-3-GP

+SP_PLLVDD

Remove R8112, R8114 2009/06/09

R8131R8123

R8125

POPDY

DY

DYNON-SS

POPPOP

Place near GPU

12

C8127

SC1U6D3V2KX-GP

Revised decoupling C 2009/05/28

12

C8150

Place under GPU near IFPA_IOVDD

SCD1U10V2KX-4GP

12

C8151

Place under GPU near IFPB_IOVDD

SCD1U10V2KX-4GP

+IFPAB_PLLVDD

CLK_VGA_27M [7]

R8132

POP

DY

1 2

12

I SP_PLLVDD=45mA

C8120

SC4D7U6D3V3KX-GP

D

efault X'tal

M

ain 82.30034.651

Second ?

SB-30

+1.05V_GFX_PCIE

L8110

BLM18SG121TN1D -GP

GPU_XTAL_IN

GPU_XTALOU T

SC15P50V2JN-2- GP

1

12

R8115

1MR2J-1-GP

12

C8135

C8138

C8138 SC15P50V2JN-2- GP

SC15P50V2JN-2- GP

SB-19

1st: HARMONY 82.30034.651 2nd: ITTI 82.30034.801 3rd: TXC 82.30034.681

8101

X

2 3

XTAL-27MHZ- 84-GP

41

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

VGA-LVDS/CRT/DP PORT

Winery13 MB DIS

1

81 88Wednesd ay, January 13, 2010

A00

5

S

SID = VIDEO

R

D D

C C

evised decoupling C 2009/05/28

P

lace under GPU

VCC_GFX _CORE

+

12

C8241

SCD01U16V2KX-3GP

12

C8248

SCD047U10V2KX-2GP

12

C8243

C8242

SCD01U16V2KX-3GP

12

C8249

C8250

SCD047U10V2KX-2GP

Place near GPU

B B

Change FBVDDQ power rail

"Remote Voltage Sensing" not used,reserve Test-Point.

2009/05/28

+1.5V_RU N_GPU

A A

5

5 OF 7

L19

FBVDDQ

L23

FBVDDQ

L26

FBVDDQ

M19

FBVDDQ

N22

FBVDDQ

U22

FBVDDQ

Y22

FBVDDQ

GT218-ES -S-A1-GP

U8001E

FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ

4

U

8001F

J9

VDD

J10

VDD

J12

VDD

J13

VDD

L9

VDD

M9

VDD

12

C8244

SCD01U16V2KX-3GP

12

C8234

SCD1U10V2KX-4GP

12

C8240

SC4D7U6D3V3KX-GP

TP8203TP AD14-GP TP8203TPAD14-GP TP8205TP AD14-GP TP8205TPAD14-GP

12

C8246

SCD01U16V2KX-3GP

1 1

C8247

SCD01U16V2KX-3GP

TP_VDD_ SENSE_E15 TP_VDD_ SENSE_W15

M11

VDD

M17

VDD

N9

VDD

N11

VDD

N12

VDD

N13

VDD

N14

VDD

N15

VDD

N16

VDD

N17

VDD

N19

VDD

P11

VDD

P12

VDD

P13

VDD

P14

VDD

P15

VDD

P16

VDD

P17

VDD

R9

VDD

R11

VDD

R12

VDD

R13

VDD

R14

VDD

R15

VDD

R16

VDD

R17

VDD

T9

VDD

T11

VDD

T17

VDD

U9

VDD

U19

VDD

W9

VDD

W10

VDD

W12

VDD

W13

VDD

W18

VDD

W19

VDD

E15

VDD_SENSE

W15

VDD_SENSE

GT218-ES -S-A1-GP

VID_PLLVDD

OF 7

6

NC#J5 NC#D15 NC#C15

RFU_1

RFU_2

RFU_3

RFU_4

RFU_5

VDD33 VDD33 VDD33 VDD33 VDD33 VDD33

3

J5 D15 C15

T6 W6 Y6 AA6 N3

Place under GPU Place near GPU

A12 B12 C12 D12 E12 F12

12

C8229

SCD1U10V2KX-5GP

12

C8230

SCD1U10V2KX-5GP

12

C8232

SCD1U10V2KX-5GP

Revised decoupling C 2009/05/28

K6

+GPU_PL LVDD

2009/05/28

2

OF 7

7

U

8001G

B2

G

ND

B5

ND

G

B8

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B26

GND

E2

GND

E5

GND

E8

GND

E11

GND

E17

GND

E20

GND

E23

GND

E26

GND

F6

GND

H2

GND

H5

GND

J11

GND

J14

GND

J17

GND

K19

GND

K9

GND

L2

GND

L11

GND

L12

GND

L13

GND

L14

GND

L15

+3.3V_RU N_GPU

12

C8211

C8231

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

GND

L16

GND

L17

GND

L5

GND

M12

GND

M13

GND

M14

GND

M15

GND

M16

GND

P2

GND

P5

GND

P9

GND

P19

GND

P23

GND

P26

GND

T12

GND

T13

GND

T14

GND

T15

GND

T16

GND

GT218-ES -S-A1-GP

GND_SENSE GND_SENSE

G G GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

AF8

ND

AF5

ND

AF26 AF23 AF20 AF2 AF17 AF14 AF11 AC26 AC23 AC20 AC17 AC14 AC11 AC8 AC6 AC5 AC2 Y26 Y23 Y5 Y2 W17 W14 W11 V9 V19 U26 U23 U17 U16 U15 U14 U13 U12 U11 U5 U2

E14 W16

1

FBVDD/Q = 2.24A

+1.5V_RU N_GPU

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA-POWER/GND(3/4)

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

VGA-POWER/GND(3/4)

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

82 88Wedn esday, January 13, 2010

1

A00

A13 B13 C13 D13 D14 E13 F13 F14 F15 F16 F17 F19 F22 H23 H26 J15 J16 J18 J19

Place under GPU

12

C8222

C8209

SCD1U10V2KX-4GP

Place near GPU

12

C8219

C8219 SC1U10V 3KX-3GP

SC1U10V 3KX-3GP

+1.5V_RU N_GPU

C8251

C8235

SCD1U10V2KX-4GP

12

Revised decoupling C 2009/05/28

4

12

C8252

C8253

SCD1U10V2KX-4GP

3

5

SID = VIDEO

S

M

DA[0..63][84,8 5]

D D

C C

B B

R830340D2R2F -GP R83 0340D2R2 F-GP

12

R831440D2R2F -GP R83 1440D2R2 F-GP

1 2

12

C8302

SC4D7U6D3V3KX-GP

12

R831560D4R2F -GP R83 1560D4R2 F-GP

SC1U6D3V2KX-GP

+1.05V_G FX_PCIE

+1.5V_RU N_GPU

L8301

1 2

BLM18SG 331TN1D-GP

Place near GPU

16mil

12

C8301

+FB_PLL VDD

M

DA0

M

DA1 DA2

M M

DA3 DA4

M M

DA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

FB_CAL_ PU_GND FB_CAL_ PD_VDDQ FB_CAL_ TERM_GND

4

U

8001A

D22

F

E24

F

E22

F

D24

F

D26

F

D27

FBA_D5

C27

FBA_D6

B27

FBA_D7

A21

FBA_D8

B21

FBA_D9

C21

FBA_D10

C19

FBA_D11

C18

FBA_D12

D18

FBA_D13

B18

FBA_D14

C16

FBA_D15

E21

FBA_D16

F21

FBA_D17

D20

FBA_D18

F20

FBA_D19

D17

FBA_D20

F18

FBA_D21

D16

FBA_D22

E16

FBA_D23

A22

FBA_D24

C24

FBA_D25

D21

FBA_D26

B22

FBA_D27

C22

FBA_D28

A25

FBA_D29

B25

FBA_D30

A26

FBA_D31

U24

FBA_D32

V24

FBA_D33

V23

FBA_D34

R24

FBA_D35

T23

FBA_D36

R23

FBA_D37

P24

FBA_D38

P22

FBA_D39

AC24

FBA_D40

AB23

FBA_D41

AB24

FBA_D42

W24

FBA_D43

AA22

FBA_D44

W23

FBA_D45

W22

FBA_D46

V22

FBA_D47

AA25

FBA_D48

W27

FBA_D49

W26

FBA_D50

W25

FBA_D51

AB25

FBA_D52

AB26

FBA_D53

AD26

FBA_D54

AD27

FBA_D55

V25

FBA_D56

R25

FBA_D57

V26

FBA_D58

V27

FBA_D59

R26

FBA_D60

T25

FBA_D61

N25

FBA_D62

N26

FBA_D63

A15

FB_CAL_PU_GND

B15

FB_CAL_PD_VDDQ

B16

FB_CAL_TERM_GND

AC19

FB_PLLAVDD

R19

FB_PLLAVDD

T19

FB_DLLAVDD

GT218-ES -S-A1-GP

BA_D0 BA_D1 BA_D2 BA_D3 BA_D4

1

OF 7

F

BA_CMD0

F

BA_CMD1 BA_CMD2

F F

BA_CMD3 BA_CMD4

F FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

FBA_DEBUG

FB_VREF

F

BA_CMD_ 0

F26

R

AS#

J24

BA_CMD_ 2

F

F25

B

A1

M23

BA_CMD_ 4

F

N27

F

BA_CMD_ 5

M27

FBA_CMD _6

K26

FBA_CMD _7

J25

FBA_CMD _8

J27

MAA11

G23

CAS#

G26

WE#

J23

BA0

M25

FBA_CMD _13

K27

MAA12

G25

MEM_RST

L24

MAA7

K23

MAA10

K24

FBA_CMD _18

G22

MAA0

K25

MAA9

H22

MAA6

M26

FBA_CMD _22

H24

MAA8

F27

FBA_CMD _24

J26

MAA1

G24

MAA13

G27

BA2

M24

FBA_CMD _28

K22

FBA_CMD _29

J22

FBA_CMD _30

L22

DQMA#0

C26

DQMA#1

B19

DQMA#2

D19

DQMA#3

D23

DQMA#4

T24

DQMA#5

AA23

DQMA#6

AB27

DQMA#7

T26

QSA#0

D25

QSA#1

A18

QSA#2

E18

QSA#3

B24

QSA#4

R22

QSA#5

Y24

QSA#6

AA27

QSA#7

R27

QSA0

C25

QSA1

A19

QSA2

E19

QSA3

A24

QSA4

T22

QSA5

AA24

QSA6

AA26

QSA7

T27

CLKA0

F24

CLKA0#

F23

CLKA1

N24

CLKA1#

N23

M22

A16

nVIDIA recommend

3

BA_CMD_ 0 [84]

F R

AS# [84,85]

F

BA_CMD_ 2 [84]

B

A1 [84,85]

F

BA_CMD_ 4 [85] FBA_CMD _5 [85] FBA_CMD _6 [85] FBA_CMD _7 [85] FBA_CMD _8 [85] MAA11 [84,8 5]

CAS# [84,85] WE# [84,85] BA0 [84,85 ]

FBA_CMD _13 [85 ] MAA12 [84,8 5]

MEM_RST [84 ,85]

MAA7 [84,85 ] MAA10 [84,8 5] FBA_CMD _18 [84 ] MAA0 [84,85 ] MAA9 [84,85 ] MAA6 [84,85 ] FBA_CMD _22 [84 ] MAA8 [84,85 ] FBA_CMD _24 [84 ] MAA1 [84,85 ] MAA13 [84,8 5]

BA2 [84,85 ]

FBA_CMD _28 [85 ] FBA_CMD _29 [84 ] FBA_CMD _30 [84 ]

2009/06/05

DQMA#0 [84] DQMA#1 [84] DQMA#2 [84] DQMA#3 [84] DQMA#4 [85] DQMA#5 [85] DQMA#6 [85] DQMA#7 [85]

QSA#0 [8 4] QSA#1 [8 4] QSA#2 [8 4] QSA#3 [8 4] QSA#4 [8 5] QSA#5 [8 5] QSA#6 [8 5] QSA#7 [8 5]

QSA0 [84 ] QSA1 [84 ] QSA2 [84 ] QSA3 [84 ] QSA4 [85 ] QSA5 [85 ] QSA6 [85 ] QSA7 [85 ]

CLKA0 [84] CLKA0# [84]

CLKA1 [85] CLKA1# [85]

2

Strap pin resist or need use 1% resistor (NV De sign Guide)

S

trap pin define

12

STRAP0[81]

STRAP1[81]

STRAP2[81]

ROM_SCL K_GPU[81]

ROM_SI_GPU[81]

ROM_SO_ GPU[81]

Logical Strap Bi t Mapping Resistor Pull-Up Pull-Down 5Kohms 1000 0000 10Kohms 1001 0001 15Kohms 1010 0010 20Kohms 1011 0011 25Kohms 1100 0100 30Kohms 1101 0101 35Kohms 1110 0110 45Kohms 1111 0111

Strap0 Strap1 Strap2

USER_BIT0 USER_BIT1 USER_BIT2 USER_BIT3

1

3GIO_PADCFG_LUT_ ADR0

1

3GIO_PADCFG_LUT_ ADR1

1

3GIO_PADCFG_LUT_ ADR2

1

3GIO_PADCFG_LUT_ ADR3

STRAP0

STRAP1

STRAP2

ROM_SCL K_GPU

ROM_SI_GPU

ROM_SO_ GPU

0 1 1 1

PCI_DEVID_0 PCI_DEVID_1 PCI_DEVID_2 PCI_DEVID_3

DY

12

R8302

R8306

45K3R2F-L-GP

12

DY

R8301

R8307

4K99R2F-L-GP

1 0 1 0

12

Y

D

R8305

34K8R2F-1-GP

4K99R2F-L-GP

12

DY

R8316

30KR2F-GP

10KR2F-2-GP

EDID is used Reserved N11M-GE1 GPU Device ID=0x0A 75

ROM_SO_GPU ROM_SCLK_GPUROM_SI_GPU

RAM_CFG0 RAM_CFG1 RAM_CFG2 RAM_CFG3

Default setting: SAMSUNG sDDR3 64Mx16BIT-->20K pull down (0x00 11) If use Hynix sDD R3 64Mx16BIT(0x 0010), R8308 ch ange to 15K.

RAM_CFG[3:0] 0000 0001 0010 0011 0100 0101 0110 0111

SUB_VENDOR 0 No VBIOS ROM 1 BIOS ROM pre sent

3GIO_PADCFG 0000 Desktop 1110 Notebook (POR)

SLOT_CLOCK_CFG 0 GPU and MCH do not share a common referenc e clock 1 GPU and MCH share a common reference clock (POR)

VGA_DEVICE SMB_ALT_ADDR FB_0_BAR_SIZE XCLK_417

Config

64MX16 DDR3 64MX16 DDR3

1 0 0 0

FB_BUS Width



64Bit 64Bit



XCLK_417 0 277MHz(POR) 1 Reserved

USER[3:0] 1111 Use EDID to detect panel s ettings

PEX_PLL_EN_TERM SLOT_CLK_CONFIG SUB_VENDOR PCI_DEVID_4

Definitions

 

Hynix Samsung

   

Default

PEX_PLL_EN_TERM 0 Disable (POR) 1 Enable

0 1 0 1

1

R8309

15KR2F-GP

R8304

15KR2F-GP

12

Y

D

12

+

3.3V_RUN _GPU

12

Y

D

R8311

R8312

4K99R2F-L-GP

12

R8308

R8313

20KR2F-L-GP

4K99R2F-L-GP

10KR2F-2-GP

FB_PLLAVDD+FB_DLLAVDD=100mA

A A

DW

07/10 Updated

1.+FB_PLLVDD power rail corr ected to +1.05V_GFX_PCIE

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA-MEMORY/STRAPS(4/4)

Size Document N umber Rev

A3

Date: Sheet of

VGA-MEMORY/STRAPS(4/4)

Taipei Hsien 221, Taiwan, R.O.C.

Winery13 MB DIS

1

83 88Wedn esday, January 13, 2010

A00

5

SID = VIDEO

S

+

1.5V_RUN_GPU

U

8401

K8

V

DD

K2

V

DD

N1

V

DD

R9

V

DD

B2

V

DD

D9

DD

V

G7

V

DD

R1

V

DD

D D

C C

1.5V_RUN_GPU

+

12

R8404

1KR2F-3-GP

12

R8401

1KR2F-3-GP

FBA_CMD_18[83]

10KR2J-3-GP

Added CKE 10K pull down R 2009/06/05

12

8411

8411 R

R

8420

8420 C

C

SCD01U16V2KX-3GP

FBA_CMD_18

12

1 2

R8406 243R 2F-2-GPR8406 243R2F-2-GP

MAA0[83,85]

MAA1[83,85] FBA_CMD_22[83] FBA_CMD_24[83]

FBA_CMD_0[83] FBA_CMD_2[83]

MAA6[83,85]

MAA7[83,85]

MAA8[83,85]

MAA9[83,85]

MAA10[83,85] MAA11[83,85] MAA12[83,85] MAA13[83,85]

BA0[83,85] BA1[83,85] BA2[83,85]

CLKA0[83] CLKA0#[83]

UMA swap for layout

12

DQMA#2[83]

C8402

C8402 E

E

WE#[83,85] CAS#[83 ,85] RAS#[83 ,85]

SC6D8P50V2CN-GP

64X16 SAMSUNG K4W1G1646E-HC12 64X16 HYNIX H5TQ1G63BFR-12C

N9

DD

V

A8

DDQ

V

A1

V

DDQ

C1

V

DDQ

C9

DDQ

V

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VREFA1 VREFA2

ZQ_VRAM11 ZQ_VRAM12

MAA0 MAA1 FBA_CMD_22 FBA_CMD_24 FBA_CMD_0 FBA_CMD_2 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13

BA0 BA1 BA2

CLKA0 CLKA0#

DQMA#1 DQMA#3 DQMA#2

WE# CAS# RAS#

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

DUMMY-K4W 1G1646E-HC12-GP

E3

D

QL0

F7

D

QL1

F2

D

QL2

F8

D

QL3

H3

D

QL4

H8

QL5

D

G2

D

QL6

H7

D

QL7

D7

D

QU0

C3

QU1

D

C8

D

QU2

C2

D

QU3

A7

QU4

D

A2

DQU5

B8

DQU6

A3

DQU7

C7

DQSU

B7

DQSU#

F3

DQSL

G3

DQSL#

K1

ODT

L2

CS#

T2

RESET#

T7

NC#T7

L9

NC#L9

L1

NC#L1

J9

NC#J9

J1

NC#J1

J8

VSS

M1

VSS

M9

VSS

J2

VSS

P9

VSS

G8

VSS

B3

VSS

T1

VSS

A9

VSS

T9

VSS

E1

VSS

P1

VSS

G1

VSSQ

F9

VSSQ

E8

VSSQ

E2

VSSQ

D8

VSSQ

D1

VSSQ

B9

VSSQ

B1

VSSQ

G9

VSSQ

P/N:72.41164.H0U P/N:72.51G63.C0U

SC-1203-2 change U8401, U8402 to ZZ.00PAD.R01 for layout

4

M

DA17

M

DA18 DA19

M M

DA22

M

DA20

M

DA21

M

DA16

M

DA23

M

DA13 DA14

M M

DA9

M

DA8 DA12

M M

DA11 MDA15 MDA10

QSA1 QSA#1

QSA2 QSA#2

FBA_CMD_30

FBA_CMD_29 MEM_RST

12

R8410

R8410 10KR2J-3-GP

10KR2J-3-GP

Added MEN_RST 10K pull down R 2009/05/28

QSA1 [83] QSA#1 [83]

QSA2 [83] QSA#2 [83]

FBA_CMD_29 [83]

MEM_RST [8 3,85]

M

DA[0..63] [83,85]

M

DA[0..63] [83,85]

MA

U swap for layout

FBA_CMD_30 [83] FBA_CMD_30 [83]

12

R8409

10KR2J-3-GP

Revised FBCLK Termination resistor value 2009/06/05

CLKA0

CLKA0#

EC8401

SC6D8P50V2CN -GP

12

R8418

R8418 243R2F-2-GP

243R2F-2-GP

Close to VRAM side

1.5V_RUN_GPU

+

12

R8403

1KR2F-3-GP

12

R8402

1KR2F-3-GP

UMA swap for layout

3

+

1.5V_RUN_GPU

U

8402

K8

V

DD

K2

V

DD

N1

V

DD

R9

V

DD

B2

V

DD

D9

DD

V

G7

V

DD

R1

V

DD

N9

DD

V

A8

DDQ

V

A1

V

DDQ

C1

V

DDQ

C9

DDQ

V

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

MAA0 MAA1 FBA_CMD_22 FBA_CMD_24 FBA_CMD_0 FBA_CMD_2

MAA6 MAA7 MAA8

MAA9 MAA10 MAA11 MAA12 MAA13

BA0 BA1 BA2

CLKA0 CLKA0#

FBA_CMD_18

DQMA#0

WE# CAS# RAS#

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

DUMMY-K4W 1G1646E-HC12-GP

C8421

FBA_CMD_22[83] FBA_CMD_24[83]

FBA_CMD_0[83]

SCD01U16V2KX-3GP

FBA_CMD_2[83]

FBA_CMD_18[83]

DQMA#3[83]DQMA#1[83] DQMA#0[83]

R8407 243R2F -2-GPR8407 243R2F-2-GP

MAA0[83,85] MAA1[83,85]

MAA6[83,85] MAA7[83,85] MAA8[83,85]

MAA9[83,85] MAA10[83,85] MAA11[83,85] MAA12[83,85] MAA13[83,85]

BA0[83,85] BA1[83,85] BA2[83,85]

CLKA0[83] CLKA0#[83]

WE#[83,85] CAS#[8 3,85] RAS#[8 3,85]

12

1 2

D D D D D D D D

D D D D D DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

RESET#

NC#T7 NC#L9 NC#L1

NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

QL0

F7

QL1

F2

QL2

F8

QL3

H3

QL4

H8

QL5

G2

QL6

H7

QL7

D7

QU0

C3

QU1

C8

QU2

C2

QU3

A7

QU4

A2 B8 A3

C7 B7

F3 G3

K1

ODT

L2

CS#

T2

T7 L9 L1 J9 J1

J8

VSS

M1

VSS

M9

VSS

J2

VSS

P9

VSS

G8

VSS

B3

VSS

T1

VSS

A9

VSS

T9

VSS

E1

VSS

P1

VSS

G1 F9 E8 E2 D8 D1 B9 B1 G9

M

DA7

M

DA6 DA3

M M

DA0

M

DA1

M

DA2

M

DA5

M

DA4

M

DA29 DA24

M M

DA30

M

DA28 DA25

M M

DA26 MDA31 MDA27

QSA3 QSA#3

QSA0 QSA#0

FBA_CMD_30

FBA_CMD_29

MEM_RST

2

M

DA[0..63] [83,85]

M

DA[0..63] [83,85]

U

MA

swap for layout

QSA3 [83] QSA#3 [83]

QSA0 [83] QSA#0 [83]

FBA_CMD_29 [83]

MEM_RST [8 3,85]

1

+1.5V_RUN_GP U

12

C8422

B B

+1.5V_RUN_GP U

12

C8404

Place under / near VRAM Place under / near VRAM

12

C8423

SC1U10V3KX-3GP

12

C8408

SCD1U10V2KX-4GP

12

C8424

C8425

SC1U10V3KX-3GP

12

C8410

C8411

C8412

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

+1.5V_RUN_GP U

12

C8426

+1.5V_RUN_GP U

12

C8405

12

C8427

SC1U10V3KX-3GP

12

C8409

SCD1U16V2KX-3GP

12

C8428

C8429

SC1U10V3KX-3GP

12

SCD1U16V2KX-3GP

SC1U10V3KX-3GP

12

C8414

C8415

C8413

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP

Revised decoupling C 2009/05/28Revised decoupling C 2009/05/28

A A

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

VRAM(1/2)

Winery13 MB DIS

1

A00

84 88Wednesd ay, January 13, 2010

A00

5

SID = VIDEO

S

+

1.5V_RUN_GPU

U

8501

K8

V

DD

K2

V

DD

N1

V

DD

R9

V

DD

B2

DD

V

D9

V

DD

G7

V

DD

ZQ_VRAM21

MAA0 MAA1

FBA_CMD_6 FBA_CMD_5 FBA_CMD_13 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13

BA0 BA1 BA2

CLKA1 CLKA1#

FBA_CMD_7

DQMA#6 DQMA#5

WE# CAS# RAS#

R1

DD

V

N9

V

DD

A8

V

DDQ

A1

V

DDQ

C1

DDQ

V

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

DUMMY-K4W 1G1646E-HC12-GP

DQSU#

RESET#

D D

+

1.5V_RUN_GPU

12

R8510

1KR2F-3-GP

VREFA3

12

8503

8503 C

R8508

10KR2J-3-GP

C

12

SCD01U16V2KX-3GP

12

EC8501

SC6D8P50V2CN -GP

R8507

1KR2F-3-GP

C C

FBA_CMD_7[83]

Added CKE 10K pull down R 2009/06/05

1 2

R8509 243R2F -2-GPR8509 243R2F-2-GP

MAA0[83,84] MAA1[83,84]

FBA_CMD_6[83] FBA_CMD_5[83]

FBA_CMD_13[83]

MAA6[83,84] MAA7[83,84] MAA8[83,84]

MAA9[83,84] MAA10[83,84] MAA11[83,84] MAA12[83,84] MAA13[83,84]

BA0[83,84] BA1[83,84] BA2[83,84]

CLKA1[83] CLKA1#[83]

DQMA#6[83] DQMA#5[83]

WE#[83,84] CAS#[83 ,84] RAS#[83 ,84]

M

DA46

E3

D

QL0

DA42

M

F7

D

QL1

M

DA43

F2

D

QL2

M

DA40

F8

D

QL3

M

DA45

H3

QL4

D

M

DA41

H8

D

QL5

M

DA47

G2

D

QL6

DA44

M

H7

QL7

D

D D D D DQU4 DQU5 DQU6 DQU7

DQSU

DQSL

DQSL#

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

ODT

DA51

M

D7

QU0

M

DA52

C3

QU1

M

DA54

C8

QU2

DA49

M

C2

QU3

M

DA48

A7

MDA50

A2

MDA55

B8

MDA53

A3

C7 B7

F3 G3

FBA_CMD_28

K1

FBA_CMD_8FBA_CMD_4

L2

CS#

MEM_RST

T2

T7 L9 L1 J9 J1

J8

VSS

M1

VSS

M9

VSS

J2

VSS

P9

VSS

G8

VSS

B3

VSS

T1

VSS

A9

VSS

T9

VSS

E1

VSS

P1

VSS

G1 F9 E8 E2 D8 D1 B9 B1 G9

SC-1203-2 change U8501, U8502 to ZZ.00PAD.R01 for layout

QSA6

QSA#6

QSA5

QSA#5

4

FBA_CMD_8 [8 3]FBA_CMD_4[83]

MEM_RST [8 3,84]

QSA6 [83]

QSA#6 [83]

QSA5 [83]

QSA#5 [83]

10KR2J-3-GP

M

DA[0..63] [83,84]

M

DA[0..63] [83,84]

12

EC8502

R8506

SC6D8P50V2CN -GP

CLKA1

CLKA1#

Revised FBCLK Termination resistor value 2009/06/05

Close to VRAM side

FBA_CMD_28 [83]

12

R8517

R8517 243R2F-2-GP

243R2F-2-GP

R8501

1KR2F-3-GP

R8504

1KR2F-3-GP

+

1.5V_RUN_GPU

12

3

1.5V_RUN_GPU

+

U

8502

K8

V

K2

V

N1

V

R9

V

B2

V

D9

V

G7

V

R1

V

N9

V

A8

V

A1

V

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VREFA4

ZQ_VRAM22

1 2

12

C8506

SCD01U16V2KX-3GP

R8503 243R2F -2-GPR8503 243R2F-2-GP

MAA0[83,84]

MAA1[83,84] FBA_CMD_4[83] FBA_CMD_6[83] FBA_CMD_5[83]

FBA_CMD_13[83]

MAA6[83,84]

MAA7[83,84]

MAA8[83,84]

MAA9[83,84]

MAA10[83,84] MAA11[83,84] MAA12[83,84] MAA13[83,84]

BA0[83,84] BA1[83,84] BA2[83,84]

CLKA1[83] CLKA1#[83]

FBA_CMD_7[83]

DQMA#4[83] DQMA#7[83]

WE#[83,84] CAS#[8 3,84] RAS#[8 3,84]

MAA0 MAA1 FBA_CMD_4 FBA_CMD_6 FBA_CMD_5 FBA_CMD_13 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13

BA0 BA1 BA2

CLKA1 CLKA1#

FBA_CMD_7

DQMA#4 DQMA#7

WE# CAS# RAS#

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

DUMMY-K4W 1G1646E-HC12-GP

D

DD

QL0

D

DD

QL1

D

DD

QL2

DD

QL3

D D

DD

QL4

D

DD

QL5

DD

QL6

D D

DD

QL7

DD

D

QU0

D

DDQ

QU1

DDQ

QU2

D DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

ODT

CS#

RESET#

NC#T7

NC#L9 NC#L1 NC#J9 NC#J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

DA[0..63] [83,84]

QSA4 [83]

QSA#4 [83]

QSA7 [83]

QSA#7 [83]

FBA_CMD_28 [83]

FBA_CMD_8 [83]

MEM_RST [8 3,84]

M

DA[0..63] [83,84]

DA63

M

E3

M

DA59

F7

M

DA60

F2

M

DA61

F8

M

DA57

H3

M

DA58

H8

DA62

M

G2

M

DA56

H7

M

DA36

D7

M

DA38

C3

DA33

M

C8

M

DA39

C2

MDA34

A7

MDA37

A2

MDA32

B8

MDA35

A3

QSA4

C7

QSA#4

B7

QSA7

F3

QSA#7

G3

FBA_CMD_28

K1

FBA_CMD_8

L2

MEM_RST

T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

1

+1.5V_RUN_GP U

12

C8531

B B

+1.5V_RUN_GP U

12

C8520

Revised decoupling C 2009/05/28

A A

5

12

C8532

SC1U10V3KX-3GP

12

C8518

C8519

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP

Place under / near VRAM

12

C8533

C8534

SC1U10V3KX-3GP

+1.5V_RUN_GP U

12

SCD1U16V2KX-3GP

12

C8516

C8517

SCD1U16V2KX-3GP

EC8503

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP

+1.5V_RUN_GP U

12

C8535

+1.5V_RUN_GP U

12

C8525

12

C8536

SC1U10V3KX-3GP

12

C8523

C8524

SCD1U16V2KX-3GP

Place under / near VRAM

12

C8538

C8537

SC1U10V3KX-3GP

12

C8522

C8521

SCD1U16V2KX-3GP

Revised decoupling C 2009/05/28

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

VRAM

Winery13 MB DIS

1

A00

85 88Wednesd ay, January 13, 2010

A00

5

S

SID = PWR.Plane.Regulator_GFX

+

PWR_SRC+PWR_SRC_GFX_CORE_

D D

C C

G8617

P

1 2

GAP-CLOSE-PWR

P

G8613

1 2

GAP-CLOSE-PWR

PG8620

1 2

GAP-CLOSE-PWR

PG8605

1 2

GAP-CLOSE-PWR

PG8611

1 2

GAP-CLOSE-PWR

GFX_CORE_EN[37]

+3.3V_RUN_GPU

12

PR8634

PR8634 100KR2J-1-GP

100KR2J-1-GP

DY

GFX_CORE_PGOOD[25]

SB-1103

PR8632

1 2

73K2R2F-GP

PR8631

1 2

1KR2F-3-GP

PR8638

PM_SLP_S3#[22,34,37,42,50,51]

1 2

DY

100KR2J-1-GP

12

PC8634

SC1KP50V2KX-1GP

+GFX_CORE_TRIP +GFX_CORE_EN +GFX_CORE_FB +GFX_CORE_CCM

PR8604

PR8604 470KR2F-GP

470KR2F-GP

1 2 3 4 5

PU8603

PGOOD TRIP EN VFB CCM

Frequency setting 470K -->290KHz 200K -->340KHz 100K -->380KHz

B B

A A

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 1.5UH PCMC104T-1R5MN Cyntec DCR:4.2mohm Isat =33Arms 68.1R510.10J O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3Arms Panasonic/ 79.33719.L01 H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 Switching freq-->350KHz

39K -->430KHz

5

PWRCNTL_0

H

PWRCNTL_1

4

11

GND

10

VBST

9

DRVH

8

SW

7

V5IN

6

DRVL

TPS51218DSCR-GP-U1

+VCC_GFX_CORE

4

+GFX_CORE_VBST +GFX_CORE_DRVH +GFX_CORE_SW

+GFX_CORE_DRVL

1.03VH

0.85VL

PR8633

2D2R3J-2-GP

1 2

SI7686DP-T1-GP

PC8616

SCD1U25V3KX-GP

+GFX_CORE_VBST1

12

SCD1U25V3KX-GP

12

+5V_ALW

PC8617

SC1U10V2KX-1GP

SB-1023

1. DY PD8601, PR8614, PR8618, PC8610, PQ8602, PR8613; change PR8611 to 24.3K, PR8607 to 20K. for N11M A3 change P12 stey Voltage to 0.85V

+3.3V_RUN_GPU

12

PR8619

10KR2F-2-GP

PWRCNTL_0[81]

+3.3V_RUN_GPU

12

2009/08/05

PR8620

10KR2F-2-GP

PWRCNTL_1[81]

10KR2F-2-GP

SC-1204-5 add PR8621 pull low 10K R

PR8621

DY

12

3

+

PWR_SRC_GFX_CORE_

678

PU8601

4 5

678

DDD

PU8604

SIR460DP-T1-GE3-GP

G

4 5

PD8601

K A

DY

B0530WS-7-F-GP

10KR2F-2-GP

PD8615

K A

B0530WS-7-F-GP

3

DDD S

SSGD

123

D

SSS

123

2009/08/05

PD8601_A

PR8618

12

DY

PR8617

10KR2F-2-GP

PD8615_A

12

PC8611

1 2

DY

PR8614

PR8614 5K1R2F-2-GP

5K1R2F-2-GP

PWRCNTL_0_R

12

1 2

PR8615

PR8615 5K1R2F-2-GP

5K1R2F-2-GP

SC10U25V6KX-1GP

12

PC8606

SC10U25V6KX-1GP

12

DY

PC8610

SCD1U16V2KX-3GP

PWRCNTL_1_R

12

SC10U25V6KX-1GP

12

PR8606

DY

2D2R5F-2-GP

+GFX_CORE_LL_R

12

PC8614

PC8614 SC330P50V3KX-GP

SC330P50V3KX-GP

DY

G

PR8602

1 2

100KR2J-1-GP

12

PC8604

PC8609

SCD1U50V3KX-GP

PL8601

1 2

IND-1D5UH-34-GP

12

PR8613

DY

75KR2F-GP

PWRCNTL_0#

PQ8602

PQ8602 2N7002A-7-GP

2N7002A-7-GP

DY

S D

2009/08/05

DY

PC8608

12

PC8603

12

SCD1U16V2KX-3GP

2

SC2200P50V2KX-2GP

12

PG8604

GAP-CLOSE-PWR-3-GP

GPU_VDD_SENS_GAP

12

PR8603

PR8603 5K1R2F-2-GP

5K1R2F-2-GP

+GFX_CORE_FB

12

PR8611

PR8611 24K3R2F-1-GP

24K3R2F-1-GP

G

DY

PR8616

1 2

100KR2J-1-GP

2

out=0.704V*(R1+R2)/R2

V

DIS Thermal Design Current = 12.9A Max Current = 16.77A

18.45A<OCP<21.81A

+VCC_GFX_COREP

12

PTC8601

12

PTC8602

SE330U2VDM-L-GP

DY

12

PC8602

SCD1U10V2KX-4GP

12

PR8607

PR8607 20KR2F-L-GP

20KR2F-L-GP

2009/08/26

PWRCNTL_1#

PQ8601

PQ8601 2N7002A-7-GP

2N7002A-7-GP

S D

1st Samsung

Title

Size Document Number Rev

Custom

Date: Sheet of

1

+VCC_GFX_CORE

PG8601

12

GAP-CLOSE-PWR

PG8619

12

GAP-CLOSE-PWR

PG8618

12

GAP-CLOSE-PWR

PG8622

1 2

GAP-CLOSE-PWR

PG8612

1 2

GAP-CLOSE-PWR

PG8621

1 2

GAP-CLOSE-PWR

PG8614

1 2

GAP-CLOSE-PWR

PG8607

1 2

GAP-CLOSE-PWR

PG8606

1 2

GAP-CLOSE-PWR

PG8608

1 2

GAP-CLOSE-PWR

PG8602

1 2

GAP-CLOSE-PWR

PG8615

1 2

GAP-CLOSE-PWR

PG8610

1 2

GAP-CLOSE-PWR

PG8609

1 2

GAP-CLOSE-PWR

PG8603

1 2

GAP-CLOSE-PWR

PG8616

1 2

GAP-CLOSE-PWR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

TPS51218 +VCC_GFX_CORE

Winery13 MB DIS

86 88Wednesday, January 13, 2010

1

A00

5

D D

4

3

2

1

SSID = VIDEO

C C

+3.3V_RUN_GPU

3.3V_RUN_GPU_EN[37]

C8786

C8786 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+1.05V_GFX_PCIE:

+1.5V_RUN_GPU:

B B

+3.3V_RTC_LDO

D8706

A K

BAS16XV2T1G-GP-U

R8778

R8778 2KR2F-3-GP

2KR2F-3-GP

12

+3.3V_RTC_LDO

assign GPIO 2009/05/28

1.05V_GFX_ON[37]

+3.3V_RTC_LDO

1D5V_VGA_ON[37]

R8714

R8714 100KR2J-1-GP

100KR2J-1-GP

1 2

3D3V_VGA_ON#

DMN66D0LDW-7- GP

12

R8712

R8712 100KR2J-1-GP

100KR2J-1-GP

1 2

1D05V_VGA_ON#

DMN66D0LDW-7- GP

R8715

R8715 100KR2J-1-GP

100KR2J-1-GP

1 2

1D5V_VGA_ON#

DMN66D0LDW-7- GP

Q8707

3.3V_GPU_EN_R

Q8704

1.05V_GFX_ON

Q8705

1D5V_VGA_ON

5

6

123 4

6

123 4

6

123 4

+15V_ALW

RUN_ON_3D3GFX

12

C8701

12

C8705

C8702

12

C8707

+3.3V_RUN_GPU

12

+1.05V_GFX_PCIE

12

+1.5V_RUN_GPU

12

R8711

R8711 100KR2J-1-GP

100KR2J-1-GP

1 2

RUN_ON_3D3GFX_R

+15V_ALW

R8708

R8708 100KR2J-1-GP

100KR2J-1-GP

5

1 2

RUN_ON_1D05V_R RUN_ON_1D05V

Added discharge circuit 2009/06/17

+15V_ALW

R8710

R8710 100KR2J-1-GP

100KR2J-1-GP

1 2

RUN_ON_1D5V_R RUN_ON_1D5V

1D5V_VGA_ON#

+1.5V_RUN_GPU

DY

Q87_D

1 2

DY

G

S D

C8704

C8704 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

R8713

R8713 10KR2J-3-GP

10KR2J-3-GP

C8708

C8708 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SC10U6D3V5KX-1GP

R8716

10KR2J-3-GP

SCD01U50V2KX-1GP

R8709

Place near devic e side(VGA chip ),

100R2J-2-GP

use 10 mil trace between power rail and Q8701 D rain

Q8701

Q8701 2N7002-7F-GP

2N7002-7F-GP

SC10U6D3V5KX-1GP

R8717

10KR2J-3-GP

SCD01U50V2KX-1GP

Peak current:360mA Design current: 252mA

+3.3V_ALW

Q8710

AO3434L-GP

DS

AO3434L-GP MAX 4 .2A

G

Rds(on) = 52 mOh m (Max)

Peak current: 3550mA Design current:3550mA

U8703

S

1

S

2

S

3

G D

4 5

FDS8880-NL-GP

10.7A Rds=12m ohm

U8705

S

1

S

2

S

3

G D

4 5

FDS8880-NL-GP

10.7A Rds=12m ohm

+1.05V_VTT

D

8

D

7

D

6

1ST: 84.08880.037 2ND: 84.04406.B37

Peak current:4230mA Design current:2961mA

+1.5V_SUS

D

8

D

7

D

6

1ST: 84.08880.037 2ND: 84.04406.B37

1ST: 84.03434.031 2ND:

A A

1st Samsung

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

LDO 1.8V

1

A00

87 88W ednesday, January 13, 2010

A00

5

equest By

age#Item

P

02 EE60 External MIC NG. Add caps C6014 C6015. SB 03 EE66 Correct battery LED color. Swap LED6601 pin2 & pin3. SB 0

4 49 EE Improve VTT_PWRGD ramp up signal. Dummy C4912. SB

D D

05 51 2009/10/08 EE Fine tune +1.8V_RUN power on sequence behind +3.3V_RUN.

ate

D

2

009/10/08 2009/10/08 2009/10/08 2009/10/08

R

E

E01 66 HDD LED light in S5. Change HDD LED power rail from +5V_ALW to +5V_RUN. SB

4

3

Change PR5102 from 2.2K to 3K and PC5105 from 4700pF to 1uF.

2

1

ev.Solution DescriptionIssue description

R

SB

2009/10/0806 54,78 EE For KBC ESD protect. Add 100 ohm resistances R5413, R7803. SB

07

2009/10/0808 30 EE Change CODEC to 92HD79. SB

09 64 2009/10/08 EE By ME request Change WLAN1 to 62.10043.841. SB 10 11 37 2009/10/09 EE Change board ID. Dummy R3708 and pop R3701. SB 12 79 2009/10/12 ME By ME request Change H6 to ZZ.00PAD.F91 SB 13 14 15 16 17 18 24 2009/10/12 EE Change C2402, C2403 to 12pFXTAL Load Capacitance as Vendor suggestion SB

C C

19 81 2009/10/12 EE Change C8135, C8138 to 15pF SBXTAL Load Capacitance as Vendor suggestion

78 27 2009/10/12 EE Remove L2701, C2701, C2702; Add TP2701 27 2009/10/12 EE Remove L2704, C2721, C2722; Add TP2702 27 2009/10/12 EE Cost down SBChange L2702, L2703 to 68.10050.10Y

20 26 2009/10/13 EE

2009/10/12 ME By ME request Change H10 to ZZ.00PAD.D4179 2009/10/12 ME By ME request

Follow Intel spec Follow Intel spec

Follow Intel spec Remove L2602, C2616; Add TP2601 SB

Change FP1 to 20.K0315.005

SB SB SB SB

SB21 26 2009/10/13 EE Follow Intel spec Remove L2601, C2606; Add TP2602 22 37 2009/10/13 EE Modify 10mW schematic SB 23 79 2009/10/13 ME By ME request SBRemove H9 (BT BOSS)

24 49 2009/10/13 EE By PSE request SB

Change pg4910~pg4918 and pg4921

close gap to mask type 25 Two AFTP for +3.3V_RUNEE Remove AFTP6030 SB73 2009/10/13 26 ME change NEW1 connector to 20.K0370.02634 2009/10/14 SBBy ME request

ME7927 SBBy ME request2009/10/14 change SPR5 to 34.4F822.002 28 64 2009/10/14 EE SBAdd AFTP6402, AFTP6403By AFTE request 29 79 2009/10/16 EE By RF request SBAdd Cross Moat Caps 30 80,81 2009/10/16 EE Voltage Drop over 3% SBchange bead value to 120 ohm DCR 0.55 ohm

EE2009/10/162231 SBRTC data loss Added 3v/5v S5 power good to control resume reset

B B

sequence prevent RTC data loss 2009/10/16 EE32 25 SBSwapped Q2515 C,E Pin 2009/10/16 EE33 78 remove CAPA_RST# from capacity board SB 2009/10/1634 37 EE Added Switch Baord Detection circuit SBBy SW request

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

Change List(1/3)

88 88Wedn esday, January 13, 2010

1

A00

5

equest By

ate

D

2

009/11/1801 EE 2009/11/25 2009/11/25

0 03

age#Item

P

37 Correct R3745 power rail to KBC_PWR

2

36 TPM connector needn't AFTE test point

04 0

5

D D

06 07 08

7 For solve WiMAX noise 43

46 09 10 11 12 13 14 15 16 17

18

C C

19 20

79 For one hand hold issue, ODD have noise

79

55 By EMI requirement

79

81

47

79

30

86 Set PWRCNTL_1 for default low.

12

2009/11/25 2009/11/30 2009/11/30 2009/11/30 2009/11/30 2009/11/30 2009/11/30 2009/11/30 2009/12/04 2009/12/04 2009/12/04 2009/12/04 2009/12/04

2009/12/04 2009/12/04 2009/12/07

R

EE EE EE2009/11/25 E

E RF RF RF EE ME RF RF EMI EMI EMI ME ME

EE EE EMI

4

3

No support HDMI and eDP so needn't pop 25MHz Xtal of PCH.23 Toggle VGA mode will flicker white screen in hybrid mode.37 Toggle VGA mode will flicker white screen in hybrid mode.54

For solve WiMAX noise For solve WiMAX noise For combine material item47

For solve WWAN noise For solve WiMAX noise

By EMI requirement By EMI requirement For cosmatic issue when insert 8 cell battery For cosmatic issue when insert 8 cell battery Base on Application Note: IDT 92H81/79 AUX Mode as input of Diagnostic sound.

By EMI requirement

2

1

Change R3745 power rail to KBC_PWR Remove TPM1 AFTP C2313 pop 0 ohm if no use 25MHz XTAL Add U3703 mux for panel backlight enable signal select Add mux U5446 to select LCDVDD enable signal

hange C701 to 4.7pF for RF

C Pop PC4303 for RF Change PC4601 pull up to +5V_ALW for layout. Change PC4762 to 0603 size Add H15 for ME Add RC7931 for RF Add SPR6 for RF Change L5501,L5502,L5503 for EMI Add EMI caps Add EC8101,EC8102,EC8103 for EMI Remove TC4701 for layout Change H2 to ZZ.00PAD.D11 Connect U3001 pin17, pin18 to pin12 net and change R3016 to 120K for vendor request Add PR8621 pull low 10K ohm Pop C1243 and change size to 0603 for EMI

ev.Solution DescriptionIssue description

R

SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC

SC SC SC

Pop C3301, EC3302, EC3303, EC3305, EC3306, EC3307, 21 22 23 24 25 26 27 28

33 54 60 63 79 24 Base on EA teset result, change to 0 ohm. 53

60 29 30

68 31

B B

2009/12/07 2009/12/07 2009/12/07 2009/12/07 2009/12/07 2009/12/08 2009/12/08 2009/12/08 2009/12/08 2009/12/08 2009/12/08

EMI EMI EMI EMI ME EE EE EE EE EE EMI

By EMI requirement By EMI requirement By EMI requirement By EMI requirement For cosmatic issue when insert 8 cell battery

Base on ARD_Sightings_Report_18 #3622146 Audio AP LO THD+N fail Base on EA teset result, change to 0 ohm.62 Change PCB Footprint By EMI requirement73

EC3308 and change from 100p to 6.8p for EMI Pop EC5403 for EMI Pop EC6001 and EC6002 for EMI Pop R6307 for EMI Add H16 for ME Change R2413,R2414,R2415 from 15ohm to 0 ohm Change PR5311 from 4.7K to 470 ohm Change EC6004,EC6005 from 0.1U to 0.01U Change R6206 from 15ohm to 0 ohm Change Q6808 to 84.06402.B3D Pop L7301 for EMI

SC SC SC SC SC SC SC SC SC SC SC

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Change List(2/3)

Size Document N umber Rev

A3

Date: Sheet of

Change List(2/3)

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

88 88Wedn esday, January 13, 2010

1

A00

5

equest By

age#Item

P

2

0 03

37 Prevent SPI ROM data lost

46 changePL4602 from 2.2U to 3.3U 04 0

5

D D

06 07 08 09 10 11 12 13 14 15 16

52 PREVNET MOS DEMAGE

53

55

62

63

64

73

78

ate

D

2

010/01/0701 EE

2010/01/05

2009/12/18 EE46 pop PR4619; dummy PR4618TO improve +15V_Pump Power on issue 2010/01/07 2009/12/23 2009/12/18 By POWER requirement

2009/12/18

2009/12/23 EE TO PREVENT power pin short to GND when plug in cable

R

EE EE2009/12/18 EE EE EE EE EMI EMI EMI ME ME EE EE

17 18 change SPR5 from 34.4F822.002 to 34.42T14.002

C C

79

4

3

remove R3402, R340334 For no co-lay after XB Add reset IC U3704

By POWER requirement

To prevent PM_SLP_S3# signal rebound51

change R5102 to short pad, PC5105 to 10K Change C701 to 4.7pF for RF

change PR5314 from 5.9K to 6.2K By EMI requirement2009/12/18 By EMI requirement2009/12/18 By EMI requirement By ME requirement2010/01/04 By ME requirement2010/01/04 For no co-lay after XB2010/01/06 For no co-lay after XB2010/01/07 For no co-lay after XB2010/01/07 EE

change L5501, L5502, L5503 to 0R

change R5504, R5505, R5506 from 0R to 33R

change C5520 from 22p to 10p

change CRT1 from 20.20431.015 to 20.20401.015

change RCT1 from 20.D0210.102 to 20.D0075.102

remove R6302, R6308,TR6301,TR6302, TR6303

remove L6401

remove R7302, R7303

dummy FP1 pin6, pin7 add damping resister R7804EE2009/12/2378 add R7804 By ME requirementME2010/01/05

2

1

ev.Solution DescriptionIssue description

R

A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00

B B

A A

5

4

3

2

1st Samsung

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Change List(3/3)

Size Document N umber Rev

A3

Date: Sheet of

Change List(3/3)

Winery13 MB DIS

Taipei Hsien 221, Taiwan, R.O.C.

88 88Wedn esday, January 13, 2010

1

A00

Wistron Winery13 Calpella Dis N11M-GE1 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual