5
D D
4
3
2
1
Winery13 CALPELLA DIS N11M-GE1 Schematics
uFCPGA Mobile Arrandale
Intel Ibex Peak-M
C C
2010-01-13
REV : A00
B B
DY : Nopop Component
UMA : Pop when schematic is UMA
DIS : Pop when schematic is DIS
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
Taipei Hsien 221, Taiwan, R.O.C.
Cover Page
Cover Page
Cover Page
1
1 88 Wednesday, January 13, 2010
1 88 Wednesday, January 13, 2010
1 88 Wednesday, January 13, 2010
A00
A00
A00
5
inery CALPELLA Block Diagram
W
P
CB LAYER
L1: Top
L2: GND
L
D D
3: Signal
L4: Signal
L5: VCC
L6: Signal
L7: GND
Clock Generator
SLG8SP585
4
7
3
P
roject code : 91.4EX01.001
Part Number : 48.4EX01.001
PCB P/N : 09288
Revision : A00
2
1
PU DC/DC
C
SL62883
I
R
T8205B
O
+
+15V_ALW
+3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW
I
NPUTS
+
PWR_SRC
S
YSTEM DC/DC
NPUTS
I
+PWR_SRC
UTPUTS
VCC_CORE
UTPUTS
O
4
7,48
4
6
L8: Bottom
100MHz/
74
2.5Gbps
Bandwidth
:8GB
RGB CRT
LVDS
PCIe x 16
2.5 GT/s 2.7 GT/s
RGB CRT
LVDS
VRAM(gDDR3)
64Mbx16x4 (512MB)
C C
LCD
(Single Chanel)
CRT
4
84,85
RGB CRT
55
LVDS
54
Nvidia
VRAM
N11M-GE1(40nm)
Switchable
LVDS
80,81,82,83
RGB CRT
Intel CPU
Arrandale
8,9,10,11,12,13,14
DMIx4 FDI(UMA)
Intel
PCH
CardReader
(3 in 1)
SD/MMC/MMC+
B B
CAMERA
73
33
REALTEK
RTS5138
USB2.0 x 1
USB 2.0
480Mbps
32
14 USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb)
High Definition Audio
SATA ports (6)
PCIE ports (8)
LPC I/F
ACPI 1.1
PCI/PCI BRIDGE
DDRIII 1066 Channel A
800/1066MHz
DDR III 1066 Channel B
800/1066MHz
PCIE x 1
100MHz
2.5Gbps
PCIE
USB 2.0
480Mbps
SM Bus
400KHz
LPC Bus
DDRIII
1066
DDRIII
1066
PCIE x 1 & USB 2.0 x 1
10/100/1000LOM
RTL8111DL
(On daughter board)
Free fall sensor
33MHz
Digital Mic Array
Azalia
CODEC
MIC IN
OP AMP
HP OUT
A A
1CH SPEAKER
60
5
IDT
92HD81UA
30
AZALIA
24MHz
4
USB,ESATA
Multi-Port x1
20,21,22,23,24 ,25,26,27,28
SATA
SATA,USB
ODD
HDD
63
59
3Gbps
SPI
Flash ROM
4MB
62
SPI
Flash ROM
256kB
3
KBC
NUVOTON
NPCE781BA0DX
Touch
PAD
62 68
Int.
KB
68
37
USB 2.0 x 2
SM Bus
Slot 0
18
Slot 1
19
35
USB 2.0 x 1
40
Thermal & Fan
EMC2102
Capacity Board
2
(FPC Cable to Connect)
PCIE x 1
USB 2.0 x 1
PCIE x 1
USB 2.0 x 1
USB 2.0 x 1
USB 2.0 x 1
39,58
78
SYSTEM DC/DC
Power SW
TPS2231R
New Card
RJ45
CONN
Mini-Card
WWAN/ WiMAX?
Left Side:
USB x 1
34
34
TPS51116
OUTPUTS INPUTS
+PWR_SRC
+1.5V_SUS
+0.75V_DDR_VTT
+V_DDR_REF
SYSTEM DC/DC
ADP3211
OUTPUTS INPUTS
+PWR_SRC +CPU_GFXCORE
SYSTEM DC/DC
TPS51218
INPUTS
+PWR_SRC
OUTPUTS
+VCC_GFX_CORE
CHARGER
Mini-Card
WLAN 802.11a/b/g/n
Right Side:
USB x 1
Bluetooth
Biometric
64
63
73
78
BQ24745
INPUTS
+DC_IN
+PBATT
OUTPUTS
+PWR_SRC
SYSTEM DC/DC
TPS51218
OUTPUTS INPUTS
+PWR_SRC
+1.05V_VTT
LDO
APL5930
INPUTS
OUTPUTS
+1.8V_RUN +3.3V_ALW
LDO
RT9025
2 88 Wednesday, January 13, 2010
2 88 Wednesday, January 13, 2010
2 88 Wednesday, January 13, 2010
OUTPUTS
+1.8V_RUN_GPU +3.3V_ALW
INPUTS
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
Taipei Hsien 221, Taiwan, R.O.C.
Block Diagram
Block Diagram
Block Diagram
1
50
53
86
45
49
51
51
A00
A00
A00
5
D D
PWR_SRC
A
dapter
AO4407A
45
+
Charger
BQ24745
Battery
+PBATT
45
RT8205B
C C
+5V_ALW
+15V_ALW
+5V_ALW2
+3.3V_ALW_2
+3.3V_RTC_LDO
4
ISL62883
+VCC_CORE
46
+5V_ALW
3
47、 48 86
ADP3211
53
+CPU_GFXCORE
TPS51218
+VCC_GFX_CORE
For NVIDIA GPU For Intel GPU
+3.3V_ALW
2
TPS51218DSCR
+1.05V_VTT
Arrandale : 1.05V
FDS8880
+1.05V_GFX_PCIE
87
1
PS51116PWPRG4
T
49
FDS8880
50
+0.75V_DDR_VTT +V_DDR_REF
87
+1.5V_SUS
+1.5V_RUN_GPU
AO3420
52
AO4468
42
+1.5V_CPU
+1.5V_RUN
TPS2062AD
+5V_USB2
B B
For USB2 For USB1 & ESATA1
AO4468
+5V_RUN
42 I/O BD
TPS2062AD
+5V_USB1
63
AO3403
+3.3V_LAN
RTL8111DL
I/O BD
+1.2V_LOM
TPS2231R
34
SI3456BDV
+LCDVDD
AO4468
+3.3V_RUN +3.3V_CARDAUX
54
APL5930
42
+1.8V_RUN
TPS2231R
+3.3V_CARD
RT9025
51
+1.8V_RUN_GPU
34
51 I/O BD
AO3434
+3.3V_RUN_GPU
87
TPS2231R
+1.5V_CARD
34
Power Shape
Regulator LDO Switch
A A
5
4
3
2
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Power Block Diagram
Power Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Power Block Diagram
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
Taipei Hsien 221, Taiwan, R.O.C.
3 88 Wednesday, January 13, 2010
3 88 Wednesday, January 13, 2010
3 88 Wednesday, January 13, 2010
1
A00
A00
A00
5
CH SMBus Block Diagram
P
3.3V_ALW
+
‧
S
RN2K2J-1-GP
P
CH
D D
MBCLK
S
SMBDATA
MB_CLK
S
SMB_DATA
23
‧
‧
2N7002SPT
+
3.3V_RUN
‧
3.3V_RUN
+
‧
‧
‧
‧
‧
‧
‧
S
PCH_SMBCLK
PCH_SMBDATA
PCH_SMBCLK
PCH_SMBDATA
PCH_SMBCLK
PCH_SMBDATA
Express
Card
SMB_CLK
SMB_CLK
SMB_DATA
SMB_DATA
C C
PCH_SMBCLK
‧
PCH_SMBDATA
‧
34
PCH_SMBCLK
‧
PCH_SMBDATA
‧
PCH_SMBCLK
‧
PCH_SMBDATA
‧
KBC SMBus Block Diagram
+5V_RUN
‧
SRN10KJ-5-GP
TPDATA
PSDAT1
TPCLK
B B
PSCLK1
+3.3V_RTC_LDO
‧
‧
‧
SRN4K7J-8-GP
BAT_SCL
SCL1
SDA1
BAT_SDA
‧
‧
‧
‧
SRN100J-3-GP
TouchPad Conn.
TPDATA
TPDATA
TPCLK
TPCLK
SMBus address:12
PBAT_SMBCLK1
PBAT_SMBDAT1
Battery Conn.
CLK_SMB
DAT_SMB
SMBus address:16
4
RN2K2J-1-GP
D
IMM 1
S
CL
SDA
MBus Address:A0
S
DIMM 2
SCL
SDA
SMBus Address:A2
Clock
Generator
SMBCLK
SMBDATA
SMBus address:D2
Minicard
WLAN
SMB_CLK
SMB_DATA
Minicard
WWAN
SMB_CLK
SMB_DATA
Free fall
sensor
SCL/SPC
SDA/SDI/SDO
BQ24745
SCL
SDA
3
witchable Graphic SMBus Block Diagram
S
+
+
3.3V_RUN
P
CH
RN2K2J-1-GP
S
L_DDC_CLK
L
DDC_CLK
L_DDC_DATA
LDDC_DATA
SRN2K2J-1-GP
GMCH_DDCCLK
CRT_CLK_DDC
I/O BD
18
19
07
64
40
L_DDC_CLK
L_DDC_DATA
CRT_DDC_CLK
CRT_DDC_DATA
N11M-GE1
I2CC_SCL
I2CC_SDA
68
45
44
I2CA_SCL
I2CA_SDA
GMCH_DDCDATA
CRT_DAT_DDC
‧
‧
‧
+3.3V_RUN
‧
‧
‧
3.3V_RUN
‧
‧
‧
+3.3V_RUN
‧
S
RN2K2J-1-GP
B
1
B0
GND
NC7SB3157P6X-1GP
B1
B0
GND
NC7SB3157P6X-1GP
‧
B1
B0
GND
NC7SB3157P6X-1GP
B1
B0
‧
GND
NC7SB3157P6X-1GP
+
3.3V_RUN
VCC
A
S
+3.3V_RUN
VCC
A
S
SRN2K2J-1-GP
+3.3V_RUN
VCC
DDC_CLK_CON2
A
S
+3.3V_RUN
VCC
DDC_DATA_CON2
A
S
2
+
3.3V_RUN
‧
SRN2K2J-1-GP
LDDC_CLK_CON
LDDC_DATA_CON
+3.3V_RUN
‧
‧
‧
DY
‧
‧
Remove HDMI
LCD Conn.
+3.3V_RUN_GPU
2N7002DW-1-GP
54
‧
DDC_CLK_CON
DDC_DATA_CON
+5V_CRT_RUN
‧
SRN2K2J-1-GP
‧
‧
1
CRT CONN
55
KBC
KBC_SCL1
KBC_SDA1
+3.3V_RTC_LDO
‧
SRN4K7J-8-GP
‧
‧
5
2N7002DW-1-GP
NPCE781
A A
GPIO73/SCL2
GPIO74/SDA2
+3.3V_RUN
‧
‧
+3.3V_RUN
‧
‧
SRN4K7J-8-GP
THERM_SCL
THERM_SDA
THERM_SCL
THERM_SDA
Thermal
SMCLK
SMDATA
SMBus address:7A
39
Capacity
Board
SCL
(On daughter board)
SDA
SMBus address:0A
4
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA#
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
SMBUS Block Diagram
SMBUS Block Diagram
SMBUS Block Diagram
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
Taipei Hsien 221, Taiwan, R.O.C.
4 88 Wednesday, January 13, 2010
4 88 Wednesday, January 13, 2010
4 88 Wednesday, January 13, 2010
1
A00
A00
A00
A
B
C
D
E
T
hermal Block Diagram
1 1
A
udio Block Diagram
SPEAKER
SPKR_PORT_D_L-
SPKR_PORT_D_L+
DP1
EMC2102_DP1
2 2
DN1
EMC2102_DN1
Thermal
SC470P50V3JN-2GP
Close to PCH
EMC2102
DP2
VGA_THERMDA
SC470P50V3JN-2GP
DN2
VGA_THERMDC
3 3
DPLUS
DMINUS
Q3905
GPU
MMBT3904-3-GP
54
DIS
HP1_PORT_B_L
HP1_PORT_B_R
Codec
92HD81
HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_OR_F
AUD_SPK_L-
AUD_SPK_L+
0R3-0-U-V-GP
AUD_HP1_JACK_L
AUD_HP1_JACK_R
AUD_EXT_MIC_L
AUD_EXT_MIC_R
AUD_VREFOUT_B
AUD_SPK_L-_C
AUD_SPK_L+_C
60
HP
OUT
60
MIC
IN
60
DP3
T8_THERMDC
DN3
T8_THERMDA
39
4 4
A
SC470P50V3JN-2GP
HW T8 sensor
B
MMBT3904-3-GP
Q3901
C
DMIC_CLK/GPIO1
DMIC0/GPIO2
AUD_DMIC_CLK
AUD_DMIC_IN0
30
33R2J-2-GP
33R2J-2-GP AUD_DMIC_IN0_R
D
AUD_DMIC_CLK_G
1st Samsung
1st Samsung
1st Samsung
Title
Title
Title
Thermal/Audio Block Diagram
Thermal/Audio Block Diagram
Thermal/Audio Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
Digital
MIC
Array
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
E
73
5 88 Wednesday, January 13, 2010
5 88 Wednesday, January 13, 2010
5 88 Wednesday, January 13, 2010
A00
A00
A00
A
CH Strapping
P
N
ame
S
PKR
4 4
GNT3#/
GPIO55
INTVRMEN
GNT0#,
GNT1#
GNT2#/
GPIO53
3 3
SPI_MOSI
NV_ALE
HAD_DOCK_EN#
/GPIO[33]
2 2
HDA_SDO
HDA_SYNC
GPIO15
S
chematics Notes
Reboot option at power-up
Internal weak P ull-down.
Default Mode:
Connect to Vcc3_3 with 8. 2-kΩ
No Reboot Mode with TCO Disab led:
- 10-kΩ weak pull-up resistor.
nternal pull-up. Leave as "No Connect" INIT3_3V#
I
Internal pull-u p.
Default Mode:
Low (0) = Top Block Swap Mode
Note: Connect to ground with 4.7-k
CRB uses a 1 k
High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is d isabled
Note:
CRB uses a 330-kΩ resistor.
Leave both GNT 0# and GNT1# floating. No pull up
Default (SPI):
required.
Boot from PCI:
Connect both G NT0# and GNT1# to ground with 1-kΩ
Boot from LPC:
pull-down resistor.
Default - Internal pull-up.
= Configures DMI for E SI compatible operation (for s ervers
Low (0)
only. Not for mobile/desktops ).
Connect to Vcc3_3
Enable Intel Anti-Theft Techn ology:
with 8.2-kΩ weak pull-up resis tor.
Left floating, no pull- down
Disable Intel Anti-Theft Tech nology:
required.
Connect to +NVRAM_Vccq w ith
Enable Intel Anti-Theft Techn ology:
8.2-kΩ weak pull-up resistor.[ CRB has it pulled up with 1-kΩ
no-stuff resistor]
Leave floating (interna l pull-down)
Disable Intel Anti-Theft Tech nology:
DMI termination voltage. Weak internal pull-up. Do not pull low. NC_CLE
Flash Descriptor Sec urity will be overridden. Also , when
Low (0)-
this signals is sampled on th e rising edge of PWROK then it will also
disable Intel ME and its feat ures.
Security measure de fined in the Flash Descriptor
High (1)-:
will be enabled.
Platform design should provid e appropriate pull-up or pull- down
depending on the desired sett ings. If a jumper option is us ed to
tie this signal to GND as req uired by the functional strap,
the signal should be pulled l ow through a weak pull-down in order
to avoid asserting HDA_DOCK_E N# inadvertently.
Note:
CRB recommends 1-kΩ pull- down for FD Override.
There is an internal pull-up of 20 kΩ for HDA_DOCK_EN# which is only
enabled at boot/reset for str apping functions.
Weak internal pull-down. Do n ot pull high.
Sampled at rising edge of RSM RST#.
Weak internal pull-down. Do n ot pull high.
Sampled at rising edge of RSM RST#.
Intel ME Crypto Trans port Layer Security (TLS) ciph er suite
Low (0)-
with no confidentiality
Intel ME Crypto Tra nsport Layer Security (TLS) ci pher suite
High (1)-:
with confidentiality
Note:
This is an unmuxed signal.
This signal has a weak intern al pull-down of 20 KΩ which is enabled
when PWROK is low.
Sampled at rising edge of RSM RST#.
CRB has a 1-kΩ pull-up on this signal to +3.3VA rail.
Calpella Schematic Checklist Rev1.6
I
ntel suggest 1K resistor (Fon seca)
Ω ; do not stuff resistor.
Connect GNT1# to ground with 1-kΩ pull-down
resistor. Leave GNT0# Floatin g.
Ω weak pull-down resistor.
B
C
rocessor Strapping
P
in Name
P
C
FG[4]
FG[3]
C
CFG[0]
trap Description
S
Embedded
DisplayPort
Presence
PCI-Express Static
Lane Reversal
PCI-Express
Configuration
Select
D
alpella Schematic Checklist Rev1.6
C
onfiguration (Default value for each bit is
C
1 unless specified otherwise)
Disabled - No Physical Dis play Port attached to
1:
Embedded DisplayPort.
Enabled - An external Disp lay Port device is
0:
connected to the Embedded Dis play Port.
Normal Operation.
1:
Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
0:
Single PCI-Express Graphic s
1:
Bifurcation enabled
0:
efault
D
Value
1
1
1
E
PCIE Routing
LANE1
LANE2
LANE3 LAN
Card reader
MiniCard WLAN
MiniCard WWAN LANE4
New Card LANE5
USB Table
Pair
0
1
2
3
4
5
6
7
8
9
10
11
12
13
USB
Device
USB1
USB for ESATA
USB2
RESERVE
WLAN
WWAN
RESERVED
(Not available for HM55)
RESERVED
(Not available for HM55)
BlUETOOTH
Card Reader
Biometric
CAMERA
New Card
RESERVED
1st Samsung
1st Samsung
1 1
GPIO8
GPIO27
Weak internal pull-up. Do not pull low.
Sampled at rising edge of RSM RST#.
Default = Do not connect (flo ating). Internal pull-up.
High(1) = Enables the interna l VccVRM to have a clean suppl y for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM . Need to use on-board filter
circuits for analog rails.
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
Taipei Hsien 221, Taiwan, R.O.C.
Table of Content
Table of Content
Table of Content
6 88 Wednesday, January 13, 2010
6 88 Wednesday, January 13, 2010
6 88 Wednesday, January 13, 2010
A00
A00
A00
5
S
SID = Clock GEN
D D
4
3
2
1
+3.3V_RU N +3.3V_RU N_SL585
R708
R708
1 2
0R0603-P AD-2-GP
0R0603-P AD-2-GP
1 2
C701
SC4D7P5 0V2CN-1GP
SC4D7P5 0V2CN-1GP
SC-1130-1
change C701 to 4 .7pF for RF
C C
C701
DY
DY
1 2
1 2
C702
C702
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
C703
C703
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
A00-0104-1
RN701
DREFCLK # [23]
DREFCLK [23]
CLKIN_DMI# [23]
CLKIN_DMI [23]
CLK_PCIE_ SATA# [23]
CLK_PCIE_ SATA [23]
CLK_CPU _BCLK# [23]
CLK_CPU _BCLK [23]
B B
RN701
0R4P2R-P AD
0R4P2R-P AD
RN702
RN702
0R4P2R-P AD
0R4P2R-P AD
RN703
RN703
0R4P2R-P AD
0R4P2R-P AD
RN704
RN704
0R4P2R-P AD
0R4P2R-P AD
2 3
1
2 3
1
2 3
1
1
2 3
TP701 TPA D14-GP T P701 TPAD14-GP
TP702 TPA D14-GP T P702 TPAD14-GP
CLK_MCH _DREFCLK1#
CLK_MCH _DREFCLK1
4
CLK_IN_DM I#
RN
RN
CLK_IN_DM I
4
CLK_PCIE_ SATA1#
RN
RN
RN
RN
CLK_PCIE_ SATA1
4
CLK_CPU _BCLK1#
4
RN
RN
CLK_CPU _BCLK1
TP_CPU_ 1#
1
TP_CPU_ 1
1
1 2
C704
C704
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C705
C705
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
U701
U701
4
DOT_96#
3
DOT_96
14
SRC_2#
13
SRC_2
11
SRC_1/SATA#
10
SRC_1/SATA
22
CPU_0#
23
CPU_0
19
CPU_1#
20
CPU_1
SLG8SP5 85VTR-GP
SLG8SP5 85VTR-GP
1 2
C708
C707
C707
C708
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+3.3V_RU N_SL585 +1.05V_RUN _SL585_IO
24
VDD_CPU
GND
33
1st Silego 71.08585.003
2nd ICS 71.93197.003
+1.05V_V TT
R709
R709
1 2
0R0603-P AD-2-GP
0R0603-P AD-2-GP
1 2
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
17
29
15
5
A00-0104-1 A00-0104-1
C709
C709
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
18
1 2
C710
C710
SC10U10 V5ZY-1GP
SC10U10 V5ZY-1GP
1 2
VGA 27M
SS
VDD_27
VDD_REF
VDD_DOT
VDD_SRC
VSS_REF
21
26
VDD_SRC_IO
VDD_CPU_IO
27MHZ
27MHZ_SS
CPU_STOP#
CKPWRGD/PD#
REF_0/CPU_SEL
XTAL_IN
XTAL_OUT
SDA
SCL
VSS_DOT
VSS_278VSS_SATA
VSS_SRC
VSS_CPU
2
12
9
+1.05V_V TT
6
7
16
25
30
28
27
31
32
1 2
CLK_27M
CLK_27M _SS
CPU_STO P#
CK_PW RGD
FSC
CLK_XTA L_IN
CLK_XTA L_OUT
1 2
X-14D318 18M-37GP
X-14D318 18M-37GP
C714
C714
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
NON-SS Mount DY
R706 33R2 J-2-GP
R706 33R2 J-2-GP
DY
DY
R710 33R2 J-2-GP
R710 33R2 J-2-GP
DY
DY
R701 2K2R 2J-2-GP R701 2K2R 2J-2-GP
R703 33R2 J-2-GP R703 33R2 J-2-GP
PCH_SMB DATA [18,19,23,40,6 4,76]
PCH_SMB CLK [18,19,23,40 ,64,76]
X701
X701
CLK_XTA L_IN
CLK_XTA L_OUT
1 2
C715
C715
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
1st: HARMONY 82.30005.901
R704
R704
4K7R2J-2 -GP
4K7R2J-2 -GP
R707
R707
10KR2J-3 -GP
10KR2J-3 -GP
DY
DY
1 2
FSC
1 2
2nd: ITTI 82.30005.C51
3rd: TXC 82.30005.B81
FSC 0 1
SPEED
133MHz
(Default)
+1.05V_R UN_SL585_IO
C711
C711
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
DY Mount
1 2
12
1 2
1 2
100MHz
R710 R706
+3.3V_RU N
1 2
DY
DY
1 2
C712
C712
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
CLK_VGA _27M [81]
CLK_PCH _14M [23]
EC701
EC701
SC4D7P5 0V2CN-1GP
SC4D7P5 0V2CN-1GP
R705
R705
10KR2J-3 -GP
10KR2J-3 -GP
CK_PW RGD
CLK_VGA _27M
R749
R749
DY
DY
0R2J-2-GP
0R2J-2-GP
1 2
CLK_VGA_27M_RC
C718
C718
DY
DY
SC4D7P5 0V2CN-1GP
SC4D7P5 0V2CN-1GP
1 2
+3.3V_RU N_SL585
1 2
G
S D
Q701
Q701
2N7002A -7-GP
2N7002A -7-GP
1ST: 84.2N702.E31
2ND: 84.2N702.D31
VR_CLKE N# [47]
A A
5
4
3
2
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Clock Generator SLG8SP585
Clock Generator SLG8SP585
Clock Generator SLG8SP585
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
7 88 Wednesd ay, January 13, 2010
7 88 Wednesd ay, January 13, 2010
7 88 Wednesd ay, January 13, 2010
1
A00
A00
A00
5
S
SID = CPU
4
3
2
1
D D
1
1
OF 9
C
C
PU1A
PU1A
DMI_PTX_C RXN0 [22]
DMI_PTX_C RXN1 [22]
DMI_PTX_C RXN2 [22]
DMI_PTX_C RXN3 [22]
DMI_PTX_C RXP0 [22]
DMI_PTX_C RXP1 [22]
DMI_PTX_C RXP2 [22]
DMI_PTX_C RXP3 [22]
DMI_CTX_P RXN0 [22]
DMI_CTX_P RXN1 [22]
DMI_CTX_P RXN2 [22]
DMI_CTX_P RXN3 [22]
DMI_CTX_P RXP0 [22 ]
DMI_CTX_P RXP1 [22 ]
DMI_CTX_P RXP2 [22 ]
DMI_CTX_P RXP3 [22 ]
C C
B B
Calpella Platform Design Guide
Revision 1.6
2.4 Arrandale Graphics Disable Guideline
FDI_FSYNC0 [22]
FDI_FSYNC1 [22]
FDI_INT [22]
FDI_LSYNC0 [22]
FDI_LSYNC1 [22]
Page 89
FDI_TXN0 [22]
FDI_TXN1 [22]
FDI_TXN2 [22]
FDI_TXN3 [22]
FDI_TXN4 [22]
FDI_TXN5 [22]
FDI_TXN6 [22]
FDI_TXN7 [22]
FDI_TXP0 [22]
FDI_TXP1 [22]
FDI_TXP2 [22]
FDI_TXP3 [22]
FDI_TXP4 [22]
FDI_TXP5 [22]
FDI_TXP6 [22]
FDI_TXP7 [22]
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
It applies to Arrandale and Clarksfield discrete graphic designs.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The GFX_IMON,
FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on
the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors).
A24
C23
B22
A21
B24
D23
B23
A22
D24
G24
F23
H23
D25
F24
E23
G23
E22
D21
D19
D18
G21
E19
F21
G18
D22
C21
D20
C18
G22
E20
F20
G19
F17
E17
C17
F18
D17
DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
FDI_TX#0
FDI_TX#1
FDI_TX#2
FDI_TX#3
FDI_TX#4
FDI_TX#5
FDI_TX#6
FDI_TX#7
FDI_TX0
FDI_TX1
FDI_TX2
FDI_TX3
FDI_TX4
FDI_TX5
FDI_TX6
FDI_TX7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
CLARKSFIELD
CLARKSFIELD
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
OF 9
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
DMI
DMI
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
Intel(R) FDI
Intel(R) FDI
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
PEG_IRCOMP _R
EXP_RBIAS
PCIE_MRX_ GTX_N15
PCIE_MRX_ GTX_N14
PCIE_MRX_ GTX_N13
PCIE_MRX_ GTX_N12
PCIE_MRX_ GTX_N11
PCIE_MRX_ GTX_N10
PCIE_MRX_ GTX_N9
PCIE_MRX_ GTX_N8
PCIE_MRX_ GTX_N7
PCIE_MRX_ GTX_N6
PCIE_MRX_ GTX_N5
PCIE_MRX_ GTX_N4
PCIE_MRX_ GTX_N3
PCIE_MRX_ GTX_N2
PCIE_MRX_ GTX_N1
PCIE_MRX_ GTX_N0
PCIE_MRX_ GTX_P15
PCIE_MRX_ GTX_P14
PCIE_MRX_ GTX_P13
PCIE_MRX_ GTX_P12
PCIE_MRX_ GTX_P11
PCIE_MRX_ GTX_P10
PCIE_MRX_ GTX_P9
PCIE_MRX_ GTX_P8
PCIE_MRX_ GTX_P7
PCIE_MRX_ GTX_P6
PCIE_MRX_ GTX_P5
PCIE_MRX_ GTX_P4
PCIE_MRX_ GTX_P3
PCIE_MRX_ GTX_P2
PCIE_MRX_ GTX_P1
PCIE_MRX_ GTX_P0
PCIE_MTX_ GRX_C_N15
PCIE_MTX_ GRX_C_N14
PCIE_MTX_ GRX_C_N13
PCIE_MTX_ GRX_C_N12
PCIE_MTX_ GRX_C_N11
PCIE_MTX_ GRX_C_N10
PCIE_MTX_ GRX_C_N9
PCIE_MTX_ GRX_C_N8
PCIE_MTX_ GRX_C_N7
PCIE_MTX_ GRX_C_N6
PCIE_MTX_ GRX_C_N5
PCIE_MTX_ GRX_C_N4
PCIE_MTX_ GRX_C_N3
PCIE_MTX_ GRX_C_N2
PCIE_MTX_ GRX_C_N1
PCIE_MTX_ GRX_C_N0
PCIE_MTX_ GRX_C_P15
PCIE_MTX_ GRX_C_P14
PCIE_MTX_ GRX_C_P13
PCIE_MTX_ GRX_C_P12
PCIE_MTX_ GRX_C_P11
PCIE_MTX_ GRX_C_P10
PCIE_MTX_ GRX_C_P9
PCIE_MTX_ GRX_C_P8
PCIE_MTX_ GRX_C_P7
PCIE_MTX_ GRX_C_P6
PCIE_MTX_ GRX_C_P5
PCIE_MTX_ GRX_C_P4
PCIE_MTX_ GRX_C_P3
PCIE_MTX_ GRX_C_P2
PCIE_MTX_ GRX_C_P1
PCIE_MTX_ GRX_C_P0
R801 49D9 R2F-GPR801 49D9 R2F-GP
1 2
R802 750R 2F-GP R802 750R 2F-GP
1 2
PCIE_MRX_G TX_N[0..15]
PCIE_MRX_G TX_P[0..15]
C829 SCD1U10 V2KX-5GP C829 SCD1U10 V2KX-5GP
1 2
C827 SCD1U10 V2KX-5GP C827 SCD1U10 V2KX-5GP
1 2
C832 SCD1U10 V2KX-5GP C832 SCD1U10 V2KX-5GP
1 2
C812 SCD1U10 V2KX-5GP C812 SCD1U10 V2KX-5GP
1 2
C803 SCD1U10 V2KX-5GP C803 SCD1U10 V2KX-5GP
1 2
C811 SCD1U10 V2KX-5GP C811 SCD1U10 V2KX-5GP
1 2
C828 SCD1U10 V2KX-5GP C828 SCD1U10 V2KX-5GP
1 2
C810 SCD1U10 V2KX-5GP C810 SCD1U10 V2KX-5GP
1 2
C823 SCD1U10 V2KX-5GP C823 SCD1U10 V2KX-5GP
1 2
C804 SCD1U10 V2KX-5GP C804 SCD1U10 V2KX-5GP
1 2
C831 SCD1U10 V2KX-5GP C831 SCD1U10 V2KX-5GP
1 2
C825 SCD1U10 V2KX-5GP C825 SCD1U10 V2KX-5GP
1 2
C821 SCD1U10 V2KX-5GP C821 SCD1U10 V2KX-5GP
1 2
C813 SCD1U10 V2KX-5GP C813 SCD1U10 V2KX-5GP
1 2
C806 SCD1U10 V2KX-5GP C806 SCD1U10 V2KX-5GP
1 2
C816 SCD1U10 V2KX-5GP C816 SCD1U10 V2KX-5GP
1 2
C826 SCD1U10 V2KX-5GP C826 SCD1U10 V2KX-5GP
1 2
C822 SCD1U10 V2KX-5GP C822 SCD1U10 V2KX-5GP
1 2
C818 SCD1U10 V2KX-5GP C818 SCD1U10 V2KX-5GP
1 2
C815 SCD1U10 V2KX-5GP C815 SCD1U10 V2KX-5GP
1 2
C808 SCD1U10 V2KX-5GP C808 SCD1U10 V2KX-5GP
1 2
C802 SCD1U10 V2KX-5GP C802 SCD1U10 V2KX-5GP
1 2
C820 SCD1U10 V2KX-5GP C820 SCD1U10 V2KX-5GP
1 2
C805 SCD1U10 V2KX-5GP C805 SCD1U10 V2KX-5GP
1 2
C817 SCD1U10 V2KX-5GP C817 SCD1U10 V2KX-5GP
1 2
C801 SCD1U10 V2KX-5GP C801 SCD1U10 V2KX-5GP
1 2
C814 SCD1U10 V2KX-5GP C814 SCD1U10 V2KX-5GP
1 2
C824 SCD1U10 V2KX-5GP C824 SCD1U10 V2KX-5GP
1 2
C830 SCD1U10 V2KX-5GP C830 SCD1U10 V2KX-5GP
1 2
C809 SCD1U10 V2KX-5GP C809 SCD1U10 V2KX-5GP
1 2
C807 SCD1U10 V2KX-5GP C807 SCD1U10 V2KX-5GP
1 2
C819 SCD1U10 V2KX-5GP C819 SCD1U10 V2KX-5GP
1 2
PCIE_MRX_G TX_N[0..15] [80]
PCIE_MRX_G TX_P[0..15] [8 0]
PCIE_MTX_ GRX_N15
PCIE_MTX_ GRX_N14
PCIE_MTX_ GRX_N13
PCIE_MTX_ GRX_N12
PCIE_MTX_ GRX_N11
PCIE_MTX_ GRX_N10
PCIE_MTX_ GRX_N9
PCIE_MTX_ GRX_N8
PCIE_MTX_ GRX_N7
PCIE_MTX_ GRX_N6
PCIE_MTX_ GRX_N5
PCIE_MTX_ GRX_N4
PCIE_MTX_ GRX_N3
PCIE_MTX_ GRX_N2
PCIE_MTX_ GRX_N1
PCIE_MTX_ GRX_N0
PCIE_MTX_ GRX_P15
PCIE_MTX_ GRX_P14
PCIE_MTX_ GRX_P13
PCIE_MTX_ GRX_P12
PCIE_MTX_ GRX_P11
PCIE_MTX_ GRX_P10
PCIE_MTX_ GRX_P9
PCIE_MTX_ GRX_P8
PCIE_MTX_ GRX_P7
PCIE_MTX_ GRX_P6
PCIE_MTX_ GRX_P5
PCIE_MTX_ GRX_P4
PCIE_MTX_ GRX_P3
PCIE_MTX_ GRX_P2
PCIE_MTX_ GRX_P1
PCIE_MTX_ GRX_P0
PCIE_MTX_ GRX_N[0..15]
PCIE_MTX_ GRX_P[0..15]
PCIE_MTX_G RX_N[0..15] [80]
PCIE_MTX_G RX_P[0..15] [8 0]
CLARKUN F
CLARKUN F
1st Samsung
1st Samsung
A A
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (PCIE/DMI/FDI)
CPU (PCIE/DMI/FDI)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (PCIE/DMI/FDI)
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
8 88 Wednesd ay, January 13, 2010
8 88 Wednesd ay, January 13, 2010
8 88 Wednesd ay, January 13, 2010
A00
A00
A00
0
RN
RN
A
4
4
1
2 3
4
00-0104-1
N903
N903
R
R
0
0
R4P2R-PAD
R4P2R-PAD
4
RN905
RN905
SRN10KJ-5-GP
SRN10KJ-5-GP
RN906
RN906
0R4P2R-PAD
0R4P2R-PAD
A00-0104-1
A00-0104-1
S
A
R
R
SRN22J-7-GP
SRN22J-7-GP
SRN1KJ-7-GP
SRN1KJ-7-GP
R
R
XDP_DBRESET# [22]
7/01 Check
1.assign GPIO EC_GPIO91 ??
N901
N901
N904
N904
RN
RN
4
2
1.05V_VTT
+
1
2 3
Calpella Platform S3 Power Reduction Platform
S3 Power Reduction CRB Implementation
Design Details Revision 0.1
B
CLK_CPU_P [25]
B
CLK_CPU_N [25]
C
LK_EXP_P [23]
C
LK_EXP_N [23]
PM_EXTTS#0 [18]
PM_EXTTS#1 [19]
S
B-1020-1
DY R935, POP C915,R934, Q901
DR_RST_GATE# [25]
D
C
C
915
915
1 2
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
+
1.5V_SUS
1 2
R
R
934
934
1KR2J-1-GP
Q
Q
901
901
BSS138-7-F-GP
BSS138-7-F-GP
G
Vgs(th)<=1.5V
R935
R935
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
DDR3 Compensation Signals
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_TDO_R
1KR2J-1-GP
D S
R907 100R2F-L1-GP-U R9 07 100R2F-L1-GP-U
1 2
R910 24D9R2F-L-GP R910 24D9R2F-L-GP
1 2
R911 130R2F-1-GP R911 130R2F-1-GP
1 2
R928
R928
51R2J-2-GP
51R2J-2-GP
D
1ST: 84.00138.E31
2ND:
+1.05V_VTT
1 2
1
3.3V_ALW
+
DR_RST_GATE#
D
SB-1103
change Q901 to 84.00138.F31
DR3_DRAMRST# [18,19]
1 2
R
R
937 10KR2J-3-GP
937 10KR2J-3-GP
SM_DRAMRST#
1 2
R988
R988
100KR2J-1-GP
100KR2J-1-GP
SB-1023
pop R988 for S3
reduce function
5
rocessor Compensation Signals
1.05V_VTT
+
Processor Pullups
902 49D9R2F-GP
902 49D9R2F-GP
R
R
1 2
R
R
933 68R2-GP
933 68R2-GP
1 2
H
_CATERR#
_PROCHOT_R#
H
D D
SSID = CPU
H_PROCHOT# [47]
C C
H_PWRGOOD [25,42]
PM_DRAM_PWR GD [22]
H_VTTPWRGD [49]
P
1 2
R
R
901 20R2F-GP
901 20R2F-GP
1 2
903 20R2F-GP
903 20R2F-GP
R
R
1 2
R
R
905 49D9R2F-GP
905 49D9R2F-GP
1 2
906 49D9R2F-GP
906 49D9R2F-GP
R
R
T
P901 TPAD14-GPTP901 TPAD14-GP
R936
R936
0R2J-2-GP
0R2J-2-GP
1 2
DY
DY
SB-1026
1. remove 1K ohm for remove XDP
PLT_RST# [21,34,36,37,64,70,76,80]
1
H_PECI [25]
H_THRMTRIP# [25,37,42]
TP902
TP902
TPAD14-GP
TPAD14-GP
H_PM_SYNC [22]
TP903 TPAD14-GP TP903 TPAD14-GP
R913
R913
1 2
1K6R2F-GP
1K6R2F-GP
S
H
H_PROCHOT_R#
TP_RESET_OBS#
1
TP_TAPPWRGOOD
1
H
H
H
H
KTOCC#_R
_CATERR#
H_PWRGOOD
1 2
4
_COMP3
_COMP2
_COMP1
_COMP0
PLT_RST#_R
R915
R915
750R2F-GP
750R2F-GP
AT23
AT24
G16
AT26
AH24
AK14
AT15
AN26
AK15
AP26
AL15
AN14
AN27
AK13
AM15
AM26
AL14
PU1B
PU1B
C
C
C
OMP3
C
OMP2
C
OMP1
C
OMP0
S
KTOCC#
ATERR#
C
PECI
PROCHOT#
THERMTRIP#
RESET_OBS#
PM_SYNC
VCCPW RGOOD_1
VCCPW RGOOD_0
SM_DRAMPW ROK
VTTPWR GOOD
TAPPWR GOOD
RSTIN#
CLARKUNF
CLARKUNF
Check
MISC THERMAL
MISC THERMAL
B
B
CLK_ITP#
P
P
EG_CLK#
D
PLL_REF_SSCLK
D
PLL_REF_SSCLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP0
MISC
MISC
SM_RCOMP1
SM_RCOMP2
PM_EXT_TS#0
PM_EXT_TS#1
CLARKSFIELD
CLARKSFIELD
DDR3
DDR3
PWR MANAGEMENT
PWR MANAGEMENT
JTAG & BPM
JTAG & BPM
3
OF 9
OF 9
2
2
B
CLK
B
CLK#
CLK_ITP
EG_CLK
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
TDI_M
TDO_M
DBR#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
TDI
A16
B16
AR30
AT30
E16
D16
A18
A17
F6
AL1
AM1
AN1
AN15
AP15
Check
AT28
AP27
AN28
AP28
AT27
AT29
AR27
AR29
AP29
AN25
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
B
CLK_CPU_P_R
B
CLK_CPU_N_R
Check
P
EG_CLK_R
EG_CLK#_R
P
D
PLL_REF_SSCLK_R
D
PLL_REF_SSCLK#_R
SM_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
PM_EXTTS#0_C
PM_EXTTS#1_C
XDP_TRST#
XDP_TDO_R
TDI_M
TDO_M
0R0402-PAD-2-GP
0R0402-PAD-2-GP
H_DBR#_R
0R0402-PAD-2-GP
0R0402-PAD-2-GP
B-1022
S
RN901 change to 22 ohm
2 3
1
1
2 3
2 3
1
R923
R923
1 2
51R2J-2-GP
51R2J-2-GP
R908
R908
1 2
R909
R909
1 2
+3.3V_ALW
B B
VTT_PWRGD [37,49,52]
A A
Remove XDP function for layout concern
5
R989 10KR2J-3-GP R989 10KR2J-3-GP
1 2
U927
U927_B
U927
1
B
VCC
2
A
3
GND
74LVC1G08GW-1-GP
74LVC1G08GW-1-GP
1ST: 73.01G08.L04
2ND:
4
Y
5
VTT_PWRGD_R3
4
R977
R977
PM_DRAM_PWR GD PM_DRAM_PWR GD
1 2
1K6R2F-GP
1K6R2F-GP
SB-1020-1
POP R977 for S3 redution
DY R919, change R920 to 0.75K
R919
R919
1K27R2F-L-GP
1K27R2F-L-GP
R920
R920
750R2F-GP
750R2F-GP
+1.5V_CPU
1 2
DY
DY
1 2
3
Normal
R920 R919
AUB
1.27k
CFD
1.1k 3k
3k
S3 Power Reduction circuit
R920 R919
AUB
1.1k(DY)
CFD
1.1k(DY) 0.75k
0.75k
R977
1.6k(DY)
1.5k(DY)
R977
1.6k
1.5k
2
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (THERMAL/CLOCK/PM )
CPU (THERMAL/CLOCK/PM )
CPU (THERMAL/CLOCK/PM )
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
9 88 Wednesday, January 13, 2010
9 88 Wednesday, January 13, 2010
9 88 Wednesday, January 13, 2010
1
A00
A00
A00
5
S
SID = CPU
C
C
PU1C
PU1C
4
OF 9
OF 9
3
3
3
C
C
PU1D
PU1D
2
OF 9
OF 9
4
4
1
W8
S
M
M
AA6
S
A_CK0
AA7
S
M
M
_A_DQ[63 ..0] [18]
D D
C C
B B
_A_DQ[63 ..0]
M_A_BS0 [18]
M_A_BS1 [18]
M_A_BS2 [18]
M_A_CAS # [18]
M_A_RAS # [18]
M_A_W E# [18]
M
_A_DQ0
M
_A_DQ1
_A_DQ2
M
M
_A_DQ3
_A_DQ4
M
M
_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ1 0
M_A_DQ1 1
M_A_DQ1 2
M_A_DQ1 3
M_A_DQ1 4
M_A_DQ1 5
M_A_DQ1 6
M_A_DQ1 7
M_A_DQ1 8
M_A_DQ1 9
M_A_DQ2 0
M_A_DQ2 1
M_A_DQ2 2
M_A_DQ2 3
M_A_DQ2 4
M_A_DQ2 5
M_A_DQ2 6
M_A_DQ2 7
M_A_DQ2 8
M_A_DQ2 9
M_A_DQ3 0
M_A_DQ3 1
M_A_DQ3 2
M_A_DQ3 3
M_A_DQ3 4
M_A_DQ3 5
M_A_DQ3 6
M_A_DQ3 7
M_A_DQ3 8
M_A_DQ3 9
M_A_DQ4 0
M_A_DQ4 1
M_A_DQ4 2
M_A_DQ4 3
M_A_DQ4 4
M_A_DQ4 5
M_A_DQ4 6
M_A_DQ4 7
M_A_DQ4 8
M_A_DQ4 9
M_A_DQ5 0
M_A_DQ5 1
M_A_DQ5 2
M_A_DQ5 3
M_A_DQ5 4
M_A_DQ5 5
M_A_DQ5 6
M_A_DQ5 7
M_A_DQ5 8
M_A_DQ5 9
M_A_DQ6 0
M_A_DQ6 1
M_A_DQ6 2
M_A_DQ6 3
C10
D10
H10
G10
AH5
AF5
AK6
AK7
AF6
AG5
AJ10
AL10
AK12
AK8
AK11
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
AC3
AB2
AE1
AB3
AE9
A10
B10
E10
F10
J10
AJ7
AJ6
AJ9
AL7
AL8
S
A_DQ0
S
A_DQ1
C7
A_DQ2
S
A7
S
A_DQ3
A_DQ4
S
SA_DQ5
SA_DQ6
A8
SA_DQ7
D8
SA_DQ8
SA_DQ9
E6
SA_DQ10
F7
SA_DQ11
E9
SA_DQ12
B7
SA_DQ13
E7
SA_DQ14
C6
SA_DQ15
SA_DQ16
G8
SA_DQ17
K7
SA_DQ18
J8
SA_DQ19
G7
SA_DQ20
SA_DQ21
J7
SA_DQ22
SA_DQ23
L7
SA_DQ24
M6
SA_DQ25
M8
SA_DQ26
L9
SA_DQ27
L6
SA_DQ28
K8
SA_DQ29
N8
SA_DQ30
P9
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS0
SA_BS1
U7
SA_BS2
SA_CAS#
SA_RAS#
SA_WE#
CLARKSFIELD
CLARKSFIELD
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
A_CK#0
S
A_CKE0
S
A_CK1
A_CK#1
S
SA_CKE1
SA_CS#0
SA_CS#1
SA_ODT0
SA_ODT1
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
B9
D7
H7
M7
AG6
AM7
AN10
AN13
C9
F8
J9
N9
AH7
AK9
AP11
AT13
C8
F9
H9
M9
AH8
AK10
AN11
AR13
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS #0
M_A_DQS #1
M_A_DQS #2
M_A_DQS #3
M_A_DQS #4
M_A_DQS #5
M_A_DQS #6
M_A_DQS #7
M_A_DQS 0
M_A_DQS 1
M_A_DQS 2
M_A_DQS 3
M_A_DQS 4
M_A_DQS 5
M_A_DQS 6
M_A_DQS 7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M
_CLK_DD R0 [18]
M
_CLK_DD R#0 [18]
M
_CKE0 [18]
_CLK_DD R1 [18]
M
M
_CLK_DD R#1 [18]
M_CKE1 [18]
M_CS0# [18]
M_CS1# [18]
M_ODT0 [1 8]
M_ODT1 [1 8]
_B_DQ[63 ..0] [19]
M_A_DM[7 ..0] [18]
M_A_DQS #[7..0] [18 ]
M_A_DQS [7..0] [18]
M_A_A[15 ..0] [18]
_B_DQ[63 ..0]
M_B_BS0 [19]
M_B_BS1 [19]
M_B_BS2 [19]
M_B_CAS # [19]
M_B_RAS # [19]
M_B_W E# [19]
M
_B_DQ0
M
_B_DQ1
M
_B_DQ2
M
_B_DQ3
M
_B_DQ4
_B_DQ5
M
M
_B_DQ6
_B_DQ7
M
M
_B_DQ8
M_B_DQ9
M_B_DQ1 0
M_B_DQ1 1
M_B_DQ1 2
M_B_DQ1 3
M_B_DQ1 4
M_B_DQ1 5
M_B_DQ1 6
M_B_DQ1 7
M_B_DQ1 8
M_B_DQ1 9
M_B_DQ2 0
M_B_DQ2 1
M_B_DQ2 2
M_B_DQ2 3
M_B_DQ2 4
M_B_DQ2 5
M_B_DQ2 6
M_B_DQ2 7
M_B_DQ2 8
M_B_DQ2 9
M_B_DQ3 0
M_B_DQ3 1
M_B_DQ3 2
M_B_DQ3 3
M_B_DQ3 4
M_B_DQ3 5
M_B_DQ3 6
M_B_DQ3 7
M_B_DQ3 8
M_B_DQ3 9
M_B_DQ4 0
M_B_DQ4 1
M_B_DQ4 2
M_B_DQ4 3
M_B_DQ4 4
M_B_DQ4 5
M_B_DQ4 6
M_B_DQ4 7
M_B_DQ4 8
M_B_DQ4 9
M_B_DQ5 0
M_B_DQ5 1
M_B_DQ5 2
M_B_DQ5 3
M_B_DQ5 4
M_B_DQ5 5
M_B_DQ5 6
M_B_DQ5 7
M_B_DQ5 8
M_B_DQ5 9
M_B_DQ6 0
M_B_DQ6 1
M_B_DQ6 2
M_B_DQ6 3
AG1
AK1
AG4
AG3
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AN6
AN4
AN3
AN7
AP6
AP8
AP9
AR10
AT10
AF3
AJ3
AJ4
AT4
AT5
AT6
AT9
AT7
AB1
W5
AC5
AC6
G4
G2
G1
G5
M1
M4
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
H6
K2
L3
K5
K4
N5
R7
Y7
J6
J3
J2
J1
J5
S
B_DQ0
S
B_DQ1
S
B_DQ2
S
B_DQ3
S
B_DQ4
B_DQ5
S
S
B_DQ6
B_DQ7
S
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS0
SB_BS1
SB_BS2
SB_CAS#
SB_RAS#
SB_WE#
CLARKSFIELD
CLARKSFIELD
DDR SYSTEM MEMORY - B
DDR SYSTEM MEMORY - B
B_CK0
S
B_CK#0
S
B_CKE0
S
B_CK1
S
B_CK#1
B_CKE1
S
SB_CS#0
SB_CS#1
SB_ODT0
SB_ODT1
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
W9
M3
V7
V6
M2
AB8
AD6
AC7
AD1
D4
E1
H3
K1
AH1
AL2
AR4
AT8
D5
F4
J4
L4
AH2
AL4
AR5
AR8
C5
E3
H4
M5
AG2
AL5
AP5
AR7
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS #0
M_B_DQS #1
M_B_DQS #2
M_B_DQS #3
M_B_DQS #4
M_B_DQS #5
M_B_DQS #6
M_B_DQS #7
M_B_DQS 0
M_B_DQS 1
M_B_DQS 2
M_B_DQS 3
M_B_DQS 4
M_B_DQS 5
M_B_DQS 6
M_B_DQS 7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M
_CLK_DD R2 [19]
M
_CLK_DD R#2 [19]
M
_CKE2 [19]
M
_CLK_DD R3 [19]
_CLK_DD R#3 [19]
M
M
_CKE3 [19]
M_CS2# [19]
M_CS3# [19]
M_ODT2 [1 9]
M_ODT3 [1 9]
M_B_DM[7 ..0] [19]
M_B_DQS #[7..0] [19 ]
M_B_DQS [7..0] [19]
M_B_A[15 ..0] [19]
CLARKUN F
CLARKUN F
CLARKUN F
A A
5
4
3
CLARKUN F
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU (DDR)
CPU (DDR)
CPU (DDR)
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
1
A00
A00
10 88 Wednesd ay, January 13, 2010
10 88 Wednesd ay, January 13, 2010
10 88 Wednesd ay, January 13, 2010
A00
5
S
SID = CPU
D D
CFG0
CFG3
C C
CFG4
B B
DIS
1 2
R1101
R1101
3KR2F-GP
3KR2F-GP
DY
DY
改 改 改 改
5%
1 2
R1102
R1102
3KR2F-GP
3KR2F-GP
DW
07/10 Reversal
1.PCI-Express Static Lane Reversal
1 2
R1103
R1103
3KR2F-GP
3KR2F-GP
DY
DY
PCI-Express Configuration Select
1:Single PEG
CFG0
0:Bifurcation enabled
CFG3 - PCI-Express Static Lane Reversal
1 :Normal Operation
CFG3
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
CFG4 - Display Port Presence
1:Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
Calpella Platform Design Guide
Revision 1.6
4.8.3.1 LVDS Switching
Switchable GFX, just like integrated GFX only, to enable LVDS it is required that the
OEM set the LDVS (L_DDC_DATA) strap to present (pulled up) and the eDP strap
(CFG[4]) to disabled (not pulled down).
4.8.3.2 eDP Switching
eDP for Switchable GFX can only be driven out of Port D of PCH. To configure Port D for
embedded DP it is required to set the DDPD_CTRLDATA strap high to 3.3V Core rail
through 2.2 kΩ ±5% resistor, LVDS (L_DDC_DATA) strap as no connect and the eDP
strap CFG[4] as no connect.
CFG7(Reserved) - Temporarily used for early
Clarksfield sampl es.
CFG7 Clarksfield (only for early samples pre-ES1) -
Connect to GND with 3.01K Ohm/5% resistor.
Note: Only temporary for early CFD sample
(rPGA/BGA) [For details please refer to the
WW33 MoW and sightin g report].
For a common M/B design (for AUB and CFD),
A A
DW30 Only support Arrandale,
CFG7 no need pull down
5
the pull-down resistor shouble be used. Does
not impact AUB functionality.
4
Page 482,486
DW
07/02 Added
1.Added display Switchable strap commentariat
4
3
AP25
AL25
AL24
AL22
AJ33
AG9
M27
CFG0
CFG3
CFG4
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
L28
J17
H17
G25
G17
E31
E30
H16
B19
A19
A20
B20
U9
T9
AC9
AB9
J29
J28
TP1116 TP1116
TP1117 TP1117
TP1119 TPAD14 -GP TP1119 TPAD14-GP
TP1120 TPAD14 -GP TP1120 TPAD14-GP
3
SA_DIMM_VREF#
1
SB_DIMM_VREF#
1
1
1
TP_H_RSVD17_R
TP_H_RSVD18_R
C
C
PU1E
PU1E
R
SVD#AP25
R
SVD#AL25
R
SVD#AL24
RSVD#AL22
RSVD#AJ33
RSVD#AG9
RSVD#M27
RSVD#L28
SA_DIMM_VREF
SB_DIMM_VREF
RSVD#G25
RSVD#G17
RSVD#E31
RSVD#E30
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD_TP_86
RSVD#B19
RSVD#A19
RSVD#A20
RSVD#B20
RSVD#U9
RSVD#T9
RSVD#AC9
RSVD#AB9
RSVD#J29
RSVD#J28
CLARKUNF
CLARKUNF
2
2
OF 9
OF 9
5
5
R
SVD#AJ13
R
SVD#AJ12
R
SVD#AH25
R
SVD#AK26
RSVD#AL26
RSVD_NCTF_37
RSVD#AJ26
RSVD#AJ27
CLARKSFIELD
CLARKSFIELD
RSVD#AL28
RSVD#AL29
RSVD#AP30
RSVD#AP32
RSVD#AL27
RSVD#AT31
RSVD#AT32
RSVD#AP33
RSVD#AR33
RSVD#AR32
RSVD_TP#E15
RSVD_TP#F15
RESERVED
RESERVED
RSVD#D15
RSVD#C15
RSVD#AJ15
RSVD#AH15
SA_CK2
SA_CK#2
SA_CKE2
SA_CS#2
SA_ODT2
SA_CK3
SA_CK#3
SA_CKE3
SA_CS#3
SA_ODT3
SB_CK2
SB_CK#2
SB_CKE2
SB_CS#2
SB_ODT2
SB_CK3
SB_CK#3
SB_CKE3
SB_CS#3
SB_ODT3
KEY
VSS
1
AJ13
AJ12
AH25
AK26
AL26
AR2
AJ26
AJ27
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AR32
E15
F15
A2
D15
C15
TP_RSVD64_R
AJ15
TP_RSVD65_R
AH15
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34
1st Samsung
1st Samsung
1st Samsung
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
TP1121 TPAD14-GP TP1121 TPAD14-G P
1
TP1122 TPAD14-GP TP1122 TPAD14-G P
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (RESERVED)
CPU (RESERVED)
CPU (RESERVED)
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
11 88 Wednesday, January 13, 2010
11 88 Wednesday, January 13, 2010
11 88 Wednesday, January 13, 2010
1
A00
A00
A00
5
S
SID = CPU
P
ROCESSOR CORE POWER
VCC_CORE
+
D D
C C
B B
C
C
C
C
C
DY
DY
DY
DY
C
1207
1207
1208
1208
1 2
1 2
S
S
S
S
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
C1214
C1214
C1213
C1213
1 2
1 2
1 2
1 2
C1226
C1226
C1236
C1236
S
S
S
S
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
C1227
C1227
1 2
S
S
S
S
C22U6D3V5MX-2GP
C22U6D3V5MX-2GP
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
C1237
C1237
1 2
S
S
S
S
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
C10U6D3V5MX-3GP
C10U6D3V5MX-3GP
DY
DY
1206
1206
1 2
S
S
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
D
D
Y
Y
C1212
C1212
1 2
S
S
C10U6D3V5KX-1GP
C10U6D3V5KX-1GP
DY
DY
C1225
C1225
1 2
S
S
C22U6D3V5MX-2GP
C22U6D3V5MX-2GP
C1235
C1235
1 2
S
S
C10U6D3V5MX-3GP
C10U6D3V5MX-3GP
DY
DY
1 2
C1243
C1243
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SC-1207-1
pop C1243 and change size to 0603 for EMI
C
C
C
C
1220
1220
1209
1209
1 2
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1215
C1215
C1223
C1223
1 2
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1228
C1228
C1229
C1229
1 2
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1239
C1239
C1238
C1238
1 2
1 2
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
4
8A (Arburdale)
C
C
1210
1210
1 2
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
D
D
Y
Y
C1224
C1224
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
C1231
C1231
C1230
C1230
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
C1240
C1240
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
C1232
C1232
1 2
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
C1242
C1242
C1241
C1241
1 2
1 2
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
4
PU1F
PU1F
C
C
+
VCC_CORE
AG35
CC
V
AG34
V
CC
AG33
CC
V
AG32
V
CC
AG31
V
CC
AG30
V
CC
AG29
CC
V
AG28
V
CC
AG27
V
CC
AG26
V
CC
AF35
VCC
AF34
VCC
AF33
VCC
AF32
VCC
AF31
VCC
AF30
VCC
AF29
VCC
AF28
VCC
AF27
VCC
AF26
VCC
AD35
VCC
AD34
VCC
AD33
VCC
AD32
VCC
AD31
VCC
AD30
VCC
AD29
VCC
AD28
VCC
AD27
VCC
AD26
VCC
AC35
VCC
AC34
VCC
AC33
VCC
AC32
VCC
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y35
VCC
Y34
VCC
Y33
VCC
Y32
VCC
Y31
VCC
Y30
VCC
Y29
VCC
Y28
VCC
Y27
VCC
Y26
VCC
V35
VCC
V34
VCC
V33
VCC
V32
VCC
V31
VCC
V30
VCC
V29
VCC
V28
VCC
V27
VCC
V26
VCC
U35
VCC
U34
VCC
U33
VCC
U32
VCC
U31
VCC
U30
VCC
U29
VCC
U28
VCC
U27
VCC
U26
VCC
R35
VCC
R34
VCC
R33
VCC
R32
VCC
R31
VCC
R30
VCC
R29
VCC
R28
VCC
R27
VCC
R26
VCC
P35
VCC
P34
VCC
P33
VCC
P32
VCC
P31
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC
CLARKSFIELD
CLARKSFIELD
CPU CORE SUPPLY
CPU CORE SUPPLY
POWER
POWER
SENSE LINES
SENSE LINES
3
6
6
1.1V RAIL POWER
1.1V RAIL POWER
PROC_DPRSLPVR
CPU VIDS
CPU VIDS
VTT_SELECT
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
OF 9
OF 9
TT0
V
V
TT0
TT0
V
V
TT0
V
TT0
V
TT0
TT0
V
V
TT0
V
TT0
V
TT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
PSI#
VID
VID
VID
VID
VID
VID
VID
1
8A
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
AN33
CPU_VID0
AK35
CPU_VID1
AK33
CPU_VID2
AK34
CPU_VID3
AL35
CPU_VID4
AL33
CPU_VID5
AM33
CPU_VID6
AM35
AM34
TP_H_VTTVID1
G15
AN35
VCC_SENSE
AJ34
VSS_SENSE
AJ35
B15
TP_VSS_SENSE_VTT
A15
C
C
1201
1201
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
1 2
C
C
1202
1202
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
DY
DY
PSI# [47]
CPU_VID[6..0] [47]
PM_DPRSLPVR [47]
TP1203
TP1203
IMVP_IMON [47]
VTT_SENSE [49]
1
TP1202
TP1202
TPAD14-GP
TPAD14-GP
C
C
1203
1203
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1233
C1233
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
TPAD14-GP
TPAD14-GP
2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1211
C1211
1 2
1 2
C
C
C
C
1217
1217
1218
1218
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1221
C1221
1 2
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
+1.05V_VTT
1 2
C
C
1216
1216
1 2
DY
DY
C1234
C1234
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1222
C1222
1 2
1 2
1 2
C
C
C
C
1219
1219
1204
1204
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
+1.05V_VTT
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1 2
C
C
1205
1205
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
D
D
Y
Y
The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
Design Guide.
+
1.05V_VTT
1
Please note that the VTT Rail
Values are
Arrandale VTT=1.05V;
Clarksfield VTT=1.1V
H_VTTVID1 = Low, 1.1V
H_VTTVID1 = High, 1.05V
SA
07/01 Check
1.DPRSLPVR ??
+VCC_CORE
1 2
R1201
R1201
100R2F-L1-GP-U
100R2F-L1-GP-U
VCC_SENSE [47]
1 2
R1204
R1204
100R2F-L1-GP-U
100R2F-L1-GP-U
VSS_SENSE [47]
A A
CLARKUNF
CLARKUNF
5
4
3
2
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (VCC_CORE)
CPU (VCC_CORE)
CPU (VCC_CORE)
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
12 88 Wednesday, January 13, 2010
12 88 Wednesday, January 13, 2010
12 88 Wednesday, January 13, 2010
1
A00
A00
A00
5
4
3
2
1
1.5V_CPU
+
S
SID = CPU
+
CPU_GFX CORE
7
7
OF 9
C
C
PU1G
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16
G28
G27
G26
E26
E25
J24
J23
H25
K26
J27
J26
J25
H27
F26
PU1G
V
AXG
V
AXG
AXG
V
V
AXG
AXG
V
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
GRAPHICS
GRAPHICS
CLARKSFIELD
CLARKSFIELD
FDI PEG & DMI
FDI PEG & DMI
POWER
POWER
SENSE
SENSE
GRAPHICS VIDs
GRAPHICS VIDs
LINES
LINES
22A
D D
C C
B B
T
T
C1303
C1303
C
C
C
C
1324
1324
1327
1327
1 2
1 2
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
DY
DY
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
+1.05V_V TT
+1.05V_V TT
1 2
C
C
C
C
1329
1329
1326
1326
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
SC10U6D 3V5MX-3GP
SC10U6D 3V5MX-3GP
1 2
18A
1 2
C1312
C1312
C
C
C
C
1328
1328
1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C1308
C1308
1 2
C1313
C1313
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1325
1325
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DY
DY
DY
DY
1 2
DY
DY
1 2
1 2
C
C
1323
1323
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
C1309
C1309
SC10U6D 3V5KX-1GP
SC10U6D 3V5KX-1GP
1 2
C1314
C1314
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
C1315
C1315
C
C
1330
1330
1 2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
OF 9
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_IMON
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VTT0
VTT0
VTT0
VTT0
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VCCPLL
VCCPLL
VCCPLL
AR22
AT22
AM22
AP22
AN22
AP23
AM23
AP24
AN24
AR25
TP_GFX_ DPRSLPVR
AT25
AM24
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
P10
N10
L10
K10
J22
J20
J18
H21
H20
H19
L26
L27
M26
SC10U6D 3V5MX-3GP
SC10U6D 3V5MX-3GP
SC10U6D 3V5KX-1GP
SC10U6D 3V5KX-1GP
V
AXG_SENSE
SSAXG_SENSE
V
GFX_VR_EN
GFX_DPRSLPVR
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
1.1V 1.8V
1.1V 1.8V
1 2
D
D
Y
Y
1376
1376
C
C
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
+
1.5V_SUS
F
ollow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.pdf"
document.
CC_AXG_ SENSE [5 3]
V
V
SS_AXG_ SENSE [53]
GFX_VID0 [53 ]
GFX_VID1 [53 ]
GFX_VID2 [53 ]
GFX_VID3 [53 ]
GFX_VID4 [53 ]
GFX_VID5 [53 ]
GFX_VID6 [53 ]
GFX_VR_ EN [53]
TP1303TPAD14-GP TP 1303TPAD14-GP
1
1 2
1 2
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C1310
C1310
C1316
C1316
C1302
C1302
DY
DY
1 2
C1318
C1318
1 2
C1303
C1303
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
1 2
DY
DY
1 2
C1319
C1319
SC1U25V5KX-1GP
SC1U25V5KX-1GP
C1301
C1301
1.5V_CPU
+
1 2
D
D
Y
Y
1377
1377
C
C
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
+
1.5V_SUS
GFX_IMON [53]
For no use switch graphic function
3A
1 2
C1304
C1304
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
C1311
C1311
SC10U6D 3V5KX-1GP
SC10U6D 3V5KX-1GP
1 2
C1317
C1317
SC10U6D 3V5MX-3GP
SC10U6D 3V5MX-3GP
1 2
1 2
C1306
C1306
C1305
C1305
SC10U6D3V5KX-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+1.05V_V TT
+1.05V_V TT
SC10U6D3V5KX-1GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1.35A
1 2
1 2
C1320
C1320
SC1U25V5KX-1GP
SC1U25V5KX-1GP
1 2
C1321
C1321
C1322
C1322
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
SC10U6D 3V5MX-3GP
SC10U6D 3V5MX-3GP
1 2
+1.5V_CP U
C1307
C1307
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1.5V_CPU
+
D
D
+
1.5V_SUS
1 2
DY
DY
+1.8V_RU N
1 2
Y
Y
1378
1378
C
C
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
TC1301
TC1301
SE330U2 D5VDM-2GP
SE330U2 D5VDM-2GP
1.5V_CPU
+
D
D
+
1.5V_SUS
1 2
Y
Y
1379
1379
C
C
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
CLARKUN F
CLARKUN F
A A
5
4
3
2
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (VCC_GFXCORE)
CPU (VCC_GFXCORE)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (VCC_GFXCORE)
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
13 88 Wednesd ay, January 13, 2010
13 88 Wednesd ay, January 13, 2010
13 88 Wednesd ay, January 13, 2010
1
A00
A00
A00
5
PU1H
PU1H
C
S
SID = CPU
D D
C C
B B
AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
C
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SS
V
V
SS
SS
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ8
VSS
AJ5
VSS
AJ2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
4
CLARKSFIELD
CLARKSFIELD
VSS
VSS
8
8
OF 9
OF 9
V
V
V
V
V
V
V
V
V
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
PU1I
PU1I
C
C
AE34
SS
AE33
SS
AE32
SS
AE31
SS
AE30
SS
AE29
SS
AE28
SS
AE27
SS
AE26
SS
AE6
SS
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
K27
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
G34
G31
G20
E35
E32
E29
E24
E21
E18
E13
E11
D33
D30
D26
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
A29
A27
A23
V
SS
K9
V
SS
K6
V
SS
K3
V
SS
J32
V
SS
J30
SS
V
J21
V
SS
J19
SS
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H8
VSS
H5
VSS
H2
VSS
VSS
VSS
VSS
G9
VSS
G6
VSS
G3
VSS
F30
VSS
F27
VSS
F25
VSS
F22
VSS
F19
VSS
F16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E8
VSS
E5
VSS
E2
VSS
VSS
VSS
VSS
D9
VSS
D6
VSS
D3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B8
VSS
B6
VSS
B4
VSS
VSS
VSS
VSS
A9
VSS
2
9
9
OF 9
OF 9
CLARKSFIELD
CLARKSFIELD
VSS
VSS
VSS_NCTF
VSS_NCTF
VSS_NCTF
NCTF
NCTF
VSS_NCTF#A35
VSS_NCTF#AT1
VSS_NCTF#AT35
VSS_NCTF#B1
RSVD_NCTF#A3
RSVD_NCTF#A33
RSVD_NCTF#A34
RSVD_NCTF#AP1
RSVD_NCTF#AP35
RSVD_NCTF#AR1
RSVD_NCTF#AR35
RSVD_NCTF#AT2
RSVD_NCTF#AT3
RSVD_NCTF#AT33
RSVD_NCTF#AT34
RSVD_NCTF#C1
RSVD_NCTF#C35
A35,AT1,AT35,B1,A3,A33,A34,
A35,AT1,AT35,B1,A3,A33,A34,
NCYF TEST PIN:
NCYF TEST PIN:
RSVD_NCTF#B35
AP1,AP35,AR1,AR35,AT2,AT3,
AT33,AT34,C1,C35,B35
AP1,AP35,AR1,AR35,AT2,AT3,
AT33,AT34,C1,C35,B35
AR34
B34
B2
TP_MCP_ VSS_NCTF2
A35
TP_MCP_ VSS_NCTF3
AT1
TP_MCP_ VSS_NCTF4
AT35
TP_MCP_ VSS_NCTF1
B1
A3
A33
A34
AP1
AP35
AR1
AR35
AT2
AT3
AT33
AT34
C1
C35
B35
For layout request
1
TP1402 TP 1402
1
TP1406 TP 1406
1
TP1405 TP 1405
1
TP1401 TP 1401
1
CLARKUN F
CLARKUN F
CLARKUN F
A A
5
4
3
CLARKUN F
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU (VSS)
CPU (VSS)
CPU (VSS)
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
1
A00
A00
14 88 Wednesd ay, January 13, 2010
14 88 Wednesd ay, January 13, 2010
14 88 Wednesd ay, January 13, 2010
A00
5
D D
S
SID = MEMORY
M_A_DQS#[7..0] [10]
M_A_DQ[63..0] [10]
M_A_DM[7..0] [10]
M_A_DQS[7..0] [10]
M_A_A[15..0] [10]
Layout Note:
1 2
1803
1803
C
C
C1804
C1804
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
+0.75V_DDR_VTT
1 2
1801
1801
DY
DY
C
C
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1873
1873
C1874
C1874
C
C
SCD1U10 V2KX-4GP
SCD1U10V2KX-4GP
Place near DM1
1 2
1 2
C1811
C1811
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
C1813
C1813
C1814
C1814
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C1875
C1875
SCD1U10 V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2 KX-4GP
SCD1U10V2KX-4GP
+V_DDR_REF
C1810
C1810
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
C1812
C1812
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
DY
DY
C1815
C1815
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C1816
C1816
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Layout Note:
Put between two SO-DIMM
DY
DY
C1823
C1823
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
C1817
C1817
C C
B B
A A
+1.5V_SUS
1 2
1802
1802
C
C
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Layout Note:
Put close to VTT1,VTT2.
DG:
1uF*4 (per SO-DIMM)
10uF*3 (two close to VR and one between the two SO-DIMM)
+1.5V_SUS
1 2
1872
1872
C
C
SCD1U10 V2KX-4GP
SCD1U10V2KX-4GP
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.
pdf" document.
5
1 2
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
4
_A_A0
M
M
_A_A1
M
_A_A2
M
_A_A3
M
_A_A4
_A_A5
M
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_BS2 [10]
M_A_BS0 [10]
M_A_BS1 [10]
1 2
DY
DY
TC1803
TC1803
ST330U2D5VBM-1-GP
ST330U2D5VBM-1-GP
M_ODT0 [10]
M_ODT1 [10]
1 2
C1809
C1809
DY
DY
+0.75V_DDR_VTT
4
M_A_BS2
M_A_BS0
M_A_BS1
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_ODT0
M_ODT1
DDR3_DRAMRST# [9,19]
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
109
108
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
10
27
45
62
135
152
169
186
12
29
47
64
137
154
171
188
116
120
126
1
30
203
204
3
D
D
M1
M1
0
A
A
1
2
A
A
3
4
A
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
Height 5.2mm
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
DDR3-204P-25-GP
DDR3-204P-25-GP
3
R
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1
NC#2
NC#/TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
2
NP1
P1
N
NP2
N
P2
110
AS#
113
E#
W
115
114
121
73
74
M_CLK_DDR0
101
CK0
CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_CLK_DDR#0
103
M_CLK_DDR1
102
M_CLK_DDR#1
104
M_A_DM0
11
M_A_DM1
28
M_A_DM2
46
M_A_DM3
63
M_A_DM4
136
M_A_DM5
153
M_A_DM6
170
M_A_DM7
187
PCH_SMBDATA
200
PCH_SMBCLK
202
198
199
SA0_DM1
197
SA0
SA1_DM1
201
SA1
77
122
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
+1.5V_SUS
M
_A_RAS# [10]
_A_WE# [10]
M
M
_A_CAS# [10]
M_CS0# [10]
M_CS1# [10]
M_CKE0 [10]
M_CKE1 [10]
M_CLK_DDR0 [10]
M_CLK_DDR#0 [10]
M_CLK_DDR1 [10]
M_CLK_DDR#1 [10]
PCH_SMBDATA [7,19,23,40,64,76]
PCH_SMBCLK [7,19,23,40,64,76]
PM_EXTTS#0 [9]
C1806
C1806
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
1 2
2
SA0_DM1
SA1_DM1
SMBUS address:A0
+3.3V_RUN
1 2
1 2
C1807
C1807
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
DY
DY
put near connector
1 2
1 2
C1821
C1821
C1819
C1819
DUMMY-C2
DUMMY-C2
DUMMY-C2
DUMMY-C2
1 2
1 2
R1801
R1802
R1802
10KR2J-3-GP
10KR2J-3-GP
1 2
C1820
C1820
DUMMY-C2
DUMMY-C2
1st Samsung
1st Samsung
1st Samsung
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
R1801
10KR2J-3-GP
10KR2J-3-GP
DW
07/02 Reserve
1.Added SA0_DM1 pull-up resis tor
07/07
2.Reserve pull- hi,lo resistor
C1818
C1818
DUMMY-C2
DUMMY-C2
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsic hih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsic hih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsic hih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
of
18 88 Wednesday, January 13, 2010
18 88 Wednesday, January 13, 2010
18 88 Wednesday, January 13, 2010
1
A00
A00
A00
5
S
SID = MEMORY
M
D D
C C
B B
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.
pdf" document.
A A
_B_DQS#[7..0] [10]
M
_B_DQ[63..0] [10]
M
_B_DM[7..0] [10]
M_B_DQS[7..0] [10]
M_B_A[15..0] [ 10]
Layout Note:
+1.5V_SUS
1 2
1905
1905
C
C
C1911
C1911
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
+0.75V_DDR_VTT
1 2
1908
1908
C
C
C1917
C1917
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DG:
1uF*4 (per SO-DIMM)
10uF*3 (two close to VR and one between the two SO-DIMM)
+1.5V_SUS
1 2
1976
1976
C
C
C1977
C1977
SCD1U10 V2KX-4GP
SCD1U10V2KX-4GP
5
Place near DM2
1 2
1 2
C1913
C1913
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Layout Note:
Put close to VTT1,VTT2.
1 2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C1978
C1978
SCD1U10 V2KX-4GP
SCD1U10V2KX-4GP
+V_DDR_REF
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C1916
C1916
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
DY
DY
C1918
C1918
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C1979
C1979
SCD1U10 V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10 V2KX-4GP
SCD1U10V2KX-4GP
1 2
C1907
C1907
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
C1920
C1920
C1919
C1919
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
DY
DY
C1909
C1909
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C1910
C1910
1 2
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
4
M
_B_A0
M
_B_A1
M
_B_A2
M
_B_A3
M
_B_A4
M
_B_A5
_B_A6
M
M
_B_A7
M
_B_A8
M
_B_A9
M
_B_A10
M
_B_A11
M
_B_A12
_B_A13
M
_B_A14
M
M_B_A15
M_B_BS2 [10]
M_B_BS0 [10]
M_B_BS1 [10]
1 2
DY
DY
TC1903
TC1903
ST330U2D5VBM-1-GP
ST330U2D5VBM-1-GP
M_ODT2 [10]
M_ODT3 [10]
1 2
C1914
C1914
DY
DY
4
DDR3_DRAMRST# [9,18]
M_B_BS2
M_B_BS0
M_B_BS1
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_ODT2
M_ODT3
+0.75V_DDR_VTT
3
3
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
109
108
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
10
27
45
62
135
152
169
186
12
29
47
64
137
154
171
188
116
120
126
1
30
203
204
M2
M2
D
D
A
0
A
1
A
2
A
3
4
A
5
A
A
6
7
A
A
8
A
9
A
10/AP
11
A
A
12
A
13
A
14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
DDR3-204P-24-GP
DDR3-204P-24-GP
NP1
N
P1
NP2
N
P2
110
R
AS#
113
E#
W
115
AS#
C
114
S0#
C
121
C
S1#
73
C
KE0
74
KE1
C
C
C
K0#
CK1
CK1#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
EVENT#
VDDSPD
SA0
SA1
NC#1
NC#2
NC#/TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
Height 9.2mm
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M
101
K0
M
103
M_CLK_DDR3
102
M_CLK_DDR#3
104
M_B_DM0
11
M_B_DM1
28
M_B_DM2
46
M_B_DM3
63
M_B_DM4
136
M_B_DM5
153
M_B_DM6
170
M_B_DM7
187
PCH_SMBDATA
200
PCH_SMBCLK
202
198
199
SA0_DM2
197
SA1_DM2
201
77
122
+1.5V_SUS
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
hange CONN
C
2009/06/01
_CLK_DDR2
_CLK_DDR#2
2
M
_B_RAS# [10]
M
_B_WE# [10]
M
_B_CAS# [10]
_CS2# [10]
M
_CS3# [10]
M
M
_CKE2 [10]
_CKE3 [10]
M
M
_CLK_DDR2 [1 0]
M
_CLK_DDR#2 [ 10]
M_CLK_DDR3 [10]
M_CLK_DDR#3 [10]
PCH_SMBDATA [7,18,23,40 ,64,76]
PCH_SMBCLK [7,18,23 ,40,64,76]
PM_EXTTS#1 [9]
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
2
put near connector
C1901
C1901
DUMMY-C2
DUMMY-C2
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
C1906
C1906
1 2
1
+
3.3V_RUN+3.3V_RUN
1 2
1 2
R
R
1903
1903
10KR2J-3-GP
10KR2J-3-GP
A1_DM2
S
SA0_DM2
R1901
R1901
10KR2J-3-GP
10KR2J-3-GP
R
R
1904
1904
10KR2J-3-GP
10KR2J-3-GP
Y
Y
D
D
1 2
1 2
R1902
R1902
10KR2J-3-GP
10KR2J-3-GP
DY
DY
SMBUS address:A4
+3.3V_RUN
1 2
1 2
C1921
C1921
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
DY
DY
Note:
If SA0_DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
If SA0_DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
If SA0_DIM0 = 0, SA1_DIM0 = 1
SO-DIMMA SPD Address is 0xA4
1 2
1 2
C1904
C1904
DUMMY-C2
DUMMY-C2
1st Samsung
1st Samsung
1st Samsung
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
C1902
C1902
Custom
Custom
Custom
C1903
C1903
DUMMY-C2
DUMMY-C2
DUMMY-C2
DUMMY-C2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
1 2
D
D
Y
Y
19 88 Wednesday, January 13, 2010
19 88 Wednesday, January 13, 2010
19 88 Wednesday, January 13, 2010
C1901
C1901
E
E
SCD1U25V3KX-GP
SCD1U25V3KX-GP
A00
A00
A00
5
W
D
0
7/05
S
SID = PCH
D D
C C
1. LCD brightness control are separated by GPU,PCH,EC
2. LCD Power Enable control a re separated by GPU,PCH,EC
3. LCD Backlight On/Off Statu s are separated by GPU,PCH,E C
07/07
4. Dummy R2003
1 2
R2002
R2002
2K37R2F -GP
2K37R2F -GP
50 ohm trace to filter
MCH_BLU E [74]
MCH_GRE EN [74]
MCH_RED [74 ]
R2007
R2007
150R2F-1 -GP
150R2F-1 -GP
B B
MCH_BLU E
MCH_GRE EN
MCH_RED
R2006
R2006
150R2F-1 -GP
150R2F-1 -GP
4
Place near PCH
1 2
1 2
Place near PCH
P
ANEL_BK EN_PCH [37]
L
CDVDD_E N_PCH [54]
L
BKLT_CT L_PCH [5 4]
L
_DDC_CL K [54]
L_DDC_D ATA [54]
+3.3V_RU N
MCH_LVD SA_CLK# [74]
MCH_LVD SA_CLK [7 4]
MCH_LVD SA_DAT0# [74]
MCH_LVD SA_DAT1# [74]
MCH_LVD SA_DAT2# [74]
MCH_LVD SA_DAT0 [74]
MCH_LVD SA_DAT1 [74]
MCH_LVD SA_DAT2 [74]
1 2
RN2001
RN2001
1
2 3
SRN10KJ -5 - G P
SRN10KJ -5-GP
TP2001 T PAD14-GP TP2001 TP AD14-GP
1
37.5 ohm trace to 150R resistor
R2005
R2005
150R2F-1 -GP
150R2F-1 -GP
1 2
GMCH_DD CCLK [55]
GMCH_DD CDATA [55 ]
GMCH_HS YNC [74]
GMCH_VS YNC [74]
1 2
R2004
R2004
1KR2J-1-G P
1KR2J-1-G P
SB-1023
change R2004 from 0.5% to 5%.
L
CDVDD_E N_PCH
A00-0104-1
R
R
2011
2011
0R0402-P AD-2-GP
0R0402-P AD-2-GP
P
ANEL_BK EN_PCHR
L
CDVDD_E N_PCH
LCTLA_C LK
4
LCTLB_D ATA
LIBG
TP_LVDS _VBG
CRT_IREF
3
1 2
R
R
2003
2003
100KR2J -1-GP
100KR2J -1-GP
U
U
2001D
2001D
T48
L
T47
L
Y48
L
AB48
L
Y45
L_DDC_DATA
AB46
L_CTRL_CLK
V48
L_CTRL_DATA
AP39
LVD_IBG
AP41
LVD_VBG
AT43
LVD_VREFH
AT42
LVD_VREFL
AV53
LVDSA_CLK#
AV51
LVDSA_CLK
BB47
LVDSA_DATA#0
BA52
LVDSA_DATA#1
AY48
LVDSA_DATA#2
AV47
LVDSA_DATA#3
BB48
LVDSA_DATA0
BA50
LVDSA_DATA1
AY49
LVDSA_DATA2
AV48
LVDSA_DATA3
AP48
LVDSB_CLK#
AP47
LVDSB_CLK
AY53
LVDSB_DATA#0
AT49
LVDSB_DATA#1
AU52
LVDSB_DATA#2
AT53
LVDSB_DATA#3
AY51
LVDSB_DATA0
AT48
LVDSB_DATA1
AU50
LVDSB_DATA2
AT51
LVDSB_DATA3
AA52
CRT_BLUE
AB53
CRT_GREEN
AD53
CRT_RED
V51
CRT_DDC_CLK
V53
CRT_DDC_DATA
Y53
CRT_HSYNC
Y51
CRT_VSYNC
AD48
DAC_IREF
AB51
CRT_IRTN
IBEXPEAK-M -GP-NF
IBEXPEAK-M -GP-NF
Y
Y
D
D
_BKLTEN
_VDD_EN
_BKLTCTL
_DDC_CLK
4
4
OF 10
OF 10
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ46
BG46
BJ48
BG48
BF45
BH45
T51
T53
BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
Y49
AB49
BE44
BD44
AV40
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
U50
U52
BC46
BD46
AT38
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
S
DVO_TVCLKINN
S
DVO_TVCLKINP
DVO_STALLN
S
S
DVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT
CRT
2
1
A A
5
4
3
2
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH (LVDS/CRT/DDI)
PCH (LVDS/CRT/DDI)
PCH (LVDS/CRT/DDI)
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
20 88 Wednesd ay, January 13, 2010
20 88 Wednesd ay, January 13, 2010
20 88 Wednesd ay, January 13, 2010
1
A00
A00
A00
5
R
R
N2101
CI_DEVSEL #
P
CI_IRDY#
P
CI_SERR#
P
I
+
3.3V_RUN
D D
+
3.3V_RUN
C C
NT_PIRQC#
P
CI_PERR#
P
CI_REQ0#
CI_REQ3#
P
P
CI_FRAME#
+3.3V_RU N
EDID_SELE CT# [54,55]
N2101
1
2
3
4
5 6
SRN8K2J -2-GP-U
SRN8K2J -2-GP-U
R
R
N2102
N2102
1
2
3
4
5 6
SRN8K2J -2-GP-U
SRN8K2J -2-GP-U
1
2
3
4 5
RN2103
RN2103
SRN10KJ -7GP
SRN10KJ -7GP
DGPU_PW M_SELECT#
8
EDID_SELE CT_R#
7
PCH_GPIO4
6
INT_PIRQE#
+3.3V_RU N
1 2
DY
DY
0
1
GPU_SEL ECT#
D
9
NT_PIRQD#
I
8
P
CI_STOP#
7
NT_PIRQA#
I
1
0
I
NT_PIRQB#
9
CI_PLOCK#
P
8
P
CI_REQ1#
7
CI_TRDY#
P
SB-1022
DY U2102; POP R2105
U2102
U2102
5
4
R2105 0R2 J-2-GP R2105 0R2 J-2-GP
C2112
C2112
SC220P5 0V2KX-3GP
SC220P5 0V2KX-3GP
B
VCC
A
Y
DY
DY
GND
74LVC1G 08GW-1-GP
74LVC1G 08GW-1-GP
1 2
+
3.3V_RUN
1
EDID_SELE CT_R#
2
3
3.3V_RUN
+
BOOT BIOS Strap
PCI_GNT#1 BO OT BIOS Locatio n PCI_GNT#0
0 0 LPC
0 1 Reserved
0 1
B B
A16 swap overrid e Strap/Top-Blo ck
Swap Override ju mper
PCI_GNT#3 Low = A16 swap
A A
PCI_GNT3#
1 1
override/Top-Blo ck
Swap Override en abled
High = Default
R2109
R2109
1 2
DY
DY
4K7R2J-2 -GP
4K7R2J-2 -GP
5
PCI
SPI(Default)
4
C
C
2101
2101
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
P
SB-1022
DY U2101; POP R2104
W
D
7/02 Added
0
1. using the single buffers f or 4 device with
equivalent capability.
2.Rename PCI_PLTRST#
1 2
LT_RST# [9,34,36,37 ,64,70,76,80]
DGPU_PW M_SELECT# [54]
PCLK_FW H [70]
CLK_PCI_F B [23]
PCLK_KB C [37]
PCLK_TP M [36]
Calpella Platform Design Guide
Revision 1.6
Table 111. Overcurrent Pin Example Configuration
These OC7# pins are not used for USB overcurrent protection and should be configured as GPIOs.
The unused USB ports can be left as no connect.
4
+
3.3V_RUN
U
U
2101
2101
5
V
CC
4
Y
74LVC1G 08GW-1-GP
74LVC1G 08GW-1-GP
1 2
R2104 0R2 J-2-GP R2104 0R2 J-2-GP
DGPU_SE LECT# [37,54,74]
TP2116 TPAD14-GPTP 2116 TPA D14-GP
HDD_FAL L_INT1 [4 0]
WW AN_RF_EN [76]
R2110 22R2J-2-G P
R2110 22R2J-2-G P
1 2
DY
DY
R2108 22R2J-2-G P R2108 22R2J-2-GP
1 2
R2111 22R2J-2-G P R2111 22R2J-2-GP
1 2
R2112 22R2J-2-G P
R2112 22R2J-2-G P
1 2
DY
DY
3
5
2001E
2001E
U
U
H40
D0
A
N34
A
D1
C44
A
D2
A38
D3
A
C36
A
D4
J34
A
D5
A40
A
D6
D45
A
D7
E36
A
D8
H48
A
1
B
LTRST#_ PCH
P
2
A
D
D
Y
Y
3
ND
G
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
PCI_REQ0#
PCI_REQ1#
DGPU_SE LECT#
PCI_REQ3#
1
R2121
R2121
0R2J-2-GP
0R2J-2-GP
1 2
TP2108 TPAD14-GPTP 2108 TPA D14-GP
TP2115 TPAD14-GPTP 2115 TPA D14-GP
PCI_GNT0#
DGPU_PW M_SELECT#
PCI_GNT3#
INT_PIRQE#
WW AN_RF_EN
PCH_GPIO4
EDID_SELE CT_R#
PCIRST#
1
PCI_SERR#
PCI_PERR#
PCI_IRDY#
PCI_DEVSE L#
PCI_FRAME #
PCI_PLOCK #
PCI_STOP#
PCI_TRDY#
PCH_PME #
1
PLTRST# _PCH
PCLK_FW H_R
CLK_PCI_F B_R
PCLK_KB C_R
PCLK_TP M_R
D9
E40
A
D10
C40
A
D11
M48
D12
A
M45
A
D13
F53
D14
A
M40
AD15
M43
AD16
J36
AD17
K48
AD18
F40
AD19
C42
AD20
K46
AD21
M51
AD22
J52
AD23
K51
AD24
L34
AD25
F42
AD26
J40
AD27
G46
AD28
F44
AD29
M47
AD30
H36
AD31
J50
C/BE0#
G42
C/BE1#
H47
C/BE2#
G34
C/BE3#
G38
PIRQA#
H51
PIRQB#
B37
PIRQC#
A44
PIRQD#
F51
REQ0#
A46
REQ1#/GPIO50
B45
REQ2#/GPIO52
M53
REQ3#/GPIO54
F48
GNT0#
K45
GNT1#/GPIO51
F36
GNT2#/GPIO53
H53
GNT3#/GPIO55
B41
PIRQE#/GPIO2
K53
PIRQF#/GPIO3
A36
PIRQG#/GPIO4
A48
PIRQH#/GPIO5
K6
PCIRST#
E44
SERR#
E50
PERR#
A42
IRDY#
H44
PAR
F46
DEVSEL#
C46
FRAME#
D49
PLOCK#
D41
STOP#
C48
TRDY#
M7
PME#
D5
PLTRST#
N52
CLKOUT_PCI0
P53
CLKOUT_PCI1
P46
CLKOUT_PCI2
P51
CLKOUT_PCI3
P48
CLKOUT_PCI4
IBEXPEAK-M -GP-NF
IBEXPEAK-M -GP-NF
PCI
PCI
N
N
N
N
N
N
N
V_DQ0/NV_IO0
N
V_DQ1/NV_IO1
N
V_DQ2/NV_IO2
N
V_DQ3/NV_IO3
V_DQ4/NV_IO4
N
N
V_DQ5/NV_IO5
V_DQ6/NV_IO6
N
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8
NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11
NVRAM
NVRAM
NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15
NV_RCOMP
NV_WR#0_RE#
NV_WR#1_RE#
NV_WE#_CK0
NV_WE#_CK1
USB
USB
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
5
V_CE#0
V_CE#1
V_CE#2
V_CE#3
V_DQS0
V_DQS1
NV_ALE
NV_CLE
NV_RB#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
OF 10
OF 10
2
AY9
BD1
AP15
BD8
AV9
BG8
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
TP_NV_A LE
BD3
TP_NV_C LE
AY6
TP_NV_R COMP
AU2
AV7
AY8
AY5
AV11
BF5
Port 0 for debug port
H18
J18
A18
C18
N20
P20
TP_USB_ PN3
J20
TP_USB_ PP3
L20
F20
G20
A20
C20
TP_USB_ PN6
M22
TP_USB_ PP6
N22
TP_USB_ PN7
B21
TP_USB_ PP7
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
TP_USB_ PN13
A24
TP_USB_ PP13
C24
USB_RBIAS _PN
B25
D25
USB_OC# 0_1
N16
USB_OC# 2_3
J16
USB_OC# 4_5
F16
USB_OC# 6_7
L16
USB_OC# 8_9
E14
USB_OC# 10_11
G16
USB_OC# 12_13
F12
PCH_OC7 #
T15
TP2124 TPAD14-GP TP2124 TPAD14-GP
1
TP2125 TPAD14-GP TP2125 TPAD14-GP
1
TP2130 TPAD14-GP TP2130 TPAD14-GP
1
USB_PN0 [63]
USB_PP0 [63]
USB_PN1 [63]
USB_PP1 [63]
USB_PN2 [76]
USB_PP2 [76]
TP2122 TP 2122
TP2123 TP 2123
USB_PN4 [64]
USB_PP4 [64]
USB_PN5 [76]
USB_PP5 [76]
TP2118 TP 2118
TP2119 TP 2119
TP2120 TP 2120
TP2121 TP 2121
USB_PN8 [73]
USB_PP8 [73]
USB_PN9 [32]
USB_PP9 [32]
USB_PN1 0 [78]
USB_PP1 0 [78]
USB_PN1 1 [73]
USB_PP1 1[73]
USB_PN1 2 [34]
USB_PP1 2 [34]
TP2128 TP 2128
TP2129 TP 2129
1 2
S
SID = PCH
D
MI Termination V oltage
NV_CLE Set t o Vss when low.
Set to Vcc when high.
Low = Default
unused NV_SLE st rap
R2106
R2106
22D6R2F -L1-GP
22D6R2F -L1-GP
USB_OC# 0_1 [22 ,63]
USB_OC# 2_3 [76 ]
Pull up in page 22
for layout convenience
USB_OC# 12_13 [23]
1
USB
Pair
Device
USB1
0
USB for ESATA
1
USB2
2
RESERVE
3
WLAN
4
WWAN
5
RESERVED
6
(Not available f or HM55)
RESERVED
7
(Not available f or HM55)
BlUETOOTH
8
Card Reader
9
Biometric
10
CAMERA
11
New Card
12
RESERVED
13
SB
swap net for layout
Pull up in page 23 for layout convenience
Page 233
RP2101
+3.3V_AL W
3
PCH_OC7 #
USB_OC# 2_3
USB_OC# 4_5
RP2101
1
2
3
4
5 6
SRN10KJ -L3-GP
SRN10KJ -L3-GP
10
PM_RI#
9
USB_OC# 8_9 USB_OC# 6_7
8
PEG_B_C LKRQ#
7
USB_OC# 10_11
SB
swap net for layout
+3.3V_AL W
PM_RI# [22]
PEG_B_C LKRQ# [23]
2
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH (PCI/USB/NVRAM)
PCH (PCI/USB/NVRAM)
PCH (PCI/USB/NVRAM)
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
21 88 Wednesd ay, January 13, 2010
21 88 Wednesd ay, January 13, 2010
21 88 Wednesd ay, January 13, 2010
1
A00
A00
A00
5
S
SID = PCH
D D
+1.05V_V TT
R2204
R2204
1 2
49D9R2F -GP
49D9R2F -GP
D
MI_CTX_PR XN0 [8]
D
MI_CTX_PR XN1 [8]
D
MI_CTX_PR XN2 [8]
D
MI_CTX_PR XN3 [8]
D
MI_CTX_PR XP0 [8]
D
MI_CTX_PR XP1 [8]
MI_CTX_PR XP2 [8]
D
D
MI_CTX_PR XP3 [8]
D
MI_PTX_CR XN0 [8]
DMI_PTX_C RXN1 [8]
DMI_PTX_C RXN2 [8]
DMI_PTX_C RXN3 [8]
DMI_PTX_C RXP0 [8 ]
DMI_PTX_C RXP1 [8 ]
DMI_PTX_C RXP2 [8 ]
DMI_PTX_C RXP3 [8 ]
DMI_IRCOMP_R
+3.3V_RU N
1 2
Remove XDP
pull-up ?
C C
B B
XDP_DBR ESET# [9]
A00-0104-1
R2207 0R0402-P AD-2-GP R2207 0R0402-P AD-2-GP
PM_PW ROK [37]
PM_DRAM _PWRGD [9]
RSMRST# _KBC [37 ] PM_SLP_ S4# [3 4,37,50]
SUS_PW R_DN_ACK [37]
PM_PW RBTN# [3 7]
AC_PRES ENT_EC [37]
PM_RI# [21]
1 2
R2208
R2208
1 2
R2209 10KR2J-3 -GP R2 209 10KR2J-3 -GP
1 2
A00-0104-1
AC_PRESENT_EC
10KR2J-3 -GP
10KR2J-3 -GP
1 2
R2210 0R2 J-2-GP R2210 0R2J-2-GP
1 2
R2218 0R0 402-PAD-2-GP R221 8 0R0 402-PAD-2-GP
1 2
R2213 0R0 402-PAD-2-GP R221 3 0R0 402-PAD-2-GP
1 2
R2216 0R0 402-PAD-2-GP R221 6 0R0 402-PAD-2-GP
4
R2205
R2205
10KR2J-3 -GP
10KR2J-3 -GP
XDP_DBR ESET#
PM_PW RGD
LAN_RST #1
PM_DRAM _PWRGD
PM_RSMR ST#_R
SUS_PW R_ACK
PM_PW RBTN#_R
AC_PRESENT
PM_BATL OW#_R
PM_RI#
U
U
2001C
2001C
BC24
D
MI0RXN
BJ22
D
MI1RXN
AW20
D
MI2RXN
BJ20
D
MI3RXN
BD24
D
MI0RXP
BG22
D
MI1RXP
BA20
D
MI2RXP
BG20
MI3RXP
D
BE22
MI0TXN
D
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_DN_ACK/GPIO30
P5
PWRBTN#
P7
ACPRESENT/GPIO31
A6
BATLOW#/GPIO72
F14
RI#
IBEXPEAK-M -GP-NF
IBEXPEAK-M -GP-NF
3
OF 10
OF 10
3
3
DI_RXN0
F
F
DI_RXN1
F
DI_RXN2
F
DI_RXN3
F
DI_RXN4
F
DI_RXN5
F
DI_RXN6
F
DI_RXN7
DI_RXP0
F
F
DI_RXP1
DI_RXP2
F
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
FDI_FSYNC0
DMI
FDI
DMI
FDI
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
WAKE#
CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_S4#
SLP_S3#
SLP_M#
System Power Management
System Power Management
TP23
PMSYNCH
SLP_LAN#/GPIO29
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
BJ14
BF13
BH13
BJ12
BG14
J12
Y1
P8
F3
E4
H7
P12
K8
N2
BJ10
F6
DI_TXN0
F
F
DI_TXN1
F
DI_TXN2
F
DI_TXN3
F
DI_TXN4
F
DI_TXN5
F
DI_TXN6
F
DI_TXN7
DI_TXP0
F
F
DI_TXP1
DI_TXP2
F
F
DI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
PM_CLKR UN#
TP_SUS_ STAT#
PCH_SUS CLK
PCH_SLP _S5#
PM_SLP_ S4#_R
PM_SLP_ S3#_R
SIO_SLP_M# _R
PM_SLP_ DSW#
H_PM_SYNC
F
DI_TXN0 [8]
F
DI_TXN1 [8]
F
DI_TXN2 [8]
F
DI_TXN3 [8]
F
DI_TXN4 [8]
F
DI_TXN5 [8]
F
DI_TXN6 [8]
F
DI_TXN7 [8]
F
DI_TXP0 [8]
DI_TXP1 [8]
F
F
DI_TXP2 [8]
FDI_TXP3 [8]
FDI_TXP4 [8]
FDI_TXP5 [8]
FDI_TXP6 [8]
FDI_TXP7 [8]
FDI_INT [8]
FDI_FSYNC0 [8 ]
FDI_FSYNC1 [8 ]
FDI_LSYNC0 [8]
FDI_LSYNC1 [8]
1
TP2205TPAD14-GP TP 2205TPAD14-GP
1
TP2202TPAD14-GP TP 2202TPAD14-GP
1 2
R2211 0R04 02-PAD-2-GP R221 1 0R0 402-PAD-2-GP
1 2
R2212 0R04 02-PAD-2-GP R221 2 0R0 402-PAD-2-GP
1
TP2203TPAD14-GP TP 2203TPAD14-GP
1
TP2204TPAD14-GP TP 2204TPAD14-GP
PCIE_W AKE# [34,76]
PM_CLKR UN# [37]
A00-0104-1
2
U
SB_OC#0 _1 [21 ,63]
Close to PCH
1 2
R2219 0R04 02-PAD-2-GP R221 9 0R0 402-PAD-2-GP
A00-0104-1
1 2
R2220 0R04 02-PAD-2-GP R222 0 0R0 402-PAD-2-GP
PM_SLP_ S3# [34,37,42,50,5 1,86]
H_PM_SYNC [9]
1
+
3.3V_ALW
R
R
N2201
U
SB_OC#0 _1
S
US_PW R_ACK
M_BATLO W#_R
P
CIE_WA KE#
P
AC_PRES ENT_EC
Option to " Disable " clkrun.
Pulling it down will keep the clks running.
PM_CLKR UN#
10KR2J-3 -GP
10KR2J-3 -GP
PCH_SUS CLK_2102 [39]
PCH_SUS CLK_KBC [37]
N2201
2 3
1
4
SRN10KJ -5-GP
SRN10KJ -5-GP
1 2
R
R
2201 1 0KR2J-3-GP
2201 1 0KR2J-3-GP
1 2
R
R
2202 1 KR2J-1-GP
2202 1 KR2J-1-GP
1 2
R2217 10KR2J-3 -GP R2 217 10KR2J-3 -GP
+3.3V_RU N
R2214
R2214
10KR2J-3 -GP
10KR2J-3 -GP
1 2
1 2
R2215
R2215
DY
DY
Pull up in page 23 for layout convenience
KBC_PW R
R2221
R2221
10KR2J-3 -GP
10KR2J-3 -GP
DY
DY
1 2
U2213
U2213
3 4
2
5
DY
DY
2213_56
U
A A
PM_RSMR ST#_R
5
1
6
DMN66D0 LDW-7-GP
DMN66D0 LDW-7-GP
R2203
R2203
1 2
10KR2J-3 -GP
10KR2J-3 -GP
PM_RSMR ST#_R
3V_5V_P OK [37,46]
SB-31
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
PCH (DM I/FDI/PM)
PCH (DM I/FDI/PM)
PCH (DM I/FDI/PM)
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
22 88 Wednesd ay, January 13, 2010
22 88 Wednesd ay, January 13, 2010
22 88 Wednesd ay, January 13, 2010
1
A00
A00
A00
5
S
SID = PCH
BG30
BJ30
BF29
BH29
D D
P
CIE_IRXN2_MTXN2 [64]
P
CIE_IRXP2_MTXP2 [64]
P
CIE_ITXN2_MRXN2 [64]
P
CIE_ITXP2_MRXP2 [64]
PCIE_IRXN3_LRTXN3 [76]
PCIE_IRXP3_LRTXP3 [76]
PCIE_ITXN3_LRXN3 [76]
PCIE_ITXP3_LRXP3 [76]
PCIE_IRXN4_MTXN4 [76]
PCIE_IRXP4_MTXP4 [76]
PCIE_ITXN4_MRXN4 [76]
PCIE_ITXP4_MRXP4 [76]
PCIE_IRXN5_NTXN5 [34]
PCIE_IRXP5_NTXP5 [34]
PCIE_ITXN5_NRXN5 [34]
PCIE_ITXP5_NRXP5 [34]
C C
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW.
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN
2318 SCD1U10V2KX-5GP
2318 SCD1U10V2KX-5GP
C
C
C
C
C2303 SCD1U10V2KX-5GP C2303 SCD1U10V2K X-5GP
C2309 SCD1U10V2KX-5GP C2309 SCD1U10V2K X-5GP
C2302 SCD1U10V2KX-5GP C2302 SCD1U10V2K X-5GP
C2311 SCD1U10V2KX-5GP C2311 SCD1U10V2K X-5GP
C2308 SCD1U10V2KX-5GP C2308 SCD1U10V2K X-5GP
C2304 SCD1U10V2KX-5GP C2304 SCD1U10V2K X-5GP
1 2
2310 SCD1U10V2KX-5GP
2310 SCD1U10V2KX-5GP
12
1 2
12
1 2
12
1 2
12
A00-0104-1
RN2311
CLK_PCIE_NEW # [34]
CLK_PCIE_NEW [34]
NEWCA RD_CLKREQ# [34]
CLK_PCIE_MINI1# [64]
CLK_PCIE_MINI1 [ 64]
MINI1_CLKREQ# [64]
CLK_PCIE_LAN# [76]
CLK_PCIE_LAN [76]
CLKREQ#_LAN [76]
CLK_PCIE_MINI2# [76]
B B
CLK_PCIE_MINI2 [ 76]
RN2311
0R4P2R-PAD
0R4P2R-PAD
RN2305
RN2305
0R4P2R-PAD
0R4P2R-PAD
RN2304
RN2304
0R4P2R-PAD
0R4P2R-PAD
RN2309
RN2309
0R4P2R-PAD
0R4P2R-PAD
PEG_B_CLKRQ# [21]
1
2 3
1
2 3
1
2 3
2 3
1
P
P
PCIE_ITXN3_LRXN3_C
PCIE_ITXP3_LRXP3_C
PCIE_ITXN4_MRXN4_C
PCIE_ITXP4_MRXP4_C
PCIE_ITXN5_NRXN5_C
PCIE_ITXP5_NRXP5_C
RN
RN
CLK_PCIE_NEW 1#
4
CLK_PCIE_NEW 1
RN
RN
CLK_PCIE_MINI1_1#
4
CLK_PCIE_MINI1_1
RN
RN
CLK_PCIE_LAN1#
4
CLK_PCIE_LAN1
CLK_PCIE_MINI2_1#
CLK_PCIE_MINI2_1
4
RN
RN
PCIECLKRQ5#
PEG_B_CLKRQ#
CIE_ITXN2_MRXN2_C
CIE_ITXP2_MRXP2_C
NEWCA RD_CLKREQ#
MINI1_CLKREQ#
CLKREQ#_LAN
MINI2_CLKREQ#
AW30
BA30
BC30
BD30
AU30
AT30
AU32
AV32
BA32
BB32
BD32
BE32
BF33
BH33
BG32
BJ32
BA34
AW34
BC34
BD34
AT34
AU34
AU36
AV36
BG34
BJ34
BG36
BJ36
AK48
AK47
AM43
AM45
AM47
AM48
AH42
AH41
AM51
AM53
AJ50
AJ52
AK53
AK51
P13
Pull up in page 21 for layout convenience
+3.3V_RUN
1 2
R2333
R2333
10KR2J-3-GP
10KR2J-3-GP
A A
MINI2_CLKREQ_R# [76]
1ST: 84.03904.H11
2ND: 84.03904.L06
5
Q2306_1
1
Q2306
Q2306
MMBT3904-7-F-GP
MMBT3904-7-F-GP
MINI2_CLKREQ#
3
2
R2309 0R2J-2-GP
R2309 0R2J-2-GP
1 2
DY
DY
4
U
U
2001B
2001B
P
ERN1
P
ERP1
ETN1
P
P
ETP1
P
ERN2
ERP2
P
WLAN
P
ETN2
ETP2
P
PERN3
PERP3
LAN
PETN3
PETP3
PERN4
PERP4
WWAN
PETN4
PETP4
PERN5
New
PERP5
PETN5
Card
PETP5
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
CLKOUT_PCIE0P
P9
PCIECLKRQ0#/GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
U4
PCIECLKRQ1#/GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
N4
PCIECLKRQ2#/GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
A8
PCIECLKRQ3#/GPIO25
CLKOUT_PCIE4N
CLKOUT_PCIE4P
M9
PCIECLKRQ4#/GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
H6
PCIECLKRQ5#/GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ#/GPIO56
IBEXPEAK-M-GP- NF
IBEXPEAK-M-GP- NF
+3.3V_ALW
+3.3V_RUN
4
RN2307
RN2307
8
7
6
SRN10KJ-7GP
SRN10KJ-7GP
RN2308
RN2308
8
7
6
SRN10KJ-6-GP
SRN10KJ-6-GP
S
MBALERT#/GPIO11
S
ML0ALERT#/GPIO60
SML1ALERT#/GPIO74
SMBus
SMBus
PCI-E*
PCI-E*
Controller
Controller
PEG
PEG
CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P
From CLK BUFFER
From CLK BUFFER
Clock Flex
Clock Flex
PCIECLKRQ5#
1
USB_OC#12_13
2
CLKREQ#_LAN
3
MINI2_CLKREQ#
4 5
NEWCA RD_CLKREQ#
1
KB_DET_R#
2
GPO_DSM
3
MINI1_CLKREQ#
4 5
SB-1023
RN2308 change to 2*1 size
SML1CLK/GPIO58
SML1DATA/GPIO75
Link
Link
PEG_A_CLKRQ#/GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N/CKSSCD_N
CLKIN_SATA_P/CKSSCD_P
CLKIN_PCILOOPBACK
XCLK_RCOMP
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
SB
swap net for layout
SB-1026
swap net for layout
2
2
OF 10
OF 10
MBCLK
S
MBDATA
S
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
CLKIN_DMI_N
CLKIN_DMI_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
USB_OC#12_13 [21]
S
B9
P
H14
P
C8
S
J14
S
C6
SML0_DATA
G8
SML1ALERT#
M14
KBC_SCL1
E10
KBC_SDA1
G12
CL_CLK
T13
CL_DATA
T11
CL_RST#
T9
PEG_CLKREQ#
H1
CLK_PCIE_VGA1#
AD43
CLK_PCIE_VGA1
AD45
CLK_EXP_N
AN4
CLK_EXP_P
AN2
AT1
AT3
CLKIN_DMI#
AW24
CLKIN_DMI
BA24
CLK_CPU_BCLK#
AP3
CLK_CPU_BCLK
AP1
DREFCLK#
F18
DREFCLK
E18
CLK_PCIE_SATA#
AH13
CLK_PCIE_SATA
AH12
CLK_PCH_14M
P41
CLK_PCI_FB
J42
XTAL25_IN
AH51
XTAL25_OUT
AH53
XCLK_RCOMP
AF38
TP_CLK_OUTFLEX0
T45
TP_CLK_PCI_LPC
P43
TP_CLK_PCH_REF14
T42
CLK48M/EDID_SEL
N50
KB_DET_R# [25]
GPO_DSM [2 4,76]
3
ML0ALERT#
S
ML1ALERT#
MBALERT#
CH_SMB_CLK
CH_SMB_DATA
ML0ALERT#
ML0_CLK
S
R
R
1 2
2301 10KR2J-3-GP
2301 10KR2J-3-GP
R
SRN10KJ-5-GP
SRN10KJ-5-GP
+
emove XDP
pull-up
1
TP2301 TPAD14-GP T P2301 TPAD14-G P
1
TP2302 TPAD14-GP T P2302 TPAD14-G P
1
TP2303 TPAD14-GP T P2303 TPAD14-G P
RN2327
RN2327
0R4P2R-PAD
0R4P2R-PAD
1 2
R2307 0R0402- PAD-2-GP R2307 0R0402-PAD-2-G P
SB-1020
move EDID_SELECT# from GPIO66 to GPIO5
3
1
2 3
CLK_EXP_N [ 9]
CLK_EXP_P [9]
CLKIN_DMI# [7]
CLKIN_DMI [7]
CLK_CPU_BCLK# [7]
CLK_CPU_BCLK [7]
DREFCLK# [7]
DREFCLK [7]
CLK_PCIE_SATA# [7]
CLK_PCIE_SATA [7]
CLK_PCH_14M [7]
CLK_PCI_FB [21]
1 2
R2306 90D9R2F -1-GP R2306 90D9R2F -1-GP
TP2307
TP2307
1
TPAD14-GP
TPAD14-GP
TP2305
TP2305
1
TPAD14-GP
TPAD14-GP
TP2306
TP2306
1
TPAD14-GP
TPAD14-GP
A00-0104-1
N2301
N2301
R
R
1
2 3
3.3V_ALW
CH_SMB_CLK [34]
P
CH_SMB_DATA [34]
P
KBC_SCL1 [37]
KBC_SDA1 [37]
+3.3V_ALW
1 2
R2304
R2304
10KR2J-3-GP
10KR2J-3-GP
RN
RN
A00-0104-1
4
+1.05V_VTT
+
3.3V_ALW
4
SB-1020
CLK_PCIE_VGA# [80]
CLK_PCIE_VGA [80]
CLK_PCH_48M [32]
2
+
+
3.3V_ALW
1
2 3
R
R
N2313
N2313
SRN2K2J-1-GP
SRN2K2J-1-GP
4
PCH_SMB_DATA
PCH_SMB_CLK
DGPU_1D8V_PGOOD [25,51]
+3.3V_RUN
3.3V_ALW
P
CH_SMB_CLK
PCH_SMB_DATA
RN2303
RN2303
2 3
1
SRN2K2J-1-GP
SRN2K2J-1-GP
6
5
1
2 3
R
R
N2302
N2302
SRN2K2J-1-GP
SRN2K2J-1-GP
4
4
1
2
3 4
Q2301
Q2301
DMN66D0LDW -7-GP
DMN66D0LDW -7-GP
PEG_CLKREQ#
G
S D
Q2305
Q2305
2N7002A-7-GP
2N7002A-7-GP
1
SB-1020
PCH_SMBDATA [7,18,1 9,40,64,76]
1ST: 84.DMN66.03F
2ND: 84.27002.F3F
PCH_SMBCLK [ 7,18,19,40,64,76]
1ST: 84.2N702.E31
2ND: 84.2N702.D31
un-stuff 25M X'tal without HDMI/eDP/DP
SC-1125-1
C2313 pop 0 ohm if no use 25MHz XTAL
C2313
XTAL25_IN
1 2
DY
DY
R2380
R2380
1MR2J-1-GP
1MR2J-1-GP
XTAL25_OUT
SB-1104
pop for 25MHz
1st Samsung
1st Samsung
1st Samsung
Title
Title
Title
PCH (PCI-E/SMBUS/CLOCK/CL)
PCH (PCI-E/SMBUS/CLOCK/CL)
PCH (PCI-E/SMBUS/CLOCK/CL)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
C2313
1 2
0R2J-2-GP
0R2J-2-GP
1 2
DY
DY
X2301
X2301
12
XTAL-25MHZ-67GP
XTAL-25MHZ-67GP
DY
DY
C2307
C2307
SC18P50V2JN-1-G P
SC18P50V2JN-1-G P
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,
21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,
21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
1
A00
A00
23 88 Wednesday, January 13, 2010
23 88 Wednesday, January 13, 2010
23 88 Wednesday, January 13, 2010
A00
5
CH_RTCX 1
P
CH_RTCX 2
1 2
2401
2401
R
R
10MR2J-L -GP
10MR2J-L -GP
X
X
2401
2401
1
4
1 2
C
C
2402
2402
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
D D
S
B-18
1st: EPSON 82.30001.861
2nd: QUARTECH 82.30001.A81
DW
07/23 Added
1.Added "ME in Manufacturing Mode" strap
2.Added CardReader_Wake# to s ent Card detect signal for P CH . ( Only For JMB380 )
3rd: KDS 82.30001.691
Flash Descriptor Security
Override/ ME Debug Mode
ME_UNLOCK#
C C
1 2
R2419 1KR2J-1-GP
R2419 1KR2J-1-GP
+3.3V_RU N
B B
SB-1026
1. remove R2411 pull high INT_SERIRQ to RN2501.1
NO REBOOT STRAP
1 2
DY
DY
R2410 1KR2J-1-GP
R2410 1KR2J-1-GP
DW
07/02 Change
1.Change R2410 to dummy
2 3
X-32D768 KHZ-46GP
X-32D768 KHZ-46GP
This strap should only be asserted low via
external pull down in manufacturing/debug
environments ONLY.
DY
DY
SB_SPKR
ME_UNLO CK_R#
P
1 2
C
C
2403
2403
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
No Reboot Strap R23
HDA_SPKR
Low = Default
High = No Reboot
RTC_CEL L
+
RTC_CEL L
+
1 2
C
C
2401
2401
SC1U6D3 V3KX-2GP
SC1U6D3 V3KX-2GP
1 2
C2404
C2404
SC1U6D3 V3KX-2GP
SC1U6D3 V3KX-2GP
2402
2402
R
R
20KR2J-L 2- GP
20KR2J-L 2-GP
R
R
2403
2403
20KR2J-L 2- GP
20KR2J-L 2-GP
4
I
NTVRMEN- Integrated SUS
1 2
2 1
1 2
G2401
G2401
GAP-OPEN
GAP-OPEN
+RTC_CE LL
PCH_AZ_ CODEC_BITCLK [30]
PCH_AZ_ CODEC_SYNC [30]
PCH_AZ_ CODEC_RST# [30]
PCH_SDIN_ CODEC [30]
SB_SPKR [30]
PCH_SDO UT_CODEC [30]
ME_UNLO CK# [37]
PCH_SPI_C LK [62]
PCH_SPI_C S0# [62]
PCH_SPI_D O [62]
PCH_SPI_D I [62]
SC-1208-1
change R2413,R2414,R2415 from 15ohm to 0 ohm
1.1V VRM Enable
High - Enable internal VRs
1 2
R2406 1MR 2J-1-GP R2406 1MR2J-1 -GP
1 2
R2404 33 0KR2F-L-GP R2404 330 KR2F-L-GP
1 2
1 2
1 2
1 2
R2417
R2417
1 2
0R0402-P AD-2-GP
0R0402-P AD-2-GP
A00-0104-1
R2413 0R2J-2-GP R2413 0R2J-2-GP
R2414 0R2J-2-GP R2414 0R2J-2-GP
R2415 0R2J-2-GP R2415 0R2J-2-GP
33R2J-2-G PR24 05 33R2J-2-GPR2 405
33R2J-2-G PR24 07 33R2J-2-GPR2 407
33R2J-2-G PR24 08 33R2J-2-GPR2 408
33R2J-2-G PR24 09 33R2J-2-GPR2 409
TP2404 TP 2404
TP2405 TP 2405
TP2406 TP 2406
TP2407 TP 2407
TP2408 TP 2408
1 2
1 2
1 2
3
CH_RTCX 1
P
CH_RTCX 2
P
PCH_RTC RST#
SRTCRST #
SM_INTRUD ER#
PCH_INTVR MEN
ACZ_BIT_C LK
ACZ_SYNC_ R
ACZ_RST #_R
ACZ_SDA TAOUT_R
ME_UNLO CK_R#
PCH_JTA G_TCK
1
PCH_JTA G_TMS
1
PCH_JTA G_TDI
1
PCH_JTA G_TDO
1
PCH_JTA G_RST#
1
SPI_CLK_R
SPI_CS#0_ R
SPI_MOSI_R
U
U
2001A
2001A
B13
TCX1
R
D13
TCX2
R
C14
RTCRST#
D17
SRTCRST#
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
D29
HDA_SYNC
P1
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN#/GPIO33
J30
HDA_DOCK_RST#/GPIO13
M3
JTAG_TCK
K3
JTAG_TMS
K1
JTAG_TDI
J2
JTAG_TDO
J4
TRST#
BA2
SPI_CLK
AV3
SPI_CS0#
AY3
SPI_CS1#
AY1
SPI_MOSI
AV1
SPI_MISO
IBEXPEAK-M -GP-NF
IBEXPEAK-M -GP-NF
RTC IHDA
RTC IHDA
SPI JTAG
SPI JTAG
WH0/LAD0
F
WH1/LAD1
F
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
LDRQ1#/GPIO23
LPC
LPC
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED#
SATA0GP/GPIO21
SATA1GP/GPIO19
1
1
OF 10
OF 10
LDRQ0#
SERIRQ
2
PC_LAD0
D33
B33
C32
A32
C34
A34
F34
AB9
AK7
AK6
AK11
AK9
AH6
AH5
AH9
AH8
AF11
AF9
AF7
AF6
AH3
AH1
AF3
AF1
AD9
AD8
AD6
AD5
AD3
AD1
AB3
AB1
AF16
AF15
T3
Y9
V1
L
PC_LAD1
L
L
PC_LAD2
LPC_LAD 3
SATA_ITXN 0_HRXN0_C
SATA_ITXP 0_HRXP0_C
SATA_ITXN 1_ORXN1_C
SATA_ITXP 1_ORXP1_C
SATAICOMP
GPO_DSM
PCH_GPIO19
DW
07/10 assign GPIO
1.assign GPIO GPIO_DSM,Felic_ DETECT#
S
SID = PCH
L
PC_LAD[0 ..3]
LPC_LFR AME# [36,37,70 ]
INT_SERIRQ [25,36,37 ]
C2405 SC D01U25V2KX-3G P C2405 SC D01U25V2KX-3G P
1 2
C2406 SC D01U25V2KX-3G P C2406 SC D01U25V2KX-3G P
1 2
C2407 SC D01U25V2KX-3G P C2407 SC D01U25V2KX-3G P
1 2
C2408 SC D01U25V2KX-3G P C2408 SC D01U25V2KX-3G P
1 2
1 2
R2412 37D4R2F-G P R24 12 37D4R2F -GP
SATA_LE D# [66]
GPO_DSM [2 3,76]
PCH_GPIO19 [25]
PC_LAD[0 ..3] [36,37 ,70]
L
+1.05V_V TT
1
HDD
SATA_IRXN 0_HTXN0_C [59]
SATA_IRXP 0_HTXP0_C [59 ]
SATA_ITXN 0_HRXN0 [59]
SATA_ITXP 0_HRXP0 [59]
ODD
SATA_IRXN 1_OTXN1_C [59]
SATA_IRXP 1_OTXP1_C [59]
SATA_ITXN 1_ORXN1 [59]
SATA_ITXP 1_ORXP1 [59]
ESATA
ESATA_IRX _DTX_N4_C [63]
ESATA_IRX _DTX_P4_C [63 ]
ESATA_ITX _DRX_N4 [63]
ESATA_ITX _DRX_P4 [63]
A A
5
4
3
2
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
PCH (SPI/RTC/LPC/SATA/IHDA)
PCH (SPI/RTC/LPC/SATA/IHDA)
PCH (SPI/RTC/LPC/SATA/IHDA)
Size Do cument Number Rev
Size Do cument Number Rev
Size Do cument Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
24 88 Wednesd ay, January 13, 2010
24 88 Wednesd ay, January 13, 2010
24 88 Wednesd ay, January 13, 2010
1
A00
A00
A00
5
R
R
2555
2555
2K2R2J-2 -GP
2K2R2J-2 -GP
2515_1
Q
Q
2515
2515
B-32
S
R2525
R2525
10KR2J-3 -GP
10KR2J-3 -GP
1 2
+3.3V_AL W
+3.3V_AL W
+3.3V_RU N
3.3V_RUN
+
1 2
R
R
2503
2503
10KR2J-3 -GP
10KR2J-3 -GP
B
IO_DET# [78]
E
CSMI# [37]
A00-0104-1
R2505 0R0 402-PAD-2-GP R2 505 0R04 02-PAD-2-GP
R2506 0R0 402-PAD-2-GP R2 506 0R04 02-PAD-2-GP
R3749 100 R2J-2-GP R3749 100 R2J-2-GP
KB_DET# [68]
KB_DET_ R# [2 3]
DGPU_HO LD_RST# [80]
1 2
1 2
1 2
PCH_GPIO3 5
DGPU_PW R_EN# [37]
R2548 100 R2J-2-GP R2548 100R2J -2-GP
DDR_RST _GATE# [9]
TURBO_B OOST_ALERT# [37]
For layout request
3.3V_RUN _GPU+3.3V_RUN _GPU
+
2552
2552
R
R
10KR2J-3 -GP
10KR2J-3 -GP
D
EEPIDLE_W AKE_INT_R# [81]
D D
+3.3V_RU N
R2507
R2507
10KR2J- 3 -GP
10KR2J-3 -GP
DGPU_PW ROK
1 2
C C
R2526
R2526
10KR2J- 3 -GP
10KR2J-3 -GP
1 2
B B
PCH_GPIO2 7
DY
DY
07/10 Added
1.Changed PCH GPIO DDR_RST_GA TE from GPIO57 to GPIO46 , B ason on design guide
07/23 Added
1.Added Finger Printer Detect Pin, control by PCH
2.Change KB_DET signal from E C to PCH control
3.Change LCD_CBL_DET signal f rom EC to PCH control
PCH_GPIO2 8
PCH_GPIO1 5
PCIECLKRQ 6#
SBswap net for layout
ECSMI#
PCH_GPIO5 7
E
CSWI# [3 7]
C2501
C2501
SC47P50 V2JN-3GP
SC47P50 V2JN-3GP
GFX_COR E_PGOOD [86]
DGPU_1D 8V_PGOOD [23,51]
LCD_CBL _DET# [5 4]
1 2
R2530 10K R2J-3-GP R2530 1 0KR2J-3-GP
1 2
R2532 1KR 2J-1-GP R2532 1KR2J-1-G P
1 2
R2521 10K R2J-3-GP R2521 1 0KR2J-3-GP
RN2504
RN2504
1
2 3
SRN10KJ -5-GP
SRN10KJ -5-GP
1 2
Q
1 2
312
MMBT390 4-7-F-GP
MMBT390 4-7-F-GP
1 2
DY
DY
DW
07/02 Change
1.Change CLK_SATA_OE# to pull -down
4
SB-1023
LCD_CBL _DET_R#
DGPU_HO LD_RST#
STP_PCI#
A A
PCH_GPIO1 9 [24]
R2520 10KR2J-3 -GP R2 520 10KR2J-3 -GP
R2516 10KR2J-3 -GP
R2516 10KR2J-3 -GP
1 2
DY
DY
R2517 10KR2J-3 -GP R2 517 10KR2J-3 -GP
1 2
SRN10KJ -5-GP
SRN10KJ -5-GP
PCH_GPIO1 9
PCH_GPIO3 8
2 3
1
RN2503
SB-1026
swap net for layout
RN2503
5
1 2
+3.3V_RU N
4
INT_SERIRQ [24,36,37]
BIO_DET# [78]
INT_SERIRQ
FFS_INT2_ R
DGPU_PW R_EN#
BIO_DET#
E
CSCI# [37]
TP2508 T PAD14-GP TP2508 TP AD14-GP
1 2
FFS_INT2_ R [40]
TP2511 T PAD14-GP TP2511 TP AD14-GP
TP2512 T PAD14-GP TP2512 TP AD14-GP
TP2510 T PAD14-GP TP2510 TP AD14-GP
TP2509 T PAD14-GP TP2509 TP AD14-GP
ECSW I#
ECSCI#
4
D
EEP_IDLE#
E
CSCI#
B
IO_DET#
CSWI#
E
CSMI#
E
PCH_GPIO1 5
DGPU_HO LD_RST#
LCD_CBL _DET_R#
PCH_GPIO2 7
PCH_GPIO2 8
1
STP_PCI#
DGPU_PW R_EN#
DGPU_PR SNT#
PCH_GPIO3 8
PCIECLKRQ 6#
DDR_RST _GATE#
FFS_INT2_ R
TURBO_B OOST_ALERT#
PCH_GPIO5 7
PCH_NCT F_2
1
PCH_NCT F_3
1
PCH_NCT F_1
1
PCH_NCT F_4
1
SRN10KJ -5-GP
SRN10KJ -5-GP
2 3
1
RN2502
RN2502
RN2501
RN2501
1
2
3
4 5
SRN10KJ -6-GP
SRN10KJ -6-GP
4
U
U
2001F
2001F
Y3
B
MBUSY#/GPIO0
C38
T
ACH1/GPIO1
D37
T
ACH2/GPIO6
J32
ACH3/GPIO7
T
F10
PIO8
G
K9
LAN_PHY_PWR_CTRL/GPIO12
T7
GPIO15
AA2
DGPU_PW ROK
KB_DET_ R#
+3.3V_RU N
4
+3.3V_RU N
8
7
6
SB-1023
RN2501 change to 2*1 size
SATA4GP/GPIO16
F38
TACH0/GPIO17
Y7
SCLOCK/GPIO22
H10
GPIO24
AB12
GPIO27
V13
GPIO28
M11
STP_PCI#/GPIO34
V6
SATACLKREQ#/GPIO35
AB7
SATA2GP/GPIO36
AB13
SATA3GP/GPIO37
V3
SLOAD/GPIO38
P3
SDATAOUT0/GPIO39
H3
PCIECLKRQ6#/GPIO45
F1
PCIECLKRQ7#/GPIO46
AB6
SDATAOUT1/GPIO48
AA4
SATA5GP/GPIO49
F8
GPIO57
A4
VSS_NCTF_1
A49
VSS_NCTF_2
A5
VSS_NCTF_3
A50
VSS_NCTF_4
A52
VSS_NCTF_5
A53
VSS_NCTF_6
B2
VSS_NCTF_7
B4
VSS_NCTF_8
B52
VSS_NCTF_9
B53
VSS_NCTF_10
BE1
VSS_NCTF_11
BE53
VSS_NCTF_12
BF1
VSS_NCTF_13
BF53
VSS_NCTF_14
BH1
VSS_NCTF_15
BH2
VSS_NCTF_16
BH52
VSS_NCTF_17
BH53
VSS_NCTF_18
BJ1
VSS_NCTF_19
BJ2
VSS_NCTF_20
BJ4
VSS_NCTF_21
BJ49
VSS_NCTF_22
BJ5
VSS_NCTF_23
BJ50
VSS_NCTF_24
BJ52
VSS_NCTF_25
BJ53
VSS_NCTF_26
D1
VSS_NCTF_27
D2
VSS_NCTF_28
D53
VSS_NCTF_29
E1
VSS_NCTF_30
E53
VSS_NCTF_31
IBEXPEAK-M -GP-NF
IBEXPEAK-M -GP-NF
GPIO
GPIO
NCTF
NCTF
DGPU_PR SNT#
3
C
C
C
R2528
R2528
10KR2J-3 -GP
10KR2J-3 -GP
C
MISC
MISC
CLKOUT_BCLK0_N/CLKOUT_PCIE8N
CLKOUT_BCLK0_P/CLKOUT_PCIE8P
CPU
CPU
RSVD
RSVD
+3.3V_RU N
1 2
R2527
R2527
DY
DY
10KR2J-3 -GP
10KR2J-3 -GP
1 2
3
6
6
OF 10
OF 10
LKOUT_PCIE6N
LKOUT_PCIE6P
LKOUT_PCIE7N
LKOUT_PCIE7P
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
NC_1
NC_2
NC_3
NC_4
NC_5
INIT3_3V#
TP24
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
AH45
AH46
AF48
AF47
U2
AM3
AM1
BG10
T1
BE10
BD10
BA22
AW22
BB22
AY45
AY46
AV43
AV45
AF13
M18
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39
P6
C10
INIT3_3V#
2
KA20GAT E [37 ]
BCLK_CP U_N [9]
BCLK_CP U_P [9]
H_PECI [9]
H_PW RGOOD [9,42 ]
PCH_THE RMTRIP_R
TP2506TPAD14-GP TP 2506TPAD14-GP
1
2
S
SID = PCH
KBRCIN# [37]
1 2
R2511
R2511
56R2J-4-G P
56R2J-4-G P
1st Samsung
1st Samsung
1st Samsung
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
+1.05V_V TT
R2509
R2509
56R2J-4-G P
56R2J-4-G P
1 2
H_THRMT RIP# [9 ,37,42]
Placed Within 2" from PCH
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
PCH (GPIO/CPU)
PCH (GPIO/CPU)
PCH (GPIO/CPU)
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
1
A00
A00
25 88 Wednesd ay, January 13, 2010
25 88 Wednesd ay, January 13, 2010
25 88 Wednesd ay, January 13, 2010
A00
5
SID = PCH
S
+
1.05V_VT T
1
.432A
SC10U6D 3V5KX-1GP
D D
+1.05V_V TT
C C
B B
3.062A
+1.05V_V TT
SC10U6D 3V5KX-1GP
1 2
C2608
C2608
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
C2609
C2609
TP2601
TP2601
1 2
C
C
2601
2601
TP2602 T PAD14-GP TP2602 TPAD 14-GP
1 2
C2610
C2610
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
+1.8V_RU N
1
TPAD14-G P
TPAD14-G P
4
1 2
C
C
D
D
Y
Y
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
1
1 2
C2611
C2611
SC1U10V3KX-3GP
SC1U10V3KX-3GP
1 2
C2614
C2614
A00-0104-1
R2606
R2606
0R0402-P AD-2-GP
0R0402-P AD-2-GP
2602
2602
+1.05V_V TT
SB-21
1 2
C2612
C2612
SC1U10V3KX-3GP
SC1U10V3KX-3GP
+3.3V_RU N
357mA
+VCC_VR M
1 2
VCCFDIPLL
SB-20
VCCAPLL EXP
U
U
AB24
V
AB26
V
AB28
V
AD26
V
AD28
V
AF26
V
AF28
V
AF30
V
AF31
VCCCORE
AH26
VCCCORE
AH28
VCCCORE
AH30
VCCCORE
AH31
VCCCORE
AJ30
VCCCORE
AJ31
VCCCORE
AK24
VCCIO
BJ24
VCCAPLLEXP
AN20
VCCIO
AN22
VCCIO
AN23
VCCIO
AN24
VCCIO
AN26
VCCIO
AN28
VCCIO
BJ26
VCCIO
BJ28
VCCIO
AT26
VCCIO
AT28
VCCIO
AU26
VCCIO
AU28
VCCIO
AV26
VCCIO
AV28
VCCIO
AW26
VCCIO
AW28
VCCIO
BA26
VCCIO
BA28
VCCIO
BB26
VCCIO
BB28
VCCIO
BC26
VCCIO
BC28
VCCIO
BD26
VCCIO
BD28
VCCIO
BE26
VCCIO
BE28
VCCIO
BG26
VCCIO
BG28
VCCIO
BH27
VCCIO
AN30
VCCIO
AN31
VCCIO
AN35
VCC3_3
AT22
VCCVRM[1]
BJ18
VCCFDIPLL
AM23
VCCIO
IBEXPEAK-M -GP-NF
IBEXPEAK-M -GP-NF
2001G
2001G
CCCORE
CCCORE
CCCORE
CCCORE
CCCORE
CCCORE
CCCORE
CCCORE
1
.432A
3.062A
OWER
OWER
P
P
VCC CORE
VCC CORE
PCI E*
PCI E*
FDI
FDI
3
7
7
V
CCADAC
V
CCADAC
V
<1mA
59mA
357mA
85mA
SSA_DAC
V
SSA_DAC
VCCALVDS
VSSA_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCC3_3
VCC3_3
VCC3_3
VCCVRM
VCCDMI
VCCDMI
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCME3_3
VCCME3_3
VCCME3_3
VCCME3_3
CRT LVDS
CRT LVDS
HVCMOS
HVCMOS
DMI
DMI
156mA
NAND / SPI
NAND / SPI
OF 10
OF 10
2
L
L
2603
+
AE50
AE52
AF53
AF51
AH38
AH39
AP43
AP45
AT46
AT45
AB34
AB35
AD35
AT24
AT16
AU16
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
AM8
AM9
AP11
AP9
VCCA_DA C_1_2
1 2
C
C
2604
2604
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
+3VS_VC CA_LVD +3.3V_RU N
C2623
C2623
1 2
DY
DY
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1 2
C2625
C2625
1 2
+1.8VS_V CCTX_LVDS
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1 2
C2624
C2624
357mA
C2607
C2607
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
+VCC_VR M
1 2
C
C
2605
2605
DY
DY
1 2
C
C
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D 3V5MX-3GP
SC10U6D 3V5MX-3GP
1 2
C2626
C2626
SC10U6D 3V5MX-3GP
SC10U6D 3V5MX-3GP
+3.3V_RU N
2603
2603
35mA
R2601
R2601
1 2
0R0402-P AD-2-GP
1 2
C2613
C2613
SC1U10V 3KX-3GP
SC1U10V 3KX-3GP
156mA
1 2
C2615
C2615
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
85mA
PCH_VCC ME3_3
1 2
C2622
C2622
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
0R0402-P AD-2-GP
A00-0104-1
+3.3V_RU N
A00-0104-1
R2605
R2605
0R0402-P AD-2-GP
0R0402-P AD-2-GP
2603
1 2
BLM18PG 181SN1D-GP
BLM18PG 181SN1D-GP
R2609
R2609
0R0603-P AD-2-GP
0R0603-P AD-2-GP
A00-0104-1
1 2
L2604
L2604
IND-D1UH-21-G P
IND-D1UH-21-G P
SC10U6D 3V5MX-3GP
SC10U6D 3V5MX-3GP
58mA
+3.3V_RU N
1 2
<1mA
1 2
59mA
+1.05V_V TT +1.05VS _VCC_DMI
C2628
C2628
+
3.3V_CRT _LDO
+1.8V_RU N
1 2
DY
DY
69mA
R
R
2602
2602
1 2
0R0402-P AD-2-GP
0R0402-P AD-2-GP
A00-0104-1
U2601
U2601
5
OUT
GND
DY
DY
4
SHDN#
NC#4
MAX8511 EXK33-T-GP
MAX8511 EXK33-T-GP
IN
1
1
2
3
+
3.3V_RUN
+5V_RUN +3.3V_CR T_LDO
C2629
C2629
SC1U10V 3KX-3GP
SC1U10V 3KX-3GP
DY
DY
1 2
A A
5
4
3
2
1st Samsung
1st Samsung
1st Samsung
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH (POWER1)
PCH (POWER1)
PCH (POWER1)
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
26 88 Wednesd ay, January 13, 2010
26 88 Wednesd ay, January 13, 2010
26 88 Wednesd ay, January 13, 2010
1
A00
A00
A00
5
P2701
P2701
T
S
SID = PCH
S
D D
B-15
+1.05V_V TT
T
1.849A
C2705
SC10U6D 3V5KX-1GP
SC10U6D 3V5KX-1GP
SB-17
+1.05V_V TT
C C
L2702
L2702
1 2
IND-10UH-218 -GP
IND-10UH-218 -GP
SC10U6D 3V5MX-3GP
SC10U6D 3V5MX-3GP
L2703
L2703
1 2
IND-10UH-218 -GP
IND-10UH-218 -GP
SC10U6D 3V5MX-3GP
SC10U6D 3V5MX-3GP
+1.05VS_ VCCA_A_DPL
1 2
C2734
C2734
DY
DY
+1.05VS_ VCCA_B_DPL
1 2
C2735
C2735
DY
DY
SC10U6D 3V5KX-1GP
SC10U6D 3V5KX-1GP
1 2
C2711
C2711
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
1 2
C2714
C2714
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
C2705
C2704
C2704
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
68mA
69mA
+1.05V_V TT
1 2
C2718
C2718
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
B B
+3.3V_AL W
C2726
C2726
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
+1.05V_V TT
1 2
C2728
SC10U6D 3V5KX-1GP
SC10U6D 3V5KX-1GP
A A
C2728
C2723
C2723
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
163mA
1 2
<1mA
SCD1U16 V2KX-3GP
SCD1U16 V2KX-3GP
+RTC_CE LL
C2719
C2719
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
1 2
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
1 2
C2729
C2729
SCD1U16 V2KX-3GP
SCD1U16 V2KX-3GP
2mA
5
4
CCACLK
V
1
TPAD14-G P
TPAD14-G P
C
C
2707
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
1 2
1 2
C2713
C2713
+VCCSST
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2707
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
1 2
+VCC_VR M
+1.05VS_ VCCA_A_DPL
+1.05VS_ VCCA_B_DPL
1 2
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
+1.05VAL W_INT_VCCSU S
1 2
C2724
C2724
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
+3.3V_RU N
C2727
C2727
C2730
C2730
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
C2732
C2732
4
D
CPSUSBYP
1 2
C2708
C2708
DY
DY
C2710
C2710
DY
DY
+VCCRTC EXT
C2720
C2720
1 2
1 2
1 2
C2733
C2733
3
0 OF 10
0 OF 10
1
163mA
<1mA
196mA
6mA
HDA
HDA
V
V
V
V
V
V
V
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
V5REF_SUS
<1mA
VCCSATAPLL
VCCSATAPLL
VCCSUSHDA
1
CCIO
V
V
CCIO
V
CCIO
V
CCIO
CCSUS3_3
CCSUS3_3
CCSUS3_3
CCSUS3_3
CCSUS3_3
CCSUS3_3
CCSUS3_3
VCCIO
V5REF
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCIO
VCCVRM
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCME
VCCME
VCCME
VCCME
3
V24
V26
Y24
Y26
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
U23
V23
+5VALW _PCH_VCC5R EFSUS
F24
+5VS_PC H_VCC5REF
K49
J38
L38
M36
N36
P36
U35
AD13
VCCSATA PLL
AK3
AK1
AH22
AT20
AH19
AD20
AF22
AD19
AF20
AF19
AH20
AB19
AB20
AB22
AD22
AA34
Y34
Y35
AA35
6mA
L30
+3VS_+1 .5VS_HDA_IO
+3.3V_AL W
1 2
+3.3V_RU N
1 2
+VCC_VR M
1 2
C2731
C2731
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
1 2
C
C
2706
2706
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
D
D
Y
Y
1 2
2703
2703
C
C
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
C2709
C2709
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
+1.05V_V TT
C2716
C2716
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
1
TPAD14-G P
TPAD14-G P
R2707
R2707
1 2
0R0402-P AD-2-GP
0R0402-P AD-2-GP
P
P
OWER
2001J
2001J
U
U
AP51
CCACLK
V
AP53
V
CCACLK
AF23
V
CCLAN
AF24
V
CCLAN
Y20
D
CPSUSBYP
AD38
VCCME
AD39
VCCME
AD41
VCCME
AF43
VCCME
AF41
1 2
1 2
1 2
VCCME
AF42
VCCME
V39
VCCME
V41
VCCME
V42
VCCME
Y39
VCCME
Y41
VCCME
Y42
VCCME
V9
DCPRTC
AU24
VCCVRM
BB51
VCCADPLLA
BB53
VCCADPLLA
BD51
VCCADPLLB
BD53
VCCADPLLB
AH23
VCCIO
AJ35
VCCIO
AH35
VCCIO
AF34
VCCIO
AH34
VCCIO
AF32
VCCIO
V12
DCPSST
Y22
DCPSUS
P18
VCCSUS3_3
U19
VCCSUS3_3
U20
VCCSUS3_3
U22
VCCSUS3_3
V15
VCC3_3
V16
VCC3_3
Y16
VCC3_3
AT18
V_CPU_IO
AU18
V_CPU_IO
A12
VCCRTC
IBEXPEAK-M -GP-NF
IBEXPEAK-M -GP-NF
OWER
52mA
320mA
USB
USB
1.849A
68mA
Clock and Miscellaneous
Clock and Miscellaneous
69mA
PCI/GPIO/LPC
PCI/GPIO/LPC
SATA
SATA
<1mA
CPU
CPU
2mA
RTC PCI/GPIO/LPC
RTC PCI/GPIO/LPC
TP2702
TP2702
2
+3.3V_AL W
2 1
1 2
+3.3V_RU N
SB-16
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
+1.05V_V TT
A00-0104-1
2
+
1.05V_VT T
+
3.3V_ALW
D2701
D2701
CH751H-4 0PT-GP
CH751H-4 0PT-GP
1 2
R2701
R2701
100R2J-2 -GP
100R2J-2 -GP
C2712
C2712
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
1 2
C2717
C2717
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
C2725
C2725
+3.3V_AL W
1
DW
07/10 Change resistor Value
1.R2701,R2702 value corrected to 100 Ohms following PDG d oc
+5V_ALW
+3.3V_RU N
2 1
D2702
D2702
CH751H-4 0PT-GP
CH751H-4 0PT-GP
1 2
R2702
1 2
+1.05V_V TT
1 2
1st Samsung
1st Samsung
1st Samsung
Title
Title
Title
PCH (POWER2)
PCH (POWER2)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH (POWER2)
R2702
100R2J-2 -GP
100R2J-2 -GP
C2715
C2715
SC1U6D3 V2KX-GP
SC1U6D3 V2KX-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Winery13 MB DIS
Winery13 MB DIS
Winery13 MB DIS
+5V_RUN
27 88 Wednesd ay, January 13, 2010
27 88 Wednesd ay, January 13, 2010
27 88 Wednesd ay, January 13, 2010
1
A00
A00
A00