Wistron W37 Schematics
5
4
3
2
1
W37 Block Diagram
D D
200-PIN DDR SODIMM
CLK GEN
IDT CV137
ICS951419
CY28RS480
C C
10/100Mb
RJ45
30
B B
TXFM
30
PCI LAN
Reltek
RTL8100CL
100/10
PCI Bus / 33MHz
29
Mini-PCI
802.11a/b/g
31
PCMCIA
One Slot
28
A A
1394
Conn
28
PWR SW
TPS2210A
TI
PCMCIA I/F
27
TI
PCI 7411
Cardbus
1394
SD/MS/MMC
SD/MS
Card Slot
3 in 1
28
5
26,27
AMD CPU
Sempron K8
RS480M
AGTL+ CPU I/F + UMA
PCI
ATI
SB400
ACPI 2.0
ATA 133
SATA
HDD
4
4,5,6,73
HyperTransport
6.4GB/S 16b/8b
ATI
11,12,13,14
PCI-Express
x2
6xUSB 2.0
6-CH
AC97 2.2
LPC I/F
18,19,20,21,22
PIDE
25
SIDE
DVD/
CD-RW
PCI Express x16
25
MODEM
MDC Card
Thermal
& Fan
G792
DDR 333/400
ATI M26
MXM
USB x 4
24
AC97
LPC Bus / 33MHz
23
3
RJ11
CONN
KBC
KB 3910 SF
Touch
Pad
35 35
DDR x2
8,9,10
SVIDEO/COMP
LVDS
RGB CRT
15
TV OUT
LCD
CRT
16
17
16
CODEC
ALC655
32
Line In
MIC In
33
Line Out
OP AMP
30
G1421
3324
33
Int. SPKR
33
34
Int.
KB
ISA ROM
36
Debug(GF)
2
Title
Title
37
Title
BLOCK DIAGR AM
BLOCK DIAGR AM
BLOCK DIAGR AM
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
W37 SB
A3
W37 SB
A3
W37 SB
A3
Date: Sheet
Date: Sheet
Date: Sheet
04241-SA
PCB Layer Stackup
L1: Signal 1
L2: GND
L3: Inner Signal 2
L4: Inner Signal 3
L5: VCC
L6: Signal 4
Battery Charger
MAX1909ETI
INPUTS
AD+
BAT+
SYSTEM DC/DC
INPUT
DCBATOUT
SYSTEM DC/DC
INPUT
DCBATOUT 5V_S5
CPU V_CORE
INPUT
DCBATOUT
SYSTEM POWER
LP2951ACM/APL5331KAC-TR
INPUT
2D5V_S3
DCBATOUT
OUTPUTS
DCBATOUT
ISL6227
TPS 5130
OUTPUT
2D5V_S3 ,
1D8V_S5
OUTPUT
3D3V_S5
1D2V_S0
ISL6559CR
OUTPUT
VCC_CORE_S0
OUTPUT
1D25V_S3
5V_AUX_S5
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1 51Monday, March 14 , 2005
1 51Monday, March 14 , 2005
1 51Monday, March 14 , 2005
1
45,46
42,43
47
of
of
of
48
44
5
4
3
2
1
-1 ver will change
CPU(62.10055.091) U70
D D
NB(71.RS48M.B0U) U16
SB(71.SB400.D0U) U34
CLK GEN(71.00137.B0W) U15
DDR cnt.(62.10017.311) DIM2
KBC (71.03910.B0G)U35
Remove SKT1(21.H0080.001)
Hole3(34.46i15.001)
Hole4(34.46i12.001)
Hole8(34.46i14.001)
Hole25(34.4B301.001)
C C
Hole26(34.46i14.001)
GND20(34.4B312.001)
B B
?
1/27
Revise:
support @D5V_ S0 for AVDD (Pa ge 13)--CRT ri pple
ADD GND8~GND2 0--EMI
change power of MDC form 3D3 V_S0 to 3D3V_S5 --spec
issue
improve power on sequence (1. 8/S5 to 3.3/S5)
C158 -->0.01u;C156-- >1u
Add 1u at 3D3V _S0/inverter ( C809)
A A
5
4
3
2
<Variant Name>
<Variant Name>
<Variant Name>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CHANGE H ISTORY
CHANGE H ISTORY
CHANGE H ISTORY
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
W37 SB
A3
W37 SB
A3
W37 SB
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
2 51Friday, March 25, 200 5
2 51Friday, March 25, 200 5
2 51Friday, March 25, 200 5
of
of
1
of
A
3D3V_CL K_VDDA
3D3V_S0 3D3V_CL K_VDD
R131
R131
1 2
0R0603-P AD
4 4
C136
C136
1 2
SC33P50 V2JN
SC33P50 V2JN
1 2
C135
C135
1 2
SC33P50 V2JN
CLK48_C ARDBUS26
CLK48_U SB21
SMBC_SB8,21
SMBD_SB8,21
3 3
C810
C810
SC1000P 16V2KX
SC1000P 16V2KX
SC33P50 V2JN
12
0R0603-P AD
XI_CLK
X1
X1
X-14D318 MHZ-1-U1
X-14D318 MHZ-1-U1
XO_CLK
CLK14_N B13
SB_OSC_ CLK21
HTREF_C LK13
12
C811
C811
SC1000P 16V2KX
SC1000P 16V2KX
12
1 2
1 2
1 2
1 2
3D3VDD4 8_S0
12
C137
C137
SC2D2U1 6V5ZY
SC2D2U1 6V5ZY
R124
R124
DUMMY-R3
DUMMY-R3
DY
DY
R12522R2 R12522R2
R12922R2 R12922R2
R1280R2-0 R1280R2-0
R1300R2-0 R1300R2-0
1 2
1 2
1 2
12
R114
R114
49D9R2F
49D9R2F
USB_48M
SMBC_CL K
SMBD_CL K
R11633R2 R11633R2
R12233R2 R12233R2
R118
R118
33R2
33R2
IREF_CLKG EN
12
FS2
FS1
FS0
CLK_HTT 66
R102
R102
475R2F
475R2F
3
39
32
21
14
35
56
51
43
48
1
2
4
7
8
10
11
9
53
54
52
47
50
37
6
B
U15
U15
VDD_48
VDDA
VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC
VDD_REF
VDD_PC1
VDD_CPU
VDD_HTT
XIN
XOUT
USB_48
SCL
SDA
CLKREQ0#
CLKREQ1#
SEL24/24_48#
REF1
REF0
REF2
HTT66
PCI0
IREF
NC#6
IDTCV137P AG
IDTCV137P AG
SRCC0
SRCT0
SRCC3
SRCT3
SRCC4
SRCT4
SRCC5
SRCT5
SRCC6
SRCT6
SRCC7
SRCT7
CPUC1
CPUT1
CPUC0
CPUT0
SRCC1
SRCT1
SRCC2
SRCT2
VSS_SRC
VSS_SRC
RESET#
TURBO1
VSS_CPU
VSS_PCI
VSS_HTT
VSS_SRC
VSSA
VSS_48
VSS_REF
Pin 9 CY28RS480 is NC
33
34
25
24
23
22
19
18
17
16
13
12
40
41
44
45
29
30
28
27
36
20
15
26
42
49
46
31
38
5
55
SRC_CLK 0#
SRC_CLK 0
SRC_CLK 3#
SRC_CLK 3
CPUCLKJ _CY
CPUCLK_ CY
ATI_CLK0#
ATI_CLK0
12
DY
DY
R106
R106
0R2-0
0R2-0
RN9
RN9
1 2
1 2
RN8
RN8
2 3
1
2 3
1
RN10
RN10
SRN33-2-U 2
SRN33-2-U 2
1 2
DY
DY
for ICS951419
CY28RS480
IDTCV137PAG
C
SRN33-2-U 2
SRN33-2-U 2
RN7
RN7
2 3
1
4
1
4
2 3
SRN33-2-U 2
SRN33-2-U 2
R119 1 5R2JR119 1 5R2J
R117 1 5R2JR117 1 5R2J
SRN33-2-U 2
SRN33-2-U 2
4
4
3D3V_CL K_VDD
R105 1 0KR2
R105 1 0KR2
NBSRC_C LK# 13
NBSRC_C LK 13
CLK_PCIE_ PEG 15
CLK_PCIE_ PEG# 15
for IDTCV137PAG testing
SBLINK_CL K# 13
SBLINK_CL K 13
SBSRC_C LK# 18
SBSRC_C LK 18
CPUCLK# 6
CPUCLK 6
Do not populate
when using UMA
Do not populate
when using UMA
3D3V_S0
L7
L7
1 2
BLM11A6 01S
BLM11A6 01S
D
12
12
CLK_PCIE_ PEG#
CLK_PCIE_ PEG
SBLINK_CL K#
SBLINK_CL K
SBSRC_C LK#
SBSRC_C LK
NBSRC_C LK#
NBSRC_C LK
C121
C121
SCD1U16 V
SCD1U16 V
C133
C133
SCD1U16 V
SCD1U16 V
12
12
C123
C123
SCD1U16 V
SCD1U16 V
C124
C124
SCD1U16 V
SCD1U16 V
DY
DY
1 2
1 2
DY
DY
1 2
1 2
1 2
1 2
1 2
1 2
12
12
R108 49D9R2F
R108 49D9R2F
R109 49D9R2F
R109 49D9R2F
R104 49D9R2FR104 49D9R2F
R103 49D9R2FR103 49D9R2F
R110 49D9R2FR110 49D9R2F
R107 49D9R2FR107 49D9R2F
R101 49D9R2FR101 49D9R2F
R100 49D9R2FR100 49D9R2F
C122
C122
SCD1U16 V
SCD1U16 V
C138
C138
SCD1U16 V
SCD1U16 V
12
12
C134
C134
SCD1U16 V
SCD1U16 V
C132
C132
SCD1U16 V
SCD1U16 V
E
3D3V_CL K_VDD
12
C146
C146
SC22U10 V6ZY-U
SC22U10 V6ZY-U
2 2
3D3V_S03D3V_CL K_VDDA
L5
L5
1 2
12
C120
C120
SCD1U16 V
SCD1U16 V
3D3V_CL K_VDD
DY
DY
R121 2 K2R2
DY
DY
R121 2 K2R2
R123
R123
DUMMY-R2
DUMMY-R2
R120 2 K2R2
R120 2 K2R2
R115
R115
DUMMY-R2
DUMMY-R2
R127 2K2R2
R127 2K2R2
R126
R126
DUMMY-R2
DUMMY-R2
A
1 2
1 2
DY
DY
DY
DY
1 2
1 2
DY
1 1
DY
1 2
1 2
DY
DY
FS0
FS1
FS2
for ICS951419
FS2
0
0
0
0
1
1
1
FS1 FS0 CPU HTT PCI
0
0
1
1
0
0
1
0
1
0
1
0
1
1
B
MHz MHz MHz
Hi-Z Hi-Z Hi-Z
X X/3 X/6
180.00 60.00 30.00
220.00 36.56 73.12
100.00 66.66 33.33
133.33
200.00
66.66
66.66
33.33
33.33
C
D
12
BLM11A6 01S
BLM11A6 01S
C111
C111
SC22U10 V6ZY-U
SC22U10 V6ZY-U
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
CLKGEN_ICS951412
CLKGEN_ICS951412
CLKGEN_ICS951412
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
3 51Friday, April 15, 2005
3 51Friday, April 15, 2005
3 51Friday, April 15, 2005
of
of
E
of
SB
SB
SB
A
1D2V_HT 0A_S0
B
C
D
E
12
C49
C49
SCD22U1 6V3ZY
SCD22U1 6V3ZY
4 4
3 3
12
C47
C47
SCD22U1 6V3ZY
SCD22U1 6V3ZY
NB0CADO UT[15..0]11
NB0CADO UTJ[15..0]11
Used SideB Power Plane
2 2
1D2V_HT 0A_S0
12
C50
C50
SCD22U1 6V3ZY
SCD22U1 6V3ZY
DY
DY
HTT for CPU sideA
Transmit power
and NB sideA Receive
power
NB0HTTC LKOUT111
NB0HTTC LKOUTJ111
NB0HTTC LKOUT011
NB0HTTC LKOUTJ011
1 2
1 2
NB0HTTC TLOUT11
NB0HTTC TLOUTJ11
R4849D9R3F R4849D9R3F
12
C48
C48
SCD22U1 6V3ZY
SCD22U1 6V3ZY
1D2V_HT 0A_S0
NB0CADO UT15
NB0CADO UTJ15
NB0CADO UT14
NB0CADO UTJ14
NB0CADO UT13
NB0CADO UTJ13
NB0CADO UT12
NB0CADO UTJ12
NB0CADO UT11
NB0CADO UTJ11
NB0CADO UT10
NB0CADO UTJ10
NB0CADO UT9
NB0CADO UTJ9
NB0CADO UT8
NB0CADO UTJ8
NB0CADO UT7
NB0CADO UTJ7
NB0CADO UT6
NB0CADO UTJ6
NB0CADO UT5
NB0CADO UTJ5
NB0CADO UT4
NB0CADO UTJ4
NB0CADO UT3
NB0CADO UTJ3
NB0CADO UT2
NB0CADO UTJ2
NB0CADO UT1
NB0CADO UTJ1
NB0CADO UT0
NB0CADO UTJ0
NB0HTTC LKOUT1
NB0HTTC LKOUTJ1
NB0HTTC LKOUT0
NB0HTTC LKOUTJ0
CPUHTTC TLIN1
R4949D9R3F R4949D9R3F
CPUHTTC TLINJ1
NB0HTTC TLOUT
NB0HTTC TLOUTJ
12
12
EC13
EC13
SCD1U
SCD1U
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
W25
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
T27
T28
V29
U29
V27
V28
Y29
Y25
Y27
Y28
R27
R26
T29
R29
12
EC30
EC30
EC21
EC21
SCD1U
SCD1U
SCD1U
SCD1U
VLDT CONNECTED INNER OF CPU
NORMALLY,HTT POWER CONNECT TO ONE
SIDE, NO NEET TO CONNECT BOTH OF
THEM
U70A
U70A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
AH29
AH27
AG28
AG26
AF29
AE28
AF25
N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29
J26
J27
J29
K29
N25
P25
P28
P27
1D2V_HT 0A_S0
CPUCADO UT15
CPUCADO UTJ15
CPUCADO UT14
CPUCADO UTJ14
CPUCADO UT13
CPUCADO UTJ13
CPUCADO UT12
CPUCADO UTJ12
CPUCADO UT11
CPUCADO UTJ11
CPUCADO UT10
CPUCADO UTJ10
CPUCADO UT9
CPUCADO UTJ9
CPUCADO UT8
CPUCADO UTJ8
CPUCADO UT7
CPUCADO UTJ7
CPUCADO UT6
CPUCADO UTJ6
CPUCADO UT5
CPUCADO UTJ5
CPUCADO UT4
CPUCADO UTJ4
CPUCADO UT3
CPUCADO UTJ3
CPUCADO UT2
CPUCADO UTJ2
CPUCADO UT1
CPUCADO UTJ1
CPUCADO UT0
CPUCADO UTJ0
CPUHTTC LKOUT1
CPUHTTC LKOUTJ1
CPUHTTC LKOUT0
CPUHTTC LKOUTJ0
CPUHTTC TLOUT0
CPUHTTC TLOUTJ0
HTT for CPU sideB
Receive power
and NB sideA
Transmit power
12
C85
C85
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
Used SideA Power Plane
CPUHTTC LKOUT1 11
CPUHTTC LKOUTJ1 11
CPUHTTC LKOUT0 11
CPUHTTC LKOUTJ0 11
CPUHTTC TLOUT0 11
CPUHTTC TLOUTJ0 11
LAYOUT: Place bypass cap on topside of board near
HTT power pins that are not connected directly to
downstream HTT device, but connected internally to
other HTT power pins.
CPUCADO UT[15..0] 11
CPUCADO UTJ[15..0] 11
62.10030 .041
62.10030 .041
BGA754-S KT-U
By ME requset U11 P/N:
1 1
Main 62.10030.041
Second 62.10053.221
Third 62.10053.201
A
B
C
BGA754-S KT-U
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
D
Date: Sheet
CPU(1/4)_HyperTransport I/F
CPU(1/4)_HyperTransport I/F
CPU(1/4)_HyperTransport I/F
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
SB
SB
4 51Friday, March 25, 200 5
4 51Friday, March 25, 200 5
4 51Friday, March 25, 200 5
of
of
E
of
SB
A
4 4
VREF_DDR_MEM
NOTE: Test with passive probes only.
2D5V_S3
3 3
NOTE: Install to bypass op-amp
R490
R490
100R3F
100R3F
R491
R491
100R3F
100R3F
12
C553
C553
SCD1U
SCD1U
12
12
12
VREF_DD R_MEM
C526
C526
SCD1U
SCD1U
12
C544
C544
SC1000P 50V2KX
SC1000P 50V2KX
NOTE: Remove to bypass op-amp
2 2
VREF_DDR_CLAW
2D5V_S3
12
12
1 1
12
R86
R86
100R3
100R3
R87
R87
100R3
100R3
C105
C105
SCD1U
SCD1U
12
C106
C106
SCD1U
SCD1U
VREF_DD R_CLAW
A
12
C107
C107
SC1000P 50V2KX
SC1000P 50V2KX
2D5V_S3
M_DATA[6 3..0]9
M_DQS[7..0 ]9
B
B
M_ADM[7..0 ]9
TP28
TP28
TPAD30
TPAD30
VREF_DD R_CLAW
1 2
1 2
R37 34D 8R2FR37 34D8R2F
R36 34D 8R2FR36 34D8R2F
DDRVTT_ SENSE
MEMZN
MEMZP
M_DATA6 3
M_DATA6 2
M_DATA6 1
M_DATA6 0
M_DATA5 9
M_DATA5 8
M_DATA5 7
M_DATA5 6
M_DATA5 5
M_DATA5 4
M_DATA5 3
M_DATA5 2
M_DATA5 1
M_DATA5 0
M_DATA4 9
M_DATA4 8
M_DATA4 7
M_DATA4 6
M_DATA4 5
M_DATA4 4
M_DATA4 3
M_DATA4 2
M_DATA4 1
M_DATA4 0
M_DATA3 9
M_DATA3 8
M_DATA3 7
M_DATA3 6
M_DATA3 5
M_DATA3 4
M_DATA3 3
M_DATA3 2
M_DATA3 1
M_DATA3 0
M_DATA2 9
M_DATA2 8
M_DATA2 7
M_DATA2 6
M_DATA2 5
M_DATA2 4
M_DATA2 3
M_DATA2 2
M_DATA2 1
M_DATA2 0
M_DATA1 9
M_DATA1 8
M_DATA1 7
M_DATA1 6
M_DATA1 5
M_DATA1 4
M_DATA1 3
M_DATA1 2
M_DATA1 1
M_DATA1 0
M_DATA9
M_DATA8
M_DATA7
M_DATA6
M_DATA5
M_DATA4
M_DATA3
M_DATA2
M_DATA1
M_DATA0
M_ADM8
M_ADM7
M_ADM6
M_ADM5
M_ADM4
M_ADM3
M_ADM2
M_ADM1
M_ADM0
M_DQS8
M_DQS7
M_DQS6
M_DQS5
M_DQS4
M_DQS3
M_DQS2
M_DQS1
M_DQS0
AE13
AG12
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
A13
AA1
AG1
AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
U70B
U70B
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
C
1D25V_S 3
D17
VTT_A
A18
VTT_A
B17
VTT_A
C17
VTT_A
AF16
VTT_B
AG16
VTT_B
AH16
VTT_B
AJ17
VTT_B
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
NC_E13
NC_C12
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
NC_E14
NC_D12
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
C
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
BGA754-S KT-U
BGA754-S KT-U
MEMRESE T#
M_CKE#0
M_CKE#1
M_CLK7
M_CLK#7
M_CLK6
M_CLK#6
M_CLK5
M_CLK#5
M_CLK4
M_CLK#4
M_CLK1
M_CLK#1
M_CLK0
M_CLK#0
M_CS#7
M_CS#6
M_CS#5
M_CS#4
M_CS#3
M_CS#2
M_CS#1
M_CS#0
M_ARAS#
M_ACAS#
M_AW E#
M_ABS#1
M_ABS#0
RSVD_M_ AA15
RSVD_M_ AA14
M_AA13
M_AA12
M_AA11
M_AA10
M_AA9
M_AA8
M_AA7
M_AA6
M_AA5
M_AA4
M_AA3
M_AA2
M_AA1
M_AA0
M_BRAS#
M_BCAS#
M_BW E#
M_BBS#1
M_BBS#0
RSVD_M_ BA15
RSVD_M_ BA14
M_BA13
M_BA12
M_BA11
M_BA10
M_BA9
M_BA8
M_BA7
M_BA6
M_BA5
M_BA4
M_BA3
M_BA2
M_BA1
M_BA0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
D
12
For REGISTED DIMM Only
UNBUFFER DIMM NC
12
C102
C102
SCD1U
SCD1U
D
C53
C53
SC1000P 50V2KX
SC1000P 50V2KX
M_CKE#0 8,9
M_CKE#1 8,9
M_CLK7 8,9
M_CLK#7 8,9
M_CLK6 8,9
M_CLK#6 8,9
M_CLK5 8,9
M_CLK#5 8,9
M_CLK4 8,9
M_CLK#4 8,9
M_CLK#1
M_CLK#0
M_CLK1
M_CLK0
M_CS#3 8,9
M_CS#2 8,9
M_CS#1 8,9
M_CS#0 8,9
M_ARAS# 8,9
M_ACAS# 8,9
M_AW E# 8,9
M_ABS#1 8,9
M_ABS#0 8,9
M_AA[13..0 ] 8,9
AMD suggested M_AA13
connect to DIMM pin123
M_BRAS# 8,9
M_BCAS# 8,9
M_BW E# 8,9
M_BBS#1 8,9
M_BBS#0 8,9
M_BA[13..0 ] 8,9
AMD suggested M_BA13
connect to DIMM pin123
TP68 T PAD30TP68 TPAD 30
TP64 T PAD30TP64 TPAD 30
TP65 T PAD30TP65 TPAD 30
TP61 T PAD30TP61 TPAD 30
TP67 T PAD30TP67 TPAD 30
TP63 T PAD30TP63 TPAD 30
TP60 T PAD30TP60 TPAD 30
TP66 T PAD30TP66 TPAD 30
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
E
2D5V_S3
RN3
RN3
SRN10K-2
SRN10K-2
1
2
3
45
MEMZN
MEMZP
M_DQS8
M_ADM8
MEMRESE T#
M_CS#7
M_CS#6
M_CS#5
M_CS#4
RSVD_M_ AA15
RSVD_M_ AA14
RSVD_M_ BA15
RSVD_M_ BA14
8
7
6
NOT SUPPORT ECC CHECK
AMD suggested remove
PULL-HI resistor.
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU(2/4)_DDR
CPU(2/4)_DDR
CPU(2/4)_DDR
W37
W37
W37
5 51Friday, March 25, 200 5
5 51Friday, March 25, 200 5
5 51Friday, March 25, 200 5
E
TP2 TPA D30TP2 TPAD30
TP1 TPA D30TP1 TPAD30
TP62 T PAD30TP62 TPAD 30
TP69 T PAD30TP69 TPAD 30
TP31 T PAD30TP31 TPAD 30
TP10 T PAD30TP10 TPAD 30
TP12 T PAD30TP12 TPAD 30
TP9 TPA D30TP9 TPAD30
TP11 T PAD30TP11 TPAD 30
TP5 TPA D30TP5 TPAD30
TP7 TPA D30TP7 TPAD30
TP6 TPA D30TP6 TPAD30
TP8 TPA D30TP8 TPAD30
of
of
of
SB
SB
SB
A
B
C
2D5V_CP UA_S0
D
E
U11
U11
1
SHDN#
2
GND
3
IN
G913C-U
G913C-U
COREFB42
COREFB#42
C98
C98
SC3900P 50V3KX
SC3900P 50V3KX
C99
C99
SC3900P 50V3KX
SC3900P 50V3KX
1 2
1 2
RN4
RN4
SRN680-U
SRN680-U
DY
DY
Iomax=120mA
DY
DY
SET
OUT
L0_REF1
L0_REF0
COREFB
COREFB#
CORE_SE NSE
VDDIOFB
VDDIOFBJ
VDDIOSENS E
CLKIN
12
R64
R64
169R3F
169R3F
CLKIN#
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
R34
R34
680R3
680R3
R35
R35
680R3
680R3
NC_AE23
NC_AF23
NC_AF22
NC_AF21
678
123
4 5
TP25 T PAD30TP25 TPAD 30
TP18 T PAD30TP18 TPAD 30
TP22 T PAD30TP22 TPAD 30
TP3 TPA D30TP3 TPAD30
TP30 T PAD30TP30 TPAD 30
TP29 T PAD30TP29 TPAD 30
TP32 T PAD30TP32 TPAD 30
TP17 T PAD30TP17 TPAD 30
TP19 T PAD30TP19 TPAD 30
C
5
4
NC_C18
NC_A19
2D5V_S0
3D3V_S0
12
LDT_RST #13,18
SB_CPUP WRGD18
LDT_STP #13,18
1 2
1 2
C91
C91
SC1U10V 3KX
SC1U10V 3KX
1D25V_S 3
2D5V_S0
LDT_RST #
CLKIN
CLKIN#
CORE_SE NSE
VDDIOFB
VDDIOFBJ
VDDIOSENS E
NC_AE24
NC_AF24
2D5V_VDDA_S0
2D5V_S0
4 4
2D5V_CP UA_S0
1 2
12
C97
C97
SC10U10 V5ZY
SC10U10 V5ZY
R77
R77
0R3-U
0R3-U
R76
R76
1 2
0R3-U
0R3-U
DY
DY
2D5V_CP UR_S0
1 2
12
TC4
TC4
ST100U4 VBM-1
ST100U4 VBM-1
AMD SUGGEST TO USE 2D5V_CPUA_S0
KEMET,NT:5.7, B2 size
ST100U4VBM-1 (80.10716.321)
3 3
Iripple=1.1A,ESR=70mohm
SANYO, NT$:6.1
Iripple=1.1A,ESR=70mohm
3.5/2.8/2.0
77.21071.031
HDT Connectors
2D5V_S0
2 2
1 1
12
DBREQJ
DBRDY
TCK
TMS
TDI
TRST_L
TDO
R462 680R3
2D5V_S3
R462 680R3
CHANGE FROM 1KR3 TO 680R2 FOR AMD
CHECK LIST
NC_D18
NC_AJ18
NC_AG17
NC_B19
NC_C21
NC_D20
NC_C19
DY
DY
C435
C435
SCD1U
SCD1U
RN25 SRN680-U
RN25 SRN680-U
DY
DY
123
1 2
RN5
RN5
1
2
3
4 5
1
2
3
4 5
RN2
RN2
SRN680-U
SRN680-U
DY
DY
A
678
4 5
SRN680-U
SRN680-U
8
7
6
8
7
6
AMD SUGGEST TO USE 100 ~ 300UH
Change
L270H
L4
2D5V_VD DA_S0
0R5JL40R5J
DY
DY
12
R84
R84
680R3
680R3
LAYOUT: Route trace 50 mils wide and
500 to 750 mils long between these
caps.
12
C93
C93
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
DY
DY
12
R83
R83
680R3
680R3
1D2V_HT 0A_S0
1 2
1 2
AMD suggest voltege
from 2D5V_S0 to 2D5V_S3
R62 44D 2R3FR62 44D2R3F
R63 44D 2R3FR63 44D2R3F
differentially impedance 100
LDT_RST #
SB_CPUP WRGD
LDT_STP #
Add HDT connector for
AMD suggested
2D5V_S0
DY
DY
12
C26
C26
SCD1U
SCD1U
CN2
CN2
DY
DY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
SMC-CONN 26A-FP
SMC-CONN 26A-FP
20.F0357 .025
20.F0357 .025
NC_C15
NC_AE23
NC_AF23
NC_AF22
NC_AF21
LAYOUT: Route VDDA trace approx.
50 mils wide (use 2x25 mil traces to
exit ball field) and 500 mils long.
1 2
1 2
1 2
1 2
1 2
12
C96
C96
SCD22U1 6V3ZY
SCD22U1 6V3ZY
12
C84
C84
SC1000P 50V2KX
SC1000P 50V2KX
CPUCLK3
CPUCLK#3
R79 820 R3R79 820R3
R78 820 R3R78 820R3
R81 680 R3R81 680R3
R85 680 R3R85 680R3
R61 680 R3R61 680R3
12
SC3300P 50V2KX
SC3300P 50V2KX
12
2D5V_S3
C95
C95
C83
C83
SC1000P 50V2KX
SC1000P 50V2KX
Validation Test Points
LAYOUT: Place close to the CPU.
TP4 TPA D30TP4 TPAD30
TP20 T PAD30TP20 TPAD 30
TP21 T PAD30TP21 TPAD 30
TP23 T PAD30TP23 TPAD 30
TP24 T PAD30TP24 TPAD 30
B
12
SC22P50 V2JN-1
SC22P50 V2JN-1
2D5V_VD DA_VREF
12
C94
C94
SC1U10V 3KX
SC1U10V 3KX
U70C
U70C
AH25
AJ25
AF20
AE18
AJ27
AF27
AE26
A23
A24
B23
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
C16
AG15
AH17
C15
E20
E17
B21
A21
C18
A19
A28
AJ28
AE23
AF23
AF22
AF21
C1
J3
R3
AA2
D3
AG2
B18
AH1
AE21
C20
AG4
C6
AG6
AE9
AG9
BGA754-S KT-U
BGA754-S KT-U
C92
C92
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A
VTT_B
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
NC_C1
NC_J3
NC_R3
NC_AA2
NC_D3
NC_AG2
NC_B18
NC_AH1
NC_AE21
NC_C20
NC_AG4
NC_C6
NC_AG6
NC_AE9
NC_AG9
12
R74
R74
R1
20KR3F
20KR3F
DY
DY
12
R75
R75
20KR3F
20KR3F
DY
DY
Vout = 1.25*(1+ R1/R2)
R2
THERMTR IP#
THERMDA
THERMDC
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
A20
A26
A27
AG13
AF14
AG14
AF15
AE15
AG18
AH18
AG17
AJ18
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
THERMTRIP_L
THERMDP 23
THERMDN 23
TP27 T PAD30TP27 TPAD 30
TP26 T PAD30TP26 TPAD 30
VID[4..0] 42
LAYOUT: Route FBCLKOUT_H/L
differentially impedance 80
12
R80
R80
80D6R3F -U
80D6R3F -U
R82
R82
DY
DY
1 2
DUMMY-R3
DUMMY-R3
2D5V_S3
SB
2D5V_S0
12
R33
R33
680R3
680R3
THERMTR IP#
THERMTRIP#Level shift to SB400
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
CPU(3/4)_Control & Debug
CPU(3/4)_Control & Debug
CPU(3/4)_Control & Debug
2
3
Q5
Q5
MMBT390 4-U1
MMBT390 4-U1
1
W37
W37
W37
NS3
1 2
R32
R32
1KR3
1KR3
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
E
CPU_THE RMTRIP# 21,23
2D5V_S0
6 51Friday, March 25, 200 5
6 51Friday, March 25, 200 5
6 51Friday, March 25, 200 5
of
of
of
SB
SB
SB
FBCLKOUT_H
FBCLKOUT_L
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
NC_AF18
NC_D22
NC_C22
NC_B13
NC_B7
NC_C3
NC_K1
NC_R2
NC_AA3
NC_F3
NC_C23
NC_AG7
NC_AE22
NC_C24
NC_A25
NC_C9
FBCLKOU T
AH19
AJ19
FBCLKOU TJ
DBREQJ
AE19
NC_D20
D20
NC_C21
C21
NC_D18
D18
NC_C19
C19
NC_B19
B19
TDO
A22
AF18
Connect to VDDIO for AMD suggest.
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
D
A
N20
Y17
VSS
K17
VSS
H17
VSS
F17
VSS
U70E
U70E
E18
VSS
AJ26
VSS
AE29
VSS
AC16
VSS
AA16
VSS
J16
VSS
G16
VSS
E16
VSS
AH14
4 4
3 3
2 2
1 1
AD15
AB15
K15
E15
D16
AE14
AC14
AA14
G14
AF17
AD13
AB13
Y13
K13
H13
F13
AH12
AC12
AA12
G12
B12
AD11
AB11
Y11
K11
H11
F11
AH10
AC10
W10
U10
R10
N10
G10
B10
AD9
AH8
AC8
AD7
AB7
AH6
AC6
AA6
AH4
AH2
AD2
AB2
C29
AH28
AF28
AC28
W28
R28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L10
VSS
J10
VSS
VSS
VSS
VSS
Y9
VSS
V9
VSS
T9
VSS
P9
VSS
M9
VSS
K9
VSS
H9
VSS
F9
VSS
VSS
VSS
W8
VSS
U8
VSS
R8
VSS
N8
VSS
L8
VSS
J8
VSS
G8
VSS
B8
VSS
VSS
VSS
V7
VSS
T7
VSS
P7
VSS
M7
VSS
K7
VSS
H7
VSS
F7
VSS
VSS
VSS
VSS
U6
VSS
R6
VSS
N6
VSS
L6
VSS
J6
VSS
G6
VSS
B6
VSS
VSS
B4
VSS
VSS
VSS
VSS
Y2
VSS
V2
VSS
T2
VSS
P2
VSS
M2
VSS
K2
VSS
H2
VSS
F2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L20
J20
AF19
AD19
AB19
Y19
K19
H19
F19
D19
AC18
AA18
G18
B16
AD17
AB17
H15
F15
G28
D28
B28
C27
AH26
AF26
AD26
Y26
T26
M26
H26
D26
B26
C25
B25
AJ24
AG24
AC24
AA24
W24
U24
R24
N24
J24
G24
E24
AG23
AD23
AB23
Y23
V23
T23
P23
K23
H23
F23
D23
AJ22
AH22
AG22
AC22
AA22
AG29
U22
R22
N22
L22
J22
G22
E22
B22
AG21
AD21
Y21
V21
T21
P21
M21
K21
H21
F21
D21
AJ20
AG20
AE20
AC20
AA20
W20
U20
R20
G20
J18
AE16
Y15
B14
J12
AA10
AB9
AA8
Y7
W6
AF2
D2
AG27
AG25
L24
M23
W22
AB21
AH20
B2
VCC_COR E_S0 2D5V_S3
L7
VDD
AC15
VDD
H18
VDD
B20
VDD
E21
VDD
U70D
U70D
H22
VDD
J23
VDD
H24
VDD
F26
VDD
N7
VDD
L9
VDD
V10
VDD
G13
VDD
K14
VDD
Y14
VDD
AB14
VDD
G15
VDD
J15
VDD
AA15
VDD
H16
VDD
K16
VDD
Y16
VDD
AB16
VDD
G17
VDD
J17
VDD
AA17
VDD
AC17
VDD
AE17
VDD
F18
VDD
K18
VDD
Y18
VDD
AB18
VDD
AD18
VDD
AG19
VDD
E19
VDD
G19
VDD
AC19
VDD
AA19
VDD
J19
VDD
F20
VDD
H20
VDD
K20
VDD
M20
VDD
P20
VDD
T20
VDD
V20
VDD
Y20
VDD
AB20
VDD
AD20
VDD
G21
VDD
J21
VDD
L21
VDD
N21
VDD
R21
VDD
U21
VDD
W21
VDD
AA21
VDD
AC21
VDD
F22
VDD
K22
VDD
M22
VDD
P22
VDD
T22
VDD
V22
VDD
Y22
VDD
AB22
VDD
AD22
VDD
E23
VDD
G23
VDD
L23
VDD
N23
VDD
R23
VDD
U23
VDD
W23
VDD
AA23
VDD
AC23
VDD
B24
VDD
D24
VDD
F24
VDD
K24
VDD
M24
VDD
P24
VDD
T24
VDD
V24
VDD
Y24
VDD
AB24
VDD
AD24
VDD
AH24
VDD
AE25
VDD
K26
VDD
P26
VDD
V26
VDD
BGA754-S KT-U
BGA754-S KT-U
A
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
B
BGA754-S KT-U
BGA754-S KT-U
VCC_COR E_S0
B
C
LAYOUT: Place in uPGA socket cavity.
VCC_COR E_S0
12
SCD22U1 6V3ZY
SCD22U1 6V3ZY
12
C60
C60
SCD22U1 6V3ZY
SCD22U1 6V3ZY
0.22u x 6
12
C467
C467
C485
C485
SCD22U1 6V3ZY
SCD22U1 6V3ZY
12
C69
C69
SC10U10 V5ZY
SC10U10 V5ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
12
C486
C486
SC10U10 V5ZY
SC10U10 V5ZY
10u x 4
12
C61
C61
SC10U10 V5ZY
SC10U10 V5ZY
LAYOUT: Place on backside of processor.
VCC_COR E_S0
12
C73
C73
1 2
SC10U10 V5ZY
SC10U10 V5ZY
10u x 2
12
C75
C75
SCD22U1 6V3ZY
SCD22U1 6V3ZY
C
12
C70
C70
12
DY
DY
C86
C86
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
C469
C469
SC10U10 V5ZY
SC10U10 V5ZY
SC10U10 V5ZY
SC10U10 V5ZY
10u x 1 4.7u x 6
1D25V_S 3
12
12
C101
C101
C103
C103
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
4.7u x 2
DY
DY
C72
C72
C484
C484
1 2
1 2
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
0.22u x 4
2D5V_S3 2D5V_S3
12
12
C104
C104
C40
C40
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
1D25V_S 3
12
C52
C52
SCD22U1 6V3ZY
12
C74
C74
SCD22U1 6V3ZY
SCD22U1 6V3ZY
12
C51
C51
SCD22U1 6V3ZY
SCD22U1 6V3ZY
12
C54
C54
0.22u x 2
12
C482
C482
12
DY
DY
C42
C42
12
C465
C465
SCD22U1 6V3ZY
SCD22U1 6V3ZY
SC10U10 V5ZY
SC10U10 V5ZY
12
C41
C41
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
D
12
C813
C813
SCD22U1 6V3ZY
SCD22U1 6V3ZY
12
C62
C62
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
D
12
C814
C814
SCD22U1 6V3ZY
SCD22U1 6V3ZY
12
C63
C63
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
E
12
C815
C815
12
12
DY
DY
C64
C64
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
12
DY
DY
C55
C55
CPU(4/4)_Power
CPU(4/4)_Power
CPU(4/4)_Power
C76
C76
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
W37
W37
W37
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
7 51Friday, March 25, 200 5
7 51Friday, March 25, 200 5
7 51Friday, March 25, 200 5
of
of
E
of
SB
SB
SB
A
M_AA0
M_AA1
M_AA2
M_AA3
M_AA4
M_AA5
M_AA6
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11
TP70TPAD30 TP70TPAD30
TP13TPAD30 TP13TPAD30
TP58TPAD30 TP58TPAD30
M_AA12
M_ABS#0
M_ABS#1
M_DATA_ R_0
M_DATA_ R_1
M_DATA_ R_2
M_DATA_ R_3
M_DATA_ R_4
M_DATA_ R_5
M_DATA_ R_6
M_DATA_ R_7
M_DATA_ R_8
M_DATA_ R_9
M_DATA_ R_10
M_DATA_ R_11
M_DATA_ R_12
M_DATA_ R_13
M_DATA_ R_14
M_DATA_ R_15
M_DATA_ R_16
M_DATA_ R_17
M_DATA_ R_18
M_DATA_ R_19
M_DATA_ R_20
M_DATA_ R_21
M_DATA_ R_22
M_DATA_ R_23
M_DATA_ R_24
M_DATA_ R_25
M_DATA_ R_26
M_DATA_ R_27
M_DATA_ R_28
M_DATA_ R_29
M_DATA_ R_30
M_DATA_ R_31
M_DATA_ R_32
M_DATA_ R_33
M_DATA_ R_34
M_DATA_ R_35
M_DATA_ R_36
M_DATA_ R_37
M_DATA_ R_38
M_DATA_ R_39
M_DATA_ R_40
M_DATA_ R_41
M_DATA_ R_42
M_DATA_ R_43
M_DATA_ R_44
M_DATA_ R_45
M_DATA_ R_46
M_DATA_ R_47
M_DATA_ R_48
M_DATA_ R_49
M_DATA_ R_50
M_DATA_ R_51
M_DATA_ R_52
M_DATA_ R_53
M_DATA_ R_54
M_DATA_ R_55
M_DATA_ R_56
M_DATA_ R_57
M_DATA_ R_58
M_DATA_ R_59
M_DATA_ R_60
M_DATA_ R_61
M_DATA_ R_62
M_DATA_ R_63
12
A
DM1_RES ET#
DM1_A13
DM1_BA2
3D3V_S0
C527
C527
SCD1U
SCD1U
4 4
3 3
2 2
1 1
M_ARAS#5,9
M_ACAS#5,9
M_AW E#5,9
VREF_DD R_MEM VREF_DD R_MEM
Layout trace 20 mil Layout trace 20 mil
DIM1
DIM1
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127
DQ32
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC#85
86
NC#86/(RESET#)
97
NC#97/A13
98
NC#98/BA2
123
NC#123
124
NC#124
200
NC#200
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
201
GND
SKT-SODIMM2 00-25
SKT-SODIMM2 00-25
NORMAL TYPE
/CS0
/CS1
CKE0
CKE1
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
CK0
/CK0
CK1
/CK1
CK2
/CK2
SCL
SDA
SA0
SA1
SA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
B
TP15TPAD30 TP15TPAD30
TP59TPAD30 TP59TPAD30
TP14TPAD30 TP14TPAD30
M_BA0
M_BA1
M_BA2
M_BA3
M_BA4
M_BA5
M_BA6
M_BA7
M_BA8
M_BA9
M_BA10
M_BA11
M_BA12
M_BBS#0
M_BBS#1
M_DATA_ R_0
M_DATA_ R_1
M_DATA_ R_2
M_DATA_ R_3
M_DATA_ R_4
M_DATA_ R_5
M_DATA_ R_6
M_DATA_ R_7
M_DATA_ R_8
M_DATA_ R_9
M_DATA_ R_10
M_DATA_ R_11
M_DATA_ R_12
M_DATA_ R_13
M_DATA_ R_14
M_DATA_ R_15
M_DATA_ R_16
M_DATA_ R_17
M_DATA_ R_18
M_DATA_ R_19
M_DATA_ R_20
M_DATA_ R_21
M_DATA_ R_22
M_DATA_ R_23
M_DATA_ R_24
M_DATA_ R_25
M_DATA_ R_26
M_DATA_ R_27
M_DATA_ R_28
M_DATA_ R_29
M_DATA_ R_30
M_DATA_ R_31
M_DATA_ R_32
M_DATA_ R_33
M_DATA_ R_34
M_DATA_ R_35
M_DATA_ R_36
M_DATA_ R_37
M_DATA_ R_38
M_DATA_ R_39
M_DATA_ R_40
M_DATA_ R_41
M_DATA_ R_42
M_DATA_ R_43
M_DATA_ R_44
M_DATA_ R_45
M_DATA_ R_46
M_DATA_ R_47
M_DATA_ R_48
M_DATA_ R_49
M_DATA_ R_50
M_DATA_ R_51
M_DATA_ R_52
M_DATA_ R_53
M_DATA_ R_54
M_DATA_ R_55
M_DATA_ R_56
M_DATA_ R_57
M_DATA_ R_58
M_DATA_ R_59
M_DATA_ R_60
M_DATA_ R_61
M_DATA_ R_62
M_DATA_ R_63
DM2_RES ET#
DM2_A13
DM2_BA2
M_BA13M_AA13
M_BRAS#
M_BCAS#
M_BW E#
12
3D3V_S0
C532
C532
SCD1U
SCD1U
121
122
M_CKE#0
96
95
M_DQS_R 0
11
M_DQS_R 1
25
M_DQS_R 2
47
M_DQS_R 3
61
M_DQS_R 4
133
M_DQS_R 5 M_DQS _R5
147
M_DQS_R 6
169
M_DQS_R 7
183
77
M_ADM_R 0
12
M_ADM_R 1
26
M_ADM_R 2
48
M_ADM_R 3
62
134
M_ADM_R 5 M_ADM_R 5
148
M_ADM_R 6
170
M_ADM_R 7
184
78
35
37
160
158
DDR_CLK 0
89
DDR_CLK #0
91
SMBC_SB
195
SMBD_SB
193
194
196
198
9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
202
NOT SUPPORT ECC CHECK
AMD suggested pull-low
B
M_CS#0 5,9
M_CS#1 5,9
M_CKE#0 5,9 M_CKE#1 5,9
M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7
M_CLK5 5,9
M_CLK#5 5,9
M_CLK7 5,9
M_CLK#7 5,9
2D5V_S3
M_BRAS#5,9
M_BCAS#5,9
M_BW E#5,9
C
DIM2
DIM2
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127
DQ32
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC
86
NC/(RESET#)
97
NC/A13
98
NC/BA2
123
NC
124
NC
200
NC
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
202
GND
SKT-SODIMM2 00-28
SKT-SODIMM2 00-28
C
REVERSE TYPE
/CS0
/CS1
CKE0
CKE1
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
CK0
/CK0
CK1
/CK1
CK2
/CK2
SCL
SDA
SA0
SA1
SA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
121
122
96
95
11
25
47
61
133
147
169
183
77
12
26
48
62
134
148
170
184
78
35
37
160
158
89
91
195
193
194
196
198
9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
201
M_CKE#1
M_DQS_R 0
M_DQS_R 1
M_DQS_R 2
M_DQS_R 3
M_DQS_R 4
M_DQS_R 6
M_DQS_R 7
M_ADM_R 0
M_ADM_R 1
M_ADM_R 2
M_ADM_R 3
M_ADM_R 4M_ADM_R 4
M_ADM_R 6
M_ADM_R 7
DDR_CLK 1
DDR_CLK #1
DM2_SA0
M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7
M_CLK4 5,9
M_CLK#4 5,9
M_CLK6 5,9
M_CLK#6 5,9
SMBC_SB 3,21
SMBD_SB 3,21
2D5V_S3
M_CS#2 5,9
M_CS#3 5,9
1 2
D
M_ADM_R [7..0] 9
M_DATA_ R_[63..0] 9
M_DQS_R [7..0] 9
M_AA[13..0 ] 5,9
M_ABS#[1 ..0] 5,9
M_BA[13..0 ] 5,9
M_BBS#[1 ..0] 5,9
3D3V_S0
R4604 K7R3 R 4604K7R3
DDR_CLK #1
DDR_CLK #0
DDR_CLK 1
DDR_CLK 0
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
D
Date: Sheet
DY
DY
RN46
RN46
8
7
6
SRN10K-2
SRN10K-2
DDR SO-DIMM SKT
DDR SO-DIMM SKT
DDR SO-DIMM SKT
W37
W37
W37
E
2D5V_S3
1
2
3
45
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
8 51Tuesday, March 15, 2 005
8 51Tuesday, March 15, 2 005
8 51Tuesday, March 15, 2 005
of
of
E
of
SB
SB
SB
A
SERIES DAMPING PARALLEL TERMINATION
PLACE RNs CLOSE TO FIRST DM ( DM1 ), < 0.75"
STRICT EQUAL LENGTH LIMITATION WITH DQS,
CB PINS
RN55
M_DATA4
M_ADM0
M_DATA6
M_DATA7
M_DATA1 3
M_DATA1 2
4 4
M_ADM1
M_DATA0
M_DATA1
M_DQS0
M_DATA2
M_DATA3
M_DATA8
M_DATA9
M_DQS1
M_DATA1 5
M_DATA2 1
M_DATA2 0
M_ADM2
M_DATA2 3 M_DATA_ R_23
M_DATA2 2
M_DATA2 5 M_DATA_ R_25
3 3
M_DATA1 1
M_DATA1 0
M_DATA1 7
M_DATA1 6
M_DQS2 M_DQS_R 2
M_DATA1 9 M_DATA_ R_19
M_DATA1 8
M_DATA2 4
M_DATA2 9
M_DATA2 8
M_ADM3
M_DATA2 6
M_DATA2 7
M_DATA3 0 M_DATA_ R_30
M_DATA3 1
2 2
RN55
1
2
3
4
5
6
7
8 9
SRN10J-3
SRN10J-3
RN56
RN56
1
2
3
4
5
6
7
8 9
SRN10J-3
SRN10J-3
RN47
RN47
1
2
3
4
5
6
7
8 9
SRN10J-3
SRN10J-3
RN48
RN48
1
2
3
4
5
6
7
8 9
SRN10J-3
SRN10J-3
RN43
RN43
1
2
3
4
5
6
7
8 9
SRN10J-3
SRN10J-3
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
M_DATA_ R_4
M_DATA_ R_5M_DATA5
M_ADM_R 0
M_DATA_ R_6
M_DATA_ R_7
M_DATA_ R_13
M_DATA_ R_12
M_ADM_R 1
M_DATA_ R_1
M_DQS_R 0
M_DATA_ R_2
M_DATA_ R_3
M_DATA_ R_8
M_DATA_ R_9
M_DQS_R 1
M_DATA_ R_14M_DATA1 4
M_DATA_ R_15
M_DATA_ R_21
M_DATA_ R_20
M_ADM_R 2
M_DATA_ R_22
M_DATA_ R_11
M_DATA_ R_10
M_DATA_ R_17
M_DATA_ R_16
M_DATA_ R_18
M_DATA_ R_24
M_DATA_ R_29
M_DATA_ R_28
M_DQS_R 3M_DQS3
M_ADM_R 3
M_DATA_ R_26
M_DATA_ R_27
M_DATA_ R_31
M_DATA3 7
M_DATA3 2
M_DATA3 3
M_DATA3 6
M_DQS4
M_ADM4 M_DATA_ R_33
M_DATA3 4
M_DATA3 9
M_DATA3 5
M_DATA4 1
M_DATA4 0
M_DQS5
M_DATA4 2
M_DATA4 3
M_DATA4 9
M_DATA4 8
M_DATA3 8
M_DATA4 5
M_DATA4 4
M_ADM5
M_DATA4 7
M_DATA4 6
M_DATA5 3
M_DATA5 2
M_DQS6
M_DATA5 0
M_DATA5 1
M_DATA5 6
M_DATA5 7
M_DQS7
M_DATA5 8
M_DATA5 9
M_ADM6
M_DATA5 4
M_DATA5 5
M_DATA6 1
M_DATA6 0
M_ADM7
M_DATA6 2
M_DATA6 3
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
RN30
RN30
SRN10J-3
SRN10J-3
RN32
RN32
SRN10J-3
SRN10J-3
RN31
RN31
SRN10J-3
SRN10J-3
RN27
RN27
SRN10J-3
SRN10J-3
RN26
RN26
SRN10J-3
SRN10J-3
B
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
M_DATA_ R_37
M_DATA_ R_32
M_DATA_ R_33
M_DATA_ R_36
M_DQS_R 4
M_ADM_R 4
M_DATA_ R_34
M_DATA_ R_39
M_DATA_ R_35
M_DATA_ R_41
M_DATA_ R_40
M_DQS_R 5
M_DATA_ R_42
M_DATA_ R_43
M_DATA_ R_49
M_DATA_ R_48
M_DATA_ R_38
M_DATA_ R_45
M_DATA_ R_44
M_ADM_R 5
M_DATA_ R_47
M_DATA_ R_46
M_DATA_ R_53
M_DATA_ R_52
M_DQS_R 6
M_DATA_ R_50
M_DATA_ R_51
M_DATA_ R_56
M_DATA_ R_57
M_DQS_R 7
M_DATA_ R_58
M_DATA_ R_59
M_ADM_R 6
M_DATA_ R_54
M_DATA_ R_55
M_DATA_ R_61
M_DATA_ R_60
M_ADM_R 7
M_DATA_ R_62
M_DATA_ R_63
M_ADM_R 1
M_DATA_ R_13
M_DATA_ R_12
M_DATA_ R_6
M_DATA_ R_7
M_ADM_R 0
M_DATA_ R_5
M_DATA_ R_4
M_DATA_ R_0
M_DATA_ R_1M_DATA_ R_0
M_DQS_R 0
M_DATA_ R_2
M_DATA_ R_3
M_DATA_ R_8
M_DATA_ R_9
M_DQS_R 1
M_DATA_ R_25
M_DATA_ R_22
M_DATA_ R_23
M_ADM_R 2
M_DATA_ R_20
M_DATA_ R_21
M_DATA_ R_14
M_DATA_ R_15
M_DATA_ R_10
M_DATA_ R_11
M_DATA_ R_16
M_DATA_ R_17
M_DQS_R 2
M_DATA_ R_19
M_DATA_ R_18
M_DATA_ R_24
M_DATA_ R_30
M_DATA_ R_31
M_DATA_ R_26
M_DATA_ R_27
M_ADM_R 3
M_DQS_R 3
M_DATA_ R_29
M_DATA_ R_28
RN57
RN57
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
RN58
RN58
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
RN49
RN49
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
RN50
RN50
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
RN45
RN45
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
C
PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 )
1D25V_S 3 1D25V_S 3
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
RN36
RN36
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
RN35
RN35
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
RN34
RN34
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
RN29
RN29
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
RN28
RN28
1
2
3
4
5
6
7
8 9
SRN68J-1
SRN68J-1
NO EQUAL LENGTH LIMITATION
M_DATA_ R_39
16
M_DATA_ R_38
15
M_DQS_R 4
14
M_ADM_R 4
13
M_DATA_ R_32
12
11
M_DATA_ R_37
10
M_DATA_ R_36
M_DATA_ R_48
16
M_DATA_ R_49
15
M_DATA_ R_43
14
M_DATA_ R_42
13
M_DQS_R 5
12
M_DATA_ R_41
11
M_DATA_ R_40
10
M_DATA_ R_34
M_DATA_ R_35
16
M_DATA_ R_44
15
M_DATA_ R_45
14
M_ADM_R 5
13
M_DATA_ R_46
12
M_DATA_ R_47
11
M_DATA_ R_53
10
M_DATA_ R_52
M_DATA_ R_59
16
M_DATA_ R_58
15
M_DQS_R 7
14
M_DATA_ R_57
13
M_DATA_ R_56
12
M_DATA_ R_51
11
M_DATA_ R_50
10
M_DQS_R 6
M_ADM_R 6
16
M_DATA_ R_55
15
M_DATA_ R_54
14
M_DATA_ R_60
13
M_DATA_ R_61
12
M_ADM_R 7
11
M_DATA_ R_63
10
M_DATA_ R_62
D
M_CKE#1
M_BA12
M_CKE#0
M_AA12
M_AA11
M_AA9
M_AA7
M_AA5
M_AA4
M_AA8
M_AA6
M_AA3
M_CS#3
M_BA13
M_CS#2
M_BRAS#
M_BBS#1
M_BCAS#
M_BA0
M_BA2
M_AA1
M_AA10
M_AA2
M_AA0
M_ABS#1
M_ABS#0
M_AW E#
M_ARAS#
M_BA7
M_BA3
M_BA6
M_BA9
M_BA10
M_BA1
M_BBS#0
M_BW E#
M_BA5
M_BA8
M_BA4
M_BA11
M_AA13
M_CS#0
M_CS#1
M_ACAS#
RN41
RN41
2
1 4
SRN47J
SRN47J
RN40
RN40
2
1 4
SRN47J
SRN47J
RN44
RN44
1
2
3
4
5
6
7
8 9
SRN47J-1 -U
SRN47J-1 -U
RN39
RN39
1
2
3
4
5
6
7
8 9
SRN47J-1 -U
SRN47J-1 -U
RN37
RN37
1
2
3
4
5
6
7
8 9
SRN47J-1 -U
SRN47J-1 -U
RN42
RN42
1
2
3
4
5
6
7
8 9
SRN47J-1 -U
SRN47J-1 -U
RN38
RN38
1
2
3
4 5
SRN47-1
SRN47-1
RN33
RN33
1
2
3
4 5
SRN47-1
SRN47-1
3
3
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
8
7
6
8
7
6
E
M_ADM_R [7..0] 8
M_ADM[7..0 ] 5
M_DATA[6 3..0] 5
M_DATA_ R_[63..0] 8
M_DQS[7..0 ] 5
M_DQS_R [7..0] 8
M_AA[13..0 ] 5,8
M_ABS#[1 ..0] 5,8
M_BA[13..0 ] 5,8
M_BBS#[1 ..0] 5,8
M_AW E# 5,8
M_ACAS# 5,8
M_ARAS# 5,8
M_BW E# 5,8
M_BCAS# 5,8
M_BRAS# 5,8
M_CS#0 5,8
M_CS#1 5,8
M_CS#2 5,8
M_CS#3 5,8
M_CKE#05,8
M_CKE#15,8
05/10
Remove the damping resistor for AMD suggest.
1 1
M_CKE#0
M_CKE#1
A
B
R42
R42
1 2
121R2F
121R2F
R41
R41
1 2
121R2F
121R2F
R66
R66
1 2
121R2F
121R2F
R65
R65
1 2
121R2F
121R2F
M_CLK7
M_CLK#7
M_CLK6
M_CLK#6
M_CLK5
M_CLK#5
M_CLK4
M_CLK#4
C
M_CLK7 5,8
M_CLK#7 5,8
M_CLK6 5,8
M_CLK#6 5,8
M_CLK5 5,8
M_CLK#5 5,8
M_CLK4 5,8
M_CLK#4 5,8
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
D
Date: Sheet
DDR DAMPING & TERMINATION
DDR DAMPING & TERMINATION
DDR DAMPING & TERMINATION
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
9 51Tuesday, March 15, 2 005
9 51Tuesday, March 15, 2 005
9 51Tuesday, March 15, 2 005
E
SB
SB
SB
of
of
of
Place it near CPU
A
B
C
D
E
4 4
2D5V_S3
1D25V_S 3
3 3
2 2
12
12
2D5V_S3
12
12
C440
C440
SCD1U
SCD1U
C461
C461
SCD1U
SCD1U
C550
C550
SCD1U
SCD1U
C521
C521
SCD1U
SCD1U
12
12
12
12
C453
C453
SCD1U
SCD1U
C515
C515
SCD1U
SCD1U
C517
C517
SCD1U
SCD1U
C454
C454
SCD1U
SCD1U
12
12
12
C428
C428
12
C500
C500
SCD1U
SCD1U
C425
C425
SCD1U
SCD1U
DY
DY
SCD1U
SCD1U
C455
C455
SCD1U
SCD1U
LAYOUT:Place altemating caps to GND and 2D5_S3
DY
DY
12
12
12
12
12
12
C499
C499
SCD1U
SCD1U
C551
C551
SCD1U
SCD1U
C514
C514
SCD1U
SCD1U
C442
C442
SCD1U
SCD1U
12
12
12
C479
C479
SCD1U
SCD1U
C460
C460
SCD1U
SCD1U
C423
C423
SCD1U
SCD1U
C452
C452
SCD1U
SCD1U
12
12
12
C504
C504
SCD1U
SCD1U
C445
C445
SCD1U
SCD1U
C552
C552
SCD1U
SCD1U
C505
C505
SCD1U
SCD1U
12
12
12
C447
C447
12
C489
C489
SCD1U
SCD1U
C457
C457
SCD1U
SCD1U
SCD1U
SCD1U
C554
C554
SCD1U
SCD1U
12
12
12
12
C494
C494
SCD1U
SCD1U
C459
C459
SCD1U
SCD1U
C476
C476
SCD1U
SCD1U
C511
C511
SCD1U
SCD1U
12
12
12
12
C493
C493
SCD1U
SCD1U
C473
C473
SCD1U
SCD1U
C490
C490
SCD1U
SCD1U
C472
C472
SCD1U
SCD1U
DY
DY
12
12
DY
DY
12
12
C536
C536
SCD1U
SCD1U
C549
C549
SCD1U
SCD1U
C458
C458
SCD1U
SCD1U
C534
C534
SCD1U
SCD1U
12
12
12
12
C497
C497
SCD1U
SCD1U
C424
C424
SCD1U
SCD1U
C456
C456
SCD1U
SCD1U
C475
C475
SCD1U
SCD1U
12
12
12
12
C528
C528
SCD1U
SCD1U
C501
C501
SCD1U
SCD1U
C474
C474
SCD1U
SCD1U
C492
C492
SCD1U
SCD1U
12
12
12
12
C537
C537
SCD1U
SCD1U
C430
C430
SCD1U
SCD1U
C462
C462
SCD1U
SCD1U
C538
C538
SCD1U
SCD1U
12
12
DY
DY
12
12
C531
C531
SCD1U
SCD1U
C518
C518
SCD1U
SCD1U
DY
DY
C421
C421
SCD1U
SCD1U
C529
C529
SCD1U
SCD1U
DY
DY
12
12
12
12
C446
C446
SCD1U
SCD1U
C519
C519
SCD1U
SCD1U
C498
C498
SCD1U
SCD1U
C535
C535
SCD1U
SCD1U
12
12
DY
DY
12
12
C520
C520
SCD1U
SCD1U
C478
C478
SCD1U
SCD1U
C491
C491
SCD1U
SCD1U
C443
C443
SCD1U
SCD1U
DY
DY
12
12
C441
C441
SCD1U
SCD1U
C487
C487
SCD1U
SCD1U
DY
DY
12
C444
C444
SCD1U
SCD1U
12
C448
C448
SCD1U
SCD1U
1D25V_S 31D25V_S 3
12
C502
C502
SCD1U
SCD1U
12
C471
C471
SCD1U
SCD1U
12
C488
C488
SCD1U
SCD1U
DY
DY
12
C513
C513
SCD1U
SCD1U
12
C496
C496
SCD1U
SCD1U
12
C439
C439
SCD1U
SCD1U
12
C530
C530
SCD1U
SCD1U
LAYOUT:Place close to Power Pin of DDR socket.
LAYOUT:Place at end of the DIMMs
1D25V_S 3
12
TC15
TC15
ST100U4 VBM-U
ST100U4 VBM-U
1 1
12
TC6
TC6
ST100U4 VBM-1
ST100U4 VBM-1
KEMET,NT:5.7, B2 size
ST100U4VBM-1 (80.10716.321)
Iripple=1.1A,ESR=70mohm
SANYO, NT$:6.1
Iripple=1.1A,ESR=70mohm
3.5/2.8/2.0
77.21071.031
A
12
C438
C438
SC22U10 V6ZY-U
SC22U10 V6ZY-U
12
C426
C426
SC22U10 V6ZY-U
SC22U10 V6ZY-U
12
C477
C477
SC22U10 V6ZY-U
SC22U10 V6ZY-U
12
C503
C503
SC22U10 V6ZY-U
SC22U10 V6ZY-U
B
C
2D5V_S3
DY
DY
DY
DY
1 2
1 2
1 2
1 2
1 2
C512
C512
SCD22U1 6V3ZY
SCD22U1 6V3ZY
C470
C470
SCD22U1 6V3ZY
SCD22U1 6V3ZY
C416
C416
SCD22U1 6V3ZY
SCD22U1 6V3ZY
C495
C495
SCD22U1 6V3ZY
SCD22U1 6V3ZY
C533
C533
SCD22U1 6V3ZY
SCD22U1 6V3ZY
0.22u x 10
D
2D5V_S3
C510
C510
1 2
SCD22U1 6V3ZY
SCD22U1 6V3ZY
C436
C436
1 2
DY
DY
DY
DY
SCD22U1 6V3ZY
SCD22U1 6V3ZY
C420
C420
1 2
SCD22U1 6V3ZY
SCD22U1 6V3ZY
C437
C437
1 2
SCD22U1 6V3ZY
SCD22U1 6V3ZY
C516
C516
1 2
SCD22U1 6V3ZY
SCD22U1 6V3ZY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
DDR DECOUPLING
DDR DECOUPLING
DDR DECOUPLING
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
10 51Tu esday, March 15, 2005
10 51Tu esday, March 15, 2005
10 51Tu esday, March 15, 2005
E
SB
SB
of
of
of
SB
A
4 4
B
C
D
E
CLAW HAMMER TO NB NB TO CLAW HAMMER
CPUCADO UT[15..0]4
CPUCADO UTJ[15..0]4
3 3
1D2V_S0
DY
C604
C604
SCD1U16 V
SCD1U16 V
12
DY
C572
C572
SCD1U16 V
SCD1U16 V
1D2V_HT 0A_S0
CPUHTTC LKOUT14
CPUHTTC LKOUTJ14
CPUHTTC LKOUT04
CPUHTTC LKOUTJ04
CPUHTTC TLOUT04
CPUHTTC TLOUTJ04
1 2
1 2
R134 49D 9R2FR134 49D9 R2F
12
2 2
AROUND NB
CPUCADO UT15
CPUCADO UTJ15
CPUCADO UT14
CPUCADO UTJ14
CPUCADO UT13
CPUCADO UTJ13
CPUCADO UT12
CPUCADO UTJ12
CPUCADO UT11
CPUCADO UTJ11
CPUCADO UT10
CPUCADO UTJ10
CPUCADO UT9
CPUCADO UTJ9
CPUCADO UT8
CPUCADO UTJ8
CPUCADO UT7
CPUCADO UTJ7
CPUCADO UT6
CPUCADO UTJ6
CPUCADO UT5
CPUCADO UTJ5
CPUCADO UT4
CPUCADO UTJ4
CPUCADO UT3
CPUCADO UTJ3
CPUCADO UT2
CPUCADO UTJ2
CPUCADO UT1
CPUCADO UTJ1
CPUCADO UT0
CPUCADO UTJ0
CPUHTTC LKOUT1
CPUHTTC LKOUTJ1
CPUHTTC LKOUT0
CPUHTTC LKOUTJ0
CPUHTTC TLOUT0
CPUHTTC TLOUTJ0
HT_RXCA LN
R521
R521
HT_RXCA LP
49D9R2F
49D9R2F
W25
W24
AA25
AA24
AB26
AA26
AC25
AC24
AD26
AC26
W30
AB29
AA29
AC29
AC28
W26
W29
W28
R26
U25
U24
V26
U26
R29
R28
T30
R30
T28
T29
V29
U29
Y30
Y28
Y29
Y26
P29
N29
D27
E27
T26
U16A
U16A
HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCTLP
HT_RXCTLN
HT_RXCALN
HT_RXCALP
RS480M-U
RS480M-U
PART 1OF6
PART 1OF6
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
R24
R25
N26
P26
N24
N25
L26
M26
J26
K26
J24
J25
G26
H26
G24
G25
L30
M30
L28
L29
J29
K29
H30
H29
E29
E28
D30
E30
D28
D29
B29
C29
L24
L25
F29
G29
M29
M28
B28
A28
NB0CADO UT15
NB0CADO UTJ15
NB0CADO UT14
NB0CADO UTJ14
NB0CADO UT13
NB0CADO UTJ13
NB0CADO UT12
NB0CADO UTJ12
NB0CADO UT11
NB0CADO UTJ11
NB0CADO UT10
NB0CADO UTJ10
NB0CADO UT9
NB0CADO UTJ9
NB0CADO UT8
NB0CADO UTJ8
NB0CADO UT7
NB0CADO UTJ7
NB0CADO UT6
NB0CADO UTJ6
NB0CADO UT5
NB0CADO UTJ5
NB0CADO UT4
NB0CADO UTJ4
NB0CADO UT3
NB0CADO UTJ3
NB0CADO UT2
NB0CADO UTJ2
NB0CADO UT1
NB0CADO UTJ1
NB0CADO UT0
NB0CADO UTJ0
NB0HTTC LKOUT1
NB0HTTC LKOUTJ1
NB0HTTC LKOUT0
NB0HTTC LKOUTJ0
NB0HTTC TLOUT
NB0HTTC TLOUTJ
HT_TXCA LP
HT_TXCA LN
1 2
NB0CADO UT[15..0] 4
NB0CADO UTJ[15..0] 4
NB0HTTC LKOUT1 4
NB0HTTC LKOUTJ1 4
NB0HTTC LKOUT0 4
NB0HTTC LKOUTJ0 4
NB0HTTC TLOUT 4
NB0HTTC TLOUTJ 4
R137
R137
100R2F
100R2F
1 1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
A
B
C
D
Date: Sheet
NB-RS480M_HT
NB-RS480M_HT
NB-RS480M_HT
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
SB
SB
11 51Tu esday, March 15, 2005
11 51Tu esday, March 15, 2005
11 51Tu esday, March 15, 2005
of
of
E
of
SB
A
4 4
3 3
2D5V_S3
12
12
R484
R484
1KR2F
1KR2F
MEM_VRE F
R485
R485
1KR2F
1KR2F
Connect MEM_VREF to VDD_MEM/2
PA_RS480F1.PDF
NB_MEM_ VMODE
12
C542
C542
SC1U10V 3KX
SC1U10V 3KX
MEM_CAP 1
MEM_CAP 2
MEM_VRE F
MPVDD_P LL
C126SCD47U1 6V3ZY C126SCD47U 16V3ZY
2 2
1D8V_S0
1 2
1 2
1 2
1 2
C548SCD47U1 6V3ZY C548SCD47U 16V3ZY
R4861KR2 R4861KR2
L260R5J-1 L260R5J -1
AF17
AK17
AH16
AF16
AJ22
AJ21
AH20
AH21
AK19
AH19
AJ17
AG16
AG17
AH17
AJ18
AG26
AJ29
AE21
AH24
AH12
AG13
AH8
AE8
AF25
AH30
AG20
AJ25
AH13
AF14
AG8
AG25
AH29
AF21
AK25
AJ12
AF13
AK7
AF9
AE17
AH18
AE18
AJ19
AF18
AK16
AJ16
AE28
AJ20
AK20
AJ15
AJ14
AJ7
AJ4
U16C
U16C
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
MEM_DQS0P
MEM_DQS1P
MEM_DQS2P
MEM_DQS3P
MEM_DQS4P
MEM_DQS5P
MEM_DQS6P
MEM_DQS7P
MEM_DQS0N
MEM_DQS1N
MEM_DQS2N
MEM_DQS3N
MEM_DQS4N
MEM_DQS5N
MEM_DQS6N
MEM_DQS7N
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_CKP
MEM_CKN
MEM_CAP1
MEM_CAP2
MEM_VMODE
MEM_VREF
MPVDD
MPVSS
RS480M-U
RS480M-U
PART 3 OF 6
PART 3 OF 6
MEM_A I/F
MEM_A I/F
MEM_COMPP
MEM_COMPN
B
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
AF28
AF27
AG28
AF26
AE25
AE24
AF24
AG23
AE29
AF29
AG30
AG29
AH28
AJ28
AH27
AJ27
AE23
AG22
AF23
AF22
AE20
AG19
AF20
AF19
AH26
AJ26
AK26
AH25
AJ24
AH23
AJ23
AH22
AK14
AH14
AK13
AJ13
AJ11
AH11
AJ10
AH10
AE15
AF15
AG14
AE14
AE12
AF12
AG11
AE11
AJ9
AH9
AJ8
AK8
AH7
AJ6
AH6
AJ5
AG10
AF11
AF10
AE9
AG7
AF8
AF7
AE7
AH5
AD30
MEM_COM PP
MEM_COM PN
DO NOT SUPPORT SIDEPORT MEMORY
DUMMY IT
PCIE_RX0P _SB18
PCIE_RX0N _SB18
PCIE_RX1P _SB18
PCIE_RX1N _SB18
DY
DY
1 2
1 2
R503
R503
DY
DY
2D5V_S3
60D4R2F
60D4R2F
1 2
1 2
R48960D4R2F
R48960D4R2F
C
PEG_RXP 15
PEG_RXN 15
PEG_RXP 14
PEG_RXN 14
PEG_RXP 13
PEG_RXN 13
PEG_RXP 12
PEG_RXN 12
PEG_RXP 11
PEG_RXN 11
PEG_RXP 10
PEG_RXN 10
PEG_RXP 9
PEG_RXN 9
PEG_RXP 8
PEG_RXN 8
PEG_RXP 7
PEG_RXN 7
PEG_RXP 6
PEG_RXN 6
PEG_RXP 5
PEG_RXN 5
PEG_RXP 4
PEG_RXN 4
PEG_RXP 3
PEG_RXN 3
PEG_RXP 2
PEG_RXN 2
PEG_RXP 1
PEG_RXN 1
PEG_RXP 0
PEG_RXN 0
R9410KR2 R9410KR 2
R938K25R3F R938K25R 3F
PEG_TXP [15..0]15
PEG_TXN [15..0]15
PEG_RXP [15..0]15
PEG_RXN [15..0]15
PCE_ISET
PCE_TXISE T
U16B
U16B
D8
GFX_RX0P
D7
GFX_RX0N
D5
GFX_RX1P
D4
GFX_RX1N
E4
GFX_RX2P
F4
GFX_RX2N
G5
GFX_RX3P
G4
GFX_RX3N
H4
GFX_RX4P
J4
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
G1
GFX_RX6P
G2
GFX_RX6N
K5
GFX_RX7P
K4
GFX_RX7N
L4
GFX_RX8P
M4
GFX_RX8N
N5
GFX_RX9P
N4
GFX_RX9N
P4
GFX_RX10P
R4
GFX_RX10N
P5
GFX_RX11P
P6
GFX_RX11N
P2
GFX_RX12P
R2
GFX_RX12N
T5
GFX_RX13P
T4
GFX_RX13N
U4
GFX_RX14P
V4
GFX_RX14N
W1
GFX_RX15P
W2
GFX_RX15N
AE1
GPP_RX0P/SB_RX2P
AE2
GPP_RX0N/SB_RX2N
AB2
GPP_RX1P/SB_RX3P
AC2
GPP_RX1N/SB_RX3N
AB5
GPP_RX2P
AB4
GPP_RX2N
Y4
GPP_RX3P
AA4
GPP_RX3N
AG1
SB_RX0P
AH1
SB_RX0N
AC5
SB_RX1P
AC6
SB_RX1N
AH3
PCE_ISET
AJ3
PCE_TXISET
RS480M-U
RS480M-U
PART 2 OF 6
PART 2 OF 6
GPP_TX0P/SB_TX2P
GPP_TX0N/SB_TX2N
GPP_TX1P/SB_TX3P
GPP_TX1N/SB_TX3N
PCIE I/F TO VIDEO
PCIE I/F TO VIDEO
PCIE I/F TO SLOT
PCIE I/F TO SLOT
PCIE I/F TO SB
PCIE I/F TO SB
D
PEG_TXP 15_NB
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
A7
B7
B6
B5
A5
A4
B3
B2
C1
D1
D2
E2
F2
F1
H2
J2
J1
K1
K2
L2
M2
M1
N1
N2
R1
T1
T2
U2
V2
V1
Y2
AA2
AD2
AD1
AA1
AB1
Y5
Y6
W5
W4
AF2
AG2
AC4
AD4
AH2
AJ2
PEG_TXN 15_NB
PEG_TXP 14_NB
PEG_TXN 14_NB
PEG_TXP 13_NB
PEG_TXN 13_NB
PEG_TXP 12_NB
PEG_TXN 12_NB
PEG_TXP 11_NB
PEG_TXN 11_NB
PEG_TXP 10_NB
PEG_TXN 10_NB
PEG_TXP 9_NB
PEG_TXN 9_NB
PEG_TXP 8_NB
PEG_TXN 8_NB
PEG_TXP 7_NB
PEG_TXN 7_NB
PEG_TXP 6_NB
PEG_TXN 6_NB
PEG_TXP 5_NB
PEG_TXN 5_NB
PEG_TXP 4_NB
PEG_TXN 4_NB
PEG_TXP 3_NB
PEG_TXN 3_NB
PEG_TXP 2_NB
PEG_TXN 2_NB
PEG_TXP 1_NB
PEG_TXN 1_NB
PEG_TXP 0_NB
PEG_TXN 0_NB
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
PCE_PCA L
PCE_NCA L
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
PCE_PCAL
PCE_NCAL
DO NOT SUPPORT SIDEPORT MEMORY
DUMMY IT
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R95 82D 5R2FR95 82D5R2F
C683 SCD1U16 VC683 SCD1U16 V
C684 SCD1U16 VC684 SCD1U16 V
C680 SCD1U16 VC680 SCD1U16 V
C682 SCD1U16 VC682 SCD1U16 V
C681 SCD1U16 VC681 SCD1U16 V
C659 SCD1U16 VC659 SCD1U16 V
C666 SCD1U16 VC666 SCD1U16 V
C664 SCD1U16 VC664 SCD1U16 V
C663 SCD1U16 VC663 SCD1U16 V
C661 SCD1U16 VC661 SCD1U16 V
C668 SCD1U16 VC668 SCD1U16 V
C669 SCD1U16 VC669 SCD1U16 V
C662 SCD1U16 VC662 SCD1U16 V
C660 SCD1U16 VC660 SCD1U16 V
C670 SCD1U16 VC670 SCD1U16 V
C667 SCD1U16 VC667 SCD1U16 V
C665 SCD1U16 VC665 SCD1U16 V
C617 SCD1U16 VC617 SCD1U16 V
C623 SCD1U16 VC623 SCD1U16 V
C624 SCD1U16 VC624 SCD1U16 V
C618 SCD1U16 VC618 SCD1U16 V
C621 SCD1U16 VC621 SCD1U16 V
C628 SCD1U16 VC628 SCD1U16 V
C625 SCD1U16 VC625 SCD1U16 V
C616 SCD1U16 VC616 SCD1U16 V
C615 SCD1U16 VC615 SCD1U16 V
C626 SCD1U16 VC626 SCD1U16 V
C627 SCD1U16 VC627 SCD1U16 V
C619 SCD1U16 VC619 SCD1U16 V
C622 SCD1U16 VC622 SCD1U16 V
C620 SCD1U16 VC620 SCD1U16 V
C577 SCD1U16 VC577 SCD1U16 V
C578 SC D1U16VC 578 SCD1U16V
C579 SC D1U16VC 579 SCD1U16V
C581 SC D1U16VC 581 SCD1U16V
C580 SCD1U16VC580 SCD1U16V
R96150R2 R96150R2
SB
E
PEG_TXP 15
PEG_TXN 15
PEG_TXP 14
PEG_TXN 14
PEG_TXP 13
PEG_TXN 13
PEG_TXP 12
PEG_TXN 12
PEG_TXP 11
PEG_TXN 11
PEG_TXP 10
PEG_TXN 10
PEG_TXP 9
PEG_TXN 9
PEG_TXP 8
PEG_TXN 8
PEG_TXP 7
PEG_TXN 7
PEG_TXP 6
PEG_TXN 6
PEG_TXP 5
PEG_TXN 5
PEG_TXP 4
PEG_TXN 4
PEG_TXP 3
PEG_TXN 3
PEG_TXP 2
PEG_TXN 2
PEG_TXP 1
PEG_TXN 1
PEG_TXP 0
PEG_TXN 0
PCIE_TX0P _SB 18
PCIE_TX0N _SB 1 8
PCIE_TX1P _SB 18
PCIE_TX1N _SB 1 8
1D2V_S0
When disable local frame buffer,
VDD_MEM connect to 2D5V_S3, MEM_VMODE
connect to GND, MEM_VREF connect to
2D5V_S3, MPVDD connected to 1D8V
1 1
DSG-215-RS480-04.PDF
A
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
NB-RS480M_MEM/PCIE_LINK I/F
NB-RS480M_MEM/PCIE_LINK I/F
NB-RS480M_MEM/PCIE_LINK I/F
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
B
C
D
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
12 51Tu esday, March 15, 2005
12 51Tu esday, March 15, 2005
12 51Tu esday, March 15, 2005
E
SB
SB
of
of
of
SB
A
12
C165
C165
3D3V_S0
1 2
1D8V_S0
12
R141
R141
R142
R142
75R2F
75R2F
75R2F
75R2F
3D3V_S0
R536
R536
1 2
0R0603-P AD
0R0603-P AD
C679
C679
SC1U10V 3ZY
SC1U10V 3ZY
DO NOT SUPPORT SIDEPORT MEMORY
DO NOT SUPPORT SERIAL STRAP ROM
DUMMY IT
R201
R201
DY
DY
1 2
0R2-0
0R2-0
R204
R204
1 2
R205
R205
1D8V_S0
0R3-U
0R3-U
1 2
C646
C646
SC10U10 V5ZY
SC10U10 V5ZY
DY
DY
4 4
Do not populate
when using M26
RS480_T V_CRMA16
RS480_T V_LUMA16
3 3
1D8V_S0
2 2
ALL_PW ROK39,40
1 1
R519
R519
12
MAIN_CRT_ R16
MAIN_CRT_ G16
MAIN_CRT_ B16
R133
R133
1 2
150R3F
150R3F
C140
C140
SC10U10 V5ZY
SC10U10 V5ZY
1D8V_S0
12
NB_SUS_ STAT#
LDT_RST #6 ,18
LPC_RST #18,37
AVDDQ
R92
R92
4K7R2
4K7R2
12
C647
C647
SCD1U16 V
SCD1U16 V
1D8V_S0
12
LDT_RST #
R176
R176
1 2
BLM11A1 21S
BLM11A1 21S
C166
C166
SC10U10 V5ZY
SC10U10 V5ZY
HTPVDD
12
C141
C141
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
A
12
R138
R138
75R2F
75R2F
12
C142
C142
1 2
3D3V_S0
1
2
3D3V_S0
9
10
12
12
DY
DY
147
147
12
R139
R139
75R2F
75R2F
PLVDD
12
C150
C150
SCD1U16 V
SCD1U16 V
R203
R203
0R2-0
0R2-0
1 2
SB
R140
R140
75R2F
75R2F
12
SCD1U16 V
SCD1U16 V
U28A
U28A
3
TSLCX08 MTC-U
TSLCX08 MTC-U
U28C
U28C
RS480_R ST#_R RS480_R ST#
8
TSLCX08 MTC-U
TSLCX08 MTC-U
DY
DY
33R2
33R2
R675
R675
DUMMY-R3
DUMMY-R3
R522
R522
1 2
33R2
33R2
B
0R3-U
0R3-U
GMCH_VS YNC16
GMCH_HS YNC16
VGA_CLK _DDC_316
VGA_DAT _DDC_316
12
AG_RST# 1 5,34
12
C189
C189
DUMMY-C3
DUMMY-C3
DY
DY
B
R515
R515
1 2
12
C649
C649
SC1U10V 3ZY
SC1U10V 3ZY
3D3VDDR _S0
CLK14_N B3
NB_PW RGD
AVDD2D5V_S0
0R3-U
0R3-U
12
LDT_STP #6,18
ALLOW _LDTSTOP18
LVDS_DIGO N
RB751V-4 0-U
RB751V-4 0-U
LVDS_BL ON
C598
C598
SC1U10V 3ZY
SC1U10V 3ZY
1D8VAVD DD1_S0
AVDDQ
12
1 2
1 2
1 2
Do not populate
when using M26
NB_PW RGD40
12
12
BMREQ#18
VGA_SMB _CLK17
VGA_SMB _DAT17
THERMAL _P_NB2 3
THERMAL _N_NB23
12
D16
D16
DY
DY
D14
D14
RB751V-4 0-U
RB751V-4 0-U
DY
DY
1 2
C648
C648
SC1U10V 3ZY
SC1U10V 3ZY
TP84T PAD28 TP 84T PAD28
TPAD28
TPAD28
R5263KR2F
R5263KR2F
12
R5243KR2F
R5243KR2F
R5253KR2F
R5253KR2F
12
R520715R3F R520715R3F
R5270R2-0 R5270R2-0
R5280R2-0 R5280R2-0
TP35
TP35
DY
DY
DY
DY
DY
DY
TP77TPAD28 TP77TPAD28
THERMAL _P_NB
THERMAL _N_NB
3D3V_S0
R202
R202
2KR2
2KR2
4
5
12
R177
R177
1KR2
1KR2
IRSET_NB
VGA_CLK _DDC_NB
VGA_DAT _DDC_NB
RS480_R ST#
NB_SUS_ STAT#
NB_OSC_ OUT
DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
U28B
U28B
147
6
TSLCX08 MTC-U
TSLCX08 MTC-U
3D3V_S0
147
12
13
1 2
C
R842
R842
1 2
0R3-U
0R3-U
DY
DY
B27
C27
D26
D25
C24
B24
E24
D24
B25
A25
A24
C25
A26
B26
A11
B11
C26
E11
F11
A14
B14
M23
L23
D14
B15
B12
C12
AH4
H13
H12
A13
B13
B9
F12
E13
D13
F10
C10
C11
AF4
AE4
DY
DY
1 2
U28D
U28D
11
TSLCX08 MTC-U
TSLCX08 MTC-U
DY
DY
R543
R543
0R2-0
0R2-0
C
2D5V_CR T
U16D
U16D
AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI
AVDDQ
AVSSQ
C
Y
COMP
RED
GREEN
BLUE
DAC_VSYNC
DAC_HSYNC
RSET
DAC_SCL
DAC_SDA
PLLVDD
PLLVSS
HTPVDD
HTPVSS
SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
SUS_STAT#
VDDR3_1
VDDR3_2
OSCIN
OSCOUT
TVCLKIN
DFT_GPIO0/RSV
DFT_GPIO1/RSV
DFT_GPIO2/RSV
BMREQb
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N
RS480M-U
RS480M-U
R542
R542
0R2-0
0R2-0
2D5V_CR T
3D3V_S0
Iomax=120mA
U82
U82
1
SHDN#
2
GND
3
IN
G913C-U
G913C-U
Vout = 1.25*(1+ R1/R2)
PART 4 OF 6
CRT/TVOUT
CRT/TVOUT
PLL PWR
PLL PWR
1 2
PART 4 OF 6
PM
PM
CLOCKs
CLOCKs
MIS.
MIS.
LCD_VDD _ON 17
R207
R207
0R2-0
0R2-0
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXOUT_L0N
TXOUT_L1N
TXOUT_L2N
TXOUT_L3N
LVDS
LVDS
LVDDR18A_1
LVDDR18A_2
LVDS_DIGON
LVDS_BLON
DFT_GPIO3/RSV
DFT_GPIO4/RSV
DFT_GPIO5/RSV
STRP_DATA
R147
R147
DUMMY-R2
DUMMY-R2
DY
DY
GMCH_BL _ON 34
RESISTOR
DY
DY
TXOUT_L0P
TXOUT_L1P
TXOUT_L2P
TXOUT_L3P
TXCLK_UP
TXCLK_UN
TXCLK_LP
TXCLK_LN
LPVDD
LPVSS
LVDDR18D
LVSSR1
LVSSR2
LVSSR3
LVSSR4
LVSSR5
LVSSR6
LVSSR7
LVSSR8
LVDS_BLEN
GFX_CLKP
GFX_CLKN
HTTSTCLK
HTREFCLK
SB_CLKP
SB_CLKN
TMDS_HPD
DDC_DATA
TESTMODE
3D3V_S0
R108
R107
SET
OUT
SC1U10V 3KX
SC1U10V 3KX
12
12
R146
R146
4K7R2
4K7R2
D
2D5V_CR T
5
4
C812
C812
DY
DY
D18
C18
B19
A19
D19
C19
TXBOUT3 +
D20
TXBOUT3 -
C20
B16
A16
D16
C16
B17
A17
TXAOUT3 +
E17
TXAOUT3 -
D17
B20
A20
B18
C17
E18
F17
E19
G20
H20
G19
E20
F20
H18
G18
F19
H19
F18
E14
F14
F13
B8
A8
HTTST_C LK
P23
N23
E8
E7
DFT_GPIO3
C13
DFT_GPIO4
C14
DFT_GPIO5
C15
A10
E10
B10
TESTMOD E_NB
E12
RS480M MODE
NORMAL MODE
D
2D5V_CR T
12
LVDS_DIGO N
LVDS_BL ON
LVDS_BL EN_NB
1 2
TP36
TP36
TPAD28
TPAD28
R181
R181
2KR2
2KR2
STRP_DA TA
R180
R180
2KR2
2KR2
DY
DY
TEST MODE
E
R1
12
R843
R843
20KR3F
20KR3F
DY
DY
12
R844
R844
20KR3F
20KR3F
DY
DY
R2
TP79 T PAD30TP79 TPAD 30
TP80 T PAD30TP80 TPAD 30
TP82 T PAD30TP82 TPAD 30
TP81 T PAD30TP81 TPAD 30
GMCH_TX BCLK+ 17
GMCH_TX BCLK- 17
GMCH_TX ACLK+ 17
GMCH_TX ACLK- 17
1D8VLPV DD_S0
LVDDR18 D_S0
LVDDR18 A_S0
12
SC1U10V 3ZY
SC1U10V 3ZY
TP83 T PAD30TP83 TPAD 30
NBSRC_C LK 3
NBSRC_C LK# 3
R516 1 0KR2R516 10KR2
HTREF_C LK 3
SBLINK_CL K 3
SBLINK_CL K# 3
R145 3 KR2F
R145 3 KR2F
12
DY
DY
R144
R144
12
3KR2F
3KR2F
DY
DY
R143
R143
12
3KR2F
3KR2F
DY
DY
TP85 T PAD28TP85 TPAD 28
TP34
TP34
TPAD28
TPAD28
12
12
DISABLE DEBUG MODE
DUMMY IT
3D3V_S0
DY
DY
12
DY
DY
C167
C167
R179
R179
SCD1U16 V
SCD1U16 V
1KR2
1KR2
1 2
VGA_SMB _CLK
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
3D3V_S0
12
12
R178
12
R178
4K7R2
4K7R2
VGA_SMB _CLK
VGA_SMB _DAT
1D8V_S0
R531
R531
1 2
BLM11A1 21S
BLM11A1 21S
12
C657
C657
SCD1U16 V
SCD1U16 V
R523
R523
1 2
BLM11A1 21S
BLM11A1 21S
12
C655
C655
SCD1U16 V
SCD1U16 V
R132
R132
1 2
BLM11A1 21S
BLM11A1 21S
C147
C147
SCD1U16 V
SCD1U16 V
DY
DY
4
GND
3
A2
2
A1
1
A0
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
13 51Friday, April 15, 20 05
13 51Friday, April 15, 20 05
13 51Friday, April 15, 20 05
E
R148
R148
4K7R2
4K7R2
GMCH_TX BOUT0+ 17
GMCH_TX BOUT0- 17
GMCH_TX BOUT1+ 17
GMCH_TX BOUT1- 17
GMCH_TX BOUT2+ 17
GMCH_TX BOUT2- 17
GMCH_TX AOUT0+ 17
GMCH_TX AOUT0- 17
GMCH_TX AOUT1+ 17
GMCH_TX AOUT1- 17
GMCH_TX AOUT2+ 17
GMCH_TX AOUT2- 17
12
C678
C678
SC1U10V 3ZY
SC1U10V 3ZY
12
C677
C677
SC1U10V 3ZY
SC1U10V 3ZY
C149
C149
U20
U20
5
SDA
6
SCL
7
WP
8
VCC
AT24C04 N-10SI
AT24C04 N-10SI
NB-RS480M_VIDEO/ CLOCK
NB-RS480M_VIDEO/ CLOCK
NB-RS480M_VIDEO/ CLOCK
SB
SB
of
of
of
SB
A
B
C
D
E
VSS89
H17
H10
H16
H14
E16
D10
E15
F15
U15
V14
R15
T14
N15
V12
N13
P14
U17
T16
R17
P12
T12
R13
W13
W17
P18
V18
M18
U13
N17
W15
V16
T18
M14
M12
M16
P16
U19
AC16
AG18
AC23
AD8
AD11
AD13
AD16
AD19
AD23
AG5
AG6
AG21
AD17
AG15
AG12
AF30
AG24
AG9
AC19
AG27
AC11
AD7
AJ30
AC21
AK5
AK10
AC13
AD21
AK22
AK29
W19
AE26
AE27
T27
R27
AD28
F24
F27
G28
U16F
U16F
4 4
1D2V_S0
12
C558
C558
12
C560
C560
12
DY
DY
C539
C539
12
DY
DY
C562
C562
R487
R487
0R2-0
0R2-0
DY
DY
3
U73
U73
BAV99-1
BAV99-1
12
12
SCD1U16 V
SCD1U16 V
12
SCD1U16 V
SCD1U16 V
12
SCD1U16 V
SCD1U16 V
12
SCD1U16 V
SCD1U16 V
12
R488
R488
0R2-0
0R2-0
DY
DY
DY
DY
R501
R501
0R5J-1
0R5J-1
C650
C650
SCD1U16 V
SCD1U16 V
C599
C599
SCD1U16 V
SCD1U16 V
DY
DY
C540
C540
SCD1U16 V
SCD1U16 V
DY
DY
C563
C563
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
12
12
12
R502
R502
0R5J-1
C603
C603
SCD1U16 V
SCD1U16 V
DY
DY
C559
C559
SCD1U16 V
SCD1U16 V
DY
DY
C545
C545
SCD1U16 V
SCD1U16 V
DY
DY
C569
C569
SCD1U16 V
SCD1U16 V
1 2
BLM11A1 21S
BLM11A1 21S
0R5J-1
12
C602
C602
12
C557
C557
12
DY
DY
C555
C555
12
DY
DY
C561
C561
L25
L25
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
1 2
A
3 3
SC22U10 V6ZY-U
SC22U10 V6ZY-U
12
12
C115
C115
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
12
12
C556
C556
SCD1U16 V
SCD1U16 V
SC22U10 V6ZY-U
SC22U10 V6ZY-U
2 2
12
12
DY
DY
C117
C117
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
12
12
DY
DY
C543
C543
SCD1U16 V
SCD1U16 V
1D8V_S0
1 1
3D3V_S0
DY
DY
3
1 2
U72
U72
BAV99-1
BAV99-1
12
C651
C651
12
C600
C600
12
DY
DY
C547
C547
12
DY
DY
C570
C570
C566
C566
SCD1U16 V
SCD1U16 V
12
12
SCD1U16 V
SCD1U16 V
12
SCD1U16 V
SCD1U16 V
12
SCD1U16 V
SCD1U16 V
12
SCD1U16 V
SCD1U16 V
1D8VDD_ S0
12
C565
C565
SCD1U16 V
SCD1U16 V
VSS111
VSS112
R504
R504
0R5J-1
0R5J-1
C653
C653
C601
C601
DY
DY
C571
C571
SCD1U16 V
SCD1U16 V
DY
DY
C568
C568
SCD1U16 V
SCD1U16 V
12
C607
C607
SC1U10V 3KX
SC1U10V 3KX
VSS108
VSS109
VSS110
2D5V_S3
12
12
VSS107
DY
DY
C546
C546
DY
DY
C573
C573
12
C541
C541
VSS102
VSS103
VSS104
VSS105
VSS106
1D2V_HT 0A_S0
VDDHT30
VDDHT31
1D2V_S0
VSS101
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
U16E
U16E
RS480M-U
RS480M-U
N27
VDD_HT1
U27
VDD_HT2
V27
VDD_HT3
G27
VDD_HT4
V24
VDD_HT5
H27
VDD_HT6
K24
VDD_HT7
AB24
VDD_HT8
P27
VDD_HT9
J27
VDD_HT10
AA27
VDD_HT11
K27
VDD_HT12
P24
VDD_HT13
AB27
VDD_HT14
AB23
VDD_HT15
V23
VDD_HT16
G23
VDD_HT17
E23
VDD_HT18
W23
VDD_HT19
K23
VDD_HT20
J23
VDD_HT21
H23
VDD_HT22
U23
VDD_HT23
AA23
VDD_HT24
D23
VDD_HT25
F23
VDD_HT26
C23
VDD_HT27
B23
VDD_HT28
A23
VDD_HT29
A29
VDD_HT30
AC30
VDD_HT31
AK23
VDD_MEM1
AK28
VDD_MEM2
AK11
VDD_MEM3
AK4
VDD_MEM4
AE30
VDD_MEM5
AC14
VDD_MEM6
AD12
VDD_MEM7
AC18
VDD_MEM8
AC20
VDD_MEM9
AD10
VDD_MEM10
AD14
VDD_MEM11
AD15
VDD_MEM12
AD20
VDD_MEM13
AC10
VDD_MEM14
AD18
VDD_MEM15
AC12
VDD_MEM16
AD22
VDD_MEM17
AC22
VDD_MEM18
AH15
VDD_MEMCK
H15
VDD_18_1
AC17
VDD_18_2
AC15
VDD_18_3
B21
VDD_CORE47
C21
VDD_CORE46
A22
VDD_CORE45
B22
VDD_CORE44
C22
VDD_CORE43
F21
VDD_CORE42
F22
VDD_CORE41
E21
VDD_CORE40
G21
VDD_CORE39
B
VSS92
VSS93
VSS88
VSS89
VSS90
VSS91
VSS132
R23
PART 5 OF 6
PART 5 OF 6
VSS87
VSS131
V28
VSS85
VSS86
VSS129
VSS130
V25
U28
POWER
POWER
VSS82
VSS83
VSS84
VSS126
VSS127
VSS128
P28
E26
K25
VDDA_12_14
VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8
VDDA_12_9
VDDA_12_10
VDDA_12_11
VDDA_12_12
VDDA_12_13
VDDA_18_1
VDDA_18_2
VDDA_18_3
VDDA_18_4
VDDA_18_5
VDDA_18_6
VDDA_18_7
VDDA_18_8
VDDA_18_9
VDDA_18_10
VDDA_18_11
VDDA_18_12
VDDA_18_13
VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE9
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE24
VDD_CORE25
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE29
VDD_CORE30
VDD_CORE31
VDD_CORE32
VDD_CORE33
VDD_CORE34
VDD_CORE35
VDD_CORE36
VDD_CORE37
VDD_CORE38
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS120
VSS122
VSS123
VSS124
VSS125
L27
P25
H24
N28
M27
H9
AA7
G9
U8
N7
N8
U7
F9
AA8
G8
G7
J8
J7
B1
AG4
R8
AC8
AC7
AF6
AE6
L8
W8
W7
L7
R7
AF5
AK2
N16
M13
M15
W16
N18
P19
N12
P15
N14
M17
T19
G22
R12
P13
R14
V19
R18
U16
U12
T13
U14
T17
U18
E22
R16
V13
T15
P17
W18
D22
W12
V15
W14
V17
M19
H22
H21
D21
VSS75
VSS119
T23
K28
VSS73
VSS74
VSS116
VSS117
VSS118
J28
N19
M24
VDDA12_ 13
VDDA18_ 13
VSS72
VSS114
VSS115
H28
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
GROUND
GROUND
VSS113
T8
F28
12
C574
C574
SC1U10V 3KX
SC1U10V 3KX
1D8V_VD DA
12
C582
C582
SC1U10V 3KX
SC1U10V 3KX
1D2V_S0
SC22U10 V6ZY-U
SC22U10 V6ZY-U
C
VSS61
VSS62
VSS63
VSS64
VSS65
12
C611
C611
SCD1U16 V
SCD1U16 V
12
C575
C575
SCD1U16 V
SCD1U16 V
12
C125
C125
SC22U10 V6ZY-U
SC22U10 V6ZY-U
SCD1U16 V
SCD1U16 V
12
C139
C139
SCD1U16 V
SCD1U16 V
VSS60
VSS57
VSS58
VSS59
VSSA60M7VSSA61V7VSSA62F6VSSA63E6VSSA64U5VSSA65U6VSSA66E5VSSA67L5VSSA68
AJ1
VSSA59
12
C610
C610
SCD1U16 V
SCD1U16 V
12
C613
C613
SCD1U16 V
SCD1U16 V
12
C605
C605
12
C654
C654
SCD1U16 V
SCD1U16 V
VSS54
VSS55
VSS56
VSSA58L6VSSA59
AG3
SCD1U16 V
SCD1U16 V
SCD1U16 V
SCD1U16 V
12
SCD1U16 V
SCD1U16 V
12
VSS53
12
12
C608
C608
DY
DY
C656
C656
VSS51
VSS52
C606
C606
C614
C614
VSS48
VSS49
VSS50
VSSA51K7VSSA52H7VSSA53M3VSSA54V6VSSA55H8VSSA56C2VSSA57
AD6
12
SCD1U16 V
SCD1U16 V
12
12
C567
C567
SCD1U16 V
SCD1U16 V
12
C652
C652
SCD1U16 V
SCD1U16 V
VSS47
VSS45
VSS46
VSSA48T7VSSA49Y7VSSA50
AB8
C658
C658
1 2
MLB-2012 09-11
MLB-2012 09-11
C576
C576
SCD1U16 V
SCD1U16 V
12
SCD1U16 V
SCD1U16 V
12
VSS43
VSS44
VSSA44D6VSSA45C4VSSA46K3VSSA47
AD5
12
L27
L27
C564
C564
C612
C612
SCD1U16 V
SCD1U16 V
VSS38
VSS39
VSS40
VSS41
VSS42
VSSA38C9VSSA39C7VSSA40J5VSSA41R6VSSA42J3VSSA43
AA5
C128
C128
SC22U10 V6ZY-U
SC22U10 V6ZY-U
1D8V_S0
DY
DY
12
C609
C609
SCD1U16 V
SCD1U16 V
D
VSS37
H11
AD25
VSS36
1D2V_S0
VSS30
G10
G12
AD29
AD27
AC27
G15
G14
Y24
G13
D15
AD9
G11
F16
G30
AB28
AB25
D12
AD24
AA28
G17
Y23
AC9
R19
Y27
C28
G16
F25
B30
T24
F26
W27
D11
RS480M-U
RS480M-U
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10E9VSS11
VSS12D9VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
PAR 6 OF 6
PAR 6 OF 6
VSSA1R5VSSA2
AA6
VSSA3V5VSSA4N3VSSA5F7VSSA6F5VSSA7R3VSSA8
VDDA12_ 13
VSSA22
VDDA18_ 13
VSSA59
VDDHT30
VSS30
VDDHT31
VSS89
E
AE5
14 51Mo nday, March 14, 2005
14 51Mo nday, March 14, 2005
14 51Mo nday, March 14, 2005
12
C151
C151
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
12
C116
C116
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
12
C148
C148
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
12
C127
C127
SC4D7U1 0V5ZY
SC4D7U1 0V5ZY
of
of
of
SB
SB
SB
VSSA22A2VSSA23
VSSA24P8VSSA25J6VSSA26C8VSSA27
VSSA28V8VSSA29F3VSSA30
VSSA31
VSSA32M5VSSA33
VSSA34G3VSSA35B4VSSA36P7VSSA37
AF3
AE3
AB7
AD3
AA3
AB3
VSSA22
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet
Date: Sheet
Date: Sheet
NB-RS480M_POWER
NB-RS480M_POWER
NB-RS480M_POWER
A3
A3
A3
VSSA9T3VSSA10M6VSSA11C5VSSA12F8VSSA13M8VSSA14Y8VSSA15V3VSSA16C3VSSA17W3VSSA18K8VSSA19D3VSSA20C6VSSA21
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
A
4 4
PEG_TXP [15..0]12
PEG_TXN [15..0]12
PEG_RXP [15..0]12
PEG_RXN [15..0]12
PM_SLP_ S3# MXM_PW EOK
1 2
0R2-0
0R2-0
3 3
DY
DY
1D8V_S0
R529
R529
5V_S0
TPAD30
TPAD30
TP78
TP78
B
DY
DY
R483
1 2
1 2
1 2
1 2
1 2
1 2
R483
150R2F
150R2F
DY
DY
R499
R499
150R2F
150R2F
DY
DY
R497
R497
150R2F
150R2F
DY
DY
R500
R500
150R2F
150R2F
DY
DY
R496
R496
150R2F
150R2F
DY
DY
R498
R498
150R2F
150R2F
Put near graphic connector
PEG_TXN15
PEG_TXN14
PEG_TXP14
PEG_TXP15
PEG_TXP12
PEG_TXP11
PEG_TXN12
PEG_TXN13
PEG_TXN11
PEG_TXP13
MXM_BLU E
MXM_GRE EN
MXM_RED
MXM_TV_ DACA
MXM_TV_ LUMA
MXM_TV_ CRMA
PEG_TXN9
PEG_TXP10
PEG_TXN10
C
MXM_TXB OUT0+17
MXM_TXB OUT0-17
MXM_TXB OUT1+17
MXM_TXB OUT1-17
MXM_TXB OUT2+17
MXM_TXB OUT2-17
MXM_TXB CLK+17
MXM_TXB CLK-17
MXM_BLU E16
MXM_GRE EN16
MXM_RED16
PEG_TXN2
PEG_TXP2
MXM_TV_ DACA
PEG_TXP1
PEG_TXN1
PEG_TXN0
PEG_TXP0
MXM_TV_ LUMA1 6
MXM_TV_ CRMA16
MXM_CD34
PEG_TXN8
PEG_TXP9
PEG_TXN7
PEG_TXP8
PEG_TXN5
PEG_TXP5
PEG_TXN6
PEG_TXP6
PEG_TXP7
PEG_TXN3
PEG_TXP3
PEG_TXP4
PEG_TXN4
TPAD30
TPAD30
TP74
TP74
D
TPAD30
TPAD30
TP73
TP73
TPAD30
TPAD30
TP71
TP71
TPAD30
TPAD30
TP72
TP72
E
MXM_TXA CLK- 17
MXM_TXA CLK+ 17
MXM_TXA OUT2- 17
MXM_TXA OUT2+ 17
MXM_TXA OUT1- 17
MXM_TXA OUT1+ 17
MXM_TXA OUT0- 17
MXM_TXA OUT0+ 17
DY
DY
R478
1 2
1 2
SMBD_GMODULE
SMBC_GMODULE
R478
0R2-0
0R2-0
R477
R477
0R2-0
0R2-0
DY
DY
EDID_DAT 17
EDID_CLK 17
MXM_LCD VDD_ON 17
LBKLT_C RTL 17
MXM_BL_ ON 34
2D5V_S0
3D3V_S0
CN6
CN6
DY
DY
SPD-CONN 230A-1
SPD-CONN 230A-1
2 2
1 1
5V_S0 2D5V_ S0
12
1D8V_S0
12
3D3V_S0
12
DCBATOU T
12
C675
C675
SCD1U16 V
SCD1U16 V
C673
C673
SCD1U16 V
SCD1U16 V
C508
C508
SCD1U16 V
SCD1U16 V
C671
C671
SCD1U16 V
SCD1U16 V
12
12
12
12
A
C524
C524
SCD1U16 V
SCD1U16 V
C674
C674
SCD1U16 V
SCD1U16 V
C507
C507
SCD1U16 V
SCD1U16 V
C672
C672
SCD1U16 V
SCD1U16 V
SMBC_KB C23,34
2468101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698
13579
231
MH1
DCBATOU T
3D3V_AU X_S5
111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
PEG_RXP11
PEG_RXP12
D
D
1
R471
R471
10KR2
10KR2
DY
DY
R470
R470
100KR2
100KR2
DY
DY
PEG_RXN11
G
G
S
S
23
12
12
PEG_RXP10
PEG_RXN9
PEG_RXN10
R493 0 R2-0
R493 0 R2-0
R495 0 R2-0
R495 0 R2-0
R494 0 R2-0
R494 0 R2-0
Q35
Q35
2N7002
2N7002
DY
DY
3D3V_S0
12
R469
R469
10KR2
10KR2
DY
DY
12
R467
R467
10KR2
10KR2
DY
DY
PEG_RXP9
R466
R466
10KR2
10KR2
DY
DY
R468
R468
10KR2
10KR2
DY
DY
PEG_RXN8
DY
DY
DY
DY
DY
DY
PEG_RXP8
12
12
PEG_RXN7
PEG_RXP7
R465
R465
DUMMY-R2
DUMMY-R2
DY
DY
R472
R472
10KR2
10KR2
DY
DY
OVERT#23
DY
1 2
R4924 K7R2DYR4924 K7R2
(E2,E1,E0) should be
(1,1,0) when use
extral VGA card
AG_RST#13,34
SMBD_KB C23,34
OVERT#
PEG_RXN15
PEG_RXP15
PEG_RXN14
3D3V_S0
B
PEG_RXN12
PEG_RXN13
PEG_RXP14
PEG_RXP13
1 2
1 2
1 2
12
12
PEG_RXP6
PEG_RXN6
1
2
3
PEG_RXN5
PEG_RXP5
CLK_PCIE_ PEG#3
CLK_PCIE_ PEG3
MXM_HSYNC1 6
MXM_VSYNC16
U71
U71
E0
E1
E2
VSS4SDA
M24C02-W
M24C02-W
DY
DY
100
102
104
106
101
103
105
PEG_RXN2
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXP2
MXM_DDC CLK16
MXM_DDC DATA16
PM_SLP_ S3#18,21,34,3 8,39,45
WC# -- H: Write disable
L: Write enable
3D3V_S0
8
VCC
7
WC#
6
SCL
5
C
108
110
112
114
116
107
109
111
113
115
PEG_RXN0
PEG_RXP0
PEG_RXP1
PEG_RXN1
SMBC_GM ODULE
SMBD_GM ODULE
12
C506
C506
SCD1U16 V
SCD1U16 V
DY
DY
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
232
MH2
TP75
TP75
TPAD30
TPAD30
R482
R482
0R2-0
0R2-0
DY
DY
1 2
WC#WC#
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
D
Date: Sheet
ATI M22_MXM_ CONNECTOR
ATI M22_MXM_ CONNECTOR
ATI M22_MXM_ CONNECTOR
G792_DX P2 23
G792_DX N2 23
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
15 51Tu esday, March 15, 2005
15 51Tu esday, March 15, 2005
15 51Tu esday, March 15, 2005
of
of
E
of
SB
SB
SB
A
CRT I/F & CONNECTOR
Layout Note:
Place these resistors
close to the CRT-out
connector
4 4
3 3
MXM_HSYNC1 5
GMCH_HS YNC13
MXM_VSYNC15
GMCH_VS YNC13
2 2
CRT_RED
CRT_GRE EN
CRT_BLU E
Hsync & Vsync level shift
R534 D UMMY-R2
R534 D UMMY-R2
DY
DY
1 2
1 2
R532
R532
R535 D UMMY-R2
R535 D UMMY-R2
DY
DY
1 2
1 2
R533
R533
MAIN_CRT_ R13
MAIN_CRT_ G13
MAIN_CRT_ B13
MXM_BLU E15
MXM_GRE EN15
MXM_RED15
0R2-0
0R2-0
0R2-0
0R2-0
VSYNC_4
1
2
3
4 5
1
2
3
4 5
RN11
RN11
DY
DY
5 6
RN12
RN12
SRN0-1-U
SRN0-1-U
HSYNC_4
SC3P50V 3KN
SC3P50V 3KN
14
4
U6B TSAHCT125U6B TSAH CT125
7
SRN0-1-U
SRN0-1-U
8
7
6
8
7
6
2 3
C68
C68
DY
DY
SC3P50V 3KN
SC3P50V 3KN
5V_S0
12
14
1
U6A TSAHCT125U6A TSAH CT125
7
B
Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
Ferrite bead impedance: 47ohm@100MHz
C67
C67
DY
DY
SC3P50V 3KN
SC3P50V 3KN
C39
C39
SCD1U16 V
SCD1U16 V
HSYNC_5
VSYNC_5
CRT_RED
CRT_GRE EN
CRT_BLU E
C58
C58
DY
DY
1 2
1 2
1 2
1 2
1 2
L3
L3
BLM18BB 470SN1-GP
BLM18BB 470SN1-GP
L1
L1
BLM18BB 470SN1-GP
BLM18BB 470SN1-GP
L2
L2
BLM18BB 470SN1-GP
BLM18BB 470SN1-GP
R39
R39
39R2J
39R2J
R38
R38
39R2J
39R2J
SC3P50V 3CN
SC3P50V 3CN
JVGA_HS
JVGA_VS
12
C66
C66
CRT_R
SC3P50V 3CN
SC3P50V 3CN
CRT_G
CRT_B
HSYNC_5
VSYNC_5
C
12
C56
C56
D12 BAV 99-2D 12 BAV99-2
3
D10 BAV 99-2D 10 BAV99-2
3
D11 BAV 99-2D 11 BAV99-2
3
D8 BAV99-2D8 BAV99 -2
3
D9 BAV99-2D9 BAV99 -2
3
CRT_R
CRT_G
CRT_B
12
C57
C57
SC3P50V 3CN
SC3P50V 3CN
2
1
2
1
2
1
2
1
2
1
5V_S0
5V_S0
CLK_DDC 1_5
JVGA_VS
CRT_B
JVGA_HS
CRT_G
DAT_DDC 1_5
CRT_R
DDC_CLK & DATA level shift
DY
DY
MXM_DDC DATA15
VGA_DAT _DDC_313
MXM_DDC CLK15
VGA_CLK _DDC_313
1 2
1 2
R539
R539
DY
DY
1 2
1 2
R537
R537
D
5V_S0
12
D36
D36
RB751V-4 0-U
RB751V-4 0-U
12
R40
R40
2K2R2
2K2R2
12
C46
C46
SC100P
SC100P
R540 D UMMY-R2
R540 D UMMY-R2
0R2-0
0R2-0
R538 D UMMY-R2
R538 D UMMY-R2
0R2-0
0R2-0
F3
F3
1 2
FUSE-1A6 V-GP
FUSE-1A6 V-GP
12
R43
R43
2K2R2
2K2R2
12
C59
C59
SC100P
SC100P
SC22P50 V2JN-1
SC22P50 V2JN-1
2D5V_S0
12
12
12
C45
C45
R44
R44
0R0402-P AD
0R0402-P AD
R46
R46
2K2R2
2K2R2
5V_CRT_ S0
C44
C44
1 2
SC22P50 V2JN-1
SC22P50 V2JN-1
12
R47
R47
2K2R2
2K2R2
2 3
12
G
G
1
S
S
C451
C451
SCD01U1 6V2KX
SCD01U1 6V2KX
FOX-CONN 15-2-U
FOX-CONN 15-2-U
16
MH2
5
15
10
4
14
9
3
13
8
2
12
7
1
11
6
MH1
17
R45
R45
0R0402-P AD
0R0402-P AD
2N7002
2N7002
Q7
Q7
D
D
2N7002
2N7002
G
G
1
Q6
Q6
2 3
S
S
E
CRT1
CRT1
D
D
3D3V_S0
12
DAT_DDC 1_5
CLK_DDC 1_5
5V @ ext. CRT side
2
1
2
1
3D3V_S0
12
3D3V_S0
12
C392
C392
SCD1U16 V
SCD1U16 V
C434
C434
SCD1U16 V
SCD1U16 V
D
<Variant Name>
<Variant Name>
<Variant Name>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
CRT/TV Connector
CRT/TV Connector
CRT/TV Connector
Taipei Hsien 221, Taiwan, R.O.C.
W37
W37
W37
16 51Friday, April 15, 20 05
16 51Friday, April 15, 20 05
16 51Friday, April 15, 20 05
of
of
E
of
SB
SB
SB
MINDIN4-29
C406S C33P C406SC33P
1 2
1 2
1 2
1 2
R1740 R2-0DYR1740 R2-0
R1750 R2-0 R1750 R2-0
R1720 R2-0DYR1720 R2-0
R1730 R2-0 R1730 R2-0
12
12
B
MXM_TV_ CRMA15
RS480_T V_CRMA13
1 1
MXM_TV_ LUMA1 5
RS480_T V_LUMA13
A
DY
DY
C409
C409
SC150P
SC150P
C408
C408
SC150P
SC150P
1 2
L18IND-1D2UH L18IND-1D2UH
1 2
C407S C33P C407SC33P
1 2
1 2
TV_CRMA
12
C404
C404
SC270P5 0V
SC270P5 0V
L19IND-1D2UH L19IND-1D2UH
12
C405
C405
SC270P5 0V
SC270P5 0V
TV_LUMA
MINDIN4-29
6
GND
2
GND
4
CRMA
3
LUMA
1
GND
5
GND
C
CN5
CN5
TV_CRMA
TV_LUMA
D34 BAV 99-2D 34 BAV99-2
3
D32 BAV 99-2D 32 BAV99-2
3
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