Wistron Vegas SKL Schematic

5

D D

4

3

2

1

Vegas Schematic

C C

KBL-R

2017/11/08
REV : A00

B B

<Core Design>

<Core Design>

DY : None Installed

<Core Design>

W

W

W

istron Corporation

istron Corporation

A A

UMA: UMA only installed
OPS: DISCRTE OPTIMUS installed

5

4

3

itle

Title

Title

T

C

C

C

over Page

over Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

4

4

4

A

A

A

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Date: Sheet

Date: Sheet

Date: Sheet

2

over Page

V

V

V

egas SKL/KBL-U

egas SKL/KBL-U

egas SKL/KBL-U

istron Corporation

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2

2

2
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1 105

1 105

1 105

f

f

f

o

o

o

1

A

A

A

00

00

00

5

Project code:
PCB P/N:
Revision: X02

D D

17841-1

2GB = 256Mb x 32 x 2 PCS

RAM(GDDR5) *2

V

2GB (256Mb x 32)

1, 82

8

GDDR5

DIS only

Vegas
Turis

C C

B B

A A

Vegas
Turis

Vegas
Turis

Vegas
Turis

Vegas
Turis

Vegas
Turis

Vegas
Turis

niversal Jack

U

14"/15" LCD

15" Touch Panel

(TURIS only)

Camera

Digital MIC

RJ45 Conn.

HDMI V1.4a

VGA Conn.

USB1(USB3.0)

USB2(USB3.0)

2CH SPEAKER
(2CH 2W/4ohm)

29

55

32

56

Left side

Left side

57

36

36

MIC_IN/GND

HP_R/L

LAN 10/100

REALTEK RTL8106E

LAN 10/100/1000

REALTEK RTL8111H

DP/VGA Converter

REALTEK RTD2166

Audio Codec

ALC3246

4

egas/Turis MLK KBL-R Block Diagram

V

NEWNEW

GPU

AMD
R17M-M1-30
25W

6, 77, 78, 79, 80

7

URIS only

T

PCIE x 4

eDP x2

USB2.0 x1

USB2.0 x1

I

Kabylake-U 4+2

15W (UMA&DIS)

K

0 USB 2.0/1.1 ports

1

6

High Definition Audio

3 SATA ports
6 PCIE ports
LPC I/F
ACPI 5.0

3

ntel CPU

BL PCH-LP

USB 3.0 ports

DDR4 2400MHz Channel A

DDR4 2400MHz Channel A

USB2.0 x1

VEGAS only

PCIE x1

USB2.0 x1

2

NEW

Fingerprint

FM-03331

NGFF WLAN

802.11a/b/g/n
BT V4.0 combo

PCIE x1

31

VEGAS only

DDI1

56

VEGAS only

USB2.0 x1

USB3.0 x1

USB2.0 x1

DDI2

SATA (Gen3) x1

SATA (Gen1) x1

eSPI BUS

Kyloren

15

E

SMSC MEC1416-NU-GP

HDD

60

Vegas

ODD

Turis

60

C

USB3.0 x1

SPI

DA

H

27

Flash ROM

16MB

25

VEGAS only

TPM 2.0

NPCT650/750

Int. KB

65

91

PS2

P

I2C

DR4 2400

D

ODIMM A

S

DDR4 2400

ODIMM B

S

NEW

92

Vegas
Turis

61

Kyloren 15

eSPI debug port

FAN Control

24

Vegas
Turis

recisionTouch pad

65

1

CHARGER

SL88739

I

INPUTS

AD+

T+

B

SYSTEM DC/DC

PS51225RUKR-GP

T

INPUTS

CBATOUT

D

12

3

1

CPU Core Power

NCP81208MNTXG
NCP81382MNTXG x 2
NCP81382MNTXG (23e)
NCP81253MNTBG

INPUTS

DCBATOUT

DCBATOUT

DCBATOUT+VCCSA

DDR4 SUS

T8231AGQW-GP

R
APL5930KAI-TRG

INPUTS

DCBATOUT
3D3V_S5

CPU VCCPRIM_CORE
1V

INPUTS

D0V_S5

1

CPU DCDC-V1D00A

OZ2262QI-10-GP-U

A

DCBATOUT

LDO-V1D8V

APL5930KAI-TRG

D3V_S5

3

T

68

EOPIO/EDRAM (23e)

T

26

INPUTS

1D0V_S5
1

AO3419L

INPUTS

3

26

ISL62771HRTZ-GP-U

INPUTS

D

Y

INPUTS

DCBATOUT

OUTPUTS

DCBATOUT

OUTPUTS

D3V_PWR

3
3D3V_S5
5V_PWR
5V_S5

OUTPUTS

CC_CORE

V

+VCCGTDCBATOUT

+VCCGT (23e)

OUTPUTS

1D2V_S3
0D6V_S0
2D5V_S3

OUTPUTS

VCCPRIM_CORE

+

OUTPUTSINPUTS

1D0V_S5

OUTPUTSINPUTS

1D8V_S5

5V/3V S0

PS22966DPUR-GP

5V_S5
3D3V_S5

PS22961DNYT

D0V_S5

3D3V VGA

D3V_S0

VGA_CORE

CBATOUT

1D5V_VGA_S0

8288RAC-GP

OUTPUTSINPUTS

5V_S0
3D3V_S0

OUTPUTS

V_EDRAM_VR

+
+V_EOPIO_VR

OUTPUTS

3D3V_VGA_S0

OUTPUTS

GA_CORE

V

OUTPUTS

1D5V_VGA_S0

46~50

33

4

44

45

51

1

1

3

5

54

0

40

86

85

86

Vegas
Turis

Vegas
Turis

IO Board

USB3(USB2.0)

SD Card Slot

5

CardReader

Realtek RTS5170

<Core Design>

<Core Design>

USB2.0 x1

USB2.0 x1

4

3

2

<Core Design>

W

W

W

istron Corporation

istron Corporation

istron Corporation

2

2

2

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

B

B

B

lock Diagram

lock Diagram

lock Diagram

egas SKL/KBL-U

egas SKL/KBL-U

egas SKL/KBL-U

V

V

V

1

o

2

o

2

o

2

f

f

f

00

00

00

A

A

A

105Wednesday, November 08, 2017

105Wednesday, November 08, 2017

105Wednesday, November 08, 2017

5

Main Func = CPU

4

3

2

1

+VCCST_ CPU

SKYLAKE_ULT

CPU MISC

12

R419
1KR2J-1-G P

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

4 OF 20

JTAGX

B61
D60
A61
C60
B59

B56
D59
A56
C59
C61
A59

XDP_TCL K
XDP_TDI
XDP_TDO _CPU
XDP_TMS
XDP_TRS T#

PCH_JTA G_TCK
PCH_JTA G_TDI
PCH_JTA G_TDO
PCH_JTA G_TMS
XDP_TRS T#
XDP_TCK _JTAGX

XDP_TRS T#

12

EC401

DY

SC1KP50 V2KX-L-1-GP

XDP_TMS
XDP_TDI

XDP_TDO _CPU

PCH_JTA G_TDI

0525 Follow KY15 & SF

PCH_JTA G_TDO

PCH_JTA G_TMS

XDP_TCK _JTAGX

XDP_TRS T#

XDP_TCL K

PCH_JTA G_TCK

1 2

R421 51R2J-2-G P

DY

1 2

R422 51R2J-2-G P

DY

1 2

R423 51R2J-2-G P

DY

1 2

R408 51R2J-2-G P

1 2

R409 51R2J-2-G P

1 2

R416 51R2J-2-G P

1 2

R417 1KR2J-1-G P

DY

1 2

R402 51R2J-2-G P

DY

1 2

R406 51R2J-2-G P

1 2

R407 51R2J-2-G P

DY

#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm

D D

[PECI] and [PRO CHOT#]
Impedance contr ol: 50 ohm

H_PECI[24]

H_PROCH OT#[24,44,46]

TOUCH_P ANEL_INTR#[24,55]

INT_TP#[24,65]

C C

#544669 Rev0.52 :
Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm an d 150 ohm

+VCCSTG

+VCCSTG = 1.0 V

12

R401

Rb

1KR2J-1-G P

Ra

1 2

R403
499R2F-2 -GP

INT_TP# TOUCHPA D_INTR#

1 2

R410
0R0402-P AD

1 2

R412 49D9R2F -L1-GP

1 2

R413 49D9R2F -L1-GP

1 2

R414 49D9R2F -L1-GP

1 2

R415 49D9R2F -L1-GP

TP401TPAD14-O P-GP

TP402TPAD14-O P-GP

TP405TPAD14-O P-GP
TP406TPAD14-O P-GP
TP407TPAD14-O P-GP
TP408TPAD14-O P-GP

TP404TPAD14-O P-GP

H_CATER R#

1

H_PECI
H_PROCH OT#_RH_PROCH OT#
PCH_THE RMTRIP

1

SKTOCC#

XDP_BPM 0

1

XDP_BPM 1

1

XDP_BPM 2

1

XDP_BPM 3

1

TOUCH_P ANEL_INTR#

GPP_B4/C PU_GP3

1

CPU_POP IRCOMP
PCH_POP IRCOMP
EDRAM_O PIO_RCOMP
EOPIO_RCO MP

CPU1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U-GP

PCH_THE RMTRIP

+VCCSTG = 1.0 V

+VCCSTG

(#543016) PROCHOT# Routing Guidelines

#544669 CRB Rev 0.52

B B

M1,2,3,4,5: <3 inches
M6: 1-11 inches
MCPU: 0.3-1.5 i nches
Mt <0.3 mils
Main route(M1+M 2+M3+M4+M5+M6+ MCPU): 1-12 i nches

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(JTAG/CPU SIDE BAND)

CPU_(JTAG/CPU SIDE BAND)

CPU_(JTAG/CPU SIDE BAND)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

4 105Wednesd ay, November 08, 201 7

4 105Wednesd ay, November 08, 201 7

4 105Wednesd ay, November 08, 201 7

1

of

of

of

A00

A00

A00

5

4

3

2

1

Main Func = CPU

DDR4 ball type: Interleaved Type

D D

PU1B

C

_A_DQ0

AL71

M

_A_DQ0[12]

M

_A_DQ1[12]

M

_A_DQ2[12]

M

_A_DQ3[12]

M_A_DQ[0:7]

M_A_DQ[8:15]

M_B_DQ[0:7]

M_B_DQ[8:15]

C C

M_A_DQ[16:23]

M_A_DQ[24:31]

M_B_DQ[16:23]

M_B_DQ[24:31]

DQ Bit Swapping is allowed w ithin the same byte, and Byt e Swapping is allowed within the same channel.

B B

Clock (CLK and CLK#) and Str obe (DQS and DQS#) different ial signal swapping within a pair is not allowed. Also d ifferential
clock pair to clock pair swa pping within a channel is no t allowed.

M

_A_DQ4[12]

M

_A_DQ5[12]

M

_A_DQ6[12]

M

_A_DQ7[12]

M

_A_DQ8[12]

M

_A_DQ9[12]

M

_A_DQ10[12]

M

_A_DQ11[12]

M

_A_DQ12[12]

M

_A_DQ13[12]

M

_A_DQ14[12]

M

_A_DQ15[12]

M

_B_DQ0[13]

M

_B_DQ1[13]

M

_B_DQ2[13]

M

_B_DQ3[13]

M

_B_DQ4[13]

M

_B_DQ5[13]

M

_B_DQ6[13]

M

_B_DQ7[13]

M

_B_DQ8[13]

M

_B_DQ9[13]

M

_B_DQ10[13]

M

_B_DQ11[13]

M

_B_DQ12[13]

M

_B_DQ13[13]

M

_B_DQ14[13]

M

_B_DQ15[13]

M

_A_DQ16[12]

M

_A_DQ17[12]

M

_A_DQ18[12]

M

_A_DQ19[12]

M

_A_DQ20[12]

M

_A_DQ21[12]

M

_A_DQ22[12]

M

_A_DQ23[12]

M

_A_DQ24[12]

M

_A_DQ25[12]

M

_A_DQ26[12]

M

_A_DQ27[12]

M

_A_DQ28[12]

M

_A_DQ29[12]

M

_A_DQ30[12]

M

_A_DQ31[12]

M

_B_DQ16[13]

M

_B_DQ17[13]

M

_B_DQ18[13]

M

_B_DQ19[13]

M

_B_DQ20[13]

M

_B_DQ21[13]

M

_B_DQ22[13]

M

_B_DQ23[13]

M

_B_DQ24[13]

M

_B_DQ25[13]

M

_B_DQ26[13]

M

_B_DQ27[13]

M

_B_DQ28[13]

M

_B_DQ29[13]

M

_B_DQ30[13]

M

_B_DQ31[13]

M

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

_A_DQ1
_A_DQ2
_A_DQ3
_A_DQ4
_A_DQ5
_A_DQ6
_A_DQ7
_A_DQ8
_A_DQ9
_A_DQ10
_A_DQ11
_A_DQ12
_A_DQ13
_A_DQ14
_A_DQ15
_B_DQ0
_B_DQ1
_B_DQ2
_B_DQ3
_B_DQ4
_B_DQ5
_B_DQ6
_B_DQ7
_B_DQ8
_B_DQ9
_B_DQ10
_B_DQ11
_B_DQ12
_B_DQ13
_B_DQ14
_B_DQ15
_A_DQ16
_A_DQ17
_A_DQ18
_A_DQ19
_A_DQ20
_A_DQ21
_A_DQ22
_A_DQ23
_A_DQ24
_A_DQ25
_A_DQ26
_A_DQ27
_A_DQ28
_A_DQ29
_A_DQ30
_A_DQ31
_B_DQ16
_B_DQ17
_B_DQ18
_B_DQ19
_B_DQ20
_B_DQ21
_B_DQ22
_B_DQ23
_B_DQ24
_B_DQ25
_B_DQ26
_B_DQ27
_B_DQ28
_B_DQ29
_B_DQ30
_B_DQ31

DR0_DQ[0]

D

AL68

DR0_DQ[1]

D

AN68

DR0_DQ[2]

D

AN69

DR0_DQ[3]

D

AL70

DR0_DQ[4]

D

AL69

DR0_DQ[5]

D

AN70

DR0_DQ[6]

D

AN71

DR0_DQ[7]

D

AR70

DR0_DQ[8]

D

AR68

DR0_DQ[9]

D

AU71

DR0_DQ[10]

D

AU68

DR0_DQ[11]

D

AR71

DR0_DQ[12]

D

AR69

DR0_DQ[13]

D

AU70

DR0_DQ[14]

D

AU69

DR0_DQ[15]

D

AF65

DR1_DQ[0]/DDR0_DQ[16]

D

AF64

DR1_DQ[1]/DDR0_DQ[17]

D

AK65

DR1_DQ[2]/DDR0_DQ[18]

D

AK64

DR1_DQ[3]/DDR0_DQ[19]

D

AF66

DR1_DQ[4]/DDR0_DQ[20]

D

AF67

DR1_DQ[5]/DDR0_DQ[21]

D

AK67

DR1_DQ[6]/DDR0_DQ[22]

D

AK66

DR1_DQ[7]/DDR0_DQ[23]

D

AF70

DR1_DQ[8]/DDR0_DQ[24]

D

AF68

DR1_DQ[9]/DDR0_DQ[25]

D

AH71

DR1_DQ[10]/DDR0_DQ[26]

D

AH68

DR1_DQ[11]/DDR0_DQ[27]

D

AF71

DR1_DQ[12]/DDR0_DQ[28]

D

AF69

DR1_DQ[13]/DDR0_DQ[29]

D

AH70

DR1_DQ[14]/DDR0_DQ[30]

D

AH69

DR1_DQ[15]/DDR0_DQ[31]

D

BB65

DR0_DQ[16]/DDR0_DQ[32]

D

AW65

DR0_DQ[17]/DDR0_DQ[33]

D

AW63

DR0_DQ[18]/DDR0_DQ[34]

D

AY63

DR0_DQ[19]/DDR0_DQ[35]

D

BA65

DR0_DQ[20]/DDR0_DQ[36]

D

AY65

DR0_DQ[21]/DDR0_DQ[37]

D

BA63

DR0_DQ[22]/DDR0_DQ[38]

D

BB63

DR0_DQ[23]/DDR0_DQ[39]

D

BA61

DR0_DQ[24]/DDR0_DQ[40]

D

AW61

DR0_DQ[25]/DDR0_DQ[41]

D

BB59

DR0_DQ[26]/DDR0_DQ[42]

D

AW59

DR0_DQ[27]/DDR0_DQ[43]

D

BB61

DR0_DQ[28]/DDR0_DQ[44]

D

AY61

DR0_DQ[29]/DDR0_DQ[45]

D

BA59

DR0_DQ[30]/DDR0_DQ[46]

D

AY59

DR0_DQ[31]/DDR0_DQ[47]

D

AT66

DR1_DQ[16]/DDR0_DQ[48]

D

AU66

DR1_DQ[17]/DDR0_DQ[49]

D

AP65

DR1_DQ[18]/DDR0_DQ[50]

D

AN65

DR1_DQ[19]/DDR0_DQ[51]

D

AN66

DR1_DQ[20]/DDR0_DQ[52]

D

AP66

DR1_DQ[21]/DDR0_DQ[53]

D

AT65

DR1_DQ[22]/DDR0_DQ[54]

D

AU65

DR1_DQ[23]/DDR0_DQ[55]

D

AT61

DR1_DQ[24]/DDR0_DQ[56]

D

AU61

DR1_DQ[25]/DDR0_DQ[57]

D

AP60

DR1_DQ[26]/DDR0_DQ[58]

D

AN60

DR1_DQ[27]/DDR0_DQ[59]

D

AN61

DR1_DQ[28]/DDR0_DQ[60]

D

AP61

DR1_DQ[29]/DDR0_DQ[61]

D

AT60

DR1_DQ[30]/DDR0_DQ[62]

D

AU60

DR1_DQ[31]/DDR0_DQ[63]

D

SKYLAKE-U-GP

SKYLAKE_ULT

DR0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5]

D

DR0_DQ[16]

D

DR0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9]

D

DDR0_DQ[17]

DR0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6]

D

DDR0_DQ[18]

DR0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8]

D

DDR0_DQ[19]

DR0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7]

D

DR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_DQ[20]

D

DDR0_DQ[21]

DR0_MA[12]/DDR0_CAA[6]/DDR0_MA[ 12]

D

DDR0_DQ[22]

DR0_MA[11]/DDR0_CAA[7]/DDR0_MA[ 11]

D

DDR0_DQ[23]

DR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

D

DR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

D

DR0_MA[13]/DDR0_CAB[0]/DDR0_MA[ 13]

D

DR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

D

DR0_WE#/DDR0_CAB[2]/D DR0_MA[14]

D

DR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

D

DR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

D

DR0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]

D

DR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

D

DR0_MA[10]/DDR0_CAB[7]/DDR0_MA[ 10]

D

DR0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1]

D

DR0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0]

D

DDR CH - A

DR1_DQSN[0]/DDR0_DQSN[2]

D

DR1_DQSP[0]/DDR0_DQSP[2]

D

DR1_DQSN[1]/DDR0_DQSN[3]

D

DR1_DQSP[1]/DDR0_DQSP[3]

D

DR0_DQSN[2]/DDR0_DQSN[4]

D

DR0_DQSP[2]/DDR0_DQSP[4]

D

DR0_DQSN[3]/DDR0_DQSN[5]

D

DR0_DQSP[3]/DDR0_DQSP[5]

D

DR1_DQSN[2]/DDR0_DQSN[6]

D

DR1_DQSP[2]/DDR0_DQSP[6]

D

DR1_DQSN[3]/DDR0_DQSN[7]

D

DR1_DQSP[3]/DDR0_DQSP[7]

D

PDG: DDR/ODT

DR0_CKN[0]

D

DR0_CKP[0]

D

DR0_CKN[1]

D

DR0_CKP[1]

D

DR0_CKE[0]

D

DR0_CKE[1]

D

DR0_CKE[2]

D

DR0_CKE[3]

D

DR0_CS#[0]

D

DR0_CS#[1]

D

DR0_ODT[0]

D

DR0_ODT[1]

D

DR0_MA[3]

D

DR0_MA[4]

D

DR0_DQSN[0]

D

DR0_DQSP[0]

D

DR0_DQSN[1]

D

DR0_DQSP[1]

D

DR0_ALERT#

D

DR0_PAR

D

DR_VREF_CA

D

DR0_VREF_DQ

D

DR1_VREF_DQ

D

DR_VTT_CNTL

D

2

OF 20

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60

AW50
AT52

AY67
AY68
BA67

AW67

_A_A5

M

_A_A9

M

_A_A6

M

_A_A8

M

_A_A7

M

_A_A12

M

_A_A11

M

_A_A13

M

_A_A15

M

_A_A14

M

_A_A16

M

_A_A2

M

_A_A10

M

_A_A1

M

_A_A0

M

_A_A3

M

_A_A4

M

_A_DQS_DN0

M

_A_DQS_DP0

M

_A_DQS_DN1

M

_A_DQS_DP1

M

_B_DQS_DN0

M

_B_DQS_DP0

M

_B_DQS_DN1

M

_B_DQS_DP1

M

_A_DQS_DN2

M

_A_DQS_DP2

M

_A_DQS_DN3

M

_A_DQS_DP3

M

_B_DQS_DN2

M

_B_DQS_DP2

M

_B_DQS_DN3

M

_B_DQS_DP3

M

M_PGCNTL

S

_A_CLK#0 [12]

M

_A_CLK0 [12]

M

_A_CLK#1 [12]

M

_A_CLK1 [12]

M

_A_CKE0 [12]

M

_A_CKE1 [12]

M

_A_CS#0 [12]

M

_A_CS#1 [12]

M

_A_DIMA_ODT0 [12]

M

_A_DIMA_ODT1 [12]

M

_A_A5 [12]

M

_A_A9 [12]

M

_A_A6 [12]

M

_A_A8 [12]

M

_A_A7 [12]

M

_A_BG0 [12]

M

_A_A12 [12]

M

_A_A11 [12]

M

_A_ACT_N [12]

M

_A_BG1 [12]

M

_A_A13 [12]

M

_A_A15 [12]

M

_A_A14 [12]

M

_A_A16 [12]

M

_A_BA0 [12]

M

_A_A2 [12]

M

_A_BA1 [12]

M

_A_A10 [12]

M

_A_A1 [12]

M

_A_A0 [12]

M

_A_A3 [12]

M

_A_A4 [12]

M

M_A_DQS0

M_A_DQS1

M_B_DQS0

M_B_DQS1
M_A_DQS2

M_A_DQS3

M_B_DQS2

M_B_DQS3

_A_ALERT_N [12]

M

_A_PARITY [12]

M

_SM_VREF_CNTA [12]

V

_SM_VREF_CNTB [13]

V

M_A_DQ[32:39]

M_A_DQ[40:47]

M_B_DQ[32:39]

M_B_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_DQ[48:55]

M_B_DQ[56:63]

M_PGCNTL

S

M

_A_DQ33[12]

M

_A_DQ34[12]

M

_A_DQ35[12]

M

_A_DQ36[12]

M

_A_DQ37[12]

M

_A_DQ38[12]

M

_A_DQ39[12]

M

_A_DQ40[12]

M

_A_DQ41[12]

M

_A_DQ42[12]

M

_A_DQ43[12]

M

_A_DQ44[12]

M

_A_DQ45[12]

M

_A_DQ46[12]

M

_A_DQ47[12]

M

_B_DQ32[13]

M

_B_DQ33[13]

M

_B_DQ34[13]

M

_B_DQ35[13]

M

_B_DQ36[13]

M

_B_DQ37[13]

M

_B_DQ38[13]

M

_B_DQ39[13]

M

_B_DQ40[13]

M

_B_DQ41[13]

M

_B_DQ42[13]

M

_B_DQ43[13]

M

_B_DQ44[13]

M

_B_DQ45[13]

M

_B_DQ46[13]

M

_B_DQ47[13]

M

_A_DQ48[12]

M

_A_DQ49[12]

M

_A_DQ50[12]

M

_A_DQ51[12]

M

_A_DQ52[12]

M

_A_DQ53[12]

M

_A_DQ54[12]

M

_A_DQ55[12]

M

_A_DQ56[12]

M

_A_DQ57[12]

M

_A_DQ58[12]

M

_A_DQ59[12]

M

_A_DQ60[12]

M

_A_DQ61[12]

M

_A_DQ62[12]

M

_A_DQ63[12]

M

_B_DQ48[13]

M

_B_DQ49[13]

M

_B_DQ50[13]

M

_B_DQ51[13]

M

_B_DQ52[13]

M

_B_DQ53[13]

M

_B_DQ54[13]

M

_B_DQ55[13]

M

_B_DQ56[13]

M

_B_DQ57[13]

M

_B_DQ58[13]

M

_B_DQ59[13]

M

_B_DQ60[13]

M

_B_DQ61[13]

M

_B_DQ62[13]

M

_B_DQ63[13]

M

D3V_S5

3

12

R

DS

G

507

10KR2J-L-GP

Q

501

Q

DMN5L06K-7-GP

84.05067.031

502_G

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

_A_DQ33
_A_DQ34
_A_DQ35
_A_DQ36
_A_DQ37
_A_DQ38
_A_DQ39
_A_DQ40
_A_DQ41
_A_DQ42
_A_DQ43
_A_DQ44
_A_DQ45
_A_DQ46
_A_DQ47
_B_DQ32
_B_DQ33
_B_DQ34
_B_DQ35
_B_DQ36
_B_DQ37
_B_DQ38
_B_DQ39
_B_DQ40
_B_DQ41
_B_DQ42
_B_DQ43
_B_DQ44
_B_DQ45
_B_DQ46
_B_DQ47
_A_DQ48
_A_DQ49
_A_DQ50
_A_DQ51
_A_DQ52
_A_DQ53
_A_DQ54
_A_DQ55
_A_DQ56
_A_DQ57
_A_DQ58
_A_DQ59
_A_DQ60
_A_DQ61
_A_DQ62
_A_DQ63
_B_DQ48
_B_DQ49
_B_DQ50
_B_DQ51
_B_DQ52
_B_DQ53
_B_DQ54
_B_DQ55
_B_DQ56
_B_DQ57
_B_DQ58
_B_DQ59
_B_DQ60
_B_DQ61
_B_DQ62
_B_DQ63

_A_DQ32

M

_A_DQ32[12]

PU1C

C

AY39

DR0_DQ[32]/DDR1_DQ[0]

D

AW39

DR0_DQ[33]/DDR1_DQ[1]

D

AY37

DR0_DQ[34]/DDR1_DQ[2]

D

AW37

DR0_DQ[35]/DDR1_DQ[3]

D

BB39

DR0_DQ[36]/DDR1_DQ[4]

D

BA39

DR0_DQ[37]/DDR1_DQ[5]

D

BA37

DR0_DQ[38]/DDR1_DQ[6]

D

BB37

DR0_DQ[39]/DDR1_DQ[7]

D

AY35

DR0_DQ[40]/DDR1_DQ[8]

D

AW35

DR0_DQ[41]/DDR1_DQ[9]

D

AY33

DR0_DQ[42]/DDR1_DQ[10]

D

AW33

DR0_DQ[43]/DDR1_DQ[11]

D

BB35

DR0_DQ[44]/DDR1_DQ[12]

D

BA35

DR0_DQ[45]/DDR1_DQ[13]

D

BA33

DR0_DQ[46]/DDR1_DQ[14]

D

BB33

DR0_DQ[47]/DDR1_DQ[15]

D

AU40

DR1_DQ[32]/DDR1_DQ[16]

D

AT40

DR1_DQ[33]/DDR1_DQ[17]

D

AT37

DR1_DQ[34]/DDR1_DQ[18]

D

AU37

DR1_DQ[35]/DDR1_DQ[19]

D

AR40

DR1_DQ[36]/DDR1_DQ[20]

D

AP40

DR1_DQ[37]/DDR1_DQ[21]

D

AP37

DR1_DQ[38]/DDR1_DQ[22]

D

AR37

DR1_DQ[39]/DDR1_DQ[23]

D

AT33

DR1_DQ[40]/DDR1_DQ[24]

D

AU33

DR1_DQ[41]/DDR1_DQ[25]

D

AU30

DR1_DQ[42]/DDR1_DQ[26]

D

AT30

DR1_DQ[43]/DDR1_DQ[27]

D

AR33

DR1_DQ[44]/DDR1_DQ[28]

D

AP33

DR1_DQ[45]/DDR1_DQ[29]

D

AR30

DR1_DQ[46]/DDR1_DQ[30]

D

AP30

DR1_DQ[47]/DDR1_DQ[31]

D

AY31

DR0_DQ[48]/DDR1_DQ[32]

D

AW31

DR0_DQ[49]/DDR1_DQ[33]

D

AY29

DR0_DQ[50]/DDR1_DQ[34]

D

AW29

DR0_DQ[51]/DDR1_DQ[35]

D

BB31

DR0_DQ[52]/DDR1_DQ[36]

D

BA31

DR0_DQ[53]/DDR1_DQ[37]

D

BA29

DR0_DQ[54]/DDR1_DQ[38]

D

BB29

DR0_DQ[55]/DDR1_DQ[39]

D

AY27

DR0_DQ[56]/DDR1_DQ[40]

D

AW27

DR0_DQ[57]/DDR1_DQ[41]

D

AY25

DR0_DQ[58]/DDR1_DQ[42]

D

AW25

DR0_DQ[59]/DDR1_DQ[43]

D

BB27

DR0_DQ[60]/DDR1_DQ[44]

D

BA27

DR0_DQ[61]/DDR1_DQ[45]

D

BA25

DR0_DQ[62]/DDR1_DQ[46]

D

BB25

DR0_DQ[63]/DDR1_DQ[47]

D

AU27

DR1_DQ[48]

D

AT27

DR1_DQ[49]

D

AT25

DR1_DQ[50]

D

AU25

DR1_DQ[51]

D

AP27

DR1_DQ[52]

D

AN27

DR1_DQ[53]

D

AN25

DR1_DQ[54]

D

AP25

DR1_DQ[55]

D

AT22

DR1_DQ[56]

D

AU22

DR1_DQ[57]

D

AU21

DR1_DQ[58]

D

AT21

DR1_DQ[59]

D

AN22

DR1_DQ[60]

D

AP22

DR1_DQ[61]

D

AP21

DR1_DQ[62]

D

AN21

DR1_DQ[63]

D

SKYLAKE-U-GP

D3V_S0

3

502

Q

G

D

S

2N7002K-2-GP

84.2N702.J31

ND = 84.2N702.031

2

3rd = 84.07002.I31

???
Difference with Kyloren

12

R

506

220KR2F-L-GP

SKYLAKE_ULT

DDR CH - B

DR1_CKN[0]

D

DR1_CKN[1]

D

DR1_CKP[0]

D

DR1_CKP[1]

D

DR1_CKE[0]

D

DR1_CKE[1]

D

DR1_CKE[2]

D

DR1_CKE[3]

D

DR1_CS#[0]

D

DR1_CS#[1]

D

DR1_ODT[0]

D

DR1_ODT[1]

DR1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5]

D

DR1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9]

D

DR1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6]

D

DR1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8]

D

DR1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7]

D

DR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

D
DR1_MA[12]/DDR1_CAA[6]/DDR1_MA[ 12]

D

DR1_MA[11]/DDR1_CAA[7]/DDR1_MA[ 11]

D

DR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

D

DR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

D

DR1_MA[13]/DDR1_CAB[0]/DDR1_MA[ 13]

D

DR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

D

DR1_WE#/DDR1_CAB[2]/D DR1_MA[14]

D

DR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

D

DR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

D

DR1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]

D

DR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

D
DR1_MA[10]/DDR1_CAB[7]/DDR1_MA[ 10]

D

DR1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1]

D

DR1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0]

D

M_PGCNTL_R [51]

S

D

D
D

DR0_DQSN[4]/DDR1_DQSN[0]

D

DR0_DQSP[4]/DDR1_DQSP[0]

D

DR0_DQSN[5]/DDR1_DQSN[1]

D

DR0_DQSP[5]/DDR1_DQSP[1]

D

DR1_DQSN[4]/DDR1_DQSN[2]

D

DR1_DQSP[4]/DDR1_DQSP[2]

D

DR1_DQSN[5]/DDR1_DQSN[3]

D

DR1_DQSP[5]/DDR1_DQSP[3]

D

DR0_DQSN[6]/DDR1_DQSN[4]

D

DR0_DQSP[6]/DDR1_DQSP[4]

D

DR0_DQSN[7]/DDR1_DQSN[5]

D

DR0_DQSP[7]/DDR1_DQSP[5]

D

DR1_DQSN[6]

D

DR1_DQSP[6]

D

DR1_DQSN[7]

D

DR1_DQSP[7]

D

DR1_ALERT#

D

D

RAM_RESET#

D

DR_RCOMP[0]

D

DR_RCOMP[1]

D

DR_RCOMP[2]

D

OF 20

3

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

_B_A5

AY48

M

_B_A9

AP50

M

_B_A6

BA48

M

_B_A8

BB48

M

_B_A7

AP48

M

AP52

_B_A12

AN50

M

_B_A11

AN48

M

_B_ACT_N

AN53

M

AN52

_B_A13

BA43

M

_B_A15

M

AY43

_B_A14

M

AY44

_B_A16

M

AW44
BB44

_B_A2

M

AY47
BA44

_B_A10

M

AW46

_B_A1

M

AY46

_B_A0

M

BA46

_B_A3

M

BB46

DR1_MA[3]
DR1_MA[4]

DR1_PAR

BA47

BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

_B_A4

M

_A_DQS_DN4

M

_A_DQS_DP4

M

_A_DQS_DN5

M

_A_DQS_DP5

M

_B_DQS_DN4

M

_B_DQS_DP4

M

_B_DQS_DN5

M

_B_DQS_DP5

M

_A_DQS_DN6

M

_A_DQS_DP6

M

_A_DQS_DN7

M

_A_DQS_DP7

M

_B_DQS_DN6

M

_B_DQS_DP6

M

_B_DQS_DN7

M

_B_DQS_DP7

M

M_DRAMRST#

S

M_RCOMP_0

S

M_RCOMP_1

S

M_RCOMP_2

S

#543016

Design Guideline:
SM_RCOMP keep routing length less than 500 mils.

_B_CLK#0 [13]

M

_B_CLK#1 [13]

M

_B_CLK0 [13]

M

_B_CLK1 [13]

M

_B_CKE0 [13]

M

_B_CKE1 [13]

M

_B_CS#0 [13]

M

_B_CS#1 [13]

M

_B_DIMB_ODT0 [13]

M

_B_DIMB_ODT1 [13]

M

_B_A5 [13]

M

_B_A9 [13]

M

_B_A6 [13]

M

_B_A8 [13]

M

_B_A7 [13]

M

_B_BG0 [13]

M

_B_A12 [13]

M

_B_A11 [13]

M

_B_ACT_N [13]

M

_B_BG1 [13]

M

_B_A13 [13]

M

_B_A15 [13]

M

_B_A14 [13]

M

_B_A16 [13]

M

_B_BA0 [13]

M

_B_A2 [13]

M

_B_BA1 [13]

M

_B_A10 [13]

M

_B_A1 [13]

M

_B_A0 [13]

M

_B_A3 [13]

M

_B_A4 [13]

M

M_A_DQS4

M_A_DQS5

M_B_DQS4

M_B_DQS5

M_A_DQS6

M_A_DQS7

M_B_DQS6

M_B_DQS7

_B_ALERT_N [13]

M

_B_PARITY [13]

M

1 2

501 121R2F-GP

R

1 2

502 80D6R2F-L-GP

R

1 2

503 100R2F-L3-GP

R

Layout Note:

D2V_S3

1

12

505

R

470R2F-GP

1 2

504

R

0R0402-PAD

12

DY

D502

E

AZ5725-01FDR7G-GP

83.05725.0A0

close to CPU

DR4_DRAMRST# [12,13]

D

_A_DQS_DN[7:0] [12]

_A_DQS_DN0

M

_A_DQS_DN1

M

_A_DQS_DN2

M

_A_DQS_DN3

M

_A_DQS_DN4

M

_A_DQS_DN5

M

_A_DQS_DN6

A A

5

4

M

_A_DQS_DN7

M

_A_DQS_DP0

M

_A_DQS_DP1

M

_A_DQS_DP2

M

_A_DQS_DP3

M

_A_DQS_DP4

M

_A_DQS_DP5

M

_A_DQS_DP6

M

_A_DQS_DP7

M

M

_A_DQS_DP[7:0] [12]

M

3

_B_DQS_DN0

M

_B_DQS_DN1

M

_B_DQS_DN2

M

_B_DQS_DN3

M

_B_DQS_DN4

M

_B_DQS_DN5

M

_B_DQS_DN6

M

_B_DQS_DN7

M

_B_DQS_DP0

M

_B_DQS_DP1

M

_B_DQS_DP2

M

_B_DQS_DP3

M

_B_DQS_DP4

M

_B_DQS_DP5

M

_B_DQS_DP6

M

_B_DQS_DP7

M

_B_DQS_DN[7:0] [13]

M

_B_DQS_DP[7:0] [13]

M

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

W

1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2

2

2

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

itle

Title

Title

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

2

2

2

A

A

A

Date: Sheet

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

PU_(DDR)

PU_(DDR)

PU_(DDR)

C

C

C

egas SKL/KBL-U

egas SKL/KBL-U

egas SKL/KBL-U

V

V

V

1

00

00

00

A

A

A

f

f

f

5 105Wednesday, November 08, 2017

5 105Wednesday, November 08, 2017

5 105Wednesday, November 08, 2017

o

o

o

5

Main Func = CPU

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

1
1

1

R

1

SVD_TP_ BA70

R

1

SVD_TP_ BA68

R

1

SVD_F65

R

1

SVD_G65

C

FG0

C

FG1

C

FG2

C

FG3

C

FG4

C

FG5

C

FG6

C

FG7

C

FG8

C

FG9

C

FG10

C

FG11

C

FG12

C

FG13

C

FG14

C

FG15

C

FG16

C

FG17

C

FG18

C

FG19

C

FG_RCOM P

I

TP_PMOD E

T

P618TPAD14 -OP-GP

T

P619TPAD14 -OP-GP

T

P620TPAD14 -OP-GP

T

P621TPAD14 -OP-GP

T

P622TPAD14 -OP-GP

T

P623TPAD14 -OP-GP

T

P624TPAD14 -OP-GP

T

P625TPAD14 -OP-GP

D D

C C

PCH strap pin:

B B

C

FG3

12

R

604

1KR2J-1-G P

DY

T

P626TPAD14 -OP-GP

T

P627TPAD14 -OP-GP

T

P628TPAD14 -OP-GP

T

P629TPAD14 -OP-GP

T

P630TPAD14 -OP-GP

T

P631TPAD14 -OP-GP

T

P632TPAD14 -OP-GP

T

P633TPAD14 -OP-GP

T

P634TPAD14 -OP-GP

T

P635TPAD14 -OP-GP

T

P636TPAD14 -OP-GP

T

P637TPAD14 -OP-GP

1 2

R

601

49D9R2F -L1-GP

T

P638TPAD14 -OP-GP

T

P601TPAD14 -OP-GP

T

P602TPAD14 -OP-GP

T

P612TPAD14 -OP-GP

T

P613TPAD14 -OP-GP

[BDW Only]PHYSI CAL_DEBUG_ENAB LED (DFX PRIV ACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MS R

G69

G68

G71

G70

AY2
AY1

AL25
AL27

BA70
BA68

G65

D65
D67
E70
C68
D68
C67
F71

F70

H70

H69

E63
F63

E66
F66

E60

K46
K45

C71
B70

F60

A52

F65

F61
E61

E68
B67

J71
J68

E8

D1
D3

4

C

PU1S

C

FG[0]

C

FG[1]

C

FG[2]

C

FG[3]

C

FG[4]

C

FG[5]

C

FG[6]

C

FG[7]

C

FG[8]

C

FG[9]

C

FG[10]

C

FG[11]

C

FG[12]

C

FG[13]

C

FG[14]

C

FG[15]

C

FG[16]

C

FG[17]

C

FG[18]

C

FG[19]

C

FG_RCOMP

I

TP_PMODE

R

SVD#AY2

R

SVD#AY1

R

SVD#D1

R

SVD#D3

R

SVD#K46

R

SVD#K45

R

SVD#AL25

R

SVD#AL27

R

SVD#C71

R

SVD#B70

R

SVD#F60

R

SVD#A52

R

SVD_TP#BA70

R

SVD_TP#BA68

R

SVD#J71

R

SVD#J68

V

SS

V

SS

R

SVD#F61

R

SVD#E61

SKYLAKE-U-GP

RESERVED SIGNALS-1

SKYLAKE_ULT

R

SVD_TP_AW71

RSVD_TP_AW70

1

9 OF 20

R

SVD_TP#BB68

R

SVD_TP#BB69

R

SVD_TP#AK13

R

SVD_TP#AK12

R

SVD#BB2

R

SVD#BA3

R

SVD#D5

R

SVD#D4

R

SVD#B2

R

SVD#C2

R

SVD#B3

R

SVD#A3

R

SVD#AW1

R

SVD#E1

R

SVD#E2

R

SVD#BA4

R

SVD#BB4

R

SVD#A4

R

SVD#C4

R

SVD#A69

R

SVD#B69

R

SVD#AY3

R

SVD#D71

R

SVD#C70

R

SVD#C54

R

SVD#D54

R

SVD_TP#AW71

R

SVD_TP#AW70

P

ROC_SELECT#

3

0

607 Delete TP

BB68
BB69

AK13
AK12

BB2
BA3

AU5

T

P5

AT5

T

P6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

T

P4

A69
B69

AY3

D71
C70

C54
D54

T

AY4
BB3

AY71
AR56

AW71
AW70

AP56
C64

P1_AY4

T

P2_BB3

V

SS_AY71

Z

VM#

R

SVD_TP_ AW71

R

SVD_TP_ AW70

M

SM#

P

ROC_SEL ECT#

T

P1

T

P2

V

SS

Z

VM#

M

SM#

1

T

P610 TPAD14-OP-GP

1

T

P611 TPAD14-OP-GP

1 2

R

602 0R0402-PAD

1

T

P616 TPAD14-OP-GP

1

T

P614 TPAD14-OP-GP

1

T

P615 TPAD14-OP-GP

1

T

P617 TPAD14-OP-GP

1 2

R

603 100KR2J-1-G P

DY

2

+

VCCST_C PU

1

#54469 CRB.

0515 DY

1 : DISABLED

C

FG4

12

R

605

1KR2J-1-G P

(#543016)

DISPLAY PORT PR ESENCE STRAP

0 : ENABLED

CFG[4]

An external Dis play Port devi ce is connect ed to the Embe dded Display P ort.

1 : DISABLED (D efault)
No Physical Dis play Port atta ched to Embed ded DisplayPor t*. No connect for disable.

CFG TERMINATIONS

20140807 david

A A

SKL(#543016):
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

5

#544669 Rev0.52 (CRB)

4

<Core Design>

<Core Design>

<Core Design>

W

W

W

istron Corporation

istron Corporation

istron Corporation

2

2

2

1F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A

A

A

3

3

3

Date: Sheet

Date: Sheet

3

2

Date: Sheet

C

C

C

PU_(RESERVED)

PU_(RESERVED)

PU_(RESERVED)

V

V

V

egas SKL/KBL-U

egas SKL/KBL-U

egas SKL/KBL-U

6 105W ednesday, November 08, 2017

6 105W ednesday, November 08, 2017

6 105W ednesday, November 08, 2017

1

00

00

00

A

A

o

o

o

A

f

f

f

Main Func = CPU

5

CPU1L

VCC_CORE VCC_CORE

A30
A34
A39

A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40

VCC_CORE

+VCCGT

AM32
AM33
AM35
AM37
AM38

AK32

AB62

AC63
AE63

AE62
AG62

AL63
AJ62

G30

K32

P62

V62

H63

G61

D D

C C

VCC_SENSE[46]

VSS_SENSE[46]

VSSSA_SENSE[46]

VCCSA_SENSE[46]

VCCGT_SENSE[46]
VSSGT_SENSE[46]

20170427
FOR KBL U22 U42

+V_EDRAM_VR
3A

+V1.8S_EDRAM

Symbol error for layout NC

140mA

+V_EOPIO_VR
3A

CPU POWER 1 OF 4

VCC
VCC

SKYLAKE_ULT

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD#K32

RSVD_K32

RSVD#AK32

RSVD_AK32

VCCOPC
VCCOPC
VCCOPC

VCC_OPC_1P8

VCC_OPC_1P8

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO
VCCEOPIO

VCCEOPIO_SENSE
VSSEOPIO_SENSE

SKYLAKE-U-GP

1 2

R710 100R2F-L3-GP

1 2

R711 100R2F-L3-GP

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
impedance= 50 ohm

3. Length matc h<25mil

1 2

R712 100R2F-L3-GP

1 2

R713 100R2F-L3-GP

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
impedance= 50 ohm

3. Length matc h<25mil

12 OF 20

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG

VCC_SENSE
VSS_SENSE

VCCGT_SENSE
VSSGT_SENSE

4

20170427

For U22 & U42

1 2

DY

GT_CORE

+VCCGT

GT_CORE

+VCCGT

GT_CORE

U22_POWER_K52

+VCCGT

VCCGT_SENSE
VSSGT_SENSE

G32

VCC

G33

VCC

G35

VCC

G37

VCC

G38

VCC

G40

VCC

G42

VCC

J30

VCC

J33

VCC

J37

VCC

J40

VCC

K33

VCC

K35

VCC

K37

VCC

K38

VCC

K40

VCC

K42

VCC

K43

VCC

VCC_SENSE

E32

VSS_SENSE

E33

H_CPU_SVIDALRT#

B63

H_CPU_SVIDCLK

A63
D64

G20

H_CPU_SVIDDAT

+VCCFUSEPRG

1 2

R703
0R0402-PAD

+VCCSTG

+VCCGT

R721
0R2J-L-GP

follow INTEL suggestion

AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

A48
A53
A58
A62

A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71

J43

J45

J46

J48

J50

J52

J53

J55

J56

J58

J60

K48

K50

K52

K53

K55

K56

K58

K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62

N63

N64

N66

N67

N69

J70

J69

3

CPU1M

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKYLAKE-U-GP

CPU POWER 2 OF 4

SKYLAKE_ULT

13 OF 20

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX

VCCGTX_SENSE
VSSGTX_SENSE

+VCCGT

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

GTX_CORE

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58

GTX_CORE

AK60
AK70
AL43
AL46
AL50
AL53

GTX_CORE

AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58

For U42 only

AU63
BB57
BB66

AK62
AL61

+VDDQ_CPU_CLK

12

C722

DY

SC1U10V2KX-1GP

2

1D2V_S3

C719

SC1U10V2KX-1GP

12

DY

+VDDQ_CPU_CLK1D2V_S3

1 2

R705
0R0603-PAD

12

C715SC10U6D3V3MX-GP

DY

+VCCST_CPU

12

C716SC1U10V2KX-1GP

DY

+VCCSTG

12

C717SC1U10V2KX-1GP

DY

1D2V_S3

12

C718SCD1U16V2KX-3GP

DY

+V1.00U_CPU

0.12 A

12

C720

SCD1U16V2KX-3GP

DY

VCC_CORE GT_CORE +VCCGT

U42

1 2

R718
D0002R5J-GP-U

VCC_CORE GTX_CORE

U42

1 2

R720
D0002R5J-GP-U

0.04 A

12

C721

SCD1U16V2KX-3GP

R719
D0002R5J-GP-U

AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51

AM40

A18

A22

AL23

K20
K21

U22

1 2

CPU1N

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQC

VCCST

VCCSTG

VCCPLL_OC

VCCPLL
VCCPLL

SKYLAKE-U-GP

CPU POWER 3 OF 4

SKYLAKE_ULT

VCCSA_SENSE
VSSSA_SENSE

14 OF 20

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

1

+VCCIO(ICCMAX.=2.73A

+VCCIO

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

R716 100R2F-L3-GP
R717 100R2F-L3-GP

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
impedance= 50 ohm

3. Length matc h<25mil

AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25

???

K27
K28

20170508

K30

待確認

AM23
AM22

KYLOREN

VSSSA_SENSE

H21

VCCSA_SENSE

H20

1 2
1 2

Layout Note:

+VCCSA

+VCCSA

Layout Note:
The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).

B B

Route the Alert signal betwe en the Clock and the Data si gnals.

SVID DATA

+VCCST_CPU

CLOSE TO CPU

12

R726
100R2F-L3-GP

#544669

H_CPU_SVIDDAT

SVID CLOCK

H_CPU_SVIDCLK

A A

H_CPU_SVIDALRT#

5

R709
0R0402-PAD

1 2

1 2

R728
220R2J-L2-GP

1 2

R732

0R0402-PAD

+VCCST_CPU

+VCCST_CPU

12

12

R723

DY

54D9R2F-L1-GP

R727
56R2J-4-GP

VR_SVID_DATA [46]

#544669
CLOSE TO VR

#544669
CLOSE TO CPU

VR_SVID_ALERT# [46]

VR_SVID_CLK [46]

SVID_543016:

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A2

A2

A2

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017
Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(VCC_CORE)

CPU(VCC_CORE)

CPU(VCC_CORE)

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

1

7 105

7 105

7 105

A00

A00

A00

5

Main Func = CPU

4

3

2

1

CPU1A

HDMI_DATA2#[57]
HDMI_DATA2[57]

D D

HDMI

DP to VGA

HDMI

C C

+VCCIO

B B

HDMI_DATA1#[57]
HDMI_DATA1[57]
HDMI_DATA0#[57]
HDMI_DATA0[57]
HDMI_CLK#[57]
HDMI_CLK[57]

PCH_DPC_N0[56]
PCH_DPC_P0[56]
PCH_DPC_N1[56]
PCH_DPC_P1[56]

CPU_DP1_CTRL_CLK[57]
CPU_DP1_CTRL_DATA[57]

R801

1 2

24D9R2F-L-GP

3D3V_S0

2 3
1

2 3
1

TPAD14-OP-GP
TP802

RN801

4

SRN2K2J-1-GP

RN803

Vegas

SRN2K2J-1-GP

4

CPU_DP2_CTRL_CLK SIO_EXT_SMI#_R
CPU_DP2_CTRL_DATA

DDPD_CTRLDATA

1

EDP_COMP

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_DATA
CPU_DP2_CTRL_CLK

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

SKYLAKE-U-GP

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.

Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.

(#543016) eDP_RCOMP Guideline

Signal Trace

Width

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%

Isolation
Spacing

Resistor
Value

Length

Max = 100 mils

SKYLAKE_ULT

DDI

DISPLAY SIDEBANDS

Strap

Strap

Strap

EDP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

Strap pin:

Port B /
Port C Detected

DDPB_CTRLDATA

DDPC_CTRLDATA

1 OF 20

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN

DDI1_AUXP

DDI2_AUXN

DDI2_AUXP

RSVD#G46

RSVD#F46

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

SIO_EXT_SMI#_R

CPU_DP2_HPD

Sampled at rising edge of PCH_PW ROK

*

*

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

EDP_DISP_UTIL

B52

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

1 2

R802 10KR2J-L-GP

1 2

R806 100KR2J-1-GP

Vegas

0 = Port B is not detected.
1 = Port B is detected.

0 = Port C is not detected.
1 = Port C is detected.

eDP_TX_CPU_N0 [55]
eDP_TX_CPU_P0 [55]
eDP_TX_CPU_N1 [55]
eDP_TX_CPU_P1 [55]

eDP_AUX_CPU_N [55]
eDP_AUX_CPU_P [55]

1

TP801 TPAD14-OP-GP

PCH_DPC_AUXN [56]
PCH_DPC_AUXP [56]

CPU_DP1_HPD [57]
CPU_DP2_HPD [56]

EDP_HPD [55]

L_BKLT_EN [24]
L_BKLT_CTRL [55]
EDP_VDD_EN [55]

3D3V_S0

(#543016) DDI Disabling and Termination Guidelines

Port Strap Enable Port Disable Port

A A

Port 1

Port 2

DDPB_CTRLDATA

DDPC_CTRLDATA

5

PU to 3.3 V with 2.2-k
±5% resistor

PU to 3.3 V with 2.2-k
±5% resistor

4

NC

NC

These two signals have weak internal pull-down.

3

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU_(DISPLAY)

CPU_(DISPLAY)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

CPU_(DISPLAY)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

8 105Wednesday, November 08, 2017

8 105Wednesday, November 08, 2017

8 105Wednesday, November 08, 2017

1

A00

A00

A00

5

4

3

2

1

Main Func = CPU

VCC_COR E

D D

C C

+VCCGT

CORE

PC1002

12

12

12

U42

PC1017

PC1066

U42

PC1003

12

PC1018

12

PC1067

12

PC1001

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1016

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1040

12

U42

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

SLICED GT

PC1033

PC1032

PC1031

12

12

12

U-line 23e 28W
IccMax current- 10ms max = 34 A

PC1007

PC1006

PC1005

PC1004

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1020

PC1019

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1068

PC1097

12

12

DY

U42

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1041

PC1034

12

12

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1022

PC1021

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1099

12

U42

U-line 23e 28W
IccMax current- 10ms max[A] = 67 A

PC1043

PC1042

12

12

PC1009

PC1008

12

12

PC1024

PC1023

12

12

+VCCIO(ICCMAX.=2.73A)

PC1035

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1044

PC1069

12

12

PC1010

PC1011

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

22U 0603 x 22

PC1025

PC1026

12

12

DY

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1037

PC1036

12

12

DY

PC1070

PC1071

12

12

DY

PC1012

PC1013

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1028

PC1027

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

1D0V_S5+VCCIO

PC1038

12

SC22U6D 3V3MX-1-DL-GP
SC22U6D 3V3MX-1-DL-GP

22U 0603 x28

PC1072

PC1073

12

12

DY

PC1014

12

PC1029

12

PC1039

12

20170810
New Common Part

PC1074

12

DY

PC1015

12

PC1030

12

PC1075

12

+VCCSA

1D2V_S3

PC1055

12

12

SC10U6D 3V3MX-GP
SC10U6D 3V3MX-GP
SC10U6D 3V3MX-GP

PC1045

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

10U 0603 x 4

PC1057

PC1058

12

VCCSA

PC1047

PC1046

12

PC1048

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1059

PC1056

12

12

DY

SC4D7P5 0V2BN-GP
SC4D7P5 0V2BN-GP
SC4D7P5 0V2BN-GP
SC4D7P5 0V2BN-GP

22U 0603 x 8

PC1049

12

PC1060

12

DY

PC1050

12

PC1061

12

DY

DY

PC1051

PC1052

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1063

PC1062

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

DY

PC1054

12

DY

PC1098

12

PC1064

12

(#543016 PDG)

PC1084

12

PC1065

12

U42

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1085

PC1086

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

4

PC1087

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1088

PC1089

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1090

12

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(Power CAP1)

CPU_(Power CAP1)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

CPU_(Power CAP1)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

10 105Wedn esday, November 08, 20 17

10 105Wedn esday, November 08, 20 17

10 105Wedn esday, November 08, 20 17

1

A00

A00

A00

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

B B

PC1076

PC1077

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1092

PC1091

12

12

DY

DY

PC1078

12

PC1093

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1079

PC1080

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1094

PC1095

12

12

DY

DY

PC1081

12

PC1096

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1083

PC1082

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1053

12

U42

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

A A

5

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

5

Main Func = CPU

4

3

2

1

PCH DERIVED RAILS

1D0V_S5

D D

R1101

1 2

0R1206-PAD

1 2

R1117
0R0603-PAD-2-GP-U

+V1.00A_SIP

12

C1108
SC22U6D3V3MX-1-GP

+VCCGT+VCCPRIM_CORE

C1136

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

1U 0402 x 6

C1138

12

12

DY

DY

C1147

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1148

DY

12

12

C1150

C1149

VCCIOUNSLICED GT

+VCCIO

+VCCIO(ICCMAX.=2.73A)

C1152

C1151

12

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1154

C1153

12

12

+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)

3D3V_S5_PCH +V3.3A_SIP

C C

1D8V_S5 +V1.8A_SIP

B B

1 2

R1110
0R0603-PAD-2-GP-U

R1139

1 2

0R0603-PAD-2-GP-U

C1104

SC22U6D3V3MX-1-GP

12

C1182

SC22U6D3V3MX-1-GP

C1174

12

C1106

SC22U6D3V3MX-1-GP

12

Layout Note:

1uF:
C1174 near N15
C1180 near K15
C1173 near AF20
C1172 near N18
C1175 near AB19
22uF :
C1182 C1184 near N15
10uF:
C1176 near N15

SC1U10V2KX-1GP

12

+VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP

C1173

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1180

12

C1184

SC22U6D3V3MX-1-GP

C1172

12

SC1U10V2KX-1GP

12

C1176

SC10U6D3V3MX-GP

C1175

12

SC1U10V2KX-1GP

12

VCC_CORE

A A

1U 0402 x 5

U-line 23e 28W
IccMax current-10ms max = 34 A

C1102

C1101

12

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

5

C1103

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP

+VCCPRIM_CORE

C1117

C1116

12

12

PC1105

12

SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP

PC1106

12

+V3.3A_SIP

C1183

SC10U6D3V3MX-GP

12

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU_(Power CAP2)

CPU_(Power CAP2)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

4

3

Date: Sheet of

2

CPU_(Power CAP2)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

11 105Wednesday, November 08, 2017

11 105Wednesday, November 08, 2017

11 105Wednesday, November 08, 2017

1

A00

A00

A00

5

4

3

2

1

Main Func = DDR4 SODIMM

DM1A

M_A_A0[5]
M_A_A1[5]
M_A_A2[5]
M_A_A3[5]
M_A_A4[5]
M_A_A5[5]
M_A_A6[5]
M_A_A7[5]
M_A_A8[5]

D D

C C

1D2V_S3

1 2

R1215

DY

240R2F-1-GP

DDR4_DRAMRST#

12

ED1217

AZ5725-01FDR7G-GP

B B

M_A_A9[5]
M_A_A10[5 ]
M_A_A11[5 ]
M_A_A12[5 ]
M_A_A13[5 ]
M_A_A14[5 ]
M_A_A15[5 ]
M_A_A16[5 ]

M_A_BA0[5]
M_A_BA1[5]
M_A_BG0[5]
M_A_BG1[5]

M_A_CLK0[5]
M_A_CLK#0[5]
M_A_CLK1[5]
M_A_CLK#1[5]

M_A_CKE0[5]
M_A_CKE1[5]

M_A_CS#0[5]
M_A_CS#1[5]

M_A_DIMA_ODT0[5]
M_A_DIMA_ODT1[5]

DDR4_DRAMRST#[5,13]
M_A_ACT_N[5]
M_A_ALERT_N[5]

M_A_PARITY[5]

PCH_SMBDATA[13,18,56,65,67]
PCH_SMBCLK[13,18,56,65,67]

SA0_CHA_DIM0
SA1_CHA_DIM0
SA2_CHA_DIM0

TS#_DIMM0_1

M_VREF_CA_DIMMA

12

C1229
SCD1U16V2KX-3GP

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

WE#/A14

156

CAS#/A15

152

RAS#/A16

150

BA0

145

BA1

115

BG0

113

BG1

92

CB0/NC

91

CB1/NC

101

CB2/NC

105

CB3/NC

88

CB4/NC

87

CB5/NC

100

CB6/NC

104

CB7/NC

137

CK0_T

139

CK0_C

138

CK1_T/NF

140

CK1_C/NF

109

CKE0

110

CKE1

149

CS0#

157

CS1#

162

C0/CS2#/NC

165

C1/CS3#/NC

155

ODT0

161

ODT1

256

SA0

260

SA1

166

SA2

254

SDA

253

SCL

108

RESET#

114

ACT#

116

ALERT#

134

EVENT#/NF

143

PARITY

164

VREFCA

DDR4-260P-65-GP

062.10011.01C1

Layout note: closed to Dimm

1D2V_S3

RN1201

1

4

2 3

SRN1KJ-7-GP

A A

M_VREF_CA_DIMMA

R1206
2R2F-GP

1 2

5

12

C1222
SCD022U16V2KX-3GP

+V_VREF_PATH1

12

R1209
24D9R2F-L-GP

V_SM_VREF_CNTA [5]

1 OF 4

8

DQ0

7

DQ1

20

DQ2

21

DQ3

4

DQ4

3

DQ5

16

DQ6

17

DQ7

28

DQ8

29

DQ9

41

DQ10

42

DQ11

24

DQ12

25

DQ13

38

DQ14

37

DQ15

50

DQ16

49

DQ17

62

DQ18

63

DQ19

46

DQ20

45

DQ21

58

DQ22

59

DQ23

70

DQ24

71

DQ25

83

DQ26

84

DQ27

66

DQ28

67

DQ29

79

DQ30

80

DQ31

174

DQ32

173

DQ33

187

DQ34

186

DQ35

170

DQ36

169

DQ37

183

DQ38

182

DQ39

195

DQ40

194

DQ41

207

DQ42

208

DQ43

191

DQ44

190

DQ45

203

DQ46

204

DQ47

216

DQ48

215

DQ49

228

DQ50

229

DQ51

211

DQ52

212

DQ53

224

DQ54

225

DQ55

237

DQ56

236

DQ57

249

DQ58

250

DQ59

232

DQ60

233

DQ61

245

DQ62

246

DQ63

???跟sw

3D3V_S0

3D3V_S0

3D3V_S0

確認

1 2

R1204 10KR2F-L1-GP

DY

1 2

R1205 0R0402-PAD

1 2

R1208 10KR2F-L1-GP

DY

1 2

R1210 0R0402-PAD

1 2

R1211 10KR2F-L1-GP

DY

1 2

R1212 0R0402-PAD

4

M_A_DQ0 [ 5]
M_A_DQ1 [ 5]
M_A_DQ2 [ 5]
M_A_DQ3 [ 5]
M_A_DQ4 [ 5]
M_A_DQ5 [ 5]
M_A_DQ6 [ 5]
M_A_DQ7 [ 5]
M_A_DQ8 [ 5]
M_A_DQ9 [ 5]
M_A_DQ10 [5]
M_A_DQ11 [5]
M_A_DQ12 [5]
M_A_DQ13 [5]
M_A_DQ14 [5]
M_A_DQ15 [5]
M_A_DQ16 [5]
M_A_DQ17 [5]
M_A_DQ18 [5]
M_A_DQ19 [5]
M_A_DQ20 [5]
M_A_DQ21 [5]
M_A_DQ22 [5]
M_A_DQ23 [5]
M_A_DQ24 [5]
M_A_DQ25 [5]
M_A_DQ26 [5]
M_A_DQ27 [5]
M_A_DQ28 [5]
M_A_DQ29 [5]
M_A_DQ30 [5]
M_A_DQ31 [5]
M_A_DQ32 [5]
M_A_DQ33 [5]
M_A_DQ34 [5]
M_A_DQ35 [5]
M_A_DQ36 [5]
M_A_DQ37 [5]
M_A_DQ38 [5]
M_A_DQ39 [5]
M_A_DQ40 [5]
M_A_DQ41 [5]
M_A_DQ42 [5]
M_A_DQ43 [5]
M_A_DQ44 [5]
M_A_DQ45 [5]
M_A_DQ46 [5]
M_A_DQ47 [5]
M_A_DQ48 [5]
M_A_DQ49 [5]
M_A_DQ50 [5]
M_A_DQ51 [5]
M_A_DQ52 [5]
M_A_DQ53 [5]
M_A_DQ54 [5]
M_A_DQ55 [5]
M_A_DQ56 [5]
M_A_DQ57 [5]
M_A_DQ58 [5]
M_A_DQ59 [5]
M_A_DQ60 [5]
M_A_DQ61 [5]
M_A_DQ62 [5]
M_A_DQ63 [5]

DDR4 SWAP 0212

1D2V_S3

SA0_CHA_DIM0

SA1_CHA_DIM0

SA2_CHA_DIM0

DM1B

DDR4-260P-65-GP

DM1C

111

VDD

112

VDD

117

VDD

118

VDD

123

VDD

124

VDD

129

VDD

130

VDD

135

VDD

136

VDD

141

VDD

142

VDD

147

VDD

148

VDD

153

VDD

154

VDD

159

VDD

160

VDD

163

VDD

DDR4-260P-65-GP

1D2V_S3

M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7

2 OF 4

DQS0_C
DQS0_T
DQS1_C
DQS1_T
DQS2_C
DQS2_T
DQS3_C
DQS3_T
DQS4_C
DQS4_T
DQS5_C
DQS5_T
DQS6_C
DQS6_T
DQS7_C
DQS7_T
DQS8_C
DQS8_T

DM0#/DBI0#

DM1#/DBI#
DM2#/DBI2#
DM3#/DBI3#
DM4#/DBI4#
DM5#/DBI5#
DM6#/DBI6#
DM7#/DBI7#

DM8#/DBI#/NC

VDDSPD

C1202

12

12

DY

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

C1214

12

12

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

3 OF 4

VPP
VPP

VTT

NP1
NP2

C1203

C1215

261
262

M_A_DQS_DN0

11

M_A_DQS_DP0

13

M_A_DQS_DN1

32

M_A_DQS_DP1

34

M_A_DQS_DN2

53

M_A_DQS_DP2

55

M_A_DQS_DN3

74

M_A_DQS_DP3

76

M_A_DQS_DN4

177

M_A_DQS_DP4

179

M_A_DQS_DN5

198

M_A_DQS_DP5

200

M_A_DQS_DN6

219

M_A_DQS_DP6

221

M_A_DQS_DN7

240

M_A_DQS_DP7

242
95
97

12
33
54
75
178
199
220
241
96

255

257
259

258

261
262

NP1
NP2

C1204

12

C1216

12

3

DY

1D2V_S3

2D5V_S3

0D6V_S0

C1206

C1205

12

12

DY

SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP

C1217

C1218

12

12

DY

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

M_A_DQS_DN[7:0] [5]

12

DY

12

12

C1228

SCD1U16V2KX-3GP

C1208

12

DY

C1219

12

DY

M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7

3D3V_S0

12

DY

C1209

C1220

C1201

SC2D2U10V3KX-L-GP

UN 0225

C1210

12

C1230

C1223

12

12

DY

DY

SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP

for placement modify 2015/10/19

C1221

12

2D5V_S3

C1211

C1212

12

DY

12

12

DY

DY

SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP

M_A_DQS_DP[7:0] [5]

0D6V_S00D6V_S0

DY

SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP

C1231

C1232

12

DY

2

1
2
5
6

9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

C1224

12

DM1D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DDR4-260P-65-GP

C1227

12

DY

C1207

12

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1213

4 OF 4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

20170502 DM1

99

062.10011.00U1>

102
103

062.10011.01C1

106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

0D6V_S0

C1226

C1225

12

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDR4-SODIMM1

DDR4-SODIMM1

DDR4-SODIMM1

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

12 106

12 106

12 106

A00

A00

A00

5

Main Func = DDR4 SODIMM

DM2A

TS#_DIMM1_1

12

+V_VREF_PATH2

12

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

WE#/A14

156

CAS#/A15

152

RAS#/A16

150

BA0

145

BA1

115

BG0

113

BG1

92

CB0/NC

91

CB1/NC

101

CB2/NC

105

CB3/NC

88

CB4/NC

87

CB5/NC

100

CB6/NC

104

CB7/NC

137

CK0_T

139

CK0_C

138

CK1_T/NF

140

CK1_C/NF

109

CKE0

110

CKE1

149

CS0#

157

CS1#

162

C0/CS2#/NC

165

C1/CS3#/NC

155

ODT0

161

ODT1

256

SA0

260

SA1

166

SA2

254

SDA

253

SCL

108

RESET#

114

ACT#

116

ALERT#

134

EVENT#/NF

143

PARITY

164

VREFCA

DDR4-260P-64-GP

062.10011.01B1

V_SM_VREF_CNTB [5]

C1323
SCD022U16V2KX-3GP

R1309
24D9R2F-L-GP

M_B_A0[5]
M_B_A1[5]
M_B_A2[5]
M_B_A3[5]
M_B_A4[5]
M_B_A5[5]
M_B_A6[5]
M_B_A7[5]
M_B_A8[5]

D D

C C

1D2V_S3

1 2

R1312

DY

240R2F-1-GP

DDR4_DRAMRST#

12

ED1302

B B

Layout note: closed to Dimm

0921 Install

1D2V_S3

RN1301

1

4

2 3

SRN1KJ-7-GP

M_B_A9[5]
M_B_A10[5 ]
M_B_A11[5 ]
M_B_A12[5 ]
M_B_A13[5 ]
M_B_A14[5 ]
M_B_A15[5 ]
M_B_A16[5 ]

M_B_BA0[5]
M_B_BA1[5]
M_B_BG0[5]
M_B_BG1[5]

M_B_CLK0[5]
M_B_CLK#0[5]
M_B_CLK1[5]
M_B_CLK#1[5]

M_B_CKE0[5]
M_B_CKE1[5]

M_B_CS#0[5]
M_B_CS#1[5]

M_B_DIMB_ODT0[5]
M_B_DIMB_ODT1[5]

PCH_SMBDATA[12,1 8,56,65,67]
PCH_SMBCLK[12,18,56,65,67]

DDR4_DRAMRST#[5,12,13]
M_B_ACT_N[5]
M_B_ALERT_N[5]

M_B_PARITY[5]

AZ5725-01FDR7G-GP

M_VREF_CA_DIMMB M_B_DQS_DN3

SA0_CHB_DIM0
SA1_CHB_DIM0
SA2_CHB_DIM0

M_VREF_CA_DIMMB

12

C1301
SCD1U16V2KX-3GP

R1305

1 2

2R2F-GP

1 OF 4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

4

8
7
20
21
4
3
16
17
28
29
41
42
24
25
38
37
50
49
62
63
46
45
58
59
70
71
83
84
66
67
79
80
174
173
187
186
170
169
183
182
195
194
207
208
191
190
203
204
216
215
228
229
211
212
224
225
237
236
249
250
232
233
245
246

跟sw確認

3D3V_S0

R1302 10KR2F-L1-GP

R1303 0R0402-PAD

3D3V_S0

R1306 10KR2F-L1-GP

R1307 0R2J-L-GP

3D3V_S0

R1310 10KR2F-L1-GP

R1311 0R0402-PAD

M_B_DQ8 [5]

M_B_DQ9 [5]
M_B_DQ10 [5]
M_B_DQ11 [5]
M_B_DQ12 [5]
M_B_DQ13 [5]
M_B_DQ14 [5]
M_B_DQ15 [5]

M_B_DQ0 [5]

M_B_DQ1 [5]

M_B_DQ2 [5]

M_B_DQ3 [5]

M_B_DQ4 [5]

M_B_DQ5 [5]

M_B_DQ6 [5]

M_B_DQ7 [5]
M_B_DQ16 [5]
M_B_DQ17 [5]
M_B_DQ18 [5]
M_B_DQ19 [5]
M_B_DQ20 [5]
M_B_DQ21 [5]
M_B_DQ22 [5]
M_B_DQ23 [5]
M_B_DQ24 [5]
M_B_DQ25 [5]
M_B_DQ26 [5]
M_B_DQ27 [5]
M_B_DQ28 [5]
M_B_DQ29 [5]
M_B_DQ30 [5]
M_B_DQ31 [5]
M_B_DQ32 [5]
M_B_DQ33 [5]
M_B_DQ34 [5]
M_B_DQ35 [5]
M_B_DQ36 [5]
M_B_DQ37 [5]
M_B_DQ38 [5]
M_B_DQ39 [5]
M_B_DQ40 [5]
M_B_DQ41 [5]
M_B_DQ42 [5]
M_B_DQ43 [5]
M_B_DQ44 [5]
M_B_DQ45 [5]
M_B_DQ46 [5]
M_B_DQ47 [5]
M_B_DQ48 [5]
M_B_DQ49 [5]
M_B_DQ50 [5]
M_B_DQ51 [5]
M_B_DQ52 [5]
M_B_DQ53 [5]
M_B_DQ54 [5]
M_B_DQ55 [5]
M_B_DQ56 [5]
M_B_DQ57 [5]
M_B_DQ58 [5]
M_B_DQ59 [5]
M_B_DQ60 [5]
M_B_DQ61 [5]
M_B_DQ62 [5]
M_B_DQ63 [5]

DDR4 SWAP 0212

1 2

DY

1 2

1 2

1 2

DY

1 2

DY

1 2

1D2V_S3

111
112
117
118
123
124
129
130
135
136
141
142
147
148
153
154
159
160
163

DM2B

DDR4-260P-64-GP

SA0_CHB_DIM0

SA1_CHB_DIM0

SA2_CHB_DIM0

DM2C

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DDR4-260P-64-GP

2 OF 4

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

DQS4_C

DQS4_T

DQS5_C

DQS5_T

DQS6_C

DQS6_T

DQS7_C

DQS7_T

DQS8_C

DQS8_T

DM0#/DBI0#

DM1#/DBI#
DM2#/DBI2#
DM3#/DBI3#
DM4#/DBI4#
DM5#/DBI5#
DM6#/DBI6#
DM7#/DBI7#

DM8#/DBI#/NC

3 OF 4

VDDSPD

11
13
32
34
53
55
74
76
177
179
198
200
219
221
240
242
95
97

12
33
54
75
178
199
220
241
96

1D2V_S3

255

257

VPP

259

VPP

258

VTT

261

261

262

262

NP1

NP1

NP2

NP2

M_B_DQS_DN1
M_B_DQS_DP1
M_B_DQS_DN0
M_B_DQS_DP0
M_B_DQS_DN2
M_B_DQS_DP2
M_B_DQS_DN3
M_B_DQS_DP3
M_B_DQS_DN4
M_B_DQS_DP4
M_B_DQS_DN5
M_B_DQS_DP5
M_B_DQS_DN6
M_B_DQS_DP6
M_B_DQS_DN7
M_B_DQS_DP7

DY

12

DY

3

C1303

12

12

DY

SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP

C1315

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

1D2V_S3

C1304

C1316

2D5V_S3

0D6V_S0

12

12

C1305

C1317

C1329

SC2D2U10V3KX-L-GP

12

DY

M_B_DQS_DN1 [5]
M_B_DQS_DP1 [5]
M_B_DQS_DN0 [5]
M_B_DQS_DP0 [5]
M_B_DQS_DN2 [5]
M_B_DQS_DP2 [5]
M_B_DQS_DN3 [5]
M_B_DQS_DP3 [5]
M_B_DQS_DN4 [5]
M_B_DQS_DP4 [5]
M_B_DQS_DN5 [5]
M_B_DQS_DP5 [5]
M_B_DQS_DN6 [5]
M_B_DQS_DP6 [5]
M_B_DQS_DN7 [5]
M_B_DQS_DP7 [5]

C1306

12

12

DY

C1318

12

12

DY

3D3V_S0

C1328

SCD1U16V2KX-3GP

12

DY

C1307

C1308

12

DY

SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP

C1320

C1319

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

2

1

20170502 DM1

062.10011.00T1>

DM2D

1
2
5
6

9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

DDR4-260P-64-GP

C1325

SC10U6D3V3MX-GP

C1324

SC10U6D3V3MX-GP

12

12

C1310

C1309

12

12

DY

UN 0225

M_B_DQS_DN0
M_B_DQS_DN1

C1321

C1322

12

12

DY

M_B_DQS_DN2

M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7

M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C1326

C1327

12

M_B_DQS_DN[7:0] [5]

M_B_DQS_DP[7:0] [5]

4 OF 4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

2D5V_S30D6V_S0 0D6V_S0 0D6 V_S0

C1311

12

12

DY

DY

SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP

062.10011.01B1

C1331

C1312

C1330

12

12

DY

DY

C1313

12

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1314

A A

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

DDR4-SODIMM1

DDR4-SODIMM1

DDR4-SODIMM1

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

13 106

13 106

13 106

A00

A00

A00

5

Main Func = PCH

4

3

2

1

CPU1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

D D

C C

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U-GP

WIFI_RF_ EN[61]

SKYLAKE_ULT

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F12/EMMC_CMD

GPP_F: VCCPGPPF = 1.8V Only

9 OF 20

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

GPP_F22/EMMC_CLK

EMMC_RCOMP

C37
D37
C32
D32
C29
D29

DC resistance < 0.5ohm.

B26
A26

CSI2_COMP

E13

WIFI_RF_ EN

B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

EMMC_RC OMP

AT1

WIFI_RF_ EN

1 2

R1501 100R2F-L 3-GP

EMMC_D0 [63 ]
EMMC_D1 [63 ]
EMMC_D2 [63 ]
EMMC_D3 [63 ]
EMMC_D4 [63 ]
EMMC_D5 [63 ]
EMMC_D6 [63 ]
EMMC_D7 [63 ]

EMMC_RC LK [63 ]
EMMC_CL K [63]
EMMC_CM D [63]

1 2

R1502 200R2F-L -GP

R1503
10KR2J-L -GP

3D3V_S0

1 2

DY

[#545659 Rev0.7 ]

B B

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(CS-2/EMMC)

CPU_(CS-2/EMMC)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU_(CS-2/EMMC)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

15 105Wedn esday, November 08, 20 17

15 105Wedn esday, November 08, 20 17

15 105Wedn esday, November 08, 20 17

1

A00

A00

A00

Main Func = PCH

5

4

3

2

1

#543016:
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2.

PEG_RX_CPU_N0[76]
PEG_RX_CPU_P0[76]

0516 Swap

GPU

LAN

WLAN

HDD1

ODD

PEG_TX_GPU_N0[76]
PEG_TX_GPU_P0[76]

PEG_RX_CPU_N1[76]
PEG_RX_CPU_P1[76]
PEG_TX_GPU_N1[76]
PEG_TX_GPU_P1[76]

PEG_RX_CPU_N2[76]
PEG_RX_CPU_P2[76]
PEG_TX_GPU_N2[76]
PEG_TX_GPU_P2[76]

PEG_RX_CPU_N3[76]
PEG_RX_CPU_P3[76]
PEG_TX_GPU_N3[76]
PEG_TX_GPU_P3[76]

PCIE_RX_CPU_N5[31]
PCIE_RX_CPU_P5[31]
PCIE_TX_CON_N5[31]
PCIE_TX_CON_P5[31]

PCIE_RX_CPU_N6[61]
PCIE_RX_CPU_P6[61]
PCIE_TX_CON_N6[61]
PCIE_TX_CON_P6[61]

SATA_RX_CPU_N0[60]
SATA_RX_CPU_P0[60]
SATA_TX_CPU_N0[60]
SATA_TX_CPU_P0[60]

SATA_RX_CPU_N1[60]
SATA_RX_CPU_P1[60]
SATA_TX_CPU_N1[60]
SATA_TX_CPU_P1[60]

0620 Connect to TPM

PIRQA#[91]

D D

C C

C1606 SCD22U10V2KX-L1-GP
C1605 SCD22U10V2KX-L1-GP

C1608 SCD22U10V2KX-L1-GP
C1607 SCD22U10V2KX-L1-GP

C1610 SCD22U10V2KX-L1-GP
C1609 SCD22U10V2KX-L1-GP

C1612 SCD22U10V2KX-L1-GP
C1611 SCD22U10V2KX-L1-GP

C1601 SCD1U16V2KX-3GP
C1602 SCD1U16V2KX-3GP

C1603 SCD1U16V2KX-3GP
C1604 SCD1U16V2KX-3GP

+V1.8A_SIP

12

R1607
10KR2J-L-GP

1 2

OPS

1 2

OPS

1 2

OPS

1 2

OPS

1 2

OPS

1 2

1 2

OPS

1 2

OPS

1 2
1 2

1 2
1 2

OPS

0511 Remove SSD

1 2

R1604
100R2F-L3-GP

1
1

TP1601TPAD14-OP-GP
TP1602TPAD14-OP-GP

0511 Remove SSD

Layout Note:

1. Trace Width: 4 mils min (b reakout) 12-15 mils (trace)
Note: Must maintain low DC re sistance routing (<0.1 ohm) .

2. Isolation Spacing: At leas t 12 mils to any adjacent
high speed I/O.

PCIE Table

Port

Device

Share BUS

USB3.0_3

N/A

1

2

3

B B

4

5(L0~L3)

6(L3)

6(L2)

6(L0~L1)

USB3.0_4

N/A

WLAN

LAN

GPU

HDD

SATA0

ODD SATA1

N/A

PEG_TX_CPU_N0
PEG_TX_CPU_P0

PEG_TX_CPU_N1
PEG_TX_CPU_P1

PEG_TX_CPU_N2
PEG_TX_CPU_P2

PEG_TX_CPU_N3
PEG_TX_CPU_P3

PCIE_TX_CPU_N5
PCIE_TX_CPU_P5

PCIE_TX_CPU_N6
PCIE_TX_CPU_P6

PCIE_RCOMPN
PCIE_RCOMPP

XDP_PRDY#
XDP_PREQ#
PIRQA#

CPU1H

PCIE/USB3/SATA

H13

PCIE1_ RXN/USB3_ 5_RXN

G13

PCIE1_ RXP/USB3 _5_RX P

B17

PCIE1_ TXN/USB3_ 5_TXN

A17

PCIE1_ TXP/USB3 _5_TX P

G11

PCIE2_ RXN/USB3_ 6_RXN

F11

PCIE2_ RXP/USB3 _6_RX P

D16

PCIE2_ TXN/USB3_ 6_TXN

C16

PCIE2_ TXP/USB3 _6_TX P

H16

PCIE3_ RXN

G16

PCIE3_ RXP

D17

PCIE3_ TXN

C17

PCIE3_ TXP

G15

PCIE4_ RXN

F15

PCIE4_ RXP

B19

PCIE4_ TXN

A19

PCIE4_ TXP

F16

PCIE5_ RXN

E16

PCIE5_ RXP

C19

PCIE5_ TXN

D19

PCIE5_ TXP

G18

PCIE6_ RXN

F18

PCIE6_ RXP

D20

PCIE6_ TXN

C20

PCIE6_ TXP

F20

PCIE7_ RXN/SATA 0_RXN

E20

PCIE7_ RXP/SAT A0_RX P

B21

PCIE7_ TXN/SATA 0_TXN

A21

PCIE7_ TXP/SAT A0_TX P

G21

PCIE8_ RXN/SATA 1A_RX N

F21

PCIE8_ RXP/SAT A1A_R XP

D21

PCIE8_ TXN/SATA 1A_TX N

C21

PCIE8_ TXP/SAT A1A_T XP

E22

PCIE9_ RXN

E23

PCIE9_ RXP

B23

PCIE9_ TXN

A23

PCIE9_ TXP

F25

PCIE10 _RXN

E25

PCIE10 _RXP

D23

PCIE10 _TXN

C23

PCIE10 _TXP

F5

PCIE_R COMPN

E5

PCIE_R COMPP

D56

PROC_P RDY#

D61

PROC_P REQ#

BB11

GPP_A7 /PIRQA#

E28

PCIE11 _RXN/SAT A1B_R XN

E27

PCIE11 _RXP/SA TA1B_ RXP

D24

PCIE11 _TXN/SAT A1B_T XN

C24

PCIE11 _TXP/SA TA1B_ TXP

E30

PCIE12 _RXN/SAT A2_RX N

F30

PCIE12 _RXP/SA TA2_R XP

A25

PCIE12 _TXN/SAT A2_TX N

B25

PCIE12 _TXP/SA TA2_T XP

SKYLAKE-U-GP

USB 2.0 Table

Pair

Device

USB3.0 port1

0

USB3.0 Port2

1

USB2.0 Port3 (IOBD)

2

Finger Print

3

CAMERA

4

Card Reader

5

Touch Panel

6

WLAN

7

SKYLAKE_ULT

SSIC / USB3

USB3_2_ RXN/SSIC _RXN
USB3_2_ RXP/SSI C_RXP
USB3_2_ TXN/SSIC _TXN
USB3_2_ TXP/SSI C_TXP

USB2

USB2_VB USSENSE

GPP_E9 /USB2_OC 0#
GPP_E1 0/USB2_O C1#
GPP_E1 1/USB2_O C2#
GPP_E1 2/USB2_O C3#

GPP_E4 /DEVSLP 0
GPP_E5 /DEVSLP 1
GPP_E6 /DEVSLP 2

GPP_E0 /SATAXP CIE0/S ATAGP 0
GPP_E1 /SATAXP CIE1/S ATAGP 1
GPP_E2 /SATAXP CIE2/S ATAGP 2

GPP_E8 /SATALE D#

8 OF 20

H8

USB3_1_ RXN

G8

USB3_1_ RXP

C13

USB3_1_ TXN

D13

USB3_1_ TXP

J6
H6
B13
A13

J10

USB3_3_ RXN

H10

USB3_3_ RXP

B15

USB3_3_ TXN

A15

USB3_3_ TXP

E10

USB3_4_ RXN

F10

USB3_4_ RXP

C15

USB3_4_ TXN

D15

USB3_4_ TXP

AB9

USB2N_1

AB10

USB2P_1

AD6

USB2N_2

AD7

USB2P_2

AH3

USB2N_3

AJ3

USB2P_3

AD9

USB2N_4

AD10

USB2P_4

AJ1

USB2N_5

AJ2

USB2P_5

AF6

USB2N_6

AF7

USB2P_6

AH1

USB2N_7

AH2

USB2P_7

AF8

USB2N_8

AF9

USB2P_8

AG1

USB2N_9

AG2

USB2P_9

AH7

USB2N_10

AH8

USB2P_1 0

AB6

USBCOMP

USB2_CO MP

USB2_ID

AG3

USB2_ID

USB2_VBUSSENSE

AG4

A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9

J1

SIO_EXT_SCI#

J2
J3

GPP_E0/SATAXPCIE0/SATAGP0

H2
H3
G4

H1

(#543016) Unused SATAGP[2:0]/ GPP_E[2:0] pins must be ter minated to either 3.3 V rail or GND
using 8.2 KΩ to 10 KΩ on the motherboard.
Do not use both pull-up and p ull-down. Either pull-up or pull-down is acceptable.

USB30_RX_CPU_N1 [36]
USB30_RX_CPU_P1 [36]
USB30_TX_CPU_N1 [36]
USB30_TX_CPU_P1 [36]

USB30_RX_CPU_N2 [36]
USB30_RX_CPU_P2 [36]
USB30_TX_CPU_N2 [36]
USB30_TX_CPU_P2 [36]

USB_CPU_PN0 [36]
USB_CPU_PP0 [36]

USB_CPU_PN1 [36]
USB_CPU_PP1 [36]

USB_CPU_PN2 [37]
USB_CPU_PP2 [37]

USB_CPU_PN4 [55]
USB_CPU_PP4 [55]

USB_CPU_PN5 [33]
USB_CPU_PP5 [33]

USB_CPU_PN6 [61]
USB_CPU_PP6 [61]

USB_CPU_PN7 [55]
USB_CPU_PP7 [55]

USB_CPU_PN8 [92]
USB_CPU_PP8 [92]

DC resistance < 0.5ohm.

1 2

R1603 113R2F-GP

1 2

R1601 0R0402-PAD

1 2

R1602 0R0402-PAD

USB_OC0# [35]

USB_OC2# [35]

HDD_DEVSLP [60]

1

USB1 (USB3.0 Port1)

USB2 (USB3.0 Port2)

USB1 (USB3.0 port1)

USB2 (USB3.0 Port2)

USB3 (IO BD/USB2.0 Port3)

CAMERA (USB2.0 Port5)

Card Reader (USB2.0 Port6)

WLAN (USB2.0 Port7)

Touch Screen (USB2.0 Port8)

Finger Print (USB2.0 Port9)

TP1603 TPAD14-OP-GP

SATA_ODD_PRSNT# [60]

SATA_LED#_R [64]

SATA_ODD_PRSNT#

R1608
10KR2J-L-GP

(#543016) When used as DEVSLP , no external pull-up or pu ll-down
termination required from SAT A Host DEVSLP.

1 2

(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.

Unused SATA[3:0]GP pins must be terminated to either

3.3V rail or GND using 8.2K to 10K on the
motherboard. Either pull-up or pull-down is acceptable.

3D3V_S0

USB_OC2#
USB_OC3#
USB_OC0#
USB_OC1#

8
7

RN802

SRN10KJ-6-GP

3D3V_S5_PCH

1
2
3456

SATA_LED#_R

(#543611)
The SATALED# signal is open-c ollector and requires a wea k external pull-up (8.2 kΩ t o 10 kΩ) to Vcc3_3.

R1606
10KR2J-L-GP

1 2

3D3V_S0

SIO_EXT_SCI#

R1610
10KR2J-L-GP

3D3V_S0

1 2

#545659 (SKL_PCH_U_Y_EDS Rev0 .7)

A A

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A1

A1

A1

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(PCIE/SATA/USB)

CPU_(PCIE/SATA/USB)

CPU_(PCIE/SATA/USB)

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

16 105Wednesday, November 08, 2017

16 105Wednesday, November 08, 2017

16 105Wednesday, November 08, 2017

A00

A00

A00

5

Main Func = PCH

3D3V_S5

RN1704

1
2
3
4 5

SRN10KJ -6-GP

D D

BATLOW#:
Pull-up required even if not implemented.

R1711
0R0603-P AD-2-GP-U

Layout note: 3 PAD SHARING

RTC_AUX _S5

R1730 330KR2J -L1-GP

3D3V_S5 _PCH

R1731 20KR2J-L 2-GP

RN1701

1
2 3

C C

SRN10KJ -5-GP

1 2

R1717

DY

10KR2J-L -GP

AC_PRES ENT

8

PCH_W AKE#

7

PCH_BAT LOW#

6

GPD11/LA NPHYPC

GPD11 pull high
by Intel PDG1.3 request

+VCCPDS W_3P33D3V_S5

1 2

#544669 (CRB): 330k.

1 2

0516 Follow Taos DY

1 2

DY

PM_PCH_ PWROK

4

PM_RSMR ST#

SYS_PW ROK

SM_INTRUD ER#

EXT_PW R_GATE#

H_VCCST _PWRGD_R

+VCCPDS W_3P3

LANW AKE#[24]

(PDG#543016)
WAKE#: Ensure t hat WAKE# sign al Trise (Max imum) is <100 ns.

4

+V3.3A_S IP

12

1 2

R1720 10KR2J-L -GP

DY

1 2

R1734 60D4R2F -GP

1 2

R1706 0R0402-P AD

1 2

R1704 0R0402-P AD

DY for OBFF dis able

1 2

R1707 10KR2J-L -GP

1 2

R1710 0R0402-P AD

R1701
10KR2J-L -GP

PCH_PLT RST#
XDP_DBR ESET#
PM_RSMR ST#

H_CPUPW RGD
H_VCCST _PWRGD

SYS_PW ROKSYS_PW ROK
PM_PCH_ PWROKRESET_O UT#
PCH_DPW ROKPM_RSMR ST#

ME_SUS_PW R_ACK_R

SUSACK# _R

PCH_W AKE#
GPD2/LAN _WAKE#
GPD11/LA NPHYPC

3

CPU1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD#AT15

SKYLAKE-U-GP

071.SKYLA.000U

SYSTEM POWER MANAGEMENT

2

11 OF 20

SIO_SLP_S 0#

SLP_SUS#
SLP_LAN#

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

SIO_SLP_S 3#
SIO_SLP_S 4#
SIO_SLP_S 5#

SLP_SUS #
SLP_LAN #
GPD9/SLP _WLAN#
SIO_SLP_A #

SIO_PW RBTN#
AC_PRES ENT
PCH_BAT LOW#

PME#
SM_INTRUD ER#

EXT_PW R_GATE#

PLT_RST #[31,55,61,63,76,91]

SKYLAKE_ULT

[#543016 Rev0.7]
EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k
pull-down that is active during the early portion of the power up sequence

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

1

1

1
1
1
1

1

R1715

100KR2J -1-GP

TP1701 TPAD 14-OP-GP

SIO_SLP_S 3# [2 4,27,40,51]
SIO_SLP_S 4# [4 0,44,51]

TP1703 TPAD 14-OP-GP
TP1702 TPAD 14-OP-GP
TP1704 TPAD 14-OP-GP
TP1705 TPAD 14-OP-GP
TP1706 TPAD 14-OP-GP

SIO_PW RBTN# [24]

TP1707
TPAD14-O P-GP

1 2

R1713
0R0402-P AD

12

12

C1701

DY

DY

SC220P5 0V2KX-3GP

12

EC1707

DY

SCD1U16 V2KX-3GP

1

PCH_PLT RST#

+VCCMPHYGTAON_1P0

R1719
47KR2F-G P

PCH_RSM RST# [24]

+VCCSTG

12

R1722

DY

100KR2J -1-GP

12

EC1708

DY

SCD01U5 0V2KX-L-GP

H_VCCST _PWRGD_R

EC1706

SC1KP50V2KX-L-1-GP

12

DY

DY

3D3V_AU X_S5

NON DS3

1 2

R1737
100KR2J -1-GP

XDP_DBR ESET#
SYS_PW ROK
PLT_RST #
RESET_O UT#

EC1703

EC1702

12

SC1KP50V2KX-L-1-GP

SC1KP50V2KX-L-1-GP

DY

12

12

3V_5V_P OK

EU1701

AZ5325-01FDR7G-GP

12

DY

EC1705

PM_RSMR ST#_M

SC1KP50V2KX-L-1-GP

Q1702

S

G

D S

0516 Follow Taos DY

+V1.8A_S IP

34

2

5

NON DS3

1

6

2N7002K DW-GP

84.2N702.A3F

2nd = 84.2 N702.E3F

3rd = 75.00 601.07C

12

R1718

DY

10KR2J-L -GP

1 2

R1708
0R0402-P AD

+VCCMPH YGTAON_1P0_LS_ SIP1D0V_S5

1 2

R1724
0R0805-P AD-2-GP-U

1 2

R1735
0R0805-P AD-2-GP-U

3D3V_AU X_S5

B B

12

R1726
10KR2J-L -GP

3V_5V_P OK#

NON DS3

1 2

R1727
100KR2J -1-GP

4 3

S

G

6

D

Q1701

S2

G2

D1

PJT138K A-GP

075.00138.0A7C

(ICCMAX.=3.5A)

12

C1704
SC10U6D 3V3MX-GP

D

D2

25

G

G1

1

S

S1

PM_RSMR ST#

3V_5V_P OK_C

ALL_SYS_P WRGD[24,4 0]

1 2

R1702 1KR2J-1-G P

1 2

R1728 0R0402-P AD

PCH_RSM RST#

3V_5V_P OK [21,40,45 ,53,54]

R1716
100KR2F -L3-GP

12

EC1709

DY

SCD1U16 V2KX-3GP

1 2

12

EC1712

DY

SCD1U16 V2KX-3GP

12

83.R2004.G8F

D

G

D1702

KA

RB751V-4 0H-GP

ME_SUS_ PWR_ACK_ R

SUSACK# _R

ACOK_IN [24,44]

AC_PRES ENT

PM_RSMR ST#

SYS_PW ROK[24]
RESET_O UT#[24,26,79]

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(POWER MANAGEMENT)

CPU_(POWER MANAGEMENT)

CPU_(POWER MANAGEMENT)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

17 105Wedn esday, November 08, 20 17

17 105Wedn esday, November 08, 20 17

17 105Wedn esday, November 08, 20 17

1

A00

A00

A00

5

Main Func = PCH

PCH strap pin:

eSPI or LPC

3D3V_S5_PCH

0511 Follow KY15.

D D

+V1.8A_SIP

R1835 and R1834 merge to RN1802
Follow Starlord

1 2

R1827
1KR2J-1-GP

1 2

R1828
1KR2J-1-GP

1 2

R1816
10KR2J-L-GP

SPI_HOLD_ROM

SPI_WP_ROM

SIO_RCIN#

SML0ALERT# /
GPP_C5

This signal has a weak interna l pull-down.

4

Sampled at rising edge o f RSMRST#

This signal has a weak interna l pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.

GPP_C5/SML0ALERT#

3

PCH Prim

3D3V_S5_PCH 3D3V_S5_PCH

12

R1822
1KR2J-1-GP

12

R1823

DY

1KR2J-1-GP

PCH strap pin:

BOOT HALT

SPI0_MOSI

This signal has a weak interna l pull-up.

0 = ENABLED
1 = DISABLED
WEAK INTERNAL PU

SPI_SI_CPU

PCH Prim

12

DY

12

DY

R1824
1KR2J-1-GP

R1825
1KR2J-1-GP

2

2nd = 84.2N702.E3F

3rd = 75.00601.07C

MEM_SMBDATA

84.2N702.A3F

MEM_SMBCLK

3D3V_S0

Q1801

6

5

2N7002KDW-GP

1

1 2

R1834 10KR2J-L-GP

1 2

R1835 10KR2J-L-GP

1

2

34

PCH_SMBDATA [12,13,56,65,67]

PCH_SMBCLK [12,13,56,65,67 ]

3D3V_S0

SML1_SMBDATA
SML1_SMBCLK
SML0_SMBDATA

CPU1E

Resister value will check later

1 2

SPI_CLK_ROM[25,91]

SPI_SO_ROM[25,91]

SPI_SI_ROM[25,91 ]
SPI_WP_ROM[25 ]
SPI_HOLD_ROM[25]

SPI_CS_ROM_N0[25]

SPI_CS_ROM_N2[91]

0511 Follow KY15.

HDD_FALL_INT[67]

ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3

CLKREQ_PCIE#5
CLKREQ_PEG#0
CLKREQ_PCIE#1
CLKREQ_PCIE#2

CLKREQ_PCIE#3
CLKREQ_PCIE#4

EC1808

SCD1U16V2KX-3GP

12

DY

5

DVT1 add FFS 2/18

12

R1817

10KR2J-L-GP

CL_CLK[61]
CL_DATA[61]
CL_RST#[61]

Q1901

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

C C

ESPI_IO[3..0][24]

B B

A A

3D3V_S0

eSPI

ESPI_IO[3..0]

ESPI_CS#[24]

ESPI_RESET#[24]

ESPI_ALERT#[24]

ESPI_CLK[24]

RN1812

1
2
3
4 5

SRN10KJ-6-GP

RN1813

1
2 3

SRN10KJ-5-GP

RTCRST_ON[21,24]

8
7
6

4

R1806 0R0402-PAD

1 2

R1807 0R0402-PAD

1 2

R1808 0R0402-PAD

1 2

R1809 0R0402-PAD

1 2

R1811 0R0402-PAD

1 2

R1812 0R0402-PAD

1 2

R1814 0R0402-PAD

DY

PEG_CLK_CPU#[76]
PEG_CLK_CPU[76]

GPU

CLKREQ_PEG#0[79]

PEG_CLK1_CPU#[61]
PEG_CLK1_CPU[61]

WLAN

CLKREQ_PCIE#1[61]

PEG_CLK2_CPU#[31]
PEG_CLK2_CPU[31]

LAN

CLKREQ_PCIE#2[31]

RTC_AUX_S5

RN1901

1
2 3

SRN20KJ-1-GP

D

12

C1901
SC1U10V2KX-1GP

TP1803TPAD14-OP-GP
TP1804TPAD14-OP-GP
TP1805TPAD14-OP-GP
TP1806TPAD14-OP-GP

12

SPI_CLK_CPU
SPI_SO_CPU
SPI_SI_CPU
SPI_WP_CPU
SPI_HOLD_CPU
SPI_CS_CPU_N0

SPI_CS_CPU_N2

CPU_D3_TP

1

CPU_D4_TP

1

CPU_D5_TP

1

CPU_D6_TP

1

???
PH only?

EC1805

SCD1U16V2KX-3GP

SIO_RCIN#

ESPI_ALERT#

0511 Remove SSD

4

21

G1901
GAP-OPEN

(#514849)

Layout: Place at the open door area.

0620 NC

CLKREQ_PEG#0

CLKREQ_PCIE#1

CLKREQ_PCIE#3

CLKREQ_PCIE#4

CLKREQ_PCIE#5

12

C1902
SC1U10V2KX-1GP

4

AW3

AW2

AW13

AY11

DY

AV2

AV3

AU4
AU3
AU2
AU1

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKYLAKE-U-GP

CPU1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U-GP

12

DY

12

EC1807
SCD1U16V2KX-3GP

SPI - FLASH

Strap

SPI - TOUCH

C LINK

RCIN#:
Frequency to Avoid: 33 MHz

SRTC_RST#

EC1806
SCD1U16V2KX-3GP

RTC_RST#

CLOCK SIGNALS

SKYLAKE_ULT

SKYLAKE_ULT

LPC

SMBUS, SMLINK

Strap

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

10 OF 20

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

SRTCRST#

RTCRST#

3

5 OF 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A8/CLKRUN#

PCIE_CLK_XDP_N

F43

PCIE_CLK_XDP_P

E43

SUSCLK_R

BA17

XTAL24_IN

E37

XTAL24_OUT

E35

XCLK_BIASREF

E42

RTC_X1

AM18

RTCX1
RTCX2

AM20

AN18
AM16

RTC_X2

SRTC_RST#
RTC_RST#

MEM_SMBCLK

R7

MEM_SMBDATA

R8

GPP_C2/SMBALERT#

R10

SML0_SMBCLK

R9

SML0_SMBDATA

W2

GPP_C5/SML0ALERT#

W1

SML1_SMBCLK

W3

SML1_SMBDATA

V3

GPP_B23/SML1ALERT#

AM7

For eSPI

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

20170504

ESPI_IO0_CPU
ESPI_IO1_CPU
ESPI_IO2_CPU
ESPI_IO3_CPU
ESPI_CS#_CPU
ESPI_RESET#_CPU ESPI_RESET#

CLKRUN#_R

0517 DY

1 2

R1813

DY

0R2J-L-GP

Intel recommend: 2.71k ohm 5%

1 2

R1803
2K7R2F-GP

R1815
10MR2J-L-GP

C1804

SC3D9P50V2CN-1GP

12

X-32D768KHZ-65-GP

82.30001.A41

SML1_SMBCLK [24,79]
SML1_SMBDATA [24,79]

1 2

R1829 15R2F-2-GP

1 2

R1830 15R2F-2-GP

1 2

R1831 15R2F-2-GP

1 2

R1833 15R2F-2-GP

1 2

R1801 0R0402-PAD

1 2

R1826 0R0402-PAD

1 2

R1804 15R2F-2-GP

1 2

R1819 0R2J-L-GP

DY

0512 DY

1

TP1807 TPAD14-OP-GP

1

TP1808 TPAD14-OP-GP

SUS_CLK [24]

+V1.00A_SIP

1 2

X1802

41

2 3

RTC_X2RTC_X1

C1803

SC3D9P50V2CN-1GP

12

ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
ESPI_CS#

ESPI_CLKESPI_CLK_CPU

12

EC1802

DY

SC10P50V2JN-L1-GP

2

SML0_SMBCLK

GPP_B23/SML1ALERT#

GPP_C2/SMBALERT#

MEM_SMBCLK
MEM_SMBDATA

CLKRUN#_R

PWR_SEClET [24]

20170428

XTAL24_IN XTAL24_IN_R

XTAL24_OUT

U22

12

1 2

0R0402-PAD

R1802

1MR2J-1-GP

RN1807

8
7
6

SRN2K2J-4-GP

0516 Check with SW(Internal PH?)

1 2

R1820 150KR2J-GP

1 2

R1821 2K2R2J-L1-GP

1 2

R1805 2K2R2J-L1-GP

1 2

R1832 2K2R2J-L1-GP

0512 Modify

R1810

23

R1818

8K2R2F-1-GP

1 2

DY

U22

4 1

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

CPU_(LPC/SPI/SMBUS/CL/CLK)

CPU_(LPC/SPI/SMBUS/CL/CLK)

CPU_(LPC/SPI/SMBUS/CL/CLK)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

3D3V_S5_PCH

1
2
3
45

+V1.8A_SIP

U22

1 2

C1801 SC15P50V2JN- 2-GP

X1801
XTAL-24MHZ-81-GP

82.30004.841

U22

1 2

C1802 SC15P50V2JN- 2-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

1

A00

A00

18 105Wednesday, November 08, 2017

18 105Wednesday, November 08, 2017

18 105Wednesday, November 08, 2017

A00

5

Main Func = PCH

4

3

2

1

PCH strap pin:

Flash Descriptor Security Overide/
Intel ME Debug Mode

D D

HDA_SDOUT

Low = Default
High = Enable

*

The internal pull-down is disabled after
PLTRST# deasserts

DGPU_PWROK[24,79,85]

HDA_CODEC_BITCLK[27]

HDA_CODEC_SDOUT[27]

HDA_CODEC_SYNC[27]

HDA_SDIN0[27]

C C

ME_FWP[24]

SPKR[27]

HDA_SYNC
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

FC1902

SC2P50V2CN-GP

12

DY

DGPU_PWROK

SPKR

CPU1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKYLAKE-U-GP

AUDIO

SKYLAKE_ULT

SDIO/SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

7 OF 20

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

CPU_A16_TP

SD_RCOMP

1 2

R1901
200R2F-L-GP

1

TP1902
TPAD14-OP-GP

PCH strap pin:

NO REBOOT

Low = Enable (Default)

HDA_SPKR

*

High = Disable

The internal pull-down is disabled after
PLTRST# deasserts

B B

3D3V_S0

1 2

R2006 1KR2J-1-GP

DY

1 2

R1904 100KR2J-1-GP

UMA

1 2

EC1901 SC10P50V2JN-L1-GP

EC1903 SC1KP50V2KX-L-1-GP

DY

1 2

DY

SPKR

DGPU_PWROK

HDA_CODEC_BITCLK

DGPU_PWROK

HDA_CODEC_BITCLK HDA_BITCLK

HDA_CODEC_SYNC

ME_FWP

1 2

R1907 0R0402-PAD

1 2

R1908 0R0402-PAD

1 2

R1912 0R0402-PAD

1 2

R1909 1KR2J-1-GP

HDA_SYNC

HDA_SDOUTHDA_CODEC_SDOUT

12

FC1901

DY

SC2P50V2CN-GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

CPU_(AUDIO/SDIO/SDXC)

CPU_(AUDIO/SDIO/SDXC)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

CPU_(AUDIO/SDIO/SDXC)

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

19 105Wednesday, November 08, 2017

19 105Wednesday, November 08, 2017

19 105Wednesday, November 08, 2017

1

A00

A00

A00

5

Main Func = PCH

UART_2_CRXD_DTXD[68]
UART_2_CTXD_DRXD[68]

1 2

EC2002 SC1KP50V2KX-L-1-GP

DY

RN2009

1
2 3

OPS

D D

C C

SRN10KJ-5-GP

(PDG#543016) If the UART/GPIO functionality is also not used,
the signals can be left as no-connect.

3D3V_S0

1 2

R2048 51KR2J-1-GP

1 2

R2049 51KR2J-1-GP

1 2

R2046 51KR2J-1-GP

1 2

R2002 10KR2J-L-GP

DY

1 2

R2003 10KR2J-L-GP

RN2010

1
2 3

SRN2K2J-1-GP

3D3V_S5_PCH

1
2 3

4

Debug
Debug
Debug

4

DY

RN2011
SRN10KJ-5-GP

DGPU_HOLD_RST#
DGPU_PWR_EN

I2C0_SDA_TCH_PAD
I2C0_SCL_TCH_PAD

SIO_EXT_WAKE#

4

RTC_DET#

PCH strap pin:

No Reboot

GSPI0_MOSI /
GPP_B18

The signal has a weak intern al pull-down.

Sampled at rising edge o f PCH_PWROK

0 = Disable “No Reboot” mode .
1 = Enable “No Reboot” mod e (PCH will disable the TCO
Timer system reboot feature). This f unction is useful
when running ITP/XDP.

DGPU_HOLD_RST# [76]

DBC_PANEL_EN[55]

TPAD14-OP-GP

BLUETOOTH_EN[61]

UART_2_CTXD_DRXD
LPSS_UART2_CTS# LPSS_UART2_CTS#

BLUETOOTH_EN

PTP

DBC_PANEL_EN

SIO_EXT_WAKE#[24]

I2C0_SDA_TCH_PAD[65]
I2C0_SCL_TCH_PAD[65]

PCH Prim

3D3V_S5_PCH

0511 Remove DB2

TP2008

12

R2007

DY

1KR2J-1-GP

GPP_B18/GSPI0_MOSI

12

R2019

DY

1KR2J-1-GP

4

VRAM_ID1
GPP_B18/GSPI0_MOSI

GPP_B22

1

BOARD_ID2

UART_2_CRXD_DTXD
UART_2_CTXD_DRXDUART_2_CRXD_DTXD

CPU1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKYLAKE-U-GP

3

LPSS ISH

SKYLAKE_ULT

Strap

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ ISH_GP6

+V1.8A_SIP +V1.8A_SIP

0517 Change PH power rate

12

DY_SKL

12

KBL

PROJECT_ID1

12

Vegas

12

Turis

R2015
10KR2J-L-GP

R2016
10KR2J-L-GP

PROJECT_ID2

6 OF 20

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_S DA
GPP_F11/I2C5_SCL/ISH_I2C2 _SCL

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

BIOS strap pin:

PROJECT Strap pin

R2017
10KR2J-L-GP

R2018
10KR2J-L-GP

Turis

Vegas

KBL

SKL

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

USB_UART_SEL_D9
DGPU_HOLD_RST#

RTC_DET#

I2C0_SDA
I2C0_SCL

I2C1_SDA
I2C1_SCL

1.8V Only

DGPU_PWR_EN
UART0_TXD
UART0_RTS#
UART0_CTS#

UART1_RXD

UART1_CTS#

PROJECT_ID1
PROJECT_ID2
KB_DET#
CAMERA_DET#
TPM_SELECT

PROJECT_ID2

2

1

TP2006 TPAD14-OP-GP

RTC_DET# [25]

(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
to the same voltage rail as the device/end point.

1
1
1

1

1

PANEL_SIZE_ID [55]

KB_DET# [65]

TP2007 TPAD14-OP-GP
TP2010 TPAD14-OP-GP
TP2011 TPAD14-OP-GP

TP2012 TPAD14-OP-GP

FFS_INT2 [67]

TP2015TPAD14-OP-GP

DVT1 add FFS 2/18

CAMERA_DET# [55]

DGPU_PWR_EN [85,86]

0517 Change PH power rate

KB_DET#
CAMERA_DET#

??? Ask SW in PH necessary

1

RN2007

1
2 3

1
2 3

1 2
1 2

SRN10KJ-5-GP

DY

RN2008

DY

SRN2K2J-1-GP

I2C0_SCL
I2C0_SDA

I2C1_SCL
I2C1_SDA

R2001 10KR2J-L-GP
R2004 10KR2J-L-GP

GPP_A18GPP_A19

PROJECT_ID1

X

0

1X

0

1

X

X

3D3V_S0

4

4

+V1.8A_SIP

0517 Change PH power rate

3D3V_S0

12

OPS

B B

BOARD_ID2

12

UMA

3D3V_S0

12

VRAM_2G

VRAM_ID1

12

VRAM_4G

A A

5

4

R2005
10KR2J-L-GP

R2008
10KR2J-L-GP

R2023
10KR2J-L-GP

R2024
10KR2J-L-GP

BIOS strap pin:

BIOS UMA/DIS Strap pin

UMA

DIS

BIOS strap pin:

BIOS VRAM Size Strap pin

4G

2G

3

GPP_C11

BOARD_ID2

0

1

TPM_SELECT

GPP_B17

VRAM_ID1

0

1

+V1.8A_SIP

TPM

NON_TPM

2

12

R2022
10KR2J-L-GP

12

R2020
10KR2J-L-GP

BIOS strap pin:

BIOS UMA/DIS Strap pin

TPM

NON_TPM

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

GPP_A22

TPM_SELECT

1

0

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(LPSS/ISH)

CPU_(LPSS/ISH)

CPU_(LPSS/ISH)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

A00

A00

20 105Wednesday, November 08, 2017

20 105Wednesday, November 08, 2017

20 105Wednesday, November 08, 2017

A00

5

Main Func = PCH

12

C2110

AB19
AB20

AF18
AF19

AB17

AD17
AD18

AJ17

AJ19

AJ16

AF20
AF21

AJ21

AK20

N15
N16
N17
P15
P16

K15

V15

Y18

T19
T20

N18

P18

V20
V21

AL1

K17

L15

DY

L1

12

12

CPU1O

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0
VCCMPHYAON_1P0

VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0

VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0
VCCPRIM_1P0

VCCDSW_3P3
VCCDSW_3P3
VCCDSW_3P3

VCCHDA

VCCSPI

VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0

VCCPRIM_3P3

VCCPRIM_1P0

VCCAPLLEBB_1P0

SKYLAKE-U-GP

C2111

C2114

CPU POWER 4 OF 4

Layout Note:

1uF:
C2105 near V19
C2106 near AK17
C2107 near AG15
C2109 near Y16

0.1uF:
C2110 near T16
C2111 near AJ19

SC22U6D3V3MX-1-GP

Layout Note:

22uF:
C2114 near V15

SKYLAKE_ULT

+V1.00A_ SIP

+VCCPRIM_ CORE

2.57A

C2120

D D

C C

EC2101

12

+V3.3A_S IP

+V3.3A_S IP

DY

B B

+VCCAMP HYPLL_1P0 +VCCAPL L_1P0

DY

A A

SC1U10V2KX-1GP

SCD1U25V2KX-GP

12

DY

+VCCMPH YGTAON_1P0_LS_ SIP

+VCCMPH YGTAON_1P0_LS_ SIP

+VCCMPH YGTAON_1P0_LS_ SIP

C2105

12

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

C2113

12

+VCCDSW _1P0

+VCCAMP HYPLL_1P0

+VCCAPL L_1P0

+VCCPDS W_3P3

R2101
0R0402-P AD

C2106

12

12

DY

DY

SC22U6D3V3MX-1-GP

Layout Note:

22uF:
C2113 near K15

+V1.00A_ SIP

+V1.00A_ SIP

1 2

+V3.3A_S IP

+V3.3A_S IP

+V1.00A_ SIP

C2107

DY

C2109

12

+VCCPAZ IO

SCD1U16 V2KX-3GP
SCD1U16 V2KX-3GP

1.8V Only

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

+V1.00A_ SIP

4

15 OF 20

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC
VCCRTC

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

C2101

12

12

DY

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

0511 Follow KY15.

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19

T1

AA1

AK17

AK19
BB14

BB10

A14

K19

L21

N20

L19

A10

AN11
AN13

+V1.8A_S IP

+V3.3A_S IP

+V1.8A_S IP

+V3.3A_S IP

+V1.00A_ SIP

+V1.8A_S IP

+V3.3A_S IP

+VCCPRT C_3P3

VCCRTCE XT

+V1.00A_ SIP

Symbol error for layout NC

3

RTC_AUX _S5

12

DY

SCD1U16 V2KX-3GP
SCD1U16 V2KX-3GP

CAP need close to VCCRTC

1 2

C2112 SCD1U16V2 KX-3GP

+VCCDSW _1P0+V1.8A_S IP

C2103

C2108

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

12

C2118

C2119

12

C2117

SC1U10V2KX-1GP

12

0512 Follow SF

RTCRST_ ON[18,24]

1 2

R2113 0R0402-P AD

Q2107

S

D

RTC_RST

G

DMP2130 L-7-GP

G

84.02130.031

2nd = 84.0 0102.031

3rd = 84.03 413.B31

RTC_RST

12

R2118

100KR2J-1-GP

2

1 2

R2107
0R0402-P AD-2-GP

1 2

R2112
0R0603-P AD-2-GP-U

1 2

R2108
0R0603-P AD-2-GP-U

D

D2102

RTC_RST

RB751VM -40TE-17-GP

83.R2004.J8F

1 2

R2102

RTC_RST

1MR2J-1-G P

1

+VCCPRT C_3P3RTC_AUX _S5

+VCCAMP HYPLL_1P0+VCCMPH YGTAON_1P0_LS_ SIP

+VCCAPL L_1P0+V1.00A_ SIP

RTC_AUX _S5RTC_3D3 V

12

R2104
4K7R2J-2 -GP

RTC_RST

RTC_3P3 _EN_D

D

Q2110
2N7002K -2-GP

G

RTC_RST

84.2N702.J31

2ND = 84.2 N702.031

3rd = 84.07 002.I31

S

4th = 84.2N 702.W31

AK

RTC_3P3 _EN_G

RTC_RST

C2123

SCD022U16V2KX-3GP

12

Layout Note:

C2116

C2104

C2121

12

12

DY

DY

C2122

SC22U6D3V3MX-1-GP

12

VCCDSW _EN#[24]

1uF:
C2101 near AB19
C2104 near K17
C2116 near A10
C2121 near AL1
22uF:
C2122 near L19

3D3V_S5

RTC_RST

12

12

DY

0512 Follow SF

R2120

100KR2J-1-GP

C2125
SC1U10V 2KX-1GP

3D3V_S5

1 2

R2114

DY

0R2J-L-GP

3V_5V_P OK[17,40,45,5 3,54]

3V_5V_P OK

VCCDSW _EN#

3D3V_S5

1

RTC_RST

2

U2101

RTC_RST

5

VIN#5

4

VIN#4

RT9724G B-GP

74.09724.09F

D2101

BAT54A-1 1-GP

EN

GND

VOUT

3

1
2
3

3V_5V_D SW_OK

3D3V_S5 _PCH_Gen9

RTC_RST

<Core Design>

<Core Design>

<Core Design>

12

R2115
10KR2J-L -GP

RTC_RST

1 2

R2116
0R3J-L1-G P

3D3V_S5 _PCH

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(POWER1)

CPU_(POWER1)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

CPU_(POWER1)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

21 105Wedn esday, November 08, 20 17

21 105Wedn esday, November 08, 20 17

21 105Wedn esday, November 08, 20 17

1

A00

A00

A00

5

4

3

2

1

D D

XTAL24_OUT_U42

C C

R2201
0R2J-2-GP

CPU1T

AW69

RSVD#AW69

AW68

RSVD#AW68

AU56

RSVD#AU56

AW48

RSVD#AW48

C7

RSVD#C7

U12

RSVD#U12

U11

RSVD#U11

H11

RSVD#H11

SKYLAKE-U-GP

1 2

U42

12

SKYLAKE_ULT

XTAL24_IN_U42_RXTAL24_IN_U42

R2203

1MR2J-1-GP

SPARE

U42

B B

XTAL24_OUT_U42

1 2

R2202

U42

0R2J-2-GP

XTAL24_OUT_R_U42

20 OF 20

RSVD#F6

RSVD#E3
RSVD#C11
RSVD#B11
RSVD#A11
RSVD#D12
RSVD#C12
RSVD#F52

23

U42

F6
E3
C11
B11
A11
D12
C12
F52

U42

1 2

C2201 SC15P50V2JN-2-GP

XTAL24_IN_U42

X2201
XTAL-24MHZ-86-GP

82.30004.891

4 1

U42

1 2

C2202 SC15P50V2JN-2-GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

CPU_(RSVD)

CPU_(RSVD)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU_(RSVD)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

22 105Wednesday, November 08, 2017

22 105Wednesday, November 08, 2017

22 105Wednesday, November 08, 2017

1

A00

A00

A00

5

Main Func = PCH

4

3

2

1

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38

AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6

AW60
AW62
AW64
AW66

AW8
AY66

BA10
BA14
BA18

BA23
BA28
BA32
BA36

BA45

AV1

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1

BA2

F68

CPU1Q

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKYLAKE-U-GP

0517 Follow KY1 5.

Symbol error for layout NC

TP2311TPAD14-OP-G P

D D

C C

B B

TP2301TPAD14-OP-G P

1
1

A67_TP
A70_TP

AA2

AA4
AA65
AA68
AB15
AB16
AB18
AB21

AB8
AD13
AD16
AD19
AD20
AD21
AD62

AD8
AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH6
AH63
AH64
AH67

AJ15
AJ18
AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AK8

AL28
AL32
AL35
AL38

AL45
AL48
AL52
AL55
AL58
AL64

A67
A70

AF1

AF2
AF4

AJ4

AL2

AL4

A5

CPU1P

GND 1 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKYLAKE-U-GP

SKYLAKE_ULT

16 OF 20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

0517 Follow KY1 5.

TP2310TPAD14-OP-G P

TP2304TPAD14-OP-G P

0517 Follow KY1 5.

TP2312TPAD14-OP-G P
TP2305TPAD14-OP-G P

Symbol error for layout NC

1

1

1
1

AV1_TP

AV71_TP

B71_TP
BA1_TP

SKYLAKE_ULT

17 OF 20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA49
BA53
BA57
BA6
BA62
BA66

Symbol error for layout NC

BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64

Symbol error for layout NC

BB67

BB70_TP

BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65

Symbol error for layout NC

E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

0517 Follow KY1 5.

1

TP2307 TPAD 14-OP-GP

[#543016 Rev0.9 ]

G10
G22
G43
G45
G48

G52
G55
G58

G60
G63
G66

H15
H18
H71

K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17

G5

G6

J11
J13
J25
J28
J32
J35
J38
J42

F8

J8

CPU1R

GND 3 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKYLAKE-U-GP

SKYLAKE_ULT

18 OF 20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(VSS)

CPU_(VSS)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU_(VSS)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

23 105Wedn esday, November 08, 20 17

23 105Wedn esday, November 08, 20 17

23 105Wedn esday, November 08, 20 17

1

A00

A00

A00

5

Main Func = KBC

Layout Note:

Need very close to EC

R2402 0R0402-PAD

1D0V_S5

D D

3D3V_S5_KBC

RN2408

SRN100KJ-5-GP

1
2
3
4 5

RN2409

SRN100KJ-5-GP

1
2
3
4 5

RN2406

SRN100KJ-5-GP

1
2
3
4 5

RN2407

SRN100KJ-5-GP

1
2
3
4 5

20170504 ESPI

ESPI_IO[3..0][18]

C C

ESPI_CS#[18]
ESPI_CLK[18]
ESPI_ALERT#[18]
ESPI_RESET#[18]

AC_DIS[43 ,44]

ACOK_IN[17,44]

ALL_SYS_PWRGD[17,40]

ALWON[40]

BEEP[27 ]

BLON_OUT[55]

CMP_VIN0_R[26]
CMP_VOUT0[26]

PWR_SEClET[18]

CLK_TP_SIO[65]
DAT_TP_SIO[65]

DGPU_PWROK[19,79,85]

NB_MUTE#[27]

FAN1_DAC_1[26]

GPU_PWR_LEVEL[79]

H_PROCHOT#[4,44,46]

HOST_DEBUG_TX[61,68]

INT_TP#[4,65]

B B

LANWAKE#[17]

LCD_VCC_TEST_EN[55]

LID_CL_SIO#[64]

MASK_SATA_LED#[64]

ME_FWP[19]

PBAT_PRES#[4 3,44]

PCH_RSMRST#[17]

PCIE_WAKE#[31]

PM_LAN_ENABLE[31]

PRIM_PWRGD[40,54]

PS_ID[43]

RESET_OUT#[17,26,79]

RTCRST_ON[18,21]

SIO_EXT_WAKE#[20]

SIO_PWRBTN#[17]

SIO_SLP_S3#[17,27,40,51]

SIO_SLP_S4#[17,40,44,51]

PBAT_CHG_SMBCLK[43,44]
PBAT_CHG_SMBDAT[43 ,44]

SML1_SMBCLK[18,79]
SML1_SMBDATA[18,79 ]

SUS_CLK[18]

SYS_PWROK[17]

A A

TP_EN#[65]

USB_PWR_EN#[35]

VCCDSW_EN#[21]

1 2

8

KSO8

7

KSO3

6

KSO1
KSO2

8

KSO5

7

KSO4

6

KSO7
KSO6

8

KSO0

7

KSO12

6

KSO16
KSO15

8

KSO13

7

KSO14

6

KSO11
KSO10

ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3

3D3V_S5_KBC

5

VREF_CPU

12

C2406
SCD1U16V2KX-3GP

3D3V_S5_KBC

12

12

DY

1
2
3
4 5

1
2
3
4 5

ESPI

R2450
100KR2J-1-GP

R2449
100KR2J-1-GP

RN2403
SRN10KJ-12-GP

RN2404
SRN10KJ-12-GP

1D8V_S5_KBC

3D3V_S5_KBC

BOARD_ID

KSO9

PROCHOT

8

KSI7

7

KSI6

6

KSI4
KSI2

8

KSI5

7

KSI1

6

KSI3
KSI0

R2410

1 2

10KR2J-L-GP

R2415

1 2

10KR2J-L-GP

3D3V_S5

12

EC_GPIO47 High Active

R2420
0R0402-PAD

R2474

1 2

0R0402-PAD

3D3V_S5 3D3V_S5_KBC

C2416

SCD1U16V2KX-3GP

C2421

SCD1U16V2KX-3GP

C2415

12

12

12

DY

0517 Change to digital GND

KSO[0..16][65]

VCCDSW_EN#

0512(SF)

ESPI_ALERT#

3D3V_S5_KBC

0511(KY15)

INT_TP#

USB_PWR_EN#
ALL_SYS_PWRGD

ALL_SYS_PWRGD assert,
delay 10ms; RESET_OUT# assert.

SUS_CLK

CMP_VOUT1_R

C2419

SCD01U50V2KX-L-GP

12

R2417

12

DY

DY

3D3V_S5

PCB_REV

12

R2443

C2408

SCD1U16V2KX-3GP

12

R2444

12

EC_AGND

12

R2401

DY

10KR2F-L1-GP

TP2406
TPAD14-OP-GP

TP2403

TPAD14-OP-GP
R2412 10KR2J-L-GP
R2431 0R0402-PAD
R2491 0R0402-PAD

R2479 0R0402-PAD
R2481 0R0402-PAD

R2428 0R2J-L-GP

0517 DY

R2418

0R2J-L-GP

G

100KR2J-1-GP

S

10KR2F-L1-GP

100KR2F-L3-GP

PBAT_PRES#

R2434
100KR2J-1-GP

1 2

BOARD_ID_R

R2446

1 2

0R0603-PAD-2-GP-U

SC2D2U10V3KX-L-GP

3D3V_S5_KBC

C2420

SCD1U16V2KX-3GP

C2412

12

12

KSI[0..7][65]

R2411

1 2

DY

0R2J-L-GP

0511(KY15)

0515(KY15)

0511(KY15)

1

0516(CY17)

0511(KY15)

0516(CY17)
0516(KY15)

1
1 2
1 2
1 2

1 2
1 2

1 2

DY

C2425

SC18P50V2JN-1-GP

12

Microchip: Use CL=9p Xtal，C = 10p

1 2

DY

Q2408

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4

C2411

SCD1U16V2KX-3GP

C2410

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

12

0519 Install

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
CAP_LED#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

CLK_TP_SIO
DAT_TP_SIO
SIO_PWRBTN#
VCCDSW_ON

ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
ESPI_CS#
MASK_SATA_LED#
ESPI_CLK
PWR_SEClET
ESPI_ALERT#
GPU_PWR_LEVEL
TP_EN#
ESPI_RESET#
LID_CL_SIO#

CCG4_I2C_INT#
SYS_PWROK
PBAT_PRES#
PRIM_PWRGD
RTCRST_ON
PCH_RSMRST#

BKLT_IN_EC
AC_DIS

USB_POWERSHARE_VBUS_EN

FPR_SCAN#
TP_WAKE_KBC#
AUX_ONPM_LAN_ENABLE

0518(CY17)

USB_EN#
RUNPWROK

RESET_OUT#

MEC_XTAL2
MEC_XTAL1_R

X2401

1 2

XTAL-32D768KHZ-91-GP

082.30003.0221

H_PROCHOT#_EC

4

C2414

SCD1U16V2KX-3GP

C2413

SCD1U16V2KX-3GP

12

12

12

DY

+RTC_CELL_VBAT

12

C2428
SCD1U16V2KX-3GP

KBC24

2

GPIO027/KSO00/PVT_IO1

14

GPIO015/KSO01/PVT_CS#

15

GPIO016/KSO02/PVT_SCLK

16

GPIO017/KSO03/PVT_IO0

37

GPIO045/BCM_INT1#/KSO04

38

GPIO046/BCM_DAT1/KSO05

39

GPIO047/BCM_CLK1/KSO06

50

GPIO025/KSO07/PVT_IO2

46

GPIO055/PWM2/KSO08/PVT_IO3

68

GPIO102/KSO09/CR_STRAP

72

GPIO106/KSO10

74

GPIO110/KSO11

75

GPIO111/KSO12

76

GPIO112/PS2_CLK1A/KSO13

77

GPIO113/PS2_DAT1A/KSO14

86

GPIO125/KSO15

92

GPIO132/KSO16

93

GPIO140/KSO17

98

GPIO143/KSI0/DTR#

99

GPIO144/KSI1/DCD#

6

GPIO005/SMB00_DATA/SMB00_DATA18/KSI2

7

GPIO006/SMB00_CLK/SMB00_CLK18/KSI3

104

GPIO147/KSI4/DSR#

105

GPIO150/KSI5/RI#

107

GPIO151/KSI6/RTS#

108

GPIO152/KSI7/CTS#

78

GPIO114/PS2_CLK0

79

GPIO115/PS2_DAT0

52

GPIO026/PS2_CLK1B

88

GPIO127/PS2_DAT1B

59

GPIO040/LAD0/ESPI_IO0

60

GPIO041/LAD1/ESPI_IO1

61

GPIO042/LAD2/ESPI_IO2

62

GPIO043/LAD3/ESPI_IO3

58

GPIO044/LFRAME#/ESPI_CS#

56

GPIO064/LRESET#

57

GPIO034/PCI_CLK/ESPI_CLK

63

GPIO067/CLKRUN#

55

GPIO063/SER_IRQ/ESPI_ALERT#

10

GPIO011/SMI#/EMI_INT#

49

GPIO060/KBRST

53

GPIO061/LPCPD#/ESPI_RESET#

66

GPIO100/EC_SCI#

32

GPIO126/SHD_SCLK

28

GPIO133/SHD_IO0

29

GPIO134/SHD_IO1

30

GPIO135/SHD_IO2

31

GPIO136/SHD_IO3

27

GPIO123/SHD_CS#

67

GPIO101/SPI_CLK

69

GPIO103/SPI_IO0

71

GPIO105/SPI_IO1

42

GPIO052/SPI_IO2

33

GPIO062/SPI_IO3

3

GPIO001/SPI_CS#/32KHZ_OUT

13

RESET_IN#/GPIO014

48

GPIO057/VCC_PWRGD

73

GPIO107/RESET_OUT#

125

XTAL2

123

XTAL1

MEC1416-NU-D0-GP

071.01416.000G

12

R2458
0R0402-PAD

XTAL_KBC_2

C2424

SC18P50V2JN-1-GP

12

R2416

1 2

0R0402-PAD

C2417

SC2D2U10V3KX-L-GP

If don't need RTC alarm wake up,
can change to 3D3V_AUX_S5

12

R2473

DY

0516 Follow KY15.

124

EC LCD test

EC_BRIGHTNESS[55]

LCD_TST_R[55]

H_PROCHOT#

12

C2403

DY

SC47P50V2JN-3GP

RTC_3D3V3D3V_AUX_S5

12

0R2J-2-GP

R2472

0R0402-PAD

43

103

122

VBAT

GPIO007/SMB01_DATA/SMB01_DATA18

GPIO012/SMB02_DATA/SMB02_DATA18

GPIO130/SMB03_DATA/SMB03_DATA18

GPIO141/SMB04_DATA/SMB04_DATA18

VSS17VSS51AVSS

VSS_VBAT

VSS

VSS64VSS

84

100

R2445

1 2

0R0402-PAD

EC_AGND

R2456 0R0402-PAD

R2419 0R0402-PAD

3

0511 Follow KY15.

1D8V_S5_KBC1D8V_S5

R2462

1 2

0R0402-PAD-2-GP

C2423

SCD1U16V2KX-3GP

12

54

VTR5VTR19VTR

GPIO010/SMB01_CLK/SMB01_CLK18

GPIO013/SMB02_CLK/SMB02_CLK18

GPIO131/SMB03_CLK/SMB03_CLK18

GPIO142/SMB04_CLK/SMB04_CLK18

GPIO166/CMP_VREF1/UART_CLK

112

EC_AGND

1 2

1 2

10KR2J-L-GP

1108 Install

VTR_33_18

VTR65VTR82VTR

GPIO030/BCM_INT0#/PWM4
GPIO031/BCM_DAT0/PWM5
GPIO032/BCM_CLK0/PWM6

GPIO157/LED0/TST_CLK_OUT

GPIO116/TFDP_DATA/UART_RX

GPIO117/TFDP_CLK/UART_TX

GPIO035/SB-TSI_CLK

GPIO033/PECI_DAT/SB_TSI_DAT

GPIO145/ICSP_CLOCK

GPIO146/ICSP_DATA

SYSPWR_PRES/GPIO003

VCI_OVRD_IN/GPIO164

GPIO124/CMP_VOUT0

GPIO020/CMP_VIN0

GPIO165/CMP_VREF0

GPIO120/CMP_VOUT1

GPIO021/CMP_VIN1

GPIO023/ADC6/A20M

VR_CAP

18

VR_CAP

12

C2418
SC1U10V2KX-1GP

Layout Note:

Connect GND and AGND planes via either
0R resistor or connect directly.

3D3V_S5_KBC 3D3V_S5_KBC

12

R2414

GPIO050/TACH0
GPIO051/TACH1

GPIO053/PWM0
GPIO054/PWM1

GPIO056/PWM3

GPIO002/PWM7

GPIO156/LED1
GPIO104/LED2

VREF_CPU

ICSP_MCLR

BGPO/GPIO004

VCI_OUT/GPIO036
VCI_IN1#/GPIO162
VCI_IN0#/GPIO163

GPIO160/DAC_0
GPIO161/DAC_1

DAC_VREF

GPIO024/ADC7

GPIO022/ADC5
GPIO153/ADC4
GPIO154/ADC3
GPIO155/ADC2
GPIO122/ADC1
GPIO121/ADC0

ADC_VREF

12

R2478
100KR2J-1-GP

EC_DEBUG

MODEL_ID

12

3

LCD_TST

ICSP_CLR

C2407

SCD1U16V2KX-3GP

3D3V_S5

MODEL_ID

EC_AGND

8
9
11
12
89
91
96
97

40
41

44
45

47
34
35
36
4

1
106
70

80
81

90
94

95

101
102
87

119
120
121
126
127
128

23
24
22

85
20
25

83
21
26

118
117
116
109
110
111
113
114
115

ICSP_CLK
ICSP_DAT

12

12

BAT2_LED#

3D3V_S5 3D3V_S5

CHG_AMBER_LED#[64]

Q2412 and Q2413 merge

3D3V_S5_KBC

4

RN2402
SRN4K7J-8-GP

1

PBAT_CHG_SMBDAT
PBAT_CHG_SMBCLK
GPU_THM_SMBDAT
GPU_THM_SMBCLK

0516 NC 41, 89, 91, 97 pin

NB_MODE#

FAN1_TACH

0518(CY15)

KB_LED_PWM
BEEP

0517 Follow Taos.

FAN1_PWM
FAN2_PWMVOL_LP#
LANWAKE#
PS_ID
PCIE_WAKE#

BAT2_LED#
BAT1_LED#
BREATH_LED#

ME_FWP
HOST_DEBUG_TX

PTP_DIS#
H_PECI_R

VREF_CPU

ICSP_CLK
ICSP_DAT
ICSP_CLR

NB_MUTE#
SYSPWR_PRES
ALWON
VCI_IN1#
POWER_SW_IN#
HW_ACAV_IN

DGPU_PWROK_EC
HW_ACAVIN_NB

CMP_VOUT0 CMP_VOUT0
CMP_VIN0
VCREF0

PROCHOT
CMP_VIN1
LCD_TST

USB_PWR_SHR_EN_L#
PANEL_BKEN_EC
SIO_EXT_WAKE#
MODEL_ID
I_ADP
BOARD_ID
LCD_VCC_TEST_EN_R
I_BATT

3D3V_S5_KBC

R2442

64K9R2F-1-GP

R2441

100KR2F-L3-GP

2 3

R2438 0R0402-PAD

1 2

R2439 0R0402-PAD

1 2

TP2401 TPAD14- OP-GP

1

TP2407 TPAD14- OP-GP

1

R2403 10KR2J-L-GP

1 2

R2486 0R2J-2-GP

1 2

DY

0518(KY15)
0518(KY15)

TP2402 TPAD14- OP-GP

1

0516(CY17 GPIO)

Need very close to EC

0518(CY17 GPIO)

R2437 43R2J-GP

1 2

12

0517(CY17 GPIO)

0517(CY17 GPIO)

C2422

SCD1U16V2KX-3GP

12

EC_AGND

R2476 0R2J-L-GP

1 2

R2463 0R2J-L-GP

1 2

R2464 0R2J-L-GP

1 2

R2466 0R2J-L-GP

1 2

R2465 0R2J-L-GP

1 2

C2405

DY

SC100P50V2JN-3GP

R2452 100KR2J-1-GP

1 2

R2469 0R0402-PAD

1 2

R2427 0R0402-PAD

1 2

1

C2429 SCD1U16V2KX-3GP

1 2

R2470 0R0402-PAD

1 2

1

R2493 10KR2F-L1-GP

1 2

R2497 0R0402-PAD

1 2

R2471 0R2J-L-GP

1 2

DY

R2495

1 2

0R0402-PAD

R2487

1 2

DY

0R2J-L-GP

I_BATT

R2423
330R2J-3-GP

C2441

SC2200P50V2KX-2GP

12

EC_AGND

EC_DEBUG

EC_DEBUG
EC_DEBUG

EC_DEBUG
EC_DEBUG

SML1_SMBDATA
SML1_SMBCLK

FAN1_DAC_1
SIO_SLP_S3#

TP2405
TPAD14-OP-GP

TPAD14-OP-GP

TP2404

LCD_VCC_TEST_EN

0516(CY17 GPIO)

SIO_SLP_S3#

1 2

Layout Note:

Need very close to EC

3D3V_AUX_KBC_R

ICSP_CLK_R
ICSP_DATA_R

E51_TXD_RHOST_DEBUG_TX
ICSP_MCLR_R

+RTC_CELL_VBAT

ACOK_IN

DGPU_PWROK

CMP_VIN0_R

3D3V_S5_KBC

BLON_OUT
CMP_VIN0_R

EC_AGND

boost_mon [44]

Q2412

1

6

2

5

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

3D3V_S0

12

R2430
10KR2J-L-GP

12

C2401
SC10U6D3V3MX-GP

H_PECI [4]

0516(CY17 GPIO)

R2421
330R2J-3-GP

C2435

SC2200P50V2KX-2GP

12

7
1

2
3
4
5
6
8

20.K0691.006

ACES-CON6-58-GP

2

R2461

1 2

DY

0R2J-2-GP

KA

D2403

RB751V-40H-GP

83.R2004.G8F

3D3V_S5_KBC

1 2

DB3

EC_DEBUG

2

BATT_WHITE_LED# [64]

BAT1_LED#

TOUCH_PANEL_INTR#

Touch Panel PH internally.

CAP_LED#

R2435 0R0402-PAD

FAN_TACH1 [26]

3D3V_S0

12

R2489

100KR2J-1-GP

0519 Follow Vendor

3D3V_S5_KBC

12

R2424
20KR2F-L3-GP

Vref = 1.117
temp around 85

12

R2448

10KR2F-L1-GP

AD_IA [44]

LID_CL_SIO#

PTP_DIS#

L_BKLT_EN[8]

Power Switch Logic(PSL)

KBC_PWRBTN#[64]

3D3V_S5

RN2405

1

8
2
3
4 5

12

R2436
100KR2J-1-GP

D

SRN100KJ-5-GP

3D3V_S0

0516 Follow CY17.

BKLT_IN_EC

7

6

CAP_LED#_S [65]

R2429
10KR2J-L-GP

1 2

Q2414
2N7002K-2-GP

G

S

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

LID_CL_SIO#
TP_EN#

1 2

DY

??? Check function with Kevin

3D3V_AUX_S5

12

R2453
1KR2J-1-GP

DY

C2409

12

1108 Install

PTP

SCD01U50V2KX-L-GP

D2402

K A

RB751V-40H-GP

83.R2004.G8F

D2405

K A

RB751V-40H-GP

83.R2004.G8F

1 2

R2432
1KR2J-1-GP

SYSPWR_PRES

0519 DY if not enable the RTC/WeekTimer

12

R2455
100KR2J-1-GP

TOUCH_PANEL_INTR# [4,55]

TP_LOCK# [65]

+RTC_CELL_VBAT

12

R2451
100KR2J-1-GP

POWER_SW_IN#

12

C2426
SC2D2U10V3KX-L-GP

0522 Follow KY15

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Friday, November 10, 2017

Friday, November 10, 2017

Friday, November 10, 2017
Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

KBC SMSC 1416

KBC SMSC 1416

KBC SMSC 1416

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

1

24 105

24 105

24 105

A00

A00

A00

5

Main Func = SPI Flash

4

3

2

1

SPI Flash ROM1(16M) for PCH

3D3V_S5_PCH

D D

0519 Follow KY15.

SPI_CS_ROM_N0
SPI_SO_ROM_R
SPI_WP_ROM_R

Layout Note :

SKT251

1
2
3 6

EVT

4

SKT-G6179HT0321-001-GP

62.10089.011

Co-lay with SPI25

SPI_CS_ROM_N0[18]
SPI_SO_ROM[18,91]

C C

Main Func = RTC

B B

AFTP2502

RTC1

PWR

GND

NP1
NP2

BAT-AAA-BAT-054-P06-GP-U

62.70001.061

A A

5

3D3V_S5_PCH

8
7

5

R2507
10R2F-L1-GP

1

1
2
NP1
NP2

SPI_HOLD_ROM_R
SPI_CLK_ROM_R
SPI_SI_ROM_R

1 2

+RTC_VCC

+RTC_VCC

1

SPI_CS_ROM_N0

SPI_WP_ROM_R

1 2

R2502
1KR2J-1-GP

AFTP2501

12

4

3D3V_AUX_S5

12

R2503
1K6R2F-GP

12

R2505
47KR2F-GP

R2504
10MR2J-L-GP

12

4

R2501

4K7R2J-2-GP

DY

1

3D3V_RTC_SYS

RTC_PWR

Q2505

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

RN2501
SRN4K7J-8-GP

2 3

SPI25

1

CS#

2

SO

3

IO2

4

VSS

GD25B128CSIGR-GP

072.25128.0H01

D2501

1

2

BAT54C-12-GP

75.00054.A7D

D

0511 Follow KY15.

RTC_3D3V

3

12

3

SC10U6D3V3MX-GP

3D3V_S5_PCH

8

VCC

7

IO3

6

SCLK

5

SI

C2503
SCD47U10V2KX-GP

RTC_DET# [20]

C2501

SPI_HOLD_ROM_RSPI_SO_ROM_R
SPI_CLK_ROM_R
SPI_SI_ROM_R

SPI_WP_ROM_R

DY

3D3V_S5_PCH

12

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

C2502
SCD1U16V2KX-3GP

RN2503

SRN0J-6-GP

1
2 3

1
2 3

RN2502

SRN0J-6-GP

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

2

4

4

Flash/RTC

Flash/RTC

Flash/RTC

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

SPI_CLK_ROM [18,91]
SPI_SI_ROM [18,91]

SPI_HOLD_ROM [18]
SPI_WP_ROM [18]

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

25 105

25 105

25 105

1

A00

A00

A00