Wistron Vegas SKL Schematic

5

D D

4

3

2

1

Vegas Schematic

C C

KBL-R

2017/11/08
REV : A00

B B

<Core Design>

<Core Design>

DY : None Installed

<Core Design>

W

W

W

istron Corporation

istron Corporation

A A

UMA: UMA only installed
OPS: DISCRTE OPTIMUS installed

5

4

3

itle

Title

Title

T

C

C

C

over Page

over Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

4

4

4

A

A

A

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Date: Sheet

Date: Sheet

Date: Sheet

2

over Page

V

V

V

egas SKL/KBL-U

egas SKL/KBL-U

egas SKL/KBL-U

istron Corporation

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2

2

2
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1 105

1 105

1 105

f

f

f

o

o

o

1

A

A

A

00

00

00

5

Project code:
PCB P/N:
Revision: X02

D D

17841-1

2GB = 256Mb x 32 x 2 PCS

RAM(GDDR5) *2

V

2GB (256Mb x 32)

1, 82

8

GDDR5

DIS only

Vegas
Turis

C C

B B

A A

Vegas
Turis

Vegas
Turis

Vegas
Turis

Vegas
Turis

Vegas
Turis

Vegas
Turis

niversal Jack

U

14"/15" LCD

15" Touch Panel

(TURIS only)

Camera

Digital MIC

RJ45 Conn.

HDMI V1.4a

VGA Conn.

USB1(USB3.0)

USB2(USB3.0)

2CH SPEAKER
(2CH 2W/4ohm)

29

55

32

56

Left side

Left side

57

36

36

MIC_IN/GND

HP_R/L

LAN 10/100

REALTEK RTL8106E

LAN 10/100/1000

REALTEK RTL8111H

DP/VGA Converter

REALTEK RTD2166

Audio Codec

ALC3246

4

egas/Turis MLK KBL-R Block Diagram

V

NEWNEW

GPU

AMD
R17M-M1-30
25W

6, 77, 78, 79, 80

7

URIS only

T

PCIE x 4

eDP x2

USB2.0 x1

USB2.0 x1

I

Kabylake-U 4+2

15W (UMA&DIS)

K

0 USB 2.0/1.1 ports

1

6

High Definition Audio

3 SATA ports
6 PCIE ports
LPC I/F
ACPI 5.0

3

ntel CPU

BL PCH-LP

USB 3.0 ports

DDR4 2400MHz Channel A

DDR4 2400MHz Channel A

USB2.0 x1

VEGAS only

PCIE x1

USB2.0 x1

2

NEW

Fingerprint

FM-03331

NGFF WLAN

802.11a/b/g/n
BT V4.0 combo

PCIE x1

31

VEGAS only

DDI1

56

VEGAS only

USB2.0 x1

USB3.0 x1

USB2.0 x1

DDI2

SATA (Gen3) x1

SATA (Gen1) x1

eSPI BUS

Kyloren

15

E

SMSC MEC1416-NU-GP

HDD

60

Vegas

ODD

Turis

60

C

USB3.0 x1

SPI

DA

H

27

Flash ROM

16MB

25

VEGAS only

TPM 2.0

NPCT650/750

Int. KB

65

91

PS2

P

I2C

DR4 2400

D

ODIMM A

S

DDR4 2400

ODIMM B

S

NEW

92

Vegas
Turis

61

Kyloren 15

eSPI debug port

FAN Control

24

Vegas
Turis

recisionTouch pad

65

1

CHARGER

SL88739

I

INPUTS

AD+

T+

B

SYSTEM DC/DC

PS51225RUKR-GP

T

INPUTS

CBATOUT

D

12

3

1

CPU Core Power

NCP81208MNTXG
NCP81382MNTXG x 2
NCP81382MNTXG (23e)
NCP81253MNTBG

INPUTS

DCBATOUT

DCBATOUT

DCBATOUT+VCCSA

DDR4 SUS

T8231AGQW-GP

R
APL5930KAI-TRG

INPUTS

DCBATOUT
3D3V_S5

CPU VCCPRIM_CORE
1V

INPUTS

D0V_S5

1

CPU DCDC-V1D00A

OZ2262QI-10-GP-U

A

DCBATOUT

LDO-V1D8V

APL5930KAI-TRG

D3V_S5

3

T

68

EOPIO/EDRAM (23e)

T

26

INPUTS

1D0V_S5
1

AO3419L

INPUTS

3

26

ISL62771HRTZ-GP-U

INPUTS

D

Y

INPUTS

DCBATOUT

OUTPUTS

DCBATOUT

OUTPUTS

D3V_PWR

3
3D3V_S5
5V_PWR
5V_S5

OUTPUTS

CC_CORE

V

+VCCGTDCBATOUT

+VCCGT (23e)

OUTPUTS

1D2V_S3
0D6V_S0
2D5V_S3

OUTPUTS

VCCPRIM_CORE

+

OUTPUTSINPUTS

1D0V_S5

OUTPUTSINPUTS

1D8V_S5

5V/3V S0

PS22966DPUR-GP

5V_S5
3D3V_S5

PS22961DNYT

D0V_S5

3D3V VGA

D3V_S0

VGA_CORE

CBATOUT

1D5V_VGA_S0

8288RAC-GP

OUTPUTSINPUTS

5V_S0
3D3V_S0

OUTPUTS

V_EDRAM_VR

+
+V_EOPIO_VR

OUTPUTS

3D3V_VGA_S0

OUTPUTS

GA_CORE

V

OUTPUTS

1D5V_VGA_S0

46~50

33

4

44

45

51

1

1

3

5

54

0

40

86

85

86

Vegas
Turis

Vegas
Turis

IO Board

USB3(USB2.0)

SD Card Slot

5

CardReader

Realtek RTS5170

<Core Design>

<Core Design>

USB2.0 x1

USB2.0 x1

4

3

2

<Core Design>

W

W

W

istron Corporation

istron Corporation

istron Corporation

2

2

2

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

B

B

B

lock Diagram

lock Diagram

lock Diagram

egas SKL/KBL-U

egas SKL/KBL-U

egas SKL/KBL-U

V

V

V

1

o

2

o

2

o

2

f

f

f

00

00

00

A

A

A

105Wednesday, November 08, 2017

105Wednesday, November 08, 2017

105Wednesday, November 08, 2017

5

Main Func = CPU

4

3

2

1

+VCCST_ CPU

SKYLAKE_ULT

CPU MISC

12

R419
1KR2J-1-G P

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

4 OF 20

JTAGX

B61
D60
A61
C60
B59

B56
D59
A56
C59
C61
A59

XDP_TCL K
XDP_TDI
XDP_TDO _CPU
XDP_TMS
XDP_TRS T#

PCH_JTA G_TCK
PCH_JTA G_TDI
PCH_JTA G_TDO
PCH_JTA G_TMS
XDP_TRS T#
XDP_TCK _JTAGX

XDP_TRS T#

12

EC401

DY

SC1KP50 V2KX-L-1-GP

XDP_TMS
XDP_TDI

XDP_TDO _CPU

PCH_JTA G_TDI

0525 Follow KY15 & SF

PCH_JTA G_TDO

PCH_JTA G_TMS

XDP_TCK _JTAGX

XDP_TRS T#

XDP_TCL K

PCH_JTA G_TCK

1 2

R421 51R2J-2-G P

DY

1 2

R422 51R2J-2-G P

DY

1 2

R423 51R2J-2-G P

DY

1 2

R408 51R2J-2-G P

1 2

R409 51R2J-2-G P

1 2

R416 51R2J-2-G P

1 2

R417 1KR2J-1-G P

DY

1 2

R402 51R2J-2-G P

DY

1 2

R406 51R2J-2-G P

1 2

R407 51R2J-2-G P

DY

#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm

D D

[PECI] and [PRO CHOT#]
Impedance contr ol: 50 ohm

H_PECI[24]

H_PROCH OT#[24,44,46]

TOUCH_P ANEL_INTR#[24,55]

INT_TP#[24,65]

C C

#544669 Rev0.52 :
Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm an d 150 ohm

+VCCSTG

+VCCSTG = 1.0 V

12

R401

Rb

1KR2J-1-G P

Ra

1 2

R403
499R2F-2 -GP

INT_TP# TOUCHPA D_INTR#

1 2

R410
0R0402-P AD

1 2

R412 49D9R2F -L1-GP

1 2

R413 49D9R2F -L1-GP

1 2

R414 49D9R2F -L1-GP

1 2

R415 49D9R2F -L1-GP

TP401TPAD14-O P-GP

TP402TPAD14-O P-GP

TP405TPAD14-O P-GP
TP406TPAD14-O P-GP
TP407TPAD14-O P-GP
TP408TPAD14-O P-GP

TP404TPAD14-O P-GP

H_CATER R#

1

H_PECI
H_PROCH OT#_RH_PROCH OT#
PCH_THE RMTRIP

1

SKTOCC#

XDP_BPM 0

1

XDP_BPM 1

1

XDP_BPM 2

1

XDP_BPM 3

1

TOUCH_P ANEL_INTR#

GPP_B4/C PU_GP3

1

CPU_POP IRCOMP
PCH_POP IRCOMP
EDRAM_O PIO_RCOMP
EOPIO_RCO MP

CPU1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U-GP

PCH_THE RMTRIP

+VCCSTG = 1.0 V

+VCCSTG

(#543016) PROCHOT# Routing Guidelines

#544669 CRB Rev 0.52

B B

M1,2,3,4,5: <3 inches
M6: 1-11 inches
MCPU: 0.3-1.5 i nches
Mt <0.3 mils
Main route(M1+M 2+M3+M4+M5+M6+ MCPU): 1-12 i nches

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(JTAG/CPU SIDE BAND)

CPU_(JTAG/CPU SIDE BAND)

CPU_(JTAG/CPU SIDE BAND)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

4 105Wednesd ay, November 08, 201 7

4 105Wednesd ay, November 08, 201 7

4 105Wednesd ay, November 08, 201 7

1

of

of

of

A00

A00

A00

5

4

3

2

1

Main Func = CPU

DDR4 ball type: Interleaved Type

D D

PU1B

C

_A_DQ0

AL71

M

_A_DQ0[12]

M

_A_DQ1[12]

M

_A_DQ2[12]

M

_A_DQ3[12]

M_A_DQ[0:7]

M_A_DQ[8:15]

M_B_DQ[0:7]

M_B_DQ[8:15]

C C

M_A_DQ[16:23]

M_A_DQ[24:31]

M_B_DQ[16:23]

M_B_DQ[24:31]

DQ Bit Swapping is allowed w ithin the same byte, and Byt e Swapping is allowed within the same channel.

B B

Clock (CLK and CLK#) and Str obe (DQS and DQS#) different ial signal swapping within a pair is not allowed. Also d ifferential
clock pair to clock pair swa pping within a channel is no t allowed.

M

_A_DQ4[12]

M

_A_DQ5[12]

M

_A_DQ6[12]

M

_A_DQ7[12]

M

_A_DQ8[12]

M

_A_DQ9[12]

M

_A_DQ10[12]

M

_A_DQ11[12]

M

_A_DQ12[12]

M

_A_DQ13[12]

M

_A_DQ14[12]

M

_A_DQ15[12]

M

_B_DQ0[13]

M

_B_DQ1[13]

M

_B_DQ2[13]

M

_B_DQ3[13]

M

_B_DQ4[13]

M

_B_DQ5[13]

M

_B_DQ6[13]

M

_B_DQ7[13]

M

_B_DQ8[13]

M

_B_DQ9[13]

M

_B_DQ10[13]

M

_B_DQ11[13]

M

_B_DQ12[13]

M

_B_DQ13[13]

M

_B_DQ14[13]

M

_B_DQ15[13]

M

_A_DQ16[12]

M

_A_DQ17[12]

M

_A_DQ18[12]

M

_A_DQ19[12]

M

_A_DQ20[12]

M

_A_DQ21[12]

M

_A_DQ22[12]

M

_A_DQ23[12]

M

_A_DQ24[12]

M

_A_DQ25[12]

M

_A_DQ26[12]

M

_A_DQ27[12]

M

_A_DQ28[12]

M

_A_DQ29[12]

M

_A_DQ30[12]

M

_A_DQ31[12]

M

_B_DQ16[13]

M

_B_DQ17[13]

M

_B_DQ18[13]

M

_B_DQ19[13]

M

_B_DQ20[13]

M

_B_DQ21[13]

M

_B_DQ22[13]

M

_B_DQ23[13]

M

_B_DQ24[13]

M

_B_DQ25[13]

M

_B_DQ26[13]

M

_B_DQ27[13]

M

_B_DQ28[13]

M

_B_DQ29[13]

M

_B_DQ30[13]

M

_B_DQ31[13]

M

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

_A_DQ1
_A_DQ2
_A_DQ3
_A_DQ4
_A_DQ5
_A_DQ6
_A_DQ7
_A_DQ8
_A_DQ9
_A_DQ10
_A_DQ11
_A_DQ12
_A_DQ13
_A_DQ14
_A_DQ15
_B_DQ0
_B_DQ1
_B_DQ2
_B_DQ3
_B_DQ4
_B_DQ5
_B_DQ6
_B_DQ7
_B_DQ8
_B_DQ9
_B_DQ10
_B_DQ11
_B_DQ12
_B_DQ13
_B_DQ14
_B_DQ15
_A_DQ16
_A_DQ17
_A_DQ18
_A_DQ19
_A_DQ20
_A_DQ21
_A_DQ22
_A_DQ23
_A_DQ24
_A_DQ25
_A_DQ26
_A_DQ27
_A_DQ28
_A_DQ29
_A_DQ30
_A_DQ31
_B_DQ16
_B_DQ17
_B_DQ18
_B_DQ19
_B_DQ20
_B_DQ21
_B_DQ22
_B_DQ23
_B_DQ24
_B_DQ25
_B_DQ26
_B_DQ27
_B_DQ28
_B_DQ29
_B_DQ30
_B_DQ31

DR0_DQ[0]

D

AL68

DR0_DQ[1]

D

AN68

DR0_DQ[2]

D

AN69

DR0_DQ[3]

D

AL70

DR0_DQ[4]

D

AL69

DR0_DQ[5]

D

AN70

DR0_DQ[6]

D

AN71

DR0_DQ[7]

D

AR70

DR0_DQ[8]

D

AR68

DR0_DQ[9]

D

AU71

DR0_DQ[10]

D

AU68

DR0_DQ[11]

D

AR71

DR0_DQ[12]

D

AR69

DR0_DQ[13]

D

AU70

DR0_DQ[14]

D

AU69

DR0_DQ[15]

D

AF65

DR1_DQ[0]/DDR0_DQ[16]

D

AF64

DR1_DQ[1]/DDR0_DQ[17]

D

AK65

DR1_DQ[2]/DDR0_DQ[18]

D

AK64

DR1_DQ[3]/DDR0_DQ[19]

D

AF66

DR1_DQ[4]/DDR0_DQ[20]

D

AF67

DR1_DQ[5]/DDR0_DQ[21]

D

AK67

DR1_DQ[6]/DDR0_DQ[22]

D

AK66

DR1_DQ[7]/DDR0_DQ[23]

D

AF70

DR1_DQ[8]/DDR0_DQ[24]

D

AF68

DR1_DQ[9]/DDR0_DQ[25]

D

AH71

DR1_DQ[10]/DDR0_DQ[26]

D

AH68

DR1_DQ[11]/DDR0_DQ[27]

D

AF71

DR1_DQ[12]/DDR0_DQ[28]

D

AF69

DR1_DQ[13]/DDR0_DQ[29]

D

AH70

DR1_DQ[14]/DDR0_DQ[30]

D

AH69

DR1_DQ[15]/DDR0_DQ[31]

D

BB65

DR0_DQ[16]/DDR0_DQ[32]

D

AW65

DR0_DQ[17]/DDR0_DQ[33]

D

AW63

DR0_DQ[18]/DDR0_DQ[34]

D

AY63

DR0_DQ[19]/DDR0_DQ[35]

D

BA65

DR0_DQ[20]/DDR0_DQ[36]

D

AY65

DR0_DQ[21]/DDR0_DQ[37]

D

BA63

DR0_DQ[22]/DDR0_DQ[38]

D

BB63

DR0_DQ[23]/DDR0_DQ[39]

D

BA61

DR0_DQ[24]/DDR0_DQ[40]

D

AW61

DR0_DQ[25]/DDR0_DQ[41]

D

BB59

DR0_DQ[26]/DDR0_DQ[42]

D

AW59

DR0_DQ[27]/DDR0_DQ[43]

D

BB61

DR0_DQ[28]/DDR0_DQ[44]

D

AY61

DR0_DQ[29]/DDR0_DQ[45]

D

BA59

DR0_DQ[30]/DDR0_DQ[46]

D

AY59

DR0_DQ[31]/DDR0_DQ[47]

D

AT66

DR1_DQ[16]/DDR0_DQ[48]

D

AU66

DR1_DQ[17]/DDR0_DQ[49]

D

AP65

DR1_DQ[18]/DDR0_DQ[50]

D

AN65

DR1_DQ[19]/DDR0_DQ[51]

D

AN66

DR1_DQ[20]/DDR0_DQ[52]

D

AP66

DR1_DQ[21]/DDR0_DQ[53]

D

AT65

DR1_DQ[22]/DDR0_DQ[54]

D

AU65

DR1_DQ[23]/DDR0_DQ[55]

D

AT61

DR1_DQ[24]/DDR0_DQ[56]

D

AU61

DR1_DQ[25]/DDR0_DQ[57]

D

AP60

DR1_DQ[26]/DDR0_DQ[58]

D

AN60

DR1_DQ[27]/DDR0_DQ[59]

D

AN61

DR1_DQ[28]/DDR0_DQ[60]

D

AP61

DR1_DQ[29]/DDR0_DQ[61]

D

AT60

DR1_DQ[30]/DDR0_DQ[62]

D

AU60

DR1_DQ[31]/DDR0_DQ[63]

D

SKYLAKE-U-GP

SKYLAKE_ULT

DR0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5]

D

DR0_DQ[16]

D

DR0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9]

D

DDR0_DQ[17]

DR0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6]

D

DDR0_DQ[18]

DR0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8]

D

DDR0_DQ[19]

DR0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7]

D

DR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_DQ[20]

D

DDR0_DQ[21]

DR0_MA[12]/DDR0_CAA[6]/DDR0_MA[ 12]

D

DDR0_DQ[22]

DR0_MA[11]/DDR0_CAA[7]/DDR0_MA[ 11]

D

DDR0_DQ[23]

DR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

D

DR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

D

DR0_MA[13]/DDR0_CAB[0]/DDR0_MA[ 13]

D

DR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

D

DR0_WE#/DDR0_CAB[2]/D DR0_MA[14]

D

DR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

D

DR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

D

DR0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]

D

DR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

D

DR0_MA[10]/DDR0_CAB[7]/DDR0_MA[ 10]

D

DR0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1]

D

DR0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0]

D

DDR CH - A

DR1_DQSN[0]/DDR0_DQSN[2]

D

DR1_DQSP[0]/DDR0_DQSP[2]

D

DR1_DQSN[1]/DDR0_DQSN[3]

D

DR1_DQSP[1]/DDR0_DQSP[3]

D

DR0_DQSN[2]/DDR0_DQSN[4]

D

DR0_DQSP[2]/DDR0_DQSP[4]

D

DR0_DQSN[3]/DDR0_DQSN[5]

D

DR0_DQSP[3]/DDR0_DQSP[5]

D

DR1_DQSN[2]/DDR0_DQSN[6]

D

DR1_DQSP[2]/DDR0_DQSP[6]

D

DR1_DQSN[3]/DDR0_DQSN[7]

D

DR1_DQSP[3]/DDR0_DQSP[7]

D

PDG: DDR/ODT

DR0_CKN[0]

D

DR0_CKP[0]

D

DR0_CKN[1]

D

DR0_CKP[1]

D

DR0_CKE[0]

D

DR0_CKE[1]

D

DR0_CKE[2]

D

DR0_CKE[3]

D

DR0_CS#[0]

D

DR0_CS#[1]

D

DR0_ODT[0]

D

DR0_ODT[1]

D

DR0_MA[3]

D

DR0_MA[4]

D

DR0_DQSN[0]

D

DR0_DQSP[0]

D

DR0_DQSN[1]

D

DR0_DQSP[1]

D

DR0_ALERT#

D

DR0_PAR

D

DR_VREF_CA

D

DR0_VREF_DQ

D

DR1_VREF_DQ

D

DR_VTT_CNTL

D

2

OF 20

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60

AW50
AT52

AY67
AY68
BA67

AW67

_A_A5

M

_A_A9

M

_A_A6

M

_A_A8

M

_A_A7

M

_A_A12

M

_A_A11

M

_A_A13

M

_A_A15

M

_A_A14

M

_A_A16

M

_A_A2

M

_A_A10

M

_A_A1

M

_A_A0

M

_A_A3

M

_A_A4

M

_A_DQS_DN0

M

_A_DQS_DP0

M

_A_DQS_DN1

M

_A_DQS_DP1

M

_B_DQS_DN0

M

_B_DQS_DP0

M

_B_DQS_DN1

M

_B_DQS_DP1

M

_A_DQS_DN2

M

_A_DQS_DP2

M

_A_DQS_DN3

M

_A_DQS_DP3

M

_B_DQS_DN2

M

_B_DQS_DP2

M

_B_DQS_DN3

M

_B_DQS_DP3

M

M_PGCNTL

S

_A_CLK#0 [12]

M

_A_CLK0 [12]

M

_A_CLK#1 [12]

M

_A_CLK1 [12]

M

_A_CKE0 [12]

M

_A_CKE1 [12]

M

_A_CS#0 [12]

M

_A_CS#1 [12]

M

_A_DIMA_ODT0 [12]

M

_A_DIMA_ODT1 [12]

M

_A_A5 [12]

M

_A_A9 [12]

M

_A_A6 [12]

M

_A_A8 [12]

M

_A_A7 [12]

M

_A_BG0 [12]

M

_A_A12 [12]

M

_A_A11 [12]

M

_A_ACT_N [12]

M

_A_BG1 [12]

M

_A_A13 [12]

M

_A_A15 [12]

M

_A_A14 [12]

M

_A_A16 [12]

M

_A_BA0 [12]

M

_A_A2 [12]

M

_A_BA1 [12]

M

_A_A10 [12]

M

_A_A1 [12]

M

_A_A0 [12]

M

_A_A3 [12]

M

_A_A4 [12]

M

M_A_DQS0

M_A_DQS1

M_B_DQS0

M_B_DQS1
M_A_DQS2

M_A_DQS3

M_B_DQS2

M_B_DQS3

_A_ALERT_N [12]

M

_A_PARITY [12]

M

_SM_VREF_CNTA [12]

V

_SM_VREF_CNTB [13]

V

M_A_DQ[32:39]

M_A_DQ[40:47]

M_B_DQ[32:39]

M_B_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_DQ[48:55]

M_B_DQ[56:63]

M_PGCNTL

S

M

_A_DQ33[12]

M

_A_DQ34[12]

M

_A_DQ35[12]

M

_A_DQ36[12]

M

_A_DQ37[12]

M

_A_DQ38[12]

M

_A_DQ39[12]

M

_A_DQ40[12]

M

_A_DQ41[12]

M

_A_DQ42[12]

M

_A_DQ43[12]

M

_A_DQ44[12]

M

_A_DQ45[12]

M

_A_DQ46[12]

M

_A_DQ47[12]

M

_B_DQ32[13]

M

_B_DQ33[13]

M

_B_DQ34[13]

M

_B_DQ35[13]

M

_B_DQ36[13]

M

_B_DQ37[13]

M

_B_DQ38[13]

M

_B_DQ39[13]

M

_B_DQ40[13]

M

_B_DQ41[13]

M

_B_DQ42[13]

M

_B_DQ43[13]

M

_B_DQ44[13]

M

_B_DQ45[13]

M

_B_DQ46[13]

M

_B_DQ47[13]

M

_A_DQ48[12]

M

_A_DQ49[12]

M

_A_DQ50[12]

M

_A_DQ51[12]

M

_A_DQ52[12]

M

_A_DQ53[12]

M

_A_DQ54[12]

M

_A_DQ55[12]

M

_A_DQ56[12]

M

_A_DQ57[12]

M

_A_DQ58[12]

M

_A_DQ59[12]

M

_A_DQ60[12]

M

_A_DQ61[12]

M

_A_DQ62[12]

M

_A_DQ63[12]

M

_B_DQ48[13]

M

_B_DQ49[13]

M

_B_DQ50[13]

M

_B_DQ51[13]

M

_B_DQ52[13]

M

_B_DQ53[13]

M

_B_DQ54[13]

M

_B_DQ55[13]

M

_B_DQ56[13]

M

_B_DQ57[13]

M

_B_DQ58[13]

M

_B_DQ59[13]

M

_B_DQ60[13]

M

_B_DQ61[13]

M

_B_DQ62[13]

M

_B_DQ63[13]

M

D3V_S5

3

12

R

DS

G

507

10KR2J-L-GP

Q

501

Q

DMN5L06K-7-GP

84.05067.031

502_G

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

_A_DQ33
_A_DQ34
_A_DQ35
_A_DQ36
_A_DQ37
_A_DQ38
_A_DQ39
_A_DQ40
_A_DQ41
_A_DQ42
_A_DQ43
_A_DQ44
_A_DQ45
_A_DQ46
_A_DQ47
_B_DQ32
_B_DQ33
_B_DQ34
_B_DQ35
_B_DQ36
_B_DQ37
_B_DQ38
_B_DQ39
_B_DQ40
_B_DQ41
_B_DQ42
_B_DQ43
_B_DQ44
_B_DQ45
_B_DQ46
_B_DQ47
_A_DQ48
_A_DQ49
_A_DQ50
_A_DQ51
_A_DQ52
_A_DQ53
_A_DQ54
_A_DQ55
_A_DQ56
_A_DQ57
_A_DQ58
_A_DQ59
_A_DQ60
_A_DQ61
_A_DQ62
_A_DQ63
_B_DQ48
_B_DQ49
_B_DQ50
_B_DQ51
_B_DQ52
_B_DQ53
_B_DQ54
_B_DQ55
_B_DQ56
_B_DQ57
_B_DQ58
_B_DQ59
_B_DQ60
_B_DQ61
_B_DQ62
_B_DQ63

_A_DQ32

M

_A_DQ32[12]

PU1C

C

AY39

DR0_DQ[32]/DDR1_DQ[0]

D

AW39

DR0_DQ[33]/DDR1_DQ[1]

D

AY37

DR0_DQ[34]/DDR1_DQ[2]

D

AW37

DR0_DQ[35]/DDR1_DQ[3]

D

BB39

DR0_DQ[36]/DDR1_DQ[4]

D

BA39

DR0_DQ[37]/DDR1_DQ[5]

D

BA37

DR0_DQ[38]/DDR1_DQ[6]

D

BB37

DR0_DQ[39]/DDR1_DQ[7]

D

AY35

DR0_DQ[40]/DDR1_DQ[8]

D

AW35

DR0_DQ[41]/DDR1_DQ[9]

D

AY33

DR0_DQ[42]/DDR1_DQ[10]

D

AW33

DR0_DQ[43]/DDR1_DQ[11]

D

BB35

DR0_DQ[44]/DDR1_DQ[12]

D

BA35

DR0_DQ[45]/DDR1_DQ[13]

D

BA33

DR0_DQ[46]/DDR1_DQ[14]

D

BB33

DR0_DQ[47]/DDR1_DQ[15]

D

AU40

DR1_DQ[32]/DDR1_DQ[16]

D

AT40

DR1_DQ[33]/DDR1_DQ[17]

D

AT37

DR1_DQ[34]/DDR1_DQ[18]

D

AU37

DR1_DQ[35]/DDR1_DQ[19]

D

AR40

DR1_DQ[36]/DDR1_DQ[20]

D

AP40

DR1_DQ[37]/DDR1_DQ[21]

D

AP37

DR1_DQ[38]/DDR1_DQ[22]

D

AR37

DR1_DQ[39]/DDR1_DQ[23]

D

AT33

DR1_DQ[40]/DDR1_DQ[24]

D

AU33

DR1_DQ[41]/DDR1_DQ[25]

D

AU30

DR1_DQ[42]/DDR1_DQ[26]

D

AT30

DR1_DQ[43]/DDR1_DQ[27]

D

AR33

DR1_DQ[44]/DDR1_DQ[28]

D

AP33

DR1_DQ[45]/DDR1_DQ[29]

D

AR30

DR1_DQ[46]/DDR1_DQ[30]

D

AP30

DR1_DQ[47]/DDR1_DQ[31]

D

AY31

DR0_DQ[48]/DDR1_DQ[32]

D

AW31

DR0_DQ[49]/DDR1_DQ[33]

D

AY29

DR0_DQ[50]/DDR1_DQ[34]

D

AW29

DR0_DQ[51]/DDR1_DQ[35]

D

BB31

DR0_DQ[52]/DDR1_DQ[36]

D

BA31

DR0_DQ[53]/DDR1_DQ[37]

D

BA29

DR0_DQ[54]/DDR1_DQ[38]

D

BB29

DR0_DQ[55]/DDR1_DQ[39]

D

AY27

DR0_DQ[56]/DDR1_DQ[40]

D

AW27

DR0_DQ[57]/DDR1_DQ[41]

D

AY25

DR0_DQ[58]/DDR1_DQ[42]

D

AW25

DR0_DQ[59]/DDR1_DQ[43]

D

BB27

DR0_DQ[60]/DDR1_DQ[44]

D

BA27

DR0_DQ[61]/DDR1_DQ[45]

D

BA25

DR0_DQ[62]/DDR1_DQ[46]

D

BB25

DR0_DQ[63]/DDR1_DQ[47]

D

AU27

DR1_DQ[48]

D

AT27

DR1_DQ[49]

D

AT25

DR1_DQ[50]

D

AU25

DR1_DQ[51]

D

AP27

DR1_DQ[52]

D

AN27

DR1_DQ[53]

D

AN25

DR1_DQ[54]

D

AP25

DR1_DQ[55]

D

AT22

DR1_DQ[56]

D

AU22

DR1_DQ[57]

D

AU21

DR1_DQ[58]

D

AT21

DR1_DQ[59]

D

AN22

DR1_DQ[60]

D

AP22

DR1_DQ[61]

D

AP21

DR1_DQ[62]

D

AN21

DR1_DQ[63]

D

SKYLAKE-U-GP

D3V_S0

3

502

Q

G

D

S

2N7002K-2-GP

84.2N702.J31

ND = 84.2N702.031

2

3rd = 84.07002.I31

???
Difference with Kyloren

12

R

506

220KR2F-L-GP

SKYLAKE_ULT

DDR CH - B

DR1_CKN[0]

D

DR1_CKN[1]

D

DR1_CKP[0]

D

DR1_CKP[1]

D

DR1_CKE[0]

D

DR1_CKE[1]

D

DR1_CKE[2]

D

DR1_CKE[3]

D

DR1_CS#[0]

D

DR1_CS#[1]

D

DR1_ODT[0]

D

DR1_ODT[1]

DR1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5]

D

DR1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9]

D

DR1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6]

D

DR1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8]

D

DR1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7]

D

DR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

D
DR1_MA[12]/DDR1_CAA[6]/DDR1_MA[ 12]

D

DR1_MA[11]/DDR1_CAA[7]/DDR1_MA[ 11]

D

DR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

D

DR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

D

DR1_MA[13]/DDR1_CAB[0]/DDR1_MA[ 13]

D

DR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

D

DR1_WE#/DDR1_CAB[2]/D DR1_MA[14]

D

DR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

D

DR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

D

DR1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]

D

DR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

D
DR1_MA[10]/DDR1_CAB[7]/DDR1_MA[ 10]

D

DR1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1]

D

DR1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0]

D

M_PGCNTL_R [51]

S

D

D
D

DR0_DQSN[4]/DDR1_DQSN[0]

D

DR0_DQSP[4]/DDR1_DQSP[0]

D

DR0_DQSN[5]/DDR1_DQSN[1]

D

DR0_DQSP[5]/DDR1_DQSP[1]

D

DR1_DQSN[4]/DDR1_DQSN[2]

D

DR1_DQSP[4]/DDR1_DQSP[2]

D

DR1_DQSN[5]/DDR1_DQSN[3]

D

DR1_DQSP[5]/DDR1_DQSP[3]

D

DR0_DQSN[6]/DDR1_DQSN[4]

D

DR0_DQSP[6]/DDR1_DQSP[4]

D

DR0_DQSN[7]/DDR1_DQSN[5]

D

DR0_DQSP[7]/DDR1_DQSP[5]

D

DR1_DQSN[6]

D

DR1_DQSP[6]

D

DR1_DQSN[7]

D

DR1_DQSP[7]

D

DR1_ALERT#

D

D

RAM_RESET#

D

DR_RCOMP[0]

D

DR_RCOMP[1]

D

DR_RCOMP[2]

D

OF 20

3

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

_B_A5

AY48

M

_B_A9

AP50

M

_B_A6

BA48

M

_B_A8

BB48

M

_B_A7

AP48

M

AP52

_B_A12

AN50

M

_B_A11

AN48

M

_B_ACT_N

AN53

M

AN52

_B_A13

BA43

M

_B_A15

M

AY43

_B_A14

M

AY44

_B_A16

M

AW44
BB44

_B_A2

M

AY47
BA44

_B_A10

M

AW46

_B_A1

M

AY46

_B_A0

M

BA46

_B_A3

M

BB46

DR1_MA[3]
DR1_MA[4]

DR1_PAR

BA47

BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

_B_A4

M

_A_DQS_DN4

M

_A_DQS_DP4

M

_A_DQS_DN5

M

_A_DQS_DP5

M

_B_DQS_DN4

M

_B_DQS_DP4

M

_B_DQS_DN5

M

_B_DQS_DP5

M

_A_DQS_DN6

M

_A_DQS_DP6

M

_A_DQS_DN7

M

_A_DQS_DP7

M

_B_DQS_DN6

M

_B_DQS_DP6

M

_B_DQS_DN7

M

_B_DQS_DP7

M

M_DRAMRST#

S

M_RCOMP_0

S

M_RCOMP_1

S

M_RCOMP_2

S

#543016

Design Guideline:
SM_RCOMP keep routing length less than 500 mils.

_B_CLK#0 [13]

M

_B_CLK#1 [13]

M

_B_CLK0 [13]

M

_B_CLK1 [13]

M

_B_CKE0 [13]

M

_B_CKE1 [13]

M

_B_CS#0 [13]

M

_B_CS#1 [13]

M

_B_DIMB_ODT0 [13]

M

_B_DIMB_ODT1 [13]

M

_B_A5 [13]

M

_B_A9 [13]

M

_B_A6 [13]

M

_B_A8 [13]

M

_B_A7 [13]

M

_B_BG0 [13]

M

_B_A12 [13]

M

_B_A11 [13]

M

_B_ACT_N [13]

M

_B_BG1 [13]

M

_B_A13 [13]

M

_B_A15 [13]

M

_B_A14 [13]

M

_B_A16 [13]

M

_B_BA0 [13]

M

_B_A2 [13]

M

_B_BA1 [13]

M

_B_A10 [13]

M

_B_A1 [13]

M

_B_A0 [13]

M

_B_A3 [13]

M

_B_A4 [13]

M

M_A_DQS4

M_A_DQS5

M_B_DQS4

M_B_DQS5

M_A_DQS6

M_A_DQS7

M_B_DQS6

M_B_DQS7

_B_ALERT_N [13]

M

_B_PARITY [13]

M

1 2

501 121R2F-GP

R

1 2

502 80D6R2F-L-GP

R

1 2

503 100R2F-L3-GP

R

Layout Note:

D2V_S3

1

12

505

R

470R2F-GP

1 2

504

R

0R0402-PAD

12

DY

D502

E

AZ5725-01FDR7G-GP

83.05725.0A0

close to CPU

DR4_DRAMRST# [12,13]

D

_A_DQS_DN[7:0] [12]

_A_DQS_DN0

M

_A_DQS_DN1

M

_A_DQS_DN2

M

_A_DQS_DN3

M

_A_DQS_DN4

M

_A_DQS_DN5

M

_A_DQS_DN6

A A

5

4

M

_A_DQS_DN7

M

_A_DQS_DP0

M

_A_DQS_DP1

M

_A_DQS_DP2

M

_A_DQS_DP3

M

_A_DQS_DP4

M

_A_DQS_DP5

M

_A_DQS_DP6

M

_A_DQS_DP7

M

M

_A_DQS_DP[7:0] [12]

M

3

_B_DQS_DN0

M

_B_DQS_DN1

M

_B_DQS_DN2

M

_B_DQS_DN3

M

_B_DQS_DN4

M

_B_DQS_DN5

M

_B_DQS_DN6

M

_B_DQS_DN7

M

_B_DQS_DP0

M

_B_DQS_DP1

M

_B_DQS_DP2

M

_B_DQS_DP3

M

_B_DQS_DP4

M

_B_DQS_DP5

M

_B_DQS_DP6

M

_B_DQS_DP7

M

_B_DQS_DN[7:0] [13]

M

_B_DQS_DP[7:0] [13]

M

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

W

1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2

2

2

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

itle

Title

Title

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

2

2

2

A

A

A

Date: Sheet

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

PU_(DDR)

PU_(DDR)

PU_(DDR)

C

C

C

egas SKL/KBL-U

egas SKL/KBL-U

egas SKL/KBL-U

V

V

V

1

00

00

00

A

A

A

f

f

f

5 105Wednesday, November 08, 2017

5 105Wednesday, November 08, 2017

5 105Wednesday, November 08, 2017

o

o

o

5

Main Func = CPU

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

1
1

1

R

1

SVD_TP_ BA70

R

1

SVD_TP_ BA68

R

1

SVD_F65

R

1

SVD_G65

C

FG0

C

FG1

C

FG2

C

FG3

C

FG4

C

FG5

C

FG6

C

FG7

C

FG8

C

FG9

C

FG10

C

FG11

C

FG12

C

FG13

C

FG14

C

FG15

C

FG16

C

FG17

C

FG18

C

FG19

C

FG_RCOM P

I

TP_PMOD E

T

P618TPAD14 -OP-GP

T

P619TPAD14 -OP-GP

T

P620TPAD14 -OP-GP

T

P621TPAD14 -OP-GP

T

P622TPAD14 -OP-GP

T

P623TPAD14 -OP-GP

T

P624TPAD14 -OP-GP

T

P625TPAD14 -OP-GP

D D

C C

PCH strap pin:

B B

C

FG3

12

R

604

1KR2J-1-G P

DY

T

P626TPAD14 -OP-GP

T

P627TPAD14 -OP-GP

T

P628TPAD14 -OP-GP

T

P629TPAD14 -OP-GP

T

P630TPAD14 -OP-GP

T

P631TPAD14 -OP-GP

T

P632TPAD14 -OP-GP

T

P633TPAD14 -OP-GP

T

P634TPAD14 -OP-GP

T

P635TPAD14 -OP-GP

T

P636TPAD14 -OP-GP

T

P637TPAD14 -OP-GP

1 2

R

601

49D9R2F -L1-GP

T

P638TPAD14 -OP-GP

T

P601TPAD14 -OP-GP

T

P602TPAD14 -OP-GP

T

P612TPAD14 -OP-GP

T

P613TPAD14 -OP-GP

[BDW Only]PHYSI CAL_DEBUG_ENAB LED (DFX PRIV ACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MS R

G69

G68

G71

G70

AY2
AY1

AL25
AL27

BA70
BA68

G65

D65
D67
E70
C68
D68
C67
F71

F70

H70

H69

E63
F63

E66
F66

E60

K46
K45

C71
B70

F60

A52

F65

F61
E61

E68
B67

J71
J68

E8

D1
D3

4

C

PU1S

C

FG[0]

C

FG[1]

C

FG[2]

C

FG[3]

C

FG[4]

C

FG[5]

C

FG[6]

C

FG[7]

C

FG[8]

C

FG[9]

C

FG[10]

C

FG[11]

C

FG[12]

C

FG[13]

C

FG[14]

C

FG[15]

C

FG[16]

C

FG[17]

C

FG[18]

C

FG[19]

C

FG_RCOMP

I

TP_PMODE

R

SVD#AY2

R

SVD#AY1

R

SVD#D1

R

SVD#D3

R

SVD#K46

R

SVD#K45

R

SVD#AL25

R

SVD#AL27

R

SVD#C71

R

SVD#B70

R

SVD#F60

R

SVD#A52

R

SVD_TP#BA70

R

SVD_TP#BA68

R

SVD#J71

R

SVD#J68

V

SS

V

SS

R

SVD#F61

R

SVD#E61

SKYLAKE-U-GP

RESERVED SIGNALS-1

SKYLAKE_ULT

R

SVD_TP_AW71

RSVD_TP_AW70

1

9 OF 20

R

SVD_TP#BB68

R

SVD_TP#BB69

R

SVD_TP#AK13

R

SVD_TP#AK12

R

SVD#BB2

R

SVD#BA3

R

SVD#D5

R

SVD#D4

R

SVD#B2

R

SVD#C2

R

SVD#B3

R

SVD#A3

R

SVD#AW1

R

SVD#E1

R

SVD#E2

R

SVD#BA4

R

SVD#BB4

R

SVD#A4

R

SVD#C4

R

SVD#A69

R

SVD#B69

R

SVD#AY3

R

SVD#D71

R

SVD#C70

R

SVD#C54

R

SVD#D54

R

SVD_TP#AW71

R

SVD_TP#AW70

P

ROC_SELECT#

3

0

607 Delete TP

BB68
BB69

AK13
AK12

BB2
BA3

AU5

T

P5

AT5

T

P6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

T

P4

A69
B69

AY3

D71
C70

C54
D54

T

AY4
BB3

AY71
AR56

AW71
AW70

AP56
C64

P1_AY4

T

P2_BB3

V

SS_AY71

Z

VM#

R

SVD_TP_ AW71

R

SVD_TP_ AW70

M

SM#

P

ROC_SEL ECT#

T

P1

T

P2

V

SS

Z

VM#

M

SM#

1

T

P610 TPAD14-OP-GP

1

T

P611 TPAD14-OP-GP

1 2

R

602 0R0402-PAD

1

T

P616 TPAD14-OP-GP

1

T

P614 TPAD14-OP-GP

1

T

P615 TPAD14-OP-GP

1

T

P617 TPAD14-OP-GP

1 2

R

603 100KR2J-1-G P

DY

2

+

VCCST_C PU

1

#54469 CRB.

0515 DY

1 : DISABLED

C

FG4

12

R

605

1KR2J-1-G P

(#543016)

DISPLAY PORT PR ESENCE STRAP

0 : ENABLED

CFG[4]

An external Dis play Port devi ce is connect ed to the Embe dded Display P ort.

1 : DISABLED (D efault)
No Physical Dis play Port atta ched to Embed ded DisplayPor t*. No connect for disable.

CFG TERMINATIONS

20140807 david

A A

SKL(#543016):
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

5

#544669 Rev0.52 (CRB)

4

<Core Design>

<Core Design>

<Core Design>

W

W

W

istron Corporation

istron Corporation

istron Corporation

2

2

2

1F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

1F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A

A

A

3

3

3

Date: Sheet

Date: Sheet

3

2

Date: Sheet

C

C

C

PU_(RESERVED)

PU_(RESERVED)

PU_(RESERVED)

V

V

V

egas SKL/KBL-U

egas SKL/KBL-U

egas SKL/KBL-U

6 105W ednesday, November 08, 2017

6 105W ednesday, November 08, 2017

6 105W ednesday, November 08, 2017

1

00

00

00

A

A

o

o

o

A

f

f

f

Main Func = CPU

5

CPU1L

VCC_CORE VCC_CORE

A30
A34
A39

A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40

VCC_CORE

+VCCGT

AM32
AM33
AM35
AM37
AM38

AK32

AB62

AC63
AE63

AE62
AG62

AL63
AJ62

G30

K32

P62

V62

H63

G61

D D

C C

VCC_SENSE[46]

VSS_SENSE[46]

VSSSA_SENSE[46]

VCCSA_SENSE[46]

VCCGT_SENSE[46]
VSSGT_SENSE[46]

20170427
FOR KBL U22 U42

+V_EDRAM_VR
3A

+V1.8S_EDRAM

Symbol error for layout NC

140mA

+V_EOPIO_VR
3A

CPU POWER 1 OF 4

VCC
VCC

SKYLAKE_ULT

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD#K32

RSVD_K32

RSVD#AK32

RSVD_AK32

VCCOPC
VCCOPC
VCCOPC

VCC_OPC_1P8

VCC_OPC_1P8

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO
VCCEOPIO

VCCEOPIO_SENSE
VSSEOPIO_SENSE

SKYLAKE-U-GP

1 2

R710 100R2F-L3-GP

1 2

R711 100R2F-L3-GP

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
impedance= 50 ohm

3. Length matc h<25mil

1 2

R712 100R2F-L3-GP

1 2

R713 100R2F-L3-GP

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
impedance= 50 ohm

3. Length matc h<25mil

12 OF 20

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG

VCC_SENSE
VSS_SENSE

VCCGT_SENSE
VSSGT_SENSE

4

20170427

For U22 & U42

1 2

DY

GT_CORE

+VCCGT

GT_CORE

+VCCGT

GT_CORE

U22_POWER_K52

+VCCGT

VCCGT_SENSE
VSSGT_SENSE

G32

VCC

G33

VCC

G35

VCC

G37

VCC

G38

VCC

G40

VCC

G42

VCC

J30

VCC

J33

VCC

J37

VCC

J40

VCC

K33

VCC

K35

VCC

K37

VCC

K38

VCC

K40

VCC

K42

VCC

K43

VCC

VCC_SENSE

E32

VSS_SENSE

E33

H_CPU_SVIDALRT#

B63

H_CPU_SVIDCLK

A63
D64

G20

H_CPU_SVIDDAT

+VCCFUSEPRG

1 2

R703
0R0402-PAD

+VCCSTG

+VCCGT

R721
0R2J-L-GP

follow INTEL suggestion

AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

A48
A53
A58
A62

A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71

J43

J45

J46

J48

J50

J52

J53

J55

J56

J58

J60

K48

K50

K52

K53

K55

K56

K58

K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62

N63

N64

N66

N67

N69

J70

J69

3

CPU1M

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKYLAKE-U-GP

CPU POWER 2 OF 4

SKYLAKE_ULT

13 OF 20

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX

VCCGTX_SENSE
VSSGTX_SENSE

+VCCGT

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

GTX_CORE

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58

GTX_CORE

AK60
AK70
AL43
AL46
AL50
AL53

GTX_CORE

AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58

For U42 only

AU63
BB57
BB66

AK62
AL61

+VDDQ_CPU_CLK

12

C722

DY

SC1U10V2KX-1GP

2

1D2V_S3

C719

SC1U10V2KX-1GP

12

DY

+VDDQ_CPU_CLK1D2V_S3

1 2

R705
0R0603-PAD

12

C715SC10U6D3V3MX-GP

DY

+VCCST_CPU

12

C716SC1U10V2KX-1GP

DY

+VCCSTG

12

C717SC1U10V2KX-1GP

DY

1D2V_S3

12

C718SCD1U16V2KX-3GP

DY

+V1.00U_CPU

0.12 A

12

C720

SCD1U16V2KX-3GP

DY

VCC_CORE GT_CORE +VCCGT

U42

1 2

R718
D0002R5J-GP-U

VCC_CORE GTX_CORE

U42

1 2

R720
D0002R5J-GP-U

0.04 A

12

C721

SCD1U16V2KX-3GP

R719
D0002R5J-GP-U

AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51

AM40

A18

A22

AL23

K20
K21

U22

1 2

CPU1N

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQC

VCCST

VCCSTG

VCCPLL_OC

VCCPLL
VCCPLL

SKYLAKE-U-GP

CPU POWER 3 OF 4

SKYLAKE_ULT

VCCSA_SENSE
VSSSA_SENSE

14 OF 20

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

1

+VCCIO(ICCMAX.=2.73A

+VCCIO

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

R716 100R2F-L3-GP
R717 100R2F-L3-GP

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
impedance= 50 ohm

3. Length matc h<25mil

AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25

???

K27
K28

20170508

K30

待確認

AM23
AM22

KYLOREN

VSSSA_SENSE

H21

VCCSA_SENSE

H20

1 2
1 2

Layout Note:

+VCCSA

+VCCSA

Layout Note:
The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).

B B

Route the Alert signal betwe en the Clock and the Data si gnals.

SVID DATA

+VCCST_CPU

CLOSE TO CPU

12

R726
100R2F-L3-GP

#544669

H_CPU_SVIDDAT

SVID CLOCK

H_CPU_SVIDCLK

A A

H_CPU_SVIDALRT#

5

R709
0R0402-PAD

1 2

1 2

R728
220R2J-L2-GP

1 2

R732

0R0402-PAD

+VCCST_CPU

+VCCST_CPU

12

12

R723

DY

54D9R2F-L1-GP

R727
56R2J-4-GP

VR_SVID_DATA [46]

#544669
CLOSE TO VR

#544669
CLOSE TO CPU

VR_SVID_ALERT# [46]

VR_SVID_CLK [46]

SVID_543016:

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A2

A2

A2

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017
Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(VCC_CORE)

CPU(VCC_CORE)

CPU(VCC_CORE)

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

1

7 105

7 105

7 105

A00

A00

A00

5

Main Func = CPU

4

3

2

1

CPU1A

HDMI_DATA2#[57]
HDMI_DATA2[57]

D D

HDMI

DP to VGA

HDMI

C C

+VCCIO

B B

HDMI_DATA1#[57]
HDMI_DATA1[57]
HDMI_DATA0#[57]
HDMI_DATA0[57]
HDMI_CLK#[57]
HDMI_CLK[57]

PCH_DPC_N0[56]
PCH_DPC_P0[56]
PCH_DPC_N1[56]
PCH_DPC_P1[56]

CPU_DP1_CTRL_CLK[57]
CPU_DP1_CTRL_DATA[57]

R801

1 2

24D9R2F-L-GP

3D3V_S0

2 3
1

2 3
1

TPAD14-OP-GP
TP802

RN801

4

SRN2K2J-1-GP

RN803

Vegas

SRN2K2J-1-GP

4

CPU_DP2_CTRL_CLK SIO_EXT_SMI#_R
CPU_DP2_CTRL_DATA

DDPD_CTRLDATA

1

EDP_COMP

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_DATA
CPU_DP2_CTRL_CLK

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

SKYLAKE-U-GP

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.

Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.

(#543016) eDP_RCOMP Guideline

Signal Trace

Width

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%

Isolation
Spacing

Resistor
Value

Length

Max = 100 mils

SKYLAKE_ULT

DDI

DISPLAY SIDEBANDS

Strap

Strap

Strap

EDP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

Strap pin:

Port B /
Port C Detected

DDPB_CTRLDATA

DDPC_CTRLDATA

1 OF 20

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN

DDI1_AUXP

DDI2_AUXN

DDI2_AUXP

RSVD#G46

RSVD#F46

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

SIO_EXT_SMI#_R

CPU_DP2_HPD

Sampled at rising edge of PCH_PW ROK

*

*

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

EDP_DISP_UTIL

B52

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

1 2

R802 10KR2J-L-GP

1 2

R806 100KR2J-1-GP

Vegas

0 = Port B is not detected.
1 = Port B is detected.

0 = Port C is not detected.
1 = Port C is detected.

eDP_TX_CPU_N0 [55]
eDP_TX_CPU_P0 [55]
eDP_TX_CPU_N1 [55]
eDP_TX_CPU_P1 [55]

eDP_AUX_CPU_N [55]
eDP_AUX_CPU_P [55]

1

TP801 TPAD14-OP-GP

PCH_DPC_AUXN [56]
PCH_DPC_AUXP [56]

CPU_DP1_HPD [57]
CPU_DP2_HPD [56]

EDP_HPD [55]

L_BKLT_EN [24]
L_BKLT_CTRL [55]
EDP_VDD_EN [55]

3D3V_S0

(#543016) DDI Disabling and Termination Guidelines

Port Strap Enable Port Disable Port

A A

Port 1

Port 2

DDPB_CTRLDATA

DDPC_CTRLDATA

5

PU to 3.3 V with 2.2-k
±5% resistor

PU to 3.3 V with 2.2-k
±5% resistor

4

NC

NC

These two signals have weak internal pull-down.

3

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU_(DISPLAY)

CPU_(DISPLAY)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

CPU_(DISPLAY)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

8 105Wednesday, November 08, 2017

8 105Wednesday, November 08, 2017

8 105Wednesday, November 08, 2017

1

A00

A00

A00

5

4

3

2

1

Main Func = CPU

VCC_COR E

D D

C C

+VCCGT

CORE

PC1002

12

12

12

U42

PC1017

PC1066

U42

PC1003

12

PC1018

12

PC1067

12

PC1001

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1016

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1040

12

U42

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

SLICED GT

PC1033

PC1032

PC1031

12

12

12

U-line 23e 28W
IccMax current- 10ms max = 34 A

PC1007

PC1006

PC1005

PC1004

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1020

PC1019

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1068

PC1097

12

12

DY

U42

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1041

PC1034

12

12

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1022

PC1021

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1099

12

U42

U-line 23e 28W
IccMax current- 10ms max[A] = 67 A

PC1043

PC1042

12

12

PC1009

PC1008

12

12

PC1024

PC1023

12

12

+VCCIO(ICCMAX.=2.73A)

PC1035

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1044

PC1069

12

12

PC1010

PC1011

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

22U 0603 x 22

PC1025

PC1026

12

12

DY

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1037

PC1036

12

12

DY

PC1070

PC1071

12

12

DY

PC1012

PC1013

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1028

PC1027

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

1D0V_S5+VCCIO

PC1038

12

SC22U6D 3V3MX-1-DL-GP
SC22U6D 3V3MX-1-DL-GP

22U 0603 x28

PC1072

PC1073

12

12

DY

PC1014

12

PC1029

12

PC1039

12

20170810
New Common Part

PC1074

12

DY

PC1015

12

PC1030

12

PC1075

12

+VCCSA

1D2V_S3

PC1055

12

12

SC10U6D 3V3MX-GP
SC10U6D 3V3MX-GP
SC10U6D 3V3MX-GP

PC1045

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

10U 0603 x 4

PC1057

PC1058

12

VCCSA

PC1047

PC1046

12

PC1048

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1059

PC1056

12

12

DY

SC4D7P5 0V2BN-GP
SC4D7P5 0V2BN-GP
SC4D7P5 0V2BN-GP
SC4D7P5 0V2BN-GP

22U 0603 x 8

PC1049

12

PC1060

12

DY

PC1050

12

PC1061

12

DY

DY

PC1051

PC1052

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1063

PC1062

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

DY

PC1054

12

DY

PC1098

12

PC1064

12

(#543016 PDG)

PC1084

12

PC1065

12

U42

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1085

PC1086

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

4

PC1087

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1088

PC1089

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1090

12

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(Power CAP1)

CPU_(Power CAP1)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

CPU_(Power CAP1)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

10 105Wedn esday, November 08, 20 17

10 105Wedn esday, November 08, 20 17

10 105Wedn esday, November 08, 20 17

1

A00

A00

A00

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

B B

PC1076

PC1077

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1092

PC1091

12

12

DY

DY

PC1078

12

PC1093

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1079

PC1080

12

12

DY

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1094

PC1095

12

12

DY

DY

PC1081

12

PC1096

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1083

PC1082

12

12

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

PC1053

12

U42

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

A A

5

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

SC22U6D 3V3MX-1-GP
SC22U6D 3V3MX-1-GP

5

Main Func = CPU

4

3

2

1

PCH DERIVED RAILS

1D0V_S5

D D

R1101

1 2

0R1206-PAD

1 2

R1117
0R0603-PAD-2-GP-U

+V1.00A_SIP

12

C1108
SC22U6D3V3MX-1-GP

+VCCGT+VCCPRIM_CORE

C1136

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

1U 0402 x 6

C1138

12

12

DY

DY

C1147

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1148

DY

12

12

C1150

C1149

VCCIOUNSLICED GT

+VCCIO

+VCCIO(ICCMAX.=2.73A)

C1152

C1151

12

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1154

C1153

12

12

+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)

3D3V_S5_PCH +V3.3A_SIP

C C

1D8V_S5 +V1.8A_SIP

B B

1 2

R1110
0R0603-PAD-2-GP-U

R1139

1 2

0R0603-PAD-2-GP-U

C1104

SC22U6D3V3MX-1-GP

12

C1182

SC22U6D3V3MX-1-GP

C1174

12

C1106

SC22U6D3V3MX-1-GP

12

Layout Note:

1uF:
C1174 near N15
C1180 near K15
C1173 near AF20
C1172 near N18
C1175 near AB19
22uF :
C1182 C1184 near N15
10uF:
C1176 near N15

SC1U10V2KX-1GP

12

+VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP

C1173

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1180

12

C1184

SC22U6D3V3MX-1-GP

C1172

12

SC1U10V2KX-1GP

12

C1176

SC10U6D3V3MX-GP

C1175

12

SC1U10V2KX-1GP

12

VCC_CORE

A A

1U 0402 x 5

U-line 23e 28W
IccMax current-10ms max = 34 A

C1102

C1101

12

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

5

C1103

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP

+VCCPRIM_CORE

C1117

C1116

12

12

PC1105

12

SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP

PC1106

12

+V3.3A_SIP

C1183

SC10U6D3V3MX-GP

12

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU_(Power CAP2)

CPU_(Power CAP2)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

4

3

Date: Sheet of

2

CPU_(Power CAP2)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

11 105Wednesday, November 08, 2017

11 105Wednesday, November 08, 2017

11 105Wednesday, November 08, 2017

1

A00

A00

A00

5

4

3

2

1

Main Func = DDR4 SODIMM

DM1A

M_A_A0[5]
M_A_A1[5]
M_A_A2[5]
M_A_A3[5]
M_A_A4[5]
M_A_A5[5]
M_A_A6[5]
M_A_A7[5]
M_A_A8[5]

D D

C C

1D2V_S3

1 2

R1215

DY

240R2F-1-GP

DDR4_DRAMRST#

12

ED1217

AZ5725-01FDR7G-GP

B B

M_A_A9[5]
M_A_A10[5 ]
M_A_A11[5 ]
M_A_A12[5 ]
M_A_A13[5 ]
M_A_A14[5 ]
M_A_A15[5 ]
M_A_A16[5 ]

M_A_BA0[5]
M_A_BA1[5]
M_A_BG0[5]
M_A_BG1[5]

M_A_CLK0[5]
M_A_CLK#0[5]
M_A_CLK1[5]
M_A_CLK#1[5]

M_A_CKE0[5]
M_A_CKE1[5]

M_A_CS#0[5]
M_A_CS#1[5]

M_A_DIMA_ODT0[5]
M_A_DIMA_ODT1[5]

DDR4_DRAMRST#[5,13]
M_A_ACT_N[5]
M_A_ALERT_N[5]

M_A_PARITY[5]

PCH_SMBDATA[13,18,56,65,67]
PCH_SMBCLK[13,18,56,65,67]

SA0_CHA_DIM0
SA1_CHA_DIM0
SA2_CHA_DIM0

TS#_DIMM0_1

M_VREF_CA_DIMMA

12

C1229
SCD1U16V2KX-3GP

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

WE#/A14

156

CAS#/A15

152

RAS#/A16

150

BA0

145

BA1

115

BG0

113

BG1

92

CB0/NC

91

CB1/NC

101

CB2/NC

105

CB3/NC

88

CB4/NC

87

CB5/NC

100

CB6/NC

104

CB7/NC

137

CK0_T

139

CK0_C

138

CK1_T/NF

140

CK1_C/NF

109

CKE0

110

CKE1

149

CS0#

157

CS1#

162

C0/CS2#/NC

165

C1/CS3#/NC

155

ODT0

161

ODT1

256

SA0

260

SA1

166

SA2

254

SDA

253

SCL

108

RESET#

114

ACT#

116

ALERT#

134

EVENT#/NF

143

PARITY

164

VREFCA

DDR4-260P-65-GP

062.10011.01C1

Layout note: closed to Dimm

1D2V_S3

RN1201

1

4

2 3

SRN1KJ-7-GP

A A

M_VREF_CA_DIMMA

R1206
2R2F-GP

1 2

5

12

C1222
SCD022U16V2KX-3GP

+V_VREF_PATH1

12

R1209
24D9R2F-L-GP

V_SM_VREF_CNTA [5]

1 OF 4

8

DQ0

7

DQ1

20

DQ2

21

DQ3

4

DQ4

3

DQ5

16

DQ6

17

DQ7

28

DQ8

29

DQ9

41

DQ10

42

DQ11

24

DQ12

25

DQ13

38

DQ14

37

DQ15

50

DQ16

49

DQ17

62

DQ18

63

DQ19

46

DQ20

45

DQ21

58

DQ22

59

DQ23

70

DQ24

71

DQ25

83

DQ26

84

DQ27

66

DQ28

67

DQ29

79

DQ30

80

DQ31

174

DQ32

173

DQ33

187

DQ34

186

DQ35

170

DQ36

169

DQ37

183

DQ38

182

DQ39

195

DQ40

194

DQ41

207

DQ42

208

DQ43

191

DQ44

190

DQ45

203

DQ46

204

DQ47

216

DQ48

215

DQ49

228

DQ50

229

DQ51

211

DQ52

212

DQ53

224

DQ54

225

DQ55

237

DQ56

236

DQ57

249

DQ58

250

DQ59

232

DQ60

233

DQ61

245

DQ62

246

DQ63

???跟sw

3D3V_S0

3D3V_S0

3D3V_S0

確認

1 2

R1204 10KR2F-L1-GP

DY

1 2

R1205 0R0402-PAD

1 2

R1208 10KR2F-L1-GP

DY

1 2

R1210 0R0402-PAD

1 2

R1211 10KR2F-L1-GP

DY

1 2

R1212 0R0402-PAD

4

M_A_DQ0 [ 5]
M_A_DQ1 [ 5]
M_A_DQ2 [ 5]
M_A_DQ3 [ 5]
M_A_DQ4 [ 5]
M_A_DQ5 [ 5]
M_A_DQ6 [ 5]
M_A_DQ7 [ 5]
M_A_DQ8 [ 5]
M_A_DQ9 [ 5]
M_A_DQ10 [5]
M_A_DQ11 [5]
M_A_DQ12 [5]
M_A_DQ13 [5]
M_A_DQ14 [5]
M_A_DQ15 [5]
M_A_DQ16 [5]
M_A_DQ17 [5]
M_A_DQ18 [5]
M_A_DQ19 [5]
M_A_DQ20 [5]
M_A_DQ21 [5]
M_A_DQ22 [5]
M_A_DQ23 [5]
M_A_DQ24 [5]
M_A_DQ25 [5]
M_A_DQ26 [5]
M_A_DQ27 [5]
M_A_DQ28 [5]
M_A_DQ29 [5]
M_A_DQ30 [5]
M_A_DQ31 [5]
M_A_DQ32 [5]
M_A_DQ33 [5]
M_A_DQ34 [5]
M_A_DQ35 [5]
M_A_DQ36 [5]
M_A_DQ37 [5]
M_A_DQ38 [5]
M_A_DQ39 [5]
M_A_DQ40 [5]
M_A_DQ41 [5]
M_A_DQ42 [5]
M_A_DQ43 [5]
M_A_DQ44 [5]
M_A_DQ45 [5]
M_A_DQ46 [5]
M_A_DQ47 [5]
M_A_DQ48 [5]
M_A_DQ49 [5]
M_A_DQ50 [5]
M_A_DQ51 [5]
M_A_DQ52 [5]
M_A_DQ53 [5]
M_A_DQ54 [5]
M_A_DQ55 [5]
M_A_DQ56 [5]
M_A_DQ57 [5]
M_A_DQ58 [5]
M_A_DQ59 [5]
M_A_DQ60 [5]
M_A_DQ61 [5]
M_A_DQ62 [5]
M_A_DQ63 [5]

DDR4 SWAP 0212

1D2V_S3

SA0_CHA_DIM0

SA1_CHA_DIM0

SA2_CHA_DIM0

DM1B

DDR4-260P-65-GP

DM1C

111

VDD

112

VDD

117

VDD

118

VDD

123

VDD

124

VDD

129

VDD

130

VDD

135

VDD

136

VDD

141

VDD

142

VDD

147

VDD

148

VDD

153

VDD

154

VDD

159

VDD

160

VDD

163

VDD

DDR4-260P-65-GP

1D2V_S3

M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7

2 OF 4

DQS0_C
DQS0_T
DQS1_C
DQS1_T
DQS2_C
DQS2_T
DQS3_C
DQS3_T
DQS4_C
DQS4_T
DQS5_C
DQS5_T
DQS6_C
DQS6_T
DQS7_C
DQS7_T
DQS8_C
DQS8_T

DM0#/DBI0#

DM1#/DBI#
DM2#/DBI2#
DM3#/DBI3#
DM4#/DBI4#
DM5#/DBI5#
DM6#/DBI6#
DM7#/DBI7#

DM8#/DBI#/NC

VDDSPD

C1202

12

12

DY

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

C1214

12

12

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

3 OF 4

VPP
VPP

VTT

NP1
NP2

C1203

C1215

261
262

M_A_DQS_DN0

11

M_A_DQS_DP0

13

M_A_DQS_DN1

32

M_A_DQS_DP1

34

M_A_DQS_DN2

53

M_A_DQS_DP2

55

M_A_DQS_DN3

74

M_A_DQS_DP3

76

M_A_DQS_DN4

177

M_A_DQS_DP4

179

M_A_DQS_DN5

198

M_A_DQS_DP5

200

M_A_DQS_DN6

219

M_A_DQS_DP6

221

M_A_DQS_DN7

240

M_A_DQS_DP7

242
95
97

12
33
54
75
178
199
220
241
96

255

257
259

258

261
262

NP1
NP2

C1204

12

C1216

12

3

DY

1D2V_S3

2D5V_S3

0D6V_S0

C1206

C1205

12

12

DY

SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP

C1217

C1218

12

12

DY

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

M_A_DQS_DN[7:0] [5]

12

DY

12

12

C1228

SCD1U16V2KX-3GP

C1208

12

DY

C1219

12

DY

M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7

3D3V_S0

12

DY

C1209

C1220

C1201

SC2D2U10V3KX-L-GP

UN 0225

C1210

12

C1230

C1223

12

12

DY

DY

SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP

for placement modify 2015/10/19

C1221

12

2D5V_S3

C1211

C1212

12

DY

12

12

DY

DY

SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP

M_A_DQS_DP[7:0] [5]

0D6V_S00D6V_S0

DY

SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP

C1231

C1232

12

DY

2

1
2
5
6

9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

C1224

12

DM1D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DDR4-260P-65-GP

C1227

12

DY

C1207

12

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1213

4 OF 4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

20170502 DM1

99

062.10011.00U1>

102
103

062.10011.01C1

106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

0D6V_S0

C1226

C1225

12

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDR4-SODIMM1

DDR4-SODIMM1

DDR4-SODIMM1

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

12 106

12 106

12 106

A00

A00

A00

5

Main Func = DDR4 SODIMM

DM2A

TS#_DIMM1_1

12

+V_VREF_PATH2

12

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

WE#/A14

156

CAS#/A15

152

RAS#/A16

150

BA0

145

BA1

115

BG0

113

BG1

92

CB0/NC

91

CB1/NC

101

CB2/NC

105

CB3/NC

88

CB4/NC

87

CB5/NC

100

CB6/NC

104

CB7/NC

137

CK0_T

139

CK0_C

138

CK1_T/NF

140

CK1_C/NF

109

CKE0

110

CKE1

149

CS0#

157

CS1#

162

C0/CS2#/NC

165

C1/CS3#/NC

155

ODT0

161

ODT1

256

SA0

260

SA1

166

SA2

254

SDA

253

SCL

108

RESET#

114

ACT#

116

ALERT#

134

EVENT#/NF

143

PARITY

164

VREFCA

DDR4-260P-64-GP

062.10011.01B1

V_SM_VREF_CNTB [5]

C1323
SCD022U16V2KX-3GP

R1309
24D9R2F-L-GP

M_B_A0[5]
M_B_A1[5]
M_B_A2[5]
M_B_A3[5]
M_B_A4[5]
M_B_A5[5]
M_B_A6[5]
M_B_A7[5]
M_B_A8[5]

D D

C C

1D2V_S3

1 2

R1312

DY

240R2F-1-GP

DDR4_DRAMRST#

12

ED1302

B B

Layout note: closed to Dimm

0921 Install

1D2V_S3

RN1301

1

4

2 3

SRN1KJ-7-GP

M_B_A9[5]
M_B_A10[5 ]
M_B_A11[5 ]
M_B_A12[5 ]
M_B_A13[5 ]
M_B_A14[5 ]
M_B_A15[5 ]
M_B_A16[5 ]

M_B_BA0[5]
M_B_BA1[5]
M_B_BG0[5]
M_B_BG1[5]

M_B_CLK0[5]
M_B_CLK#0[5]
M_B_CLK1[5]
M_B_CLK#1[5]

M_B_CKE0[5]
M_B_CKE1[5]

M_B_CS#0[5]
M_B_CS#1[5]

M_B_DIMB_ODT0[5]
M_B_DIMB_ODT1[5]

PCH_SMBDATA[12,1 8,56,65,67]
PCH_SMBCLK[12,18,56,65,67]

DDR4_DRAMRST#[5,12,13]
M_B_ACT_N[5]
M_B_ALERT_N[5]

M_B_PARITY[5]

AZ5725-01FDR7G-GP

M_VREF_CA_DIMMB M_B_DQS_DN3

SA0_CHB_DIM0
SA1_CHB_DIM0
SA2_CHB_DIM0

M_VREF_CA_DIMMB

12

C1301
SCD1U16V2KX-3GP

R1305

1 2

2R2F-GP

1 OF 4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

4

8
7
20
21
4
3
16
17
28
29
41
42
24
25
38
37
50
49
62
63
46
45
58
59
70
71
83
84
66
67
79
80
174
173
187
186
170
169
183
182
195
194
207
208
191
190
203
204
216
215
228
229
211
212
224
225
237
236
249
250
232
233
245
246

跟sw確認

3D3V_S0

R1302 10KR2F-L1-GP

R1303 0R0402-PAD

3D3V_S0

R1306 10KR2F-L1-GP

R1307 0R2J-L-GP

3D3V_S0

R1310 10KR2F-L1-GP

R1311 0R0402-PAD

M_B_DQ8 [5]

M_B_DQ9 [5]
M_B_DQ10 [5]
M_B_DQ11 [5]
M_B_DQ12 [5]
M_B_DQ13 [5]
M_B_DQ14 [5]
M_B_DQ15 [5]

M_B_DQ0 [5]

M_B_DQ1 [5]

M_B_DQ2 [5]

M_B_DQ3 [5]

M_B_DQ4 [5]

M_B_DQ5 [5]

M_B_DQ6 [5]

M_B_DQ7 [5]
M_B_DQ16 [5]
M_B_DQ17 [5]
M_B_DQ18 [5]
M_B_DQ19 [5]
M_B_DQ20 [5]
M_B_DQ21 [5]
M_B_DQ22 [5]
M_B_DQ23 [5]
M_B_DQ24 [5]
M_B_DQ25 [5]
M_B_DQ26 [5]
M_B_DQ27 [5]
M_B_DQ28 [5]
M_B_DQ29 [5]
M_B_DQ30 [5]
M_B_DQ31 [5]
M_B_DQ32 [5]
M_B_DQ33 [5]
M_B_DQ34 [5]
M_B_DQ35 [5]
M_B_DQ36 [5]
M_B_DQ37 [5]
M_B_DQ38 [5]
M_B_DQ39 [5]
M_B_DQ40 [5]
M_B_DQ41 [5]
M_B_DQ42 [5]
M_B_DQ43 [5]
M_B_DQ44 [5]
M_B_DQ45 [5]
M_B_DQ46 [5]
M_B_DQ47 [5]
M_B_DQ48 [5]
M_B_DQ49 [5]
M_B_DQ50 [5]
M_B_DQ51 [5]
M_B_DQ52 [5]
M_B_DQ53 [5]
M_B_DQ54 [5]
M_B_DQ55 [5]
M_B_DQ56 [5]
M_B_DQ57 [5]
M_B_DQ58 [5]
M_B_DQ59 [5]
M_B_DQ60 [5]
M_B_DQ61 [5]
M_B_DQ62 [5]
M_B_DQ63 [5]

DDR4 SWAP 0212

1 2

DY

1 2

1 2

1 2

DY

1 2

DY

1 2

1D2V_S3

111
112
117
118
123
124
129
130
135
136
141
142
147
148
153
154
159
160
163

DM2B

DDR4-260P-64-GP

SA0_CHB_DIM0

SA1_CHB_DIM0

SA2_CHB_DIM0

DM2C

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DDR4-260P-64-GP

2 OF 4

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

DQS4_C

DQS4_T

DQS5_C

DQS5_T

DQS6_C

DQS6_T

DQS7_C

DQS7_T

DQS8_C

DQS8_T

DM0#/DBI0#

DM1#/DBI#
DM2#/DBI2#
DM3#/DBI3#
DM4#/DBI4#
DM5#/DBI5#
DM6#/DBI6#
DM7#/DBI7#

DM8#/DBI#/NC

3 OF 4

VDDSPD

11
13
32
34
53
55
74
76
177
179
198
200
219
221
240
242
95
97

12
33
54
75
178
199
220
241
96

1D2V_S3

255

257

VPP

259

VPP

258

VTT

261

261

262

262

NP1

NP1

NP2

NP2

M_B_DQS_DN1
M_B_DQS_DP1
M_B_DQS_DN0
M_B_DQS_DP0
M_B_DQS_DN2
M_B_DQS_DP2
M_B_DQS_DN3
M_B_DQS_DP3
M_B_DQS_DN4
M_B_DQS_DP4
M_B_DQS_DN5
M_B_DQS_DP5
M_B_DQS_DN6
M_B_DQS_DP6
M_B_DQS_DN7
M_B_DQS_DP7

DY

12

DY

3

C1303

12

12

DY

SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP

C1315

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

1D2V_S3

C1304

C1316

2D5V_S3

0D6V_S0

12

12

C1305

C1317

C1329

SC2D2U10V3KX-L-GP

12

DY

M_B_DQS_DN1 [5]
M_B_DQS_DP1 [5]
M_B_DQS_DN0 [5]
M_B_DQS_DP0 [5]
M_B_DQS_DN2 [5]
M_B_DQS_DP2 [5]
M_B_DQS_DN3 [5]
M_B_DQS_DP3 [5]
M_B_DQS_DN4 [5]
M_B_DQS_DP4 [5]
M_B_DQS_DN5 [5]
M_B_DQS_DP5 [5]
M_B_DQS_DN6 [5]
M_B_DQS_DP6 [5]
M_B_DQS_DN7 [5]
M_B_DQS_DP7 [5]

C1306

12

12

DY

C1318

12

12

DY

3D3V_S0

C1328

SCD1U16V2KX-3GP

12

DY

C1307

C1308

12

DY

SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP

C1320

C1319

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

2

1

20170502 DM1

062.10011.00T1>

DM2D

1
2
5
6

9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

DDR4-260P-64-GP

C1325

SC10U6D3V3MX-GP

C1324

SC10U6D3V3MX-GP

12

12

C1310

C1309

12

12

DY

UN 0225

M_B_DQS_DN0
M_B_DQS_DN1

C1321

C1322

12

12

DY

M_B_DQS_DN2

M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7

M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7

12

SC1U10V2KX-1GP
SC1U10V2KX-1GP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C1326

C1327

12

M_B_DQS_DN[7:0] [5]

M_B_DQS_DP[7:0] [5]

4 OF 4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

2D5V_S30D6V_S0 0D6V_S0 0D6 V_S0

C1311

12

12

DY

DY

SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP

062.10011.01B1

C1331

C1312

C1330

12

12

DY

DY

C1313

12

12

DY

SC1U10V2KX-1GP
SC1U10V2KX-1GP

C1314

A A

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

DDR4-SODIMM1

DDR4-SODIMM1

DDR4-SODIMM1

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

13 106

13 106

13 106

A00

A00

A00

5

Main Func = PCH

4

3

2

1

CPU1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

D D

C C

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U-GP

WIFI_RF_ EN[61]

SKYLAKE_ULT

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F12/EMMC_CMD

GPP_F: VCCPGPPF = 1.8V Only

9 OF 20

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

GPP_F22/EMMC_CLK

EMMC_RCOMP

C37
D37
C32
D32
C29
D29

DC resistance < 0.5ohm.

B26
A26

CSI2_COMP

E13

WIFI_RF_ EN

B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

EMMC_RC OMP

AT1

WIFI_RF_ EN

1 2

R1501 100R2F-L 3-GP

EMMC_D0 [63 ]
EMMC_D1 [63 ]
EMMC_D2 [63 ]
EMMC_D3 [63 ]
EMMC_D4 [63 ]
EMMC_D5 [63 ]
EMMC_D6 [63 ]
EMMC_D7 [63 ]

EMMC_RC LK [63 ]
EMMC_CL K [63]
EMMC_CM D [63]

1 2

R1502 200R2F-L -GP

R1503
10KR2J-L -GP

3D3V_S0

1 2

DY

[#545659 Rev0.7 ]

B B

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(CS-2/EMMC)

CPU_(CS-2/EMMC)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU_(CS-2/EMMC)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

15 105Wedn esday, November 08, 20 17

15 105Wedn esday, November 08, 20 17

15 105Wedn esday, November 08, 20 17

1

A00

A00

A00

Main Func = PCH

5

4

3

2

1

#543016:
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2.

PEG_RX_CPU_N0[76]
PEG_RX_CPU_P0[76]

0516 Swap

GPU

LAN

WLAN

HDD1

ODD

PEG_TX_GPU_N0[76]
PEG_TX_GPU_P0[76]

PEG_RX_CPU_N1[76]
PEG_RX_CPU_P1[76]
PEG_TX_GPU_N1[76]
PEG_TX_GPU_P1[76]

PEG_RX_CPU_N2[76]
PEG_RX_CPU_P2[76]
PEG_TX_GPU_N2[76]
PEG_TX_GPU_P2[76]

PEG_RX_CPU_N3[76]
PEG_RX_CPU_P3[76]
PEG_TX_GPU_N3[76]
PEG_TX_GPU_P3[76]

PCIE_RX_CPU_N5[31]
PCIE_RX_CPU_P5[31]
PCIE_TX_CON_N5[31]
PCIE_TX_CON_P5[31]

PCIE_RX_CPU_N6[61]
PCIE_RX_CPU_P6[61]
PCIE_TX_CON_N6[61]
PCIE_TX_CON_P6[61]

SATA_RX_CPU_N0[60]
SATA_RX_CPU_P0[60]
SATA_TX_CPU_N0[60]
SATA_TX_CPU_P0[60]

SATA_RX_CPU_N1[60]
SATA_RX_CPU_P1[60]
SATA_TX_CPU_N1[60]
SATA_TX_CPU_P1[60]

0620 Connect to TPM

PIRQA#[91]

D D

C C

C1606 SCD22U10V2KX-L1-GP
C1605 SCD22U10V2KX-L1-GP

C1608 SCD22U10V2KX-L1-GP
C1607 SCD22U10V2KX-L1-GP

C1610 SCD22U10V2KX-L1-GP
C1609 SCD22U10V2KX-L1-GP

C1612 SCD22U10V2KX-L1-GP
C1611 SCD22U10V2KX-L1-GP

C1601 SCD1U16V2KX-3GP
C1602 SCD1U16V2KX-3GP

C1603 SCD1U16V2KX-3GP
C1604 SCD1U16V2KX-3GP

+V1.8A_SIP

12

R1607
10KR2J-L-GP

1 2

OPS

1 2

OPS

1 2

OPS

1 2

OPS

1 2

OPS

1 2

1 2

OPS

1 2

OPS

1 2
1 2

1 2
1 2

OPS

0511 Remove SSD

1 2

R1604
100R2F-L3-GP

1
1

TP1601TPAD14-OP-GP
TP1602TPAD14-OP-GP

0511 Remove SSD

Layout Note:

1. Trace Width: 4 mils min (b reakout) 12-15 mils (trace)
Note: Must maintain low DC re sistance routing (<0.1 ohm) .

2. Isolation Spacing: At leas t 12 mils to any adjacent
high speed I/O.

PCIE Table

Port

Device

Share BUS

USB3.0_3

N/A

1

2

3

B B

4

5(L0~L3)

6(L3)

6(L2)

6(L0~L1)

USB3.0_4

N/A

WLAN

LAN

GPU

HDD

SATA0

ODD SATA1

N/A

PEG_TX_CPU_N0
PEG_TX_CPU_P0

PEG_TX_CPU_N1
PEG_TX_CPU_P1

PEG_TX_CPU_N2
PEG_TX_CPU_P2

PEG_TX_CPU_N3
PEG_TX_CPU_P3

PCIE_TX_CPU_N5
PCIE_TX_CPU_P5

PCIE_TX_CPU_N6
PCIE_TX_CPU_P6

PCIE_RCOMPN
PCIE_RCOMPP

XDP_PRDY#
XDP_PREQ#
PIRQA#

CPU1H

PCIE/USB3/SATA

H13

PCIE1_ RXN/USB3_ 5_RXN

G13

PCIE1_ RXP/USB3 _5_RX P

B17

PCIE1_ TXN/USB3_ 5_TXN

A17

PCIE1_ TXP/USB3 _5_TX P

G11

PCIE2_ RXN/USB3_ 6_RXN

F11

PCIE2_ RXP/USB3 _6_RX P

D16

PCIE2_ TXN/USB3_ 6_TXN

C16

PCIE2_ TXP/USB3 _6_TX P

H16

PCIE3_ RXN

G16

PCIE3_ RXP

D17

PCIE3_ TXN

C17

PCIE3_ TXP

G15

PCIE4_ RXN

F15

PCIE4_ RXP

B19

PCIE4_ TXN

A19

PCIE4_ TXP

F16

PCIE5_ RXN

E16

PCIE5_ RXP

C19

PCIE5_ TXN

D19

PCIE5_ TXP

G18

PCIE6_ RXN

F18

PCIE6_ RXP

D20

PCIE6_ TXN

C20

PCIE6_ TXP

F20

PCIE7_ RXN/SATA 0_RXN

E20

PCIE7_ RXP/SAT A0_RX P

B21

PCIE7_ TXN/SATA 0_TXN

A21

PCIE7_ TXP/SAT A0_TX P

G21

PCIE8_ RXN/SATA 1A_RX N

F21

PCIE8_ RXP/SAT A1A_R XP

D21

PCIE8_ TXN/SATA 1A_TX N

C21

PCIE8_ TXP/SAT A1A_T XP

E22

PCIE9_ RXN

E23

PCIE9_ RXP

B23

PCIE9_ TXN

A23

PCIE9_ TXP

F25

PCIE10 _RXN

E25

PCIE10 _RXP

D23

PCIE10 _TXN

C23

PCIE10 _TXP

F5

PCIE_R COMPN

E5

PCIE_R COMPP

D56

PROC_P RDY#

D61

PROC_P REQ#

BB11

GPP_A7 /PIRQA#

E28

PCIE11 _RXN/SAT A1B_R XN

E27

PCIE11 _RXP/SA TA1B_ RXP

D24

PCIE11 _TXN/SAT A1B_T XN

C24

PCIE11 _TXP/SA TA1B_ TXP

E30

PCIE12 _RXN/SAT A2_RX N

F30

PCIE12 _RXP/SA TA2_R XP

A25

PCIE12 _TXN/SAT A2_TX N

B25

PCIE12 _TXP/SA TA2_T XP

SKYLAKE-U-GP

USB 2.0 Table

Pair

Device

USB3.0 port1

0

USB3.0 Port2

1

USB2.0 Port3 (IOBD)

2

Finger Print

3

CAMERA

4

Card Reader

5

Touch Panel

6

WLAN

7

SKYLAKE_ULT

SSIC / USB3

USB3_2_ RXN/SSIC _RXN
USB3_2_ RXP/SSI C_RXP
USB3_2_ TXN/SSIC _TXN
USB3_2_ TXP/SSI C_TXP

USB2

USB2_VB USSENSE

GPP_E9 /USB2_OC 0#
GPP_E1 0/USB2_O C1#
GPP_E1 1/USB2_O C2#
GPP_E1 2/USB2_O C3#

GPP_E4 /DEVSLP 0
GPP_E5 /DEVSLP 1
GPP_E6 /DEVSLP 2

GPP_E0 /SATAXP CIE0/S ATAGP 0
GPP_E1 /SATAXP CIE1/S ATAGP 1
GPP_E2 /SATAXP CIE2/S ATAGP 2

GPP_E8 /SATALE D#

8 OF 20

H8

USB3_1_ RXN

G8

USB3_1_ RXP

C13

USB3_1_ TXN

D13

USB3_1_ TXP

J6
H6
B13
A13

J10

USB3_3_ RXN

H10

USB3_3_ RXP

B15

USB3_3_ TXN

A15

USB3_3_ TXP

E10

USB3_4_ RXN

F10

USB3_4_ RXP

C15

USB3_4_ TXN

D15

USB3_4_ TXP

AB9

USB2N_1

AB10

USB2P_1

AD6

USB2N_2

AD7

USB2P_2

AH3

USB2N_3

AJ3

USB2P_3

AD9

USB2N_4

AD10

USB2P_4

AJ1

USB2N_5

AJ2

USB2P_5

AF6

USB2N_6

AF7

USB2P_6

AH1

USB2N_7

AH2

USB2P_7

AF8

USB2N_8

AF9

USB2P_8

AG1

USB2N_9

AG2

USB2P_9

AH7

USB2N_10

AH8

USB2P_1 0

AB6

USBCOMP

USB2_CO MP

USB2_ID

AG3

USB2_ID

USB2_VBUSSENSE

AG4

A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9

J1

SIO_EXT_SCI#

J2
J3

GPP_E0/SATAXPCIE0/SATAGP0

H2
H3
G4

H1

(#543016) Unused SATAGP[2:0]/ GPP_E[2:0] pins must be ter minated to either 3.3 V rail or GND
using 8.2 KΩ to 10 KΩ on the motherboard.
Do not use both pull-up and p ull-down. Either pull-up or pull-down is acceptable.

USB30_RX_CPU_N1 [36]
USB30_RX_CPU_P1 [36]
USB30_TX_CPU_N1 [36]
USB30_TX_CPU_P1 [36]

USB30_RX_CPU_N2 [36]
USB30_RX_CPU_P2 [36]
USB30_TX_CPU_N2 [36]
USB30_TX_CPU_P2 [36]

USB_CPU_PN0 [36]
USB_CPU_PP0 [36]

USB_CPU_PN1 [36]
USB_CPU_PP1 [36]

USB_CPU_PN2 [37]
USB_CPU_PP2 [37]

USB_CPU_PN4 [55]
USB_CPU_PP4 [55]

USB_CPU_PN5 [33]
USB_CPU_PP5 [33]

USB_CPU_PN6 [61]
USB_CPU_PP6 [61]

USB_CPU_PN7 [55]
USB_CPU_PP7 [55]

USB_CPU_PN8 [92]
USB_CPU_PP8 [92]

DC resistance < 0.5ohm.

1 2

R1603 113R2F-GP

1 2

R1601 0R0402-PAD

1 2

R1602 0R0402-PAD

USB_OC0# [35]

USB_OC2# [35]

HDD_DEVSLP [60]

1

USB1 (USB3.0 Port1)

USB2 (USB3.0 Port2)

USB1 (USB3.0 port1)

USB2 (USB3.0 Port2)

USB3 (IO BD/USB2.0 Port3)

CAMERA (USB2.0 Port5)

Card Reader (USB2.0 Port6)

WLAN (USB2.0 Port7)

Touch Screen (USB2.0 Port8)

Finger Print (USB2.0 Port9)

TP1603 TPAD14-OP-GP

SATA_ODD_PRSNT# [60]

SATA_LED#_R [64]

SATA_ODD_PRSNT#

R1608
10KR2J-L-GP

(#543016) When used as DEVSLP , no external pull-up or pu ll-down
termination required from SAT A Host DEVSLP.

1 2

(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.

Unused SATA[3:0]GP pins must be terminated to either

3.3V rail or GND using 8.2K to 10K on the
motherboard. Either pull-up or pull-down is acceptable.

3D3V_S0

USB_OC2#
USB_OC3#
USB_OC0#
USB_OC1#

8
7

RN802

SRN10KJ-6-GP

3D3V_S5_PCH

1
2
3456

SATA_LED#_R

(#543611)
The SATALED# signal is open-c ollector and requires a wea k external pull-up (8.2 kΩ t o 10 kΩ) to Vcc3_3.

R1606
10KR2J-L-GP

1 2

3D3V_S0

SIO_EXT_SCI#

R1610
10KR2J-L-GP

3D3V_S0

1 2

#545659 (SKL_PCH_U_Y_EDS Rev0 .7)

A A

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A1

A1

A1

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(PCIE/SATA/USB)

CPU_(PCIE/SATA/USB)

CPU_(PCIE/SATA/USB)

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

16 105Wednesday, November 08, 2017

16 105Wednesday, November 08, 2017

16 105Wednesday, November 08, 2017

A00

A00

A00

5

Main Func = PCH

3D3V_S5

RN1704

1
2
3
4 5

SRN10KJ -6-GP

D D

BATLOW#:
Pull-up required even if not implemented.

R1711
0R0603-P AD-2-GP-U

Layout note: 3 PAD SHARING

RTC_AUX _S5

R1730 330KR2J -L1-GP

3D3V_S5 _PCH

R1731 20KR2J-L 2-GP

RN1701

1
2 3

C C

SRN10KJ -5-GP

1 2

R1717

DY

10KR2J-L -GP

AC_PRES ENT

8

PCH_W AKE#

7

PCH_BAT LOW#

6

GPD11/LA NPHYPC

GPD11 pull high
by Intel PDG1.3 request

+VCCPDS W_3P33D3V_S5

1 2

#544669 (CRB): 330k.

1 2

0516 Follow Taos DY

1 2

DY

PM_PCH_ PWROK

4

PM_RSMR ST#

SYS_PW ROK

SM_INTRUD ER#

EXT_PW R_GATE#

H_VCCST _PWRGD_R

+VCCPDS W_3P3

LANW AKE#[24]

(PDG#543016)
WAKE#: Ensure t hat WAKE# sign al Trise (Max imum) is <100 ns.

4

+V3.3A_S IP

12

1 2

R1720 10KR2J-L -GP

DY

1 2

R1734 60D4R2F -GP

1 2

R1706 0R0402-P AD

1 2

R1704 0R0402-P AD

DY for OBFF dis able

1 2

R1707 10KR2J-L -GP

1 2

R1710 0R0402-P AD

R1701
10KR2J-L -GP

PCH_PLT RST#
XDP_DBR ESET#
PM_RSMR ST#

H_CPUPW RGD
H_VCCST _PWRGD

SYS_PW ROKSYS_PW ROK
PM_PCH_ PWROKRESET_O UT#
PCH_DPW ROKPM_RSMR ST#

ME_SUS_PW R_ACK_R

SUSACK# _R

PCH_W AKE#
GPD2/LAN _WAKE#
GPD11/LA NPHYPC

3

CPU1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD#AT15

SKYLAKE-U-GP

071.SKYLA.000U

SYSTEM POWER MANAGEMENT

2

11 OF 20

SIO_SLP_S 0#

SLP_SUS#
SLP_LAN#

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

SIO_SLP_S 3#
SIO_SLP_S 4#
SIO_SLP_S 5#

SLP_SUS #
SLP_LAN #
GPD9/SLP _WLAN#
SIO_SLP_A #

SIO_PW RBTN#
AC_PRES ENT
PCH_BAT LOW#

PME#
SM_INTRUD ER#

EXT_PW R_GATE#

PLT_RST #[31,55,61,63,76,91]

SKYLAKE_ULT

[#543016 Rev0.7]
EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k
pull-down that is active during the early portion of the power up sequence

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

1

1

1
1
1
1

1

R1715

100KR2J -1-GP

TP1701 TPAD 14-OP-GP

SIO_SLP_S 3# [2 4,27,40,51]
SIO_SLP_S 4# [4 0,44,51]

TP1703 TPAD 14-OP-GP
TP1702 TPAD 14-OP-GP
TP1704 TPAD 14-OP-GP
TP1705 TPAD 14-OP-GP
TP1706 TPAD 14-OP-GP

SIO_PW RBTN# [24]

TP1707
TPAD14-O P-GP

1 2

R1713
0R0402-P AD

12

12

C1701

DY

DY

SC220P5 0V2KX-3GP

12

EC1707

DY

SCD1U16 V2KX-3GP

1

PCH_PLT RST#

+VCCMPHYGTAON_1P0

R1719
47KR2F-G P

PCH_RSM RST# [24]

+VCCSTG

12

R1722

DY

100KR2J -1-GP

12

EC1708

DY

SCD01U5 0V2KX-L-GP

H_VCCST _PWRGD_R

EC1706

SC1KP50V2KX-L-1-GP

12

DY

DY

3D3V_AU X_S5

NON DS3

1 2

R1737
100KR2J -1-GP

XDP_DBR ESET#
SYS_PW ROK
PLT_RST #
RESET_O UT#

EC1703

EC1702

12

SC1KP50V2KX-L-1-GP

SC1KP50V2KX-L-1-GP

DY

12

12

3V_5V_P OK

EU1701

AZ5325-01FDR7G-GP

12

DY

EC1705

PM_RSMR ST#_M

SC1KP50V2KX-L-1-GP

Q1702

S

G

D S

0516 Follow Taos DY

+V1.8A_S IP

34

2

5

NON DS3

1

6

2N7002K DW-GP

84.2N702.A3F

2nd = 84.2 N702.E3F

3rd = 75.00 601.07C

12

R1718

DY

10KR2J-L -GP

1 2

R1708
0R0402-P AD

+VCCMPH YGTAON_1P0_LS_ SIP1D0V_S5

1 2

R1724
0R0805-P AD-2-GP-U

1 2

R1735
0R0805-P AD-2-GP-U

3D3V_AU X_S5

B B

12

R1726
10KR2J-L -GP

3V_5V_P OK#

NON DS3

1 2

R1727
100KR2J -1-GP

4 3

S

G

6

D

Q1701

S2

G2

D1

PJT138K A-GP

075.00138.0A7C

(ICCMAX.=3.5A)

12

C1704
SC10U6D 3V3MX-GP

D

D2

25

G

G1

1

S

S1

PM_RSMR ST#

3V_5V_P OK_C

ALL_SYS_P WRGD[24,4 0]

1 2

R1702 1KR2J-1-G P

1 2

R1728 0R0402-P AD

PCH_RSM RST#

3V_5V_P OK [21,40,45 ,53,54]

R1716
100KR2F -L3-GP

12

EC1709

DY

SCD1U16 V2KX-3GP

1 2

12

EC1712

DY

SCD1U16 V2KX-3GP

12

83.R2004.G8F

D

G

D1702

KA

RB751V-4 0H-GP

ME_SUS_ PWR_ACK_ R

SUSACK# _R

ACOK_IN [24,44]

AC_PRES ENT

PM_RSMR ST#

SYS_PW ROK[24]
RESET_O UT#[24,26,79]

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(POWER MANAGEMENT)

CPU_(POWER MANAGEMENT)

CPU_(POWER MANAGEMENT)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

17 105Wedn esday, November 08, 20 17

17 105Wedn esday, November 08, 20 17

17 105Wedn esday, November 08, 20 17

1

A00

A00

A00

5

Main Func = PCH

PCH strap pin:

eSPI or LPC

3D3V_S5_PCH

0511 Follow KY15.

D D

+V1.8A_SIP

R1835 and R1834 merge to RN1802
Follow Starlord

1 2

R1827
1KR2J-1-GP

1 2

R1828
1KR2J-1-GP

1 2

R1816
10KR2J-L-GP

SPI_HOLD_ROM

SPI_WP_ROM

SIO_RCIN#

SML0ALERT# /
GPP_C5

This signal has a weak interna l pull-down.

4

Sampled at rising edge o f RSMRST#

This signal has a weak interna l pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.

GPP_C5/SML0ALERT#

3

PCH Prim

3D3V_S5_PCH 3D3V_S5_PCH

12

R1822
1KR2J-1-GP

12

R1823

DY

1KR2J-1-GP

PCH strap pin:

BOOT HALT

SPI0_MOSI

This signal has a weak interna l pull-up.

0 = ENABLED
1 = DISABLED
WEAK INTERNAL PU

SPI_SI_CPU

PCH Prim

12

DY

12

DY

R1824
1KR2J-1-GP

R1825
1KR2J-1-GP

2

2nd = 84.2N702.E3F

3rd = 75.00601.07C

MEM_SMBDATA

84.2N702.A3F

MEM_SMBCLK

3D3V_S0

Q1801

6

5

2N7002KDW-GP

1

1 2

R1834 10KR2J-L-GP

1 2

R1835 10KR2J-L-GP

1

2

34

PCH_SMBDATA [12,13,56,65,67]

PCH_SMBCLK [12,13,56,65,67 ]

3D3V_S0

SML1_SMBDATA
SML1_SMBCLK
SML0_SMBDATA

CPU1E

Resister value will check later

1 2

SPI_CLK_ROM[25,91]

SPI_SO_ROM[25,91]

SPI_SI_ROM[25,91 ]
SPI_WP_ROM[25 ]
SPI_HOLD_ROM[25]

SPI_CS_ROM_N0[25]

SPI_CS_ROM_N2[91]

0511 Follow KY15.

HDD_FALL_INT[67]

ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3

CLKREQ_PCIE#5
CLKREQ_PEG#0
CLKREQ_PCIE#1
CLKREQ_PCIE#2

CLKREQ_PCIE#3
CLKREQ_PCIE#4

EC1808

SCD1U16V2KX-3GP

12

DY

5

DVT1 add FFS 2/18

12

R1817

10KR2J-L-GP

CL_CLK[61]
CL_DATA[61]
CL_RST#[61]

Q1901

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

C C

ESPI_IO[3..0][24]

B B

A A

3D3V_S0

eSPI

ESPI_IO[3..0]

ESPI_CS#[24]

ESPI_RESET#[24]

ESPI_ALERT#[24]

ESPI_CLK[24]

RN1812

1
2
3
4 5

SRN10KJ-6-GP

RN1813

1
2 3

SRN10KJ-5-GP

RTCRST_ON[21,24]

8
7
6

4

R1806 0R0402-PAD

1 2

R1807 0R0402-PAD

1 2

R1808 0R0402-PAD

1 2

R1809 0R0402-PAD

1 2

R1811 0R0402-PAD

1 2

R1812 0R0402-PAD

1 2

R1814 0R0402-PAD

DY

PEG_CLK_CPU#[76]
PEG_CLK_CPU[76]

GPU

CLKREQ_PEG#0[79]

PEG_CLK1_CPU#[61]
PEG_CLK1_CPU[61]

WLAN

CLKREQ_PCIE#1[61]

PEG_CLK2_CPU#[31]
PEG_CLK2_CPU[31]

LAN

CLKREQ_PCIE#2[31]

RTC_AUX_S5

RN1901

1
2 3

SRN20KJ-1-GP

D

12

C1901
SC1U10V2KX-1GP

TP1803TPAD14-OP-GP
TP1804TPAD14-OP-GP
TP1805TPAD14-OP-GP
TP1806TPAD14-OP-GP

12

SPI_CLK_CPU
SPI_SO_CPU
SPI_SI_CPU
SPI_WP_CPU
SPI_HOLD_CPU
SPI_CS_CPU_N0

SPI_CS_CPU_N2

CPU_D3_TP

1

CPU_D4_TP

1

CPU_D5_TP

1

CPU_D6_TP

1

???
PH only?

EC1805

SCD1U16V2KX-3GP

SIO_RCIN#

ESPI_ALERT#

0511 Remove SSD

4

21

G1901
GAP-OPEN

(#514849)

Layout: Place at the open door area.

0620 NC

CLKREQ_PEG#0

CLKREQ_PCIE#1

CLKREQ_PCIE#3

CLKREQ_PCIE#4

CLKREQ_PCIE#5

12

C1902
SC1U10V2KX-1GP

4

AW3

AW2

AW13

AY11

DY

AV2

AV3

AU4
AU3
AU2
AU1

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKYLAKE-U-GP

CPU1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U-GP

12

DY

12

EC1807
SCD1U16V2KX-3GP

SPI - FLASH

Strap

SPI - TOUCH

C LINK

RCIN#:
Frequency to Avoid: 33 MHz

SRTC_RST#

EC1806
SCD1U16V2KX-3GP

RTC_RST#

CLOCK SIGNALS

SKYLAKE_ULT

SKYLAKE_ULT

LPC

SMBUS, SMLINK

Strap

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

10 OF 20

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

SRTCRST#

RTCRST#

3

5 OF 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A8/CLKRUN#

PCIE_CLK_XDP_N

F43

PCIE_CLK_XDP_P

E43

SUSCLK_R

BA17

XTAL24_IN

E37

XTAL24_OUT

E35

XCLK_BIASREF

E42

RTC_X1

AM18

RTCX1
RTCX2

AM20

AN18
AM16

RTC_X2

SRTC_RST#
RTC_RST#

MEM_SMBCLK

R7

MEM_SMBDATA

R8

GPP_C2/SMBALERT#

R10

SML0_SMBCLK

R9

SML0_SMBDATA

W2

GPP_C5/SML0ALERT#

W1

SML1_SMBCLK

W3

SML1_SMBDATA

V3

GPP_B23/SML1ALERT#

AM7

For eSPI

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

20170504

ESPI_IO0_CPU
ESPI_IO1_CPU
ESPI_IO2_CPU
ESPI_IO3_CPU
ESPI_CS#_CPU
ESPI_RESET#_CPU ESPI_RESET#

CLKRUN#_R

0517 DY

1 2

R1813

DY

0R2J-L-GP

Intel recommend: 2.71k ohm 5%

1 2

R1803
2K7R2F-GP

R1815
10MR2J-L-GP

C1804

SC3D9P50V2CN-1GP

12

X-32D768KHZ-65-GP

82.30001.A41

SML1_SMBCLK [24,79]
SML1_SMBDATA [24,79]

1 2

R1829 15R2F-2-GP

1 2

R1830 15R2F-2-GP

1 2

R1831 15R2F-2-GP

1 2

R1833 15R2F-2-GP

1 2

R1801 0R0402-PAD

1 2

R1826 0R0402-PAD

1 2

R1804 15R2F-2-GP

1 2

R1819 0R2J-L-GP

DY

0512 DY

1

TP1807 TPAD14-OP-GP

1

TP1808 TPAD14-OP-GP

SUS_CLK [24]

+V1.00A_SIP

1 2

X1802

41

2 3

RTC_X2RTC_X1

C1803

SC3D9P50V2CN-1GP

12

ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
ESPI_CS#

ESPI_CLKESPI_CLK_CPU

12

EC1802

DY

SC10P50V2JN-L1-GP

2

SML0_SMBCLK

GPP_B23/SML1ALERT#

GPP_C2/SMBALERT#

MEM_SMBCLK
MEM_SMBDATA

CLKRUN#_R

PWR_SEClET [24]

20170428

XTAL24_IN XTAL24_IN_R

XTAL24_OUT

U22

12

1 2

0R0402-PAD

R1802

1MR2J-1-GP

RN1807

8
7
6

SRN2K2J-4-GP

0516 Check with SW(Internal PH?)

1 2

R1820 150KR2J-GP

1 2

R1821 2K2R2J-L1-GP

1 2

R1805 2K2R2J-L1-GP

1 2

R1832 2K2R2J-L1-GP

0512 Modify

R1810

23

R1818

8K2R2F-1-GP

1 2

DY

U22

4 1

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

CPU_(LPC/SPI/SMBUS/CL/CLK)

CPU_(LPC/SPI/SMBUS/CL/CLK)

CPU_(LPC/SPI/SMBUS/CL/CLK)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

3D3V_S5_PCH

1
2
3
45

+V1.8A_SIP

U22

1 2

C1801 SC15P50V2JN- 2-GP

X1801
XTAL-24MHZ-81-GP

82.30004.841

U22

1 2

C1802 SC15P50V2JN- 2-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

1

A00

A00

18 105Wednesday, November 08, 2017

18 105Wednesday, November 08, 2017

18 105Wednesday, November 08, 2017

A00

5

Main Func = PCH

4

3

2

1

PCH strap pin:

Flash Descriptor Security Overide/
Intel ME Debug Mode

D D

HDA_SDOUT

Low = Default
High = Enable

*

The internal pull-down is disabled after
PLTRST# deasserts

DGPU_PWROK[24,79,85]

HDA_CODEC_BITCLK[27]

HDA_CODEC_SDOUT[27]

HDA_CODEC_SYNC[27]

HDA_SDIN0[27]

C C

ME_FWP[24]

SPKR[27]

HDA_SYNC
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

FC1902

SC2P50V2CN-GP

12

DY

DGPU_PWROK

SPKR

CPU1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKYLAKE-U-GP

AUDIO

SKYLAKE_ULT

SDIO/SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

7 OF 20

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

CPU_A16_TP

SD_RCOMP

1 2

R1901
200R2F-L-GP

1

TP1902
TPAD14-OP-GP

PCH strap pin:

NO REBOOT

Low = Enable (Default)

HDA_SPKR

*

High = Disable

The internal pull-down is disabled after
PLTRST# deasserts

B B

3D3V_S0

1 2

R2006 1KR2J-1-GP

DY

1 2

R1904 100KR2J-1-GP

UMA

1 2

EC1901 SC10P50V2JN-L1-GP

EC1903 SC1KP50V2KX-L-1-GP

DY

1 2

DY

SPKR

DGPU_PWROK

HDA_CODEC_BITCLK

DGPU_PWROK

HDA_CODEC_BITCLK HDA_BITCLK

HDA_CODEC_SYNC

ME_FWP

1 2

R1907 0R0402-PAD

1 2

R1908 0R0402-PAD

1 2

R1912 0R0402-PAD

1 2

R1909 1KR2J-1-GP

HDA_SYNC

HDA_SDOUTHDA_CODEC_SDOUT

12

FC1901

DY

SC2P50V2CN-GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

CPU_(AUDIO/SDIO/SDXC)

CPU_(AUDIO/SDIO/SDXC)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

CPU_(AUDIO/SDIO/SDXC)

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

19 105Wednesday, November 08, 2017

19 105Wednesday, November 08, 2017

19 105Wednesday, November 08, 2017

1

A00

A00

A00

5

Main Func = PCH

UART_2_CRXD_DTXD[68]
UART_2_CTXD_DRXD[68]

1 2

EC2002 SC1KP50V2KX-L-1-GP

DY

RN2009

1
2 3

OPS

D D

C C

SRN10KJ-5-GP

(PDG#543016) If the UART/GPIO functionality is also not used,
the signals can be left as no-connect.

3D3V_S0

1 2

R2048 51KR2J-1-GP

1 2

R2049 51KR2J-1-GP

1 2

R2046 51KR2J-1-GP

1 2

R2002 10KR2J-L-GP

DY

1 2

R2003 10KR2J-L-GP

RN2010

1
2 3

SRN2K2J-1-GP

3D3V_S5_PCH

1
2 3

4

Debug
Debug
Debug

4

DY

RN2011
SRN10KJ-5-GP

DGPU_HOLD_RST#
DGPU_PWR_EN

I2C0_SDA_TCH_PAD
I2C0_SCL_TCH_PAD

SIO_EXT_WAKE#

4

RTC_DET#

PCH strap pin:

No Reboot

GSPI0_MOSI /
GPP_B18

The signal has a weak intern al pull-down.

Sampled at rising edge o f PCH_PWROK

0 = Disable “No Reboot” mode .
1 = Enable “No Reboot” mod e (PCH will disable the TCO
Timer system reboot feature). This f unction is useful
when running ITP/XDP.

DGPU_HOLD_RST# [76]

DBC_PANEL_EN[55]

TPAD14-OP-GP

BLUETOOTH_EN[61]

UART_2_CTXD_DRXD
LPSS_UART2_CTS# LPSS_UART2_CTS#

BLUETOOTH_EN

PTP

DBC_PANEL_EN

SIO_EXT_WAKE#[24]

I2C0_SDA_TCH_PAD[65]
I2C0_SCL_TCH_PAD[65]

PCH Prim

3D3V_S5_PCH

0511 Remove DB2

TP2008

12

R2007

DY

1KR2J-1-GP

GPP_B18/GSPI0_MOSI

12

R2019

DY

1KR2J-1-GP

4

VRAM_ID1
GPP_B18/GSPI0_MOSI

GPP_B22

1

BOARD_ID2

UART_2_CRXD_DTXD
UART_2_CTXD_DRXDUART_2_CRXD_DTXD

CPU1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKYLAKE-U-GP

3

LPSS ISH

SKYLAKE_ULT

Strap

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ ISH_GP6

+V1.8A_SIP +V1.8A_SIP

0517 Change PH power rate

12

DY_SKL

12

KBL

PROJECT_ID1

12

Vegas

12

Turis

R2015
10KR2J-L-GP

R2016
10KR2J-L-GP

PROJECT_ID2

6 OF 20

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_S DA
GPP_F11/I2C5_SCL/ISH_I2C2 _SCL

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

BIOS strap pin:

PROJECT Strap pin

R2017
10KR2J-L-GP

R2018
10KR2J-L-GP

Turis

Vegas

KBL

SKL

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

USB_UART_SEL_D9
DGPU_HOLD_RST#

RTC_DET#

I2C0_SDA
I2C0_SCL

I2C1_SDA
I2C1_SCL

1.8V Only

DGPU_PWR_EN
UART0_TXD
UART0_RTS#
UART0_CTS#

UART1_RXD

UART1_CTS#

PROJECT_ID1
PROJECT_ID2
KB_DET#
CAMERA_DET#
TPM_SELECT

PROJECT_ID2

2

1

TP2006 TPAD14-OP-GP

RTC_DET# [25]

(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
to the same voltage rail as the device/end point.

1
1
1

1

1

PANEL_SIZE_ID [55]

KB_DET# [65]

TP2007 TPAD14-OP-GP
TP2010 TPAD14-OP-GP
TP2011 TPAD14-OP-GP

TP2012 TPAD14-OP-GP

FFS_INT2 [67]

TP2015TPAD14-OP-GP

DVT1 add FFS 2/18

CAMERA_DET# [55]

DGPU_PWR_EN [85,86]

0517 Change PH power rate

KB_DET#
CAMERA_DET#

??? Ask SW in PH necessary

1

RN2007

1
2 3

1
2 3

1 2
1 2

SRN10KJ-5-GP

DY

RN2008

DY

SRN2K2J-1-GP

I2C0_SCL
I2C0_SDA

I2C1_SCL
I2C1_SDA

R2001 10KR2J-L-GP
R2004 10KR2J-L-GP

GPP_A18GPP_A19

PROJECT_ID1

X

0

1X

0

1

X

X

3D3V_S0

4

4

+V1.8A_SIP

0517 Change PH power rate

3D3V_S0

12

OPS

B B

BOARD_ID2

12

UMA

3D3V_S0

12

VRAM_2G

VRAM_ID1

12

VRAM_4G

A A

5

4

R2005
10KR2J-L-GP

R2008
10KR2J-L-GP

R2023
10KR2J-L-GP

R2024
10KR2J-L-GP

BIOS strap pin:

BIOS UMA/DIS Strap pin

UMA

DIS

BIOS strap pin:

BIOS VRAM Size Strap pin

4G

2G

3

GPP_C11

BOARD_ID2

0

1

TPM_SELECT

GPP_B17

VRAM_ID1

0

1

+V1.8A_SIP

TPM

NON_TPM

2

12

R2022
10KR2J-L-GP

12

R2020
10KR2J-L-GP

BIOS strap pin:

BIOS UMA/DIS Strap pin

TPM

NON_TPM

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

GPP_A22

TPM_SELECT

1

0

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(LPSS/ISH)

CPU_(LPSS/ISH)

CPU_(LPSS/ISH)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

A00

A00

20 105Wednesday, November 08, 2017

20 105Wednesday, November 08, 2017

20 105Wednesday, November 08, 2017

A00

5

Main Func = PCH

12

C2110

AB19
AB20

AF18
AF19

AB17

AD17
AD18

AJ17

AJ19

AJ16

AF20
AF21

AJ21

AK20

N15
N16
N17
P15
P16

K15

V15

Y18

T19
T20

N18

P18

V20
V21

AL1

K17

L15

DY

L1

12

12

CPU1O

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0
VCCMPHYAON_1P0

VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0

VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0
VCCPRIM_1P0

VCCDSW_3P3
VCCDSW_3P3
VCCDSW_3P3

VCCHDA

VCCSPI

VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0

VCCPRIM_3P3

VCCPRIM_1P0

VCCAPLLEBB_1P0

SKYLAKE-U-GP

C2111

C2114

CPU POWER 4 OF 4

Layout Note:

1uF:
C2105 near V19
C2106 near AK17
C2107 near AG15
C2109 near Y16

0.1uF:
C2110 near T16
C2111 near AJ19

SC22U6D3V3MX-1-GP

Layout Note:

22uF:
C2114 near V15

SKYLAKE_ULT

+V1.00A_ SIP

+VCCPRIM_ CORE

2.57A

C2120

D D

C C

EC2101

12

+V3.3A_S IP

+V3.3A_S IP

DY

B B

+VCCAMP HYPLL_1P0 +VCCAPL L_1P0

DY

A A

SC1U10V2KX-1GP

SCD1U25V2KX-GP

12

DY

+VCCMPH YGTAON_1P0_LS_ SIP

+VCCMPH YGTAON_1P0_LS_ SIP

+VCCMPH YGTAON_1P0_LS_ SIP

C2105

12

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

C2113

12

+VCCDSW _1P0

+VCCAMP HYPLL_1P0

+VCCAPL L_1P0

+VCCPDS W_3P3

R2101
0R0402-P AD

C2106

12

12

DY

DY

SC22U6D3V3MX-1-GP

Layout Note:

22uF:
C2113 near K15

+V1.00A_ SIP

+V1.00A_ SIP

1 2

+V3.3A_S IP

+V3.3A_S IP

+V1.00A_ SIP

C2107

DY

C2109

12

+VCCPAZ IO

SCD1U16 V2KX-3GP
SCD1U16 V2KX-3GP

1.8V Only

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

+V1.00A_ SIP

4

15 OF 20

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC
VCCRTC

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

C2101

12

12

DY

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

0511 Follow KY15.

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19

T1

AA1

AK17

AK19
BB14

BB10

A14

K19

L21

N20

L19

A10

AN11
AN13

+V1.8A_S IP

+V3.3A_S IP

+V1.8A_S IP

+V3.3A_S IP

+V1.00A_ SIP

+V1.8A_S IP

+V3.3A_S IP

+VCCPRT C_3P3

VCCRTCE XT

+V1.00A_ SIP

Symbol error for layout NC

3

RTC_AUX _S5

12

DY

SCD1U16 V2KX-3GP
SCD1U16 V2KX-3GP

CAP need close to VCCRTC

1 2

C2112 SCD1U16V2 KX-3GP

+VCCDSW _1P0+V1.8A_S IP

C2103

C2108

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

12

C2118

C2119

12

C2117

SC1U10V2KX-1GP

12

0512 Follow SF

RTCRST_ ON[18,24]

1 2

R2113 0R0402-P AD

Q2107

S

D

RTC_RST

G

DMP2130 L-7-GP

G

84.02130.031

2nd = 84.0 0102.031

3rd = 84.03 413.B31

RTC_RST

12

R2118

100KR2J-1-GP

2

1 2

R2107
0R0402-P AD-2-GP

1 2

R2112
0R0603-P AD-2-GP-U

1 2

R2108
0R0603-P AD-2-GP-U

D

D2102

RTC_RST

RB751VM -40TE-17-GP

83.R2004.J8F

1 2

R2102

RTC_RST

1MR2J-1-G P

1

+VCCPRT C_3P3RTC_AUX _S5

+VCCAMP HYPLL_1P0+VCCMPH YGTAON_1P0_LS_ SIP

+VCCAPL L_1P0+V1.00A_ SIP

RTC_AUX _S5RTC_3D3 V

12

R2104
4K7R2J-2 -GP

RTC_RST

RTC_3P3 _EN_D

D

Q2110
2N7002K -2-GP

G

RTC_RST

84.2N702.J31

2ND = 84.2 N702.031

3rd = 84.07 002.I31

S

4th = 84.2N 702.W31

AK

RTC_3P3 _EN_G

RTC_RST

C2123

SCD022U16V2KX-3GP

12

Layout Note:

C2116

C2104

C2121

12

12

DY

DY

C2122

SC22U6D3V3MX-1-GP

12

VCCDSW _EN#[24]

1uF:
C2101 near AB19
C2104 near K17
C2116 near A10
C2121 near AL1
22uF:
C2122 near L19

3D3V_S5

RTC_RST

12

12

DY

0512 Follow SF

R2120

100KR2J-1-GP

C2125
SC1U10V 2KX-1GP

3D3V_S5

1 2

R2114

DY

0R2J-L-GP

3V_5V_P OK[17,40,45,5 3,54]

3V_5V_P OK

VCCDSW _EN#

3D3V_S5

1

RTC_RST

2

U2101

RTC_RST

5

VIN#5

4

VIN#4

RT9724G B-GP

74.09724.09F

D2101

BAT54A-1 1-GP

EN

GND

VOUT

3

1
2
3

3V_5V_D SW_OK

3D3V_S5 _PCH_Gen9

RTC_RST

<Core Design>

<Core Design>

<Core Design>

12

R2115
10KR2J-L -GP

RTC_RST

1 2

R2116
0R3J-L1-G P

3D3V_S5 _PCH

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(POWER1)

CPU_(POWER1)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

CPU_(POWER1)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

21 105Wedn esday, November 08, 20 17

21 105Wedn esday, November 08, 20 17

21 105Wedn esday, November 08, 20 17

1

A00

A00

A00

5

4

3

2

1

D D

XTAL24_OUT_U42

C C

R2201
0R2J-2-GP

CPU1T

AW69

RSVD#AW69

AW68

RSVD#AW68

AU56

RSVD#AU56

AW48

RSVD#AW48

C7

RSVD#C7

U12

RSVD#U12

U11

RSVD#U11

H11

RSVD#H11

SKYLAKE-U-GP

1 2

U42

12

SKYLAKE_ULT

XTAL24_IN_U42_RXTAL24_IN_U42

R2203

1MR2J-1-GP

SPARE

U42

B B

XTAL24_OUT_U42

1 2

R2202

U42

0R2J-2-GP

XTAL24_OUT_R_U42

20 OF 20

RSVD#F6

RSVD#E3
RSVD#C11
RSVD#B11
RSVD#A11
RSVD#D12
RSVD#C12
RSVD#F52

23

U42

F6
E3
C11
B11
A11
D12
C12
F52

U42

1 2

C2201 SC15P50V2JN-2-GP

XTAL24_IN_U42

X2201
XTAL-24MHZ-86-GP

82.30004.891

4 1

U42

1 2

C2202 SC15P50V2JN-2-GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

CPU_(RSVD)

CPU_(RSVD)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU_(RSVD)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

22 105Wednesday, November 08, 2017

22 105Wednesday, November 08, 2017

22 105Wednesday, November 08, 2017

1

A00

A00

A00

5

Main Func = PCH

4

3

2

1

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38

AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6

AW60
AW62
AW64
AW66

AW8
AY66

BA10
BA14
BA18

BA23
BA28
BA32
BA36

BA45

AV1

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1

BA2

F68

CPU1Q

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKYLAKE-U-GP

0517 Follow KY1 5.

Symbol error for layout NC

TP2311TPAD14-OP-G P

D D

C C

B B

TP2301TPAD14-OP-G P

1
1

A67_TP
A70_TP

AA2

AA4
AA65
AA68
AB15
AB16
AB18
AB21

AB8
AD13
AD16
AD19
AD20
AD21
AD62

AD8
AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH6
AH63
AH64
AH67

AJ15
AJ18
AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AK8

AL28
AL32
AL35
AL38

AL45
AL48
AL52
AL55
AL58
AL64

A67
A70

AF1

AF2
AF4

AJ4

AL2

AL4

A5

CPU1P

GND 1 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKYLAKE-U-GP

SKYLAKE_ULT

16 OF 20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

0517 Follow KY1 5.

TP2310TPAD14-OP-G P

TP2304TPAD14-OP-G P

0517 Follow KY1 5.

TP2312TPAD14-OP-G P
TP2305TPAD14-OP-G P

Symbol error for layout NC

1

1

1
1

AV1_TP

AV71_TP

B71_TP
BA1_TP

SKYLAKE_ULT

17 OF 20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA49
BA53
BA57
BA6
BA62
BA66

Symbol error for layout NC

BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64

Symbol error for layout NC

BB67

BB70_TP

BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65

Symbol error for layout NC

E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

0517 Follow KY1 5.

1

TP2307 TPAD 14-OP-GP

[#543016 Rev0.9 ]

G10
G22
G43
G45
G48

G52
G55
G58

G60
G63
G66

H15
H18
H71

K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17

G5

G6

J11
J13
J25
J28
J32
J35
J38
J42

F8

J8

CPU1R

GND 3 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKYLAKE-U-GP

SKYLAKE_ULT

18 OF 20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

CPU_(VSS)

CPU_(VSS)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU_(VSS)

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

23 105Wedn esday, November 08, 20 17

23 105Wedn esday, November 08, 20 17

23 105Wedn esday, November 08, 20 17

1

A00

A00

A00

5

Main Func = KBC

Layout Note:

Need very close to EC

R2402 0R0402-PAD

1D0V_S5

D D

3D3V_S5_KBC

RN2408

SRN100KJ-5-GP

1
2
3
4 5

RN2409

SRN100KJ-5-GP

1
2
3
4 5

RN2406

SRN100KJ-5-GP

1
2
3
4 5

RN2407

SRN100KJ-5-GP

1
2
3
4 5

20170504 ESPI

ESPI_IO[3..0][18]

C C

ESPI_CS#[18]
ESPI_CLK[18]
ESPI_ALERT#[18]
ESPI_RESET#[18]

AC_DIS[43 ,44]

ACOK_IN[17,44]

ALL_SYS_PWRGD[17,40]

ALWON[40]

BEEP[27 ]

BLON_OUT[55]

CMP_VIN0_R[26]
CMP_VOUT0[26]

PWR_SEClET[18]

CLK_TP_SIO[65]
DAT_TP_SIO[65]

DGPU_PWROK[19,79,85]

NB_MUTE#[27]

FAN1_DAC_1[26]

GPU_PWR_LEVEL[79]

H_PROCHOT#[4,44,46]

HOST_DEBUG_TX[61,68]

INT_TP#[4,65]

B B

LANWAKE#[17]

LCD_VCC_TEST_EN[55]

LID_CL_SIO#[64]

MASK_SATA_LED#[64]

ME_FWP[19]

PBAT_PRES#[4 3,44]

PCH_RSMRST#[17]

PCIE_WAKE#[31]

PM_LAN_ENABLE[31]

PRIM_PWRGD[40,54]

PS_ID[43]

RESET_OUT#[17,26,79]

RTCRST_ON[18,21]

SIO_EXT_WAKE#[20]

SIO_PWRBTN#[17]

SIO_SLP_S3#[17,27,40,51]

SIO_SLP_S4#[17,40,44,51]

PBAT_CHG_SMBCLK[43,44]
PBAT_CHG_SMBDAT[43 ,44]

SML1_SMBCLK[18,79]
SML1_SMBDATA[18,79 ]

SUS_CLK[18]

SYS_PWROK[17]

A A

TP_EN#[65]

USB_PWR_EN#[35]

VCCDSW_EN#[21]

1 2

8

KSO8

7

KSO3

6

KSO1
KSO2

8

KSO5

7

KSO4

6

KSO7
KSO6

8

KSO0

7

KSO12

6

KSO16
KSO15

8

KSO13

7

KSO14

6

KSO11
KSO10

ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3

3D3V_S5_KBC

5

VREF_CPU

12

C2406
SCD1U16V2KX-3GP

3D3V_S5_KBC

12

12

DY

1
2
3
4 5

1
2
3
4 5

ESPI

R2450
100KR2J-1-GP

R2449
100KR2J-1-GP

RN2403
SRN10KJ-12-GP

RN2404
SRN10KJ-12-GP

1D8V_S5_KBC

3D3V_S5_KBC

BOARD_ID

KSO9

PROCHOT

8

KSI7

7

KSI6

6

KSI4
KSI2

8

KSI5

7

KSI1

6

KSI3
KSI0

R2410

1 2

10KR2J-L-GP

R2415

1 2

10KR2J-L-GP

3D3V_S5

12

EC_GPIO47 High Active

R2420
0R0402-PAD

R2474

1 2

0R0402-PAD

3D3V_S5 3D3V_S5_KBC

C2416

SCD1U16V2KX-3GP

C2421

SCD1U16V2KX-3GP

C2415

12

12

12

DY

0517 Change to digital GND

KSO[0..16][65]

VCCDSW_EN#

0512(SF)

ESPI_ALERT#

3D3V_S5_KBC

0511(KY15)

INT_TP#

USB_PWR_EN#
ALL_SYS_PWRGD

ALL_SYS_PWRGD assert,
delay 10ms; RESET_OUT# assert.

SUS_CLK

CMP_VOUT1_R

C2419

SCD01U50V2KX-L-GP

12

R2417

12

DY

DY

3D3V_S5

PCB_REV

12

R2443

C2408

SCD1U16V2KX-3GP

12

R2444

12

EC_AGND

12

R2401

DY

10KR2F-L1-GP

TP2406
TPAD14-OP-GP

TP2403

TPAD14-OP-GP
R2412 10KR2J-L-GP
R2431 0R0402-PAD
R2491 0R0402-PAD

R2479 0R0402-PAD
R2481 0R0402-PAD

R2428 0R2J-L-GP

0517 DY

R2418

0R2J-L-GP

G

100KR2J-1-GP

S

10KR2F-L1-GP

100KR2F-L3-GP

PBAT_PRES#

R2434
100KR2J-1-GP

1 2

BOARD_ID_R

R2446

1 2

0R0603-PAD-2-GP-U

SC2D2U10V3KX-L-GP

3D3V_S5_KBC

C2420

SCD1U16V2KX-3GP

C2412

12

12

KSI[0..7][65]

R2411

1 2

DY

0R2J-L-GP

0511(KY15)

0515(KY15)

0511(KY15)

1

0516(CY17)

0511(KY15)

0516(CY17)
0516(KY15)

1
1 2
1 2
1 2

1 2
1 2

1 2

DY

C2425

SC18P50V2JN-1-GP

12

Microchip: Use CL=9p Xtal，C = 10p

1 2

DY

Q2408

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4

C2411

SCD1U16V2KX-3GP

C2410

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

12

0519 Install

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
CAP_LED#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

CLK_TP_SIO
DAT_TP_SIO
SIO_PWRBTN#
VCCDSW_ON

ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
ESPI_CS#
MASK_SATA_LED#
ESPI_CLK
PWR_SEClET
ESPI_ALERT#
GPU_PWR_LEVEL
TP_EN#
ESPI_RESET#
LID_CL_SIO#

CCG4_I2C_INT#
SYS_PWROK
PBAT_PRES#
PRIM_PWRGD
RTCRST_ON
PCH_RSMRST#

BKLT_IN_EC
AC_DIS

USB_POWERSHARE_VBUS_EN

FPR_SCAN#
TP_WAKE_KBC#
AUX_ONPM_LAN_ENABLE

0518(CY17)

USB_EN#
RUNPWROK

RESET_OUT#

MEC_XTAL2
MEC_XTAL1_R

X2401

1 2

XTAL-32D768KHZ-91-GP

082.30003.0221

H_PROCHOT#_EC

4

C2414

SCD1U16V2KX-3GP

C2413

SCD1U16V2KX-3GP

12

12

12

DY

+RTC_CELL_VBAT

12

C2428
SCD1U16V2KX-3GP

KBC24

2

GPIO027/KSO00/PVT_IO1

14

GPIO015/KSO01/PVT_CS#

15

GPIO016/KSO02/PVT_SCLK

16

GPIO017/KSO03/PVT_IO0

37

GPIO045/BCM_INT1#/KSO04

38

GPIO046/BCM_DAT1/KSO05

39

GPIO047/BCM_CLK1/KSO06

50

GPIO025/KSO07/PVT_IO2

46

GPIO055/PWM2/KSO08/PVT_IO3

68

GPIO102/KSO09/CR_STRAP

72

GPIO106/KSO10

74

GPIO110/KSO11

75

GPIO111/KSO12

76

GPIO112/PS2_CLK1A/KSO13

77

GPIO113/PS2_DAT1A/KSO14

86

GPIO125/KSO15

92

GPIO132/KSO16

93

GPIO140/KSO17

98

GPIO143/KSI0/DTR#

99

GPIO144/KSI1/DCD#

6

GPIO005/SMB00_DATA/SMB00_DATA18/KSI2

7

GPIO006/SMB00_CLK/SMB00_CLK18/KSI3

104

GPIO147/KSI4/DSR#

105

GPIO150/KSI5/RI#

107

GPIO151/KSI6/RTS#

108

GPIO152/KSI7/CTS#

78

GPIO114/PS2_CLK0

79

GPIO115/PS2_DAT0

52

GPIO026/PS2_CLK1B

88

GPIO127/PS2_DAT1B

59

GPIO040/LAD0/ESPI_IO0

60

GPIO041/LAD1/ESPI_IO1

61

GPIO042/LAD2/ESPI_IO2

62

GPIO043/LAD3/ESPI_IO3

58

GPIO044/LFRAME#/ESPI_CS#

56

GPIO064/LRESET#

57

GPIO034/PCI_CLK/ESPI_CLK

63

GPIO067/CLKRUN#

55

GPIO063/SER_IRQ/ESPI_ALERT#

10

GPIO011/SMI#/EMI_INT#

49

GPIO060/KBRST

53

GPIO061/LPCPD#/ESPI_RESET#

66

GPIO100/EC_SCI#

32

GPIO126/SHD_SCLK

28

GPIO133/SHD_IO0

29

GPIO134/SHD_IO1

30

GPIO135/SHD_IO2

31

GPIO136/SHD_IO3

27

GPIO123/SHD_CS#

67

GPIO101/SPI_CLK

69

GPIO103/SPI_IO0

71

GPIO105/SPI_IO1

42

GPIO052/SPI_IO2

33

GPIO062/SPI_IO3

3

GPIO001/SPI_CS#/32KHZ_OUT

13

RESET_IN#/GPIO014

48

GPIO057/VCC_PWRGD

73

GPIO107/RESET_OUT#

125

XTAL2

123

XTAL1

MEC1416-NU-D0-GP

071.01416.000G

12

R2458
0R0402-PAD

XTAL_KBC_2

C2424

SC18P50V2JN-1-GP

12

R2416

1 2

0R0402-PAD

C2417

SC2D2U10V3KX-L-GP

If don't need RTC alarm wake up,
can change to 3D3V_AUX_S5

12

R2473

DY

0516 Follow KY15.

124

EC LCD test

EC_BRIGHTNESS[55]

LCD_TST_R[55]

H_PROCHOT#

12

C2403

DY

SC47P50V2JN-3GP

RTC_3D3V3D3V_AUX_S5

12

0R2J-2-GP

R2472

0R0402-PAD

43

103

122

VBAT

GPIO007/SMB01_DATA/SMB01_DATA18

GPIO012/SMB02_DATA/SMB02_DATA18

GPIO130/SMB03_DATA/SMB03_DATA18

GPIO141/SMB04_DATA/SMB04_DATA18

VSS17VSS51AVSS

VSS_VBAT

VSS

VSS64VSS

84

100

R2445

1 2

0R0402-PAD

EC_AGND

R2456 0R0402-PAD

R2419 0R0402-PAD

3

0511 Follow KY15.

1D8V_S5_KBC1D8V_S5

R2462

1 2

0R0402-PAD-2-GP

C2423

SCD1U16V2KX-3GP

12

54

VTR5VTR19VTR

GPIO010/SMB01_CLK/SMB01_CLK18

GPIO013/SMB02_CLK/SMB02_CLK18

GPIO131/SMB03_CLK/SMB03_CLK18

GPIO142/SMB04_CLK/SMB04_CLK18

GPIO166/CMP_VREF1/UART_CLK

112

EC_AGND

1 2

1 2

10KR2J-L-GP

1108 Install

VTR_33_18

VTR65VTR82VTR

GPIO030/BCM_INT0#/PWM4
GPIO031/BCM_DAT0/PWM5
GPIO032/BCM_CLK0/PWM6

GPIO157/LED0/TST_CLK_OUT

GPIO116/TFDP_DATA/UART_RX

GPIO117/TFDP_CLK/UART_TX

GPIO035/SB-TSI_CLK

GPIO033/PECI_DAT/SB_TSI_DAT

GPIO145/ICSP_CLOCK

GPIO146/ICSP_DATA

SYSPWR_PRES/GPIO003

VCI_OVRD_IN/GPIO164

GPIO124/CMP_VOUT0

GPIO020/CMP_VIN0

GPIO165/CMP_VREF0

GPIO120/CMP_VOUT1

GPIO021/CMP_VIN1

GPIO023/ADC6/A20M

VR_CAP

18

VR_CAP

12

C2418
SC1U10V2KX-1GP

Layout Note:

Connect GND and AGND planes via either
0R resistor or connect directly.

3D3V_S5_KBC 3D3V_S5_KBC

12

R2414

GPIO050/TACH0
GPIO051/TACH1

GPIO053/PWM0
GPIO054/PWM1

GPIO056/PWM3

GPIO002/PWM7

GPIO156/LED1
GPIO104/LED2

VREF_CPU

ICSP_MCLR

BGPO/GPIO004

VCI_OUT/GPIO036
VCI_IN1#/GPIO162
VCI_IN0#/GPIO163

GPIO160/DAC_0
GPIO161/DAC_1

DAC_VREF

GPIO024/ADC7

GPIO022/ADC5
GPIO153/ADC4
GPIO154/ADC3
GPIO155/ADC2
GPIO122/ADC1
GPIO121/ADC0

ADC_VREF

12

R2478
100KR2J-1-GP

EC_DEBUG

MODEL_ID

12

3

LCD_TST

ICSP_CLR

C2407

SCD1U16V2KX-3GP

3D3V_S5

MODEL_ID

EC_AGND

8
9
11
12
89
91
96
97

40
41

44
45

47
34
35
36
4

1
106
70

80
81

90
94

95

101
102
87

119
120
121
126
127
128

23
24
22

85
20
25

83
21
26

118
117
116
109
110
111
113
114
115

ICSP_CLK
ICSP_DAT

12

12

BAT2_LED#

3D3V_S5 3D3V_S5

CHG_AMBER_LED#[64]

Q2412 and Q2413 merge

3D3V_S5_KBC

4

RN2402
SRN4K7J-8-GP

1

PBAT_CHG_SMBDAT
PBAT_CHG_SMBCLK
GPU_THM_SMBDAT
GPU_THM_SMBCLK

0516 NC 41, 89, 91, 97 pin

NB_MODE#

FAN1_TACH

0518(CY15)

KB_LED_PWM
BEEP

0517 Follow Taos.

FAN1_PWM
FAN2_PWMVOL_LP#
LANWAKE#
PS_ID
PCIE_WAKE#

BAT2_LED#
BAT1_LED#
BREATH_LED#

ME_FWP
HOST_DEBUG_TX

PTP_DIS#
H_PECI_R

VREF_CPU

ICSP_CLK
ICSP_DAT
ICSP_CLR

NB_MUTE#
SYSPWR_PRES
ALWON
VCI_IN1#
POWER_SW_IN#
HW_ACAV_IN

DGPU_PWROK_EC
HW_ACAVIN_NB

CMP_VOUT0 CMP_VOUT0
CMP_VIN0
VCREF0

PROCHOT
CMP_VIN1
LCD_TST

USB_PWR_SHR_EN_L#
PANEL_BKEN_EC
SIO_EXT_WAKE#
MODEL_ID
I_ADP
BOARD_ID
LCD_VCC_TEST_EN_R
I_BATT

3D3V_S5_KBC

R2442

64K9R2F-1-GP

R2441

100KR2F-L3-GP

2 3

R2438 0R0402-PAD

1 2

R2439 0R0402-PAD

1 2

TP2401 TPAD14- OP-GP

1

TP2407 TPAD14- OP-GP

1

R2403 10KR2J-L-GP

1 2

R2486 0R2J-2-GP

1 2

DY

0518(KY15)
0518(KY15)

TP2402 TPAD14- OP-GP

1

0516(CY17 GPIO)

Need very close to EC

0518(CY17 GPIO)

R2437 43R2J-GP

1 2

12

0517(CY17 GPIO)

0517(CY17 GPIO)

C2422

SCD1U16V2KX-3GP

12

EC_AGND

R2476 0R2J-L-GP

1 2

R2463 0R2J-L-GP

1 2

R2464 0R2J-L-GP

1 2

R2466 0R2J-L-GP

1 2

R2465 0R2J-L-GP

1 2

C2405

DY

SC100P50V2JN-3GP

R2452 100KR2J-1-GP

1 2

R2469 0R0402-PAD

1 2

R2427 0R0402-PAD

1 2

1

C2429 SCD1U16V2KX-3GP

1 2

R2470 0R0402-PAD

1 2

1

R2493 10KR2F-L1-GP

1 2

R2497 0R0402-PAD

1 2

R2471 0R2J-L-GP

1 2

DY

R2495

1 2

0R0402-PAD

R2487

1 2

DY

0R2J-L-GP

I_BATT

R2423
330R2J-3-GP

C2441

SC2200P50V2KX-2GP

12

EC_AGND

EC_DEBUG

EC_DEBUG
EC_DEBUG

EC_DEBUG
EC_DEBUG

SML1_SMBDATA
SML1_SMBCLK

FAN1_DAC_1
SIO_SLP_S3#

TP2405
TPAD14-OP-GP

TPAD14-OP-GP

TP2404

LCD_VCC_TEST_EN

0516(CY17 GPIO)

SIO_SLP_S3#

1 2

Layout Note:

Need very close to EC

3D3V_AUX_KBC_R

ICSP_CLK_R
ICSP_DATA_R

E51_TXD_RHOST_DEBUG_TX
ICSP_MCLR_R

+RTC_CELL_VBAT

ACOK_IN

DGPU_PWROK

CMP_VIN0_R

3D3V_S5_KBC

BLON_OUT
CMP_VIN0_R

EC_AGND

boost_mon [44]

Q2412

1

6

2

5

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

3D3V_S0

12

R2430
10KR2J-L-GP

12

C2401
SC10U6D3V3MX-GP

H_PECI [4]

0516(CY17 GPIO)

R2421
330R2J-3-GP

C2435

SC2200P50V2KX-2GP

12

7
1

2
3
4
5
6
8

20.K0691.006

ACES-CON6-58-GP

2

R2461

1 2

DY

0R2J-2-GP

KA

D2403

RB751V-40H-GP

83.R2004.G8F

3D3V_S5_KBC

1 2

DB3

EC_DEBUG

2

BATT_WHITE_LED# [64]

BAT1_LED#

TOUCH_PANEL_INTR#

Touch Panel PH internally.

CAP_LED#

R2435 0R0402-PAD

FAN_TACH1 [26]

3D3V_S0

12

R2489

100KR2J-1-GP

0519 Follow Vendor

3D3V_S5_KBC

12

R2424
20KR2F-L3-GP

Vref = 1.117
temp around 85

12

R2448

10KR2F-L1-GP

AD_IA [44]

LID_CL_SIO#

PTP_DIS#

L_BKLT_EN[8]

Power Switch Logic(PSL)

KBC_PWRBTN#[64]

3D3V_S5

RN2405

1

8
2
3
4 5

12

R2436
100KR2J-1-GP

D

SRN100KJ-5-GP

3D3V_S0

0516 Follow CY17.

BKLT_IN_EC

7

6

CAP_LED#_S [65]

R2429
10KR2J-L-GP

1 2

Q2414
2N7002K-2-GP

G

S

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

LID_CL_SIO#
TP_EN#

1 2

DY

??? Check function with Kevin

3D3V_AUX_S5

12

R2453
1KR2J-1-GP

DY

C2409

12

1108 Install

PTP

SCD01U50V2KX-L-GP

D2402

K A

RB751V-40H-GP

83.R2004.G8F

D2405

K A

RB751V-40H-GP

83.R2004.G8F

1 2

R2432
1KR2J-1-GP

SYSPWR_PRES

0519 DY if not enable the RTC/WeekTimer

12

R2455
100KR2J-1-GP

TOUCH_PANEL_INTR# [4,55]

TP_LOCK# [65]

+RTC_CELL_VBAT

12

R2451
100KR2J-1-GP

POWER_SW_IN#

12

C2426
SC2D2U10V3KX-L-GP

0522 Follow KY15

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Friday, November 10, 2017

Friday, November 10, 2017

Friday, November 10, 2017
Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

KBC SMSC 1416

KBC SMSC 1416

KBC SMSC 1416

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

1

24 105

24 105

24 105

A00

A00

A00

5

Main Func = SPI Flash

4

3

2

1

SPI Flash ROM1(16M) for PCH

3D3V_S5_PCH

D D

0519 Follow KY15.

SPI_CS_ROM_N0
SPI_SO_ROM_R
SPI_WP_ROM_R

Layout Note :

SKT251

1
2
3 6

EVT

4

SKT-G6179HT0321-001-GP

62.10089.011

Co-lay with SPI25

SPI_CS_ROM_N0[18]
SPI_SO_ROM[18,91]

C C

Main Func = RTC

B B

AFTP2502

RTC1

PWR

GND

NP1
NP2

BAT-AAA-BAT-054-P06-GP-U

62.70001.061

A A

5

3D3V_S5_PCH

8
7

5

R2507
10R2F-L1-GP

1

1
2
NP1
NP2

SPI_HOLD_ROM_R
SPI_CLK_ROM_R
SPI_SI_ROM_R

1 2

+RTC_VCC

+RTC_VCC

1

SPI_CS_ROM_N0

SPI_WP_ROM_R

1 2

R2502
1KR2J-1-GP

AFTP2501

12

4

3D3V_AUX_S5

12

R2503
1K6R2F-GP

12

R2505
47KR2F-GP

R2504
10MR2J-L-GP

12

4

R2501

4K7R2J-2-GP

DY

1

3D3V_RTC_SYS

RTC_PWR

Q2505

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

RN2501
SRN4K7J-8-GP

2 3

SPI25

1

CS#

2

SO

3

IO2

4

VSS

GD25B128CSIGR-GP

072.25128.0H01

D2501

1

2

BAT54C-12-GP

75.00054.A7D

D

0511 Follow KY15.

RTC_3D3V

3

12

3

SC10U6D3V3MX-GP

3D3V_S5_PCH

8

VCC

7

IO3

6

SCLK

5

SI

C2503
SCD47U10V2KX-GP

RTC_DET# [20]

C2501

SPI_HOLD_ROM_RSPI_SO_ROM_R
SPI_CLK_ROM_R
SPI_SI_ROM_R

SPI_WP_ROM_R

DY

3D3V_S5_PCH

12

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

C2502
SCD1U16V2KX-3GP

RN2503

SRN0J-6-GP

1
2 3

1
2 3

RN2502

SRN0J-6-GP

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

2

4

4

Flash/RTC

Flash/RTC

Flash/RTC

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

SPI_CLK_ROM [18,91]
SPI_SI_ROM [18,91]

SPI_HOLD_ROM [18]
SPI_WP_ROM [18]

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

25 105

25 105

25 105

1

A00

A00

A00

5

4

Main Func = Thermal Sensor

3

2

1

3D3V_S5_KBC

12

R2607

10KR2J-L-GP

D D

CMP_VOUT0[24]

DY

R2602

1 2

DY

0R2J-2-GP

KBC T8

RESET_OUT#[17,24,79]

THERM_SYS_SHDN#

Q2602

G

S

2N7002K-2-GP

DY

D

DY

C2610

SCD1U16V2KX-3GP

12

PURE_HW_SHUTDOWN# [40,79]

84.2N702.J31

2ND = 84.2N702.031

R2612 0R0402-PAD1 2

Close to Thermal sensor

3D3V_S5_KBC3D3V_AUX_S5

12

R2609

C C

DY

24K9R2F-L-GP

thermistor

12

R2610
NTC-100K-8-GP

12

R2608
25K5R2F-GP

12

C2612
SCD1U16V2KX-3GP

VD_IN1_C

Close to KBC

VD_IN1 for system thermal sensor

CMP_VIN0_R [24]

12

C2613
SC100P50V2JN-3GP

1 2

R2611
0R0402-PAD

Fan controller1

FAN_TACH1_C

AFTP2602

B B

AFTP2603

DY

A A

Layout Note:

Signal Routing Guideline:
Trace width = 15mil

5

1

FAN_VCC1

1

FAN_TACH1

FAN_VCC1

EC2602

SC10P50V2JN-L1-GP

12

DY

12

EC2601

SCD1U16V2KX-3GP

FAN1_DAC_1[24]

Layout Note:

Need 10 mil trace width.

FAN_TACH1[24]

FAN_VCC1

SC4D7U6D3V3KX-GP

5V_S0

FAN_VCC1

C2604

R2605

0R2J-2-GP

1 2

DY

12

DY

FON#

FAN_VCC1

R2606

1 2

0R0402-PAD

DY

KA

83.R5003.H8H

change the fan define & connect P/N 020.F0283.0003 by Andy 1/27

4

FAN261

1

FSM#

2

VIN

3

VOUT
VSET4GND

APL5606AKI-TRG-GP

74.05606.A71

2rd = 74.02113.0E1

3rd = 74.03940.A71

FAN_TACH1_C

FAN_VCC1

D2601

12

DY

RB551V30-GP

8

GND

7

GND

6

GND

5

3
2

1

C2603

AFTP2601

SC2200P50V2KX-2GP

3

5V_S0

C2605

SCD1U16V2KX-3GP

12

FAN1

ETY-CON3-11-GP

12

5

4

020.F0283.0003

2nd = 20.F1621.003

1

C2611

SC4D7U6D3V3KX-GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

THERMAL NCT7718W/Fan

THERMAL NCT7718W/Fan

THERMAL NCT7718W/Fan

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

26 105

26 105

26 105

1

A00

A00

A00

5

4

3

2

1

Main Func = Audio

AUD_HP1_JACK_L[29]

5V_S0 +5V_PVDD

Audio Codec Chip ALC3204

1 2

R2701
0R0805-PAD-2-GP-U

1 2

R2707
0R0805-PAD-2-GP-U

1D8V_S0

D D

R2709
0R0402-PAD-2-GP

+5V_PVDD

DVDD must >= DVDD_IO

C C

CPVDD

1 2

1D8V_S0

>2A

1 2

R2713 0R0805-PAD-2-GP-U

1 2

R2714 0R0805-PAD-2-GP-U

1 2

R2715
0R0603-PAD-2-GP-U

+3V_1D8V_DVDD3D3V_S0

C2741

12

Analog

Digital

R2719
0R0402-PAD-2-GP

moat

C2740

SCD1U16V2KX-3GP

12

1.8V power rail should be supplied by
linear regulator, not awitching
regulator.if switch regulator is
unavilable, please make sure that switch
frequency operates at out-band(over 20KHz)

1 2

12

C2710
SC10U6D3V3MX-GP

AUD_AGND

12

12

C2713

SC10U6D3V3MX-GP

12

12

C2717

SC10U6D3V3MX-GP

SC2D2U10V2KX-GP

NB_MUTE#[24]

C2714

SCD1U16V2KX-3GP

C2718

SCD1U16V2KX-3GP

+3V_1D8V_DVDD

12

DY

AUD_AGND

AUD_AGND

AUD_SPK_L+[29]

AUD_SPK_L-[29]

AUD_SPK_R-[29]

AUD_SPK_R+[29]

Layout Note:

Speaker trace
width >40mil @
2W4ohm speaker
power

R2717
100KR2J-1-GP

R2712
0R0402-PAD

C2711

SC10U6D3V3MX-GP

1 2

CPVDD

PDB_R

12

LDO2_CAP

+3V_1D8V_AVDD

+5V_PVDD1

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

+5V_PVDD1

PDB_R

AUD_HP1_JACK_R[29]

C2704

SCD1U16V2KX-3GP

12

12

HDA27

31

32

33

34

35

36

37

38

39

40

41

ALC3204-CG-GP-U

+3V_1D8V_DVDD

C2720

SC10U6D3V3MX-GP

12

place close to pin1

C2705

SC2D2U10V2KX-GP

CBP

30

29

CBP

AVSS2

LDO2-CAP

AVDD2

PVDD1

SPK-L+

SPK-L-

SPK-R-

SPK-R+

PVDD2

PDB

GND

DVDD1GPIO0/DMIC-DATA122GPIO1/DMIC-CLK3SDATA-OUT4BIT-CLK5LDO3-CAP6SDATA-IN7DVDD-IO8SYNC9DC_DET

C2721

SCD1U16V2KX-3GP

12

DMIC_DATA_R

CPVDD

C2708 SC2D2U10V3KX-L-GP

12

CBN

28

CBN

ALC3204

QFN40 (5X5)

DMIC_CLK_R

12

CPVEE

27

CPVEE

HDA_SDOUT_CODEC_R

C2709

SC2D2U10V2KX-GP

26

25

HP-OUT-R

LDO3_CAP

HDA_BITCLK_CODEC_R

12

HP-OUT-L

C2722
SC10U6D3V3MX-GP

LINE1_VREFO [29]

MIC2_VREFO [ 29]

AUD_AGND

MIC2_VREFO

LINE1_VREFO

24

23

MIC2-VREFO

LINE1-VREFO-L

HDA_CODEC_SDIN0

C2702

SC2D2U10V2KX-GP

12

AUD_VREF

LDO1_CAP

22

21

VREF

LDO1-CAP

SLEEV/MIC2-R

RING2/MIC2-L

HP/LINE1-JD_JD1

10

HDA_CODEC_SYNC

DVSS

AVDD1

AVSS1

LINE1-L

LINE1-R

VD33STB

MIC2-CAP

PCBEEP

12

LDO1_CAP

12

+5V_AVDD

20

19

18

17

16

15

14

13

12

11

+3V_1D8V_DVDD

C2723

SC4D7U6D3V3KX-GP

C2703

SC2D2U10V2KX-GP

R2702

100KR2J-1-GP

12

AUD_AGND

LINE1_L

LINE1_R

V3D3_STB

MIC_CAP

SLEEVE

RING2

AUD_SENSE_A

AUD_PC_BEEP

1 2

C2715 SC10U6D3V3MX-GP

place close to pin8

Open drain output.
pull up to DVDD or
max. 5V

RTC_AUX_S5

Layout Note:

Place close to Pin 20

AUD_AGND

AUD_AGND

1 2

R2708 0R0402-PAD-2-GP

1 2

R2716 100KR2J-1-GP

DY

3D3V_S0

LINE1_L [29]

LINE1_R [29]

SLEEVE [29]

RING2 [29]

12

+5V_AVDD

C2706

SCD1U16V2KX-3GP

12

AUD_AGND

Analog

Digital

moat

1 2

R2703
0R0603-PAD-2-GP-U

C2707

SC10U6D3V3MX-GP

V3D3_STB

DVSS

5V_S0

EC2701 SCD1U25V2KX-GP
EC2702 SCD1U25V2KX-GP
EC2703 SCD1U25V2KX-GP
EC2704 SCD1U25V2KX-GP
EC2705 SCD1U25V2KX-GP

AUD_AGND

R2704 0R0603-PAD
R2705 0R0603-PAD
R2706 0R0603-PAD

AUD_AGND

moat

moat

1 2

DY

1 2

DY

1 2

DY

1 2

DY

1 2

DY

1 2
1 2
1 2

Layout Note:

Tied at point only under
Codec or near the Codec

1 2

DMIC_DATA[55]

DMIC_CLK[ 55]

Azalia I/F EMI

HDA_CODEC_SDOUT
HDA_CODEC_BITCLK

DMIC_DATA AUD_PC_BEEP_C

12

SIO_SLP_S3#[17,24,40,51]

12

EC2710

SC22P50V2JN-4GP

DY

0602 Delete R2739

EC2711

SC22P50V2JN-4GP

1 2

R2740
0R0402-PAD-2-GP

5

Q4009_G

12

EC2709

SC22P50V2JN-4GP

DY

B B

A A

3D3V_S0

DY

HDA_SDIN0[19]

HDA_CODEC_SYNC[19]

HDA_CODEC_SDOUT[19]

HDA_CODEC_BITCLK[19]

1D8V_S5 1D8V_S0

C2737

SCD1U16V2KX-3GP

12

12

R2737
0R2J-2-GP

Q2705

G

S

2N7002K-2-GP

D

1D8V_EN#

R2718 0R0402-PAD

R2720 22R2J-2-GP

12

C2725

DY

SC10P50V2JN-L1-GP

1 2

R2724 22R2J-2-GP

1 2

R2722

0R0402-PAD-2-GP

1 2

R2723 22R2J-2-GP

150mA

12

R2736
10KR2J-L-GP

1 2

R2738
4K7R2J-2-GP

1 2

12

C2738
SCD22U10V2KX-L1-GP

1D8V_EN_R#

DMIC_DATA_R

DMIC_CLK_R

0602 DY

Close pin3

HDA_CODEC_SDIN0

HDA_CODEC_SYNC

HDA_SDOUT_CODEC_R

HDA_BITCLK_CODEC_R

0602 Delete C2727

Q2704
DMP2130L-7-GP

S

G

G

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.B31

4

AUD_SENSE[29]

HDA_SPKR_R

1 2

R2741

SPKR[19]

0R0402-PAD-2-GP

R2734

BEEP[24]

0R0402-PAD-2-GP

D

D

12

C2736

DY

SCD1U16V2KX-3GP

1 2

KBC_BEEP_R

3

+3V_1D8V_DVDD

D2703

1

2

BAT54C-12-GP

75.00054.A7D

AUD_SENSE

3

12

R2711
200KR2F-L-GP

R2710
100KR2J-1-GP

R2735

1KR2J-1-GP

12

DY

1 2

1 2

C2735

1 2

C2739

SC100P50V3JN-2GP

AUD_SENSE_A

AUD_PC_BEEP

SCD1U16V2KX-3GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Audio Codec ALC3204

Audio Codec ALC3204

Audio Codec ALC3204

A2

A2

A2

Taipei Hsien 221, Taiwan, R.O.C.

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

1

X00

X00

27 105Wednesday, November 08, 2017

27 105Wednesday, November 08, 2017

27 105Wednesday, November 08, 2017

X00

5

Main Func = Audio

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

D D

AUD_SPK_R+[27]

AUD_SPK_R-[27]
AUD_SPK_L+[27]
AUD_SPK_L-[27]

EC2902

SC1KP50V2KX-L-1-GP

EC2901

SC1KP50V2KX-L-1-GP

MIC2_VREFO[ 27]

LINE1-L_C

1 2

SC10U6D3V3MX-L-GP

LINE1-L_R

1 2

SC10U6D3V3MX-L-GP

D2901

BAT54A-11-GP

12

LINE1_VREFO_D1

1

LINE1_VREFO_D2

2

12

C C

RING2[ 27]

AUD_HP1_JACK_L[27]

LINE1_L[27]

LINE1_R[27]

AUD_HP1_JACK_R[27]

SLEEVE[27]

B B

LINE1_VREFO[27]

C2907

C2908

3

EC2903

12

R2922 1KR2J-1-GP

R2921 1KR2J-1-GP

R2904 0R0603-PAD-2-GP-U1 2

1 2

R2903 0R0603-PAD-2-GP-U
R2902 0R0603-PAD-2-GP-U1 2

1 2

R2901 0R0603-PAD-2-GP-U

SC1KP50V2KX-L-1-GP

EC2904

SC1KP50V2KX-L-1-GP

12

RN2901

2 3
1

1 2

1 2

R2912
4K7R2J-2-GP

R2913
4K7R2J-2-GP

4

SRN2K2J-1-GP

1 2

1 2

R2908 10R2F-L1-GP1 2

R2910 10R2F-L1-GP

AUD_SPK_R+_C

AUD_SPK_R-_C
AUD_SPK_L+_C
AUD_SPK_L-_C

1 2

AUD_SPK_L-_C
AUD_SPK_L+_C
AUD_SPK_R-_C
AUD_SPK_R+_C

12

DY

EC2908

SC100P50V2JN-3GP

12

DY

Speaker

SPK1

5

1

2
3
4

6

ACES-CON4-29-GP

20.F1639.004

2nd = 020.F0700.0004

3rd = 20.F1804.004

1
1

1

R2920

10KR2J-L-GP

DY

AFTP2901
AFTP2902
AFTP29031
AFTP2904

EC2907

SC100P50V2JN-3GP

12

DY

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

12

R2919

10KR2J-L-GP

12

DY

CONN Pin

Pin1

Pin2

Pin3

Pin4

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L-

Universal Jack (Moved to I/O Board)

1 2

R2906 0R0603-PAD-2-GP-U
R2907 0R0603-PAD-2-GP-U1 2

1 2

R2909 0R0603-PAD-2-GP-U
R2911 0R0603-PAD-2-GP-U1 2

EC2906

SC100P50V2JN-3GP

EC2905

SC100P50V2JN-3GP

12

DY

RING2_R
AUD_PORTA_L_R_B

JACK_PLUG

AUD_PORTA_R_R_B
SLEEVE_R

RING2_R [66]

AUD_PORTA_L_R_B [66]

JACK_PLUG [66]

AUD_PORTA_R_R_B [66]

SLEEVE_R [66]

AUD_AGND

AUD_AGND AUD_AGND

Delay circuit
(JACK_PLUG_DET: on IO Board)

JACK_PLUG

A A

5

10 mils

R2923

1 2

0R0603-PAD-2-GP-U

10 mils

12

DY

AUD_AGND

AUD_SENSE [27]

C2902
SC10U6D3V3MX-GP

4

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Audio IO

Audio IO

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

3

Date: Sheet of

2

Audio IO

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

29 105

29 105

29 105

1

A00

A00

A00

5

Main Func = LAN

4

3

2

1

Layout:
For RTL8111G(S)
* Place Ca~Cd close to each VDD10 pin-- 8, 30, 3, 22
For RTL8106E
* Place Ca,Cb close to each VDD10 pin-- 8, 30

D D

C C

C3101,R3101:
Only for
RTL8111 LDO mode.

C3118

8111G

Layout:
For RTL8111G(S)
* Place Ce and Cf close to each VDD33 pin-- 11, 32
For RTL8106E
* Place Cg and Cf close to each VDD33 pin-- 23, 32

40 mils

12

C3113

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

8111G/LAN_SW

SCD1U16V2KX-3GP

12

Ch

SCD1U16V2KX-3GP

12

Ra

1 2

R3101
0R0603-PAD-2-GP-U

L3101

La

1 2

IND-4D7UH-242-GP

LAN_SW

68.4R71E.10G

C3117

8106E

CgCfCe

C3108

SC4D7U6D3V3KX-GP

12

LAN_SW

1 2

R3104 0R0603-PAD

12

C3103

Cf: close to Pin32
Ce: close to Pin11
Cg: close to Pin23

PLT_RST#[17,55,61,63,76,91]

Cj CdCi Cc

C3115

12

LAN_SW

0512 Deleted DY part

B B

PM_LAN_ENABLE[24]

12

R3107

Ca: colse to Pin8
Cb close to Pin30
Cc: close to Pin3
Cd: close to Pin22

LAN power Noise 1V_LAN_VDD10 < 100mV Vpeak to Vpeak.

VDD10REGOUT

CbCa

C3112

SCD1U16V2KX-3GP

100KR2J-1-GP

12

1 2

R3110
0R0402-PAD

G

S

SCD1U16V2KX-3GP

12

C3124

3D3V_S5

Q3102

2N7002K-2-GP

C3119

SCD1U16V2KX-3GP

VDDREG3D3V_LAN_S5

LAN_SW

SCD1U16V2KX-3GP

C3121

SCD1U16V2KX-3GP

12

12

D

C3123

SCD1U16V2KX-3GP

12

8111G/LAN_SW

Ck

PLT_RST#_LAN

LAN_ENABLE_R_C

LAN_SW

12

Cl

12

R3106
10KR2J-L-GP

8111G/LAN_SW

C3122

SCD1U16V2KX-3GP

12

C3110
SC4D7U6D3V3KX-GP

X5R

R3111

1 2

20KR2J-L2-GP

85mA

12

C3105
SC1U10V2KX-1GP

PM_LAN_ENABLE_C

RTL8111GUS-CG RTL8111G-CGT RTL8106E-CGRTL8106EUS-CG

SWR mode

3D3V_LAN_S5

Q3101

DMP2130L-7-GP

S

D

D

G

G

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.B31

LAN CHIP (10/100/1000M & 10/100M co-lay)

71.08111.U0371.08111.W03 071.08106.0003

71.08106.003

LDO mode

SWR mode

10/100/1000M10/100/1000M

10/100M

LAN_MDI0P[32]
LAN_MDI0N[32]

LAN_MDI1P[32]
LAN_MDI1N[32]
LAN_MDI2P[32]
LAN_MDI2N[32]

C3111

SC4D7U6D3V3KX-GP

C3109

SC4D7U6D3V3KX-GP

12

12

DY

DY

Layout:
C3109 : close to Pin32
C3111 : close to Pin11

3D3V_LAN_S5 rise time must be controlled
between 0.5 mS and 100 mS.

LAN power Noise 3D3V_LAN_VDD33 < 200mV Vpeak to Vpeak.

3D3V_LAN_S5

12

C3120

SCD1U16V2KX-3GP

DY

LDO mode

10/100M

CLKREQ_PCIE#2[ 18]

R3102
2K49R2F-2-L-GP

1 2

LOM31

33

GND

1

MDIP0

2

MDIN0

3

VDD10

AVDD10

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

8

VDD10

AVDD10

RTL8111G-CGT-1-GP-U2

LAN_MDI3P[32]
LAN_MDI3N[32]

3D3V_LAN_S5
LAN_CLKREQ_LAN#
PCIE_TX_CON_P5
PCIE_TX_CON_N5
PEG_CLK2_CPU
PEG_CLK2_CPU#

1 2

R3105
0R0402-PAD

0512 Deleted DY part

3D3V_LAN_S5

(NC)

71.08111.U03

(NC)

(NC)

LAN_CLKREQ_LAN#

RSET

VDD10

LANXOUT

LANXIN

32

31

30

28

27

LED0

RSET

AVDD33

AVDD10

CKXTAL229CKXTAL1

(DVDD33)

(071.08106.0003)

(NC)

(NC)

(NC)

HSIP13HSIN14REFCLK_P15REFCLK_N

CLKREQ#

MDIP39MDIN3

AVDD33

12

10

11

REGOUT
VDDREG
VDD10
PCIE_WAKE#
ISOLATE#

PLT_RST#_LAN

PCIE_RX_CON_N5
PCIE_RX_CON_P5

C3102

1 2

SCD1U16V2KX-3GP

1 2

SCD1U16V2KX-3GP

C3107

PEG_CLK2_CPU [18]
PEG_CLK2_CPU# [18]

3D3V_S5

1 2

C3104
SC1U10V2KX-1GP

1 2

C3114 S CD1U16V2KX-3GP

R3109
1KR2J-1-GP

12

R3113
15KR2J-1-GP

12

1 2

RTL8107E-CG PN:071.08106.0003

C3116

41

1 2

SC15P50V2JN-2-GP

X3101
XTAL-25MHZ-260-GP

082.30005.0041

2 3

C3125

1 2

SC15P50V2JN-2-GP

LANXOUT

LANXIN

PCIE_RX_CON_P5
PCIE_RX_CON_N5

PCIE_TX_CON_P5
PCIE_TX_CON_N5

1

LED0

TP3103 TPAD14-OP-GP

1

LED1

TP3102 TPAD14-OP-GP

1

LED2

TP3101 TPAD14-OP-GP

25

26

LED2

LED1/GPO

(LED1)

24

(NC)

REGOUT

(GPO)

23

VDDREG

22

(NC)

DVDD10

21

LANWAKE#

20

ISOLATE#

19

PERST#

18

HSON

17

HSOP

Manual: :071.08106.000 3

16

RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW.
RTL8106E-CG (071.8107E.0A03): 10/100M <70mW.

PCIE_RX_CPU_P5 [16]
PCIE_RX_CPU_N5 [16]

PCIE_TX_CON_P5 [16]
PCIE_TX_CON_N5 [16]

R3103
10KR2J-L-GP

3D3V_S0

PCIE_WAKE# [ 24]

BOM Option

RTL8111G-CGT
(71.08111.U03)

A A

5

4

RTL8111GUS-CG
(71.08111.W03)/
RTL8106EUS-CG
(71.08106.003)

RTL8106E-CG
(071.08106.0003)

8111G

LAN_SW

8106E

1.0V
Source

LDO

SWR

LDO

CcChRa

XX

X

3

OOOO O

XXX

CeCd

O

O O O O

XX

X

2

ClCjCiLa

CgCk

XXXXX

X

XOOO

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

XXX

O

Title

Title

Title

LAN RTL8106

LAN RTL8106

LAN RTL8106

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A2

A2

A2

Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

A00

A00

31 105Wednesday, November 08, 2017

31 105Wednesday, November 08, 2017

31 105Wednesday, November 08, 2017

A00

5

4

3

2

1

Main Func = LAN

D D

LAN_MDI3N[31]

LAN_MDI3P[31]

LAN_MDI2N[31]

LAN_MDI2P[31]

LAN TransFormer (10/100/1000M & 10/100M co-lay)

XF3201 XFORM-12P-48-GP

1CT:1CT

12

11

10

10/100/1000

1CT:1CT

8

7

9

Layout:

1

3

MCT0

2

5

4

MCT1

6

MDO3-

MDO3+

MDO2-

MDO2+

Place near RJ45

AFTP3204AFTE14P-GP
AFTP3201AFTE14P-GP
AFTP3202AFTE14P-GP
AFTP3205AFTE14P-GP
AFTP3203AFTE14P-GP
AFTP3208AFTE14P-GP
AFTP3207AFTE14P-GP
AFTP3206AFTE14P-GP

1

MDO0+

1

MDO0-

1

MDO1+

1

MDO2+

1

MDO2-

1

MDO1-

1

MDO3+

1

MDO3-

MDO0+

MDO0­MDO1+
MDO2+
MDO2­MDO1­MDO3+
MDO3-

RJ45

9

CHASSIS#9

1

MDO0+

2

MDO0-

3

MDO1+

4

MDO2+

5

MDO2-

6

MDO1-

7

MDO3+

8

MDO3-

10

CHASSIS#10

RJ45

RJ45-8P-186-GP

022.10001.00C1

2nd = 022.10001.0D41

3rd = 022.10001.0C41

68.68167.30D

MCT3

XF3202 XFORM-12P-48-GP

C C

LOM_TCT

LAN_MDI1N[31]

LAN_MDI1P[31]

LAN_MDI0N[31]

LAN_MDI0P[31]

9

7

8

10

11

12

1CT:1CT

1CT:1CT

6

4

MCT2

5

2

3

MCT3

1

MDO1-

MDO1+

MDO0-

MDO0+

68.68167.30D

Layout note:

12

C3201

B B

SCD01U50V2KX-L-GP

30 mil spacing between MDI differential pairs.

Layout note:
30 mil spacing between MDI differential pairs.

MCT2
MCT1
MCT0

123

45

RN3201
SRN75J-1-GP

678

MCT

12

C3202
SC56P3KV8JN-1-GP

Follow Reference Schematic 0.01uF~0.4uF

ED3202

LAN_MDI0P
LAN_MDI0N

LAN_MDI1P
LAN_MDI1N

A A

5

1

IN1

2

4
5

NC#10

IN2

NC#9
GND3GND
IN3

NC#7

DY

IN4

NC#6

TVWDF1004AD0-1-GP

75.01004.073

10
9
8
7
6

LAN_MDI0P
LAN_MDI0N

LAN_MDI1P
LAN_MDI1N

4

LAN_MDI2P
LAN_MDI2N

LAN_MDI3P
LAN_MDI3N

ED3201

1

IN1

2

4
5

NC#10

IN2

NC#9
GND3GND
IN3

NC#7

DY

IN4

NC#6

TVWDF1004AD0-1-GP

75.01004.073

3

10
9
8
7
6

LAN_MDI2P
LAN_MDI2N

LAN_MDI3P
LAN_MDI3N

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

XFOM&RJ45

XFOM&RJ45

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

XFOM&RJ45

32 105Wednesday, November 08, 2017

32 105Wednesday, November 08, 2017

32 105Wednesday, November 08, 2017

1

A00

A00

A00

5

4

3

2

1

Main Func = Card Reader

D D

1 2

USB_CPU_PN5[16]

C C

USB_CPU_PP5[16]

R3301 0R0402-PAD-2-GP

1 2

R3302 0R0402-PAD-2-GP

Layout Note:
Close to CON1

USB_PN5_C [66]

USB_PP5_C [66]

B B

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

Card Reader-RTS5170

Card Reader-RTS5170

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

Card Reader-RTS5170

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

A00

33 105Wednesday, November 08, 2017

33 105Wednesday, November 08, 2017

33 105Wednesday, November 08, 2017

1

5

4

Main Func = USB3.0 Port1

3

2

1

USB3.0 Port1

D D

5V_S5

12

5

C3510

SC1U10V2KX-1GP

USB_PWR_EN#[24,35]

IN

4

EN#

Active Low

SY6288DAAC-GP

U3501

OUT

GND

OC#

USB30_VCCC

1
2
3

USB_OC0# [16]

USB30_VCCC

C3507

SCD1U16V2KX-3GP

12

2A

Layout Note: Close USB1

C3512

C3508

SC1U10V2KX-1GP

12

SC22U6D3V3MX-1-DL-GP

12

C3513

SC22U6D3V3MX-1-DL-GP

12

12

TC3501

DY

SC100U6D3V6MX-GP

78.10710.52L

074.06288.009B

0817 Change Cap Size

C C

Main Func = USB2.0 Port3

USB2.0 Port3 (IO Board)

USB20_VCCA

5V_S5

B B

USB_PWR_EN#[24,35]

12

C3504
SCD1U16V2KX-3GP

Support 2A

U3503

5

IN

4

EN#

Active Low

SY6288DAAC-GP

074.06288.009B

OUT

GND

OC#

USB20_VCCA

1
2
3

USB_OC2# [16]

C3517

SCD1U16V2KX-3GP

12

2A

C3515

DY

SC22U6D3V5MX-L3-GP

12

C3518

SC1U10V2KX-1GP

12

Layout Note: Close CON1

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

USB switch

USB switch

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

USB switch

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

A00

35 105Wednesday, November 08, 2017

35 105Wednesday, November 08, 2017

35 105Wednesday, November 08, 2017

1

5

4

3

2

1

Main Func = USB3.0 Port1

USB3.0 Port1

EL3601

USB_CPU_PP0[16]

USB_CPU_PN0[16]

D D

C3602
SCD1U16V2KX-3GP

USB30_TX_CPU_N1[16]

USB30_TX_CPU_P1[16]

USB30_RX_CPU_N1[16]

USB30_RX_CPU_P1[16]

C C

1 2

C3601
SCD1U16V2KX-3GP

1 2

1 2

FILTER-4P-137-GP-U

68.01012.20B

USB3_PTX_CRX_N1_R

USB3_PTX_CRX_P1_R

R3607 0R0402-PAD-2-GP1 2

R3608 0R0402-PAD-2-GP1 2

34

R3605
0R0402-PAD-2-GP

R3606
0R0402-PAD-2-GP

1 2

1 2

USB_PP0_C

USB_PN0_C

USB3_PTX_CRX_N1_C

USB3_PTX_CRX_P1_C

USB3_PRX_CTX_N1_C

USB3_PRX_CTX_P1_C

USB30_VCCC

USB_PN0_C
USB_PP0_C

USB3_PRX_CTX_N1_C
USB3_PRX_CTX_P1_C

USB3_PTX_CRX_N1_C
USB3_PTX_CRX_P1_C

USB3_PRX_CTX_N1_C USB3_PRX_CTX_N1_C
USB3_PRX_CTX_P1_C USB3_PRX_CTX_P1_C

USB3_PTX_CRX_N1_C USB3_PTX_CRX_N1_C
USB3_PTX_CRX_P1_C USB3_PTX_CRX_P1_C

USB1

1

VBUS

CHASSIS#10

D­D+

SSRX­SSRX+

SSTX­SSTX+

CHASSIS#11
CHASSIS#12
CHASSIS#13

USB3.0

PGND

GND

2
3

5
6

8
9

SKT-USB13-179-GP

022.10005.00B1

2nd = 022.10005.0831

3rd = 022.10005.00A1

Stuff for ESD R2 spec

ED3602

1

LINE_1

2

LINE_2

3

GND

4

LINE_3

5

LINE_4

AZ1045-04F-R7G-GP

NC#10

NC#9

GND
NC#7
NC#6

10
9
8
7
6

75.01045.073

10
11
12
13

4

7

1

AFTP3604

USB30_VCCC
USB_PN0_C
USB_PP0_C

1

1

AFTP3601
AFTP36021
AFTP3603

Main Func = USB3.0 Port2

USB3.0 Port2

USB2

USB30_VCCC

USB_PN1_C

EL3602

USB_CPU_PN1[16]

USB_CPU_PP1[16]

1 2

FILTER-4P-137-GP-U

34

USB_PN1_C

USB_PP1_C

68.01012.20B

C3605

B B

USB30_TX_CPU_N2[16]

USB30_TX_CPU_P2[16]

USB30_RX_CPU_N2[16]

USB30_RX_CPU_P2[16]

A A

SCD1U16V2KX-3GP

1 2

C3604
SCD1U16V2KX-3GP

1 2

USB_PN1_C

USB_PN0_C USB_PP0_C

USB3_PTX_CRX_P2_R

R3611 0R0402-PAD-2-GP1 2

1 2

R3612 0R0402-PAD-2-GP

Stuff for ESD R2 spec

ED3604

1

I/O1

2

I/O4

GND

VDD

I/O23I/O3

AZC099-04S-2-GP

6

5

4

R3609

1 2

0R0402-PAD-2-GP

R3610

1 2

0R0402-PAD-2-GP

USB_PP1_C

USB3_PTX_CRX_N2_CUSB3_PTX_CRX_N2_R

USB3_PTX_CRX_P2_C

USB3_PRX_CTX_N2_C

USB3_PRX_CTX_P2_C

USB30_VCCC

12

C3618

DY

SCD1U16V2KX-3GP

USB_PP1_C

USB3_PRX_CTX_N2_C
USB3_PRX_CTX_P2_C

USB3_PTX_CRX_N2_C
USB3_PTX_CRX_P2_C

USB30_VCCC
USB_PN1_C
USB_PP1_C

1

VBUS

CHASSIS#10

D­D+

SSRX­SSRX+

SSTX­SSTX+

CHASSIS#11
CHASSIS#12
CHASSIS#13

USB3.0

2
3

5
6

8
9

SKT-USB13-179-GP

022.10005.00B1

2nd = 022.10005.0831

3rd = 022.10005.00A1

Stuff for ESD R2 spec

ED3603

1

LINE_1

2
3
4
5

NC#10

LINE_2

NC#9

GND
LINE_3
LINE_4

AZ1045-04F-R7G-GP

75.01045.073

2nd = 75.00107.073

GND
NC#7
NC#6

1

075.09904.0A7C

5

4

3

PGND

GND

10
9
8
7
6

AFTP36051
AFTP3606
AFTP36071

10
11
12
13

4

7

USB3_PRX_CTX_N2_CUSB3_PRX_CTX_N2_C
USB3_PRX_CTX_P2_CUSB3_PRX_CTX_P2_C

USB3_PTX_CRX_N2_CUSB3_PTX_CRX_N2_C
USB3_PTX_CRX_P2_CUSB3_PTX_CRX_P2_C

1

AFTP3608

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

USB30

USB30

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

USB30

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

36 105Wednesday, November 08, 2017

36 105Wednesday, November 08, 2017

36 105Wednesday, November 08, 2017

1

A00

A00

A00

5

4

3

2

1

Main Func = USB2.0 Port3

D D

USB port 3 (USB2.0 only) CMC

1 2

R3701

DY

0R2J-L-GP

EL3706

USB_CPU_PN2[16]

C C

USB_CPU_PP2[16]

1 2

34

FILTER-4P-137-GP-U

68.01012.20B

1 2

R3702

DY

0R2J-L-GP

Layout Note:
Close to CON1

USB_PN2_C

USB_PP2_C

USB_PN2_C [66]

USB_PP2_C [66]

USB ESD Diode

Stuff for ESD R2 spec

ED3704

B B

USB_PP2_C USB_PN2_C

1

I/O1

2

GND

DY

I/O23I/O3

AZC099-04S-2-GP

I/O4

VDD

6

5

4

Layout Note:
Close to CON1

075.09904.0A7C

A A

5

4

USB20_VCCA

DY

3

12

C3706
SCD1U16V2KX-3GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

USB20

USB20

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

USB20

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

37 105Wednesday, November 08, 2017

37 105Wednesday, November 08, 2017

37 105Wednesday, November 08, 2017

1

A00

A00

A00

5

Main Func = Power Plane & Sequence

ROSA Run Power

0519 Follow KY15 to delete DY part

5V_S5

3D3V_S5

D D

SIO_SLP_S3#[17,24,27,40,51]

C C

R4010
0R0402-PAD

1 2

5V_S5

3V5V_S0_ON

12

U4001

1

VIN1#1

2

VIN1#2

6

VIN2#6

7

VIN2#7

4

VBIAS

3

EN1

5

EN2

AP22966DC8-7-GP

074.22966.0093

0522 Follow EC vendor Marc suggest.

1 2

R4012
0R2J-L-GP

D4001

2
1

C4009

SC10U6D3V3MX-GP

R4006

20KR2J-L2-GP

12

0519 Follow KY15 to change cap value

LBAS16LT1G-GP

83.00016.P11

1 2

R4009 10KR2J-L-GP

VOUT1#13
VOUT1#14

VOUT2#8
VOUT2#9

GND
GND

DY

SS1
SS2

4

5V_S0

5V_S0

C4005

SC10U6D3V3MX-GP

12

SC10U6D3V3MX-GP

5V_S0 Comsumpti on
Peak current 5A

3D3V_S0

3D3V_S0 Comsump tion
Peak current 2. 5A

13
14

8
9

3V5V_CT1

12

3V5V_CT2

10

12

11
15

3

3D3V_S0

C4001

SC470P50V2KX-3GP

12

PURE_HW_SHUTDOWN# [26,79]3V_5V_EN[45]

ALWON [24]

C4004

12

C4002

SC470P50V2KX-3GP

3

PWR_VDDQ_PG[51]

RSMRST_PWRGD#

[#543016] Optional, Added for addition system robustness

0511 Follow KY15.

VIL > 0.7 V, VIH < 2 V
Rds(on) = 11 mΩ @ VDD = 4 V
Ids(max) 10 A

1D0V_S5_PWRGD[53]

PRIM_PWRGD[24,54]

3V_5V_POK[17,21,45,53,54]

NON DS3: PH 3V_5V_POK to 3D3V_AUX_S5 at page17

1 2

SIO_SLP_S3#[17,24,27,40,51]

R4034
0R0402-PAD

VCCSTG should only ramp up equal to or after VCCST.

2

Power Good

1 2

R4011
0R0402-PAD

D4002

3

1 2

R4029 0R0402-PAD

1 2

R4030 0R0402-PAD

1 2

R4033 0R2J-2-GP

DY

5V_S5

VCCSTG_EN_R

12

C4017

DY

SCD1U16V2KX-3GP

1
2

DY

LBAS16LT1G-GP

83.00016.P11

VCCSTG and VCCIO

C4029

SC1U10V2KX-1GP

12

DY

3D3V_S0

12

R4005
1KR2J-1-GP

1 2

R4002
0R0402-PAD

3D3V_S5_KBC3D3V_S5

12

12

R4031

100KR2J-1-GP

U4002

1

VIN

2

VIN

3

VBIAS

4

EN

APE8939GN3-GP

R4032

DY

100KR2J-1-GP

+VCCIO(ICCMAX = 2.73A)

8

VOUT#8

7

VOUT#7

6

VOUT#6

5

GND

9

VIN

074.08939.0093

U4002 U4006 change to 074.08939.0093
for quality issue change 2/26

RSMRST_PWRGD#

1D0V_S5

1

ALL_SYS_PWRGD [17,24]

VR_EN [46]

+VCCIO

12

C4016

SC10U6D3V3MX-GP

12

+VCCSTG(ICCMAX.=0.16A)
Trise=10US < TR < 65US

1 2

R4048
0R0805-PAD-2-GP-U

C4007

SC10U6D3V3MX-GP

+VCCSTG

MANAGEMENT RAIL POWER GENERATION

5V_S5

12

C4028

SC1U10V2KX-1GP

B B

1 2

SIO_SLP_S4#[17,44,51 ]

R4024
0R0402-PAD

DY

VCCSTU_EN_R

C4018

SCD1U16V2KX-3GP

12

DY

VIL > 0.7 V, VIH < 2 V
Rds(on) = 11 mΩ @ VDD = 4 V
Ids(max) 10 A

U4006

1

VIN

2

VIN

3

VBIAS

4

EN

APE8939GN3-GP

VOUT#8
VOUT#7
VOUT#6

GND

8
7
6
5

9

VIN

+V1.00U_CPU_LS

12

R4025
0R0805-PAD-2-GP-U

1D0V_S5

C4013

SC10U6D3V3MX-GP

1 2

+V1.00U_CPU

12

C4012

SC10U6D3V3MX-GP

VCCST

074.08939.0093

U4002 U4006 change to 074.08939.0093
for quality issue change 2/26

VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization.

A A

5

4

+V1.00U_CPU +VCCST_CPU

1 2

R4036
0R0402-PAD-2-GP

0.04 A

3

EOPIO and EDRAM

20170428

V1.8S

20170428

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Taipei Hsien 221, Taiwan, R.O.C.

Power Plane Enable

Power Plane Enable

Power Plane Enable

40 105

40 105

40 105

1

A00

A00

A00

5

4

3

2

1

Main Func = Power & Sequence

D D

3D3V_S5 3D3V_S5_PCH

1 2

R4101
0R0805-PAD-2-GP-U

C C

B B

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

Connected_Standby(1/2)+DS3

Connected_Standby(1/2)+DS3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

Connected_Standby(1/2)+DS3

A4

A4

A4

2

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

A00

41 105Wednesday, November 08, 2017

41 105Wednesday, November 08, 2017

41 105Wednesday, November 08, 2017

1

5

Main Func = ADT Input

Layout Note:

PSID Layout width > 25mil

1 2

PR4317

12

PR4312
100KR2J -1-GP

DY

12

PR4313
0R0402-P AD

0R0603-P AD

D D

1 2

EL4303
0R0805-P AD-2-GP-U

1 2

EL4304
0R0805-P AD-2-GP-U

PS_ID_R

+DC_IN

12

DY

JGND JGND

+DC_IN

1

PS_ID_R

1

+DC_IN

1

JGND

EC4301

1
1

0921 Install

SC10U25V5KX-L-GP

12

AFTP430 1
AFTP431 5

EC4302

SCD1U25V2KX-GP

DCIN1

8
6
5
4
3
2

1
7

ACES-CON 6-63-GP

20.F2132.006

2nd = 20.F 2505.006

C C

AFTP431 3
AFTP431 2
AFTP431 4

4

PD4303
PESD24V S2UT-GP

12

PR4314
3K3R6J-G P

PQ3809_ D

AC_IN#_G

PS_ID_R2

1

2

3

20170810
ESD 600W TVS

PD4301

A K

PQ4306

3 4

2

1

2N7002K DW-GP

84.2N702.A3F

2nd = 84.2 N702.E3F

3rd = 75.00 601.07C

P6SMBJ24A-H-GP

5

6

12

PR4309
100KR2J -1-GP

PQ3802_ 1

12

PR4302
15KR2F-G P

PC4302

SCD1U50V3KX-GP

12

AC_IN_KBC #

1 2

PR4306

DY

33R2J-2-G P

PQ4301
DMN5L06 K-7-GP

D S

B

B

1

84.05067.031

G

PSID_DISABLE #_R_C

C

PQ4302
LMBT390 4LT1G-GP

84.T3904.H11

E

AC_DIS [24,44]

PQ4304

C

R1

E

R2

LMUN521 2T1G-GP

84.05212.B11

TP4301
TPAD14-O P-GP

PS_ID_R1

AD_OFF_ L

3

1 2

PR4305
33R2J-2-G P

1 2

PR4303
10KR2J-L -GP

PQ4305

1

LTA024E UB-FS8-GP

84.00024.01K

2

3D3V_S53D3V_S5

1

2

75.00099.O7D

2nd = 75.0 0099.K7D
3rd = 75.00 099.Q7D

PD4302

3

LBAV99L T1G-1-GP

5V_S5

R2

2

R1

AD_OFF_ R

3

12

PR4304
2K2R2J-L 1-GP

PS_ID [2 4]

Id=-9.6A
Qg=-25nC

12

PR4307

240KR3-GP

12

PR4308

47KR3J-L-GP

Rdson=18~30mohm

1
2
3
4 5

AON7403 -GP-U

84.07403.037

+DC_IN AD+

PC4301

SC1U50V3KX-GP

12

PU4301

S
S
S
G D

8

D
D

7

D

6

20170502 remove DCIN2

PC4304

PC4303

12

DY

DY

12

12

SCD01U5 0V2KX-L-GP
SCD01U5 0V2KX-L-GP
SCD01U5 0V2KX-L-GP

1

PC4306

PC4305

SC10U25V5KX-L-GP

12

Main Func = M-BAT Input

BT+

B B

5

PBAT_CH G_SMBCLK
PBAT_CH G_SMBDAT

PBAT_PR ES#

AFTP430 3
AFTP430 8
AFTP430 4
AFTP430 7
AFTP430 6
AFTP430 2
AFTP430 5

PBAT_CH G_SMBCLK[2 4,44]
PBAT_CH G_SMBDAT[24,4 4]

PBAT_PR ES#[24,4 4]

PBAT_PR ES1#
PBAT_SM BDAT1
PBAT_SM BCLK1

A A

BT+
BT+
BT+
SYS_PRES1 #

1
1
1
1
1
1
1

12

DY

EC4309

12

12

DY

DY

SC10P50 V2JN-L1-GP
SC10P50 V2JN-L1-GP
SC10P50 V2JN-L1-GP

EC4308

EC4310

20170502 remove BATT2

12

EC4307

SCD1U50V3KX-GP

DY

SCD1U25V2KX-GP

PD4304

DY

SMF18A-G P

A K

0921 Install

2 3

RN4302 SRN10 0J-3-GP

1

4

1 2

R4302
100R2J-L -GP

EC4306

12

4

Batt Connecter

PBAT_SM BCLK1
PBAT_SM BDAT1
PBAT_PR ES1#
SYS_PRES1 #

12

R4301
0R0402-P AD

Layout note:
SYS_PRES1# >40 mil

BATT1

9
1

2
3
4
5
6
7
8

10

ALP-CON8 -17-GP-U1

20.82003.008

2nd = 20.8 1775.008

3rd = 020.8 0842.0008

1

AFTP431 1

1

AFTP430 9

1

AFTP431 0

Placement: Close to Batt Connector

PBAT_PRES1#

3

D4304
LBAV99L T1G-1-GP

75.00099.O7D

1

2

2nd = 75.00099.K7D

3rd = 75.00099.Q7D

3

2nd = 75.00099.K7D

3rd = 75.00099.Q7D

1

PBAT_SMBDAT1

3

2

D4305
LBAV99L T1G-1-GP

75.00099.O7D

2

PBAT_SMBCLK1

3

D4306
LBAV99L T1G-1-GP

75.00099.O7D

1

2

3D3V_S5 _KBC

2nd = 75.00099.K7D

3rd = 75.00099.Q7D

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

DCIN

DCIN

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

DCIN

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

43 105Wedn esday, November 08, 20 17

43 105Wedn esday, November 08, 20 17

43 105Wedn esday, November 08, 20 17

1

A00

A00

A00

5

4

3

2

1

Main Func = Charger

AD+ +SDC_IN

PQ4410

1

8

S

D

S

D

2

7

S

D

3

6

GD

45

AON7403-GP-U

84.07403.037

D D

PWR_CHG_REGN

12

PR4417
100KR2J-1-GP

C C

B B

ACOK_IN[17,24]

PBAT_CHG_SMBDAT[24,43]

PBAT_CHG_SMBCLK[24,43]

12

PR4418
191KR2F-1-GP

0R0402-PAD

1 2

1 2

0R0402-PAD

PR4470

PR4471

3D3V_AUX_S5

12

DY

12

PR4435

10KR2F-L1-GP

DY

H_PROCHOT#

AD_IA[24]

boost_mon[24]

P_SYS[46]

12

PR4450

100KR2F-L3-GP

PR4449

10KR2F-L1-GP

DY

ACOK_IN

12

PR4420
10KR2F-L1-GP

DC_IN_D

AC_IN:3.35~3.75V

DY

PR4474

0R0402-PAD

1 2

PR4475 0R0402-PAD

PR4476 0R0402-PAD

12

PC4402

SC2K2P50V2KX-L-GP

VDD

12

PR4402

CCLIM

ACLIM

12

PR4404

DY

2N7002KDW-GP

ACOK_IN

2nd = 84.2N702.E3F

4th = 84.DMN66.03F

3rd = 75.00601.07C

VAC DET
Greater than 2.633 V
Less than 3.5 V

VDD

12

12

PR4434

300KR2F-L-GP

PR4451

100KR2F-L3-GP

DY

1 2

1 2

12

12

PC4403

PC4404

SC2K2P50V2KX-L-GP

SC2K2P50V2KX-L-GP

DY

12

PR4401

200KR2F-L-GP

200KR2F-L-GP

12

PR4403

82K5R2F-GP

95K3R2F-GP

DY

3 4

2

5

1

6

PQ4405

84.2N702.A3F

12

PR4411

DY

AD+

12

12

1KR2F-L1-GP

Need fine tune

Battery PROCHOT# Circuit

BP_D

D

2ND = 84.2N702.031

3rd = 84.07002.I31

PBAT_PRES#[24,43,44]

PQ4402

2N7002K-2-GP

84.2N702.J31

A A

PR4415

5

1 2

0R0402-PAD

H_PROCHOT#[4,24,44,46]

3D3V_S5

12

PR4472

100KR2F-L3-GP

DY

12

PC4433
SCD47U25V3KX-1GP

BP_G

G

12

S

PR4478
100KR2J-1-GP

4

12

PR4441
100KR2J-1-GP

AD+_G_2

12

PR4422
10KR2F-L1-GP

AD+_G_1

DY

DCBATOUT

12

PR4477
1KR2F-L1-GP

SC1KP50V2KX-L-1-GP

PC4409

12

PC4407

SC1KP50V2KX-L-1-GP

12

PR4452
150KR2F-L-GP

PWR_CHG_ACDET

PC4419

SCD01U50V2KX-L-GP

PR4416

18K7R2F-GP

12

PU4401

1

ACIN

2

PWR_CHG_SDA PWR_CHG_PHASE

PWR_CHG_SCL

PWR_CHG_AMON

ACOK

3

SDA

4

SCL

5

PROCHOT#

6

AMON

7

BMON

8

PSYS

33

GND

PR4405

147KR2F-GP

12

12

PWR_CHG_CMSRC

PWR_CHG_ASGATE

PWR_CHG_ACP

PWR_CHG_ACN

PWR_OPCN

32

31

30

29

28

CSIP

CSIN

QPCN

CMSRC

ASGATE

ISL95521AHRZ-T-GP

074.95521.0A73

Use bom change to ISL88739
(P/N: 074.8873 9.0073)

PROG9COMP10CCLIM11FSET12BATGONE13CSON

PWR_CHG_COMP

PWR_CHG_BATGONE

PWR_CHG_PROG

PWR_CHG_FSET

PR4407

100R2F-L3-GP

PR4406 0R0402-PAD

12

PC4406

SC470P50V2KX-L-GP

PC4405

SCD022U25V2KX-DLGP

PR_2

PR4439

1 2

100KR2F-L3-GP

12

12

PC4436
SC10P50V2JN-L1-GP

D01R3721F-GP-U

PG4429
GAP-CLOSE-PWR-3-GP

1 2

PG_1

12

PR4467

0R0402-PAD-1-GP

PC4467

SC2K2P50V2KX-L-GP

12

12

PC4408

SC1KP50V2KX-L-1-GP

PWR_CHG_BATDRV

PWR_VBAT

PWR_OPCP

27

26

25

VBAT

QPCP

BGATE

BOOT

UGATE

PHASE

LGATE

VDDP

VDD

DCIN

NTC

CSOP

ACLIM

14

15

16

3D3V_AUX_S5

DY

1 2

Change net name from BAT_IN# to PBAT_PRES#
by power team Edward 1/30

PR4426

1 2

PC4466
SCD1U25V2KX-GP

1 2

PWR_CHG_ACP

PR4454
100R5F-2-GP

1 2

24

23

22

21

20

19

18

17

PWR_CHG_SRP

PWR_CHG_SRN

12

PR4409
100KR2F-L3-GP

PBAT_PRES#

3

DCBATOUT

1 2

PG_2

12

PWR_CHG_ACN

BT+

PWR_CHG_BTST

PWR_CHG_HIDRVPWR_CHG_ACOK

PWR_CHG_LODRV

PWR_CHG_REGN

VDD

PWR_CHG_DCINPWR_CHG_BMON

PWR_CHG_NTC

12

PR4410

DY

7K15R2F-L-GP

PWR_CHG_NTC_1

12

PR4412

DY

NTC-220K-1-GP-U

PG4407
GAP-CLOSE-PWR-3-GP

PR4468
2R2F-GP

12

PC4468

DY

SC2K2P50V2KX-L-GP

PR4428
0R0603-PAD-1-GP-U

1 2

12

PC4435
SC1U50V3KX-GP

PBAT_PRES# [24,43,44]

SCD22U25V3KX-GP

PWR_CHG_BTST1

VDD

PR4438

1 2

4D7R3F-L-GP

12

PC4446
SC1U10V2KX-1GP

PR4437
2R2F-GP

1 2

DCBATOUT

PC4431

1 2

PWR_CHG_DCIN_R

PD4404

K A

RB551V30-GP

PD4404_K

PR4459
0R0402-PAD

1 2

AD+

12

PR4445
470KR2J-L1-GP

12

PC4445
SC1U10V2KX-1GP

PD4404_A

PR4440
20KR3J-1-GP

1 2

12

PR4414

DY

3

B

SM4378NSKPC-TRG-GP

SM4378NSKPC-TRG-GP

PWR_CHG_REGN

PD4410

1

2

BAT54C-12-GP

75.00054.A7D

SIO_SLP_S4#[17,40,51]

AD+

12

PR4431
100KR2J-1-GP

1MR2J-1-GP

PQ4409_E

E

PQ4409

MMBT3906-7F-GP

84.03906.P11

C

PQ4409_C

12

PR4455
680KR2F-GP

AD+_R

PQ4412

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

PU4411

PU4412

AD+

PWR_CHG_DCIN_D

12

PR4462

0R0402-PAD

2

+VCHGR

PQ4401

1

8

S

D

S

D

2

7

S

D

3

6

G D

4 5

AON7403-GP-U

84.07403.037

AC_DIS_R

G

S

DCBATOUT

567

8

DDD

D

65 BOM

G

4

SSS

123

084.04378.0037

PWR_CHG_PHASE

5

6

7

8

DDD

D

65 BOM

G

4

SSS

123

084.04378.0037

PQ4415
LMUN5212T1G-GP

84.05212.B11

C

R1

B

E

R2

CPU PROCHOT# Circuit

PR4458
0R0402-PAD

1 2

PQ4406

PQ4406_3

3 4

PQ4406_2

2

1

12

2N7002KDW-GP

PR4408

DY

0R2J-2-GP

PWR_CHG_ACOK

3D3V_S5

PR4444
1KR2J-1-GP

12

PC4471
SCD22U10V2KX-L1-GP

PC4427

PC4418

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

12

12

PL4401

1 2

COIL-4D7UH-33-GP

68.4R71A.20H

PR4481
0R2J-2-GP

12

DY

213

PQ4416
LTA024EUB-FS8-GP

84.00024.01K

R2

R1

SC2K2P50V2KX-L-GP

PQ4416_1

H_PROCHOT# [ 4,24,44,46]

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

PQ4406_5

5

6

12

12

1 2

PC4438

SC10U25V5KX-L-GP

12

DY

PC4439

SC1U10V2KX-1GP

PQ4406_6

PR4453

10KR2F-L1-GP

AC_DIS [24,43]

PC4459

SC10U25V5KX-L-GP

PC4456

SCD1U25V2KX-GP

12

12

+VCHGR

PR4443

1 2

D01R3721F-GP-U

PG4428

GAP-CLOSE-PWR-3-GP

1 2

BT+

PWR_CHG_SRP_R

12

PR4456
2R2F-GP

PC4463
SCD1U25V2KX-GP

1 2

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A2

A2

A2

Date: Sheet

Date: Sheet

Date: Sheet

PC4461

12

DY

PR4413

100KR2F-L3-GP

1 2

symbol name change by Andy 1/19

PG4426

GAP-CLOSE-PWR-3-GP

1 2

PWR_CHG_SRN_R

12

PR4457
0R0402-PAD-1-GP

DY

PC4462
SC2K2P50V2KX-L-GP

1 2

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Charger

Charger

Charger

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

BT+

PC4410

SC10U25V5KX-L-GP

PC4401

SC10U25V5KX-L-GP

12

12

BT+

PC4453

PC4452

SC10U25V5KX-L-GP

PC4464

SC10U25V5KX-L-GP

12

DY

44 105Wednesday, November 08, 2017

44 105Wednesday, November 08, 2017

44 105Wednesday, November 08, 2017

SCD1U25V2KX-GP

12

12

A00

A00

A00

of

of

of

A

B

C

D

E

Main Func = 3D3V_5V

3D3V_AUX_S5

12

4 4

3V_5V_EN[40]

DCBATOUT

3 3

Design Current=3.5A

5.25A<OCP>6.3A

3D3V_S5

3D3V_PWR

PG4526

12

GAP-CLOSE-PWR

PG4517

12

GAP-CLOSE-PWR

PG4528

12

GAP-CLOSE-PWR
PG4522

12

GAP-CLOSE-PWR

PG4529

12

GAP-CLOSE-PWR

2 2

3D3V_PWR

12

DY

PWR_DCBATOUT_3D3V

PG4525

12

GAP-CLOSE-PWR

PG4521

12

GAP-CLOSE-PWR

PG4524

12

GAP-CLOSE-PWR
PG4531

12

GAP-CLOSE-PWR

PC4517

SCD1U16V2KX-3GP

79.22710.3KL

6K65R2F-GP

12

PT4502

PR4512

SE220U6D3VM-38-GP

PC4525

SCD1U50V3KX-GP

12

PL4502

1 2

IND-3D3UH-57-GP-U

68.3R310.20A

PG4535

12

GAP-CLOSE-PWR-3-GP

3V_FEEDBACK

12

12

PR4535
0R2J-2-GP

DY

PWR_3D3V_FB2_R

12

PC4523
SC18P50V2JN-1-GP

DY

12

PR4523
10KR2F-L1-GP

PC4528

SC10U25V5KX-L-GP

12

PR4533

2D2R5F-2-GP

Change PU4503 from 074.06575.0A to

74.51225.073 by power change 2/26

PC4509

SC4D7U25V5KX-L2-GP

12

DY

678

DDD

PU4504
AON7410-GP

84.07410.A3765 BOM

PC4535

PWR_3D3V_VBST2_1

PU4505

3V_5V_POK[17,21,40,53,54]

AON7410-GP

12

SCD1U50V3KX-GP

PR4517 change to 127K
by PWR team Jerry

SSS

G D

123

4 5

12

DY

678

DDD

PWR_3D3V_SNUB

65 BOM

SSS

G D

123

4 5

PC4520

SC330P50V2KX-3GP

12

DY

84.07410.A37

3D3V_S5

PR4534

100KR2J-1-GP

PH at Page17

PR4528

1 2

1D5R3-GP

12

PR4517
127KR2F-L-GP

12

DY

Close to VFB Pin (pin5)

0R2J-2-GP

PR4530

DY

0R2J-2-GP

PWR_3D3V_VBST2

PWR_3D3V_DRVH2

PWR_3D3V_LL2

PWR_3D3V_DRVL2

PWR_3D3V_FB2

PWR_3D3V_EN2

PWR_3D3V_CS2

SC4D7U6D3V3KX-GP

3D3V_PWR_2

1 2

PR4505

0R0402-PAD

PR4501

12

3D3V_PWR_2

3D3V_AUX_S5

DY

PWR_5V_EN1_R

12

PR4504
0R0402-PAD

PU4503

9

VBST2

10

DRVH2

8

SW2

11

DRVL2

4

VFB2

6

EN2

5

CS2

TPS51225RUKR-GP

74.51225.073

7

PGOOD

PC4526

PR4502

0R0402-PAD

PWR_5V_EN1

1 2

PR4503

0R0402-PAD

PWR_3D3V_EN2

1 2

DCBATOUTPWR_DCBATOUT_3D3V

PC4519

SC10U25V5KX-L-GP

PC4531

SCD01U50V2KX-L-GP

12

12

12

VIN

PWR_5V_VBST1

17

VBST1

PWR_5V_DRVH1

16

DRVH1

PWR_5V_LL1

18

SW1

PWR_5V_DRVL1

15

DRVL1

PWR_5V_VO1

14

VO1

PWR_5V_FB1

2

VFB1

PWR_5V_EN1

20

EN1

PWR_5V_CS1

1

CS1

PWR_5V_VCLK

19

VCLK

21

GND

VREG3

VREG5

3

13

5V_PWR_2

12

12

PC4524
SC1U50V3KX-GP

PR4524

1

1D5R3-GP

TP4501

TPAD14-OP-GP

1

PWR_5V_VBST1_1

2

12

PR4531
127KR2F-L-GP

PR4531 change to 127K
by PWR team Jerry

PC4516

1 2

SCD1U50V3KX-GP

84.07410.A37

PU4501

AON7410-GP

PU4502

AON7506-GP

84.07506.037

65 BOM

65 BOM

G

4

DCBATOUT

678

DDD

GD

4 5

567

DDD

PWR_DCBATOUT_5V

12

SSS

123

8

D

SSS

123

SC18P50V2JN-1-GP

PWR_DCBATOUT_5V

PG4520

12

GAP-CLOSE-PWR

PG4536

12

GAP-CLOSE-PWR

PG4518

12

GAP-CLOSE-PWR

PG4534

12

GAP-CLOSE-PWR
PG4542

12

GAP-CLOSE-PWR
PG4543

12

GAP-CLOSE-PWR

PC4529

PC4530

SCD1U50V3KX-GP

12

PL4501

1 2

IND-2D2UH-46-GP-U1

12

68.2R210.20B

PR4529
2D2R5F-2-GP

DY

PWR_5V_SNUB

12

PC4536

DY

SC560P50V-GP

PR4525

0R2J-2-GP

PWR_5V_FB1_R

PC4522

SC4D7U25V5KX-L2-GP

PC4527

SC10U25V5KX-L-GP

12

Design Current=6.85A

10.275A<OCP>12.33A

5V_PWR

PG4532

GAP-CLOSE-PWR-3-GP

12

12

12

DY

PR4527
15K4R2F-GP

12

DY

12

PR4526
10KR2F-2-GP

PC4518

12

DY

SCD1U16V2KX-3GP

20170810
5V output voltage modify

12

PT4501

SE220U6D3VM-38-GP

79.22710.3KL

5V_PWR

5V_S5

PG4527

12

GAP-CLOSE-PWR

PG4519

12

GAP-CLOSE-PWR

PG4538

12

GAP-CLOSE-PWR

PG4537

12

GAP-CLOSE-PWR
PG4533

12

GAP-CLOSE-PWR

PG4523

12

GAP-CLOSE-PWR
PG4541

12

GAP-CLOSE-PWR
PG4540

12

GAP-CLOSE-PWR
PG4545

12

GAP-CLOSE-PWR

PG4544

12

GAP-CLOSE-PWR

Close to VFB Pin (pin2)

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A

1 1

O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037

A

B

C

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B
O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A2

A2

A2

Date: Sheet

Date: Sheet

D

Date: Sheet

DCDC-3D3V&5V

DCDC-3D3V&5V

DCDC-3D3V&5V

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

E

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

of

of

45 105Wednesday, November 08, 2017

45 105Wednesday, November 08, 2017

45 105Wednesday, November 08, 2017

A00

A00

A00

5

4

3

2

1

Main Func = CPU_CORE

https://shop62935598.taobao.com

+VCCST_CPU

20170427

D D

1 2

PC4610
SC33P50V2JN-3GP

PWR_VCCGT_FB_RC

PC4623

SC2K2P50V2KX-L-GP

1 2

PWR_VCCGT_ISUMN_RC

12

PR4645

1KR2F-L1-GP

20170810
New Common Part

12

U42

PC4638

H_PROCHOT#[4,24,44]

SC330P50V2KX-3-DL-GP

20170810
IA VRHot

PR4616
5K76R2F-2-GP

PR4626
3K3R2F-2-GP

1 2

PR4630
2KR2F-L1-GP

1 2

PR4636
499R2F-2-GP

1 2

20170810
IA OCP

12

PR4642

324R2F-GP

20170810
GT IMON

4

12

1 2

PR4669 0R2J-L-GP

DY

5V_S5

12

12

PR4635

PR4670

267R2F-1-GP

U22

U22

20170810
GT VRHot

12

PR4662

4K75R2F-1-GP

PWR_VCORE_NTC1

12

PR4661

88K7R2F-GP

PR4654

NTC-470K-9-GP-U

12

Place near high side MOSFET of Phase1
B=3940K

PR4608
90K9R2F-GP

1 2

U42

PR4672
88K7R2F-GP

1 2

U22

PC4604
SC330P50V2KX-3-DL-GP

1 2

20170810
New Common Part

PR4617 NTC-470K-9-GP-U

PR4621 27K4R2F-GP

PC4651 SC1KP50V2KX-L-1-GP

PC4612 SC2K2P50V2KX-L-GP

0707 Modify by PWR Jerry

PC4661 SC470P50V2KX-3GP

PC4614 SC330P50V2KX-3GP

C C

1 2

PR4631
100R2F-L3-GP

PR4639
100R2F-L3-GP

PC4622

PR4641

2K61R2F-1-GP

DY

PR4665

1 2

0R0402-PAD-1-GP

PR4666
0R0402-PAD-1-GP

1 2

1 2

DY

12

SCD01U50V2KX-L-GP

12

12

PR4646
NTC-10K-29-GP-U

Place near Phase1 choke
B=3370K

PR4643

12

12

PC4633
SCD1U25V2KX-GP

VCC_CORE

VCC_SENSE[7]

VSS_SENSE[7]

PWR_VCCGT_ISUMP[48]

PWR_VCCGT_ISUMN_P_2

B B

PWR_VCCGT_ISUMN[48]

Place near high side MOSFET of Phase1
B=3940K

1 2

1 2

12

12

12

U42

12

U22

12

PC4615

DY

SCD01U50V2KX-L-GP

PWR_VCCGT_FB2

12

PC4619

DY

SC1KP50V2KX-L-1-GP

20170810
IA RC time constant

PC4609

SCD01U50V2KX-L-GP

12

12

U22

11KR2F-L-GP

PWR_VCCGT_ISUMN_P_1

1 2

PC4618
SC1KP50V2KX-L-1-GP

PC4662
SC220P50V2KX-3GP

0707 Modify by PWR Jerry

PC4628

SCD033U25V2KX-GP

PC4653

12

U42

PR4647
0R0402-PAD-1-GP

PWR_VCCGT_ISEN1[48]

PWR_VCCGT_ISEN2[48]

PWR_VCCGT_NTC1

PWR_VCCGT_COMP1

PWR_VCCGT_FB1

1 2

PR4671 1K54R2F-GP

U22

1 2

PR4633 3K01R2F-3-GP

U42

1 2

U22

1 2

U42

SCD047U25V2KX-GP

PC4630

SCD1U25V2KX-GP

12

PWR_VCCGT_FCCM#[48]

PWR_VCCGT_PWMA[48]

PWR_VCCGT_PWMB[48]

U22 U42

PC4625

PC4626

PR4669

PR4635

PR4670

PC4630

A A

PC4609

PC4653

PR4671

PR4672

PC4614

PC4618

DY

DY

1K(64.10015.6D L)

267(64.26705.6 DL)

0.1u(78.10422. 5FL)

0.01u(78.10324 .L0L) 0.02 2u(78.22322.2F L)

DY

1.54K(64.15415 .6DL)

88.7K(64.88725 .6DL)

330p(78.33124. 2FL)

1000p(78.10224 .2FL)

5

PC4625

PC4626

PR4669

PR4635

PR4642

PC4630

PC4628

PC4653

PR4633

PR4608

PC4661

PC4662

0.022u(78.22321.2FL)DY

0.022u(78.22321.2FL)

DY

DY

316(64.31605.6 DL)

0.1u(78.10422. 5FL)

47n(78.47322.2 FL)

3.01K(64.30115 .6DL)

90.9K(64.90925 .6DL)

470p(78.47124. 2FL)

220p(78.22124. 2FL)

+VCCST_CPU

12

PR4603
1KR2F-L1-GP

DY

PR4607
100R2F-L3-GP

1 2

3D3V_S0

12

PR4609
10KR2F-L1-GP

DY

1

AFTP4601

VR_EN[40]

0517 Modify

P_SYS[44]

PR4614

1 2

DY

0R2J-L-GP

PWR_VCCGT_IMON
PWR_VCCGT_NTC
PWR_VCCGT_COMP
PWR_VCCGT_FB
PWR_VCCGT_RTN
PWR_VCCGT_ISUMP
PWR_VCCGT_ISUMNB
PWR_VCCGT_ISEN1
PWR_VCCGT_ISEN2

PC4625

PR4655

27K4R2F-GP

SCD022U25V2KX-DLGP

12

U42

12

PC4639

SC33P50V2JN-3GP

20170811
GT compensation

12

U42

20170810
GT compensation

12

PR4656

2K87R2F-1-GP

PWR_VCORE_COMP1

12

PC4640

SC4700P50V2KX-1DLGP

1KR2F-L1-GP

1 2

PC4626

SCD022U25V2KX-DLGP

12

12

20170810
New Common Part

PWR_VCORE_FB1

PR4657

PC4641

PU4601

1
2
3
4
5
6
7
8
9

10

41

2KR2F-L1-GP

20170810
GT load line

SC330P50V2KX-3-DL-GP

PSYS
IMON_B
NTC_B
COMP_B
FB_B
RTN_B
ISUMP_B
ISUMN_B
ISEN1_B
ISEN2_B

GND

12

PWR_VCORE_FB2

PR4660

VR_RDY

1K91R2F-1-GP

PR4606 45D3R2F-L-GP12PR4604 100R2F-L3-GP

PR4605 75R2F-2-GP

12

12

DY

PR4624 49D9R2F-L1-GP

PR4622 10R2F-L1-GP

PR4623 0R0402-PAD-1-GP

12

12

12

PWR_VCORE_VCC

PWR_VCORE_SCLK

PWR_VCORE_SDIO

PWR_VCORE_ALERT#

PWR_VCORE_VRHOT#

34

35

36

38

39

40

37

SDA

VCC

SCLK

ALERT#

VR_HOT#

VR_READY

VR_ENABLE

FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A16FB_A17RTN_A18ISUMP_A19ISUMN_A

PWR_VCORE_IMON

PWR_VCORE_COMP

PWR_VCORE_FB

PWR_VCORE_NTC

12

PR4658

499R2F-2-GP

PWR_VCORE_FB_RC

DY

12

PC4643

SC1KP50V2KX-L-1-GP

12

PC4602
SCD1U25V2KX-GP

VR_SVID_CLK [7]
VR_SVID_ALERT# [7]
VR_SVID_DATA [7]

DCBATOUT

PR4612

0R0402-PAD-1-GP

12

PC4606

SCD22U25V3KX-GP

12

12

PR4628

9K31R2F-GP

PWR_VCORE_PROG1

PWR_VCORE_PROG2

PWR_VCORE_VIN

32

33

VIN

PROG231PROG1

30

PWM_C

29

FCCM_C

ISUMN_C

ISUMP_C

COMP_C

IMON_C

FCCM_A

ISL95859AHRTZ-T-GP

20

074.95859.0B33

PWR_VCORE_RTN

PWR_VCORE_ISUMNA

PWR_VCORE_ISUMP

PC4632
SC2K2P50V2KX-L-GP

PR4659
100R2F-L3-GP

12

PC4642
SC1KP50V2KX-L-1-GP

PR4663
100R2F-L3-GP

PC4644 SCD01U50V2KX-L-GP

3

PWR_VCCSA_ISUMNB

28

PWR_VCCSA_ISUMP

27

PWR_VCCSA_RTN

26

RTN_C

PWR_VCCSA_FB

25

FB_C

PWR_VCCSA_COMP

24

PWR_VCCSA_IMON

23
22

PWM_A

21

20170810
GT OCP

1 2

PR4648 274R2F-GP

PWR_VCORE_ISUMN_RC

12

PC4637
SCD01U50V2KX-L-GP

1 2

1 2

DY

1 2

DY

1 2

DY

5V_S5

PR4610

1R2J-GP

12

PC4607

SC1U10V2KX-1GP

12

12

PR4629

88K7R2F-GP

PR4668
0R0402-PAD-1-GP

PR4667
0R0402-PAD-1-GP

PWR_VCCSA_PWM [50]
PWR_VCCSA_FCCM [50]

PWR_VCORE_PWM [47]
PWR_VCORE_FCCM# [47]

PR4651
1KR2F-L1-GP

1 2

12

12

+VCCGT

PC4634

SCD1U25V2KX-GP

12

VSSGT_SENSE [7]

VCCGT_SENSE [7]

12

PR4620
392R2F-GP

12

PC4631
SCD1U25V2KX-GP

PWR_VCORE_ISUMN_P_1

PC4652

12

DY

12

PR4615
1KR2F-L1-GP

DY

PWR_VCCSA_ISUMN_RC

PC4611

DY

SC2K2P50V2KX-L-GP

1 2

20170811
SA compensation

PR4632
1KR2F-3-GP

PR4649

0R0402-PAD-1-GP

1 2

SCD022U25V2KX-DLGP

12

20170810
GT RC time constant

2

PWR_VCCSA_FB_RC

12

PR4637
1K69R2F-2-GP

1 2

PR4638
2KR2F-L1-GP

DY

PR4640
2K49R2F-2-L-GP

1 2

20170811
SA compensation

1 2

PC4635

SCD022U25V2KX-DLGP

12

PC4605
SCD068U25V2KX-GP

PWR_VCCSA_FB1

12

PWR_VCCSA_COMP_RC

PC4624
SC33P50V2JN-3GP

1 2

PR4652

11KR2F-L-GP

DY

DY

PC4617
SC1KP50V2KX-L-1-GP

PWR_VCCSA_FB2

1 2

PC4629
SC330P50V2KX-3-DL-GP

PR4644

1 2

113KR2F-1-GP

PWR_VCORE_ISUMN [47]

12

PR4650
NTC-10K-29-GP-U

B=3370K
Place near Phase1 choke

PWR_VCORE_ISUMN_P_2

PR4653
2K61R2F-1-GP

1 2

PWR_VCORE_ISUMP [47]

12

PR4613
0R2J-L-GP

PWR_VCCSA_ISUMN_P_1

PC4608
SCD033U25V2KX-GP

1 2

PC4621
SC680P50V2KX-2GP

12

DY

PC4601
SC2200P50V2KX-2DLGP

1 2

20170811
SA compensation

12

20170810
New Common Part

12

PC4603
SCD1U25V2KX-GP

PWR_VCCSA_ISUMN [50]

12

PR4611
NTC-10K-29-GP-U

B=3370K
Place near Phase1 choke

PR4618
11KR2F-L-GP

PWR_VCCSA_ISUMN_P_2

1 2

PR4625
2K61R2F-1-GP

1 2

PC4613
SCD01U50V2KX-L-GP

1 2

1 2

PR4627

DY

100R2F-L3-GP

1 2

PR4602 0R0402-PAD-1-GP

12

PC4616

DY

SC1KP50V2KX-L-1-GP

1 2

PR4601 0R0402-PAD-1-GP

12

PC4620

DY

SCD01U50V2KX-L-GP

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

NCP81208MN_CPU_VCORE(1/3)

NCP81208MN_CPU_VCORE(1/3)

NCP81208MN_CPU_VCORE(1/3)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A2

A2

A2

Vegas SKL/KBL-R

Vegas SKL/KBL-R

Date: Sheet

Date: Sheet

Date: Sheet

Vegas SKL/KBL-R

PWR_VCCSA_ISUMP [50]

VSSSA_SENSE [7]

VCCSA_SENSE [7]

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

46 105Wednesday, November 08, 2017

46 105Wednesday, November 08, 2017

1

46 105Wednesday, November 08, 2017

of

of

of

A00

A00

A00

5

4

3

2

1

Main Func = CPU_CORE

DCBATOU T PW R_DCBATO UT_VCORE

PG4701

1 2

GAP-CLOS E-PWR-3-GP

D D

PWR_ VCORE_FCCM#[46]

C C

B B

PG4702

1 2

GAP-CLOS E-PWR-3-GP

PG4703

1 2

GAP-CLOS E-PWR-3-GP

PG4704

1 2

GAP-CLOS E-PWR-3-GP

PG4705

1 2

GAP-CLOS E-PWR-3-GP

PG4706

1 2

GAP-CLOS E-PWR-3-GP

5V_S5

PR4704
2D2R2F-G P

1 2

PR4706

1 2

0R0402-P AD

PC4708

SC1U10V2KX-1GP

12

PWR_ VCORE_VCC_R

PWR_ VCORE_SW

20170427

PWR_ DCBATOUT_VC ORE

PC4701

12

12

DY

SC10U25 V5KX-L-GP
SC10U25 V5KX-L-GP
SC10U25 V5KX-L-GP
SC10U25 V5KX-L-GP

PU4701

1
2
3
4

CSD9739 6Q4M-GP

074.97396.0043

PC4702

SKIP#
VDD
PGND
VSW

DY

PC4704

PC4703

12

12

PR4702

PWM

BOOT

BOOT_R

PGND

8
7
6
5

VIN

9

PWR_ VCORE_PW M_RPW R_VCORE_FCC M#_R
PWR_ VCORE_BOOT
PWR_ VCORE_BOOTR

PWR_ DCBATOUT_VC ORE

1 2

0R0402-P AD

12

PR4712
5K11R2F -L1-GP

PWR_ VCORE_PW M [4 6]

PWR_ VCORE_BOOT_ RC

12

PR4705
2D2R3F-L -GP

12

PC4707
SCD22U2 5V3KX-GP

SKL_U22_15W
Icc(max)=29A
TDC=21A

Confirm with EE
22uF/0805 total 33pcs
(78.22610.L2L)

+VCCGT

PT4701

12

SE330U2 VDM-4-GP

PANASONIC
ESR: 9 mohm

12

PR4703

DY

2D2R6J-3 -GP

PWR_ VCORE_SNB

12

DY

PC4706
SC1KP50 V2KX-L-1-GP

PWR_ VCORE_SW

PR4708

3K65R2F -1-GP

PL4701
COIL-D15UH -2-GP

1 2

PG4707
GAP-CLOS E-PWR-3-GP

1 2

12

68.R1510.20A

Cyntec. 6.8mm x6.4mmx4.0mm
DCR: 0.66m Ohm +/-7%
Idc : 26A , Isat : 52A

PG4708
GAP-CLOS E-PWR-3-GP

1 2

PWR_ VCORE_ISUMN_GPWR_ VCORE_ISUMP_G

12

PR4701
0R0402-P AD

PWR_ VCORE_ISUMP[4 6]

PWR_ VCORE_ISUMN[46]

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

NCP81382MN_CPU_VCORE(2/3)

NCP81382MN_CPU_VCORE(2/3)

NCP81382MN_CPU_VCORE(2/3)

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Vegas SKL/KBL-R

Vegas SKL/KBL-R

Vegas SKL/KBL-R

1

47 105Wednesd ay, November 08, 201 7

47 105Wednesd ay, November 08, 201 7

47 105Wednesd ay, November 08, 201 7

of

of

of

A00

A00

A00

Main Func = CPU_CORE

D D

C C

B B

A A

5

DCBATOUT PWR_DCBATOUT_VCCGTAPWR_DCBATOUT_VCCGTA

PG4802 GAP-CLOSE-PWR-3-GP

12

PG4803 GAP-CLOSE-PWR-3-GP

12

PG4804 GAP-CLOSE-PWR-3-GP

12

PG4805 GAP-CLOSE-PWR-3-GP

12

PG4806 GAP-CLOSE-PWR-3-GP

12

DCBATOUT PWR_DCBATOUT_VCCGTB

PG4810 GAP-CLOSE-PWR-3-GP

12

PG4816 GAP-CLOSE-PWR-3-GP

12

PG4811 GAP-CLOSE-PWR-3-GP

12

PG4812 GAP-CLOSE-PWR-3-GP

12

PG4814 GAP-CLOSE-PWR-3-GP

12

5

20170427

12

PWR_VCCGT_FCCM#[46,48]

PWR_DCBATOUT_VCCGTB

12

PC4816

U42

PWR_VCCGT_FCCM#[46,48]

PC4802

PC4803

12

DY

SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP

5V_S5

12

PR4803
2D2R2F-GP

PC4809

SC1U10V2KX-1GP

12

12

PC4817

SC10U25V5KX-L-GP

U42

1 2

SC10U25V5KX-L-GP

5V_S5

U42

PR4812

U42

U42

PC4804

12

PR4806

1 2

0R0402-PAD

12

PC4814

12

PR4813

PC4812

12

12

DY

SC10U25V5KX-L-GP

0R0402-PAD

2D2R2F-GP

SC1U10V2KX-1GP

PC4805

PWR_VCCGT_FCCM#_RA
PWR_VCCGT_VCCDA

PWR_VCCGT_SWA

12

PC4815

SC10U25V5KX-L-GP

U42

PWR_VCCGT_FCCM#_RB
PWR_VCCGT_VCCDB

PWR_VCCGT_SWB

4

PR4802

1 2

0R0402-PAD

PWR_VCCGT_BOOTA_RC

12

12

PR4817

5K11R2F-L1-GP

PU4801

SKIP#1PWM

2

VDD

3
4

2
3
4

4

BOOT

PGND

BOOT_R

VSW

PGND

CSD97396Q4M-GP

074.97396.0043

PU4802

SKIP#1PWM
VDD

BOOT

PGND

BOOT_R

U42

VSW

PGND

CSD97396Q4M-GP

074.97396.0043

VIN

VIN

PWR_VCCGT_PWMA_RA

8

PWR_VCCGT_BOOTA

7

PWR_VCCGT_BOOTRA

6
5

9

8

PWR_VCCGT_PWMB_RA

PWR_VCCGT_BOOTB

7

PWR_VCCGT_BOOTRB

6
5

9

PWR_DCBATOUT_VCCGTA

PR4811

1 2

0R0402-PAD

12

PR4818
5K11R2F-L1-GP

U42

PWR_DCBATOUT_VCCGTB

3

PWR_VCCGT_PWMA [46]

PR4804

2D2R3F-L-GP

12

PWR_VCCGT_ISEN1[46,48]

PWR_VCCGT_ISUMP[46,48]

PWR_VCCGT_ISUMN[ 46,48]

PWR_VCCGT_PWMB [46]

PWR_VCCGT_BOOTB_RC

12

PR4810
2D2R3F-L-GP

U42

PWR_VCCGT_ISEN2[46,48]

PWR_VCCGT_ISUMP[46,48]

PWR_VCCGT_ISUMN[ 46,48]

3

PC4808
SCD22U25V3KX-GP

12

PC4811

U42

SCD22U25V3KX-GP

12

PR4805

DY

2D2R6J-3-GP

PWR_VCCGT_SNB1

12

PC4810

DY

SC1KP50V2KX-L-1-GP

1 2

PR4821

U42

100KR2F-L3-GP

1 2

PR4808
3K65R2F-1-GP

12

PR4814

DY

2D2R6J-3-GP

PWR_VCCGT_SNB2

12

PC4813

DY

SC1KP50V2KX-L-1-GP

1 2

PR4823

U42

100KR2F-L3-GP

1 2

PR4816

U42

3K65R2F-1-GP

Cyntec. 6.8mm x6.4mmx4.0mm
DCR: 0.66m Ohm +/-7%
Idc : 26A , Isat : 52A

PL4801
COIL-D15UH-2-GP

1 2

68.R1510.20A

12

PG4808
GAP-CLOSE-PWR-3-GP

PWR_VCCGT_ISEN2[46,48]

Cyntec. 6.8mm x6.4mmx4.0mm
DCR: 0.66m Ohm +/-7%
Idc : 26A , Isat : 52A

PL4802
COIL-D15UH-2-GP

1 2

U42

12

PG4813
GAP-CLOSE-PWR-3-GP

PWR_VCCGT_ISUMP_GB

PWR_VCCGT_ISEN1[46,48]

2

SKL_U22_15W
Icc(max)=31A
TDC=18A

Confirm with EE
22uF/0805 total 36pcs
(78.22610.L2L)

12

PG4809
GAP-CLOSE-PWR-3-GP

PWR_VCCGT_ISUMN_GAPWR_VCCGT_ISUMP_GA

12

PR4809
10R2F-L1-GP

12

PG4815
GAP-CLOSE-PWR-3-GP

PWR_VCCGT_ISUMN_GB

12

PR4815

U42

10R2F-L1-GP

2

12

PR4822

DY

100KR2F-L3-GP

12

DY

VCC_CORE

PR4824
100KR2F-L3-GP

DCBATOUT

For acoustic noice

12

PT4801
SE330U2VDM-4-GP

PANASONIC
ESR: 9 mohm

VCC_CORE

U42

12

PT4803
SE330U2VDM-4-GP

1

12

PT4805
ST100U25VDM-1-GP

12

PT4806
SE33U25VM-11-GP

0920 Change acoustic solution
1101 Change acoustic solution

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

NCP81382MN_CPU_VCCGT(3/3)

NCP81382MN_CPU_VCCGT(3/3)

NCP81382MN_CPU_VCCGT(3/3)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A2

A2

A2

Vegas SKL/KBL-R

Vegas SKL/KBL-R

Vegas SKL/KBL-R

Date: Sheet

Date: Sheet

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

1

48 105Wednesday, November 08, 2017

48 105Wednesday, November 08, 2017

48 105Wednesday, November 08, 2017

A00

A00

A00

of

of

of

5

Main Func = CPU_CORE

20170427

4

3

2

1

PG5002

D D

GAP-CLOS E-PWR-3-GP

PG5003
GAP-CLOS E-PWR-3-GP

PWR_ DCBATOUT_VC CSADCBATOU T

12

12

PWR_ DCBATOUT_VC CSA

SKL_U22_15W
Icc(max)=4.5A
TDC=3.7A

12

PC5002

SC10U25V5KX-L-GP

DY

678

PU5002

DDD

AON7410 -GP

C C

PWR_ VCCSA_PW M[46]

12

PR5001
2D2R3F-L -GP

PWR_ VCCSA_DRVH
PWR_ VCCSA_BST

PWR_ VCCSA_BST_R C

PU5001

1

UGATE

2

BOOT

3

PWM

4

GND

ISL95808H RZ-T-1-GP

PHASE

FCCM

VCC

LGATE

GND

8
7
6
5

9

074.95808.0B73

If no need support PS4 mode
please change to ISL6208C

12

PC5005

SCD22U2 5V3KX-GP

5V_S5

12

PC5001
SC2D2U1 0V3KX-L-GP

PWR_ VCCSA_SW

PWR_ VCCSA_FCCM [46]

PWR_ VCCSA_DRVL

SSS

GD

123

4 5

678

PU5003

DDD

AON7410 -GP

SSS

GD

123

4 5

12

PC5003

SC10U25V5KX-L-GP

12

PC5004

SCD1U25V2KX-GP

Confirm with EE
22uF/0805 total 6pcs
(78.22610.L2L)

Cyntec. 7.3mm x6.8mm x3.0mm
DCR: 4.0~4.2 mohm
Idc : 17.5A , Isat : 26A

PL5001

1 2

IND-D47UH-22 -GP-U

PG5011
GAP-CLOS E-PWR-3-GP

1 2

PWR_VCCSA_ISUMP_R

+VCCSA

PG5001
GAP-CLOS E-PWR-3-GP

1 2

PWR_VCCSA_ISUMN_R

74.06208.B73

B B

12

PR5003
3K65R2F -1-GP

PWR_ VCCSA_ISUMP[46]

PWR_ VCCSA_ISUMN[46]

A A

5

4

3

2

12

PR5004
0R0402-P AD

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

NCP81253MN_CPU_VCCSA

NCP81253MN_CPU_VCCSA

NCP81253MN_CPU_VCCSA

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Vegas SKL/KBL-R

Vegas SKL/KBL-R

Vegas SKL/KBL-R

50 105Wednesd ay, November 08, 201 7

50 105Wednesd ay, November 08, 201 7

50 105Wednesd ay, November 08, 201 7

of

of

1

of

A00

A00

A00

5

SSID = PWR.Plane.Regulator_1p2v& 2D5V

4

3

2

1

13

PGOOD

TON

S5

S3

VLDOIN

VTTGND

VTT

VTTSNS

GND

21

CS

GND

3

PWR_VDDQ_VID

11

VID

VID
Logic-High = 0.75V
Logic-Low = 0.6V

12

PWR_VDDQ_VDDPWR_VDDQ_CS

12

PU5101
RT8231AGQW-GP

12

074.08231.0073

VDD

18

BOOT

17

UGATE

16

PHASE

15

LGATE

14

PGND

5

VDDQ

6

FB

VTTREF

4

PWR_VDDQ_VTTREF

12

PC5116

PR5107
5D1R2F-GP

1 2

PC5102
SC1U10V2KX-1GP

PR5109

0R0402-PAD-1-GP

1 2

PC5107
SC1U10V2KX-1GP

PWR_VDDQ_BOOT PWR_VDDQ_BOOT_A

PWR_VDDQ_HG

PWR_VDDQ_PH

PWR_VDDQ_LG

PWR_VDDQ_VDDQ

PWR_VDDQ_FB

5V_S5

5V_S5

PR5112
2D2R3F-L-GP

1 2

DY

R1

12

12

PC5115

PR5116

SC18P50V2JN-1-GP

15K8R2F-GP

R2

12

PR5117
20KR2F-L3-GP

Vout Setting
Vout = Vref * ( 1 + R1/R2 )
= 0.675 * ( 1 + 12.1K / 20K)
= 1.2V

PC5108
SCD1U50V3KX-GP

1 2

Close to output cap pin1, not
inside of the output cap

PG5101
GAP-CLOSE-PWR-3-GP

1 2

PWR_1D2V

PWR_DCBATOUT_VDDQ

12

12

PC5103

DY

678

DDD

PU5102

AON7410-GP

84.07410.A37

PR5116 from 12.1Kohm change to 15.8Kohm(64.15825.6DL) to setting VDDQ =1.2V
Due to pin 11 VID is pull high, Vref. should be 0.675V
by power team Edward 1/30

PU5105

AON7506-GP

84.07506.037

65 BOM

65 BOM

4

SSS

GD

123

4 5

567

DDD

G

DY

8

D

SSS

DY

123

12

PC5104

PC5105

SC4D7U25V5KX-L2-GP

SC4D7U25V5KX-L2-GP

DCR=5~5.5mohm
IDC=15.5A, Isat=25A

PL5101
COIL-D68UH-5-GP-U

1 2

12

PR5120
2D2R5F-2-GP

PWR_VDDQ_SNUB

12

PC5120
SC2200P50V2KX-2GP

SCD1U25V2KX-GP

Design Current=6.9A

10.4A<OCP>13.8A

PC5110

12

PC5112

PC5111

12

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

PWR_1D2V

PC5113

12

DY

20170810
New Common Part

PC5114

12

PG5119
GAP-CLOSE-PWR-3-GP

1 2

PG5120
GAP-CLOSE-PWR-3-GP

1 2

PG5121
GAP-CLOSE-PWR-3-GP

1 2

PG5122
GAP-CLOSE-PWR-3-GP

1 2

PG5123
GAP-CLOSE-PWR-3-GP

1 2

PG5124
GAP-CLOSE-PWR-3-GP

1 2

PG5127
GAP-CLOSE-PWR-3-GP

1 2

PG5125
GAP-CLOSE-PWR-3-GP

1 2

PG5126
GAP-CLOSE-PWR-3-GP

1 2

PG5128
GAP-CLOSE-PWR-3-GP

1 2

PG5129
GAP-CLOSE-PWR-3-GP

1 2

PG5130
GAP-CLOSE-PWR-3-GP

1 2

1D2V_S3PWR_1D2V

DCBATOUT

D D

C C

PWR_DCBATOUT_VDDQ

PG5117
GAP-CLOSE-PWR-3-GP

1 2

PG5118
GAP-CLOSE-PWR-3-GP

1 2

Freq. setting
750K -> 350K Hz

1D2V_S3

1 2

PR5128 0R0402-PAD

PWR_VDDQ_PG[4 0]

DY

12

PC5106
SCD1U16V2KX-3GP

3D3V_S5

12

PR5111
10KR2F-L1-GP

DY

PWR_DCBATOUT_VDDQ

PG5115
GAP-CLOSE-PWR-3-GP

1 2

PG5116
GAP-CLOSE-PWR-3-GP

1 2

PWR_VDDQ_EN2D5V_PWROK

PR5113
750KR2F-L-GP

1 2

12

PC5109
SC10U6D3V3MX-GP

PWR_VDDQ_VTT

0620 Change Res value
by PWR team Jerry

OCP setting

12

PWR_VDDQ_PG

PWR_VDDQ_TON

PWR_VDDQ_EN

PWR_VTT_EN

PWR_VDDQ_VLDOIN

PR5114
255KR2F-GP

10

9

8

7

19

1

20

2

S5

1 2

SIO_SLP_S3#[17,24,27,40]

SM_PGCNTL_R[5]

PR5126 0R2J-2-GP

DY

1 2

PR5127 0R0402-PAD

PWR_VTT_EN

S3

VID vs Vref Table
VID Logic-High => Vref = 0.675 V
VID Logic-Low => Vref = 0.75 V

Vout = 0.6V

B B

PWR_VDDQ_VTT

DY

GAP-CLOSE-PWR-3-GP

PC5118

SC10U6D3V3MX-GP

PC5117

SC10U6D3V3MX-GP

12

GAP-CLOSE-PWR-3-GP

12

PG5113

PG5114

12

12

Iomax = 1.2A

0D6V_S0

note. Vref can only be changed form

0.675v to 0.75v after power-on

APL5930 for VPP_2D5V

5V_S5 3D3V_S5

3D3V_S5

12

SC1U50V3KX-GP

PR5155

EE needs check sequence control

SIO_SLP_S4#[17,40,44]

A A

5

10KR2F-L1-GP

1 2

PR5158 0R0402-PAD

1

PR5153 0R0402-PAD

2

4

PR5152

47KR2J-2-GP

PC5156

PWR_2D5V_POK2D5V_PWROK
PWR_2D5V_EN

12

DY

12

12

DY

PC5155

SC4700P50V2KX-1GP

6
7
8
9

2ND = 74.G9731.03D

SCD047U25V2KX-GP

PU5151

VIN#5

VOUT#4

VCNTL

VOUT#3

POK
EN

GND

VIN#9

APL5930KAI-TRG-GP

74.05930.03D

FB

PC5152

SC10U6D3V3MX-GP

12

5
4
3
2
1

12

PR5151

PWR_2D5V_FB

12

PR5154
20KR2F-L3-GP

3

Design Current = 700mA

2D5V_PWR

PC5154

SC22U6D3V3MX-1-DL-GP

PC5153

SC68P50V2JN-1GP

12

20170810
New Common Part

43K2R2F-L-GP

12

DY

Vout=0.8V*(R1+R2)/R2

1 2

PG5151 GAP-CLOSE-PWR

1 2

PG5152 GAP-CLOSE-PWR

2

2D5V_S32D5V_PWR

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

RT8231_VDDQ/VTT

RT8231_VDDQ/VTT

RT8231_VDDQ/VTT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A2

A2

A2

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Date: Sheet

Date: Sheet

Date: Sheet

Vegas SKL/KBL-U

Taipei Hsien 221, Taiwan, R.O.C.

1

A00

A00

A00

of

of

of

51 105Wednesday, November 08, 2017

51 105Wednesday, November 08, 2017

51 105Wednesday, November 08, 2017

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p0v

D D

DCBATOU T

GAP-CLOS E-PWR-3-GP

GAP-CLOS E-PWR-3-GP

GAP-CLOS E-PWR-3-GP

C C

PWR_ DCBATOUT_1D 0V

PC5308

SCD1U25V2KX-GP

12

B B

PG5301

1 2

PG5302

1 2

PG5303

1 2

PC5309

12

PWR_ DCBATOUT_1D 0V

SC10U25V5KX-L-GP

PC5310

SC10U25V5KX-L-GP

12

100KR2F -L3-GP

PR5303

PR5301
95K3R2F -GP

1 2

12

1D0V_S5 _PWRGD[40]

3V_5V_P OK[17,21,40,4 5,54]

5V_S5

PC5302

SC4D7U25V5KX-L2-GP

12

PWR_ 1D0V_TON

PWR_ 1D0V_PG

PWR_ 1D0V_EN

PWR_ 1D0V_PFM

PWR_ 1D0V_SS

12

PC5313
SCD01U5 0V2KX-L-GP

PU5301

21

VCC

7

IN#7

8

IN#8

9

IN#9

6

TON

1

PGOOD

2

EN

3

PFM#

22

SS

AOZ2262 QI-10-GP-U

1 2

PR5305
0R0402-P AD

1 2

PR5306
0R0402-P AD

LX#18
LX#17
LX#16
LX#11
LX#10

AGND

PGND
PGND
PGND
PGND
PGND

074.02262.0043

5V_S5

12

PR5308

DY

100KR2J -1-GP

12

PC5314
SC1KP50 V2KX-L-1-GP

AOZ2262 for 1D0V

DCR=5~5.5mohm
IDC=15.5A, Isat=25A

PL5301

18
17
16
11
10

20

BST

5

FB

4

19
14
13
12
15

PWR_ 1D0V_PG

PWR_ 1D0V_EN

PWR_ 1D0V_PH

PWR_ 1D0V_BT

PWR_ 1D0V_VFB

12

PC5304
SCD1U25 V2KX-GP

COIL-1UH-34-G P-U1

1 2

68.1R01A.20B

12

PR5309

DY

2D2R5F-2 -GP

PWR_ 1D0V_SNUB

12

PC5315

DY

SC2200P 50V2KX-2GP

Vo=0.8x(1+R1/R2)
=0.8x(1+7.5/30)
=1.00

1 2

PWR_ 1D0V_VFB_A

12

R1

12

R2

PG5310
GAP-CLOS E-PWR-3-GP

PC5312

PR5302

PR5304

SC220P50V2KX-3GP

2K55R2F-GP

12

DY

10KR2F-L1-GP

design current : 8.92A

PC5301

12

SC22U6D 3V3MX-1-DL-GP
SC22U6D 3V3MX-1-DL-GP
SC22U6D 3V3MX-1-DL-GP
SC22U6D 3V3MX-1-DL-GP
SC22U6D 3V3MX-1-DL-GP

PC5305

PC5303

12

12

PWR_ 1D0V

PC5307

12

12

DY

20170810
New Common Part

PWR_ 1D0V 1D0V_S5

PC5306

PG5304

GAP-CLOS E-PWR-3-GP

1 2

PG5305

GAP-CLOS E-PWR-3-GP

1 2

PG5306

GAP-CLOS E-PWR-3-GP

1 2

PG5307

GAP-CLOS E-PWR-3-GP

1 2

PG5308

GAP-CLOS E-PWR-3-GP

1 2

PG5309

GAP-CLOS E-PWR-3-GP

1 2

PG5311

GAP-CLOS E-PWR-3-GP

1

2

PG5312

GAP-CLOS E-PWR-3-GP

1 2

PG5313

GAP-CLOS E-PWR-3-GP

1 2

PG5314

GAP-CLOS E-PWR-3-GP

1 2

A A

5

4

3

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

AOZ2262QI_1D0V

AOZ2262QI_1D0V

AOZ2262QI_1D0V

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

53 105Wednesd ay, November 08, 201 7

53 105Wednesd ay, November 08, 201 7

53 105Wednesd ay, November 08, 201 7

1

A00

A00

of

of

of

A00

5

4

3

2

1

Main Func = 1D8V

D D

APL5930 for 1D8V_S5

PG5405

1 2

GAP-CLOSE-PWR

PG5406

1 2

GAP-CLOSE-PWR

PG5407

5V_S5 3D3V_S5

C C

PH at Page40

0511 Follow KY15.

PRIM_PWRGD[24,40]

3V_5V_POK[17,21,40,45,53]

1 2

PR5408 0R0402-PAD

1 2

PR5406

0R0402-PAD

[#544669 Rev0.53]

B B

3D3V_S5

12

DY

PR5402

100KR2F-L3-GP

12

PWR_1D8V_POK
PWR_1D8V_EN

PR5401

47KR2J-2-GP

12

DY

PC5401

SC1U10V2KX-1GP

12

DY

PC5403

SC10U6D3V3MX-GP

12

PU5401

5

VIN#5

FB

GND

4
3
2
1

1.8V_RUN_FB

6

VCNTL

7

POK

8

EN

9

PC5406

SC4700P50V2KX-1GP

VIN#9

APL5930KAI-TRG-GP

VOUT#4
VOUT#3

12

1D8V_PWR

PR5403

16K5R2F-2-GP

DY

12

74.05930.03D

2ND = 74.G9731.03D

12

PR5404
13KR2F-GP

1 2

GAP-CLOSE-PWR

Design Current = 1.1A

PC5405

SC68P50V2JN-1GP

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

1D8V_S51D8V_PWR

PC5402

PC5404

DY

12

20170810
New Common Part

Vout=0.8V*(R1+R2)/R2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A A

Title

Title

Title

LDO-V1D5V&V1D8V

LDO-V1D5V&V1D8V

LDO-V1D5V&V1D8V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet

Date: Sheet

Date: Sheet of

5

4

3

2

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

54 105Wednesday, November 08, 2017

54 105Wednesday, November 08, 2017

54 105Wednesday, November 08, 2017

of

of

1

A00

A00

A00

Main Func = LCD Main Func = CAMERA

LCD1

43

41

1

2
3
4

44

IPEX-CON4 0-3-GP

20.F2406.040

2nd = 20 .F1407.040

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

42

D D

C C

B B

A A

5

DCBATOUT_LCD

Trace width = 80mil

DBC_EN_R
EDP_HPD_ CONN
LCD_TST_C
eDP_AUX_CO N_P
eDP_AUX_CO N_N

eDP_TX_CON_ N0
eDP_TX_CON_ P0

eDP_TX_CON_ N1
eDP_TX_CON_ P1

LCD_BRIGH TNESS
BLON_OUT_C
PANEL_S IZE_ID_CONN

DMIC_CLK_ EDP
DMIC_DATA_E DP

USB_CAME RA_PN4
USB_CAME RA_PP4

CAMERA_DE T#_R
USB_CON_ PN7
USB_CON_ PP7

TP_RS
TP_RESET

TPAN_VDD

LCD_BRIGHTNESS

12

EC5504

DY

SC22P50 V2JN-4GP

LCDVDD

EDP_VDD_ EN[8]

LCD_VCC_TES T_EN[24]

5

C5538

SC10U6D3V3MX-GP

12

MIC_GND

3D3V_CAM ERA_S0

eDP_TX_CPU_ N0[8]
eDP_TX_CPU_ P0[8 ]

eDP_TX_CPU_ N1[8]

eDP_TX_CPU_ P1[8 ]

eDP_AUX_CP U_N[8]

eDP_AUX_CP U_P[8]

Brightness

LCDVDD_LCD

C5536

SC1U10V2KX-1GP

12

Layout Note:
Colse to LCD1.

1 2

MIC_GND

L_BKLT_CTRL[8]

D5502

1

3

2

BAT54C-12-G P

75.00054.A7D

Layout Note:

Trace width = 80mil

LCDVDD_LCD

EE note: Never change R5211 to short pad after MP

DBC_EN_R

CAMERA_DE T#_R

LCD

PU/PD FOR AUX CHANNEL

SKL PDG (#543016):
Recommends having a pull-up resistor of 100 kΩ for AUXN
and a pull-down resistor of 100 kΩ for AUXP

Camera

Touch Panel

R5531

0R0402-P AD

C5508 SCD1U16V2 KX-3GP
C5532 SCD1U16V2 KX-3GP

C5534 SCD1U16V2 KX-3GP
C5537 SCD1U16V2 KX-3GP

C5533 SCD1U16V2 KX-3GP
C5531 SCD1U16V2 KX-3GP

R5530 0R04 02-PAD

12

R5506
100KR2J-1 -GP

LCDVDD

between the AC capacitor and the connector,
to assist source detection by the sink device.

1 2
1 2

1 2
1 2

1 2
1 2

1 2

LCDVDD_EN

C5506

SC22U6D3V3MX-1-GP

12

4

LCDVDD

R5523

1 2

0R5J-5-GP

1 2

R5518
100R2J-L-G P

1 2

R5501
0R0402-P AD-2-GP

add for camera detect pin 1/25

eDP_AUX_CO N_P

eDP_AUX_CO N_N

LCD_TST_C
LCD_BRIGH TNESS

BLON_OUT_C
EDP_HPD_ CONN

eDP_TX_CON_ N0
eDP_TX_CON_ P0

eDP_TX_CON_ N1
eDP_TX_CON_ P1

eDP_AUX_CO N_N
eDP_AUX_CO N_P

eDP_BKLT_CTRL

U5501

1

EN

2

GND

3

VOUT

RT9724GB-G P

VIN#5

VIN#4

5

4

74.09724.09F

4

DBC_PANE L_EN [20 ]

CAMERA_DE T# [20 ]

R5528 100 KR2J-1-GP

R5529 100 KR2J-1-GP

RN5502

1
2
3
4 5

SRN100KJ -5-GP

RN5501

SRN100J-3 -GP

1
2 3

1
2 3

RN5503
SRN100J-3 -GP

3D3V_S0

C5505

SC4D7U6D3V3KX-GP

12

INVERTER POWER

PANEL_S IZE_ID_CONN

1 2

DY

1 2

DY

BKLT_CTRL

8

BLON_OUT_C

7

EDP_HPD

6

4

BKLT_CTRL

4

12

DY

For ESD

1 2

R5525

DY

100R2J-L-G P

3D3V_S0

LCD_TST_R [2 4]

BLON_OUT [2 4] EC_BRIGHTNES S [24]
EDP_HPD [8]

5V_S03D3 V_S0

12

R5522

0R3J-L1-GP

R5527
0R0603-P AD-2-GP-U

69.50007.A31

1 2

TPAN_VDD_F

EE note: Never change R5232 to short pad after MP
Reserved for one time fuse: 69.43001.201

F5502 POLYSW-1 D1A24V-GP-U

1 2

R5520 0R0 603-PAD-2-GP -U

F5503

1 2

POLYSW -1D1A24V-GP -U

69.50007.A31

0517 Change PH power rate

1D8V_S5

12

R5521
10KR2J-L-G P

For AUDIO Grade B or C selection.

12

R5526

DY

0R2J-2-GP

1 2

R5524 0R2 J-2-GP

DY

D5503

1

3

2

BAT54C-12-G P

75.00054.A7D

DY

3

800mA

PANEL_S IZE_ID

eDP_BKLT_CTRL

EC (BIST MODE)

TPAN_VDD

C5543

SC2D2U10V3KX-L-GP

12

DY

3

DCBATOUT_LCDDCBA TOUT

C5535

SCD1U50V3KX-GP

12

DY

PANEL_S IZE_ID [2 0]

2

EE note: Never change R5229 to short pad after MP

C5515

SC1KP50V2KX-L-1-GP

12

Reserved for one time fuse: 69.43001.201

1 2

DY

EL5507

1 2

DY

3D3V_CAM ERA_S03D3V_S0

EC5503

SC33P50V2JN-3GP

C5539

SC4D7U6D3V3KX-GP

12

12

DY

EC5501

SC22P50V2JN-4GP

12

DY

USB_CAME RA_PN4

USB_CAME RA_PP4

DMIC_DATA_E DP
DMIC_CLK_ EDP

1 2

R5532
0R5J-5-GP

R5533
0R2J-L-GP

1 2

4 3

COIL-90OH M-100MHZ-5-GP

68.00396.001

R5534
0R2J-L-GP

1 2

R5502 100 R2J-L-GP

1 2

R5503 100 R2J-L-GP

USB_CPU_ PN4 [16]

USB_CPU_ PP4 [16]

DMIC_DATA [27]
DMIC_CLK [27]

EC5502

SC22P50V2JN-4GP

12

1

Main Func = Touch panel

Touch Panel

TP_RS

12

C5541

DY

SC10P50 V2JN-L1-GP

TP_RESET

12

C5540

DY

SC10P50 V2JN-L1-GP

1 2

R5537
0R0402-P AD-2-GP

1 2

R5538
0R0402-P AD-2-GP

USB_CON_PN7

USB_CON_ PP7

2

TOUCH_PANE L_INTR# [4,24]

PLT_RST# [17,31,6 1,63,76,91 ]

1 2

R5535 0R0 402-PAD-2-GP

1 2

R5536 0R0 402-PAD-2-GP

USB_CON_PN7

USB_CPU_ PN7 [16]

USB_CPU_ PP7 [16]

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

Date: Sh eet of

Date: Sh eet of

Date: Sh eet

ED5501

1

I/O1

I/O4

2

DY

GND

VDD

I/O23I/O3

AZC099-04 S-2-GP

075.09904.0A7C

LCD&CAM&DMC&Touch

LCD&CAM&DMC&Touch

LCD&CAM&DMC&Touch

Custom

Custom

Custom

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

USB_CON_ PP7

6

5

4

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih ,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih ,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih ,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

12

C5501

DY

SCD1U16V 2KX-3GP

55 1 05Wednesday, N ovember 08, 2017

55 1 05Wednesday, N ovember 08, 2017

55 1 05Wednesday, N ovember 08, 2017

TPAN_VDD

of

A00

A00

A00

5

Main Func = CRT

C5623

SCD01U16V2KX-3GP

D D

C C

DP_CRT_B

5V_CRT_S0_R

1 2

DY

CRT_DDCDATA_CON
CRT_DDCCLK_CON

CRT_R
CRT_G
CRT_B

CRT_VSYNC_CON
CRT_HSYNC_CON

12

12

R5608

R5607

CRT Connector

VGA1

9

VCC_CRT

12

DDCDATA_ID1

15

DDCCLK_ID3

1
2
3

14
13

12

R5606

CRT_RED
CRT_GREEN
CRT_BLUE

VSYNC
HSYNC

D-SUB-15-297-GP

020.20067.0015

2nd = 20.20975.015

12

Vegas

C5612

12

C5611

12

4

NC#4

11

NC#11

5

GND

6

GND

7

GND

8

GND

10

GND

16

GND

17

GND

EL5601

1 2

Vegas

BLM18BB470SN1D-GP

1 2

EL5603

Vegas

BLM18BB470SN1D-GP

1 2

EL5602

Vegas

BLM18BB470SN1D-GP

C5613

4

D5604

Vegas

RB551V30-GP

5V_CRT_S0_R5V_HDMI_S0

KA

83.R5003.H8H

CRT_DDCDATA_CON

CRT_DDCCLK_CON

CRT_DDCCLK_CON_R CRT_DDCCLK_CON

CRT_PCH_HPD

CRT_RDP_CRT_R

CRT_GDP_CRT_G

CRT_B

C5619

12

12

C5618

C5614

12

1 2

R5602 0R0402-PAD
R5603 0R0402-PAD1 2

1 2

R5612 47R2J-2-GP

Vegas

R5611 47R2J-2-GP

1 2

Vegas

R5605 0R0402-PAD1 2

12

DY

SRN2K2J-1-GP

C5617

12

DY

3

C5616

RN5601

5V_CRT_S0_R

4

Vegas

1

2 3

CRT_DDCDATA_CONCRT_DDCDATA_CON_R

CRT_HSYNC_CONDP_CRT_HSYNC_CON
CRT_VSYNC_CONDP_CRT_VSYNC_CON

C5622

12

DY

DY

CPU_DP2_HPD [ 8]

CRT_HSYNC_CON
CRT_VSYNC_CON
CRT_DDCDATA_CON
CRT_DDCCLK_CON

C5607

12

2

For EMI R2 SPEC Reserved

CRT_G

12

DY

ED5603

AZ5725-01FDR7G-GP

83.05725.0A0

R5609
0R0603-PAD-2-GP-U

83.05725.0A0

1 2

DY

CRT_R

12

ED5602

Vegas

CRT_B

12

DY

AZ5725-01FDR7G-GP

83.05725.0A0

VDD_DAC_333D3V_S0

12

C5615
SC10U6D3V3MX-GP

ED5601

AZ5725-01FDR7G-GP

1

Vegas

PCH_SMBCLK[12,13,18,65,67]
PCH_SMBDATA[12,13,18,65,67]

Vegas

RN5603

RN5602

1
2 3

2 3
1

SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP

Vegas

Vegas
Vegas
Vegas

Vegas

Vegas
Vegas
Vegas

DY

Vegas

SRN4K7J-8-GP
SRN4K7J-8-GP

Vegas

Vegas

75R2F-2-GP
75R2F-2-GP

Layout note:
R5607, R5608, R5606 need to close U5601
Trace length not over 300 mil

3D3V_S0

B B

75R2F-2-GP

12

R5613

4K7R2J-2-GP

DY

SPI_CLK_CRT

3D3V_S0

A A

3D3V_S0

5

Vegas

Vegas

Layout note:
C5611 & C5612 & C5613 & C5614 & C5618 & C5619 & L5601 & L5602 & L5603
need to close connect

VCCK_12

12

C5620SCD1U16V2KX-3GP

VCCK_12

12

C5609SCD1U16V2KX-3GP
C5608SC2D2U10V3KX-L-GP

12
12

AVCC33

C5606SCD1U16V2KX-3GP

3D3V_S0

C5626SCD1U16V2KX-3GP

12

VDD_DAC_33

C5627SCD1U16V2KX-3GP

12
12

C5628SC10U6D3V3MX-GP

3D3V_S0 DP_CRT_VSYNC_CON

12

C5610SCD1U16V2KX-3GP

CRT_DDCCLK_CON_R
CRT_DDCDATA_CON_R

SPI_CLK_CRT
SPI_SI_CRT

4

SPI_SO_CRT

POL1/SPI_CEB

4

POL2

Vegas

SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP

U5601

4

AVCC_12

25

VCCK_12

1

AVCC_33

14

VCC_33

20

VDD_DAC_33

26

PVCC_33

15

VGA_SCL

16

VGA_SDA

30

SMB_SCL

29

SMB_SDA

11

GPI1/SPI_CLK

12

GPI2/SPI_SI

13

GPI3/SPI_SO

10

POL1/SPI_CEB

9

POL2

RTD2166-CGT-GP

071.02166.0003

4

Vegas

Vegas

Vegas

LANE0_P
LANE0_N
LANE1_P
LANE1_N

HVSYNC_PWR

BLUE_P

GREEN_P

LDO_RSTB

EXT_CLK_IN

EXT1.2V_CTRL

AUX_P

AUX_N

HSYNC
VSYNC

RED_P

HPD

GND
GND

SC18P50V2JN-1-GP
SC18P50V2JN-1-GP

PCH_DPC_AUXP_U

2

PCH_DPC_AUXN_U

3

PCH_DPC_P0_U

5

PCH_DPC_N0_U

6

PCH_DPC_P1_U

7

PCH_DPC_N1_U

8

17

DP_CRT_HSYNC_CON

19
18

DP_CRT_B

21

DP_CRT_G

22

DP_CRT_R

23

27

EXT_CLK_IN_CRT

28
31

CRT_PCH_HPD

32

24
33

5V_CRT_S0_R
CRT_VSYNC_CON
CRT_HSYNC_CON
CRT_DDCDATA_CON
CRT_DDCCLK_CON
CRT_R
CRT_G
CRT_B

3

SC100P50V2JN-3GP
SC100P50V2JN-3GP

1

AFTP5604 AFTE14P-GP

1

AFTP5602 AFTE14P-GP

1

AFTP5603 AFTE14P-GP

1

AFTP5609 AFTE14P-GP

1

AFTP5608 AFTE14P-GP

1

AFTP5605 AFTE14P-GP

1

AFTP5607 AFTE14P-GP

1

AFTP5606 AFTE14P-GP

12

C5624SCD1U16V2KX-3GP

Vegas

C5625SCD1U16V2KX-3GP

12

Vegas

C5601SCD1U16V2KX-3GP

12

Vegas

12

C5605SCD1U16V2KX-3GP

Vegas

12

C5603SCD1U16V2KX-3GP

Vegas

C5604SCD1U16V2KX-3GP

12

Vegas

5V_S0

0523 Follow vendor suggest.

12

R5616

4K7R2J-2-GP

DY

3D3V_S0 AVCC33

R5610

1 2

0R0603-PAD-2-GP-U

Vegas

5V_S0

PCH_DPC_AUXP [8]

PCH_DPC_AUXN [8]

PCH_DPC_P0 [8]

PCH_DPC_N0 [ 8]

PCH_DPC_P1 [8]

PCH_DPC_N1 [ 8]

Layout note:
close to pin17

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

C5621
SC10U6D3V3MX-GP

1 2

Vegas

C5629

SC4D7P50V2BN-GP

12

CRT

CRT

CRT

Vegas

C5602

SCD1U16V2KX-3GP

12

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

A00

A00

56 105Wednesday, November 08, 2017

56 105Wednesday, November 08, 2017

56 105Wednesday, November 08, 2017

of

of

of

1

A00

5

Main Func = HDMI

4

3

2

1

HDMI_CLK_ R

HDMI_CLK# _R

HDMI_DATA 0#_R

123

ED5702

678

4 5

34

2

1

DY

HDMI_CLK# _R
HDMI_CLK_ R

HDMI_DATA 0#_R
HDMI_DATA 0_R

HDMI_DATA 1#_R
HDMI_DATA 1_R

HDMI_DATA 2#_R
HDMI_DATA 2_R

RN5701
SRN470J -3-GP

5V_S0

3

2

DDC_CLK_PH1

1

4

10

9

7

D5701
LBAW 56LT1G-GP

83.00056.Y11

1

DDC_DATA_PH2

23

RN5702
SRN2K2J -1-GP

DDC_CLK _HDMI

DDC_DAT A_HDMI

HDMI_DATA 0#_R_C
HDMI_DATA 0_R_C
HDMI_CLK_ R_C
HDMI_CLK# _R_C

1 2

HDMI_CLK#[8]
HDMI_CLK[8]

D D

C C

69.50007.691:
OBS REASON: Please transfer to down size item 69.48001.081 for cost reduction and good cost down trend

B B

HDMI_DATA 0#[8]
HDMI_DATA 0[8]

HDMI_DATA 1#[8]
HDMI_DATA 1[8]

HDMI_DATA 2#[8]
HDMI_DATA 2[8]

5V_S0

1 2

R5719

DY

100KR2J -1-GP

5V_S0

EMI Request:

ED5701

1

2

3
8
4

A A

5 6

DY

10

9

7

C5701 SC D1U16V2KX-3GP

1 2

C5704 SC D1U16V2KX-3GP

1 2

C5705 SC D1U16V2KX-3GP

1 2

C5703 SC D1U16V2KX-3GP

1 2

C5707 SC D1U16V2KX-3GP

1 2

C5706 SC D1U16V2KX-3GP

1 2

C5708 SC D1U16V2KX-3GP

1 2

C5709 SC D1U16V2KX-3GP

Q5701

G

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2 N702.031

3rd = 84.07 002.I31

F5701

1 2

1 2

R5718

DY

0R3J-L1-G P

CPU_DP1 _CTRL_CLK[8 ]

CPU_DP1 _CTRL_DATA[8]

HDMI_DATA 1#_R_C

HDMI_DATA 1_R_C

HDMI_DATA 2#_R_C

HDMI_DATA 2_R_C

SRN470J -3-GP

D

5V_HDMI_S 0

POLYSW -1D1A6V-9-GP-U

69.48001.081

2ND = 69.5 0011.081
3RD = 69.5 0013.061

RN5703

HDMI_PLL_ GND

123

678

4 5

12

DY

3D3V_S0

Q5702

5

6

2N7002K DW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

R5707
0R2J-2-GP

1

2

3
8
4

5 6

1 2

ER5706
0R0402-P AD-2-GP

1 2

ER5714
0R0402-P AD-2-GP

1 2

ER5713
0R0402-P AD-2-GP

1 2

ER5715
0R0402-P AD-2-GP

ED5703

1

2

3
8
4

5 6

DY

HDMI_CLK_ R_C HDMI_DATA 1_R_C

12

R5702
150R2J-L 1-GP-U

HDMI_DATA 0_R_C

12

R5701
150R2J-L 1-GP-U

HDMI_DATA 0#_R_C

5V_HDMI_S 0

12

C5702

SCD1U16V2KX-3GP

CPU_DP1 _HPD[8]

DDC_CLK _HDMI
DDC_DAT A_HDMI
HPD_HDM I_CON

10

9

7

HDMI_DATA 1_R

HDMI_DATA 1#_RHDMI_CLK# _R_C

HDMI_DATA 2_RHDMI_DATA 0_R

HDMI_DATA 2#_R

HDMI_DATA 0_R_C
HDMI_DATA 0#_R_C
HDMI_DATA 1_R_C
HDMI_DATA 1#_R_C
HDMI_DATA 2_R_C
HDMI_DATA 2#_R_C

HDMI_CLK_ R_C
HDMI_CLK# _R_C

18

11
10
12

1 2

R5712
0R0402-P AD

1 2

ER5705
0R0402-P AD-2-GP

1 2

ER5704
0R0402-P AD-2-GP

1 2

ER5717
0R0402-P AD-2-GP

1 2

ER5716
0R0402-P AD-2-GP

HDMI CONN

HDMI1

+5V_POWER

7

TMDS_DATA0+

9

TMDS_DATA0-

4

TMDS_DATA1+

6

TMDS_DATA1-

1

TMDS_DATA2+

3

TMDS_DATA2-

8

TMDS_DATA0_SHIELD

5

TMDS_DATA1_SHIELD

2

TMDS_DATA2_SHIELD

TMDS_CLOCK_SHIELD
TMDS_CLOCK+
TMDS_CLOCK-

SKT-HDMI23 -168-GP

022.10025.0161

2nd = 022 .10025.0181

3rd = 022.1 0025.0051

84.T3904.H11

HDMI_HPD_ E

<Core Design>

<Core Design>

<Core Design>

DDC/CEC_GROUNG

HOT_PLUG_DETECT

HDMI
(A_Type)

3D3V_S0

C

Q5703

LMBT390 4LT1G-GP

E

12

R5709
10KR2J-L -GP

12

R5708
150R2J-L 1-GP-U

12

R5703
150R2J-L 1-GP-U

SCL

SDA

CEC

RESERVED#14

GND
GND
GND
GND

HDMI_HPD_ B

B

HDMI_DATA 1#_R_C

HDMI_DATA 2_R_C

HDMI_DATA 2#_R_C

DDC_CLK _HDMI

15

DDC_DAT A_HDMI

16

13
17
19

14

20
21
22
23

R5710
150KR2F -L-GP

12

HPD_HDMI_CON

12

R5711
200KR2F -L-GP

RCLAMP0 524P-2-GP

75.00524.A73

5

RCLAMP0 524P-2-GP

75.00524.A73

4

Wistron Corporation

Wistron Corporation

RCLAMP0 524P-2-GP

75.00524.A73

Title

Title

Title

HDMI

HDMI

HDMI

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Wednesd ay, November 08, 201 7

Wednesd ay, November 08, 201 7

Wednesd ay, November 08, 201 7

Date: Sheet

Date: Sheet

3

2

Date: Sheet

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

57 105

57 105

57 105

of

of

1

of

A00

A00

A00

5

4

3

2

1

Main Func = HDD

SATA HDD Connector

5V_S0

E E

DY

12

80 mils

C6002

SC10U6D3V3MX-GP

DY

12

R6001

1 2

0R0805-PA D-2-GP-U

C6001

SCD1U16V2KX-3GP

5V_HDD_S0

SATA_TX_ CON_P0
SATA_TX_ CON_N0

C6007

C6008

SC10U6D3V3MX-GP

12

SCD1U16V2KX-3GP

12

SATA_RX_ CON_N0 S ATA_RX_C ON_N0
SATA_RX_ CON_P0

Close to HDD1

1 2

SATA_TX_ CPU_P0[16]

D D

C C

SATA_TX_ CPU_N0[1 6]

SATA_RX_ CPU_N0[16]
SATA_RX_ CPU_P0[16]

HDD_DEVSLP[16 ]

5V_HDD_S0

Main Func = ODD

5V_S0 ODD_PW R_5V

1 2

R6003
0R0805-PA D-2-GP-U

ODD

B B

C6005 SCD22U1 0V2KX-L 1-GP

1 2

C6006 SCD22U1 0V2KX-L 1-GP

1 2

C6004 SCD22U1 0V2KX-L 1-GP

1 2

C6003 SCD22U1 0V2KX-L 1-GP

1 2

R6002 0R0402-PAD

AFTP6001 AFTE14P-GP

1

C6009

SC10U6D3V3MX-GP

12

ODD

C6018

SCD1U16V2KX-3GP

12

ODD Connector

SATA_ODD_ PRSNT#[16]

SATA_RX_ CPU_P1[16]
SATA_RX_ CPU_N1[16]

SATA_TX_ CPU_N1[16]
SATA_TX_ CPU_P1[16]

SATA_TX_ CON_P0
SATA_TX_ CON_N0

SATA_RX_ CON_N0
SATA_RX_ CON_P0

HDD_DEVSLP _R

5V_HDD_S0

FFS_INT2_Q[67 ]

R6004 0R0402-PAD-2-GP

C6011 SCD01U50V2KX-L -GP
C6010 SCD01U50V2KX-L -GP

C6013 SCD01U50V2KX-L -GP
C6014 SCD01U50V2KX-L -GP

ED6001

1

LINE_1

2

LINE_2

3

DY

GND

4

LINE_3

5

LINE_4

AZ1045-04 F-R7G-GP

75.01045.073

Swap based on the swap report.

NC#10

NC#9

GND
NC#7
NC#6

10
9
8
7
6

Layout Note:
Place near HDD1

HDD1

14
12
11
10

9
8
7
6
5
4
3
2

1

13

STAR-CON12-1 -GP

020.K0049.0012

2nd = 02 0.K0125. 0012

3rd = 020. K0190.0 012

TP6001

TPAD14-OP-G P

ODD_PW R_5V

1 2

1 2

ODD

1 2

ODD

1 2

ODD

1 2

ODD

SATA_TX_ CON_P0
SATA_TX_ CON_N0

SATA_RX_ CON_P0

SATA_ODD_ DA#_C

1

SATA_ODD_ PRSNT#_R

SATA_RX_ CON_P1
SATA_RX_ CON_N1

SATA_TX_ CON_N1
SATA_TX_ CON_P1

ODD1

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2

1

22

ODD

21

ACES-CON20 -30-GP-U1

20.K0708.020

2nd = 02 0.K0050. 0020

<Core Design >

<Core Design >

<Core Design >

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, S ec.1, Hsin Tai Wu Rd., Hsichih ,

21F, 88, S ec.1, Hsin Tai Wu Rd., Hsichih ,

A

Title

Title

Title

INT IO (HDD/ODD)

INT IO (HDD/ODD)

INT IO (HDD/ODD)

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev
Custom

Custom

Custom

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

2

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wedn esday, Nov ember 08, 2017

Wedn esday, Nov ember 08, 2017

Wedn esday, Nov ember 08, 2017

21F, 88, S ec.1, Hsin Tai Wu Rd., Hsichih ,
Taipei Hsien 221, Taiwa n, R.O.C.

Taipei Hsien 221, Taiwa n, R.O.C.

Taipei Hsien 221, Taiwa n, R.O.C.

of

60 105

of

60 105

of

60 105

1

A00

A00

A00

A

5

4

3

2

1

Main Func = WLAN

3D3V_S0

1.1A

C6105

SC10U6D3V3MX-GP

12

D D

C C

PEG_CLK1_CPU#[18]
PEG_CLK1_CPU[18]

PCIE_RX_CPU_N6[16]
PCIE_RX_CPU_P6[16]

PCIE_TX_CON_N6[16]
PCIE_TX_CON_P6[16]

CLKREQ_PCIE#1[18]

WIFI_RF_EN[15]

BLUETOOTH_EN[20]

HOST_DEBUG_TX[24,68]

PLT_RST#[17,31,55,63,76,91]

CL_RST#[18]

CL_CLK[18]
CL_DATA[18]

USB_CPU_PN6[16]
USB_CPU_PP6[16]

DY

TP6103 TPAD14-OP-GP

WIFI_RF_EN WLAN_DISABLE#1
BLUETOOTH_EN
PLT_RST# PLT_RST_NGFF#

CL_CLK
CL_DATA
CL_RST#

3160 does not support C-Link

DY

C6101

12

C6102

SCD1U16V2KX-3GP

12

DY

1

1 2

R6114 0R0402-PAD

1 2

R6113 0R0402-PAD

1 2

R6116 0R0402-PAD

TP6102
TPAD14-OP-GP

1 2

R6109 0R2J-L-GP

1 2

R6119 0R2J-L-GP

1 2

R6108 0R2J-L-GP

R6117

1 2

0R0805-PAD-2-GP-U

SCD1U16V2KX-3GP

1

DY
DY
DY

C6106

SC10U6D3V3MX-GP

12

DY

3D3V_WLAN_S0

E51_RX2

BLUETOOTH_EN_NGFF

E51_RX1
E51_TX1
CL_CLK_R
CL_DATA_R
CL_RST#_R

Reserved for NGFF Debug Card

3D3V_S5

1 2

R6118

B B

0R2J-L-GP

1 2

R6115
0R2J-L-GP

EE Note:
For NFGG Debug Card:
Stuff Ra, Rb; DY Rc.

Note:pin 76 and pin 77 need contact to GND

Support: Intel Dual Band Wireless-AC 3160

A A

AFTP6101AFTE14P-GP
AFTP6105AFTE14P-GP
AFTP6106AFTE14P-GP
AFTP6107AFTE14P-GP
AFTP6108AFTE14P-GP
AFTP6109AFTE14P-GP
AFTP6110AFTE14P-GP

5

Ra

DY

DY

Rb

3D3V_WLAN_S0

E51_TX1HOST_DEBUG_TX

3D3V_WLAN_S0

1

WLAN_CLKREQ_WLAN#

1

WLAN_DISABLE#1

1

BLUETOOTH_EN_NGFF

1

PLT_RST_NGFF#

1

USB_CON_PN6

1

USB_CON_PP6

1

3D3V_WLAN_S0

4

3

3D3V_WLAN_S0

C6104

SCD1U16V2KX-3GP

12

C6103

SCD1U16V2KX-3GP

12

WLAN1

74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30 31
28 29
24

22
20
18
16
14
12
10

8
6
4

2

PAD-SKT-NGFF75P-GP

062.10003.0621

2nd = 062.10007.0081

3rd = 062.10007.0391

USB_CON_PP6

USB_CON_PN6

77

NP

75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33

27
2526
23
21
19
17
15
13
11
9
7
5
3

1

NP

76

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

WLAN_WAKE
WLAN_CLKREQ_WLAN#

PEG_CLK1_CPU#
PEG_CLK1_CPU

PCIE_RX_CPU_N6
PCIE_RX_CPU_P6

PCIE_TX_CON_N6
PCIE_TX_CON_P6

USB_CON_PN6
USB_CON_PP6

A4

A4

A4

2

1 2

R6111 0R0402-PAD-2-GP

1 2

R6110 0R0402-PAD-2-GP

TP6101

1

TPAD14-OP-GP

1 2

R6112
0R0402-PAD

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

NGFF_WLAN CONN

NGFF_WLAN CONN

NGFF_WLAN CONN

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

USB_CPU_PP6

USB_CPU_PN6

CLKREQ_PCIE#1

61 105Wednesday, November 08, 2017

61 105Wednesday, November 08, 2017

61 105Wednesday, November 08, 2017

of

of

of

1

A00

A00

A00

5

4

3

2

1

Main Func = eMMC

1D8V_S5

12

R6311

EMMC_D7[15]

D D

EMMC_D6[15]
EMMC_D5[15]
EMMC_D4[15]
EMMC_D3[15]
EMMC_D2[15]
EMMC_D1[15]
EMMC_D0[15]

EMMC_CL K[15]
EMMC_CM D[15]

EMMC

3D3V_S5

12

R6325

eMMC

0R3J-L1-G P

12

C6318

eMMC

EMMC_RC LK[15]

PLT_RST #[17,31,55 ,61,76,91]

SC1U10V 2KX-1GP

EMMC_CL K
EMMC_CM D

EMMC_RC LK EMMC_R CLK_R
EMMC_RE SET#

eMMC

0R3J-L1-G P

C6316

SCD1U16 V2KX-3GP

eMMC

12

C6319

eMMC

SCD1U16 V2KX-3GP

1 2

R6320 0R2J-2-GP

eMMC

1 2

R6321 0R2J-2-GP

eMMC

1 2

R6322 10R2F-L1 -GP

eMMC

12

12

eMMC

C6320
SC1U10V 2KX-1GP

12

eMMC

EMMC_VC CQ

C6317
SC4D7U6 D3V3KX-GP

EMMC_VC C

EMMC_VD DI

EMMC_CL K_R
EMMC_CM D_R

U6301A

C6

M4

N4
P3
P5

E6
F5

J10

K9

C2

M6
M5

H5
K5

VDD
VDD
VDD
VDD
VDD

VDDF
VDDF
VDDF
VDDF

VDDI

CLK
CMD

DATA_STROBE
RST#

eMMC

072.KMBG 4.0C0U

1 OF 2

DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

EMMC_D0 _R

A3

EMMC_D1 _R

A4

EMMC_D2 _R

A5

EMMC_D3 _R

B2

EMMC_D4 _R

B3

EMMC_D5 _R

B4

EMMC_D6 _R

B5

EMMC_D7 _R

B6

A6
C4
E7
G5
H10
J5
K8
N2
N5
P4
P6

1 2

R6312 10R2F-L1 -GP

eMMC

1 2

R6313 10R2F-L1 -GP

eMMC

1 2

R6314 10R2F-L1 -GP

eMMC

1 2

R6316 10R2F-L1 -GP

eMMC

1 2

R6317 10R2F-L1 -GP

eMMC

1 2

R6318 10R2F-L1 -GP

eMMC

1 2

R6319 10R2F-L1 -GP

eMMC

1 2

R6315 10R2F-L1 -GP

eMMC

Change 10 ohm follow PDG
modify date 4/17

EMMC_D0
EMMC_D1
EMMC_D2
EMMC_D3
EMMC_D4
EMMC_D5
EMMC_D6
EMMC_D7

C C

U6301B

A1

NC#A1

A2

NC#A2

A8

eMMC_E9
eMMC_E10
eMMC_F10
eMMC_K10

B B

EMMC_VC CQ

12

eMMC

EMMC_RE SET# PLT_RST #

A A

5

0510
Corrected to S5

1D8V_S5

R6323

10KR2J-L-GP

1

TP6301 TPAD 14-OP-GP

1

TP6302 TPAD 14-OP-GP

1

TP6303 TPAD 14-OP-GP

1

TP6304 TPAD 14-OP-GP

G

eMMC

S

Q6301
PJA138K A-GP

084.00138.0A31

DY

1 2

R6324
0R2J-2-GP

D

Vth(max)=1.0V

4

NC#A8

A9

NC#A9

A10

NC#A10

A11

NC#A11

A12

NC#A12

A13

NC#A13

A14

NC#A14

B1

NC#B1

B7

NC#B7

B8

NC#B8

B9

NC#B9

B10

NC#B10

B11

NC#B11

B12

NC#B12

B13

NC#B13

B14

NC#B14

C1

NC#C1

C3

NC#C3

C5

NC#C5

C7

NC#C7

C8

NC#C8

C9

NC#C9

C10

NC#C10

C11

NC#C11

C12

NC#C12

C13

NC#C13

C14

NC#C14

D1

NC#D1

D2

NC#D2

D3

NC#D3

D4

NC#D4

D12

NC#D12

D13

NC#D13

D14

NC#D14

E1

NC#E1

E2

NC#E2

E3

NC#E3

E12

NC#E12

E13

NC#E13

E14

NC#E14

F1

NC#F1

F2

NC#F2

F3

NC#F3

F12

NC#F12

F13

NC#F13

F14

NC#F14

G1

NC#G1

G2

NC#G2

G12

NC#G12

G13

NC#G13

G14

NC#G14

H1

NC#H1

H2

NC#H2

H3

NC#H3

H12

NC#H12

H13

NC#H13

H14

NC#H14

J1

NC#J1

J2

NC#J2

072.KMBG 4.0C0U

3

eMMC

2 OF 2

NC#J3
NC#J12
NC#J13
NC#J14

NC#K1

NC#K2

NC#K3

NC#K12
NC#K13
NC#K14

NC#L1

NC#L2

NC#L3
NC#L12
NC#L13
NC#L14

NC#M1
NC#M2
NC#M3
NC#M7
NC#M8

NC#M9
NC#M10
NC#M11
NC#M12
NC#M13
NC#M14

NC#N1

NC#N3

NC#N6

NC#N7

NC#N8

NC#N9
NC#N10
NC#N11
NC#N12
NC#N13
NC#N14

NC#P1
NC#P2
NC#P8

NC#P9
NC#P11
NC#P12
NC#P13
NC#P14

RFU#A7
RFU#E5
RFU#E8
RFU#E9

RFU#E10
RFU#F10

RFU#G3

RFU#G10

RFU#K6
RFU#K7

RFU#K10

RFU#P7

RFU#P10

J3
J12
J13
J14
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
M1
M2
M3
M7
M8
M9
M10
M11
M12
M13
M14
N1
N3
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P8
P9
P11
P12
P13
P14

A7
E5
E8
E9
E10
F10
G3
G10
K6
K7
K10
P7
P10

eMMC_E9
eMMC_E10
eMMC_F10

eMMC_K10

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet

Date: Sheet

2

Date: Sheet

eMMC

eMMC

eMMC

Vegas SKL/KBL-R

Vegas SKL/KBL-R

Vegas SKL/KBL-R

63 105Wednesd ay, November 08, 201 7

63 105Wednesd ay, November 08, 201 7

63 105Wednesd ay, November 08, 201 7

1

A00

A00

of

of

of

A00

5

Main Func = Power BTN

4

Power button

3

2

1

Layout note:

RN6401

1

LID_CL_SIO#[24]
KBC_PW RBTN#[24]

D D

3D3V_S5

LID_CLOSE #_C

KBC_PW RBTN#_C

1

1

1

2 3

SRN100J -3-GP

AFTP640 2

AFTP640 1

AFTP640 4

4

EC6401

SCD1U16V2KX-3GP

12

DY

G6401 place to buttom
G6402 place to top

12

EC6403

SC1KP50V2KX-L-1-GP

ED6401

DY

12

DY

LID_CLOSE #_C
KBC_PW RBTN#_C

AZ5725-01FDR7G-GP

G6401

GAP-OPEN

2 1

3D3V_S5

G6402

GAP-OPEN

C6401

DY

SCD1U16V2KX-3GP

12

2 1

PWR1

6
4
3
2

1
5

ACES-CON 4-88-GP

020.K0005.0004

2nd = 020 .K0264.0004

1

AFTP640 3

Main Func = Battery LED

Low actived from KBC GPIO

1 2

CHG_AMB ER_LED#[24]

C C

R6405
0R0402-P AD

CHG_AMB ER_LED_R#

Low actived from KBC GPIO

1 2

BATT_W HITE_LED#[24]

R6404
0R0402-P AD

BATT_W HITE_LED_R#

Main Func = HDD LED

SATA HDD LED

B B

LOW actived from PCH GPIO

Q6403

R2

B

R1

RN2418-G P

084.02418.0011

Q6404

R2

B

R1

RN2418-G P

084.02418.0011

0516 Follow KY15

E

C

E

C

MASK_SA TA_LED#[24]

5V_S5

AMBER_L ED_BAT

12

DY

5V_S5

WHITE _LED_BAT

12

DY

EC6402

SCD1U25V2KX-GP

EC6404

SCD1U25V2KX-GP

1 2

R6407
422R2F-2 -GP

1 2

R6406
274R2F-G P

1D8V_S0

12

R6401
10KR2J-L -GP

HWHDLED

G

BAT_AMB ER

BAT_W HITE

Battery LED1

(AMBER_LED)

LED1

+

Yellow

1

2

-

3

White

+

LED-YW-5 -GP

083.1212A.0070

Battery LED2

(WHITE_LED)

BATT_W HITE_LED_R#

SATA_LE D#_R[16]

A A

5

4

DS

Q6401
DMN5L06 K-7-GP

HWHDLED

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Wednesd ay, November 08, 201 7

Wednesd ay, November 08, 201 7

Wednesd ay, November 08, 201 7

Date: Sheet

Date: Sheet

3

2

Date: Sheet

LED Board&Power Button

LED Board&Power Button

LED Board&Power Button

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

64 105

64 105

64 105

of

of

of

A00

A00

A00

5

KB_DET#[20 ]

KSI[0..7][24]

D D

KSO[0..1 6][2 4]

CAP LED Control

LOW actived from KBC GPIO

CAP_LED_ R#

1 2

CAP_LED# _S[2 4]

C C

R6508
0R0402-P AD

Internal Keyboard Connector

B

RN2418-GP

1
1

KSI7

1

KSI6

1

KSI4

1

KSI2

1

KSI5

1

KSI1

1

KSI3

1

KSI0

1

KSO5

1

KSO4

1

KSO7

1

KSO6

1

KSO8

1

KSO3

1

KSO1

1

KSO2

1

KSO0

1

KSO12

1

KSO16

1

KSO15

1

KSO13

1

KSO14

1

KSO9

1

KSO11

1

KSO10

CAP_LED

1

5V_S0

Q6502

R2

E

R1

C

AFTP6519
AFTP6523
AFTP6511
AFTP6521
AFTP6533
AFTP6513
AFTP6540
AFTP6502
AFTP6507
AFTP6536
AFTP6522
AFTP6534
AFTP6512
AFTP6505
AFTP6518
AFTP6517
AFTP6510
AFTP6520
AFTP6538
AFTP6508
AFTP6515
AFTP6535
AFTP6539
AFTP6516
AFTP6506
AFTP6503

AFTP6537

084.02418.0011

R6506
1KR2J-1-GP

AFTP6532

32
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2

1

31

KB1

PTWO-CON3 0-10-GP

20.K0621.030

2nd= 20. K0592.030

3nd= 20. K0565.030

1 2

1

CAP_LEDCAP_L ED_Q

CAP_LED

0502 Deleted KB2
0524 Deleted KBBL1 block

B B

4

Main Func = TPADMain Func = KB

Support PTP

PS2

I2C

SMBUS

CLK_TP_SI O[24]
DAT_TP_SIO[24]

I2C0_SCL _TCH_PAD[20]
I2C0_SDA _TCH_PAD[20]

PCH_SMBCL K[12, 13,18,56,6 7]

PCH_SMBDA TA[12,1 3,18,56,67 ]

Need to check with SW.

3

R6516
1KR2J-1-GP

TP_EN#

TP_EN#[24]

TP_VDD

1

23

RN6504
SRN10KJ-5 -GP

4

EC6503

SC33P50V2JN-3GP

EC6501

SC33P50V2JN-3GP

12

12

DY

12

DY

DY

I2C0_SCL _TCH_PAD I2C1 _SCL_R

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

I2C0_SDA _TCH_PAD

1 2

1

RN6503

2 3

1 2

R6518 0R2J-2 -GP

NON_PTP

1 2

R6519 0R2J-2 -GP

NON_PTP

EC6502

SC33P50V2JN-3GP

EC6504

SC33P50V2JN-3GP

12

DY

12

R6512
0R0402-P AD

Q6204_G

Q6503

1

2

PTP

3 4

2N7002K DW-GP

Vages install Non PTP

1 2

R6515 0R2 J-2-GP

DY

1 2

R6511 0R2 J-2-GP

DY

EC6505

EC6506

12

12

DY

DY

SC33P50 V2JN-3GP
SC33P50 V2JN-3GP

3D3V_S0

3D3V_S5

R6521

0R0402-PAD-2-GP

12

12

R6520

0R2J-2-GP

2

NON_PTP

3D3V_TP_S5_R

C6503
SCD1U16V 2KX-3GP

1 2

TP_VDD

R6509

1 2

100KR2J-1 -GP

Precision Touch Pad Connector

TP_VDD

I2C1_SDA _R

12

12

R6513

C6504

SCD1U16V2KX-3GP

4K7R2J-2-G P

NON_PTP

INT_TP#[4,24]
TP_LOCK#[24]

I2C1_SCL _R

INT_TP#
TP_LOCK#
TPDATA_C
TPCLK_C

AFTP6531

Need to check if it is Active High or Active Low
and check if there is PH on TPAD side.

TP_VDD

1 2

DY

TPCLK_C
TPDATA_C

I2C1_SCL _R
I2C1_SDA _R

1

23

RN6502
SRN2K2J-1 -GP

4

I2C1_SDA _R

I2C1_SCL _R
I2C1_SDA _R

S

G

G

D

D

TP_VDD

TP_ON#_GA TE TP_LOCK#

Q6504
DMP2130L -7-GP

84.02130.031

2ND = 84.03413.A31

3D3V_S0

R6517

0R3J-L1-GP

4

SRN33J-5-G P-U

TP_VDD5V_S0

PTP

6

5

TP_VDD Discharge Circuit

TP_ON#_GA TE

9
1

2
3
4
5
6
7
8

10

1

STAR-CON8-2-G P

020.K0182.0008

2nd = 02 0.K0243.00 08

Change TP1 pin define ,
pin1 connect VDD 1/26

TP side has pull high

1 2

R6514
10KR2J-L-G P

TP_VDD

1

TPCLK_C
TPDATA_C
I2C1_SCL _R
I2C1_SDA _R
INT_TP#
TP_LOCK#

AFTP6529

1

AFTP6530

1

AFTP6524

1

AFTP6528

1

AFTP6527

1

AFTP6525

1

AFTP6526

Q6505

G

DY

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

TP1

INT_TP#

D

Pin number

Q6205_Q

1

2

3

4

5

6

7

8

TP_VDD

DY

12

R6522
100R3J-4-G P

Pin name

VDD

DAT(I2C)

CLK(I2C)

GND

ATTN

GPIO

DAT(PS2)

CLK(PS2)

1

A A

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih ,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih ,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih ,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
Custom

Custom

Custom

Wednesday, N ovember 08, 2017

Wednesday, N ovember 08, 2017

Wednesday, N ovember 08, 2017
Date: Sh eet of

Date: Sh eet of

5

4

3

2

Date: Sh eet

Taipei Hsien 221, Taiwan, R.O.C.

Key Board&Touch Pad

Key Board&Touch Pad

Key Board&Touch Pad

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

of

65 1 05

65 1 05

65 1 05

A00

A00

A00

5

4

3

2

1

Main Func = IO Connector

I/O Board Connector

D D

IOBD1

31

1

2

USB_PN5 _C[33]

Cardreader

USB3(USB2.0)

C C

Universal Jack

1 2

R6601

DY

0R3J-L1-G P

AUD_AGN D

USB_PP5 _C[3 3]

USB_PN2 _C[37]

USB_PP2 _C[37]

USB20_V CCA

3D3V_S0

AUD_POR TA_L_R_B[29 ]
AUD_POR TA_R_R_B[29]

SLEEVE_ R[29]

RING2_R[29]

JACK_PL UG[29]

AUD_AGN D

AUD_AGN D

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

32

ACES-CON 30-9-GP-U2

20.K0510.030

2nd = 20.K 0580.030

Pitch: 1mm
Power: 6 pins
GND: 7 pins
AGND: 2 Pins

B B

AUD_AGN D

A A

5

4

USB_PN5 _C
USB_PP5 _C
USB_PN2 _C
USB_PP2 _C
RING2_R
AUD_POR TA_L_R_B
JACK_PL UG

AUD_POR TA_R_R_B
SLEEVE_ R
USB20_V CCA

1
1
1
1
1
1
1

1
1
1

1

1

3

AFTP660 1 AFTE1 4P-GP
AFTP660 2 AFTE1 4P-GP
AFTP660 3 AFTE1 4P-GP
AFTP660 4 AFTE1 4P-GP
AFTP660 5 AFTE1 4P-GP
AFTP660 6 AFTE1 4P-GP
AFTP660 7 AFTE1 4P-GP

AFTP660 8 AFTE1 4P-GP
AFTP660 9 AFTE1 4P-GP
AFTP661 0 AFTE1 4P-GP

AFTP661 1 AFTE1 4P-GP

AFTP661 2 AFTE1 4P-GP

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Date: Sheet

Date: Sheet

2

Date: Sheet

application without get Wistron permission

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

IO Board Connector

IO Board Connector

IO Board Connector

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wednesd ay, November 08, 201 7

Wednesd ay, November 08, 201 7

Wednesd ay, November 08, 201 7

Vegas SKL/KBL-U

66 105

66 105

66 105

1

A00

A00

of

of

of

A00

5

4

3

2

1

SSID = User.interface

Free Fall Sensor

DVT1 add FFS 2/18

D D

3D3V_S0

1 2

R6701
0R0603-P AD-2-GP-U

C C

12

FFS

PCH_SMB CLK[12 ,13,18,56,65]
PCH_SMB DATA[12,1 3,18,56,65]

C6702

SCD1U16V2KX-3GP

FFS

12

SCD1U16V2KX-3GP

DY

3D3V_RU N_FFS

C6701

3D3V_RU N_FFS

C6703

SC10U6D3V3MX-GP

12

U6701

9

VDD

10

VDD_IO

1

SCL/SPC

4

SDA/SDI/SDO

3

SDO/SA0

LNG2DMT R-GP

074.LNG2D.00BZ

3D3V_S0

12

R6703

FFS

100KR2J -1-GP

FFS

RES

INT1
INT2

GND
GND
GND

CS

3D3V_S0

12

R6702

2
5

12
11

6
7
8

DY

100KR2J -1-GP

HDD_FAL L_INT [18]

FALL_INT2

Q6701

R6705

100KR2J-1-GP

1 2

R6706
0R2J-2-GP

1234

FFS

5

6

DY

2N7002K DW-GP

84.2N702.A3F

2nd = 084.27002.003F

3rd = 84.2N702.E3F

3

3D3V_S0

12

R6704

DY

100KR2J -1-GP

12

R6707

FFS

1MR2J-1-G P

2014.04.24 Venrer suggest,reserve to prevent error trigger

FFS_INT2 [20]

PCH

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

Free Fall Sensor

Free Fall Sensor

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Free Fall Sensor

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

67 105Wednesd ay, November 08, 201 7

67 105Wednesd ay, November 08, 201 7

67 105Wednesd ay, November 08, 201 7

of

of

of

A00

A00

A00

5V_S0

12

DY

B B

HDD

Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.

Note

- no via, trace, under the sensor (keep out area around 2mm)

- stay away from the screw hole or metal shield soldering joints

- design PCB pad based on our sensor LGA pad size (add 0.1mm)

- solder stencil opening to 90% of the PCB pad size

A A

- mount the sensor near the center of mass of the NB as possible as you can

5

FFS_INT2_ Q[60]

4

5

4

3

2

1

Main Func = Debug

D D

ESPI Debug Connector

DBG1

0607 Modify

ESPI_CLK_CON

TP6801TPAD14-OP-GP

0522 Modify

C C

HOST_DEBUG_TX[24,61]

UART_2_CTXD_DRXD[20]

UART_2_CRXD_DTXD[20]

UART

HOST_DEBUG_TX

UART_2_CTXD_DRXD

3D3V_S0

1 2

R6807 0R2J-2-GP

Debug

1 2

R6808 0R2J-2-GP

Debug

1 2

R6809 0R2J-2-GP

Debug

BOM:DVT2 DY

TP6802TPAD14-OP-GP
TP6803TPAD14-OP-GP
TP6804TPAD14-OP-GP
TP6805TPAD14-OP-GP
TP6806TPAD14-OP-GP
TP6807TPAD14-OP-GP

1

ESPI_RESET#_CON

1

ESPI_CS#_CON

1

ESPI_IO3_CON

1

ESPI_IO2_CON

1

ESPI_IO1_CON

1

ESPI_IO0_CON

1

HOST_DEBUG_TX_CON

UART_2_CTXD_DRXD_CON
UART_2_CRXD_DTXD_CONUART_2_CRXD_DTXD

15

1

2
3
4

20.F0765.014

5
6
7
8

9
10
11
12
13
14
16

DM-ACES-CON14-5-GP-01

ZZ.F0765.01401

B B

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

2

Vegas SKL/KBL-R

Vegas SKL/KBL-R

Vegas SKL/KBL-R

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Dubug connector

Dubug connector

Dubug connector

68 105Friday, November 10, 2017

68 105Friday, November 10, 2017

68 105Friday, November 10, 2017

of

of

of

1

A00

A00

A00

5

Main Func = dGPU

4

GFX & GPP, 85Ω
GFX & GPP CLK, 85Ω

GPU1A

3

1 OF 7

2

1

20170502

PEG_TX_ GPU_P0[16]

D D

C C

B B

PEG_TX_ GPU_N0[16]

PEG_TX_ GPU_P1[16]
PEG_TX_ GPU_N1[16]

PEG_TX_ GPU_P2[16]
PEG_TX_ GPU_N2[16]

PEG_TX_ GPU_P3[16]
PEG_TX_ GPU_N3[16]

DGPU_HOLD_RST#

H

L

H IGPU with BACO

DGPU_HO LD_RST#[20]

dGPU mode

IGPU

PLT_RST #[17,31,55 ,61,63,91]

1 2

R7623
0R0402-P AD

2

1

D7601
BAW 56-5-GP

DY

3D3V_VG A_S0

12

R7625

DY

10KR2J-L -GP

3

PEG_TX_ GPU_P0
PEG_TX_ GPU_N0

PEG_TX_ GPU_P1
PEG_TX_ GPU_N1

PEG_TX_ GPU_P2

PEG_TX_ GPU_P3
PEG_TX_ GPU_N3

R7601
1KR2F-L1 -GP

1 2

OPS

1 2

R7621
0R0402-P AD

PEG_CLK _CPU[1 8]
PEG_CLK _CPU#[18]

PWRG OOD_TEST

VGA_RST #ATI_RST#

DY

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

NC#V30

U31

NC#U31

U29

NC#U29

T28

NC#T28

T30

NC#T30

R31

NC#R31

R29

NC#R29

P28

NC#P28

P30

NC#P30

N31

NC#N31

N29

NC#N29

M28

NC#M28

M30

NC#M30

L31

NC#L31

L29

NC#L29

K30

NC#K30

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

TEST_PG

AL27

PERST#

C7609

SC47P50V2JN-3GP

12

JET-XT-S3 -GP

OPS

PCI EXPRESS INTERFACE

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

NC#W24
NC#W23

NC#V27

NC#U26

NC#U24
NC#U23

NC#T26
NC#T27

NC#T24
NC#T23

NC#P27
NC#P26

NC#P24
NC#P23

NC#M27
NC#N26

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

AH30
AG31

AG29
AF28

AF27
AF26

AD27
AD26

AC25
AB25

Y23
Y24

AB27
AB26

Y27
Y26

W24
W23

V27
U26

U24
U23

T26
T27

T24
T23

P27
P26

P24
P23

M27
N26

Y22

AA22

PEG_RX_ GPU_P0
PEG_RX_ GPU_N0

PEG_RX_ GPU_P1
PEG_RX_ GPU_N1

PEG_RX_ GPU_P2
PEG_RX_ GPU_N2PEG_TX_ GPU_N2

PEG_RX_ GPU_P3
PEG_RX_ GPU_N3

PCIE_CALR _TX

PCIE_CALR _RX

1 2

C7601 SC D22U10V2KX-L1 -GP

OPS

1 2

C7602 SC D22U10V2KX-L1 -GP

OPS

1 2

C7603 SC D22U10V2KX-L1 -GP

OPS

1 2

C7604 SC D22U10V2KX-L1 -GP

OPS

1 2

C7605 SC D22U10V2KX-L1 -GP

OPS

1 2

C7606 SC D22U10V2KX-L1 -GP

OPS

1 2

C7607 SC D22U10V2KX-L1 -GP

OPS

1 2

C7608 SC D22U10V2KX-L1 -GP

OPS

12

R76221K69R2F -2-GP

OPS

1 2

R7618

OPS

1KR2F-L1 -GP

PEG_RX_ CPU_P0 [16]
PEG_RX_ CPU_N0 [16 ]

PEG_RX_ CPU_P1 [16]
PEG_RX_ CPU_N1 [16 ]

PEG_RX_ CPU_P2 [16]
PEG_RX_ CPU_N2 [16 ]

PEG_RX_ CPU_P3 [16]
PEG_RX_ CPU_N3 [16 ]

0D95V_VGA_S0

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

Date: Sheet

Date: Sheet

Date: Sheet

Wednesd ay, November 08, 201 7 10576

Wednesd ay, November 08, 201 7 10576

Wednesd ay, November 08, 201 7 10576

076_GPU(1/5) PEG

076_GPU(1/5) PEG

076_GPU(1/5) PEG

<Project Name>

<Project Name>

<Project Name>

1

of

of

of

5

Main Func = dGPU

GPU1E

AA27

GND

AB24

GND

AB32

D D

C C

B B

A A

AC24
AC26
AC27
AD25
AD32

AE27

AF32
AG27
AH32

K28
K32

L27
M32
N25
N27
P25
P32
R27

T25

T32
U25
U27
V32

W25
W26
W27

Y25
Y32

M6
N13
N16
N18
N21

P6

P9
R12
R15
R17
R20

T13
T16
T18
T21

T6
U15
U17
U20

U9
V13
V16
V18
Y10
Y15
Y17
Y20
R11

T11

AA11

M12
N11
V11

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

JET-XT-S3-GP

GND

OPS

5

5 OF 7

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

VSS_MECH
VSS_MECH
VSS_MECH

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

A32
AM1
AM32

VSS_MECH1
VSS_MECH2
VSS_MECH3

4

3

1.8V and 0.95V for Clock resource

DPLL_PVDD1D8V_VGA_S0

1 2

R7704 0R0603-PAD

12

C7713

DY

SC10U6D3V3MX-GP

0D95V_VGA_S0 DPLL_VDDC

1 2

R7705 0R0603-PAD

GPU1F

NC_VARY_BL

NC_DIGON

NC_UPHYAB_TMDPA_TX0N
NC_UPHYAB_TMDPA_TX0P

NC_UPHYAB_TMDPA_TX1N
NC_UPHYAB_TMDPA_TX1P

NC_UPHYAB_TMDPA_TX2N
NC_UPHYAB_TMDPA_TX2P

NC_UPHYAB_TMDPA_TX3N
NC_UPHYAB_TMDPA_TX3P

NC_TXOUT_L3P
NC_TXOUT_L3N

TMDP

NC_UPHYAB_TMDPB_TX0N
NC_UPHYAB_TMDPB_TX0P

NC_UPHYAB_TMDPB_TX1N
NC_UPHYAB_TMDPB_TX1P

NC_UPHYAB_TMDPB_TX2N
NC_UPHYAB_TMDPB_TX2P

NC_UPHYAB_TMDPB_TX3N

1

TP7701

1

TP7702

1

TP7703

NC_UPHYAB_TMDPB_TX3P

JET-XT-S3-GP

NC_TXOUT_U3P

NC_TXOUT_U3N

OPS

4

OPS

OPS

6 OF 7

3

12

C7711
SC1U10V2KX-1GP

12

C7715
SC1U10V2KX-1GP

AB11
AB12

AL15
AK14

AH16
AJ15

AL17
AK16

AH18
AJ17

AL19
AK18

AH20
AJ19

AL21
AK20

AH22
AJ21

AL23
AK22

AK24
AJ23

40mA

12

C7710

OPS

SCD1U16V2KX-3GP

32mA

12

C7714

OPS

SCD1U16V2KX-3GP

BALL: AB11, AB12
R16 : NC
MESO : VDDC

2

GPU1G

AG15

NC_DP_VDDR#AG15

AG16

NC_DP_VDDR#AG16

AF16

NC_DP_VDDR#AF16

AG17

NC_DP_VDDR#AG17

AG18

NC_DP_VDDR#AG18

AG19

NC_DP_VDDR#AG19

AF14

DP_VDDR

AG20

NC_DP_VDDC#AG20

AG21

NC_DP_VDDC#AG21

AF22

NC_DP_VDDC#AF22

AG22

NC_DP_VDDC#AG22

AD14

DP_VDDC

AG14

NC_DP_VSSR#AG14

AH14

NC_DP_VSSR#AH14

AM14

NC_DP_VSSR#AM14

AM16

NC_DP_VSSR#AM16

AM18

NC_DP_VSSR#AM18

AF23

NC_DP_VSSR#AF23

AG23

NC_DP_VSSR#AG23

AM20

NC_DP_VSSR#AM20

AM22

NC_DP_VSSR#AM22

AM24

NC_DP_VSSR#AM24

AF19

NC_DP_VSSR#AF19

AF20

NC_DP_VSSR#AF20

AE14

DP_VSSR

AF17

NC_UPHYAB_DP_CALR

JET-XT-S3-GP

DP POWER

NC/DP POWER

7 OF 7

NC#AE11
NC#AF11
NC#AE13
NC#AF13

NC#AG8

NC#AG10

NC#AF6
NC#AF7
NC#AF8
NC#AF9

NC#AE1

NC#AE3
NC#AG1
NC#AG6
NC#AH5

NC#AF10

NC#AG9
NC#AH8

NC#AM6
NC#AM8

NC#AG7

NC#AG11

NC#AE10

1

AE11
AF11
AE13
AF13
AG8
AG10

AF6
AF7
AF8
AF9

AE1
AE3
AG1
AG6
AH5
AF10
AG9
AH8
AM6
AM8
AG7
AG11

AE10

OPS

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

077_GPU (2/5) DIGITALOUT

077_GPU (2/5) DIGITALOUT

077_GPU (2/5) DIGITALOUT

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Date: Sheet

Date: Sheet

Date: Sheet

Wednesday, November 08, 2017 10577

Wednesday, November 08, 2017 10577

Wednesday, November 08, 2017 10577

2

of

of

of

1

X00

5

Main Func = dGPU

D D

MAA0_0[81]
MAA0_1[81]
MAA0_2[81]
MAA0_3[81]
MAA0_4[81]
MAA0_5[81]
MAA0_6[81]

C C

B B

A A

MAA0_7[81]
MAA0_8[81]

MAA1_0[81]
MAA1_1[81]
MAA1_2[81]
MAA1_3[81]
MAA1_4[81]
MAA1_5[81]
MAA1_6[81]
MAA1_7[81]
MAA1_8[81]

EDCA0_0[81]
EDCA0_1[81]
EDCA0_2[81]
EDCA0_3[81]

EDCA1_0[81]
EDCA1_1[81]
EDCA1_2[81]
EDCA1_3[81]

DDBIA0_0[81]
DDBIA0_1[81]
DDBIA0_2[81]
DDBIA0_3[81]

DDBIA1_0[81]
DDBIA1_1[81]
DDBIA1_2[81]
DDBIA1_3[81]

WCKA 0_0[81]
WCKA 0b_0[81]
WCKA 0_1[81]
WCKA 0b_1[81]
WCKA 1_0[81]
WCKA 1b_0[81]
WCKA 1_1[81]
WCKA 1b_1[81]

ADBIA0[81]
ADBIA1[81]

CSA0b_0[81]
CSA1b_0[81]

CKEA0[8 1]
CKEA1[8 1]

WEA 0b[81]
WEA 1b[81]

CASA0b[81]
CASA1b[81]
RASA0b[81]
RASA1b[81]

CLKA0[81]
CLKA0b[81]
CLKA1[81]
CLKA1b[81]

5

DQA0_0[81]
DQA0_1[81]
DQA0_2[81]
DQA0_3[81]
DQA0_4[81]
DQA0_5[81]
DQA0_6[81]
DQA0_7[81]
DQA0_8[81]
DQA0_9[81]
DQA0_10[8 1]
DQA0_11[8 1]
DQA0_12[8 1]
DQA0_13[8 1]
DQA0_14[8 1]
DQA0_15[8 1]
DQA0_16[8 1]
DQA0_17[8 1]
DQA0_18[8 1]
DQA0_19[8 1]
DQA0_20[8 1]
DQA0_21[8 1]
DQA0_22[8 1]
DQA0_23[8 1]
DQA0_24[8 1]
DQA0_25[8 1]
DQA0_26[8 1]
DQA0_27[8 1]
DQA0_28[8 1]
DQA0_29[8 1]
DQA0_30[8 1]
DQA0_31[8 1]

Please MVREF drivers and Caps close to ASIC

DDR3/GDDR3 Memory Stuff Option(R16)

MVDDQ

Ra 40.2R

Rb

12

R7817
40D2R2F -GP

Ra

OPS

12

R7818

Rb

100R2F-L 3-GP

OPS

Place all these componets very close to GPU (within 25mm) and keep all
components close to each other
This basic topology should be used for DRAM_RST for DDR3/GDDR5

GDDR5

1.5V

40.2R

100R

DRAM_RS T[81]

4

GDDR3

1D35V

100R

12

C7805

OPS

SC1U10V 2KX-1GP

4

DQA1_0[81]
DQA1_1[81]
DQA1_2[81]
DQA1_3[81]
DQA1_4[81]
DQA1_5[81]
DQA1_6[81]
DQA1_7[81]
DQA1_8[81]
DQA1_9[81]
DQA1_10[8 1]
DQA1_11[8 1]
DQA1_12[8 1]
DQA1_13[8 1]
DQA1_14[8 1]
DQA1_15[8 1]
DQA1_16[8 1]
DQA1_17[8 1]
DQA1_18[8 1]
DQA1_19[8 1]
DQA1_20[8 1]
DQA1_21[8 1]
DQA1_22[8 1]
DQA1_23[8 1]
DQA1_24[8 1]
DQA1_25[8 1]
DQA1_26[8 1]
DQA1_27[8 1]
DQA1_28[8 1]
DQA1_29[8 1]
DQA1_30[8 1]
DQA1_31[8 1]

1D35V_V GA_S0

12

DY

DDR3

1.5V

40.2R

100R

Ra

Rb

R7802
2K2R2J-L 1-GP

R7804
49D9R2F -L1-GP

1D35V_V GA_S01D35V_V GA_S0

12

R7810
40D2R2F -GP

OPS

12

R7814
100R2F-L 3-GP

OPS

1 2

OPS

3

3.24

MVREFSAMVREFDA

12

C7801

OPS

SC1U10V 2KX-1GP

???
Difference with AMD

DRAM_RS T_R

C7802

12

OPS

1 2

OPS

SC100P50V2JN-3GP

10R2J-L-G P

R7803

12

OPS

3

DRAM_RS T_VGA1

R7819

2

GPU1C

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4

DRAM_RS T_VGA1

12

C7821
SCD1U16 V2KX-3GP

CLKTESTB_C

12

R7820
51D1R2F -GP

DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MVREFDA
MVREFSA

MEM_CAL RP0

CLKTEST A
CLKTEST B

Debug only, for
clock observation,
if not needed, DNI

DQ

Jet Setting

1 2

R7809 120R2F-GP

OPS

12

DY

DY

C7822

SCD1U16 V2KX-3GP

51D1R2F -GP

0510
Follow AMD adding DY cap

12

C7803

5K1R2F-2-GP

SC68P50V2JN-1GP

DY

R7821

DY

CLKTESTA_C

12

DY

K27

DQA0_0

J29

DQA0_1

H30

DQA0_2

H32

DQA0_3

G29

DQA0_4

F28

DQA0_5

F32

DQA0_6

F30

DQA0_7

C30

DQA0_8

F27

DQA0_9

A28

DQA0_10

C28

DQA0_11

E27

DQA0_12

G26

DQA0_13

D26

DQA0_14

F25

DQA0_15

A25

DQA0_16

C25

DQA0_17

E25

DQA0_18

D24

DQA0_19

E23

DQA0_20

F23

DQA0_21

D22

DQA0_22

F21

DQA0_23

E21

DQA0_24

D20

DQA0_25

F19

DQA0_26

A19

DQA0_27

D18

DQA0_28

F17

DQA0_29

A17

DQA0_30

C17

DQA0_31

E17

DQA1_0

D16

DQA1_1

F15

DQA1_2

A15

DQA1_3

D14

DQA1_4

F13

DQA1_5

A13

DQA1_6

C13

DQA1_7

E11

DQA1_8

A11

DQA1_9

C11

DQA1_10

F11

DQA1_11

A9

DQA1_12

C9

DQA1_13

F9

DQA1_14

D8

DQA1_15

E7

DQA1_16

A7

DQA1_17

C7

DQA1_18

F7

DQA1_19

A5

DQA1_20

E5

DQA1_21

C3

DQA1_22

E1

DQA1_23

G7

DQA1_24

G6

DQA1_25

G1

DQA1_26

G3

DQA1_27

J6

DQA1_28

J1

DQA1_29

J3

DQA1_30

J5

DQA1_31

K26

MVREFDA

J26

MVREFSA

J25

NC#J25

K25

MEM_CALRP0

L10

DRAM_RST#

K8

CLKTESTA

L7

CLKTESTB

JET-XT-S3 -GP

OPS

2

MEMORY INTERFACE

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

Date: Sheet

Date: Sheet

Date: Sheet

Wednesd ay, November 08, 201 7 10578

Wednesd ay, November 08, 201 7 10578

Wednesd ay, November 08, 201 7 10578

GDDR5/DDR3GDDR5/DDR3

3 OF 7

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8
MAA0_9

MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7
MAA1_8
MAA1_9

WCKA0_0

WCKA0#_0

WCKA0_1

WCKA0#_1

WCKA1_0

WCKA1#_0

WCKA1_1

WCKA1#_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3
DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

ADBIA0
ADBIA1

CLKA0

CLKA0#

CLKA1

CLKA1#

RASA0#
RASA1#

CASA0#
CASA1#

CSA0#_0
CSA0#_1

CSA1#_0
CSA1#_1

CKEA0
CKEA1

WEA0#
WEA1#

1

MAA0_0

K17

MAA0_1

J20

MAA0_2

H23

MAA0_3

G23

MAA0_4

G24

MAA0_5

H24

MAA0_6

J19

MAA0_7

K19

MAA0_8

G20
L17

MAA1_0

J14

MAA1_1

K14

MAA1_2

J11

MAA1_3

J13

MAA1_4

H11

MAA1_5

G11

MAA1_6

J16

MAA1_7

L15

MAA1_8

G14
L16

WCKA 0_0

E32

WCKA 0b_0

E30

WCKA 0_1

A21

WCKA 0b_1

C21

WCKA 1_0

E13

WCKA 1b_0

D12

WCKA 1_1

E3

WCKA 1b_1

F4

EDCA0_0

H28

EDCA0_1

C27

EDCA0_2

A23

EDCA0_3

E19

EDCA1_0

E15

EDCA1_1

D10

EDCA1_2

D6

EDCA1_3

G5

DDBIA0_0

H27

DDBIA0_1

A27

DDBIA0_2

C23

DDBIA0_3

C19

DDBIA1_0

C15

DDBIA1_1

E9

DDBIA1_2

C5

DDBIA1_3

H4

L18

ADBIA0

K16

ADBIA1

H26

CLKA0

H25

CLKA0b

G9

CLKA1

H9

CLKA1b

G22

RASA0b

G17

RASA1b

G19

CASA0b

G16

CASA1b

CSA0b_0

H22
J22

CSA1b_0

G13
K13

K20

CKEA0

J17

CKEA1

G25

WEA 0b

H10

WEA 1b

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

078_GPU (3/5) VRAM I/F

078_GPU (3/5) VRAM I/F

078_GPU (3/5) VRAM I/F

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

ADD

DM

DQS

Ctrl

CLK

CMD

Ctrl, CS

Ctrl

CMD

of

of

of

TESTEN

TESTEN

XO_IN
XO_IN2

1 2

R7937
0R0402-PAD

5

2N7002KDW-GP

1D8V_VGA_S0

1

6

2345

OPS

Q7901

GPU_PWR_LEVEL_R

R16: DY
MESO : 上件

SMB_CLK_VGA_R

SMB_DATA_VGA_R

DGPU_PWROK[19,24,85]

3D3V_VGA_S0

4

RN7902
SRN4K7J-8-GP

OPS

1

2 3

SMB_CLK_VGA_R

SMB_DATA_VGA_R

Q7902

G

S

2N7002K-2-GP

RN7905

4

MESO

SRN10KJ-5-GP

1 2

R7912 0R0402-PAD

1 2

R7914 0R0402-PAD

3D3V_VGA_S0

12

R7921

OPS

10KR2J-L-GP

OPS

D

23
1

R7904
0R2J-2-GP

1 2

DY

MESO_U1
MESO_U3

SMB_CLK_VGA

SMB_DATA_VGA

DGPU_PWROK_R

TP7918

TOPAZ_OCP[85]

Main Func = dGPU

3D3V_VGA_S0

R7903 5K1R2F-2-GP

D D

C C

12

DY

1 2

R7902 1KR2F-L1-GP

OPS

RN7904

23
1

4

OPS

SRN10KJ-5-GP

SML1_SMBCLK[18,24,79]

SML1_SMBDATA[18,24,79]

GPU_PWR_LEVEL[24]

Pre-PWROK METAL VID CODES

SVC SVD Output Vol tage

0

0

AMD suggestion

VGA_SVC[79,85]
VGA_SVD[79,85]

B B

VGA_SVD[79,85]
VGA_SVT[85]
VGA_SVC[79,85]

1 0

1

R7919 0R0402-PAD
R7920 0R0402-PAD

PWR_VGA_CORE_VDDIO

12

R7940

10KR2J-L-GP

DY

12

R7925

10KR2J-L-GP

MESO

SVID

R16

R7919 R7920

XTL_27M_X1_VGA

12

R7901

A A

XTL_27M_X2_VGA

OPS

1MR2J-1-GP

5

1.1

0

1

1.0

0.9

1

0.8

1 2
1 2

12

R7924

MESO

12

R7934

MESO

10KR2J-L-GP

10KR2J-L-GP

JET_SVC
JET_SVD

12

R7923

10KR2J-L-GP

MESO

R7944 0R2J-2-GP
R7945 0R2J-2-GP
R7946 0R2J-2-GP

MESO non-insta ll

12

R7939

10KR2J-L-GP

DY

1 2
1 2
1 2

PWR Sequencing

PR8611 PC8607 / PR8612 PC8612

C7901
SC6D8P50V2CN-DL-GP

1 2

OPS

23

OPS

C7903
SC6D8P50V2CN-DL-GP

1 2

OPS

X7901

4 1

XTAL-27MHZ-159-GP

MESO
MESO
MESO

MESO_SVD
MESO_SVT
MESO_SVC

BALL: AB13, W9, AC14
R16: NC
MESO : VDDC

4

3D3V_VGA_S0

12

R7942

10KR2J-L-GP

DY

Q7903

G

DY

D

S

2N7002K-2-GP

1 2

R7943

OPS

0R2J-2-GP

TP7902

GPU_DPRSLP GPU_DPRSLP_R

1

1 2

R7922

OPS

10KR2J-L-GP

1 2

R7911
0R2J-2-GP

1 2

R7913
0R2J-2-GP

3D3V_VGA_S0

12

DY

DY

TP7905
TP7906
TP7901

TP7903
TP7923

TP7910
TP7919
TP7920

TP7907
TP7908
TP7911
TP7912
TP7913

TP7904

R7935

10KR2J-L-GP

DY

12

R7936

10KR2J-L-GP

OPS

0: Enable MLPS, disable GPIO PINSTRAP
1: Disable MLPS, enable GPIO PINSTRAP

4

CLKREQ_PEG#0 [18]

MESO_U1

MESO_U3

PLL_ANALOG_IN

1

BALL: U10,T10,Y9,W10
R16: NC
MESO : VDDC

SMB_DATA_VGA
SMB_CLK_VGA
GPIO_5_AC_BATT

GPIO_8_ROMSO

1

GPIO_9_ROMSI

1

GPIO_10_ROMSCK

1

JET_SVD
GPIO16_VGA

1

GPIO_17_THERMAL_INT

1

GPIO_19_CTF
JET_SVC

GPIO_22_ROMCS#

1

H_VID3

1

H_VID4

1

JTAG_TRST#_VGA

1

JTAG_TDI_VGA

1

JTAG_TCK_VGA

1

JTAG_TMS_VGA

1

JTAG_TDO_VGA

1

TESTEN

PX_EN

1

1

TP7909

1

TP7914

1D8V_VGA_S0

12

OPS

PINs for debug

XTL_27M_X1_VGA
XTL_27M_X2_VGA

XO_IN
XO_IN2

GPU_DPLUS
GPU_DMINUS
MLPS_EN#

13mA

C7904
SC1U10V2KX-1GP

GPU1B

N9

DBG_DATA16

L9

DBG_DATA15

AE9

DBG_DATA14

Y11

DBG_DATA13

AE8

DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC#W6

V6

NC#V6

AC6

NC#AC6

AC5

NC#AC5

AA5

NC#AA5

AA6

NC#AA6

U1

NC#U1

W1

NC#W1

U3

NC#U3

Y6

NC#Y6

AA1

NC#AA1

I2C

R1

SCL

R3

SDA

U6

GPIO_0

U10

NC_GPIO_1

T10

NC_GPIO_2

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

NC_GPIO_7

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

NC_GPIO_11

N5

NC_GPIO_12

N3

NC_GPIO_13

Y9

NC_GPIO_14

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

W10

NC_GPIO_18

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCS#

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQ#

L6

JTAG_TRST#

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC#AF24

AB13

NC_GENERICA

W8

NC_GENERICB

W9

NC_GENERICC

W7

NC_GENERICD

AD10

NC_GENERICE_HPD4

AJ9

NC#AJ9

AL9

DBG_CNTL0

AC14

NC_HPD1

AB16

PX_EN

AC16

NC_DBG_VREFG

PLL/CLOCK

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

SEYMOUR/FutureASIC

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

JET-XT-S3-GP

THERMAL

DVO

GENERAL PURPOSE I/O

FutureASIC/SEYMOUR/PARK

DPA

DPB

DPC

NC_AVSSN#AK26

NC_AVSSN#AJ25

NC_AVSSN#AG25

DAC1

NC_SVI2#AK12

NC_SVI2#AL11
NC_SVI2#AJ11

NC_GENLK_CLK

NC_GENLK_VSYNC

NC_SWAPLOCKA
NC_SWAPLOCKB

DDC/AUX

NC_DDC1CLK

NC_DDC1DATA

NC_DDC2CLK

NC_DDC2DATA

NC_DDCVGACLK

NC_DDCVGADATA

OPS

R_pu (Ω) R_pd (Ω) Bits [3:1]
NC 4750 000
8450 2000 001
4530 2000 010
6980 4990 011
4530 4990 100
3240 5620 101
3400 10000 110
4750 NC 111
Note: 0402 1% resistors are required.

3

2 OF 7

AF2

NC#AF2

AF4

NC#AF4

AG3

NC#AG3

AG5

NC#AG5

AH3

NC#AH3

AH1

NC#AH1

AK3

NC#AK3

AK1

NC#AK1

AK5

NC#AK5

AM3

NC#AM3

AK6

NC#AK6

AM5

NC#AM5

AJ7

NC#AJ7

AH6

NC#AH6

AK8

NC#AK8

AL7

NC#AL7

V4

NC#V4

U5

NC#U5

W3

NC#W3

V2

NC#V2

Y4

NC#Y4

W5

NC#W5

AA3

NC#AA3

NC#AA3

Y2

NC#Y2

J8

NC#J8

Circuit checklist
Test only,
Connect to GND through a 16.2-K resistor.
The resistor is not needed on production.

NC_R

AM26

NC_R

AK26

AL25

NC_G

AJ25

AH24

NC_B

AG25

AH26

NC_HSYNC
NC_VSYNC

NC_RSET

NC_AVDD

NC_AVSSQ

NC_VDD1DI

NC_VSS1DI

NC_AUX1P
NC_AUX1N

NC_AUX2P
NC_AUX2N

NC#AD20
NC#AC20

NC#AE16
NC#AD16

CEC_1

3

TS_A

PS_0

PS_1

PS_2

PS_3

NC_VSYNC

AJ27

AD22

AG24
AE22

AE23
AD23

AM12

MESO_SVD

AK12

MESO_SVT

AL11

MESO_SVC

AJ11

AL13
AJ13

AG13
AH12

AC19

AD19

AE17

AE20

AE19

BALL: AC11,AC13
R16: NC
MESO : VDDC

AE6
AE5

AD2
AD4

AC11
AC13

AD13
AD11

AD20
AC20

AE16
AD16

AC1
AC3

Cap Value (nF) Bits [5:4]
680 00
82 01
10 10
NC 11

#3

PS0 ~ PS3 Setting

R7938
16K2R2F-GP

12

DY

1

TP7922

R7941

4K7R2J-2-GP

12

MESO

R16 : DY
MESO : 上件

PS_0

#3

PS_1

PS_2

PS_3

3D3V_S0

C2615

SC10U6D3V3MX-GP

12

DY

NCT7718_DXP

C

Q7905

GPU T8

E

LMBT3904LT1G-GP

NCT7718_DXN

Layout Note:

Both DXN and DXP routing 10 mil trace width
and 10 mil spacing.

C2614

SC2200P50V2KX-2GP

12

B

GPU T8

GPU thermal sensor

C2616

SCD1U16V2KX-3GP

GPU_T8

12

THM262

1
2
3

GPU_T_CRIT#

NCT7718W-GP

74.07718.0B9

RESET_OUT#[17,24,26]

1 2

R2615
0R0402-PAD

2

3D3V_S0

GPU T8

VDD
D+
D-

ALERT#

T_CRIT#4GND

GPU_T_CRIT_R#

2

SCL
SDA

GPU T8

1 2

R2613 18K7R2F-GP

GPU T8

1 2

R2614 2KR2F-L1-GP

SMB_CLK_THM_R

8

SMB_DATA_THM_R

7

GPU_ALERT#

6
5

Q2605

G

D

GPU T8

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

AMD suggest Aperture Size = 256MB

PS_0

GEN3

PS_1

R7929 cgange to 2K ohm 1/21

PS_2

## PS_3[3-1] => MEM_ID setting, need decide for AMD

R_pu

PS_3

R_pd

GPU_ALERT#

GPU_T_CRIT#

C2617

SCD1U16V2KX-3GP

12

12

DY

DY

PURE_HW_SHUTDOWN# [26,40]

C2618

SML1_SMBCLK[18,24,79]

SCD1U16V2KX-3GP

SML1_SMBDATA[18,24,79]

1

1D8V_VGA_S0

OPS

R_pu

OPS

R_pd

1D8V_VGA_S0

R_pu

R_pd

1D8V_VGA_S0

R_pu

R_pd

1D8V_VGA_S0

VRAM

VRAM

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

Date: Sheet

Date: Sheet

Date: Sheet

11001

12

R7926
8K45R2F-2-GP

12

R7927

2KR2F-L1-GP

12

C7918

DY

SCD082U16V2KX-GP

11000

12

R7928
8K45R2F-2-GP

OPS

12

R7929

2KR2F-L1-GP

12

C7919

DY

SCD68U16V3KX-GP-U

OPS

DY

OPS

12

R7932

3K24R2F-GP

12

R7933

Wednesday, November 08, 2017 10579

Wednesday, November 08, 2017 10579

Wednesday, November 08, 2017 10579

680nF

11000

12

R7930
8K45R2F-2-GP

12

R7931

4K75R2F-1-GP

12

C7920

DY

SCD68U16V3KX-GP-U

680nF

5K62R2F-GP

12

C7921

DY

SCD01U50V2KX-L-GP

6

GPU T8

Q7904
2N7002KDW-GP

079_GPU (4/5) GPIO/STRAP

079_GPU (4/5) GPIO/STRAP

079_GPU (4/5) GPIO/STRAP

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

1

2345

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

3D3V_S0

1

GPU T8

4

23

RN7903
SRN4K7J-8-GP

SMB_CLK_THM_R

SMB_DATA_THM_R

of

of

of

5

4

3

2

1

Main Func = dGPU

20170502

AMD schematic Review need

1D35V_V GA_S0

10uF x 1, 2.2uFx5, 0.1uF x1, 0.01uF x1

1A

12

D D

1D35V_V GA_S0

12

12

C8004

OPS

12

C8005

DY

C8003

OPS

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

C8001

OPS

SC10U6D 3V3MX-GP

12

C8006

DY

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

12

C8009

DY

DY

12

C8031

DY

1D8V_VG A_S0

12

C8007
SCD1U16 V2KX-3GP

12

C8032

DY

12

C8014

DY

SCD01U5 0V2KX-L-GP

12

12

C8033

DY

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

12

C8017
SC1U10V 2KX-1GP

OPS

C8034

OPS

12

C8042

DY

13mA

25mA

C C

Memory phase lock loop power: Dedicated

1D8V_VG A_S0

L8001 MMZ 1005S241C-GP

1D8V_VG A_S0

B B

L8002 BL M15AG121SN-1G P

analogue power in for memory PLLs

1 2

OPS

12

C8043
SC10U6D 3V3MX-GP

OPS

Engine phase loop power: Dedicated analogue
power pin for engine PLL

1 2

OPS

68.00084.921

12

C8053
SC10U6D 3V3MX-GP

OPS

3D3V_VG A_S0

12

C8044
SC10U6D 3V3MX-GP

OPS

SPV18

12

C8054
SC1U10V 2KX-1GP

OPS

12

C8024
SC1U10V 2KX-1GP

OPS

MPV18

12

C8045
SC1U10V 2KX-1GP

OPS

MPV18

90mA

SPV18

75mA

SPV10

100mA

Engine phase loop power: Dedicated digital

0D95V_V GA_S0

A A

power pin for engine PLL

1 2

L8003 BL M15AG121SN-1G P

OPS

68.00084.921

5

12

C8055
SC1U10V 2KX-1GP

OPS

SPV10

12

C8056
SCD1U16 V2KX-3GP

OPS

VGA_COR E

12

C8038

OPS

SC10U6D 3V3MX-GP
SC10U6D 3V3MX-GP
SC10U6D 3V3MX-GP

4

GPU1D

MEM I/O

H13

VDDR1

H16

VDDR1

H19

VDDR1

J10

VDDR1

J23

VDDR1

J24

VDDR1

J9

VDDR1

K10

VDDR1

K23

VDDR1

K24

VDDR1

K9

VDDR1

L11

VDDR1

L12

VDDR1

L13

VDDR1

L20

VDDR1

L21

VDDR1

L22

VDDR1

LEVEL
TRANSLATION

AA20

VDD_CT

AA21

VDD_CT

AB20

VDD_CT

AB21

VDD_CT

I/O

AA17

VDDR3

AA18

VDDR3

AB17

VDDR3

AB18

VDDR3

V12

NC_VDDR4#V12

Y12

NC_VDDR4#Y12

U12

NC_VDDR4#U12

PLL

L8

MPLL_PVDD

H7

SPLL_PVDD

H8

SPLL_VDDC

J7

SPLL_PVSS

JET-XT-S3 -GP

12

12

C8039

OPS

C8040

OPS

12

12

SC10U6D 3V3MX-GP
SC10U6D 3V3MX-GP
SC10U6D 3V3MX-GP

C8041

OPS

C8063

OPS

PCIE

CORE

ISOLATED
CORE I/O

12

C8064

OPS

3

PCIE_PVDD

NC#AB23
NC#AC23
NC#AD24

NC#AE24

NC#AE25

NC#AE26

NC#AF25
NC#AG26

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

POWER

BIF_VDDC
BIF_VDDC

4 OF 7

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

AM30

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
AA12
M11
N12
U11

R21
U21

M13
M15
M16
M17
M18
M20
M21
N20

0.1A

1D8V_VG A_S0

12

C8008

DY

SC1U10V 2KX-1GP

AMD schematic Review need 10uF x 2, 1uFx3, 0.1uF x2

2.5A

12

C8011

OPS

SCD1U16 V2KX-3GP
SCD1U16 V2KX-3GP

AMD ORB 10U x 6

2.2U x 16

12

C8018

OPS

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

NC on JET
AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13

12

C8028

OPS

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

0D95V_V GA_S0

12

12

12

OPS

C8012

OPS

C8019

OPS

C8029

OPS

12

C8002
SC10U6D 3V3MX-GP

12

C8020

OPS

12

C8030

OPS

1.4A

12

C8065
SC1U10V 2KX-1GP

OPS

5A

AMD ORB 10U x 2
1U x 3

0.1U x2

12

12

SCD1U16 V2KX-3GP
SCD1U16 V2KX-3GP

VGA_COR E

C8046

OPS

OPS

C8047

OPS

C8061

C8066

12

SC1U10V2KX-1GP

SC22U6D3V3MX-1-GP

OPS

12

OPS

12

0D95V_V GA_S0

12

SC10U6D 3V3MX-GP
SC10U6D 3V3MX-GP

12

12

C8013

C8015

OPS

OPS

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

LF145M 4.7U x 6
1U x 20

12

12

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

12

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

12

C8048

OPS

C8062

C8021

OPS

12

C8035

OPS

12

C8049

OPS

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

SC1U10V2KX-1GP

2

C8022

OPS

C8036

OPS

LF145M 4.7U x 2
1U x 3

0.1U x 2

12

C8010

DY

C8016

OPS

0D95V_V GA_S0

12

C8057

OPS

VGA_COR E

12

12

12

12

12

C8025

C8023

OPS

OPS

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

12

C8037

C8058

OPS

OPS

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

C8050

OPS

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

Date: Sheet

Date: Sheet

Date: Sheet

12

Wednesd ay, November 08, 201 7 10580

Wednesd ay, November 08, 201 7 10580

Wednesd ay, November 08, 201 7 10580

12

C8026

C8027

OPS

OPS

VGA_COR E

12

12

C8059

C8060

OPS

OPS

12

C8051

C8052

OPS

OPS

SC4D7U6 D3V3KX-GP
SC4D7U6 D3V3KX-GP

VGA_COR E

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

080_GPU (5/5) PWR/GND

080_GPU (5/5) PWR/GND

080_GPU (5/5) PWR/GND

<Project Name>

<Project Name>

<Project Name>

1

of

of

of

5

4

3

2

1

SSID = Vram (GDDR5)

DQA0_0[78]
DQA0_1[78]
DQA0_2[78]
DQA0_3[78]
DQA0_4[78]
DQA0_5[78]
DQA0_6[78]
DQA0_7[78]
DQA0_8[78]
DQA0_9[78]
DQA0_10[78]
DQA0_11[78]
DQA0_12[78]
DQA0_13[78]
DQA0_14[78]

D D

C C

B B

A A

DQA0_15[78]
DQA0_16[78]
DQA0_17[78]
DQA0_18[78]
DQA0_19[78]
DQA0_20[78]
DQA0_21[78]
DQA0_22[78]
DQA0_23[78]
DQA0_24[78]
DQA0_25[78]
DQA0_26[78]
DQA0_27[78]
DQA0_28[78]
DQA0_29[78]
DQA0_30[78]
DQA0_31[78]

DQA1_0[78]
DQA1_1[78]
DQA1_2[78]
DQA1_3[78]
DQA1_4[78]
DQA1_5[78]
DQA1_6[78]
DQA1_7[78]
DQA1_8[78]
DQA1_9[78]
DQA1_10[78]
DQA1_11[78]
DQA1_12[78]
DQA1_13[78]
DQA1_14[78]
DQA1_15[78]
DQA1_16[78]
DQA1_17[78]
DQA1_18[78]
DQA1_19[78]
DQA1_20[78]
DQA1_21[78]
DQA1_22[78]
DQA1_23[78]
DQA1_24[78]
DQA1_25[78]
DQA1_26[78]
DQA1_27[78]
DQA1_28[78]
DQA1_29[78]
DQA1_30[78]
DQA1_31[78]

MAA0_0[78]
MAA0_1[78]
MAA0_2[78]
MAA0_3[78]
MAA0_4[78]
MAA0_5[78]
MAA0_6[78]
MAA0_7[78]
MAA0_8[78]

MAA1_0[78]
MAA1_1[78]
MAA1_2[78]
MAA1_3[78]
MAA1_4[78]
MAA1_5[78]
MAA1_6[78]
MAA1_7[78]
MAA1_8[78]

DDBIA0_0[ 78]
DDBIA0_1[ 78]
DDBIA0_2[ 78]
DDBIA0_3[ 78]

DDBIA1_0[ 78]
DDBIA1_1[ 78]
DDBIA1_2[ 78]
DDBIA1_3[ 78]

CSA0b_0[78]

WEA0b[78]
RASA0b[78]
CASA0b[78]

CSA1b_0[78]

WEA1b[78]
RASA1b[78]
CASA1b[78]

ADBIA0[78]
ADBIA1[78]

CLKA0[78]
CLKA0b[78]
CKEA0[78]

CLKA1[78]
CLKA1b[78]
CKEA1[78]

WCKA0_0[78]
WCKA0b_0[78]
WCKA0_1[78]
WCKA0b_1[78]

WCKA1_0[78]
WCKA1b_0[78]
WCKA1_1[78]
WCKA1b_1[78]

EDCA0_0[78]
EDCA0_1[78]
EDCA0_2[78]
EDCA0_3[78]

EDCA1_0[78]
EDCA1_1[78]
EDCA1_2[78]
EDCA1_3[78]

DRAM_RST[78]

5

1 2

R8111 1KR2J-L2-GP

OPS

1 2

R8110 120R2F-GP

OPS

1 2

R8112 1KR2J-L2-GP

OPS

1D35V_VGA_S0

1D35V_VGA_S0

0510
Follow AMD to remove net
Symbol error for layout NC

MAA0_7
MAA0_1
MAA0_0
MAA0_6
MAA0_8

MAA0_2
MAA0_5
MAA0_4
MAA0_3

ADBIA0
RASA0b
CSA0b_0
CASA0b
WEA0b

CLKA0
CLKA0b
CKEA0

DDBIA0_3
DDBIA0_2
DDBIA0_0
DDBIA0_1

DRAM_RST

SEN_A0
ZQ_A0
MF_A0

WCKA0_1
WCKA0b_1

WCKA0_0 EDCA0_0
WCKA0b_0

VRAM1A

C5

VDD

C10

VDD

OPS

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

VPP/NC#A5
VPP/NC#U5

A10

VREFD

U10

VREFD

H5GQ2H24AFR-T2C-GP

Normal(MF=0) Mirrored(MF=1)

VRAM1B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

H5GQ2H24AFR-T2C-GP

OPS

2 OF 2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

EDC0
EDC1
EDC2
EDC3

4

1 OF 2

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B5

VSS

B10

VSS

D10

VSS

G5

VSS

G10

VSS

H1

VSS

H14

VSS

K1

VSS

K14

VSS

L5

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

A5
U5

DQA0_30

A4

DQA0_28

A2

DQA0_31

B4

DQA0_29

B2

DQA0_24

E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

C2
C13
R13
R2

DQA0_27
DQA0_25
DQA0_26
DQA0_16
DQA0_19
DQA0_18
DQA0_17
DQA0_23
DQA0_21
DQA0_22
DQA0_20
DQA0_4
DQA0_3
DQA0_5
DQA0_2
DQA0_7
DQA0_1
DQA0_6
DQA0_0
DQA0_15
DQA0_8
DQA0_11
DQA0_10
DQA0_14
DQA0_9
DQA0_13
DQA0_12

EDCA0_3
EDCA0_2

EDCA0_1

3

2

0

1

1D35V_VGA_S0

1 2

R8113 1KR2J-L2-GP

OPS

1 2

R8109 120R2F-GP

OPS

1 2

R8114 1KR2J-L2-GP

OPS

1D35V_VGA_S0

1D35V_VGA_S0

VREFC_A1VREFC_A0

0510
Follow AMD to remove net
Symbol error for layout NC

MAA1_0
MAA1_6
MAA1_7
MAA1_1
MAA1_8

MAA1_4
MAA1_3
MAA1_2
MAA1_5

ADBIA1
CASA1b
WEA1b
RASA1b
CSA1b_0

CLKA1
CLKA1b
CKEA1

DDBIA1_2
DDBIA1_3
DDBIA1_1
DDBIA1_0

DRAM_RST

SEN_A1
ZQ_A1
MF_A1

WCKA1_1
WCKA1b_1

WCKA1_0
WCKA1b_0

VRAM2A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

A10

VREFD

U10

VREFD

H5GQ2H24AFR-T2C-GP

VRAM2B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

H5GQ2H24AFR-T2C-GP

3

OPS

VPP/NC#A5
VPP/NC#U5

OPS

1 OF 2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

A5
U5

2 OF 2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

EDC0
EDC1
EDC2
EDC3

0510
Follow AMD Change to 1%

1D35V_VGA_S0

Close to VRAM1

R8101 60D4R2F-GP

R8102 60D4R2F-GP

1D35V_VGA_S0

Close to VRAM2

R8103 60D4R2F-GP

R8104 60D4R2F-GP

1 2

OPS

1 2

OPS

1 2

OPS

1 2

OPS

CLKA0

CLKA0b

CLKA1

CLKA1b

Frame Buffer Patition A-Lower Half

1D35V_VGA_S0

0510
Follow AMD to dummy

C8101

SC1U10V2KX-1GP

VREFC_A0

C8103

SC1U10V2KX-1GP

Place close VRAM2 VDD ba ll

1D35V_VGA_S0 1D 35V_VGA_S0

12

12

C8105

OPS

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

DQA1_18

A4

DQA1_17

A2

DQA1_20

B4

DQA1_21

B2

DQA1_22

E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

C2
C13
R13
R2

DQA1_16
DQA1_23
DQA1_19
DQA1_26
DQA1_31
DQA1_29
DQA1_30
DQA1_27
DQA1_24
DQA1_25
DQA1_28
DQA1_15
DQA1_14
DQA1_13
DQA1_11
DQA1_12
DQA1_10
DQA1_9
DQA1_8
DQA1_0
DQA1_3
DQA1_1
DQA1_2
DQA1_7
DQA1_4
DQA1_6
DQA1_5

EDCA1_2
EDCA1_3
EDCA1_1
EDCA1_0

2

3

1

0

1D35V_VGA_S0

Place close VRAM2 VDDQ ba ll

12

12

C8114

C8113

OPS

OPS

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

1D35V_VGA_S0

Place close VRAM1 VDDQ ba ll

12

12

C8123

C8124

OPS

OPS

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

2

12

DY

12

OPS

0.1uF(X7R)
K0402 ×4

12

C8106

OPS

12

C8115

OPS

12

C8125

OPS

C8107

OPS

OPS

OPS

12

R8105
2K37R2F-GP

12

R8107
5K49R2F-GP

12

12

C8116

OPS

12

C8126

OPS

C8108

OPS

0510
Follow AMD to dummy

SC1U10V2KX-1GP

VREFC_A1

SC1U10V2KX-1GP

Place close VRAM1 VDD ba ll

12

C8109

OPS

1.0uF(X7R)
K0402 ×8

12

12

C8117

OPS

12

C8127

OPS

C8118

OPS

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

1.0uF(X7R)
K0402 ×8

12

C8128

OPS

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

12

C8119

OPS

12

C8129

OPS

1D35V_VGA_S0

12

12

C8102

C8104

12

C8110

OPS

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

12

C8120

OPS

12

C8130

OPS

R8106

DY

2K37R2F-GP

OPS

12

12

R8108

OPS

5K49R2F-GP

OPS

0.1uF(X7R)
K0402 ×4

12

12

C8112

C8111

OPS

OPS

10uF(X5R)
M0603 ×2

12

12

C8121

C8122

OPS

OPS

SC10U6D3V3MX-GP
SC10U6D3V3MX-GP

10uF(X5R)
M0603 ×2

12

12

C8131

C8132

OPS

OPS

SC10U6D3V3MX-GP
SC10U6D3V3MX-GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A2

A2

A2

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017
Date: Sheet

Date: Sheet

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

GPU-VRAM1,2 (1/4)

GPU-VRAM1,2 (1/4)

GPU-VRAM1,2 (1/4)

Vegas SKL/KBL-R

Vegas SKL/KBL-R

Vegas SKL/KBL-R

1

of

of

of

81 105

81 105

81 105

A00

A00

A00

5

4

3

2

1

Main Func = dGPU power

12

12

PR8501

10KR2J-L-GP

PR8502

10KR2J-L-GP

OPS

OPS

0926 Modify PC8502 voltage

1 2

PR8503 10KR2F-L1-GP

3D3V_VGA_S0

D D

DGPU_PWR_EN[20,86]

C C

B B

A A

1D8V_VGA_S0

3D3V_VGA_S0

VGA_SVC[ 79]

TOPAZ_OCP[79]

VGA_SVD[ 79]

PWR_VGA_CORE_VDDIO

VGA_SVT[79]

RB551VM-30TE-17-GP

EN/DEM_VGA[86]

PD8501

K A

DY

PE_GPIO1 is for
turning off PWR IC

PWR_VGA_CORE_VSUM-

OPS

1 2

PC8502 SCD1U25V2KX-1-DL-GP

OPS

1 2

PR8546 0R2J-2-GP

MESO

1 2

PR8505 0R0402-PAD

1 2

PC8503 SC1KP50V2KX-L-1-GP

OPS

1 2

PR8506

OPS

100KR2F-L3-GP

1 2

PR8508

OPS

100KR2F-L3-GP

1 2

PR8509

0R0402-PAD

1 2

PR8511

0R0402-PAD

1 2

PR8512

0R0402-PAD

1 2

PR8513

0R0402-PAD

1 2

PR8514

0R0402-PAD

EN/DEM_VGA

5

OPS

3D3V_S5

12

12

PC8517

SCD22U10V2KX-L1-GP

OPS

PR8539
100KR2J-1-GP

EN/DEM_VGA

PWR_VGA_CORE_VDDIO

PWR_VGA_CORE_UGATE_LX_NB

PWR_VGA_CORE_LGATE_NB

PU8201_36

PU8201_39

32

34

38

40

39

PU8501

VSEN_NB

ISUMP_NB

PWR_VGA_CORE_NTC_NB

PWR_VGA_CORE_IMON_NB PWR_VGA_CORE_UGATE2

PWR_VGA_CORE_SVC

PWR_VGA_CORE_VR_HOT#

PWR_VGA_CORE_SVD

PWR_VGA_CORE_SVT

PWR_VGA_CORE_ENABLE

PWR_VGA_CORE_PWROK

PWR_VGA_CORE_IMON

12

PR8516
133KR2F-GP

OPS

12

PC8518

SCD22U10V2KX-L1-GP

2K61R2F-1-GP

NTC-10K-29-GP-U

1 2

DY

PC8511

OPS

SC1KP50V2KX-L-1-GP

PR8529

PR8533

OPS

PWR_VGA_CORE_EN_R#

EN/DEM_VGA

12

OPS

OPS

VGA_VSUM-_1

12

OPS

PQ8501
2N7002KDW-GP

DY

1

2

3

4

5

6

7

8

9

10

41

100KR2F-L3-GP

12

PR8532

11KR2F-L-GP

DY

12

PC8525
SCD1U25V2KX-GP

6

123 4

NTC_NB

IMON_NB

SVC

VR_HOT#

SVD

VDDIO

SVT

ENABLE

PWROK

IMON

GND

PR8524

12

5

OPS

PC8522

SCD022U25V2KX-DLGP

PQ8206_3

NTC

11

PWR_VGA_CORE_NTC

12

12

OPS

VGA_CORE

ISUMN_NB

ISEN212ISEN1

13

PWR_VGA_CORE_ISEN1

PWR_VGA_CORE_ISEN2

PC8523

SCD1U25V2KX-GP

PR8536

1 2

OPS

1K65R2F-GP

12

DY

PR8545
100R2J-L-GP

35

37

36

FB_NB

COMP_NB

LGATE_NB

PGOOD_NB

ISL62771HRTZ-GP-U

74.62771.033
OPS

ISUMP14ISUMN15VSEN

RTN

16

17

PWR_VGA_CORE_RTN

PWR_VGA_CORE_VSEN

PWR_VGA_CORE_ISUMN

PWR_VGA_CORE_ISUMP

PWR_VGA_CORE_PWROK

PWR_VGA_CORE_PGOOD

4

33

31

BOOT_NB

PHASE_NB

UGATE_NB

PGOOD

FB

COMP

20

18

19

PWR_VGA_CORE_FB

PWR_VGA_CORE_COMP

1 2

PR8530

0R0402-PAD

PC8501
SCD01U50V2KX-L-GP

1 2

OPS

PC8524
SC330P50V2KX-3GP

1 2

DY

1 2

PR8534

0R0402-PAD

5V_S5

PWR_VGA_CORE_BOOT2 PW R_VGA_CORE__BOOT2_1

30

BOOT2

29

UGATE2

PWR_VGA_CORE_PHASE2

28

PHASE2

PWR_VGA_CORE_LGATE2

27

LGATE2

26

VDDP

PWR_VGA_CORE_VDD

25

VDD

PWR_VGA_CORE_LGATE1

24

LGATE1

PWR_VGA_CORE_PHASE1

23

PHASE1

PWR_VGA_CORE_UGATE1

22

UGATE1

PWR_VGA_CORE_BOOT1

21

BOOT1

PWR_VGA_CORE_PGOOD

SC180P50V2JN-1GP

12

PR8528

32K4R2F-1-GP

DY

3D3V_VGA_S0

12

PR8518
1KR2J-1-GP

OPS

12

PC8512
SC100P50V2JN-3GP

OPS

PC8514

OPS

12

OPS

PWR_VGA_CORE_FB2_R PWR_VGA_CORE_COMP_1

12

PC8515
SC330P50V2KX-3GP

PR8531 10R2J-L-GP

VGA_VDD_RUN_FB_L

VGA_VDD_RUN_FB_H

PR8535 10R2J-L-GP

1 2

PR8544

0R0402-PAD

PWR_DCBATOUT_VGA_CORE2

DCBATOUT PWR _DCBATOUT_VGA_CORE1DCBATOUT

PG8501

1 2

GAP-CLOSE-PWR

PG8502

1 2

GAP-CLOSE-PWR

PG8503

1 2

GAP-CLOSE-PWR

PG8504

1 2

GAP-CLOSE-PWR
PG8505

1 2

GAP-CLOSE-PWR

PG8506

1 2

GAP-CLOSE-PWR

5V_S5

PR8523

OPS

301R2F-GP

PR8525

1 2

OPS

1K13R2F-1-GP

PR8527

1 2

OPS

2KR2F-L1-GP

VGA_CORE

3

PC8507
SCD22U25V3KX-GP

1 2

OPS

PC8510
SCD22U25V3KX-GP

1 2

OPS

DGPU_PWROK [19,24,79]

PWR_VGA_CORE_FB_R

12

PWR_VGA_CORE_VSEN

PR8510

1R2F-GP

12

OPS

PC8509 SC1U10V2KX-1GP

PC8513
SC1KP50V2KX-L-1-GP

1 2

OPS

SC330P50V2KX-3GP

PWR_VGA_CORE_UGATE2

PWR_VGA_CORE_PHASE2

PWR_VGA_CORE_LGATE2

PR8507

1 2

OPS

2D2R3F-L-GP

PR8515

1 2

OPS

2D2R3F-L-GP

1 2

0R0402-PAD

1 2

OPS

1 2

OPS

PR8520

PWR_VGA_CORE__BOOT1_1

PR8526

1 2

OPS

33KR2F-GP

1

TP8501

1

TP8502

PG8511

1 2

GAP-CLOSE-PWR

PG8512

1 2

GAP-CLOSE-PWR
PG8513

1 2

GAP-CLOSE-PWR

PG8514

1 2

GAP-CLOSE-PWR
PG8515

1 2

GAP-CLOSE-PWR
PG8516

1 2

GAP-CLOSE-PWR

1 2

PC8508 SC1U10V2KX-1GP

OPS

1 2

OPS

PC8516

1 2

OPS

1st source: 075.06994.0037
2nd source: 075.00998.0073

PU8502

FDMS3600-02-RJK0215-COLAY-GP

1

65 BOM

9

8

2
3
4
10

7
6
5

ZZ.00215.037

PWR_VGA_CORE_UGATE1

PWR_VGA_CORE_PHASE1

PWR_VGA_CORE_LGATE1

PWR_VGA_SNUB1

SC330P50V2KX-3GP

PWR_VGA_CORE_ISUMP

PWR_VGA_CORE_ISEN1

PWR_VGA_CORE_VSUM-

PWR_VGA_CORE_ISEN2

PR8541

2D2R3J-2-GP

PC8506

12

DY

12

DY

PR8517

1 2

OPS

3K65R2F-1-GP

PR8519
10KR2F-L1-GP

1st source: 075.06994.0037
2nd source: 075.00998.0073

PU8504

FDMS3600-02-RJK0215-COLAY-GP

1

9

8

ZZ.00215.037

PR8542

2D2R3J-2-GP

PWR_VGA_SNUB2

PC8533

SC330P50V2KX-3GP

DY

PWR_VGA_CORE_ISUMP

PWR_VGA_CORE_ISEN2

PWR_VGA_CORE_VSUM-

PWR_VGA_CORE_ISEN1

2
3
4
10

7
6
5

12

DY

12

PR8537

1 2

OPS

3K65R2F-1-GP

PR8538
10KR2F-L1-GP

1 2

OPS

PR8540

PR8543 10KR2J-L-GP

2

PU8505

FDMS3600-02-RJK0215-COLAY-GP

1

9

65 BOM

8

ZZ.00215.037

PL8502

OPS

1 2

IND-D33UH-7-GP-U

68.R3310.201

PG8509

1 2

PWR_VGA_CORE_PH2

GAP-CLOSE-PWR-3-GP

1 2

OPS

1R2F-GP

1 2

OPS

PG8510

2
3
4
10

7
6
5

GAP-CLOSE-PWR-3-GP

PU8503

FDMS3600-02-RJK0215-COLAY-GP

2
3

1

4
10

9

7
6

8

5

ZZ.00215.037

PL8501

1 2

GAP-CLOSE-PWR-3-GP

IND-D33UH-7-GP-U

68.R3310.201

PG8507

1 2

PWR_VGA_CORE_PH1

1 2

OPS

OPS

1 2

PR8521 1R2F-GP

1 2

PR8522 10KR2J-L-GP

OPS

PC8520

SC4D7U25V5KX-L2-GP

12

OPS

OPS

VGA_CORE

79.33719.20C

1 2

PWR_VGA_CORE_VO2

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A2

A2

A2

Date: Sheet

Date: Sheet

Date: Sheet

PC8526

SC4D7U25V5KX-L2-GP

12

OPS

OPS

OPS

PG8508

1 2

PWR_VGA_CORE_VO1

PC8532

SC4D7U25V5KX-L2-GP

PC8519

12

OPS

SC10U25V5KX-L-GP

12

OPS

PC8534

12

12

PT8508

SE330U2VDM-4-GP

OPS

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

PWR_DCBATOUT_VGA_CORE1

PC8527

SC4D7U25V5KX-L2-GP

12

GAP-CLOSE-PWR-3-GP

PWR_DCBATOUT_VGA_CORE2

1

OPS

2

12

SC22U6D3V3MX-1-GP

OPS

Flash/RTC

Flash/RTC

Flash/RTC

Turis/Vegas KBL-R

Turis/Vegas KBL-R

Turis/Vegas KBL-R

1

PC8529

PC8528

SC10U25V5KX-L-GP

12

12

OPS

OPS

TDC=34A
OCP<??A

VGA_CORE

PT8506

SE330U2VDM-4-GP

OPS

OPS

12

79.33719.20C

79.33719.20C

PC8531

SC10U25V5KX-L-GP

PC8521

SCD1U25V2KX-GP

12

OPS

PC8535

SC22U6D3V3MX-1-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SC10U25V5KX-L-GP

PC8530

SCD1U25V2KX-GP

12

OPS

PT8507

SE330U2VDM-4-GP

12

of

of

of

85 105

85 105

85 105

A00

A00

A00

5

Main Func = dGPU

4

3

2

1

3D3V_S0 to 3D3V_VGA_S0 Transfer

PC8603

SCD1U16V2KX-3GP

OPS

DGPU_PWR_EN[20,85]

PC8651

SCD1U25V2KX-GP

PR8673
100KR2J-1-GP

OPS

3D3V_S0

12

PR8606

100KR2J-1-GP

12

PR8619

DY

PR8661
10KR2J-L-GP

3D3V_S5

PWR_1D35V_VCC

OPS

PC8652

SC10U25V5KX-L-GP

12

OPS

12

PR8672

1MR2J-1-GP

OPS

PR8601 0R2J-2-GP

100KR2J-1-GP

12

PC8601

DY

SCD1U16V2KX-3GP

2N7002KDW-GP

1 2

OPS

12

OPS

12

PC8654
SC2D2U10V3KX-L-GP

PR8677
0R2J-2-GP

12

PR8671
0R0402-PAD-1-GP

1 2

DY

S D

3.3V_ALW_1

PQ8604

DGPU_PWR_EN_R

High Active

PC8655

SC1U10V2KX-1GP

PWR_1D35V_VCC

PWR_1D35V_EN
PWR_1D35V_BOOT
PWR_1D35V_PG
PWR_1V35V_ILMT
PWR_1D35V_FB

1 2

DY

ILIM LOW , ILIM=6.5A
ILIM FLOAT , ILIM=9.5A
ILIM HIGH , ILIM=12.5A

PWR_DCBATOUT_1D35V

PG8651

GAP-CLOSE-PWR-3-GP

1 2

PG8652

GAP-CLOSE-PWR-3-GP

1 2

PWR_DCBATOUT_1D35V

3D3V_S5

GAP-CLOSE-PWR-3-GP

3D3V_S5

12

DY

OPS

PG8655

1 2

12

1 2

3D3V_VGA_S0

PC8605

PC8604

D D

C C

B B

12

12

DY

DY

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

DCBATOUT

0D95V_VGA_S0_PG

EN rating 23V
EN Rising Threshold : 0.8V

OPS084.03419.0031

PQ8609
PJA3419-GP

G

5

6

OPS

123 4

12

PC8602

OPS

SCD47U25V3KX-1GP

PWR_1D35V_VCC

3D3V_VGA_S0

25mA

3D3V_VGA discharge

12

PR8609

DY

75R2F-2-GP

3.3V_RUN_VGA_1

0R0603-PAD-1-GP-U

PU8651

OPS

17

VCC

15

BYP

2

IN#2

3

IN#3

4

IN#4

5

IN#5

11

EN

1

BS

9

PG

13

ILMT

14

FB

SY8286RAC-GP

074.08286.0B43

PR8674

1 2

LX#6
LX#19
LX#20

NC#10
NC#12
NC#16

GND
GND
GND
GND

GPU PWR Sequencing

3D3V_VGAS0

=> 0D95V_VGA_S0/1D8V_VGA_S0

=> 1D5V_VGA_S0

=> VGA_CORE

All the ASIC supplies must reach their respective nominal
voltages withing of the start of the ramp-up sequence,
though a shorter ramp-up duration is preferred. The maximum
slew rate on all rails is 50mV/us.

20ms

It is recommended that the 3.3V rail ramp up first.

It is recommended that the 0.95V rail reach at least 90% of its
normal value no later than 2ms from the start of VDDC ramping
up.

PWR_1D35V_BOOT_APWR_1D35V_BOOT

6
19
20

PWR_1D35V_PG

10
12

PWR_1D35V_VCC

16

7
8
18
21

PWR_1D35V_PH

EN/DEM_VGA[85]

PWR_1D35V_EN

PC8656
SCD1U25V2KX-GP

1 2

OPS

PL8651
IND-D68UH-36-GP-U

1 2

68.R681A.10A

GAP-CLOSE-PWR-3-GP

PC8662

SC470P50V2KX-L-GP

D8602

2

OPS

1

BAT54C-12-GP

75.00054.A7D

MagLayer. 6.86 x 6.47 x 3.0mm
DCR: 5~5.5mOhm
Idc :15.5A , Isat : 25A

OPS

PG8653

1 2

PWR_1D35V_FB_A

12

12

PR8675
24K9R2F-L-GP

OPS

OPS

VOUT=0.6*(1+(R1/R2))

12

PR8676
16K5R2F-2-GP

OPS

3.3V_RUN_VGA_1

3

OPS

12

PC8657

12

OPS

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

PC8658

OPS

12

design current = 3.56A

PC8660

PC8659

12

OPS

1D35V_VGA_S0

PC8661

12

DY

1D8V_VGA_S0

0D95V_VGA_EN

SYW232 for 0.95V_S5

3D3V_VGA_S0

12

PR8625
10KR2J-L-GP

OPS

0D95V_VGA_EN

1 2

PR8603
1KR2J-1-GP

0D95V_VGA_EN_R

1D8V_VGA_EN

OPS

PR8621
0R0402-PAD

OPS

PU8601

5

NC#5

OPS

8

SGND

4

PGND

9

PGND

SYW232DFC-GP

74.00232.033

1 2

2

1

1D8V_VGA_EN

12

PC8612
SCD22U10V2KX-L1-GP

3

IN

1

FB

2

PG

6

LX

7

EN

D8601

3

OPS

BAT54C-12-GP

75.00054.A7D

PWR_0D95V_FB
0D95V_VGA_S0_PG
PWR_0D95V_PHASE
0D95V_VGA_EN_R

12

PC8607

DY

SCD1U16V2KX-3GP

3.3V_RUN_VGA_1

1D8V_S5

0926 Modify PC8502 voltage

OPS

PQ8608

G

OPS

S

2N7002K-2-GP

OPS

PC8635

12

D

12

PC8621

SC10U6D3V3MX-GP

SCD1U25V2KX-1-DL-GP

12

OPS

1D8V_VGA_EN#

PWR_0D95V_PVDD

12

PC8622

SC10U6D3V3MX-GP

DY

PL8601

1 2

OPS

IND-1UH-281-GP

PWR_0D95V_FB

Close Pin1

Vo=0.6x(1+R1/R2)
=0.6x(1+30.1/51.1)
=0.953

PR8650
10KR2J-L-GP

1 2

PR8651

OPS

2K2R2J-L1-GP

12

PC8623

SC1U10V2KX-1GP

OPS

12

R1

PR8622
30K1R2F-L-GP

OPS

12

PR8623

OPS

51K1R2F-GP

3D3V_S5

12

PR8624
10KR2J-L-GP

OPS

0D95V_VGA_S0_PG

2015/02/09 modify

400mA

12

PC8634

DY

SC1U10V2KX-1GP

1D8V_VGA_EN_R#

PG8601

GAP-CLOSE-PWR

PG8602

GAP-CLOSE-PWR

OPS

R2

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.B31

3D3V_S5

12

12

PWR_0D95V

12

PC8624

SC22P50V2JN-4GP

OPS

PQ8607
DMP2130L-7-GP

OPS

S

D

D

G

G

Design Current =1.35A

PC8625

PC8626

12

12

SC22U6D3V3MX-1-GP

OPS

1D8V_VGA_S0

12

PC8636

DY

GAP-CLOSE-PWR

GAP-CLOSE-PWR

SC22U6D3V3MX-1-GP

SCD1U16V2KX-3GP

PG8603

1 2

PG8604

1 2

0D95V_VGA_S0

For power down sequence

2015/02/09 modify

A A

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

GPU Discrete Power

GPU Discrete Power

GPU Discrete Power

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

A00

A00

A00

of

86 105Wednesday, November 08, 2017

86 105Wednesday, November 08, 2017

86 105Wednesday, November 08, 2017

5

Main Func = UnusedParts

H1
HOLE335 R178-GP

1

ZZ.00PAD.7F1

D D

H2
HOLE335 R178-GP

1

ZZ.00PAD.7F1

H3
HOLE335 R178-GP

1

ZZ.00PAD.7F1

H4
HOLE335 R178-GP

1

ZZ.00PAD.7F1

H5
HOLE335 R178-GP

1

ZZ.00PAD.7F1

4

H6
HOLE335 R178-GP

1

ZZ.00PAD.7F1

H7
HOLE335 R178-GP

1

ZZ.00PAD.7F1

H8
HOLE335 R178-GP

1

ZZ.00PAD.7F1

H9
HOLE335 R115-GP

1

ZZ.00PAD.D01

3

H10
HOLE335 R115-GP

1

ZZ.00PAD.D01

H11
HT85B85 X925R29-S-GP

1

ZZ.00PAD.D81

H12
HOLE335 R115-GP

1

ZZ.00PAD.D01

2

H13
HOLE335 R115-GP

1

ZZ.00PAD.D01

H14
HT85B85 X925R29-S-GP

1

ZZ.00PAD.D81

H15
HOLE276 R91-GP

1

ZZ.00PAD.CZ1

H16
HT85BE9 5R29-U-5-GP

1

ZZ.00PAD.D31

1

H17
HOLE384 X421R115-GP

1

ZZ.SCREW.681

DCBATOU T

For acoustic noice

AUD_AGN D

12

DY

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC8918

12

12

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9727

12

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

EC8907

12

DY

DY

0512 Deleted HS20502 Changed PN

EC9725

EC9726

12

12

12

DY

DY

EC8909

EC8908

12

EC9730

EC9728

12

12

DY

DY

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

3D3V_S5

12

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9729

EC9731

12

DY

0921 Install0921 Uninstall

EC8916

EC8917

12

EC9706

12

DY

DY

EC9711

12

SC1KP50 V2KX-L-1-GP
SC1KP50 V2KX-L-1-GP

EC9722

EC9723

12

DY

SPR5
SPRING-63-G P

1

Spring

34.4Y806.001

EC9707

12

EC9714

12

DY

EC9724

12

SPR4
SPRING-43-G P-U

1

Spring

34.15J03.001

EC9709

EC9708

12

12

SC1KP50 V2KX-L-1-GP
SC1KP50 V2KX-L-1-GP
SC1KP50 V2KX-L-1-GP

DY

HS1
STF237R 128H128-3-GP

1

34.4LO45.201

2nd = 34.4 LO45.301

For RF solution DVT1 3/2

3D3V_S0 5V_S0 +V CCGT

FC9704

FC9702

12

DY

EC9710

12

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

1D2V_S3

12

DY

EC8901

12

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC8910

12

DY

12

DY

EC8903

EC8902

12

12

DY

EC8911

EC8912

12

12

SCD1U25V2KX-GP

FC9703

FC9707

FC9706

12

12

DY

SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP

EC8904

12

DY

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC8913

12

DY

DY

12

12

1D35V_V GA_S0

FC9708

12

EC8905

DY

EC8914

EC8906

12

EC8915

12

DY

12

DY

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

SPR1
SPRING-63-G P

1

Spring

34.4Y806.001

SPR2
SPRING-63-G P

1

Spring

34.4Y806.001

SPR3
SPRING-63-G P

1

Spring

34.4Y806.001

Main Func = EMI & RF Capacitors

Mind the voltag e rating of th e caps.

C C

DCBATOU T

EC9702

EC9701

12

DY

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9712

12

DY

B B

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

5V_S0

EC9718

12

DY

EC9703

12

12

EC9713

EC9715

12

12

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9719

EC9720

12

12

EC9704

12

12

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

0921 Uninstall

EC9716

12

12

EC9721

12

EC9705

EC9717

12

0927 Change acoustic solution
1101 Change acoustic solution

12

PT8901

DY

SE33U25 VM-11-GP

EC9744

EC9739

EC8919

DY

12

12

DY

EC8920

12

12

12

OPS

EC9743

12

DY

EC8921

12

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

PT8902
ST100U2 5VDM-1-GP

VGA_COR E

EC9745

SC1KP50V2KX-L-1-GP

EC8922

EC8923

12

EC9746

12

DY

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC8924

12

12

EC9750

12

12

DY

DY

EC8925

EC8926

12

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9752

EC9751

12

DY

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC8927

12

12

DY

EC9753

12

EC8928

SCD1U25 V2KX-GP

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9736

A A

EC9735

12

DY

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9737

12

12

5

12

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

5V_S53 D3V_S0 DCBATOU T

EC9733

EC9738

EC9732

12

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9734

12

12

EC9741

1 2

4

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9742

12

DY

1 2

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9749

EC9747

DY

1 2

SCD1U25 V2KX-GP
SCD1U25 V2KX-GP
SCD1U25 V2KX-GP

EC9748

EC9740

12

12

DY

SC1KP50 V2KX-L-1-GP
SC1KP50 V2KX-L-1-GP

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

UNUSED PARTS/EMI Capacitors

UNUSED PARTS/EMI Capacitors

UNUSED PARTS/EMI Capacitors

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Date: Sheet

Date: Sheet

3

2

Date: Sheet

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wednesd ay, November 08, 201 7

Wednesd ay, November 08, 201 7

Wednesd ay, November 08, 201 7

89 105

89 105

89 105

1

of

of

of

A00

A00

A00

5

SSID = TPM

4

3

2

1

3D3V_S5 3D3V_TPM

3D3V_TPM

3D3V_S0

modify from 3D3V_S5_PCH to 3D3V_S5
20160909(DVT2)

R9147
0R0402-PAD-2-GP

D D

C C

B B

??? RTC Gen9 power

R1

TPM_65x

1 2

R9149
0R2J-2-GP

1 2

R9150
0R0402-PAD-2-GP

R2

0523 Change to 0402
0920 Change to Pad

TPM IC

NPC65x

NPC75x

3D3V_S5 3D3V_TPM_1

1 2

Mounted

R1

R2 R1

1 2

R9143
0R0402-PAD-2-GP

C9107

TPM

12

TPM

SCD1U16V2KX-3GP

TPM_65x

Unmounted

R2

C9106

SC4D7U6D3V3KX-GP

12

12

TPM

TPM_VDD14

C9111

SCD1U16V2KX-3GP

TPM

C9114

SC2200P50V2KX-2GP

12

DY

12

0512 Deleted C9110
0523 Modify C9113

C9113

12

12

DY

modify 0.1u->4.7u

20160627(DVT1)

C9108

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

C9116

C9115

SC2200P50V2KX-2GP

TPM

SCD1U16V2KX-3GP

12

3D3V_S0 3D3V_S5

R9145

0R0402-PAD-2-GP

12

12

R9146

0R2J-L-GP

DY

C9112

C9109

SC4D7U6D3V3KX-GP

12

TPM

PIRQA#

PLT_RST# PLT_RST#_Q_TPM2

TPM

R9144
0R0402-PAD-2-GP

R9152
0R0402-PAD-2-GP

R9136
0R0402-PAD-2-GP

SCD1U16V2KX-3GP

12

1 2

1 2

1 2

TPM

+UZ12_TPM

TPM_VDD14

TPM_VSB

SPI_SO_ROM_TPM2
SPI_SI_ROM_TPM2
SPI_IRQ#_TPM2

SPI_CLK_ROM_TPM2
SPI_CS2#_R_TPM2
SERIRQ_TPM

12

R9141
10KR2J-L-GP

SPI_CS_ROM_N2[18]

SPI_SO_ROM[18,25]

SPI_SI_ROM[18,25]

SPI_CLK_ROM[18,25]

U9103

8

VDD

14

VHIO

22

VHIO

1

VSB

24

LAD0/MISO

21

LAD1/MOSI

18

LAD2/SPI_IRQ#

15

LAD3

17

LRESET#/SPI_RST#/SRESET#

19

LCLK/SCLK

20

LFRAME#/SCS#

27

SERIRQ

28

LPCPD#

4

PP

5

TEST

NPCT750JAAYX-GP

071.00750.0003

3D3V_TPM

R9130 0R0402-PAD
R9132 33R2J-2-GP

TPM

R9133 33R2J-2-GP

TPM

R9138 33R2J-2-GP

TPM

SDA/GPIO0

GPIO1/SCL

GPX/GPIO2

TPM

GPIO3/BADD

RESERVED#12

NC#2

NC#7
NC#10
NC#11
NC#25
NC#26
NC#31

GND
GND
GND
GND
GND

<Core Design>

<Core Design>

<Core Design>

CLKRUN#/GPIO4/SINT#

1 2

R9140

TPM

10KR2J-L-GP

1 2
1 2
1 2
1 2

29
30
3
6
13

12

2
7
10
11
25
26
31

9
16
23
32
33

TPM_GPIO0

TPM_GPIO2

TPM_GPIO4

SPI_CS2#_R_TPM2
SPI_SO_ROM_TPM2
SPI_SI_ROM_TPM2
SPI_CLK_ROM_TPM2

1 2

R9121

TPM

10KR2J-L-GP

1 2

R9120

DY

10KR2J-L-GP

1 2

R9122

DY

2K2R2J-L1-GP

3D3V_S0

SPI_CS2#_R_TPM2

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

PLT_RST#[17,31,55,61,63,76]

PIRQA#[16]

5

4

3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet

Date: Sheet

Date: Sheet of

2

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

TPM

TPM

TPM

91 105Wednesday, November 08, 2017

91 105Wednesday, November 08, 2017

91 105Wednesday, November 08, 2017

of

of

1

A00

A00

A00

5

SSID = Finger Print

4

3

2

1

1 2

D D

C C

USB_CPU_PN8[16]

USB_CPU_PP8[16]

3D3V_S0

12

12

FPR

0524 Follow new FPR pin define

R9202

0R0402-PAD-2-GP

C9202

SC1U10V2KX-1GP

FPR

C9201

12

R9203 0R0402-PAD-2-GP

1 2

R9204 0R0402-PAD-2-GP

FPR1

8
6

USB_PP8_C
USB_PN8_C

FP_PWR

SCD1U16V2KX-3GP

5
4
3
2

1
7

HRS-CON6-15-GP

020.K0237.0006

2nd = 020.K0002.0006

FPR

USB_PN8_C

USB_PP8_C

For EMI Reserved

ED9201

1

USB_PP8_C

B B

DY

EC9201

12

USB_PN8_C

SC22P50V2JN-4GP

DY

EC9202

SC22P50V2JN-4GP

12

I/O1

2

GND

I/O23I/O3

DY

I/O4

VDD

USB_PN8_CUSB_PP8_C

6

5

4

3D3V_S0

AZC099-04S-2-GP

075.09904.0A7C

Layout Note:

close to FPR1

FP_PWR

AFTP8902AFTE14P-GP
AFTP8903AFTE14P-GP
AFTP8904AFTE14P-GP

A A

5

1

USB_PN8_C

1

USB_PP8_C

1

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A4

A4

A4

Date: Sheet

Date: Sheet

4

3

Date: Sheet

2

Finger Print

Finger Print

Finger Print

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

A00

A00

A00

92 102Wednesday, November 08, 2017

92 102Wednesday, November 08, 2017

92 102Wednesday, November 08, 2017

of

of

of

1

5

D D

PCH_JTAG_TMS

test point

4

3

2

1

XDP_TMS

PCH_JTAG_TDI

test point

XDP_TDI

XDP_TCLK

test point

XDP_TCK_JTAGX

XDP_TDO_CPU

test point

PCH_JTAG_TDO

C C

B B

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

Debug (XDP debug)

Debug (XDP debug)

Debug (XDP debug)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet of

2

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wednesday, November 08, 2017

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

99 105

99 105

99 105

of

of

1

A00

5

4

3

2

1

CLK Block Diagram

Intel CPU

D D

DDR4 DIMM1

DDR4 DIMM2

C C

VRAM1

VRAM2

VRAM3

VRAM4

CK

CK#

CK

CK#

CK

CK#

CK

CK#

CLKA0

CLKA0b

CLKA0

CLKA0b

CLKA1

CLKA1b

CLKA1

CLKA1b

GPU

AMD R17-M1-30

CLKA0

‧

‧

‧

CLKA0#

CLKA1

‧

CLKA1#

PEX_REFCLK#

XTAL_IN

XTAL_OUT

CK0_T

CK0_C

CK1_T

CK1_C

CK0_T

CK0_C

CK1_T

CK1_C

M_A_CLK0

M_A_CLK0#

M_A_CLK1

M_A_CLK1#

M_B_CLK0

M_B_CLK0#

M_B_CLK1

M_B_CLK1#

PEG_CLK_CPU#

PEG_CLK_CPU

27MHZ_IN

27MHZ_OUT

X7901
27MHz

DDR0_CKP[0]

DDR0_CKN[0]

DDR0_CKP[1]

DDR0_CKN[1]

DDR1_CKP[0]

DDR1_CKN[0]

DDR1_CKP[1]

DDR1_CKN[1]

CLKOUT_PCIE_N0

CLKOUT_PCIE_P0PEX_REFCLK

KBL-R

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

PEG_CLK1_CPU

PEG_CLK1_CPU#

PEG_CLK2_CPU

PEG_CLK2_CPU#

HDA_BITCLK /
HDA_CODEC_BITCLK

LANXIN

X3001
25MHz

LANXOUT

HDA_BITCLK_CODEC_R

R2723

22R2J

REFCLKP0

REFCLKN0

WLAN
NGFF

LAN
RTL8106E/RTL8111G

REFCLK_P

REFCLK_N

CKXTAL1

CKXTAL2

Audio

BIT-CLKHDA_BCLK/I2S0_SCLK

Realtek
ALC3223

B B

X1901

32.768KHz

X1801
24MHz

A A

5

4

RTC_X1

RTC_X2

XTAL24_IN

XTAL24_OUT

RTCX1

RTCX2

XTAL24_IN

XTAL24_OUT

GPP_A9/CLKOUT_LPC0/ESPI_CLK

3

ESPI_CLK_CPU

R1804

15R2F

2

ESPI_CLK

KBC
MEC1416-NU-D0-GP

GPIO034/PCI_CLK/ESPI_CLK

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

A2

A2

A2

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

CLK Block Diagram

CLK Block Diagram

CLK Block Diagram

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

100 105W ednesday, November 08, 2017

100 105W ednesday, November 08, 2017

1

100 105W ednesday, November 08, 2017

A00

A00

A00

of

of

of

5

4

3

2

1

Change notes -

DATE

D D

C C

Page

OWNERDATE VERSON Modify List

B B

<Core Design>

<Core Design>

A A

5

4

3

2

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Taipei Hsien 221, Taiwan, R.O.C .

Title

Title

Title

Change History

Change History

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A3

A3

A3

Date: Sheet of

Wednesd ay, November 08, 201 7

Date: Sheet of

Wednesd ay, November 08, 201 7

Date: Sheet of

Wednesd ay, November 08, 201 7

Change History

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

1

101

101

101

105

105

105

A00

A00

A00

KBL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform]

5

D D

C C

B B

4

3

POWER UP SEQUENCE DIAGRAM (NON Deep Sx Platform)

3D3V_AUX_S5

1

TBD

GPIO36

3D3V_S5_PCH

VIN

VCI_OUT/
GPIO036

VCI_IN0#/
GPIO163

VCI_OVRD_IN/
GPIO164

Delay 10ms

GPIO57

GPIO44

GPIO01

3V_5V_POK

SIO_SLP_S4#

SIO_SLP_S4#

EN1

R2446

AND

f

3

3

c d eb fa g

d

3V_5V_EN

EN2

3D3V_S5

TPS51225RUKR

DC/DC

(3.3V/5V)

5V_S5

Page45

f

3V_5V_POK

Page24

GPIO34

GPIO66

f

GPIO20

2

KBC
MEC1416

8b

GPIO107

PM_SUSWARN#

GPIO02

GPIO81

8c

GPIO141

Page24

ALL_SYS_PWRGD assert,
delay 100ms; SYS_PWROK asser t.

PWR_VDDQ_PG

6

VR_RDY

PWR_DCBATOUT_1D0V

VIN

EN

AOZ2262QI

VCCPRIM_CORE

1D0V_PWR

0R

1D0V_S5

5V_S5

Vin

VDD

EN

APE8939GN3

3D3V_S5

Vin

EN

APL5930KAI

Red: Power Rail

Orange: Output from KBC

Light Blue: Output from CPU

DC

Battery

a

Page43

AC

Adapter in

a

Page43

It is recommended that SYS_P WROK be asserted after
both PWROK assertion and pro cessor core VR PWRGD assertion.

3V_5V_POK

f

1D8V_S5_PWROK

g

1D0V_S5_PWRGD

g

3D3V_S5

5V_S5

Vin

3V_5V_POK

EN

f

APL5930KAI

1D8V_S5

0R

SI7121DN-T1-GE3

BT+

V8P10-5300M3-86A

+DC_IN

AON7403

Page43

AD+

Charger

ISL88739

Page44

ACOK

PWR_CHG_ACOK

b

PR4474

Page44

RSMRST#_KBC: Delay 10 ms aft er receive
RSMRST_PWRGD# and PM_SLP_SUS #.

ALL_SYS_PWRGD assert,
delay 10ms; PCH_PWROK assert.

EN SW

PCH_ALW_ON

SY6288C10CAC

RSMRST_PWRGD#

0R 0402

h

0R 0402

0R 0402

DY

VCNTL

1D8V_S5

Vout

1D8V_S5_PWROK

PGOOD

Page54

g

+V1.8A_SIP

h

7

3D3V_S5

Vin

(DS3)

Page43

Page43

d

3V_5V_EN

c

KBC_PWRBTN#

RSMRST_PWRGD#

RSMRST#_KBC

ALL_SYS_PWRGD

PM_SLP_S4#

3

PM_SLP_S3#

4

Page41

DCBATOUT

R4009

ALWON

bACOK_IN

4b 765 8a8 8b 91 102 4a43a

e

3

SIO_SLP_S4#

SLP_S4#

DPWROK

The DSW rails must be stable for at least
10 ms before DSW_PWROK is as serted to PCH.

PCH_RSMRST#

DSW_PWROK

PM_RSMRST#

RSMRST#

SIO_PWRBTN#

PWRBTN#

ALL_SYS_PWRGD and VR_RDY ass ert,
delay 10ms; PCH_PWROK assert .

RESET_OUT#

PCH_PWROK

SUSWARN#

i

SUSACK#

SYS_PWROK

SYS_PWROK

SVID Transanctions

IMVP8

CPU SVID Rails
SA/Core/GT/GTx

VR_ON

VR_READY

8a

1D0V_PWR

LX

1D0V_S5_PWRGD

PGOOD

g

Page53

SW

+V1.00U_CPU(VCCST)

Page40

4a

2D5V_S3

LX

PWR_2D5V_PG

PGOOD

Page54

4b

2

1

h i

5

DDR_VTT_PG_CTRL

SIO_SLP_S3#

DDR_PG_CTL

SLP_S3#

Level
Shifter

SM_PGCNTL_R

KBL-R

SIO_SLP_S0#

SLP_S0#

9

PROCPWRGD

AND

SLP_SUS#

SIO_SLP_S3#

5

4

5

SIO_SLP_S3#

10

PCH_PLTRST#

PLTRST#

8d

H_VCCST_PWRGD

VCCST_PWRGD

EXT_PWR_GATE#

DS3

SIO_SLP_SUS#

1D0V_S5

Vin

APE8939GN3

EN

5V_S5

Vin1

AP22966DC8

EN

EXT_PWR_GATE#

Page40

3D3V_S5

Vin2

Page40

VOut1

VOut2

SW

Level Shifter

e

+VCCIO

0R 0402

5V_S0

3D3V_S0

74LVC1G07GW

6

h

+VCCSTG

PWR_VDDQ_PG

RSMRST_PWRGD#

DY

ALL_SYS_PWRGD

Page17

7

ALL_SYS_PWRGD

AMD GPU Power sequence

3D3V_VGAS0
=> 0D95V_VGA_S0/1D8V_VGA_S0
=> 1D5V_VGA_S0
=> VGA_CORE

20ms
All the ASIC supplies must re ach their respective nomina l
voltages withing of the start of the ramp- up sequence,
though a shorter ramp-up dura tion is preferred. The maxi mum
slew rate on all rails is 50m V/us.
It is recommended that the 3. 3V rail ramp up first.
It is recommended that the 0. 95V rail reach at least 90% of its
normal value no later than 2m s from the start of VDDC ra mping
up.

3D3V_VGA_S0

0D95V_VGA_S0/
1D8V_VGA_S0

1D5V_VGA_S0

For DDR4 power sequence

2D5V_S3

1D2V_S3

0D6V_S0

4b

SIO_SLP_S3#

5

PWR_2D5V_PG

S5

RT8231AGQW

S3

4c

1D2V_S3

0D6V_S0

PWR_VDDQ_PG

PGOOD

Page51

6

VGA_CORE

A A

<Core Des ign>

<Core Des ign>

Title

Title

Title

Size D ocum ent Nu mbe r Rev

Size D ocum ent Nu mbe r Rev

Size D ocum ent Nu mbe r Rev

Date: Sheet of

Date: Sheet

5

4

3

2

1

Date: Sheet

A0

A0

A0

Wednesda y, Novemb er 08, 20 17

Wednesda y, Novemb er 08, 20 17

Wednesda y, Novemb er 08, 20 17

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih ,

21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih ,

21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih ,
Taipei Hsi en 221 , Taiwa n, R.O.C.

Taipei Hsi en 221 , Taiwa n, R.O.C.

Taipei Hsi en 221 , Taiwa n, R.O.C.

Power Sequence

Power Sequence

Power Sequence

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

102

of

102

of

102

105

105

105

A00

A00

A00

5

4

3

2

1

Adapter

Battery

D D

DCBATOUT

Charger

ISL88739HRZ

BT+

TPS51225RUKR

+VCCGT

VR_EN

EN

46

ISL95808HRZ

4748 50

VCC_CORE

GTX_CORE

0 ohm0 ohm

GT_CORE

EN/DEM_VGA

2D5V_PWROK

RT8231AGQW

44

0D6V_S0 1D2V_ S3

EN(S5)
EN(S3)

51

SM_PGCNTL

ISL62771HRTZ

VGA_CORE

EN

SY8288RAC-GP AOZ2262QI-10

86

1D35V_VGA_S0

0D95V_VGA_S0_PG

EN

86

CSD97396Q4M

ISL95859AHRTZ

CSD97396Q4M

+VCCSA

0 ohm

3V_5V_EN

EN

45

+VDDQ_CPU_CLK

3V_5V_POK

EN

53

5V_S5 3D3V_S5

LCDVDD

PM_SLP_S3#

EN

3D3V_S0

DGPU_PWR_EN

EN

PJA3419

3D3V_VGA_S0

SIO_SLP_S4#

40

APL5930KAI

EN

51

APL5930KAI

2D5V_S3

1D8V_S5

3V_5V_POK

EN

54

3D3V_VGA_S0

SYW232DFC

0D95V_VGA_S0

EN

86

0 ohm

3D3V_S5_PCH
3D3V_S5_KBC

+VCCPDSW_3P3

PM_LAN_ENABLE

DMP2130L

3D3V_LAN_S5

EN

31

3D3V_VGA_S0

8655

0 ohm

+3V_1D8V_DVDD
VDD_DAC_33
AVCC33
3D3V_WLAN_S0
3D3V_CAMERA_S0

0 ohm

+V1.8A_SIP

DMP2130L

1D8V_VGA_S0

EN

86

APE8939GN3

+V1.00U_CPU

1D0V_S5

40

0 ohm

+VCCPRIM_CORE

APE8939GN3

+VCCIO

41

0 ohm

42

+V1.00A_SIP

USB_PWR_EN#

C C

SY6288DAAC x2

USB20_VCCA
USB30_VCCC

EN

35

5V_S0

PM_SLP_S3#

EN

AP22966DC8

0 ohm

RT9724GB

ODD_PWR_5V
TPAN_VDD
5V_HDMI_S0
5V_HDD_S0
+5V_AVDD
+5V_PVDD

B B

0 ohm

+VCCST_CPU

0 ohm

0 ohm

+VCCSTG

0 ohm

+VCCAPLL_1P0

+VCCMPHYGTAON_1 P0_LS_SIP
+VCCAMPHYPLL_1P 0

A A

<Core Design>

<Core Design>

<Core Design>

Power Shape

Title

Title

Regulator LDO Switch

5

4

3

2

Title

Power Block Diagram

Power Block Diagram

Power Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

103 105W ednesday, November 08, 2017

103 105W ednesday, November 08, 2017

103 105W ednesday, November 08, 2017

of

of

1

of

A00

A00

A00

A

B

C

D

E

PCH SMBus Block Diagram

3D3V_S5_PCH

‧

1 1

GPP_C0/SMBCLK

GPP_C1/SMBDATA

MEM_SMBCLK

MEM_SMBDATA

SRN2K2J-1-GP

‧

‧

3D3V_S5_PCH

‧

SRN2K2J-1-GP

2 2

GPP_C3/SML0CLK

GPP_C4/SML0DATA

SML0_SMBCLK

SML0_SMBDATA

PCH

3D3V_S5_PCH

SRN2K2J-8-GP

3 3

GPP_C6/SML1CLK

GPP_C7/SML1DATA

‧

‧

SMBus Address:0x82/0x83

3D3V_S0

‧

SML1_SMBCLK

‧

SML1_SMBDATA

3D3V_S0

‧

2N7002SPT

0R2J

0R2J

3D3V_VGA_S0

‧

3D3V_S0

KBC SMBus Block Diagram

‧

SRN10KJ-5-GP

SMBus Address:0xA0/0xA1

DIMM 1

‧

‧

PCH_SMBCLK

PCH_SMBDATA

SCL

SDA

SMBus Address:0xA0/0xA1

DIMM 2

PCH_SMBCLK

‧

PCH_SMBDATA

‧

PCH_SMBCLK

‧

PCH_SMBDATA GPIO010/SMB01_CLK/SMB01_CLK18

‧

PCH_SMBCLK

‧

PCH_SMBDATA

‧

SCL

SDA

TPAD

SCL

SDA

LNG2DMTR

SCL/SPC

SDA/SDI/SDO

GPIO007/SMB01_DATA/SMB01_DATA18

MEC1416

PCH_SMBCLK

PCH_SMBDATA

SMBCLK2

SMBDA2

RTD2166

SMB_SCL

SMB_SDA

(Janus Only)

3D3V_VGA_S0

SMBus Address:0x9E/0x9F

‧

SRN4K7J-8-GP

GPIO013/SMB02_CLK/SMB02_CLK18

GPIO012/SMB02_DATA/SMB02_DATA18

SMBus Address:
0x94/0x95/0x96/0x97

dGPU

SMB_CLK_VGA

SMB_DATA_VGA

5V_S0

‧

‧

SMBCLK

SMBDATA

SMBus Address:0x98/0x99

Thermal

SCL

SDL

NCT7718W

GPU T8

GPIO114/PS2_CLK0

GPIO115/PS2_DAT0

CLK_TP_SIO

DAT_TP_SIO

TP_VDD

‧

SRN10KJ-5-GP

‧

‧

3D3V_AUX_KBC

‧

SRN4K7J-8-GP

SMBCLK1

‧

SMBDA1

‧

SRN33J

SRN100J

TouchPad Conn.

TPCLK

TPCLK_C

TPDATA

TPDATA_C

Battery Conn.

PBAT_SMBCLK1

PBAT_SMBDAT1

CLK_SMB

SMBus address:16

DAT_SMB

ISL88739

SCL

SDA

SMBus address:12

‧

SRN2K2J-1-GP

3D3V_S0

‧

GPP_E18/DDPB_CTRLCLK

GPP_E19/DDPB_CTRLDATA

4 4

A

CPU_DP1_CTRL_CLK DDC_CLK_HDMI

‧

CPU_DP1_CTRL_DATA

‧

2N7002DW-1-GP

‧‧

DDC_DATA_HDMI

B

‧

‧

‧

SRN2K2J-1-GP

HDMI CONN

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

C

D

Date: Sheet

SMBUS Block Diagram

SMBUS Block Diagram

SMBUS Block Diagram

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Taipei Hsien 221, Taiwan, R.O.C.

104 105W ednesday, November 08, 2017

104 105W ednesday, November 08, 2017

104 105W ednesday, November 08, 2017

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Thermal Block Diagram

1 1

PCH

SML1CLK/GPIO75

SML1DATA/GPIO74

GPIO012/SMB02_DATA/SMB02_DATA18

2 2

GPIO013/SMB02_CLK/SMB02_CLK18

KBC

3D3V_S5_PCH 3D3V_S0

SML1_CLK

SML1_DATA

0R2J

‧

‧

SMBDA2

SMBCLK2

0R2J

2N7002

‧

‧

SMB_CLK_VGA_R

SMB_DATA_VGA_R

Put under CPU(T8 HW shutdown)

Thermal
NCT7718

SCL

SDA

SMBCLK

SMBDATA

T_CRIT#

VGA
R17M-M1-30

GPU_T_CRIT#

EN

3V/5V

PURE_HW_SHUTDOWN#

2N7002

Audio Block Diagram

SPKR_L+
SPKR_L-

Codec
ALC3204

AUD_HP1_JACK_R

SLEEVE

RING2

GPIO0/DMIC-DATA12

GPIO1/DMIC-CLK

SPKR_R­SPKR_R+

AUD_HP1_JACK_L

DMIC_DATA_R

DMIC_CLK_R

SPEAKER

HP
COMBO

R2714

0R2J-2-GP

R2716

0R2J-2-GP

MIC

DMIC_DATA

DMIC_CLK

HDMI

MEC1416

GPIO056/PWM3

GPIO050/TACH0

FAN_TACH1

3 3

FAN1_DAC_1

TACH

FAN

VIN

5V

FAN_VCC1

VIN VSET

FAN CONTROL

APL5606AKI

4 4

VOUT

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Thermal/Audio Block Diagram

Thermal/Audio Block Diagram

Thermal/Audio Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

A

B

C

Date: Sheet

D

Vegas SKL/KBL-U

Vegas SKL/KBL-U

Vegas SKL/KBL-U

105 105Wednesday, November 08, 2017

105 105Wednesday, November 08, 2017

105 105Wednesday, November 08, 2017

of

of

of

E

A00

A00

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