Wistron Siberia Schematic

A

Thermal Sensor

4 4

EMC4001

20

SMBus

Clock Generator
CY28547LFXC

SLi Graphic Card

GPU

LCD

DVI Port

TV-Out

3 3

LVDS

DVI-Out
RGB CRT

S-Video
SPDIF

Bridge

GPU

Graphic CONN.

15

SPDIF

SATA (P0)

21

SATA (P2)

21

21

25

INT. Speaker
5W x 2

25

SATA HDD

SATA HDD

ODD Bay

Speaker AMP.

MAX9714

SPDIF

MIC IN

INT. Digital
Array MIC

24

2 2

LINE OUT / HP2

LINE OUT / HP1

Azalia CODEC
STAC 9228

Headphone AMP.

MAX4411 x 2

W to B CONN.

26

24

26

Audio Jack Board

7 in1
CONN

1 1

1394
CONN

USB CONN.x1

7 in1

1394

B to B CONN.

USB2.0 (P0)

23

Ricoh R5C833

7 in 1 card reader

1394

22

IO Board

A

B

C

Siberia Block Diagram

Intel Mobile CPU

4

PCI-e x16

SATA (2)

PATA IDE

AZALIA
PCI BUS

BIOS

SPI FLASH
16Mb

B

Merom 4M
FSB:667/ 800 Mhz

FSB 667/800MHzHOST BUS

Crestline-PM

AGTL+ CPU I/F
DDR Memory I/F

EXTERNAL GRAHPICS

7,8,9,10,11,12

DMI x4 C-LINK0

Intel

ICH8-M

Enhanced

USB 2.0/1.1 ports (10)
PCI Express ports (6)

High Definition Audio

ATA 66/ 100

SATA (3)
LPC I/F

SPI

ACPI 1.1

PCI/PCI BRIDGE

SPI

36

Touch
Pad

Touch Pad Module

16,17,18,19

SPI

LPC

EC
SMSC MEC5025

PS/2

BC

Touch Pad CONN.

PS/2

BC

KBC
SMSC ECE1077

5,6

33

35

DDRII 533/667MHz

DDRII 533/667MHz

PCI Express (6)

USB2.0 (10)

SIO Expander

BC

SMSC ECE5021

C

D

Project code:91.4Q601.001
PCB P/N :48.4Q613.0SC
REVISION :06248-SC

200-PIN DDR2 SODIMM

UNBUFFERED
DDR2 SODIMM
Socket

UNBUFFERED
DDR2 SODIMM
Socket

Power Switch

34

CIR

36

CIR Board

Int. KB

Numpad

13

14

31

PCIe (Lane4)
USB2.0 (P6)

USB2.0 (P4)
PCIe (Lane3)

PCIe (Lane2)

PCIe (Lane5)

PCIe (Lane6)

PCIe (Lane1)
USB2.0 (P9)

USB2.0 (P1)

USB2.0 (P2,P3)

USB2.0 (P8)

USB2.0 (P7)

USB2.0 (P5)

Express Card
Slot 54mm

Mini-Card
WPAN/Robson

Mini-Card

802.11a/g/n
PPU Card

CONN.
BCM5754M

Giga LAN

Mini-Card
WWAN

USB CONN.x1

W to B
CONN.

W to B
CONN.

USB2.0 (P2,P3)

32

USB2.0 (P8)

32

Buletooth 2.1

Camera
Module

D

30

31

30

29

RJ45

27

CONN

SIM

31

23

CONN

USB CONN.x2

Sniffer Board

Gaming LCD
Module

36

35

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet of

E

System DC/DC

TPS51120

OUTPUTSINPUTS

+PWR_SRC

+5V_ALW +5V_SUS
+3.3V_SUS
+3.3V_RTC_LDO

System DC/DC

SN0508073

+PWR_SRC

+1.5V_RUN
+1.25V_RUN

DDR2 DC/DC

SN0508073

+PWR_SRC

+1.8V_SUS
+1.05V_VCCP

LDO

TPS51100

+1.8V_SUS

+0.9V_DDR_VTT

LDO

MAX668

+PWR_SRC

+12V_S

Battery Charger

ISL88731

INPUTS OUTPUTS

+PWR_SRC

+VCHGR

CPU DC/DC

ISL6260C

INPUTS OUTPUTS

+PWR_SRC

28

PCB LAYER

+VCC_CORE

46

44

45

47

47

41

42,43

L1:TOP

31

L2:GND
L3:Signal
L4:Signal
L5:VCC
L6:Signal
L7:GND
L8:BOT

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

A3

A3

A3

Siberia

Siberia

Siberia

150Friday, May 25, 2007

150Friday, May 25, 2007

150Friday, May 25, 2007

E

SC

SC

SC

of

of

A

B

C

D

E

CLOCK GEN CY28547

27M_SS/LCD96_100M SELECTION TABLE
BYTE 10

Bit5 S1 Bit4 S0 Spread Spectrum S[1:0]

00
0

4 4

1
11

BYTE 15
IO_VOUT[2,1,0]

Bit2

Bit1

IO_VOUT2

IO_VOUT1

0
0
00
0
1
11
1
1

SEL2
FSC

1
0
0101

3 3

-0.5%(Default)

-1.0%

1

-1.5%

0

-2.0%

0
0
1

0
0
1
1

SEL1
FSB

Bit0
IO_VOUT0

0
1

11
0

0
1

SEL0
FSA

IO_VOUT[2,1,0]

0.3V

0.4V

0.5V

0.6V

0.7V

0.8V(Default)

0.9V

1.0V

01
01

01

CPU

100M
133M
166M
200M

FSB

X

X
667M
800M

INTEL ICH8-M STRAP PIN

INTEL CRESTLINE STRAP PIN

CFG Strap HIGH 1LOW 0

CFG 5

CFG 9

PCI Express Graphics
Lane Reversal

CFG 16

FSB Dynamic ODT Disabled Enabled

CFG 19

DMI Lane Reserved Normal Operation Lane Reserved

CFG 20

Concurrent SDVO/PCIE

SDVO_CTRL_DATA

SDVO Present

CFG 12
CFG 13

LL(00)
LH(01)
HL(10)
HH(11)

DMI X 2 DMI X 4

Lane Reversal Normal Mode(Lanes

Only PCIE or SDVO
is operation

NO SDVO Card
Present

★

★

★

★

number in order)

★

PCIE and SDVO are
operation simultaneous

SDVO Card Present

XOR/ALL-Z

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation

★

PCIE Routing USB TABLE

LANE1
LANE2
LANE3
LANE4
LANE5
LANE6

MiniCard WWAN
MiniCard WLAN
BT/UWB/Robson
Express Card
PPU card
Giba Bit LOM

PCI ROUTING

INT REQ GNTIDSEL

1394/
MediaCard

AD17

C
D

11

ICH

USB0
USB1
USB2
USB3
USB4
USB5
USB6
USB7
USB8
USB9

Ext Lift Side
Ext Back
Ext Right Side (Top)
Ext Right Side (Bottom)
3rd mini card
Camera
Express Card
BT
Gaming LCD
WWAN

INTEL ICH8-M INTEGRATED
PULL-UPS and PULL-DOWNS

Signal

HDA_SDOUT

HDA_SYNC

GNT2#

GPIO20

GNT3#

2 2

GNT0#
SPI_CS1#

INTVRMEN

LAN100_SLP

SATALED#

SPKR

1 1

TP3

GPIO33/
HDA_DOCK_EN#

Usage/When Sampled Comment

XOR Chain Entrance/
PCIE Port Config 1 bit1,
Rising Edge of PWROK

PCIE Port Config 1 bit0,
Rising Edge of PWROK.

PCIE Port Config 2 bit0,
Rising Edge of PWROK.

Reserved.
Rising Edge of PWROK.

Top-Block Swap Override.
Rising Edge of PWROK.

Boot BIOS Destination
Selection.
Rising Edge of PWROK.

Integrated VccSus1_05
VccSus1_5 and VccCL1_5
VRM Enable/Disable.
Always sampled.

Integrated VccLAN1_05
VccCL1_05 VRM enable
/Disable. Always sampled.

PCIE LAN REVERSAL.Rising
Edge of PWROK.

No Reboot.
Rising Edge of PWROK.

XOR Chain Entrance.
Rising Edge of PWROK.

Flash Descriptor Security
Override Strap
Rising Edge of PWROK.

A

Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK.When TP3 not
pulled low at rising edge of PWROK,sets bit1 of
RPC.PC(Config Registers:offset 224h)

Sets bit0 of RPC.PC(Config Registers:Offset 224h)

Sets bit2 of RPC.PC(Config Registers:Offset 224h)

Weak Internal PULL-DOWN.NOTE:This signal should
not be pull HIGH.

Sampled low:Top-Block Swap mode(inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Enables integrated VccSus1_05,VccSus1_5 and
VccCL1_5 VRM when sampled high

Enables integrated VccLAN1_05,VccCL1_05 VRM
when sampled high

This signal has weak internal pull-up.
set bit27 of MPC.LR(Device28:Function0:Offset D8)

If sampled high, the system is strapped to the
"No Reboot" mode(ICH8M will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)

This signal should not be pull low unless using
XOR Chain testing.

Internal Pull-Up.If sampled low,the Flash Descriptor
Security will be overidden.if high,the Security
measures defined in the Flash Descriptor will be in
effect.
This should only be used in manufacturing
environments

XOR Chain Entrance Strap

ICH_RSVD

A16 swap override strap

PCI_GNT#3 low = A16 swap override enable

BOOT BIOS Strap

integrated VccSus1_05,VccSus1_5,VccCL1_5

SM_INTVRMEN

integrated VccLan1_05VccCL1_05

LAN100_SLP

AZ_DOUT_ICH

tp3

0
0

11

0 1 SPI

0
1
01

high = default

SPI_CS#1 BOOT BIOS LocationPCI_GNT#0

01
11

High=Enable Low=Disable

High=Enable Low=Disable

Description

RSVD

Enter XOR Chain
Normal Operation(default)
Set PCIE port cofig bit1

PCI
LPC(Default)

DEFAULE HIGH

No Reboot Strap

SPKR LOW = Defaule

High=No Reboot

8.2K PULL HIGH

B

C

SIGNAL Resistor Type/Value

HDA_BIT_CLK
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GNT[3:0]
GPIO[20]
LDA[3:0]#/FHW[3:0]#
LAN_RXD[2:0]
LDRQ[0]
LDRQ[1]/GPIO23
PME#
PWRBTN#
SATALED#
SPI_CS1#
SPI_CLK
SPI_MOSI
SPI_MISO
TACH_[3:0]
SPKR
TP[3]
USB[9:0][P,N]
CL_RST0#

D

PULL-DOWN 20K
NONE
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 10K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 15K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 15K
PULL-UP 13K

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet of

Table of Content

Table of Content

Table of Content

Siberia

Siberia

Siberia

SC

SC

250Friday, May 25, 2007

250Friday, May 25, 2007

250Friday, May 25, 2007

E

SC

of

of

A

4 4

B

C

D

E

CPU

ITP Conn.

TCK(PIN 5)

TCK(PIN AC5)

FBO(PIN 11)

3 3

12

R10

R10
51R2F-2-GP

51R2F-2-GP

+1.05V_VCCP

12

R14

R14
51R2F-2-GP

51R2F-2-GP

R13 0R2J-2-GPR13 0R2J-2-GP

R11 22D6R2F-L1-GPR11 22D6R2F-L1-GP

+1.05V_VCCP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1 2

1 2

C28

C28

12

R16

R16
39D2R2F-L-GP

39D2R2F-L-GP

XDP_TDO_FELX

CPURST_FLEX#

12

12

R17

R17
150R2F-1-GP

150R2F-1-GP

ITP1

ITP1

1

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

MLX-CON28-3-GP

MLX-CON28-3-GP

20.K0116.028

20.K0116.028

DY

DY

29

H_RESET# use pull-up Resistor close
ITP connector 500 mil ( max )

30

+1.05V_VCCP use Decoupling Capacitor close
ITP connector 100 mil ( max )

+3.3V_SUS

12

R9

R9
150R2F-1-GP

150R2F-1-GP

ITP_TDI5

ITP_TMS5
ITP_TRST#5

ITP_TCK5

ITP_TDO5
CLK_CPU_ITP#4
CLK_CPU_ITP4

H_RESET#5,7

ITP_BPM#55

2 2

ITP_BPM#45

ITP_BPM#35

ITP_BPM#25

ITP_BPM#15

ITP_BPM#05

ITP_DBRESET#5,18,34

ITP_TDI

ITP_TMS
ITP_TRST#

ITP_TDO
CLK_CPU_ITP#
CLK_CPU_ITP

H_RESET#
ITP_BPM#5

ITP_BPM#4

ITP_BPM#3

ITP_BPM#2

ITP_BPM#1

ITP_BPM#0

12

R15

R15
680R2J-3-GP

680R2J-3-GP

ITP_TCK

12

R12

R12
27D4R2F-L1-GP

27D4R2F-L1-GP

ITP_DBRESET#

1 1

A

B

ITP Debug Conn.

C

<Variant Name>

<Variant Name>

<Variant Name>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

D

Date: Sheet

ITP Debug

ITP Debug

ITP Debug

Siberia

Siberia

Siberia

SC

SC

350Friday, May 25, 2007

350Friday, May 25, 2007

350Friday, May 25, 2007

E

SC

of

of

of

A

+3.3V_ALW

4

1

CKG_SMBDAT33

4 4

CLK_SCLK

CKG_SMBCLK33

3 3

2 3

Enable ITP

+3.3V_RUN

R122 10KR2J-3-GPR122 10KR2J-3-GP

1 2

R135 10KR2J-3-GPR135 10KR2J-3-GP

1 2

Enable TME

2 2

DY

DY

DY

DY

12

12

C657

C657

C661

C661

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

R111 8K2R2J-3-GPR111 8K2R2J-3-GP

1 2

FSC CPU_MCH_BSEL2

R126 8K2R2J-3-GPR126 8K2R2J-3-GP

1 2

1 1

SEL2
FSC

SEL1
FSB

1
0

SEL0
FSA

01
01

0101

SMBus address:D2

RN2

RN2
SRN2K2J-1-GP

SRN2K2J-1-GP

U24

U24

6

5

2N7002DW-7F-GP

2N7002DW-7F-GP

SRN2K2J-1-GP

SRN2K2J-1-GP

R119

CKG_SMBDAT

CKG_SMBCLK

R119

1 2

DY

DY

0R2J-2-GP

0R2J-2-GP

R120

R120

1 2

DY

DY

0R2J-2-GP

0R2J-2-GP

H_STP_CPU#18

CLK_3GPLLREQ#8

PCI_ICH

PCI_PCCARD

H_STP_PCI#18

DY

DY

12

C694

C694

CPU_MCH_BSEL0FSA
CPU_MCH_BSEL1

CPU

100M
133M
166M

01

A

200M

+3.3V_RUN

CLK_SDATA

+3.3V_RUN

4

RN47

RN47

1

2 3

CLK_SDATA

CLK_SCLK

CLK_CPU_BCLK#5
CLK_CPU_BCLK5

CLK_MCH_BCLK#7
CLK_MCH_BCLK7

R529

R529

1 2

475R2F-L1-GP

475R2F-L1-GP

CLK_ICH_48M18
CLK_PCI_ICH18

CLK_PCI_PCCARD22

CLK_PCI_502533

DY

DY

12

C187

C693

C693

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

CPU_MCH_BSEL0 5,8
CPU_MCH_BSEL1 5,8
CPU_MCH_BSEL2 5,8

C187

For wireless performance

DY

DY

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

1

2

34

12

FSB

X

X
667M
800M

SATA_CLKREQ#18
MINI3CLK_REQ#31

LOM_CLKREQ#27
CARD_CLK_REQ#30

MINI2CLK_REQ#31
MINI1CLK_REQ#30

CLK_ICH_48M
CLK_PCI_ICH

CLK_PCI_PCCARD
CLK_PCI_5025

CLK_ICH_14M

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

+3.3V_RUN +3.3V_RUN

12

R115

R115
10KR2J-3-GP

10KR2J-3-GP

DY

DY

12

R116

R116
10KR2J-3-GP

10KR2J-3-GP

DY

DY

B

L34

L34

1 2

BLM21PG600SN-1GP

BLM21PG600SN-1GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

RN46

CLK_CPU_BCLK#
CLK_CPU_BCLK

CLK_MCH_BCLK#
CLK_MCH_BCLK

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

FSA PCI_TPM

RN46

1
2 3

SRN33J-5-GP-U

SRN33J-5-GP-U

RN43

RN43

1
2 3

SRN33J-5-GP-U

SRN33J-5-GP-U

R503 33R2J-2-GPR503 33R2J-2-GP

1 2

R515 33R2J-2-GPR515 33R2J-2-GP

1 2

R527 33R2J-2-GPR527 33R2J-2-GP

1 2

R528 33R2J-2-GPR528 33R2J-2-GP

1 2

CL=20pF±0.2pF
Freq. Tolerance:±30ppm

C670

C670

12

R129

R129

10KR2J-3-GP

10KR2J-3-GP

12

R128

R128

10KR2J-3-GP

10KR2J-3-GP

DY

DY

B

+CK_VDD_MAIN2

12

C679

C679

CPU_BCLK#

4

CPU_BCLK

MCH_BCLK#

4

MCH_BCLK

H_STP_CPU#

SATA_CLKREQ#

MCH_3GPLL_REQ#
LOM_CLKREQ#
CARD_CLK_REQ#

MINI2CLK_REQ#
MINI1CLK_REQ#

CPU_MCH_BSEL1

H_STP_PCI#

X5

X5

CLK_XOUT

1 2

12

X-14D31818M-25GP

X-14D31818M-25GP

PCI_TPM=FCTSEL1

PIN34
FCTSEL1

PIN43
PIN44
PIN47
PIN48

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

Place near C10

12

C668

C668

R121

R121

1 2

1R3F-GP

1R3F-GP

R507

R507

1 2

2R3J-2-GP

2R3J-2-GP

13

CPUC0

14

CPUT0

10

CPUC1

11

CPUT1

24

CPU_STP#

46

CLKREQ1#

26

CLKREQ2#

28

CLKREQ3#

57

CLKREQ4#

29

CLKREQ5#

62

CLKREQ6#

38

CLKREQ7#

71

CLKREQ8#

72

CLKREQ9#

45

FSAFSA
PCI_ICH

PCI_TPM

PCI_PCCARD
PCI_SIO

12

C669

C669
SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

41
37

25
34

33
32
27

R518

R518

1 2

FSB/TEST_MODE
48M/FSA
PCIF0/ITP_SEL

PCI_STP#
PCI4/FCTSEL1

PCI3
PCI2
PCI1/TME

0R2J-2-GP

0R2J-2-GP

DOT96T

DOT96C
LCD100/96T
LCD100/96C

+CK_VDD_A

12

C148

C148

12

C665

C665

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+CK_VDD_REF

+CK_VDD_48

U87

U87

CLK_XTAL_IN

CLK_XTAL_OUT

0

C

12

C644

C644
SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

R99

R99

1 2

2D2R3J-2-GP

2D2R3J-2-GP

36

65

40

7

VDDA

VDD_48

VDD_SRC49VDD_SRC54VDD_SRC

XOUT19XIN

REF122REF0/FSC_TEST_SEL

20

23

CLKREF

FSC

1

27M_NonSpread
27M_Spread
SRCT_0
SRCC_0

C

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

C168

C168

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

39

1

12

18

VDD_PCI30VDD_PCI

VDD_REF

VDD_SRC

VDD_CPU

VTT_PWRGD#/PD

VSS_REF21VSS_CPU15VSS_SRC

VSS_PCI31VSS_PCI35VSS_48

VSS_SRC

4

68

R127 33R2J-2-GPR127 33R2J-2-GP

42

1 2

+3.3V_RUN

12

C658

C658

12

12

C640

C640

R107

R107

DY

DY

R104

R104

DY

DY

SDATA

SCLK

SRCT_1
SRCC_1
SRCT_2
SRCC_2
SRCT_3
SRCC_3
SRCT_4
SCRC_4
SRCT_5
SCRC_5
SRCT_6
SRCC_6
SRCT_7
SRCC_7
SRCT_8
SRCC_8
SRCT_9
SRCC_9

12

C635

C635

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

CLK_PWRGD 18

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

17
16

47
48
50
51
52
53
55
56
58
59
60
61
63
64
66
67
70
69
3
2
6
5

43
44

CLK_ICH_14M 18

C637

C637

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

CLK_PWRGD

PGMODE

1 2

1 2

9

VSS_CPU

SRCT_0/LCD100MT

SRCC_0/LCD100MC

CPUT2_ITP/SRCT_10

CPUC2_ITP/SRCC_10

DOT96T/27M_NSS

DOT96C/27M_SS

VSSA

GND

CY28547LFXCT-GP

CY28547LFXCT-GP

8

73

Solder Thermal Pad to
GND add min 4 vias

CLKREQ PULL HIGH

R451 10KR2J-3-GPR451 10KR2J-3-GP

1 2

R452 10KR2J-3-GPR452 10KR2J-3-GP

1 2

R140 10KR2J-3-GPR140 10KR2J-3-GP

1 2

R139 10KR2J-3-GPR139 10KR2J-3-GP

1 2

R108 10KR2J-3-GPR108 10KR2J-3-GP

1 2

R532 10KR2J-3-GPR532 10KR2J-3-GP

1 2

R93 10KR2J-3-GPR93 10KR2J-3-GP

1 2

D

L9

L9

+CK_VDD_REF+CK_VDD_48

12

2 3
1

2 3
1

2 3
1

2 3
1

2 3
1

2 3
1

2 3
1

2 3
1

1
2 3

1
2 3

1
2 3

12

C179

C179
SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

+CK_VDD_MAIN+CK_VDD_A

12

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+3.3V_RUN

CLK_SDATA
CLK_SCLK

PCIE_PPU
PCIE_PPU#
PCIE_SATA
PCIE_SATA#
PCIE_MINI3
PCIE_MINI3#MINI3CLK_REQ#
MCH_3GPLL
MCH_3GPLL#
PCIE_LOM
PCIE_LOM#
PCIE_EXPCARD
PCIE_EXPCARD#
PCIE_VGA
PCIE_VGA#
PCIE_ICH
PCIE_ICH#
PCIE_MINI2
PCIE_MINI2#
PCIE_MINI1
PCIE_MINI1#
CPU_ITP
CPU_ITP#

Clock Gen.
1st source: ICS ICS9LPR333CKLF (71.09333.A03)
2nd source: Cypress CY28547LFXC (71.28547.003)

BLM21PG600SN-1GP

BLM21PG600SN-1GP

12

C650

C650
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C648

C648

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Pull low to Decide
VTT_PWRGO Low active

PIN9
PGMODE

MINI1CLK_REQ#

MINI2CLK_REQ#

MINI3CLK_REQ#

CARD_CLK_REQ#

SATA_CLKREQ#

CLK_3GPLLREQ#

LOM_CLKREQ#

D

0
1

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

12

C660

C660
SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

+3.3V_RUN+3.3V_RUN

RN44

RN44

SRN33J-5-GP-U

SRN33J-5-GP-U

4

RN41

RN41

SRN33J-5-GP-U

SRN33J-5-GP-U

4

RN38

RN38

SRN33J-5-GP-U

SRN33J-5-GP-U

4

RN35

RN35

SRN33J-5-GP-U

SRN33J-5-GP-U

4

RN34

RN34

SRN33J-5-GP-U

SRN33J-5-GP-U

4

RN33

RN33

SRN33J-5-GP-U

SRN33J-5-GP-U

4

RN32

RN32

SRN33J-5-GP-U

SRN33J-5-GP-U

4

RN31

RN31

SRN33J-5-GP-U

SRN33J-5-GP-U

4

RN30

RN30

4

SRN33J-5-GP-U

SRN33J-5-GP-U

RN36

RN36

4

SRN33J-5-GP-U

SRN33J-5-GP-U

RN39

RN39

4

SRN33J-5-GP-U

SRN33J-5-GP-U

PIN39
DISCRIPTION

VTT_PWRGD#/PD
CKPWRGD/PD#(DEFAULT)

CLK GEN CY28547

CLK GEN CY28547

CLK GEN CY28547

Siberia

Siberia

Siberia

E

CLK_PCIE_PPU 29
CLK_PCIE_PPU# 29

CLK_PCIE_SATA 16
CLK_PCIE_SATA# 16

CLK_PCIE_MINI3 31
CLK_PCIE_MINI3# 31

CLK_MCH_3GPLL 8
CLK_MCH_3GPLL# 8

CLK_PCIE_LOM 27
CLK_PCIE_LOM# 27

CLK_PCIE_EXPCARD 30
CLK_PCIE_EXPCARD# 30

CLK_PCIE_VGA 15
CLK_PCIE_VGA# 15

CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17

CLK_PCIE_MINI2 31
CLK_PCIE_MINI2# 31

CLK_PCIE_MINI1 30
CLK_PCIE_MINI1# 30

CLK_CPU_ITP 3
CLK_CPU_ITP# 3

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SC

SC

450Friday, May 25, 2007

450Friday, May 25, 2007

450Friday, May 25, 2007

E

SC

of

of

of

A

H_D#[63..0]

H_A#[35..3]

H_REQ#[4..0]

H_RS#[2..0]

4 4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_ADSTB#07

3 3

H_ADSTB#17

H_A20M#16
H_FERR#16
H_IGNNE#16

H_STPCLK#16
H_INTR#16
H_NMI#16
H_SMI#16

TP6TPAD28 TP6TPAD28
TP8TPAD28 TP8TPAD28

2 2

TP7TPAD28 TP7TPAD28
TP3TPAD28 TP3TPAD28
TP51TPAD28 TP51TPAD28
TP4TPAD28 TP4TPAD28
TP2TPAD28 TP2TPAD28
TP10TPAD28 TP10TPAD28
TP5TPAD28 TP5TPAD28
TP9TPAD28 TP9TPAD28

H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR#
H_NMI#
H_SMI#

CPU_RSVD01
CPU_RSVD02
CPU_RSVD03
CPU_RSVD04
CPU_RSVD05
CPU_RSVD06
CPU_RSVD07
CPU_RSVD08
CPU_RSVD09
CPU_RSVD10

U76A

U76A

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD#M4

N5

RSVD#N5

T2

RSVD#T2

V3

RSVD#V3

B2

RSVD#B2

C3

RSVD#C3

D2

RSVD#D2

D22

RSVD#D22

D3

RSVD#D3

F6

RSVD#F6

B1

KEY_NC

SKT-CPU478P-GP

SKT-CPU478P-GP

62.10079.021

62.10079.021

1 OF 4

1 OF 4

ADDR GROUP 0

ADDR GROUP 0

ADDR GROUP 1

ADDR GROUP 1

XDP/ITP SIGNALS CONTROL

XDP/ITP SIGNALS CONTROL
THERMAL

THERMAL

PROCHOT#

ICH

ICH

THERMTRIP#

HCLK

HCLK

RESERVED

RESERVED

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

IERR#

LOCK#

RESET#

TRDY#

HITM#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#

TRST#

DBR#

THRMDA
THRMDC

BCLK0
BCLK1

Use old Symbol replace New P/N

original value:MEROM-CPU479P-GP-U

+1.05V_VCCP

R21 200R2F-L-GP

R21 200R2F-L-GP

1 2

DY

DY

R20 56R2J-4-GPR20 56R2J-4-GP

1 2

R30 56R2J-4-GPR30 56R2J-4-GP

1 2

R19 56R2J-4-GPR19 56R2J-4-GP

1 1

1 2

R23 54D9R2F-L1-GP

R23 54D9R2F-L1-GP

1 2

DY

DY

A

H_PWRGOOD

H_THERMTRIP#

EC_CPU_PROCHOT#

H_FERR#

ITP_BPM#4

H_D#[63..0] 7

H_A#[35..3] 7

H_REQ#[4..0] 7

H_RS#[2..0] 7

H1
E2
G5

H5
F21
E1

F1

BR0#

D20
B3

INIT#

H4

C1
F3

RS0#

F4

RS1#

G3

RS2#

G2

G6

HIT#

E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5

TCK

AA6

TDI

AB3

TDO

AB5

TMS

AB6
C20

D21
A24
B25

C7

A22
A21

B

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#

H_IERR#
H_INIT#

H_LOCK#

H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

ITP_DBRESET#

H_THERMDA
H_THERMDC

H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

B

H_ADS# 7
H_BNR# 7

H_BPRI# 7

H_DEFER# 7

H_DRDY# 7
H_DBSY# 7

H_BR0# 7

H_INIT# 16

H_LOCK# 7

H_RESET# 3,7

H_TRDY# 7

H_HIT# 7
H_HITM# 7

ITP_BPM#0 3
ITP_BPM#1 3
ITP_BPM#2 3

ITP_BPM#3 3
ITP_BPM#4 3

ITP_BPM#5 3
ITP_TCK 3
ITP_TDI 3

ITP_TDO 3

ITP_TMS 3
ITP_TRST# 3

ITP_DBRESET# 3,18,34

EC_CPU_PROCHOT# 33

H_THERMTRIP# 20

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

layout note:Zo =55
ohm , 0.5" MAX for
GTLREF

+1.05V_VCCP

12

R28

R28
56R2J-4-GP

56R2J-4-GP

H_THERMDA 20

12

C63

C63
SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

DY

DY

H_THERMDC 20

+1.05V_VCCP

12

R34

R34
1KR2F-3-GP

1KR2F-3-GP

V_CPU_GTLREF

12

R33

R33
2KR2F-3-GP

2KR2F-3-GP

PLACE C66 close to the TEST4 PIN,
make sure TEST4 PIN routing is
reference to GND and away from
other noisy signals

C

R31 1KR2J-1-GP

R31 1KR2J-1-GP

1 2

DY

DY

R298 1KR2J-1-GP

R298 1KR2J-1-GP

1 2

DY

DY

C66 SCD1U10V2KX-4GP

C66 SCD1U10V2KX-4GP

1 2

DY

DY

R299 0R2J-2-GP

R299 0R2J-2-GP

1 2

DY

DY

CPU_MCH_BSEL04,8
CPU_MCH_BSEL14,8
CPU_MCH_BSEL24,8

C

D

2 OF 4

2 OF 4

U76B

U76B

H_D#0

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24

J24

J23
H22
F26
K22
H23

J26
H26
H25

N22
K25
P26
R23

L23
M24

L22
M23
P25
P23
P22
T24
R24

L25
T25
N25

L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

B22
B23
C21

SKT-CPU478P-GP

SKT-CPU478P-GP

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL0
BSEL1
BSEL2

D

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_DSTBN#07
H_DSTBP#07

H_DINV#07

H_DSTBN#17
H_DSTBP#17
H_DINV#17

For the purpose of testability,
route thes signals through a ground
referenced Zo=55ohm trace thatends
in a via that is near a GND via
and is accessible through an
oscilloscope connection.

H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_DSTBN#1
H_DSTBP#1
H_DINV#1

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

TP11TPAD28 TP11TPAD28
TP1TPAD28 TP1TPAD28

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

TEST3
TEST5

E

H_D#32

Y22

D32#
D33#
D34#
D35#

DATA GRP0 DATA GRP1

DATA GRP0 DATA GRP1

D36#
D37#
D38#
D39#
D40#
D41#
D42#

DATA GRP2DATA GRP3

DATA GRP2DATA GRP3

D43#
D44#
D45#
D46#

D47#
DSTBN2#
DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#
DSTBN3#
DSTBP3#

DINV3#

COMP0

MISC

MISC

COMP1
COMP2
COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25

H_DSTBN#2

Y26

H_DSTBP#2

AA26

H_DINV#2

U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23

H_DSTBN#3

AE25

H_DSTBP#3

AF24

H_DINV#3

AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1

H_DPRSTP#

E5

H_DPSLP#

B5

H_DPWR#

D24

H_PWRGOOD

D6

H_CPUSLP#

D7

H_PSI#

AE6

Make COMP[3..0] traces length shorter
than 0.5". Trace should be at least 25
mils away from any other toggling
signal.
COMP 0,2 connect Zo=27.4ohm.
COMP 1,3 connect Zo=55ohm.

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7

Note:
H_DPRSTP# need to daisy chain
from ICH8 to IMVP6 to CPU

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

R297 27D4R2F-L1-GPR297 27D4R2F-L1-GP

1 2

R296 54D9R2F-L1-GPR296 54D9R2F-L1-GP

1 2

R22 27D4R2F-L1-GPR22 27D4R2F-L1-GP

1 2

R24 54D9R2F-L1-GPR24 54D9R2F-L1-GP

1 2

H_DPRSTP# 8,16,42
H_DPSLP# 16

H_DPWR# 7
H_PWRGOOD 16
H_CPUSLP# 7
H_PSI# 42

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU-FSB (1/2)

CPU-FSB (1/2)

CPU-FSB (1/2)

Siberia

Siberia

Siberia

E

SC

SC

550Friday, May 25, 2007

550Friday, May 25, 2007

550Friday, May 25, 2007

SC

of

of

of

A

B

C

D

E

4 4

A11
A14
A16
A19
A23
AF2

B11
B13
B16
B19
B21
B24

C11
C14
C16
C19

C22

3 3

2 2

1 1

C25

D11
D13
D16
D19
D23
D26

E11
E14
E16
E19
E21
E24

F11
F13
F16
F19

F22
F25

G4

G1
G23
G26

H21
H24

J22
J25

K23
K26

L21
L24

M2

M5
M22
M25

N23
N26

A

U76D

U76D

A4

VSS

A8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

B6

VSS

B8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

C5

VSS

C8

VSS
VSS
VSS
VSS
VSS

C2

VSS
VSS
VSS

D1

VSS

D4

VSS

D8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

E3

VSS

E6

VSS

E8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

F5

VSS

F8

VSS
VSS
VSS
VSS
VSS

F2

VSS
VSS
VSS
VSS
VSS
VSS
VSS

H3

VSS

H6

VSS
VSS
VSS

J2

VSS

J5

VSS
VSS
VSS

K1

VSS

K4

VSS
VSS
VSS

L3

VSS

L6

VSS
VSS
VSS
VSS
VSS
VSS
VSS

N1

VSS

N4

VSS
VSS
VSS

P3

VSS

SKT-CPU478P-GP

SKT-CPU478P-GP

4 OF 4

4 OF 4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

0SC

TP131 TPAD28TP131 TPAD28

TP132 TPAD28TP132 TPAD28

TP134 TPAD28TP134 TPAD28
TP133 TPAD28TP133 TPAD28

For NCTF

12

12

12

12

12

Please these inside socket cavity on L8 ( North side Secondary )

+PWR_SRC

Need to add 100uF cap on PWR_SRC for cap singing.
Please this capacitor near +VCC_CORE

B

C45

C45

C43

C43

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C47

C47

C490

C490

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C503

C503

C501

C501

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C52

C52

C44

C44

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

10uF 0805 X5R -> 85 degree C ,
Or better such As X6S and X7R

12

12

C37

C37

C35

C35

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

TC27

TC27

SE100U25VM-14GP

SE100U25VM-14GP

12

C505

C505

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C53

C53

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C498

C498

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C49

C49

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+1.05V_VCCP

12

C58

C58

12

TC28

TC28

SE100U25VM-14GP

SE100U25VM-14GP

12

C491

C491

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C502

C502

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C50

C50

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C504

C504

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C36

C36

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C488

C488

12

C495

C495

12

C54

C54

12

C493

C493

12

12

C51

C51

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C492

C492

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C500

C500

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C57

C57

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C60

C60

C59

C59

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

TC30

TC30

SE100U25VM-14GP

SE100U25VM-14GP

C

12

12

12

12

12

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C48

C48

C489

C489

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C56

C56

C55

C55

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C38

C38

C46

C46

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C494

C494

C497

C497

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

TC1

TC1
SE220U2VDM-8GP

SE220U2VDM-8GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+VCC_CORE +VCC_CORE

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

U76C

U76C

A7

VCC

A9

VCC

A10

VCC

A12

VCC

A13

VCC

A15

VCC

A17

VCC

A18

VCC

A20

VCC

B7

VCC

B9

VCC

B10

VCC

B12

VCC

B14

VCC

B15

VCC

B17

VCC

B18

VCC

B20

VCC

C9

VCC

C10

VCC

C12

VCC

C13

VCC

C15

VCC

C17

VCC

C18

VCC

D9

VCC

D10

VCC

D12

VCC

D14

VCC

D15

VCC

D17

VCC

D18

VCC

E7

VCC

E9

VCC

E10

VCC

E12

VCC

E13

VCC

E15

VCC

E17

VCC

E18

VCC

E20

VCC

F7

VCC

F9

VCC

F10

VCC

F12

VCC

F14

VCC

F15

VCC

F17

VCC

F18

VCC

F20

VCC

AA7

VCC

AA9

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AB9

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

SKT-CPU478P-GP

SKT-CPU478P-GP

3 OF 4

3 OF 4

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCCA
VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

D

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

VCCSENSE

VSSSENSE

VCCSENSE

VSSSENSE

+1.05V_VCCP

+1.5V_RUN

H_VID[6..0] 42

VCCSENSE 42

VSSSENSE 42

R26

R26

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U

R27

R27

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet of

12

C507

C507

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

Layout note:
Place R26 and R27 within 1" of CPU.
Routing VCC_SENSE and VSS_SENSE at

27.4 ohms with 50 mils spacing.

+VCC_CORE

CPU-POWER (2/2)

CPU-POWER (2/2)

CPU-POWER (2/2)

Siberia

Siberia

Siberia

Layout note:
Place C507 near
PIN B26

12

C508

C508
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

650Friday, May 25, 2007

650Friday, May 25, 2007

650Friday, May 25, 2007

E

SC

SC

SC

of

of

A

B

C

D

E

H_D#[63..0]

H_A#[35..3]

H_REQ#[4..0]

H_RS#[2..0]

4 4

3 3

2 2

H_REF Decoupling Crestline
close Crestline 100 mil

+1.05V_VCCP

12

R49

R49
1KR2F-3-GP

1KR2F-3-GP

12

R48

R48
2KR2F-3-GP

1 1

2KR2F-3-GP

H_D#[63..0] 5

H_A#[35..3] 5

H_REQ#[4..0] 5

H_RS#[2..0] 5

12

C71

C71
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1 OF 10

1 OF 10

U84A

U84A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#3,5
H_CPUSLP#5

H_RESET#
H_CPUSLP#

H_REF

E2

H_D#0

G2

H_D#1

G7

H_D#2

M6

H_D#3

H7

H_D#4

H3

H_D#5

G4

H_D#6

F3

H_D#7

N8

H_D#8

H2

H_D#9

M10

H_D#10

N12

H_D#11

N9

H_D#12

H5

H_D#13

P13

H_D#14

K9

H_D#15

M2

H_D#16

W10

H_D#17

Y8

H_D#18

V4

H_D#19

M3

H_D#20

J1

H_D#21

N5

H_D#22

N3

H_D#23

W6

H_D#24

W9

H_D#25

N2

H_D#26

Y7

H_D#27

Y9

H_D#28

P4

H_D#29

W3

H_D#30

N1

H_D#31

AD12

H_D#32

AE3

H_D#33

AD9

H_D#34

AC9

H_D#35

AC7

H_D#36

AC14

H_D#37

AD11

H_D#38

AC11

H_D#39

AB2

H_D#40

AD7

H_D#41

AB1

H_D#42

Y3

H_D#43

AC6

H_D#44

AE2

H_D#45

AC5

H_D#46

AG3

H_D#47

AJ9

H_D#48

AH8

H_D#49

AJ14

H_D#50

AE9

H_D#51

AE11

H_D#52

AH12

H_D#53

AJ5

H_D#54

AH5

H_D#55

AJ6

H_D#56

AE7

H_D#57

AJ7

H_D#58

AJ2

H_D#59

AE5

H_D#60

AJ3

H_D#61

AH2

H_D#62

AH13

H_D#63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

H_ADS#
H_ADSTB#0
H_ADSTB#1

H_BNR#

HOST

HOST

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_HIT#

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

H_ADS#

G12

H_ADSTB#0

H17

H_ADSTB#1

G20

H_BNR#

C8

H_BPRI#

E8

H_BR0#

F12

H_DEFER#

D6

H_DBSY#

C10

CLK_MCH_BCLK

AM5

CLK_MCH_BCLK#

AM7

H_DPWR#

H8

H_DRDY#

K7
E4
C6

H_LOCK#

G10

H_TRDY#

B7

H_DINV#0

K5

H_DINV#1

L2

H_DINV#2

AD13

H_DINV#3

AE13

H_DSTBN#0

M7

H_DSTBN#1

K3

H_DSTBN#2

AD2

H_DSTBN#3

AH11

H_DSTBP#0

L7

H_DSTBP#1

K2

H_DSTBP#2

AC2

H_DSTBP#3

AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_HIT#
H_HITM#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_ADS# 5
H_ADSTB#0 5
H_ADSTB#1 5
H_BNR# 5

H_BPRI# 5

H_BR0# 5

H_DEFER# 5

H_DBSY# 5
CLK_MCH_BCLK 4
CLK_MCH_BCLK# 4

H_DPWR# 5

H_DRDY# 5

H_HIT# 5

H_HITM# 5
H_LOCK# 5

H_TRDY# 5

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_SWING routing Trace width and
Spacing use 10 / 20 mil

H_SWING Resistors and
Capacitors close
Caliistoga 500 mil ( MAX )

From Schematic Design
Checklit v.1201

221 1% pull high 100
1% pull low

H_SCOMP and H_SCOMP# Resistors
and Capacitors close Caliistoga
500 mil ( MAX )
Zo=55ohms

+1.05V_VCCP

1 2

54D9R2F-L1-GP

54D9R2F-L1-GP

R74

R74

+1.05V_VCCP

1 2

54D9R2F-L1-GP

54D9R2F-L1-GP

R77

R77

H_RCOMP routing Trace width and
Spacing use 10 / 20 mil

1 2

24D9R2F-L-GP

24D9R2F-L-GP

R353

R353

H_SWING

12

C548

C548

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

H_SCOMP

H_SCOMP#

H_RCOMP

+1.05V_VCCP

12

R344

R344
221R2F-2-GP

221R2F-2-GP

12

R343

R343
100R2F-L1-GP-U

100R2F-L1-GP-U

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

CRB v0.9 REQUEST

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

A

B

C

D

Date: Sheet

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GMCH-FSB LIBC (1/6)

GMCH-FSB LIBC (1/6)

GMCH-FSB LIBC (1/6)

Siberia

Siberia

Siberia

750Friday, May 25, 2007

750Friday, May 25, 2007

750Friday, May 25, 2007

E

SC

SC

SC

of

of

of

A

2 OF 10

2 OF 10

U84B

U84B

P36

RSVD#P36

P37

RSVD#P37

R35

RSVD#R35

N35

RSVD#N35

AR12

RSVD#AR12

AR13

RSVD#AR13

AM12

RSVD#AM12

AN13

RSVD#AN13

J12

RSVD#J12

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

AR37
AM36

AL36

AM37

BJ20

BK22

BF19
BH20
BK18

BJ18

BF23
BG23
BC23
BD24

BH39

AW20

BK20

G23

M20
M24

G41

AW49

AV20

G36

BJ51
BK51
BK50

BL50

BL49

BK1

BK2

D20

H10
B51

B44
C44
A35
B37
B36
B34
C34

P27
N27
N24
C21
C23
F23
N23

C20
R24
L23

E23
E20
K23

L32
N33
L35

L39
L36

N20

BL3
BL2

BJ1

C51
B50
A50
A49

J20

J23

J36

RSVD#AR37
RSVD#AM36
RSVD#AL36
RSVD#AM37
RSVD#D20

RSVD#H10
RSVD#B51
RSVD#BJ20
RSVD#BK22
RSVD#BF19
RSVD#BH20
RSVD#BK18
RSVD#BJ18
RSVD#BF23
RSVD#BG23
RSVD#BC23
RSVD#BD24

RSVD#BH39
RSVD#AW20
RSVD#BK20

RSVD#B44
RSVD#C44
RSVD#A35
RSVD#B37
RSVD#B36
RSVD#B34
RSVD#C34

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#0
PM_EXT_TS#1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC#BJ51
NC#BK51
NC#BK50
NC#BL50
NC#BL49
NC#BL3
NC#BL2
NC#BK1
NC#BJ1

E1

NC#E1

A5

NC#A5
NC#C51
NC#B50
NC#A50
NC#A49
NC#BK2

RSVD

RSVD

CFG PM NC

CFG PM NC

DPRSLPVR_R

SB_NB_PCIE_RST#

SB_NB_PCIE_RST#

SM_RCOMP_VOH
SM_RCOMP_VOL

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

CLK

SDVO_CTRL_CLK

SDVO_CTRL_DATA

4 4

+1.05V_VCCP

12

R72

R72
56R2J-4-GP

56R2J-4-GP

3 3

2 2

1 1

THERMTRIP_MCH#

+3.3V_RUN

R338 10KR2J-3-GPR338 10KR2J-3-GP

1 2

R339 10KR2J-3-GPR339 10KR2J-3-GP

1 2

CPU_MCH_BSEL04,5
CPU_MCH_BSEL14,5
CPU_MCH_BSEL24,5

CFG[2..0] FSB
Select

010 = FSB 800
011 = FSB 667
Other = Reserved

PM_BMBUSY#18

H_DPRSTP#5,16,42
PM_EXTTS#013
PM_EXTTS#114
ICH_PWRGD18,39

THERMTRIP_MCH#20

DPRSLPVR18,42

PLTRST#18,27,29,30,31,33

GPIO4_PIRQG#18

PM_EXTTS#0

PM_EXTTS#1

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

TP20TP20
TP52TP52

CFG512

TP32TP32
TP24TP24
TP22TP22

CFG912

TP34TP34
TP27TP27
TP23TP23
TP19TP19
TP21TP21
TP28TP28

CFG1612

TP31TP31
TP29TP29

CFG1912
CFG2012

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
SB_NB_PCIE_RST#
THERMTRIP_MCH#
DPRSLPVR_R

R336 0R2J-2-GPR336 0R2J-2-GP

1 2

R97 100R2F-L1-GP-UR97 100R2F-L1-GP-U

1 2

R96 0R2J-2-GP

R96 0R2J-2-GP

1 2

DY

DY

A

B

AV29

SM_CK0

BB23

SM_CK1

BA25

SM_CK3

AV23

SM_CK4

AW30

SM_CK#0

BA23

SM_CK#1

AW25

SM_CK#3

AW23

SM_CK#4

BE29

SM_CKE0

AY32

SM_CKE1

BD39

SM_CKE3

BG37

SM_CKE4

BG20

SM_CS#0

BK16

SM_CS#1

BG16

SM_CS#2

BE13

SM_CS#3

DDR MUXING

DDR MUXING

SM_RCOMP

SM_RCOMP#

SM_VREF#AR49

SM_VREF#AW4

DPLL_REF_CLK

DPLL_REF_CLK#

PEG_CLK#

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI

DMI

GFX_VR_EN

CL_PWROK

ICH_SYNC#

MISC ME GRAPHICS VID

MISC ME GRAPHICS VID

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

PEG_CLK

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3

CL_CLK

CL_DATA

CL_RST#
CL_VREF

CLKREQ#

TEST1
TEST2

BH18
BJ15
BJ14
BE16

BK31
BL31

BL15
BK14

AR49
AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37
R32

B

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_RCOMP
SM_RCOMP#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VR_EN

Layout Note:
MCH_CLVREF ~= 0.350V
Width/Spacing = 12/12

MCH_CLVREF

CLK_3GPLLREQ#
MCH_ICH_SYNC#

TEST1_GMCH
TEST2_GMCH

12

R64

R64
20KR2J-L2-GP

20KR2J-L2-GP

CLK_MCH_3GPLL 4
CLK_MCH_3GPLL# 4

DMI_MRX_ITX_N0 17
DMI_MRX_ITX_N1 17
DMI_MRX_ITX_N2 17
DMI_MRX_ITX_N3 17

DMI_MRX_ITX_P0 17
DMI_MRX_ITX_P1 17
DMI_MRX_ITX_P2 17
DMI_MRX_ITX_P3 17

DMI_MTX_IRX_N0 17
DMI_MTX_IRX_N1 17
DMI_MTX_IRX_N2 17
DMI_MTX_IRX_N3 17

DMI_MTX_IRX_P0 17
DMI_MTX_IRX_P1 17
DMI_MTX_IRX_P2 17
DMI_MTX_IRX_P3 17

TP17TP17
TP15TP15
TP18TP18
TP14TP14
TP16TP16

TP33TP33

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 13,14

DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14

R95

R95

1 2

DY

DY

R90

R90

1 2

DY

DY

CL_CLK0 18
CL_DATA0 18

ICH_CL_PWROK 18,33

ICH_CL_RST0# 18

CLK_3GPLLREQ# 4
MCH_ICH_SYNC# 18

TP53TP53

R341

R341
0R2J-2-GP

0R2J-2-GP

1 2

C

CLOSE PIN BL15 BK14

SM_RCOMP

SM_RCOMP#

10KR2F-2-GP

10KR2F-2-GP

10KR2F-2-GP

10KR2F-2-GP

C630

C630

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C

1 2

1 2

+1.25V_RUN

12

R517

R517

20R2F-GP

20R2F-GP

R516

R516

20R2F-GP

20R2F-GP

+1.8V_SUS

V_DDR_MCH_REF

12

R441

R441
1KR2F-3-GP

1KR2F-3-GP

12

R442

R442
392R2F-GP

392R2F-GP

+1.8V_SUS

+1.8V_SUS

R124

R124
1KR2F-3-GP

1KR2F-3-GP

1 2

12

R132

R132
3K01R2F-3-GP

3K01R2F-3-GP

R125

R125
1KR2F-3-GP

1KR2F-3-GP

1 2

H39
E39
E40
C37
D35
K40

N41
N40
D46
C45
D44
E42

G51
E51
F49
C48

G50
E50
F48
D47

G44
B47
B45

E44
A47
A45

E27
G27
K27

F27

M35
P33

H32
G32
K29

F29
E29

K33
G35
E33
C32
F33

U84C

U84C

J40

L41
L43

J27
L27

J29

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL0
TV_DCONSEL1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_VSYNC
CRT_TVO_IREF
CRT_HSYNC

3 OF 10

3 OF 10

12

C180

C180
SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

12

C181

C181
SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

D

LVDS

LVDS

TV VGA

TV VGA

PCI_EXPRESS GRAPHICS

PCI_EXPRESS GRAPHICS

12

SM_RCOMP_VOL

12

D

+VCC_PEG

PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8

PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

PEG_COMPI

PEG_COMPO

PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15

PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15

SM_RCOMP_VOH

C184

C184
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C185

C185
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

E

R62

R62

1 2

24D9R2F-L-GP

24D9R2F-L-GP

PEG_COMP_GMCH

PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15

PCIE_MTX_GRX_C_N0 PCIE_MTX_GRX_N0

PCIE_MTX_GRX_C_N3 PCIE_MTX_GRX_N3

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet of

GMCH-LVDS/VGA/DMI/DDR (2/6)

GMCH-LVDS/VGA/DMI/DDR (2/6)

GMCH-LVDS/VGA/DMI/DDR (2/6)

PCIE_MRX_GTX_N[15..0] 15

PCIE_MRX_GTX_P[15..0] 15

PCIE_MTX_GRX_N[15..0] 15
PCIE_MTX_GRX_P[15..0] 15

C524 SCD1U10V2KX-4GPC524 SCD1U10V2KX-4GP

1 2

C567 SCD1U10V2KX-4GPC567 SCD1U10V2KX-4GP

1 2

C526 SCD1U10V2KX-4GPC526 SCD1U10V2KX-4GP

1 2

C557 SCD1U10V2KX-4GPC557 SCD1U10V2KX-4GP

1 2

C528 SCD1U10V2KX-4GPC528 SCD1U10V2KX-4GP

1 2

C559 SCD1U10V2KX-4GPC559 SCD1U10V2KX-4GP

1 2

C522 SCD1U10V2KX-4GPC522 SCD1U10V2KX-4GP

1 2

C561 SCD1U10V2KX-4GPC561 SCD1U10V2KX-4GP

1 2

C530 SCD1U10V2KX-4GPC530 SCD1U10V2KX-4GP

1 2

C555 SCD1U10V2KX-4GPC555 SCD1U10V2KX-4GP

1 2

C538 SCD1U10V2KX-4GPC538 SCD1U10V2KX-4GP

1 2

C563 SCD1U10V2KX-4GPC563 SCD1U10V2KX-4GP

1 2

C565 SCD1U10V2KX-4GPC565 SCD1U10V2KX-4GP

1 2

C532 SCD1U10V2KX-4GPC532 SCD1U10V2KX-4GP

1 2

C534 SCD1U10V2KX-4GPC534 SCD1U10V2KX-4GP

1 2

C536 SCD1U10V2KX-4GPC536 SCD1U10V2KX-4GP

1 2

C523 SCD1U10V2KX-4GPC523 SCD1U10V2KX-4GP

1 2

C566 SCD1U10V2KX-4GPC566 SCD1U10V2KX-4GP

1 2

C525 SCD1U10V2KX-4GPC525 SCD1U10V2KX-4GP

1 2

C556 SCD1U10V2KX-4GPC556 SCD1U10V2KX-4GP

1 2

C527 SCD1U10V2KX-4GPC527 SCD1U10V2KX-4GP

1 2

C558 SCD1U10V2KX-4GPC558 SCD1U10V2KX-4GP

1 2

C521 SCD1U10V2KX-4GPC521 SCD1U10V2KX-4GP

1 2

C560 SCD1U10V2KX-4GPC560 SCD1U10V2KX-4GP

1 2

C529 SCD1U10V2KX-4GPC529 SCD1U10V2KX-4GP

1 2

C554 SCD1U10V2KX-4GPC554 SCD1U10V2KX-4GP

1 2

C537 SCD1U10V2KX-4GPC537 SCD1U10V2KX-4GP

1 2

C562 SCD1U10V2KX-4GPC562 SCD1U10V2KX-4GP

1 2

C564 SCD1U10V2KX-4GPC564 SCD1U10V2KX-4GP

1 2

C531 SCD1U10V2KX-4GPC531 SCD1U10V2KX-4GP

1 2

C533 SCD1U10V2KX-4GPC533 SCD1U10V2KX-4GP

1 2

C535 SCD1U10V2KX-4GPC535 SCD1U10V2KX-4GP

1 2

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Siberia

Siberia

Siberia

E

PCIE_MTX_GRX_N1PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_N2PCIE_MTX_GRX_C_N2

PCIE_MTX_GRX_N4PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_N5PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_N6PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_N7PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_N8PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_N9PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_N10PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_N11PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_N12PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_N13PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_N14PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_N15PCIE_MTX_GRX_C_N15

PCIE_MTX_GRX_P0PCIE_MTX_GRX_C_P0
PCIE_MTX_GRX_P1PCIE_MTX_GRX_C_P1
PCIE_MTX_GRX_P2PCIE_MTX_GRX_C_P2
PCIE_MTX_GRX_P3PCIE_MTX_GRX_C_P3
PCIE_MTX_GRX_P4PCIE_MTX_GRX_C_P4
PCIE_MTX_GRX_P5PCIE_MTX_GRX_C_P5
PCIE_MTX_GRX_P6PCIE_MTX_GRX_C_P6
PCIE_MTX_GRX_P7PCIE_MTX_GRX_C_P7
PCIE_MTX_GRX_P8PCIE_MTX_GRX_C_P8
PCIE_MTX_GRX_P9PCIE_MTX_GRX_C_P9
PCIE_MTX_GRX_P10PCIE_MTX_GRX_C_P10
PCIE_MTX_GRX_P11PCIE_MTX_GRX_C_P11
PCIE_MTX_GRX_P12PCIE_MTX_GRX_C_P12
PCIE_MTX_GRX_P13PCIE_MTX_GRX_C_P13
PCIE_MTX_GRX_P14PCIE_MTX_GRX_C_P14
PCIE_MTX_GRX_P15PCIE_MTX_GRX_C_P15

SC

SC

850Friday, May 25, 2007

850Friday, May 25, 2007

850Friday, May 25, 2007

SC

of

of

A

B

C

D

E

U84D

U84D

AR43

SA_DQ0

AW44

SA_DQ1

BA45

SA_DQ2

AY46

SA_DQ3

AR41

SA_DQ4

AR45

SA_DQ5

AT42

SA_DQ6

AW47

SA_DQ7

BB45

SA_DQ8

BF48

SA_DQ9

BG47

SA_DQ10

BJ45

SA_DQ11

BB47

SA_DQ12

BG50

SA_DQ13

BH49

SA_DQ14

BE45

SA_DQ15

AW43

SA_DQ16

BE44

SA_DQ17

BG42

SA_DQ18

BE40

SA_DQ19

BF44

SA_DQ20

BH45

SA_DQ21

BG40

SA_DQ22

BF40

SA_DQ23

AR40

SA_DQ24

AW40

SA_DQ25

AT39

SA_DQ26

AW36

SA_DQ27

AW41

SA_DQ28

AY41

SA_DQ29

AV38

SA_DQ30

AT38

SA_DQ31

AV13

SA_DQ32

AT13

SA_DQ33

AW11

SA_DQ34

AV11

SA_DQ35

AU15

SA_DQ36

AT11

SA_DQ37

BA13

SA_DQ38

BA11

SA_DQ39

BE10

SA_DQ40

BD10

SA_DQ41

BD8

SA_DQ42

AY9

SA_DQ43

BG10

SA_DQ44

AW9

SA_DQ45

BD7

SA_DQ46

BB9

SA_DQ47

BB5

SA_DQ48

AY7

SA_DQ49

AT5

SA_DQ50

AT7

SA_DQ51

AY6

SA_DQ52

BB7

SA_DQ53

AR5

SA_DQ54

AR8

SA_DQ55

AR9

SA_DQ56

AN3

SA_DQ57

AM8

SA_DQ58

AN10

SA_DQ59

AT9

SA_DQ60

AN9

SA_DQ61

AM9

SA_DQ62

AN11

SA_DQ63

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

DDR_A_D[63..0]

DDR_A_BS[2..0]

DDR_A_DM[7..0]

DDR_A_DQS[7..0]

DDR_A_DQS#[7..0]

DDR_A_MA[14..0]

4 OF 10

4 OF 10

DDR SYSTEM MEMORRY A

DDR SYSTEM MEMORRY A

SA_RCVEN#

4 4

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6

DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12

3 3

2 2

DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_D16

DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D20

DDR_A_D21

DDR_A_D22

DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

DDR_A_D32

DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

DDR_A_D48

DDR_A_D49

DDR_A_D50

DDR_A_D51

DDR_A_D52

DDR_A_D53

DDR_A_D54

DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_BS[2..0] 13,14

DDR_A_DM[7..0] 13

DDR_A_MA[14..0] 13,14

SA_BS0
SA_BS1
SA_BS2

SA_CAS#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6

SA_DQS7
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14

SA_RAS#

SA_WE#

DDR_A_D[63..0] 13

DDR_A_DQS[7..0] 13

DDR_A_DQS#[7..0] 13

DDR_A_BS0

BB19

DDR_A_BS1

BK19

DDR_A_BS2

BF29

DDR_A_CAS#

BL17

DDR_A_DM0

AT45

DDR_A_DM1

BD44

DDR_A_DM2

BD42

DDR_A_DM3

AW38

DDR_A_DM4

AW13

DDR_A_DM5

BG8

DDR_A_DM6

AY5

DDR_A_DM7

AN6

DDR_A_DQS0

AT46

DDR_A_DQS1

BE48

DDR_A_DQS2

BB43

DDR_A_DQS3

BC37

DDR_A_DQS4

BB16

DDR_A_DQS5

BH6

DDR_A_DQS6

BB2

DDR_A_DQS7

AP3

DDR_A_DQS#0

AT47

DDR_A_DQS#1

BD47

DDR_A_DQS#2

BC41

DDR_A_DQS#3

BA37

DDR_A_DQS#4

BA16

DDR_A_DQS#5

BH7

DDR_A_DQS#6

BC1

DDR_A_DQS#7

AP2

DDR_A_MA0

BJ19

DDR_A_MA1

BD20

DDR_A_MA2

BK27

DDR_A_MA3

BH28

DDR_A_MA4

BL24

DDR_A_MA5

BK28

DDR_A_MA6

BJ27

DDR_A_MA7

BJ25

DDR_A_MA8

BL28

DDR_A_MA9

BA28

DDR_A_MA10

BC19

DDR_A_MA11

BE28

DDR_A_MA12

BG30

DDR_A_MA13

BJ16

DDR_A_MA14 DDR_B_MA14

BJ29

DDR_A_RAS#

BE18

M_A_RCVEN#

AY20

DDR_A_WE#

BA19

DDR_A_CAS# 13

DDR_A_RAS# 13

DDR_A_WE# 13

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6

DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15

DDR_B_D16

DDR_B_D17

DDR_B_D18

DDR_B_D19

DDR_B_D20

DDR_B_D21

DDR_B_D22

DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31

DDR_B_D32

DDR_B_D33

DDR_B_D34

DDR_B_D35

DDR_B_D36

DDR_B_D37

DDR_B_D38

DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

DDR_B_D48

DDR_B_D49

DDR_B_D50

DDR_B_D51

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U84E

U84E

AP49

SB_DQ0

AR51

SB_DQ1

AW50

SB_DQ2

AW51

SB_DQ3

AN51

SB_DQ4

AN50

SB_DQ5

AV50

SB_DQ6

AV49

SB_DQ7

BA50

SB_DQ8

BB50

SB_DQ9

BA49

SB_DQ10

BE50

SB_DQ11

BA51

SB_DQ12

AY49

SB_DQ13

BF50

SB_DQ14

BF49

SB_DQ15

BJ50

SB_DQ16

BJ44

SB_DQ17

BJ43

SB_DQ18

BL43

SB_DQ19

BK47

SB_DQ20

BK49

SB_DQ21

BK43

SB_DQ22

BK42

SB_DQ23

BJ41

SB_DQ24

BL41

SB_DQ25

BJ37

SB_DQ26

BJ36

SB_DQ27

BK41

SB_DQ28

BJ40

SB_DQ29

BL35

SB_DQ30

BK37

SB_DQ31

BK13

SB_DQ32

BE11

SB_DQ33

BK11

SB_DQ34

BC11

SB_DQ35

BC13

SB_DQ36

BE12

SB_DQ37

BC12

SB_DQ38

BG12

SB_DQ39

BJ10

SB_DQ40

BL9

SB_DQ41

BK5

SB_DQ42

BL5

SB_DQ43

BK9

SB_DQ44

BK10

SB_DQ45

BJ8

SB_DQ46

BJ6

SB_DQ47

BF4

SB_DQ48

BH5

SB_DQ49

BG1

SB_DQ50

BC2

SB_DQ51

BK3

SB_DQ52

BE4

SB_DQ53

BD3

SB_DQ54

BJ2

SB_DQ55

BA3

SB_DQ56

BB3

SB_DQ57

AR1

SB_DQ58

AT3

SB_DQ59

AY2

SB_DQ60

AY3

SB_DQ61

AU2

SB_DQ62

AT2

SB_DQ63

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

DDR_B_D[63..0]

DDR_B_BS[2..0]

DDR_B_DM[7..0]

DDR_B_DQS[7..0]

DDR_B_DQS#[7..0]

DDR_B_MA[14..0]

5 OF 10

5 OF 10

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

DDR_B_BS[2..0] 14

DDR_B_DM[7..0] 14

DDR_B_MA[14..0] 13,14

SB_BS0
SB_BS1
SB_BS2

SB_CAS#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6

SB_DQS7
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14

SB_RAS#

SB_RCVEN#

SB_WE#

DDR_B_D[63..0] 14

DDR_B_DQS[7..0] 14

DDR_B_DQS#[7..0] 14

AY17
BG18
BG36

BE17

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE24

AV16
AY18

BC17

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

M_B_RCVEN#

DDR_B_WE#

DDR_B_CAS# 14

DDR_B_RAS# 14

TP43TP43TP41TP41

DDR_B_WE# 14

1 1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

A

B

C

D

Date: Sheet

GMCH-DDR (3/6)

GMCH-DDR (3/6)

GMCH-DDR (3/6)

Siberia

Siberia

Siberia

E

SC

SC

950Friday, May 25, 2007

950Friday, May 25, 2007

950Friday, May 25, 2007

SC

of

of

of

A

+1.05V_VCCP

AT35
AT34
AH28
AC32
AC31
AK32

AJ31
AJ28

4 4

+1.8V_SUS

3 3

2 2

1 1

AH32
AH31
AH29

AF32

R30

AU32
AU33
AU35

AV33
AW33
AW35

AY35

BA32

BA33

BA35

BB33

BC32

BC33

BC35

BD32

BD35

BE32

BE33

BE35

BF33

BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

R20

T14
W13
W14

Y12

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28

AF21

AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

A

LIB C

6 OF 10

6 OF 10

U84F

U84F

VCC
VCC
VCC
VCC

1.31A

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC CORE

VCC CORE

VCC

POWER

POWER

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

2.4A

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

VCC SM

VCC SM

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

VCC GFX

VCC GFX

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

VCC SM LF

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

B

Signal Group Supply Icc-max
+1.05V_VCCP VCC 1.31A
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+1.8V_SUS
+1.8V_SUS 0.2A
+1.25V_RUN
+1.25V_RUN

VCC_NCTF A

VTT 0.85A

VCC_PEG 1.2A

VCC_RXR_DMI 0.25A

VCC_ATX 84.15mA

VCC_SM 2.4A

VCC_SM_CK

VCCA_HPLL 0.05A

VCCA_MPLL 0.15A
+1.25V_RUN
+1.25V_RUN
+1.25V_RUN
+1.25V_RUN

VCCD_HPLL 0.25A
+1.25V_RUN
+1.25V_RUN
+1.25V_RUN VCCA_PEG_PLL

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

B

12

C134

C134

12

C142

C142

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

/VCCD_PEG_PLL

Place CAP where
LVDS and DDR2 taps

12

12

C159

C159

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

C161

C161

12

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

+3.3V_RUN

C164

C164

SCD47U10V3KX-3GP

SCD47U10V3KX-3GP

R60

R60

1 2

10R2J-2-GP

10R2J-2-GP

0.735AVCCA_SM
AVCCA_SM_NCTF

0.015AVCCA_SM_CK

0.2AVCCA_AXD
AVCCA_AXD_NCTF

0.1A

0.35AVCCA_AXF+1.25V_RUN

0.1AVCCA_DMI+1.25V_RUN

0.06AVCCD_TVDAC+1.5V_RUN

0.005AVCCA_PEG_BG+3.3V_RUN

0.1AVCC_HV+3.3V_RUN

12

C154

C154

SC1U10V3KX-3GP

SC1U10V3KX-3GP

C

+VCC_MCH_L

ST220U2D5VBM-2GP

ST220U2D5VBM-2GP

308 mils
from the
Edge

(Non-AMT)

(667MHz)

(667MHz)

+1.8V_SUS

12

C144

C144

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C141

C141

SC1U10V3KX-3GP

SC1U10V3KX-3GP

C

+1.05V_VCCP

D2

D2

2 1

RB751V-40-1-GP

RB751V-40-1-GP

+1.05V_VCCP

TC7

TC7

12

12

C125

C125

12

12

C132

C132

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

Coupling CAP

FOR VCC AXM NCTF AND VCC AXM

+1.05V_VCCP

12

C96

C96

12

12

C99

C99

C108

C108

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

Place on the Edge

FOR VCC SM

12

TC9

TC9
ST330U6D3VDM-17GP

ST330U6D3VDM-17GP

12

C666

C666

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

C662

C662

Place on the Edge

D

FOR VCC CORE AND VCC NCTF

AB33
AB36

12

12

C95

C95

C98

C98

C118

C118

DY

DY

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

12

C127

C127

Coupling CAP
Inside MCH cavity

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

C107

C107

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

D

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C106

C106

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

AB37
AC33
AC35
AC36
AD35
AD36

AF33

AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36
AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

AL24
AL26

AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet of

7 OF 10

7 OF 10

U84G

U84G

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

VCC NCTF

VCC NCTF

POWER

POWER

E

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS NCTF

VSS NCTF

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS SCBVSS AXM

VSS SCBVSS AXM

VCC

VSS AXM NCTF

VSS AXM NCTF

GMCH-POWER (4/6)

GMCH-POWER (4/6)

GMCH-POWER (4/6)

Siberia

Siberia

Siberia

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3

VSS_SCB

B2

VSS_SCB

C1

VSS_SCB

BL1

VSS_SCB

BL51

VSS_SCB

A51

VSS_SCB

+1.05V_VCCP

AT33

VCC_AXM

AT31

VCC_AXM

AK29

VCC_AXM

AK24

VCC_AXM

AK23

VCC_AXM

AJ26

VCC_AXM

AJ23

VCC_AXM

VCC

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

For NCTF

TP123 TPAD28TP123 TPAD28
TP124 TPAD28TP124 TPAD28
TP126 TPAD28TP126 TPAD28
TP125 TPAD28TP125 TPAD28

10 50Friday, May 25, 2007

10 50Friday, May 25, 2007

10 50Friday, May 25, 2007

of

of

0SC

SC

SC

SC

A

B

C

D

E

+1.25V_RUN+VCC_AXD

R484

R484

1uH 300mA

1 2

IND-1UH-36-GP

IND-1UH-36-GP

+VCC_SM_CK_L

L2

L2

+1.05V_VCCP

Reserved R484 for inductor 5.6nH

L33

L33

+1.8V_SUS+VCC_SM_CK

12

C682

C682
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+1.05V_VCCP

45mA MAX.

+1.25V_RUN

1 2

BLM18AG121SN-1GP

BLM18AG121SN-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

4 4

1 2

BLM18AG121SN-1GP

BLM18AG121SN-1GP

+1.25V_RUN

1 2

BLM21PG221SN1D-1GP

BLM21PG221SN1D-1GP

3 3

2 2

120ohm 100MHz
200mA 0.2ohm DC

L6

L6

C105

C105

120ohm 100MHz
200mA 0.2ohm DC

L32

L32

220ohm 100MHz 2A 0.1ohm DC

L31

L31

+VCCA_HPLL

12

+VCCA_MPLL

12

R453

R453
D5R3F-1-GP

D5R3F-1-GP

+VCCA_MPLL_L

12

C629

C629
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

+VCCA_PEG_PLL

12

R415

R415
1R3F-GP

1R3F-GP

+VCCA_PEG_PLL_L

12

C619

C619
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SCD022U16V2KX-3GP

SCD022U16V2KX-3GP

12

C116

C116
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C628

C628
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C608

C608
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.5V_RUN

12

C85

C85

+1.25V_RUN

12

+1.25V_RUN

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

R474

R474

12

0R5J-5-GP

0R5J-5-GP

TC31

TC31
ST100U4VBM-L1-GP

ST100U4VBM-L1-GP

R524

R524

12

0R2J-2-GP

0R2J-2-GP

C677

C677

C84

C84
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+VCCA_SM_CK

12

12

C676

C676

12

C77

C77
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+VCCA_SM

12

C143

C143

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

SC1U10V3KX-3GP

SC1U10V3KX-3GP

+3.3V_RUN

12

C80

C80
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C123

C123

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C150

C150
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C155

C155

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

+1.25V_RUN

12

C117

C117

12

C124

C124

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

+VCCA_HPLL

+VCCA_MPLL

+VCCA_PEG_PLL

12

C641

C641

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

+VCCA_PEG_PLL

12

C90

C90
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

A33
B33

A30

B32

B49

H49

AL2

AM2

A41

B41

K50

K49

U51

AW18

AV19
AU19
AU18
AU17

AT22

AT21

AT19

AT18

AT17
AR17
AR16

BC29

BB29

C25
B25
C27
B27
B28
A28

M32

L29

N28

AN2

U48

H42

J32

J41

8 OF 10

8 OF 10

U84H

U84H

VCC_SYNC

VCCA_CRT_DAC
VCCA_CRT_DAC

VCCA_DAC_BG

VSSA_DAC_BG

VCCA_DPLLA

VCCA_DPLLB

0.05A

VCCA_HPLL

VCCA_MPLL

VCCA_LVDS

VSSA_LVDS

VCCA_PEG_BG

0.005A

VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM

VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM_NCTF
VCCA_SM_NCTF

0.015A

VCCA_SM_CK
VCCA_SM_CK

VCCA_TVA_DAC
VCCA_TVA_DAC
VCCA_TVB_DAC
VCCA_TVB_DAC
VCCA_TVC_DAC
VCCA_TVC_DAC

VCCD_CRT
VCCD_TVDAC

0.06A

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

VCCD_LVDS
VCCD_LVDS

0.15A

0.25A

POWER

POWER

A LVDS PLL CRT

A LVDS PLL CRT

A PEG

A PEG

0.1A

0.735A

TV A CK A SM

TV A CK A SM

0.1A

LVDS TV/CRT

LVDS TV/CRT

VCC_AXD
VCC_AXD

0.2A

VCC_AXD
VCC_AXD
VCC_AXD

AXD

AXD

VCC_AXD

VCC_AXD_NCTF

VCC_AXF
VCC_AXF

AXF

AXF

VCC_AXF

0.35A

0.2A

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

SM CK

SM CK

VCC_TX_LVDS

HV

HV

0.1A

VCC_PEG
VCC_PEG
VCC_PEG

1.2A

PEG

PEG

VCC_PEG
VCC_PEG

VCC_RXR_DMI
VCC_RXR_DMI

DMI

DMI

0.25A

VTTLF

VTTLF

VTT
VTT
VTT
VTT
VTT
VTT
VTT

0.85A

VTT
VTT
VTT
VTT

VTT

VTT

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VCC_DMI

0.1A

VCC_HV
VCC_HV

VTTLF
VTTLF
VTTLF

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

Place on the edge

12

+3.3V_RUN

VTTLF1
VTTLF2
VTTLF3

12

C626

C626

12

C610

C610

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C604

C604

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

C126

C126

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

12

C547

C547
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

12

C592

C592

C91

C91

C545

C545

C664

C664

C97

C97

C110

C110

C546

C546

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+VCC_PEG

12

C92

C92

SCD47U10V3KX-3GP

SCD47U10V3KX-3GP

12

C645

C645
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

Place caps close to VCC_AXD

+1.25V_RUN

12

12

12

12

12

+1.25V_RUN

12

R522

R522

1 2

C673

C673
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

TC6

TC6
ST220U2D5VBM-2GP

ST220U2D5VBM-2GP

12

TC29

TC29
ST220U2D5VBM-2GP

ST220U2D5VBM-2GP

1 2

0R3-0-U-GP

0R3-0-U-GP

C543

C543
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C625

C625
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1R3F-GP

1R3F-GP

91nH 1.5A

1 2

IND-91NH-1-GP

IND-91NH-1-GP

SCD47U10V3KX-3GP

SCD47U10V3KX-3GP

1 1

A

B

C

SCD47U10V3KX-3GP

SCD47U10V3KX-3GP

SCD47U10V3KX-3GP

SCD47U10V3KX-3GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

D

Date: Sheet of

GMCH-POWER/FILTERR (5/6)

GMCH-POWER/FILTERR (5/6)

GMCH-POWER/FILTERR (5/6)

Siberia

Siberia

Siberia

11 50Friday, May 25, 2007

11 50Friday, May 25, 2007

11 50Friday, May 25, 2007

of

E

of

SC

SC

SC

A

4 4

3 3

Layout Note:
Location of all MCH CFG strap resistors
need to be close to trace to minimize stub

+3.3V_RUN

CFG19

CFG20

CFG5

CFG9

CFG16

1 2

DY

DY

R337 4K02R2F-GP

R337 4K02R2F-GP

1 2

DY

DY

R340 4K02R2F-GP

R340 4K02R2F-GP

1 2

DY

DY

R58 4K02R2F-GP

R58 4K02R2F-GP

1 2

DY

DY

R342 4K02R2F-GP

R342 4K02R2F-GP

1 2

DY

DY

R63 4K02R2F-GP

R63 4K02R2F-GP

CFG198

CFG208

CFG58

CFG98

2 2

CFG168

CFG Strap HIGH 1LOW 0

CFG 5
CFG 9

PCI Express Graphics
Lane Reversal

Lane Reversal

CFG 16
CFG 18
CFG 19

DMI Lane Reserved

CFG 20

1 1

Concurrent SDVO/PCIE

CFG 12
CFG 13

LL(00)

LH(01)

HL(10)

HH(11)

★

1.05V 1.5VVCC select

★

Only PCIE or SDVO

★

is operation

XOR/ALL-Z

Reserved

XOR Mode Enabled

All Z Mode Enabled

Normal Operation

A

★

DMI X 4DMI X 2

★

Normal Mode(Lanes
number in order)

★

EnabledDisabledFSB Dynamic ODT

Reserved LaneNormal Operation
PCIE and SDVO are
operation simultaneous

★

B

B

C

9 OF 10

9 OF 10

U84I

U84I

A13

VSS

A15

VSS

A17

VSS

A24

VSS

AA21

VSS

AA24

VSS

AA29

VSS

AB20

VSS

AB23

VSS

AB26

VSS

AB28

VSS

AB31

VSS

AC10

VSS

AC13

VSS

AC3

VSS

AC39

VSS

AC43

VSS

AC47

VSS

AD1

VSS

AD21

VSS

AD26

VSS

AD29

VSS

AD3

VSS

AD41

VSS

AD45

VSS

AD49

VSS

AD5

VSS

AD50

VSS

AD8

VSS

AE10

VSS

AE14

VSS

AE6

VSS

AF20

VSS

AF23

VSS

AF24

VSS

AF31

VSS

AG2

VSS

AG38

VSS

AG43

VSS

AG47

VSS

AG50

VSS

AH3

VSS

AH40

VSS

AH41

AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW12
AW16

C

AH7

AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49

AL1

AM3

AM4

AN1

AN5

AN7

AP4

AR2

AR7

AU1

AU3

AW1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

D

10 OF 10

10 OF 10

U84J

U84J

C46

VSS

C50

VSS

C7

VSS

D13

VSS

D24

VSS

D3

VSS

D32

VSS

D39

VSS

D45

VSS

D49

VSS

E10

VSS

E16

VSS

E24

VSS

E28

VSS

E32

VSS

E47

VSS

F19

VSS

F36

VSS

F4

VSS

F40

VSS

F50

VSS

G1

VSS

G13

VSS

G16

VSS

G19

VSS

G24

VSS

G28

VSS

G29

VSS

G33

VSS

G42

VSS

G45

VSS

G48

VSS

G8

VSS

H24

VSS

H28

VSS

H4

VSS

H45

VSS

J11

VSS

VSS

VSS

J16

VSS

J2

VSS

J24

VSS

J28

VSS

J33

VSS

J35

VSS

J39

VSS

K12

VSS

K47

VSS

K8

VSS

L1

VSS

L17

VSS

L20

VSS

L24

VSS

L28

VSS

L3

VSS

L33

VSS

L49

VSS

M28

VSS

M42

VSS

M46

VSS

M49

VSS

M5

VSS

M50

VSS

M9

VSS

N11

VSS

N14

VSS

N17

VSS

N29

VSS

N32

VSS

N36

VSS

N39

VSS

N44

VSS

N49

VSS

N7

VSS

P19

VSS

P2

VSS

P23

VSS

P3

VSS

P50

VSS

R49

VSS

T39

VSS

T43

VSS

T47

VSS

U41

VSS

U45

VSS

U50

VSS

V2

VSS

V3

VSS

D

W11

VSS

W39

VSS

W43

VSS

W47

VSS

W5

VSS

W7

VSS

Y13

VSS

Y2

VSS

Y41

VSS

Y45

VSS

Y49

VSS

Y5

VSS

Y50

VSS

Y11

VSS

P29

VSS

MCH_GND1

T29

VSS

MCH_GND2

T31

VSS

MCH_GND3

T33

VSS

MCH_GND4

R28

VSS

AA32

VSS

AB32

VSS

AD32

VSS

AF28

VSS

AF29

VSS

AT27

VSS

AV25

VSS

H50

VSS

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

R71 0R2J-2-GPR71 0R2J-2-GP
R70 0R2J-2-GPR70 0R2J-2-GP
R69 0R2J-2-GPR69 0R2J-2-GP
R66 0R2J-2-GPR66 0R2J-2-GP

GMCH-GND (6/6)

GMCH-GND (6/6)

GMCH-GND (6/6)

Siberia

Siberia

Siberia

E

1 2
1 2
1 2
1 2

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

12 50Friday, May 25, 2007

12 50Friday, May 25, 2007

12 50Friday, May 25, 2007

of

of

E

of

SC

SC

SC

A

MEM_SCLK14,18,31
MEM_SDATA14,18,31 DDR_A_DM[7..0] 9

M_CLK_DDR#18
M_CLK_DDR18
M_CLK_DDR#08
M_CLK_DDR08

4 4

DDR_A_CAS#

DDR_A_RAS#

DDR_A_WE#

DDR_CS0_DIMMA#

109

108

113

/WE

/RAS

/CAS

A0

A399A498A597A694A792A893A991A10/AP

3 3

102A1101A2100

110

DDR_CS1_DIMMA#

115

/CS0

M_CLK_DDR0

DDR_CKE1_DIMMA

DDR_CKE0_DIMMA

80

/CS1

CKE079CKE1

DDR_A_DM0

DDR_A_DM5

DDR_A_DM4

DDR_A_DM3

DDR_A_DM2

DDR_A_DM1

DDR_A_DM7

M_CLK_DDR#1

M_CLK_DDR#0

M_CLK_DDR1

30

164

32

166

CK0

CK1

/CK0

/CK1

A1190A1289A13

A1486A1584A16/BA2

105

116

DDR_A_DM6

MEM_SDATA

195

130

147

170

185

DM010DM126DM252DM367DM4

DM5

DM6

DM7

BA0

BA1

DQ05DQ17DQ217DQ319DQ44DQ56DQ614DQ716DQ823DQ925DQ1035DQ1137DQ1220DQ1322DQ1436DQ1538DQ1643DQ1745DQ1855DQ1957DQ2044DQ2146DQ2256DQ2358DQ2461DQ2563DQ2673DQ2775DQ2862DQ2964DQ3074DQ3176DQ32

85

107

106

R170 10KR2J-3-GPR170 10KR2J-3-GP

R171 10KR2J-3-GPR171 10KR2J-3-GP

DDR_SEL_A1

DDR_SEL_A0

MEM_SCLK

198

200

197

199

SA0

SA1

SCL

SDA

VDDSPD

1 2

1 2

PM_EXTTS#0

83

NC#5050NC#6969NC#83

B

+3.3V_RUN

12

12

C239

C234

PM_EXTTS#0 8

+1.8V_SUS

VDD81VDD82VDD87VDD88VDD95VDD96VDD

C234

103

104

111

VDD

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

120

163

NC#120

NC#163/TEST

REVERSE TYPE

C239
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

112

117

118

VSS3VSS8VSS9VSS12VSS15VSS18VSS21VSS24VSS27VSS28VSS33VSS34VSS39VSS40VSS41VSS42VSS47VSS48VSS53VSS54VSS59VSS60VSS65VSS66VSS71VSS72VSS77VSS78VSS

VDD

VDD

VDD

VDD

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

123

125

135

137

124

126

134

136

141

143

151

153

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

C

A is required to route to Top SoDIMM for
AMT to function. Ch.A SoDIMM needs to be
populated for Intel AMT support.

High 6.5 mm

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

159

173

175

158

160

174

176

179

181

189

191

121

DQ59

180

122

DQ60

182

127

VSS

DQ61

192

128

VSS

DQ62

194

132

VSS

DQ63

133

138

VSS

VSS

/DQS011/DQS129/DQS249/DQS368/DQS4

VSS

D

DDR_A_DM[7..0]

DDR_A_DQS[7..0]

DDR_A_DQS#[7..0]

DDR_A_D[63..0]

DDR_A_BS[2..0]

DDR_A_MA[14..0]

139

144

145

149

150

155

156

161

162

165

168

171

172

177

178

183

184

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

/DQS5

/DQS6

/DQS7

DQS013DQS131DQS251DQS370DQS4

DQS5

DQS6

DQS7

129

146

167

186

131

148

169

188

114

187

VSS

ODT0

119

190

VSS

ODT1

VSS

201

193

196

VSS

VSS

VREF1VSS2GND

202

DIM1

DIM1
DDR2-200P-10-U1

DDR2-200P-10-U1

GND

62.10017.881

62.10017.881

DDR_A_DQS[7..0] 9

DDR_A_DQS#[7..0] 9

DDR_A_D[63..0] 9

DDR_A_BS[2..0] 9,14

DDR_A_MA[14..0] 9,14

E

Crestline-PM

(BOT side)

DDR_A_MA4

DDR_A_MA6

DDR_A_MA5

DDR_A_MA2

DDR_A_MA0

DDR_A_MA3

DDR_A_MA1

12

C283

C283
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

DY

2 2

12

C690

C690
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C297

C297
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1 1

DDR_A_MA10

DDR_A_MA12

DDR_A_MA11

DDR_A_MA8

DDR_A_MA7

DDR_A_MA9

12

C274

C274
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

DY

12

C215

C215
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C688

C688
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

A

DDR_A_MA13

DDR_A_BS1

DDR_A_BS0

DDR_A_BS2

DDR_A_MA14

12

C251

C251
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

DY

DDR_A_D3

DDR_A_D0

DDR_A_D1

DDR_A_D2

DDR_A_D6

DDR_A_D4

DDR_A_D5

DDR_A_D7

DDR_A_D8

12

C248

C248
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DDR_A_D9

DDR_A_D11

DDR_A_D10

DDR_A_D12

DDR_A_D13

Pleace close to the DIMM Slot

+0.9V_DDR_VTT

12

C213

C213
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Pleace use One Capacitor close to
every Two pull-up Resistors

12

C698

C698
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C216

C216
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C689

C689
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DDR_A_D18

DDR_A_D16

DDR_A_D17

DDR_A_D14

DDR_A_D15

12

C241

C241
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C217

C217
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C686

C686
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DDR_A_D23

DDR_A_D22

DDR_A_D20

DDR_A_D19

DDR_A_D21

B

DDR_A_D28

DDR_A_D26

DDR_A_D27

DDR_A_D25

DDR_A_D24

12

C242

C242
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C214

C214
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C699

C699
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DDR_A_D30

DDR_A_D29

DDR_A_D32

DDR_A_D31

DDR_A_D36

DDR_A_D34

DDR_A_D33

DDR_A_D35

12

C250

C250
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C687

C687
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DDR_A_D38

DDR_A_D37

DDR_A_D39

DDR_A_D42

DDR_A_D40

DDR_A_D41

DDR_A_D48

DDR_A_D45

DDR_A_D47

DDR_A_D44

DDR_A_D43

DDR_A_D46

+1.8V_SUS

12

C252

C252
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

DDR_A_D49

SWAP

M_CKE[1:0] and M_CS[1:0]#
pull-up Resistors close DIMM
Slot 1300 mil ( MAX )

DDR_A_D55

DDR_A_D52

DDR_A_D51

DDR_A_D53

DDR_A_D54

DDR_A_D50

DDR_A_MA14

DDR_A_MA2

DDR_A_MA0
DDR_A_RAS#

DDR_A_MA5
DDR_A_MA8

M_ODT1
DDR_CS1_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_MA9
DDR_A_MA12

DDR_A_D56

C

DDR_A_D61

DDR_A_D58

DDR_A_D57

DDR_A_D63

DDR_A_D59

DDR_A_D60

DDR_A_D62

12

C243

C243
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

+0.9V_DDR_VTT

R161

R161

1 2

56R2J-4-GP

56R2J-4-GP

RN6

RN6

1
2 3

1
2 3

1
2 3

1
2 3

1
2 3

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN7

RN7

SRN56J-4-GP

SRN56J-4-GP

RN53

RN53

SRN56J-4-GP

SRN56J-4-GP

RN49

RN49

SRN56J-4-GP

SRN56J-4-GP

RN9

RN9

SRN56J-4-GP

SRN56J-4-GP

RN54

RN54

SRN56J-4-GP

SRN56J-4-GP

4

4

4

4

4

4

DDR_A_DQS#2

DDR_A_DQS#1

DDR_A_DQS#0

DDR_A_DQS#3

DDR_A_DQS4

DDR_A_DQS3

DDR_A_DQS1

DDR_A_DQS0

DDR_A_DQS#5

DDR_A_DQS#7

DDR_A_DQS#6

DDR_A_DQS#4

12

C247

C247
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

DDR_A_MA1
DDR_A_MA3

DDR_A_MA7DDR_A_MA6
DDR_A_MA4

DDR_A_BS1
DDR_CS0_DIMMA#

DDR_B_MA11
DDR_CKE3_DIMMB

DDR_A_CAS#
DDR_A_WE#

DDR_A_BS2
DDR_CKE0_DIMMA

DDR_CKE1_DIMMA
DDR_A_MA11

Others pull-up Resistors close
DIMM Slot 750 mil ( MAX )

DDR_A_DQS2

DDR_A_DQS7

DDR_A_DQS6

DDR_A_DQS5

M_ODT0

M_ODT1

12

C236

C236
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

RN52

RN52

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN5

RN5

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN8

RN8

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN16

RN16

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN50

RN50

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN55

RN55

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN4

RN4

1
2 3

SRN56J-4-GP

SRN56J-4-GP

12

C233

C233
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

+0.9V_DDR_VTT

D

4

4

4

4

4

4

4

V_DDR_MCH_REF

12

C235

C235
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

(Reverse Type)
DIMM 1(BOT side)

DIMM 2(BOT side)

12

C238

C238
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

12

TC11

TC11
ST220U4VDM-23GP

ST220U4VDM-23GP

DY

DY

DDR_B_MA11
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#

DDR_CS1_DIMMA#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
M_ODT0
M_ODT1

DDR2-SODIMM1

DDR2-SODIMM1

DDR2-SODIMM1

Siberia

Siberia

Siberia

DDR_B_MA11 9,14
DDR_CKE3_DIMMB 8,14

DDR_CS0_DIMMA# 8
DDR_CS1_DIMMA# 8
DDR_CKE0_DIMMA 8
DDR_CKE1_DIMMA 8
DDR_A_RAS# 9
DDR_A_CAS# 9
DDR_A_WE# 9
M_ODT0 8
M_ODT1 8

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

SC

SC

13 50Friday, May 25, 2007

13 50Friday, May 25, 2007

13 50Friday, May 25, 2007

SC

of

of

of

A

M_CLK_DDR3 and M_CLK_DDR#3
can map to Row/Rank 2

M_CLK_DDR#38
M_CLK_DDR38

M_CLK_DDR#28
M_CLK_DDR28

4 4

DDR_B_CAS#

DDR_B_RAS#

DDR_B_WE#

109

108

113

WE#

RAS#

CAS#

A0

3 3

102A1101A2100

DDR_B_MA0

DDR_B_MA1

DDR_B_MA2

DDR_B_MA3

MEM_SCLK13,18,31
MEM_SDATA13,18,31

DDR_CKE3_DIMMB

DDR_CKE2_DIMMB

DDR_CS3_DIMMB#

DDR_CS2_DIMMB#

80

110

115

CS0#

CS1#

CKE079CKE1

A399A498A597A694A792A893A991A10/AP

DDR_B_MA6

DDR_B_MA7

DDR_B_MA8

DDR_B_MA9

DDR_B_MA4

DDR_B_MA5

M_CLK_DDR2

30

CK0

105

DDR_B_MA10

M_CLK_DDR#2

32

CK0#

A1190A1289A13

DDR_B_MA11

M_CLK_DDR3

M_CLK_DDR#3

164

166

CK1

DM010DM126DM252DM367DM4

CK1#

A1486A1584A16/BA2

85

116

DDR_B_BS2

DDR_B_MA12

DDR_B_MA13

DDR_B_MA14

DDR_B_DM7

DDR_B_DM5

DDR_B_DM3

DDR_B_DM2

107

DDR_B_BS0

BA0

DDR_B_BS1

MEM_SDATA

MEM_SCLK

197

199

195

130

147

170

185

SCL

SDA

DM5

DM6

DM7

VDDSPD

BA1

DQ05DQ17DQ217DQ319DQ44DQ56DQ614DQ716DQ823DQ925DQ1035DQ1137DQ1220DQ1322DQ1436DQ1538DQ1643DQ1745DQ1855DQ1957DQ2044DQ2146DQ2256DQ2358DQ2461DQ2563DQ2673DQ2775DQ2862DQ2964DQ3074DQ3176DQ32

106

DDR_B_D6

DDR_B_D7

DDR_B_D2

DDR_B_D3

DDR_B_D1

DDR_B_D4

DDR_B_D5

DDR_B_D0

DDR_B_D8

DDR_B_DM4

DDR_B_DM6

DDR_B_DM1

DDR_B_DM0

DDR_SEL_B0

DDR_SEL_B1

198

SA0

DDR_B_D10

DDR_B_D9

R611

R611
10KR2J-3-GP

10KR2J-3-GP

1 2

PM_EXTTS#1

200

SA1

NC#5050NC#6969NC#83

DDR_B_D11

DDR_B_D12

B

R612

R612

12

10KR2J-3-GP

10KR2J-3-GP

12

12

C266

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

PM_EXTTS#1 8

+1.8V_SUS

120

83

163

NC#120

NC#163/TEST

REVERSE TYPE

DDR_B_D18

DDR_B_D19

DDR_B_D16

DDR_B_D17

DDR_B_D14

DDR_B_D13

DDR_B_D15

VDD81VDD82VDD87VDD88VDD95VDD96VDD

DDR_B_D22

DDR_B_D20

DDR_B_D21

DDR_B_D23

DDR_B_D24

103

DDR_B_D25

C266

104

111

112

117

118

VDD

DDR_B_D26

VSS3VSS8VSS9VSS12VSS15VSS18VSS21VSS24VSS27VSS28VSS33VSS34VSS39VSS40VSS41VSS42VSS47VSS48VSS53VSS54VSS59VSS60VSS65VSS66VSS71VSS72VSS77VSS78VSS

VDD

VDD

VDD

VDD

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

123

125

135

137

124

126

134

DDR_B_D38

DDR_B_D36

DDR_B_D37

DDR_B_D34

DDR_B_D35

DDR_B_D32

DDR_B_D27

DDR_B_D33

DDR_B_D30

DDR_B_D31

DDR_B_D28

DDR_B_D29

C

+3.3V_RUN

C263

C263
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

136

141

143

151

153

140

142

152

154

DDR_B_D39

DDR_B_D42

DDR_B_D43

DDR_B_D41

DDR_B_D46

DDR_B_D44

DDR_B_D45

DDR_B_D40

DDR_B_D47

High 11mm

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

157

159

173

175

158

160

174

176

DDR_B_D54

DDR_B_D55

DDR_B_D52

DDR_B_D53

DDR_B_D50

DDR_B_D51

DDR_B_D48

DDR_B_D49

DDR_B_D56

179

DQ56

181

DDR_B_D57

DQ57

189

DDR_B_D58

DQ58

191

DDR_B_D59

121

DQ59

180

DDR_B_D60

122

DQ60

182

DDR_B_D61

127

VSS

DQ61

192

DDR_B_D62

128

VSS

DQ62

194

DDR_B_D63

132

VSS

DQ63

133

138

VSS

VSS

DQS0#11DQS1#29DQS2#49DQS3#68DQS4#

DDR_B_DQS#1

DDR_B_DQS#0

VSS

D

DDR_B_DM[7..0]

DDR_B_DQS[7..0]

DDR_B_DQS#[7..0]

DDR_B_D[63..0]

DDR_B_BS[2..0]

DDR_B_MA[14..0]

201

139

144

145

149

150

155

156

161

162

165

168

171

172

177

178

183

184

187

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

DQS5#

DQS6#

DQS7#

DQS013DQS131DQS251DQS370DQS4

DQS5

DQS6

DQS7

ODT0

129

146

167

186

DDR_B_DQS#2

DDR_B_DQS#3

DDR_B_DQS#4

DDR_B_DQS#5

DDR_B_DQS#6

DDR_B_DQS#7

131

148

169

188

DDR_B_DQS0

DDR_B_DQS1

DDR_B_DQS2

DDR_B_DQS7

DDR_B_DQS3

DDR_B_DQS4

DDR_B_DQS5

DDR_B_DQS6

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

114

M_ODT2

C270

C270

119

M_ODT3

190

VSS

ODT1

VSS

193

VSS

VREF1VSS

12

196

2

VSS

NP1

202

GND

NP1

NP2

DIM2

DIM2
DDR2-200P-33-GP

DDR2-200P-33-GP

GND

62.10017.D41

62.10017.D41

NP2

V_DDR_MCH_REF

12

DDR_B_DM[7..0] 9

DDR_B_DQS[7..0] 9

DDR_B_DQS#[7..0] 9

DDR_B_D[63..0] 9

DDR_B_BS[2..0] 9

DDR_B_MA[14..0] 9,13

C269

C269
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

E

+1.8V_SUS

12

C249

C249
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

DY

2 2

12

C315

C315
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C309

C309
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1 1

12

C237

C237
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

DY

12

C312

C312
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C255

C255
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

A

12

C748

C748
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

DY

12

C311

C311
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Pleace use One Capacitor close to
every Two pull-up Resistors

12

C256

C256
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C276

C276
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Pleace close to the DIMM Slot

+0.9V_DDR_VTT

12

C310

C310
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C253

C253
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C275

C275
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C313

C313
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C254

C254
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C277

C277
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C298

C298
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C268

C268
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

B

12

C285

C285
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C264

C264
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C284

C284
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SWAP

M_CKE[3:2] and M_CS[3:2]#
pull-up Resistors close DIMM
Slot 1300 mil ( MAX )

12

C278

C278
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

DDR_B_MA14

DDR_B_MA3
DDR_B_MA1

M_ODT3
DDR_B_MA13

DDR_CKE2_DIMMB
DDR_B_BS2

DDR_B_MA5

M_ODT2
DDR_CS2_DIMMB#

DDR_B_BS1

C

R186

R186

1 2

56R2J-4-GP

56R2J-4-GP

RN13

RN13

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN22

RN22

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN10

RN10

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN12

RN12

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN21

RN21

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN19

RN19

1
2 3

SRN56J-4-GP

SRN56J-4-GP

12

C747

C747
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

+0.9V_DDR_VTT +0.9V_DDR_VTT

DDR_A_BS0
DDR_A_MA10

4

4

4

4

4

4

DDR_B_MA12
DDR_B_MA9

DDR_B_MA4
DDR_B_MA2

DDR_B_MA7
DDR_B_MA6

DDR_B_CAS#DDR_B_MA8
DDR_CS3_DIMMB#

DDR_B_MA10
DDR_B_BS0

DDR_B_RAS#
DDR_B_WE#DDR_B_MA0

Others pull-up Resistors close
DIMM Slot 750 mil ( MAX )

12

C280

C280
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

RN51

RN51

1
2 3

1
2 3

1
2 3

1
2 3

1
2 3

1
2 3

1
2 3

SRN56J-4-GP

SRN56J-4-GP

RN11

RN11

SRN56J-4-GP

SRN56J-4-GP

RN18

RN18

SRN56J-4-GP

SRN56J-4-GP

RN17

RN17

SRN56J-4-GP

SRN56J-4-GP

RN15

RN15

SRN56J-4-GP

SRN56J-4-GP

RN14

RN14

SRN56J-4-GP

SRN56J-4-GP

RN20

RN20

SRN56J-4-GP

SRN56J-4-GP

D

4

4

4

4

4

4

4

12

C749

C749
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

12

TC12

TC12
ST220U4VDM-23GP

ST220U4VDM-23GP

DY

DY

DDR_A_BS0
DDR_A_MA10

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
M_ODT2
M_ODT3

DDR2-SODIMM2

DDR2-SODIMM2

DDR2-SODIMM2

Siberia

Siberia

Siberia

DDR_A_BS0 9,13
DDR_A_MA10 9,13

DDR_CS2_DIMMB# 8
DDR_CS3_DIMMB# 8
DDR_CKE2_DIMMB 8
DDR_CKE3_DIMMB 8,13
DDR_B_RAS# 9
DDR_B_CAS# 9
DDR_B_WE# 9
M_ODT2 8
M_ODT3 8

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SC

SC

14 50Friday, May 25, 2007

14 50Friday, May 25, 2007

14 50Friday, May 25, 2007

E

SC

of

of

of

A

PCIE_MTX_GRX_N[15..0]8

PCIE_MTX_GRX_P[15..0]8

+3.3V_RUN

12

12

C552

SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

4 4

3 3

2 2

1 1

C552

A

12

C573

C573
SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

C551

C551

SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

+GFX_PWR_SRC

SCD1U50V3KX-GP

SCD1U50V3KX-GP

+3.3V_SUS

C519

C519

+12V_ALW

RUNPWROK33,39,42

+2.5V_RUN

12

1 2

R730 0R2J-2-GPR730 0R2J-2-GP

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1

PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3

PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4

PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5

PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6

PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7

PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8

PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9

PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10

PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11

PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12

PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13

PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14

PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

12

C518

C518
SCD1U50V3KX-GP

SCD1U50V3KX-GP

+3.3V_GFX

B

B

SKT1

SKT1

NP1

201 202

1

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203 204

NP2

JAE-CONN200A-4-GP-U

JAE-CONN200A-4-GP-U

20.F0988.200

20.F0988.200

2

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SPDIF_D

GFX_FAN1_PWR

GFX_FAN2_PWR

GFX_FAN1_TACH
GFX_FAN2_TACH

GFX_GPU2_EN
GFX_GPU2_PG
GFX_LCD_TST

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_N0

PCIE_MRX_GTX_P1
PCIE_MRX_GTX_N1

PCIE_MRX_GTX_P2
PCIE_MRX_GTX_N2

PCIE_MRX_GTX_P3
PCIE_MRX_GTX_N3

PCIE_MRX_GTX_P4
PCIE_MRX_GTX_N4

PCIE_MRX_GTX_P5
PCIE_MRX_GTX_N5

PCIE_MRX_GTX_P6
PCIE_MRX_GTX_N6

PCIE_MRX_GTX_P7
PCIE_MRX_GTX_N7

PCIE_MRX_GTX_P8
PCIE_MRX_GTX_N8

PCIE_MRX_GTX_P9
PCIE_MRX_GTX_N9

PCIE_MRX_GTX_P10
PCIE_MRX_GTX_N10

PCIE_MRX_GTX_P11
PCIE_MRX_GTX_N11

PCIE_MRX_GTX_P12
PCIE_MRX_GTX_N12

PCIE_MRX_GTX_P13
PCIE_MRX_GTX_N13

PCIE_MRX_GTX_P14
PCIE_MRX_GTX_N14

PCIE_MRX_GTX_P15
PCIE_MRX_GTX_N15

GFX_GPU1_PG
LCDVCC_TST_EN

12

GFX_PWR_LIMIT

C

PCIE_MRX_GTX_N[15..0] 8
PCIE_MRX_GTX_P[15..0] 8

+5V_ALW

LCD_SMBCLK 33

1 2

1 2

1 2
1 2

PLTRST_DELAY# 18

CLK_PCIE_VGA 4
CLK_PCIE_VGA# 4

LCDVCC_TST_EN 33

THERMTRIP_VGA# 20

+5V_RUN

12

C568

C568

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

LCD_SMBDAT 33

12

12

12

10KR2J-3-GP

10KR2J-3-GP

12

12

12

C553

C553

SCD1U50V3KX-GP

SCD1U50V3KX-GP

+3.3V_RUN

R383

R383

1 2

DY

DY

0R2J-2-GP

0R2J-2-GP

C

C76

C76

5

4

R347 0R3-0-U-GPR347 0R3-0-U-GP

R59 0R3-0-U-GPR59 0R3-0-U-GP

R310 0R2J-2-GPR310 0R2J-2-GP
R57 0R2J-2-GPR57 0R2J-2-GP

R56 0R2J-2-GPR56 0R2J-2-GP
R55 0R2J-2-GPR55 0R2J-2-GP
R350 0R2J-2-GPR350 0R2J-2-GP

+3.3V_RUN

R354 0R2J-2-GPR354 0R2J-2-GP

C75

C75

R346

R346

FAN2_OUT 20

FAN3_OUT 29

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

GFX_GPU2_ON 34

LCD_TST 34

+3.3V_RUN

12

R357

R357

GFX_GPU1_PWRGD 34

PANEL_BKEN 34

+GFX_PWR_SRC

12

C78

C78
SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

U11

U11

VCC

Y

74LVC1G08GW-1-GP

74LVC1G08GW-1-GP

GND

1

B

2

A

3

D

+5V_RUN

U81

C550

C550

1 2

SCD1U10V2KX-4GP

RUN_ON33,38,39,46

SCD1U10V2KX-4GP

SPDIF_D_1

+3.3V_RUN

12
12

FAN2_TACH 33
FAN3_TACH 33

+3.3V_RUN

12

R54

R54

10KR2J-3-GP

10KR2J-3-GP

+PWR_SRC +GFX_PWR_SRC

12

R378

R378

100KR2J-1-GP

100KR2J-1-GP

G

D

12

0R2J-2-GP

0R2J-2-GP

R306 10KR2J-3-GPR306 10KR2J-3-GP
R61 10KR2J-3-GPR61 10KR2J-3-GP

12

C512

C512

DY

DY

For current design card:
Depop R55-R57,R59, R310,R346,R347,R350,R354.
For new design card:
Pop R55-R57,R59, R310,R346,R347,R350,R354.

12

C79

C79
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

DY

DY

ACAV_IN 20,33,41

SIO_GFX_PWR 20

U81

5

4

74AHCT1G125GW-1-GP

74AHCT1G125GW-1-GP

GFX_GPU2_PWRGD 34

350mil 350mil

12

C87

C87
SCD1U50V3KX-GP

SCD1U50V3KX-GP

GFX_PWR_G

12

R386

R386
100KR2J-1-GP

100KR2J-1-GP

GFX_PWR_GR

Q6

Q6
2N7002-7F-GP

2N7002-7F-GP

S D

E

VCC

Y

OE#

GND

1

2

A

3

12

R738

R738
10KR2J-3-GP

10KR2J-3-GP

SPDIF_SHDN 34

AUD_SPDIF_OUT 24

0SC

U10

U10

S

S

D

1
2
3
4 5

1
2
3
4 5

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

D

S

S
S

S
GD

GD

SI4435BDY-T1-1GP

SI4435BDY-T1-1GP

U9

U9

S

S
S

S
S

S
GD

GD

SI4435BDY-T1-1GP

SI4435BDY-T1-1GP

Id=5.6A
Rdson=15~20mohm

8

D

D

7

D

D

6

D

D

8

D

D

7

D

D

6

Graphic CONN.

Graphic CONN.

Graphic CONN.

Siberia

Siberia

Siberia

12

C73

C73
SCD1U50V3KX-GP

SCD1U50V3KX-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

12

C81

C81
SCD1U50V3KX-GP

SCD1U50V3KX-GP

15 50Friday, May 25, 2007

15 50Friday, May 25, 2007

15 50Friday, May 25, 2007

of

of

of

SC

SC

SC

A

+PWR_SRC

B

C

D

E

RTC circuitry

12

C366

C366
SC1U25V5KX-1GP

U59

U59

1
2
MH1
MH2

GND

OUT

1

IN

2
3

+RTC

5

SHDN#

4

5/3#(FB)

MAX1615EUK-GP

4 4

3 3

2 2

MAX1615EUK-GP

DY

DY

RTC1

RTC1

PWR

GND
MH1
MH2

BAT-CON2-U2-GP

BAT-CON2-U2-GP

22.70031.001

22.70031.001

Place all series terms close to
ICH8 except for SDIN input lines,
which shoud be close to source.

ICH8-Strap PIN

SPKR

SPKR18,24

ACZ_DOUT

ICH_RSVD18

1 1

ICH_RSVD

12

12

SC1U25V5KX-1GP

DY

DY

+3.3V_RTC_LDO

12

RB751V-40-1-GP

RB751V-40-1-GP

C381

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

This circuit is only
needed if the platform
has the SNIFFER

R650

R650
330KR2F-L-GP

330KR2F-L-GP

ICH_INTVRMEN

R663

R663
0R2J-2-GP

0R2J-2-GP

DY

DY

A

C381

+RTC_VCC

R240

R240

1 2

1KR2J-1-GP

1KR2J-1-GP

LED_MASK#31,34

SATA_ACT#32

R643 1KR2J-1-GP

R643 1KR2J-1-GP

1 2

R682 1KR2J-1-GP

R682 1KR2J-1-GP

1 2

R679 1KR2J-1-GP

R679 1KR2J-1-GP

1 2

+RTC_CELL+RTC_CELL

12

ICH_LAN100_SLP

12

RB751V-40-1-GP

RB751V-40-1-GP

DY

DY
DY

DY

DY

DY

R628

R628
330KR2F-L-GP

330KR2F-L-GP

R629

R629
0R2J-2-GP

0R2J-2-GP

DY

DY

D17

D17

D16

D16

ICH_AZ_CODEC_BITCLK24

ICH_AZ_CODEC_SYNC24

ICH_AZ_CODEC_RST#24

ICH_AZ_CODEC_SDOUT24

+RTC_CELL

21

21

12

G

Q55

Q55
2N7002-7F-GP

2N7002-7F-GP

R690

R690

1 2

DY

DY

0R2J-2-GP

0R2J-2-GP

+3.3V_RUN

1 2

20KR2J-L2-GP

20KR2J-L2-GP

R674

R674
1MR2J-1-GP

1MR2J-1-GP

+3.3V_RUN

SD

12

C797

C797
SC1U10V3KX-3GP

SC1U10V3KX-3GP

R675

R675

ICH_RTCRST#

12

C799

C799
SC1U10V3KX-3GP

SC1U10V3KX-3GP

ICH_INTRUDER#

ICH_AZ_CODEC_BITCLK

ICH_AZ_CODEC_SYNC

ICH_AZ_CODEC_RST#

ICH_AZ_CODEC_SDOUT

12

R685

R685
10KR2J-3-GP

10KR2J-3-GP

SATA_ACT#_R

No Reboot Strap

SPKR LOW = Defaule

High=No Reboot

XOR Chain Entrance Strap

ICH_RSVD

0
0

11

ACZ_DOUT

0
1
01

integrated VccSus1_05,VccSus1_5,VccCL1_5

ICH_INTVRMEN

High=Enable Low=Disable

integrated VccLan1_05VccCL1_05

ICH_LAN100_SLP

High=Enable Low=Disable

B

CL=6pF
Freq. Tolerance:±10ppm

1 2

R216 10MR3J-L1-GPR216 10MR3J-L1-GP

X3

X3

3 2

X-32D768KHZ-39GP

X-32D768KHZ-39GP

12

C348

C348

SC3D3P50V2CN-GP

SC3D3P50V2CN-GP

R223 33R2J-2-GPR223 33R2J-2-GP

1 2

R222 33R2J-2-GPR222 33R2J-2-GP

1 2

R680 33R2J-2-GPR680 33R2J-2-GP

1 2

12

C385

C385
SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

DY

DY

R681 33R2J-2-GPR681 33R2J-2-GP

1 2

SATA_RX0-21

SATA_RX0+21
SATA_TX0-21
SATA_TX0+21

SATA_RX2-21

SATA_RX2+21
SATA_TX2-21
SATA_TX2+21

Distance between the ICH8-M and
cap on the "P" signal should be
identical distance between the
ICH8-M and cap on the "N"
signal for same pair.

Description

RSVD

Enter XOR Chain
Normal Operation(default)
Set PCIE port cofig bit1

DY

DY

SC3D3P50V2CN-GP

SC3D3P50V2CN-GP

+3.3V_RUN

ICH_RTCX1

ICH_RTC_X2

14

12

C355

C355

DY

DY

+1.5V_PCIE_ICH

GLAN_COMP place within 500 mil of ICH8M

ICH_AZ_CODEC_SDIN024

AUD_SPK_DET#25

1 2

R731 100KR2J-1-GPR731 100KR2J-1-GP

C790 SC3900P50V3KX-GPC790 SC3900P50V3KX-GP

1 2

C789 SC3900P50V3KX-GPC789 SC3900P50V3KX-GP

1 2

C791 SC3900P50V3KX-GPC791 SC3900P50V3KX-GP

1 2

C792 SC3900P50V3KX-GPC792 SC3900P50V3KX-GP

1 2

1 2

R220

R220

TP121TP121

1 2

R597 24D9R2F-L-GPR597 24D9R2F-L-GP

TP118TP118

TP114TP114
TP109TP109

TP116TP116
TP120TP120

CLK_PCIE_SATA#4
CLK_PCIE_SATA4

C

ICH_RTCX2

0R2J-2-GP

0R2J-2-GP

ICH_RTCRST#

ICH_INTRUDER#

ICH_INTVRMEN
ICH_LAN100_SLP

GLAN_DOCK#

GLAN_COMP

ACZ_BITCLK
ACZ_SYNC

ACZ_RST#

ICH_AZ_CODEC_SDIN0
ICH_AZ_MDC_SDIN1

ICH_AZ__SDIN2
ICH_AZ__SDIN3

ACZ_DOUT

SATA_ACT#_R

SATA_RX0­SATA_RX0+
SATA_TX0-_C
SATA_TX0+_C

SATA_TX1-_C
SATA_TX1+_C

SATA_RX2­SATA_RX2+
SATA_TX2-_C
SATA_TX2+_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

1 2

R211 24D9R2F-L-GPR211 24D9R2F-L-GP

SM_SATASB Place
within 500 mil
of ICH8-M

SM_SATASB

SIO_A20GATE

SIO_RCIN#

1 OF 6

1 OF 6

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

R634

R634

1 2

R229

R229

1 2

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

RTC

RTC

LAN/GLAN

LAN/GLAN

IHDA

IHDA

SATA

SATA

+3.3V_RUN

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

LPC

LPC

A20GATE

DPRSTP#

CPUPWRGD/GPIO49

CPU

CPU

THRMTRIP#

IDE

IDE

D

U39A

U39A

LPC_LAD0

E5

LPC_LAD1

F5

LPC_LAD2

G8

LPC_LAD3

F6

LPC_FRAME#

C4

LPC_DRQ0#

G9

LDRQ0#

A20M#

DPSLP#

FERR#

IGNNE#

INIT#
INTR

RCIN#

NMI

SMI#

STPCLK#

TP8

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DA0

DA1

DA2

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

LPC_DRQ1#

E6

SIO_A20GATE

AF13

H_A20M#

AG26

H_DPRSTP#

AF26

H_DPSLP#

AE26

H_FERR#

AD24

H_PWRGOOD

AG29

H_IGNNE#

AF27

H_INIT#

AE24

H_INTR#

AC20

SIO_RCIN#

AH14

H_NMI#

AD23

H_SMI#

AG28

H_STPCLK#

AA24

THERMTRIP#_ICH

AE27

AA23

IDE_DD0

V1

IDE_DD1

U2

IDE_DD2

V3

IDE_DD3

T1

IDE_DD4

V4

IDE_DD5

T5

IDE_DD6

AB2

IDE_DD7IDE_DD7

T6

IDE_DD8

T3

IDE_DD9

R2

IDE_DD10

T4

IDE_DD11

V6

IDE_DD12

V5

IDE_DD13

U1

IDE_DD14

V2

IDE_DD15

U6

IDE_DA0

AA4

IDE_DA1

AA1

IDE_DA2

AB3

IDE_DCS1#

Y6

IDE_DCS3#

Y5

IDE_DIOR#

W4

IDE_DIOW#

W3

IDE_DDACK#

Y2

IDE_IRQ

Y3

IDE_DIORDY

Y1

IDE_DDREQ

W5

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet of

ICH8M-RTC/IDE/LPC/DHI (1/4)

ICH8M-RTC/IDE/LPC/DHI (1/4)

ICH8M-RTC/IDE/LPC/DHI (1/4)

A3

A3

A3

LPC_LAD0 33
LPC_LAD1 33
LPC_LAD2 33
LPC_LAD3 33

LPC_FRAME# 33

TP101TP101
TP95TP95

SIO_A20GATE 33

H_A20M# 5

H_DPRSTP# 5,8,42
H_DPSLP# 5

H_FERR# 5

H_PWRGOOD 5

H_IGNNE# 5

H_INIT# 5
H_INTR# 5

SIO_RCIN# 33

H_NMI# 5
H_SMI# 5

H_STPCLK# 5

56 ohm must be place within 2"of stub

TP104TP104

IDE_DA0 21
IDE_DA1 21
IDE_DA2 21

IDE_DCS1# 21
IDE_DCS3# 21

IDE_DIOR# 21
IDE_DIOW# 21
IDE_DDACK# 21

IDE_IRQ 21
IDE_DIORDY 21
IDE_DDREQ 21

Siberia

Siberia

Siberia

+1.05V_VCCP

IDE_DD[15..0] 21

56R2J-4-GP

56R2J-4-GP

H_DPRSTP#
H_DPSLP#

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

12

R637

R637
56R2J-4-GP

56R2J-4-GP

R649

R649

DY

DY

16 50Friday, May 25, 2007

16 50Friday, May 25, 2007

16 50Friday, May 25, 2007

+1.05V_VCCP

12

12

R641

R641
56R2J-4-GP

56R2J-4-GP

DY

DY

of

of

SC

SC

SC