5
D D
4
3
2
1
ATOM 230 +945GC + ICH7R
VRM 11.X
Intersil 6312
DEBUG BD
CONNECTOR
C C
NAND
Flash
B B
A A
Flash Controller
SM321
Front I/O Board
Front USB(SB
Port7)
VGA output
Keyboard/Mouse
COM Port
Front USB(SB
Port6)
REAR
LAN
Port-RJ45
connector
USB(SB Port 0)
USB(SB Port 1)
REAR
USB(SB Port 2)
USB(SB Port 3)
R,G,B
USB 2.0
PCI-E X4 SLOT
100MHz/100MHz#
DOT/DOT#
96MHz/96MHz#
(USB SB Port 4)
USB 2.0
PCI-E X4
88SE6111
E-SATA CN
BALL GRID ARRAY (BGA)
ATOM230
SOLDER DOWN PROCESSOR
CTRL
ADDR
ADDR
DATA
DATA
CTRL
Intel
LAKE PORT 945GC
GRAPHICS MEMORY
CONTROLLER HUB
DMI
DMI
100MHz/100MHz#
Intel
ICH7R
BP BD
HD*4
SPI
Control
Serial BIOS
Flash (SPI)
PCI-E
SATA X 4
SATA
Connector*4
Block Diagram
Channel A
DDR2
533/667
48MHz
33MHz
14.318MHz
32.768KHz
PCI-E
LPC Bus
Front IO Board
USB ConnectorX2
Power Indicator LED X1
System Health LED X1
Link Status LED X1
Reset Button Switch
X1
DIMM 0
25MHz
LAN
88E8071
Clock CK-410
SYSTEM
FAN
14.318MHz
100MHz/100MHz#
96MHz/96MHz#
Super
I/O
SMSC SCH5127
SYSTEM
Tmperature
FAN
Monitor
48MHz
33MHz
14.318MHz
REAR
LAN Port-RJ45
connector
33MHz
14.318MHz
32.768KHz
Voltage
Monitor
PAGE INDEX
Sheet 1
Sheet 2
Sheet 3
Sheet 4
Sheet 5
Sheet 7
Sheet 8
Sheet 9
Sheet 10
Sheet 11
Sheet 12
Sheet 13
Sheet 14
Sheet 15
Sheet 16
Sheet 17
Sheet 18
Sheet 19
Sheet 20
Sheet 21
Sheet 22
Sheet 23
Sheet 24
Sheet 25
BlOCK DIAGRAM & PAGE INDEX
REVISION HISTORY
POWER DISTRIBUTION
CLOCK DISTRIBUTION
PCB STACK_UP
RESET & PWRGD MAP
GPIO & IRQ & SMBUS SETTING
CPU 1 OF 3
CPU 2 OF 3
CPU 3 OF 3
CPU DECOUPLING CAPS
MCH PCIE/FSB/DMI 1 OF 6
MCH DDR2 A 2 OF 6
MCH DDR2 B 3 OF 6
MCH MISC 4 OF 6
MCH POWER 5 OF 6
MCH POWER 6 OF 6
MCH 2P5_DAC & PLL FILTERS
MCH DECOUPLING & COM P
MCH &DIMM VREF & COMP
MCH DCPL & VGA TERMINATION
240P CONN DDR2 CH A
DDR VTT TERMINATION
DDR VTT DECOUPLING
CK_410
Sheet 26
Sheet 27
Sheet 28
Sheet 29
Sheet 30
Sheet 31Sheet 6
Sheet 32
Sheet 33
Sheet 34
Sheet 35
Sheet 36
Sheet 37
Sheet 38
ICH7 SECTIONS 1&2 OF 6
ICH7 SECTION 3 OF 6
ICH7 SECTION 4 OF 6
ICH7 POWER 5&6 OF 6
MISC DECOUPLING
ICH PULL UP
SPI FLASH
SATA CONNECTOR
PCI TERMINATION
LAN 88E8071
USB CONN
E-SATA CONTROLLE R
SUPER I/O SMSC5127
FLASH CONTROLLER SMI321Sheet 39
Sheet 40
Sheet 41
Sheet 42
Sheet 43
Sheet 44
Sheet 45
Sheet 46
Sheet 47
PCIE & OTHER CONNECTOR
DEBUG BD CONNECTOR
FRONT IO BD CONNECTOR
ITP-XDP
POWER VCCP VREG CONTROLLER
POWER V_1P5_SFR & BATTERY
POWER DECOUPLING & STITCHING
POWER V_SM
Sheet 48 POWER 1P5 1P05 3P3_STB
Sheet 49 POWER VTT 5VDUAL 2P5_MCH
Sheet 50 GLUC LOGIC
<Variant Name>
Title
BlOCK DIAGRAM & PAGE INDEX
Size Document Number Rev
S15
A2
5
4
3
2
Date: Sheet of
1
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
150Friday, December 12, 2008
-1
5
Rev. History
4
3
2
1
RevDATE Description
0725 SA Add C493~C509 for EMI solution
0729 SA
D D
0730 SA
C C
0731
B B
0804
A A
0806 SA
0808 SA
R152,R154~R160 change to Dummy on page 27
R8 change to 0 ohm on page 9
R10 change to 1.2K ohm on page 9
R52,R54 change to Dummy on page 19
change R69,R70,R71 to 150 Ohm on page 21
change R69,R70,R71 to 150 Ohm on page 21
change R340,R342,R344 to 150 Ohm on page 41
change R340,R342,R344 to 150 Ohm on page 41
R129 to 33 ohm on page 25
R129 to 33 ohm on page 25
delete Net CK410_VDDPCI,and change to VDD_SRC_CLKA on page 25
delete Net CK410_VDDPCI,and change to VDD_SRC_CLKA on page 25
change R146 to DUMMY on page25
change R146 to DUMMY on page25
delete TP48,TP49 and add R610,R611 on page 26
delete TP48,TP49 and add R610,R611 on page 26
ADD R612,R613 on page 28
ADD R612,R613 on page 28
Change R392 value from 35.7k to 11k
Add C8 to reduce noise on current sense amplifier
Add R405(11.3KR)
Add C345 (1000PF)
Change R407 from 2.1K to 10KR
Change C343 from 15nF to 820PF
Change C341 from 180P to 100P
Change R385 from 10k to 16.9kR
Add R422 for power source filter
Delete R592 and R579
Change R575 from 2.1K to 3KR
Add C379, C387 (10uF) for V_SM
Add C389 and C390 (10uF) for V_1 P5 _C O R E
Change R593 from 10KR to 12KR
Change C477 from 4700pF to 10nF
Change R596 from 18KR to 24KR
Change R580 from 10KR to 15KR
Change C468 form 4700pF to 10nF
Change C583 from 18KR to 22KR
Change R391 to 470R
Delete TP122 and add R614, JP3 on page28
change R600 pin2 from net ICH_VRMPWRGD_PU to ICH_THRM_PU_N on page 38
SA
R194,R195,R196 mount 8.2K on page 32
R529 change from 560K to 15K on page 35
R526 change from 560K to 15K on page 36
R347 change from 560K to 15K on page 36
Delete TP119 and TP120, chagne net TP119 and TP 120 to ICH_GPIO38 and ICH_GPIO39 and pull high to VCC3 on
page28
delete R170 change to 10K on page 28
delete R287
delete C184
R176 change to Dummy,for VRM's power good already pull high
change C439 & R475 power source from VCC to V_5P0_STBY\G on page 50
Add D4 for Intel Recommend
R492,R495, C444change to Dummy
Add R617 and connector to ICH_VRMPWRGD_PU
TC3,TC4,TC5-SE560U2D5VM-GP EOL change to SE560U2D5VM-1-GP ON PAGE44
SA
change USBP8+,USBP8- to ICH7 port 7,change USB_FRONT1 and USB_FRONT2 to ICH port 4,5 ON PAGE26
delete net USB_OC4#_PULL_UP,USB_OC5#_PULL_UP,USB_OC_FRONT_67, CHANGE TO
USB_OC6#_PULL_UP,USB_OC7#_PULL_UP,USB_OC_FRONT_12 ON PAGE26
IND-1UH-64-GP change to IND-1UH-41-GP-U ON PAGE 48
U25 AT24C08AN-1-GP EOL change to AT24C08BN-SH-T-GP ON PAGE35
Add R226 Dummy, and connector to ICH_GPIO12 ON PAGE 28
R604 change to Dummy on page 38
Add R618 pull high to V_3P3_STBY\G on page38
Add C510 on page38
Change the U14 power source from V_SM to VCC3 on page 45
Change JR1 library,add L6,R623~R626
F6 ,F7 FUSE-1D5A6V-7GP EOL change to 69.50007.961
SA0811
change the SMI321 write protect from ICH_GPIO14 to ICH_GPIO6,because of power plane issue
Add R627
Add stitching caps C515,C516,C517,C518
change net RESET_BUTTON from SIO GP54 to ICH_GPIO10,Add SIO GP54 to TP138
Delete R551(pull high to VCC3)
SA0812
Add C519
5
V_SM
V_1P5_CORE
4
DATE Rev Description
0812 SA
0813 SA
0814
1002 1A Change V_SM controller source to 5VDUAL (P.47)
1014
1212
3
Delete net SDVO_CTRL_DATA,SDVO_CTRL_CLK,R325,R326
U47 change from AO4422-1-GP(N-MOS) to P2003EVG-GP(P-MOS),delete Q31,R608,delete net
VUSB_PU2
Add R628
Q29 OPEN for Intel recommend
SA
Q33 OPEN for Intel recommend
Q8 OPEN
Correct on Board flash USB interface
Add L7 to connect 1.2V power to E-SATA IC (P.37)
Correct U8 to CN10 trace name for Marvell 88SE6111
Add R232 R255 Dummy resistor to disconnect HDD Power control by SIO
Correct Front panel LAN LED control by LAN Active Pin (P.35)
Add C9 to reserve HDD Power control sequency function (P.40)
Correct LAN LED GIGA/100M connection
Change RAID LED and Backup LED to GPIO 27, 28
Add EMI Cap (C12) for 1D8V_LAN power (P.35)
Add EMI Cap (C10, C11) for CPU 12V power source (P.44)
Add EMI Cap (C13) for CK_PE_100M_PCIE_SLOT (P.25)
1B Remove U47, C492, C491, R609, R607, C490 Q32 and connect V_5_USB to 5VDUAL to
solve USB Vbus drop issue
Re-layout CN22 Pin 13 and Pin 15 for connect 5VDUAL to Front Board
change R391 to 820R to set current limit to 8A
Remove U6 R233 C214 to connect front LAN LED to LED_LAN_ACT directly no BOM change
1B
at -1A (20081023)
For wake up issue, remove R521 and put R521 to R522
Add C14 and R233 for separate LAN connector GND from System GND
-1B Add net 1_KBDAT,1_KBCLK pull high 10K,for reserved @PAGE41
1B
Delete C14 and R233 for EMI
1
Delete net 0
Add TC21 for reserved
2
<Variant Name>
Title
REVISION HISTORY
Size Document Number Rev
S15
A2
Date: Sheet of
1
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
250Friday, December 12, 2008
-1
5
4
3
2
1
ATOM 230
VRM 11.X ON
D D
+12V
FDS6298-GP
VCC
V_5P0_STBY\G
VCC3
U42
Q59
V_3P3_STBY/G
5VDUAL
5VDUAL
ATX
POWER SUPPLY
C C
STBY/DUAL POWER
VCC
V_5P0_STBY\G
V_5P0_STBY\G
P2003EVG-GP
PMOS
V_12
ACPI Regulator
&Controller /
Switching
ISL6341
VCC3
BOARD/ISL6314
1.8V
V_SM
PWM
VCORE
APL1085
Linear
0 Ohm
(reserved)
V_1P5_CORE
1.5V
RT9199
Linear
V_SM 0.9V
LM358(Amplifer)(1/2)
Linear
LM358(Amplifer)(2/2)
LD1117DT
B B
ACPI Regulator
&Controller /
Switching
ISL6341
V_SM V_ICH_CORE
LM358(Amplifer)(2/2)
V_3P3_STBY/G
V_3P3_STBY/G
A A
V_3P3_STBY/G
LC
Filter
LAN
INTERNAL
Regulator
LAN
INTERNAL
Regulator
3D3V_LAN
1D8V_LAN
1D2V_LAN
1.5V
V_1P5_CORE
1.2V
V_5SB_DUAL
4A
0.13A
2.5A
V_5P0_STBY\G
V_1P5_SFR
V_FSB_VTT
V_FSB_VTT
V_2P5_MCH
V_1P5_CORE
V_FSB_VTT
V_1P5_CORE
V_1P5_COREVCC3
VCC3
V_3P3_STBY/G
V_ICH_CORE
V_3P3_STBY/G
V_5_USB
U47
5
4
3
Core:
0.65~1.2V
VCORE
Icc_max: 4A
S0, S1
VCCA : 1.5V +/- 0.075V
0.13A S0,S1
FSBVTT : 1.1V +/- 0.05V
2.5A S0,S1
DDR2
DIMM Channel 0
Core:1.8V+/-0.1V
V_SM
3A,S0,S1
400mA S3
V_SM_VTT
VTT:0.9V+/-0.2V
0.6A,S0,S1
420mA,S3(Vtt Up)
LAKE PORT 945GC
FSBVTT Host Termination
1.2V +/-0.06
0.9A(max) S0,S1
DDR2:1.8V +/- 0.1V
V_SM
4.1A(max) S0,S1
mA S3
DAC: 2.5V +/- 0.125V
0.1A
Core: 1.5V +/- 0.075V
15.5A S0, S1
ICH7R
FSBVTT 1.2V +/- 0.05V
14mA S0,S1
Internal Logic and I/O Buffer
1.5V +/- 0.075V
1.78A(max) S0,S1
PLL
1.5V +/- 0.075V
0.11A S0, S1
VCC3_3 3.3V +/- 0.165V
330mA(max) S0,S1
VCC
5VRef: 5.0V +/- 0.25V
6mA S0,S1
VCCSUS_3.3
3.3V +/- 0.165V
52mA S0,S1,S3,S5
VCCSUS_5
5.0V +/- 0.25V
10mA S0,S1,S3,S5
ICH7 Core(1.05V):
1.05V +/- 0.052V
0.86A S0, S1
CK-410
Clock Core&I/O:
3.3V+/-0.165V
500mA S0,S1
USB*4
USB and PS/2 cable
5V+/-0.25V
2A S0,S1
3D3V_LAN
1D8V_LAN
1D2V_LAN
V_3P3_STBY/G
VCC3
V_3P3_STBY/G
V_3P0_BAT_VREG
V_12
VCC
V_12
VCC
VCC3
VCC3
2
LAN 88E8071
VDD(3.3)
80mA
VDD(1.8)
150mA
VDD(1.2)
290mA
SPI
SPI Core:3.3V+/-0.3V
67mA S0,S1
SIO
LPC Super I/O
SMSC5127:3.3V
60mA(need ask vender)
60mA(need ask vender)
HDx4
12V
2*4=8A S0,S1
5V
2*4=8A S0,S1
SYSTEM FAN
12V
1.2A
LED
5V
100mA
SMI321
3.3V
400mA
E-SATA
1.5V
0.065A S0,S1
3.3V
0.205A S0,S1
1.2V
0.17A
<Variant Name>
Title
POWER DISTRIBUTION
Size Document Number Rev
S15
Custom
Date: Sheet
1
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
350Friday, December 12, 2008
of
-1
5
http://hobi-elektronika.net/
4
3
2
1
D D
C C
Crystal
B B
14.318MHZ
3.3 VOLT
PCI CLOCK
24/48M SEL CLOCK
LAN CLOCK
USB CLOCK
SATA CLOCK PAIR
PEIE CLOCK PAIRS
SMBUS CLOCK
REF CLOCK
33MHZ
33MHZ
33MHZ
33MHZ
48MHZ
25MHZ
25MHZ
48MHZ
100MHZ
100MHZ
100MHZ
100MHZ
100MHZ
SCLK
14.318MHZ
14.318MHZ
SPARE
SIO
SPARE
SPARE
SIO
SPARE
ICH
ICH
Crystal
LAN
32.768KHZ
CK 410
CLK
14.318KHZ
LANCLK
PCICLK
RTCCLK
USBCLK
SATACLK
88E8071
PCIEREF
VOSCI
ICH7R
XTAL
GMCH
CLK
100MHZ
PCLK100
AC_BIT_CLK
25MHZ
Crystal
533MHz
Crystal
SPARE
DDR2 DIMM0
14.318MHZ
SCLK
CLK
33MHZ
SIO
SMSC5127
SCL
PCICLK
KBCLK
MCLK
MS/KB
ZCLK
DOT_96M
HOST
SCL
SCLK
96MHZ DREF
133MHZ CPU_CK
HOST CLOCK
PAIRS
133MHZ Z_CK0
CPU
XDP PORT
A A
5
SCL
4
SCLK
<Variant Name>
Title
CLOCK DISTRIBUTION
Size Document Number Rev
S15
A3
3
2
Date: Sheet
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
450Friday, December 12, 2008
1
-1
of
5
D D
C C
4
3
2
1
B B
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
A A
Title
Hsichih, Taipei
PCB STACK_UP
Size Document Number Rev
S15
Date: Sheet of
5
4
3
2
550Friday, December 12, 2008
1
-1
5
http://hobi-elektronika.net/
4
3
2
1
V_FSB_VTT
PWRGOOD(V17)
D D
VRM
ISL6314
EN(17)
PG(1)
RESET_B(D15)
LAKEPORT
C C
HCPURST#(C30)
ATOM 230
PWROK(AJ9)
RSTIN#(AJ12)
DBR#(AC2)
ATX
PS_ON(16)
PWRGD_PS(8)
PWRGD_PS(84)
PS_ON#(92)
PWRGD_3V(84)
PCIRST~(25)
PB_OUT(99)
PB_IN(98)
POWER
BUTTON
PCIRST_OUT2(96)
PCIRST_OUT3(95)
SIO
SMSC5127
RSMRST~(100)
SLP_S3~(89)
SLP_S5~(88)
PCIEX4 SOLT
PERST#(A11)
PERST_N(53)
ESATA
CONTROLLER
B B
CMOS JUMP
A A
CPUPWRGD(AG24)
VRMPWRGD(AD22)
RCTRST#(AA3)
ACZ_RST#(R5)
ICH7R
RESET/POWER GOOD MAP
5
4
PWRBIN#(C23)
PWROK(AA4)
LAN_RST#(C19)
REMRST#(Y4)
SLP_S4#(D23)
SLP_S3#(B24)
3
Marvell LAN
PERSTn(5)PLTRST#(C26)
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
RESET & PWRGD MAP
Size Document Number Rev
S15
A3
2
Date: Sheet
<Variant Name>
Hsichih, Taipei
1
-1
of
650Friday, December 12, 2008
5
4
3
2
1
ICH 7R
DURING
RESET
-----
-----
-----
-----
-----
-----
----- -----
-----
----- -----
IN
-----
-----
-----
IN
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
----- -----
----- -----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
Enable
Setting
DESCRIPTION
-----
-----
-----
-----
-----
-----
Write protect for onboard flash
-----
BACKUP DETECT
reserved function
-----
RESET_BUTTON
-----
System Management Interrupt from
Low
SIO
PME from SIO
Low
-----
Low
MODEL_SELECT JUMPER
-----
Boot BIOS Destination
-----
Selection (SPI)
-----
-----
SYS_STATUS LED to Front Panel
Low
-----
-----
-----
SYS_ERROR LED to Front Panel
Low
PWR_LED to Front Panel
Low
RAID_LED_CTRL to Front Panel
Low
-----
-----
Overcurrent Indicators
Overcurrent Indicators (NO UESD)
Overcurrent Indicators (NO UESD)
-----
-----
BACKUP_STATUS LED
RAID_LED_CTRL2 to Front Panel
-----
-----
-----
----- -----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
----------
Boot BIOS Destination
Selection (SPI)
NOTES
10K P/U TO VCC3 ON PAGE 28
8.2K P/U TO VCC3 ON PAGE 34
8.2K P/U TO VCC3 ON PAGE 34
8.2K P/U TO VCC3 ON PAGE 34
8.2K P/U TO VCC3 ON PAGE 34
10K P/U TO VCC3 ON PAGE 31
10K P/U TO VCC3 ON PAGE 31
10K P/U TO V_3P3_STBY\G ON PAGE 28
10K P/U TO V_3P3_STBY\G ON PAGE 28
10K P/U TO V_3P3_STBY\G ON PAGE 28RESET_BUTTON
10K P/U TO V_3P3_STBY\G ON PAGE 31
10K P/U TO V_3P3_STBY\G ON PAGE 28
10K P/U TO V_3P3_STBY\G ON PAGE 19
-----
10K P/D TO GND ON PAGE 26
PULL UP 4K7 TO VCC3 ON PAGE2 7
8.2K P/U TO VCC3 ON PAGE 34
connect to TP
USB OC protect ON PAGE26
8.2K P/U TO V_3P3_STBY\G ON PAGE 26
8.2K P/U TO V_3P3_STBY\G ON PAGE 26
connect to TP
connect to TP
PULL UP 4K7 TO VCC3 ON PAGE2 7
PULL UP 4K7 TO VCC3 ON PAGE2 7
PULL UP 10K TO VCC3 ON PAGE2 8
PULL UP 10K TO VCC3 ON PAGE2 8
10K P/U TO VCC3 ON PAGE 26
PIN NAME
GPIO0 MAIN GPI
GPIO1
GPIO2
GPIO3
D D
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO17
GPIO19
GPIO20 MAIN
C C
GPIO21
GPIO22
GPIO23 MAIN NO USED Native
GPIO24
GPIO25 RESUME
GPIO26
GPIO27 GPO
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
B B
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48 MAIN
POWER
WELL
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAINGPIO18 connect to TPGPO
MAIN
MAIN
MAIN
RESUME SYS_ERROR
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
NA
NA
NA
NA
NA
NA
NA
NA
V_CPU_IOGPIO49
USAGE
NO_USED
NO_USED 8.2K P/U TO VCC3 ON PAGE 34
NO USED
NO USED
NO USED
NO USED
SMI321 Reset
NO USED
BACKUP_BUTTON
2 PIN JUMPER
SMB_ALERT_PU
SIO_SMI_N
PME_N
NO USED 10K P/U TO V_3P3_STBY\G ON PAGE 28
MODEL_SELECT
NO USED
Boot BIOS Destination
Selection (SPI)
NO_USED
NO_USED
SYS_STATUS GPO
NO_USED PULL UP 4K7 TO VCC3 ON PAGE2 7
NO_USED
PWR_LED
RAID_LED_CTRL
BACKUP_STATUS
RAID_LED_CTRL2
USB OC5ÂUSB OC6ÂUSB OC7ÂNO_USED
NO_USED
NO_USED
NO USED
NO USED
NO USED
NO USED
Not implemented.
Not implemented.
Not implemented.
Not implemented.
Not implemented.
Not implemented.
Not implemented.
Not implemented.
Boot BIOS Destination
Selection (SPI)
H_PWRGD
(Multi-function)
Default
Type
GPI
GPI
GPI
GPI
GPI
GPI
GPI
GPI
GPI
GPI
Native
GPI
GPI
GPI
GPI
GPOMAINGPIO16
GPI
GPI
GPI
Native
GPO
GPO
GPO
GPO
Native
Native
Native
GPO
GPO
GPO
GPONO USED
GPI
GPI
GPI
GPI
NA
NA
NA
NA
NA
NA
NA
NA
Native
Native
PIN NAME
GP10
GP11 RESUME
GP15
GP16
GP17
GP20
GP22
GP37
GP40
GP41
GP50
GP51
GP52 HDD2_AMBER
GP53
GP54
GP55
GP56
GP57
GP60
GP10-GP17 are only an output and can not be configured as an input. GP60 and GP61
are OD output only.
SMSC5127
POWER
USAGE
WELL
MAIN OUT
RESUMEGP12 OUT
RESUMEGP13 ESATA_RST_N
RESUMEGP14
MAIN
RESUME
RESUME
MAIN
MAIN I/O
MAIN
MAIN
MAIN
MAIN
MAIN OUT
MAIN OUT
RESUME
RESUME
RESUME OUT
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUMEGP61
NO USED
HDD4_BLUE
PLTRST_SLOTS_N
HDD4_AMBER
NO USED
SIO_PROCHOT_N
FAN_CTL3
HWM_INT_N(reserve)
SIO_KDATGP21
SIO_KCLK
SIO_SMI_NGP27 OUT
SIO_MDATGP32
SIO_MCLKGP33
KBRST_NGP36
A20GATE
PWRGD_ICH_SIO
NO USED
SIO_PME_S3GP42
NO USED
HDD3_AMBER
HDD3_BLUE
HDD2_BLUE
NO USED
NO USED CONNECT TO TP
HDD1_AMBER
HDD1_BLUE
HDD3_PWR
HDD1_PWR
FLASH TYPE
GNT5#
GNT4#
1
0
1
1
Flash cycles routed to SPI
Flash cycles routed to PCI
0
1
Flash cycles routed to LPC
I/O Address : 0x02E
Enable
DURING
RESET
OUT
OUT
OUT
OUT
OUT Low
I/O
I/O
I/O
OUT
OUTGP43
I/O
I/O
I/O
I/O
I/O
Routing
DESCRIPTION NOTES
Setting
HDD4 ACT
Low
PCIE SLOT RESET
Low
ESATA_RST_N
HDD4 FAIL
Control VR THERMAL THROTTLE
High PUSH PULL
CIRCUITRY ON PAGE28
Low
Control of POWER V_LED
Control Thermal Alarm in
SB on Page19
Keyboard Data I/O
-----
Keyboard Clock I/O
-----
High
Mouse Data I/O
-----
Mouse Clock I/O
-----
Keyboard Reset
Low
Open-Drain Output
Control A20GATE IN ICH9
Low
reserved function
Low
----- -----
Power Management Event
High
Output.
Front Panel Reset
-----
HDD3 FAIL
-----
HDD3 ACT
HDD2 FAIL
-----
HDD2 ACT
-----
-----
HDD1 FAIL
-----
HDD1 ACT
-----
-----
-----
CONNECT TO TP
10K P/U TO V_3P3_STBY\G ON
PAGE 38
-----
10K PU on PAGE31
10K P/U TO 3P3_STBY\G ON PAGE 38
10K P/U TO VCC3 ON PAGE 38
10K P/U TO VCC3 ON PAGE 38
Reserved 1K P/U TO VCC3 ON
PAGE 28
10K P/U TO 3P3_STBY\G ON
PAGE 38
10K P/U TO 3P3_STBY\G ON PAGE 38
CONNECT TO TP
330R P/U TO VCC ON PAGE 40
330R P/U TO V_3SB ON PA GE 40
A A
<Variant Name>
Title
GPIO & IRQ & SMBUS SETTING
Size Document Number Rev
S15 -1
Custom
5
4
3
2
Date: Sheet
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
750Friday, December 12, 2008
1
of
5
4
3
2
1
D D
H_A_N16
H_A_N15
H_A_N14
H_A_N13
H_A_N12
H_A_N11
H_A_N10
H_A_N9
H_A_N8
H_A_N7
H_A_N6
H_A_N5
H_A_N4
H_A_N3
TPAD28
H_ADSTB0_N
TP3
H_ADSTB1_N
H_REQ_N4
H_REQ_N3
H_REQ_N2
H_REQ_N1
H_REQ_N0
TP_AP_B2
1
H_A_N35
H_A_N34
H_A_N33
H_A_N32
H_A_N31
H_A_N30
H_A_N29
H_A_N28
H_A_N27
H_A_N26
H_A_N25
H_A_N24
H_A_N23
H_A_N22
H_A_N21
H_A_N20
H_A_N19
H_A_N18
H_A_N17
H_ADSTB0_N<12>
H_REQ_N[4..0]<12>
C C
H_ADSTB1_N<12>
B B
L21
K19
M20
L20
H21
M19
G20
N19
R20
N20
H20
P21
K20
R19
P20
G19
N21
D17
A14
B15
B14
A17
C16
B17
B16
C15
B18
D20
E20
C20
C18
C14
D19
A16
E21
F19
C19
B19
M18
J20
J19
J21
U1A
A_B16
A_B15
A_B14
A_B13
A_B12
A_B11
A_B10
A_B9
A_B8
A_B7
A_B6
A_B5
A_B4
A_B3
ADSTB_B0
REQ_B4
REQ_B3
REQ_B2
REQ_B1
REQ_B0
AP_B0
A_B35
A_B34
A_B33
A_B32
A_B31
A_B30
A_B29
A_B28
A_B27
A_B26
A_B25
A_B24
A_B23
A_B22
A_B21
A_B20
A_B19
A_B18
A_B17
ADSTB_B1
AP_B1
ADDR 0
ADDR 1
COMMON CLK
PAD-CPU437P-GP
TP_AP_B1
TP6
1
TPAD28
H_A_N[16..3]<12>
H_A_N[35..17]<12>
H_RS_N[2..0]
A A
5
H_A_N[16..3]
H_A_N[35..17]
H_RS_N[2..0] <12>
4
1 OF 5
ADS_B
BNR_B
BR0_B
BPRI_B
DBSY_B
DEFER_B
DRDY_B
HIT_B
HITM_B
LOCK_B
RS_B0
RS_B1
RS_B2
TRDY_B
RESET_B
H_ADS_N
V19
H_BNR_N
Y19
H_BREQ0_N
T20
H_BPRI_N
U21
H_DBSY_N
Y18
H_DEFER_N
T21
H_DRDY_N
T19
H_HIT_N
AA17
H_HITM_N
V20
H_LOCK_N
W20
H_RS_N0
W18
H_RS_N1
Y17
H_RS_N2
U20
H_TRDY_N
W19
H_CPURST_B_N H_CPURST_N
D15
R1
1 2
H_ADS_N <12>
H_BNR_N <12>
H_BREQ0_N <9,12>
H_BPRI_N <12>
H_DBSY_N <12>
H_DEFER_N <12>
H_DRDY_N <12>
H_HIT_N <12>
H_HITM_N <12>
H_LOCK_N <12>
H_TRDY_N <12>
0R2J-2-GP
CN1
1
2
FOX-CON2-3
H_CPURST_N <9,12,43>
CN2
1
2
FOX-CON2-3
3
H_D_N0
H_D_N1
H_D_N2
H_D_N3
H_D_N4
H_D_N5
H_D_N6
H_D_N7
H_D_N8
H_D_N9
H_D_N10
H_D_N11
H_D_N12
H_D_N13
H_D_N14
H_D_N15
H_DBI_N<0><12>
H_STBN_N<0><12>
H_STBP_N<0><12>
H_DBI_N<1><12>
H_STBN_N<1><12>
H_STBP_N<1><12>
H_DBI_N<0>
H_STBN_N<0>
H_STBP_N<0>
TP1
TPAD28
H_D_N16
H_D_N17
H_D_N18
H_D_N19
H_D_N20
H_D_N21
H_D_N22
H_D_N23
H_D_N24
H_D_N25
H_D_N26
H_D_N27
H_D_N28
H_D_N29
H_D_N30
H_D_N31
H_DBI_N<1>
H_STBN_N<1>
H_STBP_N<1>
TP4
TPAD28
Y11
D_B0
W10
D_B1
Y12
D_B2
AA14
D_B3
AA11
D_B4
W12
D_B5
AA16
D_B6
Y10
D_B7
Y9
D_B8
Y13
D_B9
W15
D_B10
AA13
D_B11
Y16
D_B12
W13
D_B13
AA9
D_B14
W9
D_B15
W16
DINV_B0
Y14
DSTBN_B0
Y15
AA5
AA6
AA8
W3
W7
W6
W2
W4
V9
Y8
U1
Y7
Y3
V3
U2
T3
V2
Y6
Y4
Y5
R4
DSTBP_B0
DP_B0
D_B16
D_B17
D_B18
D_B19
D_B20
D_B21
D_B22
D_B23
D_B24
D_B25
D_B26
D_B27
D_B28
D_B29
D_B30
D_B31
DINV_B1
DSTBN_B1
DSTBP_B1
DP_B1
1
1
DATA 2 DATA 3
DATA 0DATA 1
U1B
2 OF 5
D_B32
D_B33
D_B34
D_B35
D_B36
D_B37
D_B38
D_B39
D_B40
D_B41
D_B42
D_B43
D_B44
D_B45
D_B46
D_B47
DINV_B2
DSTBN_B2
DSTBP_B2
DP_B2
D_B48
D_B49
D_B50
D_B51
D_B52
D_B53
D_B54
D_B55
D_B56
D_B57
D_B58
D_B59
D_B60
D_B61
D_B62
D_B63
DINV_B3
DSTBN_B3
DSTBP_B3
DP_B3
R3
R2
P1
N1
M2
P2
J3
N3
G3
H2
N2
L2
M3
J2
H1
J1
L1
K2
K3
M4
C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
C5
E2
F3
D4
H_D_N32
H_D_N33
H_D_N34
H_D_N35
H_D_N36
H_D_N37
H_D_N38
H_D_N39
H_D_N40
H_D_N41
H_D_N42
H_D_N43
H_D_N44
H_D_N45
H_D_N46
H_D_N47
H_DBI_N<2>
H_STBN_N<2>
H_STBP_N<2>
TP2
1
TPAD28
H_D_N48
H_D_N49
H_D_N50
H_D_N51
H_D_N52
H_D_N53
H_D_N54
H_D_N55
H_D_N56
H_D_N57
H_D_N58
H_D_N59
H_D_N60
H_D_N61
H_D_N62
H_D_N63
H_DBI_N<3>
H_STBN_N<3>
H_STBP_N<3>
1
TP5
TPAD28
H_DBI_N<2> <12>
H_STBN_N<2> <12>
H_STBP_N<2> <12>
H_DBI_N<3> <12>
H_STBN_N<3> <12>
H_STBP_N<3> <12>
PAD-CPU437P-GP
H_D_N[15..0]<12>
H_D_N[31..16]<12>
H_D_N[15..0]
H_D_N[31..16]
H_D_N[15..0]<12>
H_D_N[31..16]<12>
H_D_N[47..32]<12>
H_D_N[63..48]<12>
H_D_N[15..0]
H_D_N[31..16]
H_D_N[47..32]
H_D_N[63..48]
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
CPU 1 OF 3
Size Document Number Rev
S15
B
Date: Sheet
2
Hsichih, Taipei
850Friday, December 12, 2008
1
-1
of
5
4
3
2
1
V_FSB_VTT
12
12
R2
U1C
H_INIT_N
V11
V12
U18
T16
V16
T15
R15
U17
R16
F16
V17
G17
H17
K17
H15
K18
V15
M17
N16
M16
L17
K16
M15
L16
J4
E4
E5
G4
F4
J18
J15
G6
H6
K4
K5
J16
BCLK0
BCLK1
A20M_B
FERR_B
IGNNE_B
INIT_B
LINT0
LINT1
SMI_B
STPCLK_B
IERR_B
PWRGOOD
PROCHOT_B
THERMTRIP_B
THRMDA
THRMDC
VSS
VSS
BPM_B0
BPM_B1
BPM_B2
BPM_B3
NC#G6
NC#H6
NC#K4
NC#K5
PRDY_B
PREQ_B
BR1_B
TCK
TDI
TDO
TMS
TRST_B
NC#M15
NC#L16
ASYNC
THERM
DEBUG
D D
SA-0729-R8 change to 0 ohm
H_SB_INIT_N<27>
R8 0R2J-2-GP
1 2
CK_H_CPU_DP<25>
CK_H_CPU_DN<25>
H_SB_A20M_N<27>
H_SB_FERR_N<27>
H_SB_IGNNE_N<27>
H_SB_INTR<27>
H_SB_NMI<27>
H_SB_SMI_N<27>
H_SB_STPCLK_N<27>
H_IERR_N
1
C3
TPAD28
1
TP11
TPAD28
TP7
R12
H_PWRGD<28,43>
H_TEMP_SRC_DP<38>
H_TEMP_RET_DN<38>
H_BPM4_PRDY_N<43>
H_BPM5_PREQ_N<43>
H_PROCHOT_B_N
H_BPM_N<0><43>
H_BPM_N<1><43>
H_BPM_N<2><43>
H_BPM_N<3><43>
1
H_TCK<43>
H_TDI<43>
H_TDO<43>
H_TMS<43>
H_TRST_N<43>
1
H_PROCHOT_N<38>
V_FSB_VTT
62R2J-GP
1 2
H_THERMTRIP_N
R11
22R2J-2-GP
1 2
12
C C
RESERVE FOR 1UF
TP10
TPAD28
1
TPAD28
R16 DUMMY-R2
FP_RST_N<28,31,43>
1 2
RESERVE FOR 0R
H_BR1_N
B B
12
R17
DUMMY-R2
RESERVE FOR 1KR
TP9
1
TP12
TPAD28
DUMMY-C2
TPAD28
TP8
3 OF 5
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VSS
VSS
VSS
VSS
CMREF
GTLREF
NC#D6
EXTBGREF
SLP_B
DPRSTP_B
DPSLP_B
DPWR_B
FORCEPR_B
HFPLL
VSS
BINIT_B
MCERR_B
ACLKPH
DCLKPH
VSS
VSS
RSP_B
EDM
VSS
NC#A3
NC#C1
NC#C21
CORE_DET
J6
H5
G5
T1
T2
F20
F21
L5
N5
N4
P4
B7
A7
D6
M6
N18
R18
R17
U4
N15
N6
L15
T17
P17
U5
V5
P5
T5
T6
R6
A19
A3
C1
C21
A13
470R2J-2-GP
H_COMP0
H_COMP1
H_COMP2
H_COMP3
H_SB_CPUSLP_N <27>
H_DPRSTP_N
H_DPSLP_N
H_DPWR_N
H_FORCEPR
PAD-CPU437P-GP
H_DPWR_N
H_PWRGD<28,43>
H_BREQ0_N<8,12>
H_CPURST_N<8,12,43>
H_DPRSTP_N
H_SB_FERR_N<27>
H_DPSLP_N
A A
H_IERR_N
H_BR1_N
H_SB_THERMTRIP_N<27>
5
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R191KR2J-1-GP
R211KR2J-1-GP
V_FSB_VTT
R2251R2F-2-GP
R2351R2F-2-GP
R241KR2J-1-GP
H_PWRGD<28,43>
R251KR2J-1-GP
C5 DUMMY-C2
1 2
RESERVE FOR 1UF
R261KR2J-1-GP
R271KR2J-1-GP
R28150R2F-1-GP
R291KR2J-1-GP
4
3
12
R3
R4
470R2J-2-GP
470R2J-2-GP
R5 24D9R2F-L-GP
1 2
R6 49D9R2F-GP
1 2
R7 24D9R2F-L-GP
1 2
R9 49D9R2F-GP
1 2
H_GTLREF
H_EXTBGREF
H_PROCHOT_N<38> H_FORCEPR
2
COMP PIN MAX TRACE LENGTH
OF 500 MIL
H_FSBSEL0 <19,25>
H_FSBSEL1 <19,25>
H_FSBSEL2 <19,25>
SA-0729-R10 change to 1.2K
ohm
R10
V_FSB_VTT
GTLREF MAX TRACE LENGTH
OF 500 MIL AND 5 MIL
SPACING
1 2
1K2R2F-1-GP
PLACE NEAR GTLREF 'S PINS
12
C1
SC220P50V2JN-3GP
SC1U10V2KX-1GP
12
12
R13
C2
2KR2F-3-GP
12
C4
12
R14
1KR2J-1-GP
12
R15
2KR2F-3-GP
V_FSB_VTT
SC1U10V2KX-1GP
R18 DUMMY-R2
1 2
RESERVE FOR 0R
R20
1 2
H_SB_THERMTRIP_N <27>H_THERMTRIP_N
0R2J-2-GP
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
CPU 2 OF 3
Size Document Number Rev
S15
B
Date: Sheet
Hsichih, Taipei
950Friday, December 12, 2008
1
-1
of
5
4
3
2
1
5 OF 5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W14
W17
W21
W5
W8
Y1
A20
AA4
B21
E16
E8
F18
F7
H19
H4
K1
K7
L19
L4
L7
M1
P16
P19
P7
R1
T13
U16
U7
V14
V8
Y21
A2
AA3
B20
E15
E7
F17
F6
H18
H3
J9
K6
L18
L3
L6
L9
P15
P18
P6
P9
T12
U15
U6
V13
V7
Y20
AA20
B2
E6
F5
T11
V6
Y2
AA2
T10
AA19
AA18
CAPS FOR VCCP PLANE 11 *
(SC1U10V2KX-1GP) delete by JIM
20080714 for routing
CHECK PIN E14, DOES IT THE SAME WITH VTT ?
D D
V_1P5_SFR
12
12
C7
C6
SCD1U50V3KX-GP
SC10U6D3V3MX-GP
C C
B B
PLACE C6 CLOSE PIN D7
V_FSB_VTT
V_FSB_VTT
V_FSB_VTT
V_FSB_VTT
U1D
D7
VCCA
V10
VCCF
E14
VCCPC6_4
A9
VCCQ0_1
B9
VCCQ0_2
G14
VTT
H14
VTT
E13
VCCPC6_1
F14
VCCPC6_2
F13
VCCPC6_3
C9
VTT
D9
VTT
E9
VTT
G8
VTT
H8
VTT
J14
VTT
J8
VTT
K14
VTT
K8
VTT
L14
VTT
L8
VTT
M14
VTT
M8
VTT
N14
VTT
N8
VTT
P14
VTT
P8
VTT
R14
VTT
R8
VTT
T14
VTT
T8
VTT
F9
VTT
U14
VTT
U9
VTT
F8
VTT
U13
VTT
U8
VTT
U12
VTT
U11
VTT
U10
VTT
PAD-CPU437P-GP
4 OF 5
VCC_SENSE
VSS_SENSE
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
C13
VCC_SENSE_CPU_SKT <44>
D13
VSS_SENSE_CPU_SKT <44>
H_VID0
F15
H_VID1
D16
H_VID2
E18
H_VID3
G15
H_VID4
G16
H_VID5
E17
H_VID6
G18
A12
B12
C12
D12
E12
F12
G12
H12
J12
K12
L12
M12
N12
P12
R12
A11
B11
C11
D11
E11
F11
G11
H11
J11
K11
L11
M11
N11
P11
R11
A10
B10
C10
D10
E10
F10
G10
H10
J10
K10
L10
M10
N10
P10
R10
VCCP
H_VID0 <44>
H_VID1 <44>
H_VID2 <44>
H_VID3 <44>
H_VID4 <44>
H_VID5 <44>
H_VID6 <44>
A15
A18
AA10
AA12
AA15
AA7
B13
C17
D14
D18
D21
E19
G13
G21
H13
H16
J13
J17
K13
K15
K21
L13
M13
M21
N13
N17
P13
R13
R21
T18
U19
V18
V21
W11
U1E
VSS
VSS
A4
VSS
A8
VSS
VSS
VSS
VSS
VSS
B1
VSS
VSS
B5
VSS
B8
VSS
VSS
C8
VSS
D1
VSS
VSS
VSS
VSS
D5
VSS
D8
VSS
VSS
E3
VSS
G1
VSS
VSS
VSS
G7
VSS
G9
VSS
VSS
VSS
H7
VSS
H9
VSS
VSS
VSS
J5
VSS
J7
VSS
VSS
VSS
VSS
K9
VSS
VSS
VSS
VSS
M5
VSS
M7
VSS
M9
VSS
VSS
VSS
N7
VSS
N9
VSS
VSS
P3
VSS
VSS
VSS
R5
VSS
R7
VSS
R9
VSS
VSS
T4
VSS
T7
VSS
T9
VSS
VSS
U3
VSS
V1
VSS
VSS
VSS
V4
VSS
W1
VSS
VSS
A A
5
4
3
PAD-CPU437P-GP
2
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
CPU 3 OF 3
Size Document Number Rev
S15
B
Date: Sheet
Hsichih, Taipei
10 50Friday, December 12, 2008
1
of
-1
5
4
3
2
1
BACKSIDE CAPS FOR V_FSB_VTT PLANE
D D
C C
TOP SIDE CAPS FOR V_FSB_VTT PLANE
V_FSB_VTT
12
C29
SC1U10V2KX-1GP
12
C30
SC1U10V2KX-1GP
12
C26
SC1U10V2KX-1GP
12
C27
SC1U10V2KX-1GP
12
C28
SC1U10V2KX-1GP
DECOUPLING FOR V_FSB_VTT
V_FSB_VTT
12
12
C38
C39
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
B B
12
C40
SC1U10V2KX-1GP
12
C41
V_FSB_VTT
VCCP
12
12
12
C22
12
C34
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C23
12
C35
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C19
12
C31
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C20
12
C32
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C21
12
C33
SC1U10V2KX-1GP
SC1U10V2KX-1GP
BACKSIDE CAPS FOR VCCP PLANE
12
12
C43
12
C44
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C42
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C45
12
C46
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C24
12
C36
12
C47
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C25
12
C37
DECOUPLING FOR VCCP
VCCP
A A
5
12
12
12
C48
C49
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C50
12
C51
SC1U10V2KX-1GP
4
3
12
12
C52
C53
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
2
12
12
12
C55
C54
SC1U10V2KX-1GP
SC1U10V2KX-1GP
<Variant Name>
Title
CPU DECOUPLING CAPS
Size Document Number Rev
S15
B
Date: Sheet
C56
12
C57
SC1U10V2KX-1GP
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
1
-1
of
11 50Friday, December 12, 2008
5
H_D_N[63..0]<8>
D D
4X GTL+
C C
B B
HXSWING<19>
HXSCOMP<19>
HXRCOMP<19>
MCH_GTLREF0<19>
CK_H_MCH_DP<25>
CK_H_MCH_DN<25>
A A
H_D_N[63..0]
H_D_N0
H_D_N1
H_D_N2
H_D_N3
H_D_N4
H_D_N5
H_D_N6
H_D_N7
H_D_N8
H_D_N9
H_D_N10
H_D_N11
H_D_N12
H_D_N13
H_D_N14
H_D_N15
H_D_N16
H_D_N17
H_D_N18
H_D_N19
H_D_N20
H_D_N21
H_D_N22
H_D_N23
H_D_N24
H_D_N25
H_D_N26
H_D_N27
H_D_N28
H_D_N29
H_D_N30
H_D_N31
H_D_N32
H_D_N33
H_D_N34
H_D_N35
H_D_N36
H_D_N37
H_D_N38
H_D_N39
H_D_N40
H_D_N41
H_D_N42
H_D_N43
H_D_N44
H_D_N45
H_D_N46
H_D_N47
H_D_N48
H_D_N49
H_D_N50
H_D_N51
H_D_N52
H_D_N53
H_D_N54
H_D_N55
H_D_N56
H_D_N57
H_D_N58
H_D_N59
H_D_N60
H_D_N61
H_D_N62
H_D_N63
5
U2B
P41
HD0
M39
HD1
P42
HD2
M42
HD3
N41
HD4
M40
HD5
L40
HD6
M41
HD7
K42
HD8
G39
HD9
J41
HD10
G42
HD11
G40
HD12
G41
HD13
F40
HD14
F43
HD15
F37
HD16
E37
HD17
J35
HD18
D39
HD19
C41
HD20
B39
HD21
B40
HD22
H34
HD23
C37
HD24
J32
HD25
B35
HD26
J34
HD27
B34
HD28
F32
HD29
L32
HD30
J31
HD31
H31
HD32
M33
HD33
K31
HD34
M27
HD35
K29
HD36
F31
HD37
H29
HD38
F29
HD39
L27
HD40
M24
HD41
J26
HD42
K26
HD43
G26
HD44
H24
HD45
K24
HD46
F24
HD47
E31
HD48
A33
HD49
E40
HD50
D37
HD51
C39
HD52
D38
HD53
D33
HD54
C35
HD55
D34
HD56
C34
HD57
B31
HD58
C31
HD59
C32
HD60
D32
HD61
B30
HD62
D30
HD63
B27
HSWING
C27
HSCOMP
A28
HRCOMP
D27
HDVREF
D28
HACCVREF
M31
HCLKP
M29
HCLKN
LAKEPORT-1-GP
H_A_N[35..3]<8>
H_RS_N[2..0]<8>
2 OF 8
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
RESERVED#AA35
RESERVED#AA42
RESERVED#AA34
RESERVED#AA38
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1
HDSTBP#0
HDSTBN#0
HDINV#0
HDSTBP#1
HDSTBN#1
HDINV#1
HDSTBP#2
HDSTBN#2
HDINV#2
HDSTBP#3
HDSTBN#3
HDINV#3
HADS#
HTRDY#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HRS#0
HRS#1
HRS#2
HCPURST#
HPCREQ#
HEDRDY#
J39
K38
J42
K35
J37
M34
N35
R33
N32
N34
M38
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
AA37
V32
Y34
AA35
AA42
AA34
AA38
E41
D41
K36
G37
E42
M36
V35
K41
L43
K40
F35
G34
A38
J27
M26
E29
E34
B37
B32
W42
W40
V41
P40
W41
U41
U40
AA41
U39
D42
U42
T40
Y43
T43
C30
F38
Y40
4
H_A_N[35..3]
H_RS_N[2..0]
H_A_N3
H_A_N4
H_A_N5
H_A_N6
H_A_N7
H_A_N8
H_A_N9
H_A_N10
H_A_N11
H_A_N12
H_A_N13
H_A_N14
H_A_N15
H_A_N16
H_A_N17
H_A_N18
H_A_N19
H_A_N20
H_A_N21
H_A_N22
H_A_N23
H_A_N24
H_A_N25
H_A_N26
H_A_N27
H_A_N28
H_A_N29
H_A_N30
H_A_N31
H_A_N32
H_A_N33
H_A_N34
H_A_N35
H_REQ_N0
H_REQ_N1
H_REQ_N2
H_REQ_N3
H_REQ_N4
H_RS_N0
H_RS_N1
H_RS_N2
4
H_REQ_N[4..0]
H_ADSTB0_N <8>
H_ADSTB1_N <8>
H_STBP_N<0> <8>
H_STBN_N<0> <8>
H_DBI_N<0> <8>
H_STBP_N<1> <8>
H_STBN_N<1> <8>
H_DBI_N<1> <8>
H_STBP_N<2> <8>
H_STBN_N<2> <8>
H_DBI_N<2> <8>
H_STBP_N<3> <8>
H_STBN_N<3> <8>
H_DBI_N<3> <8>
H_ADS_N <8>
H_TRDY_N <8>
H_DRDY_N <8>
H_DEFER_N <8>
H_HITM_N <8>
H_HIT_N <8>
H_LOCK_N <8>
H_BREQ0_N <8,9>
H_BNR_N <8>
H_BPRI_N <8>
H_DBSY_N <8>
H_CPURST_N <8,9,43>
1
2X GTL+
H_REQ_N[4..0] <8>
4X GTL+
1X GTL+
TP13
TP14
TPAD28
1
TPAD28
3
CN3
1
2
FOX-CON2-3
CN4
1
2
FOX-CON2-3
3
2
U2A
D14
EXP_TXP0
C13
EXP_TXN0
A13
EXP_TXP1
B12
EXP_TXN1
A11
EXP_TXP2
B10
EXP_TXN2
C10
EXP_TXP3
C9
EXP_TXN3
A9
EXP_TXP4
B7
EXP_TXN4
D7
EXP_TXP5
D6
EXP_TXN5
A6
EXP_TXP6
B5
EXP_TXN6
E2
EXP_TXP7
F1
EXP_TXN7
G2
EXP_TXP8
J1
EXP_TXN8
J3
EXP_TXP9
K4
EXP_TXN9
L4
EXP_TXP10
M4
EXP_TXN10
M2
EXP_TXP11
N1
EXP_TXN11
P2
EXP_TXP12
T1
EXP_TXN12
T4
EXP_TXP13
U4
EXP_TXN13
U2
EXP_TXP14
V1
EXP_TXN14
V3
EXP_TXP15
W4
EXP_TXN15
W2
DMI_MT_IR_0_DP<26>
DMI_MT_IR_0_DN<26>
DMI_MT_IR_1_DP<26>
DMI_MT_IR_1_DN<26>
DMI_MT_IR_2_DP<26>
DMI_MT_IR_2_DN<26>
DMI_MT_IR_3_DP<26>
DMI_MT_IR_3_DN<26>
GRCOMP<19> CK_PE_100M_MCH_DP <25>
AA2
AB1
AA4
AB3
AC4
AC12
AC11
Y1
Y4
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
EXP_COMPO
EXP_COMPI
LAKEPORT-1-GP
1 OF 8
EXP_RXP0
EXP_RXN0
EXP_RXP1
EXP_RXN1
EXP_RXP2
EXP_RXN2
EXP_RXP3
EXP_RXN3
EXP_RXP4
EXP_RXN4
EXP_RXP5
EXP_RXN5
EXP_RXP6
EXP_RXN6
EXP_RXP7
EXP_RXN7
EXP_RXP8
EXP_RXN8
EXP_RXP9
EXP_RXN9
EXP_RXP10
EXP_RXN10
EXP_RXP11
EXP_RXN11
EXP_RXP12
EXP_RXN12
EXP_RXP13
EXP_RXN13
EXP_RXP14
EXP_RXN14
EXP_RXP15
EXP_RXN15
DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3
GCLKP
GCLKN
SDVO_CTRLDATA
SDVO_CTRLCLK
G12
F12
D11
D12
J13
H13
E10
F10
J9
H10
F7
F9
C4
D3
G6
J6
K9
K8
F4
G4
M6
M7
K2
L1
U11
U10
R8
R7
P4
N3
Y10
Y11
Y7
Y8
AA9
AA10
AA6
AA7
AC9
AC8
B14
B16
F15
E15
1
DMI_IT_MR_0_DP <26>
DMI_IT_MR_0_DN <26>
DMI_IT_MR_1_DP <26>
DMI_IT_MR_1_DN <26>
DMI_IT_MR_2_DP <26>
DMI_IT_MR_2_DN <26>
DMI_IT_MR_3_DP <26>
DMI_IT_MR_3_DN <26>
CK_PE_100M_MCH_DN <25>
Delete net SDVO_CTRL_DATA,SDVO_CTRL_CLK,R325,R326
<Variant Name>
Title
MCH PCIE/DMI 1 OF 6
Size Document Number Rev
S15
Custom
Date: Sheet
2
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
12 50Friday, December 12, 2008
1
-1
of
5
D D
C C
B B
M_MAA_A[13..0]<22,23>
CK_M_166M_DDR0_A_DP<22>
CK_M_166M_DDR0_A_DN<22>
CK_M_166M_DDR1_A_DP<22>
CK_M_166M_DDR1_A_DN<22>
CK_M_166M_DDR2_A_DP<22>
CK_M_166M_DDR2_A_DN<22>
M_SCS_A_N0<22,23>
M_SCS_A_N1<22,23>
M_SCKE_A0<22,23>
M_SCKE_A1<22,23>
M_ODT_A0<22,23>
M_ODT_A1<22,23>
4
M_MAA_A[13..0]
M_WE_A_N<22,23>
M_CAS_A_N<22,23>
M_RAS_A_N<22,23>
M_SBS_A0<22,23>
M_SBS_A1<22,23>
M_SBS_A2<22,23>
TP18 TPAD28
MCH_VREF_A<14,20>
M_SCS_A_N0
M_SCS_A_N1
TP15 TPAD28
1
TP16 TPAD28
1
M_SCKE_A0
M_SCKE_A1
TP17 TPAD28
1
1
M_ODT_A0
M_ODT_A1
TP19 TPAD28
1
TP20 TPAD28
1
TP21 TPAD28
1
TP22 TPAD28
1
TP23 TPAD28
1
TP24 TPAD28
1
TP25 TPAD28
1
TP26 TPAD28
1
MCH_VREF_A
TP27 TPAD28
1
TP28 TPAD28
1
M_MAA_A0
M_MAA_A1
M_MAA_A2
M_MAA_A3
M_MAA_A4
M_MAA_A5
M_MAA_A6
M_MAA_A7
M_MAA_A8
M_MAA_A9
M_MAA_A10
M_MAA_A11
M_MAA_A12
M_MAA_A13
M_WE_A_N
M_CAS_A_N
M_RAS_A_N
M_SBS_A0
M_SBS_A1
M_SBS_A2
BA32
AW32
BB30
BA30
AY30
BA27
BC28
AY27
AY28
BB27
AY33
AW27
BB26
BC38
BB35
BA37
BA34
BC33
AY34
BA26
BB37
BA39
BA35
AY38
BB25
AY25
BC24
BA25
AW37
AY39
AY37
BB40
BB32
AY32
AK42
AK41
BA31
BB31
AH40
AH43
BC16
AY14
AW17
AW18
AK40
AL17
AK17
AY5
BB5
AY6
BA5
AM4
3 OF 8
U2C
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SWE_A#
SCAS_A#
SRAS_A#
SBS_A0
SBS_A1
SBS_A2
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SCLK_A0
SCLK_A#0
SCLK_A1
SCLK_A#1
SCLK_A2
SCLK_A#2
SCLK_A3
SCLK_A#3
SCLK_A4
SCLK_A#4
SCLK_A5
SCLK_A#5
RESERVED#BC16
RESERVED#AY14
RESERVED#AW17
RESERVED#AW18
RESERVED#AK40
SM_VREF_0
RSV_TP1
RSV_TP0
SDQS_A0
SDQS_A#0
SDM_A0
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQS_A1
SDQS_A#1
SDM_A1
SDQ_A8
SDQ_A9
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQS_A2
SDQS_A#2
SDM_A2
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQS_A3
SDQS_A#3
SDM_A3
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQS_A4
SDQS_A#4
SDM_A4
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQS_A5
SDQS_A#5
SDM_A5
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQS_A6
SDQS_A#6
SDM_A6
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQS_A7
SDQS_A#7
SDM_A7
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
3
AU4
AR2
AR3
AP3
AP2
AU3
AV4
AN1
AP4
AU5
AU2
BA3
BB4
AY2
AW3
AY3
BA7
BB7
AV1
AW4
BC6
AY7
AY11
BA10
BB10
AW12
AY10
BA12
BB12
BA9
BB9
BC11
AY12
AU18
AR18
AP18
AM20
AM18
AV20
AM21
AP17
AR17
AP20
AT20
AU35
AV35
AT34
AP32
AV34
AV38
AU39
AV32
AT32
AR34
AU37
AP42
AP40
AP39
AR41
AR42
AN43
AM40
AU41
AU42
AP41
AN40
AG42
AG41
AG40
AL41
AL42
AF39
AE40
AM41
AM42
AF41
AF42
AC42
AC41
AC40
AD40
AD43
AA39
AA40
AE42
AE41
AB41
AB42
M_DQS_A_DP0
M_DQS_A_DN0
M_DQM_A0
M_DATA_A0
M_DATA_A1
M_DATA_A2
M_DATA_A3
M_DATA_A4
M_DATA_A5
M_DATA_A6
M_DATA_A7
M_DQS_A_DP1
M_DQS_A_DN1
M_DQM_A1
M_DATA_A8
M_DATA_A9
M_DATA_A10
M_DATA_A11
M_DATA_A12
M_DATA_A13
M_DATA_A14
M_DATA_A15
M_DQS_A_DP2
M_DQS_A_DN2
M_DQM_A2
M_DATA_A16
M_DATA_A17
M_DATA_A18
M_DATA_A19
M_DATA_A20
M_DATA_A21
M_DATA_A22
M_DATA_A23
M_DQS_A_DP3
M_DQS_A_DN3
M_DQM_A3
M_DATA_A24
M_DATA_A25
M_DATA_A26
M_DATA_A27
M_DATA_A28
M_DATA_A29
M_DATA_A30
M_DATA_A31
M_DQS_A_DP4
M_DQS_A_DN4
M_DQM_A4
M_DATA_A32
M_DATA_A33
M_DATA_A34
M_DATA_A35
M_DATA_A36
M_DATA_A37
M_DATA_A38
M_DATA_A39
M_DQS_A_DP5
M_DQS_A_DN5
M_DQM_A5
M_DATA_A40
M_DATA_A41
M_DATA_A42
M_DATA_A43
M_DATA_A44
M_DATA_A45
M_DATA_A46
M_DATA_A47
M_DQS_A_DP6
M_DQS_A_DN6
M_DQM_A6
M_DATA_A48
M_DATA_A49
M_DATA_A50
M_DATA_A51
M_DATA_A52
M_DATA_A53
M_DATA_A54
M_DATA_A55
M_DQS_A_DP7
M_DQS_A_DN7
M_DQM_A7
M_DATA_A56
M_DATA_A57
M_DATA_A58
M_DATA_A59
M_DATA_A60
M_DATA_A61
M_DATA_A62
M_DATA_A63
M_DQS_A_DP[7..0]
M_DQS_A_DN[7..0]
M_DQM_A[7..0]
M_DATA_A[63..0]
M_DQS_A_DP[7..0] <22>
M_DQS_A_DN[7..0] <22>
M_DQM_A[7..0] <22>
M_DATA_A[63..0] <22>
2
1
LAKEPORT-1-GP
A A
<Variant Name>
Title
MCH DDR2 A 2 OF 6
Size Document Number Rev
S15
C
Date: Sheet
5
4
3
2
1
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
13 50Friday, December 12, 2008
-1
5
D D
C C
B B
4
MCH_VREF_A<13,20>
SMRCOMP_P<20>
SMRCOMP_N<20>
MCH_VREF_A
BB22
BB21
BA21
AY21
BC20
AY19
AY20
BA18
BA19
BB18
BA22
BB17
BA17
AW42
BB23
AY24
BA23
AW23
AY23
AY17
BA40
AW41
BA41
AW40
BA14
AY16
BA13
BB13
AY42
AV40
AV43
AU40
AM29
AM27
AL38
AL36
AP26
AR26
AU10
AT10
AJ38
AJ36
AL39
AK18
AK23
AV9
AW9
AM2
AM3
AJ8
AJ6
AL5
3
4 OF 8
U2D
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SWE_B#
SCAS_B#
SRAS_B#
SBS_B0
SBS_B1
SBS_B2
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SCLK_B0
SCLK_B#0
SCLK_B1
SCLK_B#1
SCLK_B2
SCLK_B#2
SCLK_B3
SCLK_B#3
SCLK_B4
SCLK_B#4
SCLK_B5
SCLK_B#5
RESERVED#AL39
SM_VREF_1
RSV_TP3
RSV_TP2
SM_OCDCOPM_1
SM_OCDCOPM_0
SM_RCOMP1
SM_RCOMP0
SDQS_B0
SDQS_B#0
SDM_B0
SDQ_B0
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_B4
SDQ_B5
SDQ_B6
SDQ_B7
SDQS_B1
SDQS_B#1
SDM_B1
SDQ_B8
SDQ_B9
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQS_B2
SDQS_B#2
SDM_B2
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQS_B3
SDQS_B#3
SDM_B3
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQS_B4
SDQS_B#4
SDM_B4
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQS_B5
SDQS_B#5
SDM_B5
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQS_B6
SDQS_B#6
SDM_B6
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQS_B7
SDQS_B#7
SDM_B7
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
AM8
AM6
AL11
AL6
AL8
AP8
AP9
AJ11
AL9
AM10
AP6
AV7
AR9
AW7
AU7
AV6
AV12
AM11
AR5
AR7
AR12
AR10
AV13
AT13
AP13
AM15
AM13
AV15
AM17
AN12
AR13
AP15
AT15
AU23
AR23
AP23
AM24
AM23
AV24
AM26
AP21
AR21
AP24
AT24
AT29
AV29
AR29
AU27
AN29
AR31
AM31
AP27
AR27
AP31
AU31
AP36
AM35
AR38
AP35
AP37
AN32
AL35
AR35
AU38
AM38
AM34
AG34
AG32
AJ39
AL34
AJ34
AF32
AF34
AL31
AJ32
AG35
AD32
AD36
AD38
AD39
AC32
AD34
Y32
AA32
AF35
AF37
AC33
AC35
2
1
LAKEPORT-1-GP
A A
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
MCH DDR2 B 3 OF 6
Size Document Number Rev
S15
C
Date: Sheet
5
4
3
2
Hsichih, Taipei
-1
of
14 50Friday, December 12, 2008
1
5
http://hobi-elektronika.net/
D D
R31
DUMMY-R2
V_FSB_VTT
C C
B B
1 2
R31 Reserved
for 1K
R32 Reserved
for 1K
12
R32
DUMMY-R2
V_1P5_CORE
SIGNAL NAMING CONVENTION
EXP : PCI EXPRESS
DMI : DIRECT MEDIA INTERFACE
MEM_TYPE<19>
EXP_SLR<19>
BSEL_0<19>
BSEL_1<19>
BSEL_2<19>
EXP_EN
4
TP29 TPAD28
TP30 TPAD28
TP31 TPAD28
TP32 TPAD28
3
U2E
5 OF 8
F21
BSEL0
H21
BSEL1
L20
H20
N21
M17
R27
U27
M15
BB2
BA2
AW26
AW2
AV27
AV26
AJ27
AG27
AG26
AG25
AJ24
AD30
AC34
AF31
AD31
U30
AA30
AC30
K18
L18
K21
L21
F20
L17
L15
E35
B42
B41
Y30
Y33
V31
BSEL2
ALLZTEST
XORTEST
RSV_TP5
EXP_SLR
RSV_TP4
EXP_EN
RSV_TP6
VCC
VSS
RESERVED#R27
RESERVED#U27
RESERVED#M15
RESERVED#L15
NC#BB2
NC#BA2
NC#AW26
NC#AW2
NC#AV27
NC#AV26
NC#E35
NC#B42
NC#B41
RESERVED#AJ27
RESERVED#AG27
RESERVED#AG26
RESERVED#AG25
RESERVED#AJ24
RESERVED#AD30
RESERVED#AC34
RESERVED#Y30
RESERVED#Y33
RESERVED#AF31
RESERVED#AD31
RESERVED#U30
RESERVED#V31
RESERVED#AA30
RESERVED#AC30
LAKEPORT-1-GP
DDC_DATA
DREFCLKP
DREFCLKN
RESERVED#M11
RESERVED#V30
ICH_SYNC#
RESERVED#A43
RESERVED#AK21
RESERVED#AJ23
RESERVED#AJ26
RESERVED#AL29
RESERVED#AL20
RESERVED#AJ21
RESERVED#AL26
RESERVED#AK27
RESERVED#AJ29
RESERVED#AG29
1
1
1
1
HSYNC
VSYNC
RED
GREEN
BLUE
RED#
GREENB
BLUE#
DDC_CLK
IREF
EXTTS#
RSTIN#
PWROK
NC#BC43
NC#BC42
NC#BC2
NC#BC1NC#C42
NC#BB43
NC#BB1
NC#C2
NC#B43
NC#B3
NC#B2
NC#A42
D17
C17
F17
K17
H18
G17
J17
J18
N18
N20
A20
J15
H15
J20
M11
V30
AJ12
AJ9
M18
A43
BC43
BC42
BC2
BC1C42
BB43
BB1
C2
B43
B3
B2
A42
AK21
AJ23
AJ26
AL29
AL20
AJ21
AL26
AK27
AJ29
AG29
HSYNC <41>
VSYNC <41>
VGA_RED <21,41>
VGA_GREEN <21,41>
VGA_BLUE <21,41>
MCH_DDC_DATA <21,41>
MCH_DDC_CLK <21,41>
DACREFSET <21>
CK_96M_DREF_DP <25>
CK_96M_DREF_DN <25>
EXTTS_N
PLTRST_N <28,35,38>
PWRGD_3V <28,38>
ICH_SYNC_N <28>
R33
1 2
10KR2J-3-GP
2
V_2P5_MCH
1
ITP : ICH TRANSMIT POSITIVE
ITN : ICH TRANSMIT NEGATIVE
IRP : ICH RECEIVE POSITIVE
IRN : ICH RECEIVE NEGATIVE
MTP : MCH TRANSMIT POSITIVE
A A
MTN : MCH TRANSMIT NEGATIVE
MRP : MCH RECEIVE POSITIVE
MRN : MCH RECEIVE NEGATIVE
5
4
3
2
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
MCH MSIC 4 OF 6
Size Document Number Rev
S15
B
Date: Sheet
Hsichih, Taipei
15 50Friday, December 12, 2008
1
of
-1
5
D D
C C
B B
VCCA_HPLL_MPLL
VCCA_HPLL_MPLL
A A
5
V_2P5_DAC_FILTERED
V_1P5_CORE
V_FSB_VTT
VCCA_DPLLB
VCCA_DPLLA
V_2P5_MCH
VCCA_GPLL
4
6 OF 8
U2F
N17
VCC
P17
VCC
AH4
VCC
AJ5
VCC
AK4
VCC
AF30
VCC
AK20
VCC
AK3
VCC
AK2
VCC
AJ14
VCC
AK14
VCC
AK15
VCC
AJ13
VCC
AH2
VCC
AH1
VCC
AG14
VCC
AG13
VCC
AG12
VCC
AG11
VCC
AG10
VCC
AG9
VCC
AG8
VCC
AG7
VCC
AG6
VCC
AG5
VCC
AG4
VCC
AG3
VCC
AG2
VCC
AF14
VCC
AF13
VCC
AF12
VCC
AF11
VCC
AF10
VCC
AF9
VCC
AF8
VCC
AF7
VCC
AF6
VCC
AD14
VCC
AC22
VCC
AB23
VCC
AB22
VCC
AB21
VCC
AA22
VCC
P21
VCC
P20
VCC
P18
VCC
F27
VTT
G23
VTT
H23
VTT
J23
VTT
K23
VTT
L23
VTT
M23
VTT
A24
VTT
N23
VTT
C26
VTT
D23
VTT
D24
VTT
D25
VTT
P23
VTT
F23
VTT
E27
VTT
E26
VTT
E24
VTT
E23
VTT
C25
VTT
C23
VTT
B26
VTT
B25
VTT
B24
VTT
B23
VTT
B19
VCCADPLLB
B20
VCCAMPLL
C21
VCCAHPLL
C19
VCCADPLLA
C18
VCCA_DAC
B18
VCCA_DAC
D19
VCC2
B17
VCCA_EXPPLL
A18
VSSA_DAC
LAKEPORT-1-GP
4
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
3
3
BC18
BC22
BC26
BC31
BC35
BC13
BB42
BB38
BB33
BB28
BB24
BB20
BB16
AY41
AW21
AW13
AV31
AV21
AW35
AW34
AW31
AW29
AW24
AW20
AW15
AV42
AV23
AV18
AD4
AD5
AD6
AD8
AD10
AD12
N5
N7
N9
N10
N12
R5
R10
AE2
R11
R13
U6
U7
U8
U13
V5
V6
V7
V9
AE3
V10
V13
Y13
AA5
AA13
AC5
AC6
AC13
AD1
AD2
AE4
N11
V_SM
V_1P5_CORE
2
1
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
MCH POWER 5 OF 6
Size Document Number Rev
S15
B
Date: Sheet
2
Hsichih, Taipei
16 50Friday, December 12, 2008
1
-1
of
5
D D
U2H
G9G7G5
G38
G35
G32
G31G3G29
G27
G24
G21
G20
G18
G15
G13
G10F6F42
F34
AU15
F26F2F18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AU17
AU20
AU21
AU24
AU26
AU29
AU32
AU34
AU6
8 OF 8
Y9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AT18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AT21
AT23
AT26
AT27
AT31
AU12
AU13
VSS
Y6
VSS
Y5
VSS
Y42
VSS
Y39
VSS
Y37
VSS
Y35
VSS
Y31
VSS
Y2
VSS
Y14
VSS
Y12
VSS
W3
VSS
V8
VSS
V43
VSS
V39
VSS
V38
VSS
V37
VSS
V36
VSS
V34
VSS
V2
VSS
V14
VSS
V12
VSS
V11
VSS
U9
AR39
U5
U38
U36
U33
U31
U3
U14
U12
T42
T2
R9
R6
R39
R37
R34
R31
R30
R14
R12
P30
P3
P29
P27
P26
P24
P15
P14
N8
N6
N43
N39
N36
N33
N31
N29
N27
N26
N24
N2
N15
N13
M9
M8
M5
M37
M35
M3
M21
M20
M13
M10
L42
L31
L29
L26
L24
L2
L13
L12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
LAKEPORT-1-GP
AR43
AR6
VSS
VSS
VSS
AT12
AT17
C C
B B
F13E9E7E4E32E3E21
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AU9
AV10
AV17
AV2
AV37
4
E20
E18
E17
E13
E12D5D21
D20D2D16
D10C7C5
C40C3C22
C14
C12
BC9
BB6
H12
H17
H26
H27
H32
J10
J12J2J21
J24
J29
J38
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AW10
B11
B13
B21
B22
B28
B33
B38B4B6B9BA4
BA42
BB11
BB14
BB19
BB3
BB34
BB39
BB41
AR37
AR32
AR24
AR20
AR15
AR1
VSS
AP7
AP5
AP38
AP34
AP29
AP12
AP10
AN42
AN4
VSS
VSS
J43J5J7
VSS
VSS
AN31
AN27
3
K10
K12
K13
K15
K20
K27K3K32
K34
K37
K39K5K6
K7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN21
AN20
VSS
AN2
AN18
AN17
AN15
AN13
AM9
AN26
AN24
AN23
A16
VSS
VSS
VSS
VSS
VSS
A22
VSS
A26
VSS
A31
VSS
A35
VSS
AA11
VSS
AA12
VSS
AA14
VSS
AA21
VSS
AA23
VSS
AA3
VSS
AA31
VSS
AA33
VSS
AA36
VSS
AA8
VSS
AB2
VSS
AB43
VSS
AC10
VSS
AC14
VSS
AC2
VSS
AC21
VSS
AC23
VSS
AC3
VSS
AC31
VSS
AC36
VSS
AC37
VSS
AC38
VSS
AC39
VSS
AC7
VSS
AD11
VSS
AD13
VSS
AD33
VSS
AD35
VSS
AD37
VSS
AD42
VSS
AD7
VSS
AD9
VSS
AF1
VSS
AF2
VSS
AF3
VSS
AF33
VSS
AF36
VSS
AF38
VSS
AF43
VSS
AF5
VSS
AG30
VSS
AG31
VSS
AG33
VSS
AG36
VSS
AG37
VSS
AG38
VSS
AG39
VSS
AH42
VSS
AJ10
VSS
AJ30
VSS
AJ31
VSS
AJ33
VSS
AJ35
VSS
AJ37
VSS
AJ7
VSS
AK24
VSS
AK26
VSS
AK29
VSS
AK30
VSS
AL1
VSS
AL10
VSS
AL12
VSS
AL13
VSS
AL15
VSS
AL18
VSS
AL2
VSS
AL21
VSS
AL23
VSS
AL24
VSS
AL27
VSS
AL3
VSS
AL32
VSS
AL33
VSS
AL37
VSS
AL43
VSS
AL7
VSS
AM33
VSS
AM36
VSS
VSS
VSS
VSS
VSS
AM7
AM5
AM39
AM37
2
V_1P5_CORE
AJ15
AG23
AG22
AG21
AG20
AG19
AG18
AG17
AG15
AB18
Y27
Y25
Y19
Y18
W27
W26
W20
U19
U18
U17
U15
R24
R23
R21
R20
R18
AF29
R17
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
AF25
AF26
AF27
AG24
V19
V20
V21
V22
V23
V25
V27
W17
W18
W19
W22
W24
Y15
Y17
Y21
Y23
AA15
AA17
AA18
AA19
AA20
AA24
AA26
AB17
AB19
AB20
AB24
AB25
AB26
AB27
LAKEPORT-1-GP
1
7 OF 8
U2G
AC15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCSM
VCCSM
AC17
VCC
AC18
VCC
AC20
VCC
AC24
VCC
AC26
VCC
AC27
VCC
AD15
VCC
AD17
VCC
AJ17
VCC
AD19
VCC
AD21
VCC
AD23
VCC
AD25
VCC
AD26
VCC
AE17
VCC
AE18
VCC
AE20
VCC
AE22
VCC
AE24
VCC
AJ18
VCC
AE26
VCC
AE27
VCC
AF15
VCC
AF17
VCC
AF19
VCC
AF21
VCC
AF23
VCC
AJ20R15
VCCVCC
BC40
AY43
W21
VSS
V29
VSS
V26
VSS
V24
VSS
U29
VSS
R29
VSS
R26
VSS
D43
VSS
D1
VSS
A40
VSS
A4
VSS
AE21
VSS
AE23
VSS
AE25
VSS
AF18
VSS
AF20
VSS
AF22
VSS
AF24
VSS
W23
VSS
W25
VSS
Y20
VSS
Y22
VSS
Y24
VSS
Y26
VSS
Y29
VSS
AA25
VSS
AA27
VSS
AA29
VSS
AY1
VSS
AC19
VSS
AC25
VSS
AC29
VSS
AD18
VSS
AD20
VSS
AD22
VSS
AD24
VSS
AD27
VSS
AD29
VSS
AE19
VSS
BC4
VSS
V_1P5_CORE
V_SM
A A
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
MCH POWER 6 OF 6
Size Document Number Rev
S15
C
Date: Sheet
5
4
3
2
Hsichih, Taipei
-1
of
17 50Friday, December 12, 2008
1
5
4
3
2
1
V_1P5_CORE VCCA_GPLL
D D
R34
1 2
0R5J-1-GP
SC100U6D3V0MX-2GP
12
C460
SC100U6D3V0MX-2GP
12
C461
R35
1 2
0R3J-L-GP
R38
1 2
0R3J-L-GP
C C
R36
1 2
1R3J-L1-GP
R37
1 2
1R3J-L1-GP
12
C58
SC10U6D3V3MX-GP
12
C60
SCD1U50V3KX-GP
12
C59
SC1U10V2KX-1GP
VCC_HPLL_MPLL
VCCA_HPLL_MPLL
12
C61
SC1U10V2KX-1GP
R39
1 2
0R3J-L-GP
B B
12
C62
SCD1U50V3KX-GP
12
C63
SCD1U50V3KX-GP
12
R40
0R2J-2-GP
VCCA_DPLLA
VCCA_DPLLB
V_2P5_MCH
R41
1 2
0R3J-L-GP
A A
5
12
C64
SC100U6D3V0MX-2GP
12
C65
SCD1U50V3KX-GP
4
12
C66
SCD01U50V2KX-1GP
V_2P5_DAC_FILTERED
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
MCH 2P5_DAC & PLL FIL TERS
Size Document Number Rev
S15
B
Date: Sheet
3
2
Hsichih, Taipei
18 50Friday, December 12, 2008
1
-1
of
5
4
3
2
1
R48
1 2
60D4R2F-GP
R51
1 2
16D9R2F-1-GP
1 2
C67
1 2
SC10U6D3V3MX-GP
C68
1 2
SC10U6D3V3MX-GP
C73
1 2
SC2D2U10V3KX-1GP
12
R53
24D9R2F-L-GP
HXSCOMP <12>
C74
SC2D2P50V2CC-GP
HXRCOMP <12>
V_1P5_CORE
12
R42
124R2F-U-GP
12
R46
210R2F-L-GP
H_FSBSEL0<9,25>
H_FSBSEL1<9,25>
H_FSBSEL2<9,25>
R52 DUMMY-R2
1 2
R54 DUMMY-R2
1 2
1 2
12
C69
SCD1U25V2ZY-1GP
R47
1 2
10KR2J-3-GP
R49
1 2
10KR2J-3-GP
R50
1 2
10KR2J-3-GP
R45
10R2J-2-GP
12
C70
SC220P50V2JN-3GP
BSEL_0 <15>
BSEL_1 <15>
BSEL_2 <15>
MEM_TYPE <15>
EXP_SLR <15>
MCH_GTLREF0 <12>
V_1P5_CORE
V_1P5_CORE V_FSB_VTT
R43
0R2J-2-GP
V_1P5_CORE
12
12
C72
R44
0R2J-2-GP
SC10U6D3V3MX-GP
12
C76
SC4D7U10V3KX-GP
V_1P5_CORE
V_1P5_CORE
GMCH BACKSIDE CAPS
V_FSB_VTT
12
D D
12
C71
SC10U6D3V3MX-GP
CAPS FOR SPECIFIC CORE MCH
C C
PCI EXPRESS FILTER
V_1P5_CORE V_1P5_CORE
12
C75
SC10U6D3V3MX-GP
PLACE CLOSE TO LOAD
B B
GRCOMP<12>
V_FSB_VTT
12
12
R57
R55
301R2F-GP
H_XSWING
R56
1 2
12
C77
62R2J-GP
COMP SIGNAL TERMINATION
HXSWING <12>
SA-0729-R54,R52 change to
Dummy
NOA SIGNAL TERMINATION
84D5R2F-L-GP
A A
SCD01U50V2KX-1GP
5
4
3
2
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
MCH 2P5_DAC & PLL FIL TERS
Size Document Number Rev
S15
B
Date: Sheet
Hsichih, Taipei
19 50Friday, December 12, 2008
1
of
-1
5
4
3
2
1
V_SM
D D
12
12
R58
1KR2J-1-GP
R60
1KR2J-1-GP
PLACE CLOSE TO MCH
C C
V_SM
B B
12
12
1KR2J-1-GP
R62
1KR2J-1-GP
R63
MCH VREF
12
C79
SCD1U50V3KX-GP
SCD1U50V3KX-GP
12
SC1U10V2KX-1GP
C81
V_SM
MCH_VREF_A <13,14>
12
C80
DIMM_VREF_A <22>
12
SC1U10V2KX-1GP
C82
12
C83
SC1U10V2KX-1GP
12
C78
SC1U10V2KX-1GP
R59
1 2
80D6R2F-L-GP
R61
1 2
80D6R2F-L-GP
SMRCOMP_N <14>
SMRCOMP_P <14>
PLACE CLOSE TO CH_A DIMMS PLACE CLOSE TO DIMM PIN
DIMM VREF
<Variant Name>
A A
Title
MCH & DIMM VREF & COMP
Size Document Number Rev
S15
B
Date: Sheet
5
4
3
2
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
20 50Friday, December 12, 2008
1
-1
5
SCD1U25V2ZY-1GP
12
C87
SCD1U25V2ZY-1GP
12
C88
SCD1U25V2ZY-1GP
12
C89
12
12
C85
12
C86
SC10U6D3V3MX-GP
C84
D D
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
4
VCC VCCV_FSB_VTTV_FSB_VTT
12
12
R64
2K7R2J-GP
R66
2K7R2J-GP
3
12
R65
2K7R2J-GP
MCH_DDC_DATA <15,41> MCH_DDC_CLK <15,41>
12
R67
2K7R2J-GP
2
1
FSB GENERIC DECOUPLING
V_SM
12
12
12
12
C91
SC2D2U10V3KX-1GP
C90
SC2D2U10V3KX-1GP
C C
SC2D2U10V3KX-1GP
C92
SC2D2U10V3KX-1GP
C93
SC2D2U10V3KX-1GP
12
C94
SC2D2U10V3KX-1GP
12
C95
MCH MEMORY DECOUPLING
VGA TRACE DEFINITION SHOULD
BE THE SAME WITH SJ-D4
12
R68
DACREFSET <15>
PLACE CLOSE TO MCH
B B
A A
255R2F-L-GP
VGA_RED<15,41>
VGA_GREEN<15,41>
VGA_BLUE<15,41>
1 2
1 2
1 2
PLACE CLOSE TO MCH
WITHIN 750MIL OF
PIN
SA-0730-change R69,R70,R71 to 150 Ohm
5
R69 150R2F-1-GP
R70 150R2F-1-GP
R71 150R2F-1-GP
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
MCH DCPL & VGA TERMINATION
Size Document Number Rev
S15
B
Date: Sheet
4
3
2
Hsichih, Taipei
21 50Friday, December 12, 2008
1
-1
of
5
M_DATA_A31
M_DATA_A30
M_DATA_A29
M_DATA_A28
M_DATA_A27
M_DATA_A26
M_DATA_A25
D D
C C
B B
M_DATA_A24
M_DATA_A23
M_DATA_A22
M_DATA_A21
M_DATA_A20
M_DATA_A19
M_DATA_A18
M_DATA_A17
M_DATA_A16
M_DATA_A15
M_DATA_A14
M_DATA_A13
M_DATA_A12
M_DATA_A11
M_DATA_A10
M_DATA_A9
M_DATA_A8
M_DATA_A7
M_DATA_A6
M_DATA_A5
M_DATA_A4
M_DATA_A3
M_DATA_A2
M_DATA_A1
M_DATA_A0
M_DQS_A_DN7
M_DQS_A_DP7
M_DQS_A_DN6
M_DQS_A_DP6
M_DQS_A_DN5
M_DQS_A_DP5
M_DQS_A_DN4
M_DQS_A_DP4
M_DQS_A_DN3
M_DQS_A_DP3
M_DQS_A_DN2
M_DQS_A_DP2
M_DQS_A_DN1
M_DQS_A_DP1
M_DQS_A_DN0
M_DQS_A_DP0
DIMM_VREF_A<20>
CN5A
159
DQ31
158
DQ30
153
DQ29
152
DQ28
40
DQ27
39
DQ26
34
DQ25
33
DQ24
150
DQ23
149
DQ22
144
DQ21
143
DQ20
31
DQ19
30
DQ18
25
DQ17
24
DQ16
141
DQ15
140
DQ14
132
DQ13
131
DQ12
22
DQ11
21
DQ10
13
DQ9
12
DQ8
129
DQ7
128
DQ6
123
DQ5
122
DQ4
10
DQ3
9
DQ2
4
DQ1
3
DQ0
113
DQS7_
114
DQS7
104
DQS6_
105
DQS6
92
DQS5_
93
DQS5
83
DQS4_
84
DQS4
36
DQS3_
37
DQS3
27
DQS2_
28
DQS2
15
DQS1_
16
DQS1
6
DQS0_
7
DQS0
1
VREF
M_DATA_A[63..0]<13>
M_DQS_A_DN[7..0]<13>
M_DQS_A_DP[7..0]<13>
M_DQM_A[7..0]<13>
M_SCKE_A[1..0]<13,23>
236
DQ63
235
DQ62
230
DQ61
229
DQ60
117
DQ59
116
DQ58
111
DQ57
110
DQ56
227
DQ55
226
DQ54
218
DQ53
217
DQ52
108
DQ51
107
DQ50
99
DQ49
98
DQ48
215
DQ47
214
DQ46
209
DQ45
208
DQ44
96
DQ43
95
DQ42
90
DQ41
89
DQ40
206
DQ39
205
DQ38
200
DQ37
199
DQ36
87
DQ35
86
DQ34
81
DQ33
80
DQ32
232
DM7
223
DM6
211
DM5
202
DM4
155
DM3
146
DM2
134
DM1
125
DM0
221
CLK2_
220
CLK2
138
CLK1_
137
CLK1
186
CLK0_
185
CLK0
171
CKE1
52
CKE0
DDR2-240P-13-GP-U
M_DATA_A[63..0]
M_DQS_A_DN[7..0]
M_DQS_A_DP[7..0]
M_DQM_A[7..0]
M_SCKE_A[1..0]
M_DATA_A63
M_DATA_A62
M_DATA_A61
M_DATA_A60
M_DATA_A59
M_DATA_A58
M_DATA_A57
M_DATA_A56
M_DATA_A55
M_DATA_A54
M_DATA_A53
M_DATA_A52
M_DATA_A51
M_DATA_A50
M_DATA_A49
M_DATA_A48
M_DATA_A47
M_DATA_A46
M_DATA_A45
M_DATA_A44
M_DATA_A43
M_DATA_A42
M_DATA_A41
M_DATA_A40
M_DATA_A39
M_DATA_A38
M_DATA_A37
M_DATA_A36
M_DATA_A35
M_DATA_A34
M_DATA_A33
M_DATA_A32
M_DQM_A7
M_DQM_A6
M_DQM_A5
M_DQM_A4
M_DQM_A3
M_DQM_A2
M_DQM_A1
M_DQM_A0
CK_M_166M_DDR2_A_DN
CK_M_166M_DDR2_A_DP
CK_M_166M_DDR1_A_DN
CK_M_166M_DDR1_A_DP
CK_M_166M_DDR0_A_DN
CK_M_166M_DDR0_A_DP
M_SCKE_A1
M_SCKE_A0
4
CK_M_166M_DDR2_A_DN <13>
CK_M_166M_DDR2_A_DP <13>
CK_M_166M_DDR1_A_DN <13>
CK_M_166M_DDR1_A_DP <13>
CK_M_166M_DDR0_A_DN <13>
CK_M_166M_DDR0_A_DP <13>
M_SCKE_A1 <13,23>
M_SCKE_A0 <13,23>
M_MAA_A13
M_MAA_A12
M_MAA_A11
M_MAA_A10
M_MAA_A9
M_MAA_A8
M_MAA_A7
M_MAA_A6
M_MAA_A5
M_MAA_A4
M_MAA_A3
M_MAA_A2
M_MAA_A1
M_MAA_A0
CN5B
173
A15
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
101
240
239
135
126
102
68
49
48
46
45
43
42
19 224
M_MAA_A[13..0]<13,23>
SMB_CLK_MAIN<25,38>
SMB_DATA_MAIN<25,38>
RAS_
A14
CAS_
A13
WE_
A12
BA2
A11
BA1
A10
BA0
A9
A8
S1_
A7
S0_
A6
A5
ODT1
A4
ODT0
A3
A2
RC1
A1
RC0
A0
SA2
SA1
SCL
SA0
SDA
VDDSPD
NC135
NC147
NC126
NC156
NC102
NC161
NC68
NC162
NC49
NC164
NC48
NC165
NC46
NC167
NC45
NC168
NC43
NC203
NC42
NC212
NC19 NC224
NC233
DDR2-240P-13-GP-U
3
192
74
73
54
190
71
76
193
77
195
18
55
120
119
238
147
156
161
162
164
165
167
168
203
212
233
M_MAA_A[13..0]
SMB_CLK_MAIN
SMB_DATA_MAIN
M_RAS_A_N
M_CAS_A_N
M_WE_A_N
M_SBS_A2
M_SBS_A1
M_SBS_A0
M_SCS_A_N1
M_SCS_A_N0
M_ODT_A1
M_ODT_A0
SMB_CLK_MAIN
SMB_DATA_MAIN
M_RAS_A_N <13,23>
M_CAS_A_N <13,23>
M_WE_A_N <13,23>
M_SBS_A2 <13,23>
M_SBS_A1 <13,23>
M_SBS_A0 <13,23>
M_SCS_A_N1 <13,23>
M_SCS_A_N0 <13,23>
M_ODT_A1 <13,23>
M_ODT_A0 <13,23>
TP33TPAD28
1
TP34TPAD28
1
VCC3
12
C96
SCD1U10V2KX-4GP
SA-0729-Change CN5 pin238
to VCC3
2
CN5C
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
100
VSS
103
VSS
106
VSS
109
VSS
112
VSS
115
VSS
118
VSS
121
VSS
124
VSS
127
VSS
130
VSS
133
VSS
136
VSS
139
VSS
142
VSS
145
VSS
148
VSS
151
VSS
DDR2-240P-13-GP-U
VSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
1
1542
157
160
163
166
169
198
201
204
207
210
213
216
219
222
225
228
231
234
237
53
59
64
67
69
172
178
184
187
189
197
51
56
62
72
75
78
170
175
181
191
194
V_SM
<Variant Name>
A A
Title
240P CONN DDR2 CH A
Size Document Number Rev
S15
B
Date: Sheet
5
4
3
2
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
22 50Friday, December 12, 2008
1
-1
5
4
3
2
1
M_MAA_A13
M_MAA_A12
D D
M_MAA_A11
M_MAA_A10
M_MAA_A9
M_MAA_A8
M_MAA_A7
M_MAA_A6
M_MAA_A5
M_MAA_A4
C C
M_MAA_A3
M_MAA_A2
M_MAA_A1
M_MAA_A0
M_MAA_A[13..0]<13,22>
M_RAS_A_N<13,22>
B B
M_CAS_A_N<13,22>
M_WE_A_N<13,22>
R72 33KR2J-3-GP
1 2
R73 33KR2J-3-GP
1 2
R74 33KR2J-3-GP
1 2
R75 33KR2J-3-GP
1 2
R77 33KR2J-3-GP
1 2
R79 33KR2J-3-GP
1 2
R80 33KR2J-3-GP
1 2
R81 33KR2J-3-GP
1 2
R83 33KR2J-3-GP
1 2
R85 33KR2J-3-GP
1 2
R86 33KR2J-3-GP
1 2
R87 33KR2J-3-GP
1 2
R88 33KR2J-3-GP
1 2
R90 33KR2J-3-GP
1 2
R92 33KR2J-3-GP
1 2
R93 33KR2J-3-GP
1 2
R94 33KR2J-3-GP
1 2
V_SM_VTT
V_SM_VTT
R76 43R2J-GP
M_SCS_A_N0<13,22>
M_SCS_A_N1<13,22>
1 2
R78 43R2J-GP
1 2
V_SM
R82 43R2J-GP
M_SCKE_A0<13,22>
M_SCKE_A1<13,22>
M_ODT_A0<13,22>
M_ODT_A1<13,22>
1 2
R84 43R2J-GP
1 2
R89 43R2J-GP
1 2
R91 43R2J-GP
1 2
SCD1U10V2KX-4GP
12
C97
SCD1U10V2KX-4GP
12
C98
SCD1U10V2KX-4GP
12
C99
R95 33KR2J-3-GP
M_SBS_A2<13,22>
M_SBS_A1<13,22>
M_SBS_A0<13,22>
1 2
R96 33KR2J-3-GP
1 2
R97 33KR2J-3-GP
1 2
<Variant Name>
A A
Title
DDR VTT TERMINATION
Size Document Number Rev
S15
B
Date: Sheet
5
4
3
2
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
23 50Friday, December 12, 2008
1
-1
5
V_SM_VTT
4
3
2
1
D D
SCD1U10V2KX-4GP
CH A V_SM_VTT DECOUPLING CAPS
C C
V_SM_VTT
V_SM
B B
CH A ADDRESS/CONTROL SWITCHING
CAPS
12
C100
SCD1U10V2KX-4GP
12
C101
SCD1U10V2KX-4GP
12
C119
SCD1U10V2KX-4GP
12
C102
SCD1U10V2KX-4GP
12
C120
SCD1U10V2KX-4GP
12
C103
SCD1U10V2KX-4GP
12
C121
SCD1U10V2KX-4GP
12
C104
SCD1U10V2KX-4GP
12
C122
SCD1U10V2KX-4GP
12
C105
SCD1U10V2KX-4GP
12
C123
SCD1U10V2KX-4GP
12
C106
SCD1U10V2KX-4GP
12
C124
SCD1U10V2KX-4GP
12
C107
V_SM
SC1U10V2KX-1GP
12
C108
SC1U10V2KX-1GP
12
C109
SC1U10V2KX-1GP
12
C110
SC1U10V2KX-1GP
12
C111
SC1U10V2KX-1GP
12
C112
SC1U10V2KX-1GP
12
C113
SC1U10V2KX-1GP
12
C114
SC1U10V2KX-1GP
12
C115
SC1U10V2KX-1GP
12
C116
SC1U10V2KX-1GP
12
C117
SC1U10V2KX-1GP
12
C118
<Variant Name>
A A
Title
DDR VTT DECOUPLING
Size Document Number Rev
S15
B
Date: Sheet
5
4
3
2
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
24 50Friday, December 12, 2008
1
-1
5
http://hobi-elektronika.net/
SA-0730-delete Net CK410_VDDPCI,and change to VDD_SRC_CLKA
D D
12
FCM1608K-601T3-GP
12
C135
C C
SC10U6D3V3MX-GP
B B
A A
12
12
C140
C141
SC10P50V2JN-4GP
SC10P50V2JN-4GP
12
L1
L2
FCM1608K-601T3-GP
12
C131
SC4D7U10V3KX-GP
12
C136
SCD01U50V2KX-1GP
12
12
C142
C143
SC10P50V2JN-4GP
SC10P50V2JN-4GP
VCC3VCC3VCC3 VCC3
SCD1U50V3KX-GP
SC10P50V2JN-4GP
12
C132
SC22P50V2JN-4GP
12
C144
CK410_VDDSRC
12
C133
SCD1U50V3KX-GP
X1
1 2
X-14D318180MHZ
12
C137
5
CK_48M_USB_ICH <26>
CK_P_33M_LPC <41>
CK_P_33M_PA <38>
CK_14M_PA <38>
R100
1 2
2R2J-2-GP
12
C134
SCD1U50V3KX-GP
R116 475R3F-4-GP
OSC_CK14M_XTALIN_CLK
SC22P50V2JN-4GP
CK410_VDD48
12
C129
SC4D7U10V3KX-GP
SMB_CLK_MAIN<22,38>
SMB_DATA_MAIN<22,38>
VTT_PWRGD_N
1 2
H_FSBSEL0<9,19>
H_FSBSEL1<9,19>
H_FSBSEL2<9,19>
OSC_CK14M_XTALOUT
12
C138
SA-0730-change R146 to DUMMY
VDD_SRC_CLKA
12
C130
U3
7
VDD_PCI
SCD01U50V2KX-1GP
12
R144
10KR2J-3-GP
12
R146
DUMMY-R2
1
VDD_PCI
48
VDD_REF
11
VDD_48
42
VDD_CPU
34
VDD_SRC
21
VDD_SRC
28
VDD_SRC
37
VDD_A
46
SCL
47
SDA
17
VTT_PWRGD#
39
IREF
18
FS_A
16
FS_B
53
FS_C
50
XTAL_IN
49
XTAL_OUT
38
VSS_A
45
VSS_CPU
51
VSS_REF
13
VSS_48
2
VSS_PCI
29
VSS_SRC
SLG84410B-GP
VDD_SRC_CLKA
CK_P_33M_PA <38>
4
PLACE PER PIN
12
12
C125
C126
SCD1U50V3KX-GP
SC22U6D3V5MX-2GP
VDD_SRC_CLKA
VRM_PWRGD<44>
4
1 2
12
12
C127
C128
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PCIF_0
PCIF_1
PCIF_2
SRC_1P
SRC_1N
SRC_2P
SRC_2N
SRC_3P
SRC_3N
SRC_4_SATAP
SRC_4_SATAN
SRC_5P
SRC_5N
SRC_6P
SRC_6N
CPU_2P
CPU_2N
CPU_1P
CPU_1N
CPU_0P
CPU_0N
DOT_96P
DOT_96N
USB_48VSS_PCI
R142 10KR2J-3-GP
1 2
R145 6K2R2J-1-GP
1 2
12
SC1U10V2KX-1GP
VCC3
R98
0R2J-2-GP
PCI_0
PCI_1
PCI_2
PCI_3
PCI_4
PCI_5
REF
CK_PCIF0_R
8
9
CK_PCIF2_R
10
CK_PCI5_R
54
55
56
3
4
5
19
20
22
23
24
25
26
27
31
30
33
32
36
35
41
40
44
43
14
15
R129 33R2J-2-GP
126
CK_14M_R
52
1
1
1
1
1
CK_PE_SRC0_R_DP
CK_PE_SRC0_R_DN
CK_PE_SRC1_R_DP
CK_PE_SRC1_R_DN
CK_PE_SRC2_R_DP
CK_PE_SRC2_R_DN
CK_PE_SRC3_R_DP
CK_PE_SRC3_R_DN
CK_PE_SRC4_R_DP
CK_PE_SRC4_R_DN
CK_PE_SRC5_R_DP
CK_PE_SRC5_R_DN
1 2
R131 33R2J-2-GP
R133 33R2J-2-GP
R104 33R2J-2-GP
1 2
TP35TPAD28
1
R107 33R2J-2-GP
1 2
R109 33R2J-2-GP
1 2
TP36TPAD28
TP37TPAD28
TP38TPAD28
TP39TPAD28
TP40TPAD28
CK_H_XDP_R_DP
CK_H_XDP_R_DN
CK_H_CPU_R_DP
CK_H_CPU_R_DN
CK_H_MCH_R_DP
CK_H_MCH_R_DN
1 2
1 2
CK_48M_USB_ICH <26>
CK_14M_PA <38>
CK_14M_ICH <28>
SA-0730-change R129 to 33 ohm
VTT_PWRGD_NCK_P_33M_ICH <26>
3
Q1
1
MMBT3904-7-F-GP
2
C139
3
CK_P_33M_PA <38>
CK_P_33M_ICH <26>
CK_P_33M_LPC <41>
3
CK_PE_SRC0_R_DP
CK_PE_SRC0_R_DN
CK_96M_DOT_R_DP
CK_96M_DOT_R_DN
R552 49D9R2F-GP
1 2
R554 33R2J-2-GP
1 2
R555 33R2J-2-GP
1 2
R553 49D9R2F-GP
1 2
R99 49D9R2F-GP
1 2
R101 33R2J-2-GP
1 2
R102 33R2J-2-GP
1 2
R103 49D9R2F-GP
1 2
R105 49D9R2F-GP
1 2
R106 33R2J-2-GP
1 2
R108 33R2J-2-GP
1 2
R110 49D9R2F-GP
1 2
R111 49D9R2F-GP
1 2
R112 33R2J-2-GP
1 2
R113 33R2J-2-GP
1 2
R114 49D9R2F-GP
1 2
R119 49D9R2F-GP
1 2
R121 33R2J-2-GP
1 2
R122 33R2J-2-GP
1 2
R123 49D9R2F-GP
1 2
R127 49D9R2F-GP
1 2
R130 33R2J-2-GP
1 2
R132 33R2J-2-GP
1 2
R134 49D9R2F-GP
1 2
R135 49D9R2F-GP
1 2
R136 33R2J-2-GP
1 2
R137 33R2J-2-GP
1 2
R138 49D9R2F-GP
1 2
R139 49D9R2F-GP
1 2
R140 33R2J-2-GP
1 2
R141 33R2J-2-GP
1 2
R143 49D9R2F-GP
1 2
2
PCLKP <37>
PCLKN <37>
CK_PE_100M_PCIE_SLOT_DP <40>
CK_PE_100M_PCIE_SLOT_DN <40>
CK_PE_100M_MCH_DP <12>
CK_PE_100M_MCH_DN <12>
CK_ICHSATA_DP <27>
CK_ICHSATA_DN <27>
CK_H_XDP_DP <43>
CK_H_XDP_DN <43>
CK_H_CPU_DP <9>
CK_H_CPU_DN <9>
CK_H_MCH_DP <12>
CK_H_MCH_DN <12>
CK_96M_DREF_DP <15>
CK_96M_DREF_DN <15>
2
TO
E-SATA
R115 49D9R2F-GP
1 2
R117 33R2J-2-GP
1 2
R118 33R2J-2-GP
1 2
R120 49D9R2F-GP
1 2
CK_PE_SRC5_R_DP
CK_PE_SRC5_R_DN
1
12
C13
SCD1U10V2KX-4GP
CK_PE_100M_ICH_DP <26>
CK_PE_100M_ICH_DN <26>
R124 49D9R2F-GP
1 2
R125 33R2J-2-GP
1 2
R126 33R2J-2-GP
1 2
R128 49D9R2F-GP
1 2
<Variant Name>
Title
CK_410
Size Document Number Rev
S15
Custom
Date: Sheet
CK_PE_100M_LAN_DP <35>
CK_PE_100M_LAN_DN <35>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
1
25 50Friday, December 12, 2008
-1
of
5
D D
DMI_IT_MR_0_DN<12>
DMI_IT_MR_0_DP<12>
DMI_IT_MR_1_DN<12>
DMI_IT_MR_1_DP<12>
THE CAPS NEAR ICH7R
PER:INPUT
PET:OUTPUT
C C
PCIE SLOT
NIC
ESATA
CONTROLLER
B B
PCIE_ICH_RXN1<40>
PCIE_ICH_RXP1<40>
PCIE_ICH_TXN1_SLOT<40>
PCIE_ICH_TXP1_SLOT<40>
PCIE_ICH_RXN2<40>
PCIE_ICH_RXP2<40>
PCIE_ICH_TXN2_SLOT<40>
PCIE_ICH_TXP2_SLOT<40>
PCIE_ICH_RXN3<40>
PCIE_ICH_RXP3<40>
PCIE_ICH_TXN3_SLOT<40>
PCIE_ICH_TXP3_SLOT<40>
PCIE_ICH_RXN4<40>
PCIE_ICH_RXP4<40>
PCIE_ICH_TXN4_SLOT<40>
PCIE_ICH_TXP4_SLOT<40>
PCIE_ICH_RXN5<35>
PCIE_ICH_RXP5<35>
PCIE_ICH_TXN5_NIC<35>
PCIE_ICH_TXP5_NIC<35>
PCIE_ICH_RXN6<37>
PCIE_ICH_RXP6<37>
PCIE_ICH_TXN6_ESATA<37>
PCIE_ICH_TXP6_ESATA<37>
V_1P5_CORE
DMI_IT_MR_2_DN<12>
DMI_IT_MR_2_DP<12>
DMI_IT_MR_3_DN<12>
DMI_IT_MR_3_DP<12>
C145SCD1U16V2KX-3GP
12
12
C147SCD1U16V2KX-3GP
12
C148SCD1U16V2KX-3GP
12
C149SCD1U16V2KX-3GP
12
C150SCD1U16V2KX-3GP
12
C151SCD1U16V2KX-3GP
12
C152SCD1U16V2KX-3GP
12
C153SCD1U16V2KX-3GP
12
C154SCD1U16V2KX-3GP
12
C155SCD1U16V2KX-3GP
12
C156SCD1U16V2KX-3GP
12
24D9R2F-L-GP
1 2
R148
CK_PE_100M_ICH_DN<25>
CK_PE_100M_ICH_DP<25>
DMI_MT_IR_0_DN<12>
DMI_MT_IR_0_DP<12>
DMI_MT_IR_1_DN<12>
DMI_MT_IR_1_DP<12>
DMI_MT_IR_2_DN<12>
DMI_MT_IR_2_DP<12>
DMI_MT_IR_3_DN<12>
DMI_MT_IR_3_DP<12>
PCIE_ICH_TXN1
PCIE_ICH_TXP1
PCIE_ICH_TXN2
PCIE_ICH_TXP2
PCIE_ICH_TXN3
PCIE_ICH_TXP3
PCIE_ICH_TXN4
PCIE_ICH_TXP4
PCIE_ICH_TXN5
PCIE_ICH_TXP5
PCIE_ICH_TXN6
PCIE_ICH_TXP6
V_1P5_CORE_DMI
4
V26
V25
U28
U27
Y26
Y25
W28
W27
AB26
AB25
AA28
AA27
AD25
AD24
AC28
AC27
F26
F25
E28
E27
H26
H25
G28
G27
K26
K25
J28
J27
M26
M25
L28
L27
P26
P25
N28
N27
T25
T24
R28
R27
C25
D25
AE28
AE27
U4B
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
DMI_ZCOMP
DMI_IRCOMP
DMI_CLKN
DMI_CLKP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
USBRBIAS
USBRBIAS#
CLK48
ICH7-2-GP
2 OF 6
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
D3
OC0#
C4
OC1#
D5
OC2#
D4
OC3#
E5
OC4#
C3
A2
B3
D1
D2
B2
SA-0804-delete net
USB_OC4#_PULL_UP,USB_OC5#_PULL_UP,USB_OC_FRONT_67,
CHANGE TO USB_OC6#_PULL_UP,USB_OC7#_PULL_UP,USB_OC_FRONT_12
3
USB_BACK1_DN <36>
USB_BACK1_DP <36>
USB_BACK2_DN <36>
USB_BACK2_DP <36>
USB_BACK3_DN <36>
USB_BACK3_DP <36>
USB_BACK4_DN <36>
USB_BACK4_DP <36>
USB_FRONT1_DN <42>
USB_FRONT1_DP <42>
USB_FRONT2_DN <42>
USB_FRONT2_DP <42>
USBP8- <39>
USBP8+ <39>
USB_OC_BACK_12 <35>
USB_OC_BACK_34 <36>
USBRBIAS_ICH
USB_OC_FRONT_12 <42>
SA-0730-delete TP48,TP49 and add
R610,R611
USB_OC6#_PULL_UP
USB_OC7#_PULL_UP
USBRBIAS_ICH
CK_48M_USB_ICH <25>
12
R147
22D6R2F-L1-GP
TRACE TIED TOGETHER CLOSE TO PINS LENGTH NO
LONGER THAN 200 MIL TO RESISTOR
2
SA-0804-change USBP8+,USBP8Âto ICH7 port 7,change
USB_FRONT1 and USB_FRONT2 to
ICH port 4,5
1 2
1 2
TP41TPAD28
PCI_DEVSEL_N<34>
CK_P_33M_ICH<25>
PCI_IRDY_N<34>
VCC3
V_3P3_STBY\G
R610 10KR2J-3-GP
R611 10KR2J-3-GP
P_REQ_N[5..0]<34>
TP42TPAD28
TP43TPAD28
PCI_SERR_N<34>
PCI_STOP_N<34>
PCI_PLOCK_N<34>
PCI_TRDY_N<34>
PCI_PERR_N<34>
PCI_FRAME_N<34>
TP44TPAD28C146SCD1U16V2KX-3GP
TP45TPAD28
TP46TPAD28
TP47TPAD28
P_REQ_N[5..0]
P_INTA_N<34>
P_INTB_N<34>
P_INTC_N<34>
P_INTD_N<34>
P_INTE_N<34>
P_INTF_N<34>
P_INTG_N<34>
P_INTH_N<34>
TP_PCI_PAR
TP_PCIRST_N
TP_PME_N
TP_GNT0
TP_GNT1
TP_GNT2
TP_GNT3
TP_GNT4
TP_GNT5
P_REQ_N0
P_REQ_N1
P_REQ_N2
P_REQ_N3
P_REQ_N4
P_REQ_N5
D16
D17
C16
C17
E10
A12
B18
B19
B10
F15
E11
F14
F16
F13
A14
E13
A13
A9
A7
C9
E7
D8
D7
C8
A3
B4
C5
B5
G8
F7
F8
G7
1
U4A
PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#/GPIO48
GPIO17/GNT5#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#/GPIO22
GPIO1/REQ5#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
ICH7-2-GP
1 OF 6
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
B15
C12
D12
C15
USB_OC6#_PULL_UP
A A
5
4
USB_OC7#_PULL_UP
3
R564
1 2
R565
1 2
8K2R2F-1-GP
8K2R2F-1-GP
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
ICH7 SECTIONS 1&2 OF 6
Size Document Number Rev
S15
B
Date: Sheet
2
Hsichih, Taipei
26 50Friday, December 12, 2008
1
-1
of
5
D D
IDE UNUSED Terminating
VCC3
R566
IDE_IORDYIDE_IORDY
1 2
8K2R2F-1-GP
C C
R567
1 2
8K2R2F-1-GP
IDE_IRQ
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AF16
AE15
AF15
AH15
AG16
AH17
AE17
AF17
AE16
AD16
AH16
4
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DDACK#
DDREQ
DIOR#
DIOW#
IORDY
DA0
DA1
DA2
DCS1#
DCS3#
IDEIRQ
3 OF 6
U4C
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
SATALED#
GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
GPIO37/SATA3GP
A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THERMTRIP#
AF3
AE3
AG2
AH2
AE5
AD5
AG4
AH4
AF7
AE7
AG6
AH6
AD9
AE9
AG8
AH8
AF1
AE1
AH10
AG10
AF18
AF19
AH18
AH19
AE19
AE22
AH28
AG27
AG22
AG21
AF22
AF25
AG26
AH24
AG23
AH21
AF23
AH22
AF26
3
SATAHDR_RX0_DN <33>
SATAHDR_RX0_DP <33>
SATAHDR_RX1_DN <33>
SATAHDR_RX1_DP <33>
SATAHDR_RX2_DN <33>
SATAHDR_RX2_DP <33>
SATAHDR_RX3_DN <33>
SATAHDR_RX3_DP <33>
CK_ICHSATA_DN <25>
CK_ICHSATA_DP <25>
SATARBIAS_ICH
ICH_SATA_LED_N
R150 4K7R2J-2-GP
1 2
TP_ICH_INIT_3_3V
KBRST_N <38>
SATAHDR_TX0_DN <33>
SATAHDR_TX0_DP <33>
SATAHDR_TX1_DN <33>
SATAHDR_TX1_DP <33>
SATAHDR_TX2_DN <33>
SATAHDR_TX2_DP <33>
SATAHDR_TX3_DN <33>
SATAHDR_TX3_DP <33>
ICH_SATA_LED_N <42>
A20GATE <38>
H_SB_A20M_N <9>
H_SB_CPUSLP_N <9>
H_SB_IGNNE_N <9>
H_SB_INIT_N <9>
H_SB_INTR <9>
H_SB_FERR_N <9>
H_SB_NMI <9>
SER_IRQ <28,38>
H_SB_SMI_N <9>
SB_STPCLK_N
H_SB_THERMTRIP_N <9>
VCC3
FWH_INIT_N <41>
0R2J-2-GP
R151
1 2
2
SATARBIAS_ICH
H_SB_STPCLK_N <9>
SB_STPCLK_N
R149
1 2
24D9R2F-L-GP
1
ICH7-2-GP
V_FSB_VTT
B B
R152 DUMMY-R2
H_SB_A20M_N<9>
H_SB_CPUSLP_N<9>
H_SB_IGNNE_N<9>
H_SB_INIT_N<9>
H_SB_INTR<9>
H_SB_NMI<9>
H_SB_SMI_N<9>
A A
SB_STPCLK_N
1 2
R154 DUMMY-R2
1 2
R155 DUMMY-R2
1 2
R156 DUMMY-R2
1 2
R157 DUMMY-R2
1 2
R158 DUMMY-R2
1 2
R159 DUMMY-R2
1 2
R160 DUMMY-R2
1 2
5
R152,R154~R160
change to Dummy-0729
4
3
ICH_SATA_LED_N
R153
1 2
10KR2J-3-GP
VCC3
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
ICH7 SECTIONS 3 OF 6
Size Document Number Rev
S15
B
Date: Sheet
2
Hsichih, Taipei
27 50Friday, December 12, 2008
1
-1
of
5
V_3P3_STBY\G
12
1MR2J-1-GP
ICH_RTCX2
12
C158
SC18P50V2JN-1-GP
R571
4K7R2J-2-GP
12
R572
4K7R2J-2-GP
VCC3
VCC3
ICH_RSMRST_N<38>
VCC3
D D
C C
B B
JP2
1
2
3
DVD-CON3-7-GP
1 - 2
2 - 3
1 2
ICH_RTCX1
12
SC18P50V2JN-1-GP
MODEL_SELECT
Aspire
Altos
R167
X2
34
1 2
RESO-32D768KHZ-GP
C157
delete R170 change to 10K
R169 4K7R2J-2-GP
L_DRQ_N<38>
SER_IRQ<27,38>
L_AD0<38,41>
A A
L_AD1<38,41>
L_AD2<38,41>
L_AD3<38,41>
1 2
R170
1 2
R172 4K7R2J-2-GP
1 2
R173 4K7R2J-2-GP
1 2
R174 4K7R2J-2-GP
1 2
R175 4K7R2J-2-GP
1 2
5
10KR2J-3-GP
4
L_AD0<38,41>
L_AD1<38,41>
L_AD2<38,41>
L_AD3<38,41>
L_DRQ_N<38>
L_FRAME_N<38,41>
ADD
R612,R613
R612
1 2
R613
1 2
CK_14M_ICH<25>
TP58 TPAD28
TP59 TPAD28
TP60 TPAD28
TP61 TPAD28
R165 DUMMY-R2
1 2
R166 0R2J-2-GP
1 2
ICH_RTCRST_PULLUP<31>
SMB_ALERT_PU<31>
SMB_CLK_RESUME<38,40>
SMB_DATA_RESUME<38,40>
SMLALERT_ICH<31>
SMLINK0_ICH<31>
SMLINK1_ICH<31>
SPI_MOSI<32>
SPI_MISO<32>
SPI_CS_N<32>
SPI_CLK<32>
RESERVED FOR 1K
SPKR
4
TP50
TPAD28
1
L_AD0
L_AD1
L_AD2
L_AD3
DUMMY-R2
DUMMY-R2
1
1
1
1
ICH_RTCX1
ICH_RTCX2
L_DRQ1_N
1
TP67
TPAD28
VCC3
1 2
AA5
LDRQ1#/GPIO23
AA6
LAD0
AB5
LAD1
AC4
LAD2
Y6
LAD3
AC3
LDRQ0#
AB3
LFRAME#
U1
ACZ_BIT_CLK
R5
ACZ_RST#
T2
ACZ_SDIN0
T3
ACZ_SDIN1
T1
ACZ_SDIN2
T4
ACZ_SDOUT
R6
ACZ_SYNC
AC1
CLK14
W1
EE_CS
W3
EE_DIN
Y2
EE_DOUT
Y1
EE_SHCLK
V3
LAN_CLK
U3
LAN_RSTSYNC
C19
LAN_RST#
U5
LAN_RXD0
V4
LAN_RXD1
T5
LAN_RXD2
U7
LAN_TXD0
V6
LAN_TXD1
V7
LAN_TXD2
AB1
RTXC1
AB2
RTCX2
AA3
RTCRST#
B23
SMBALERT#/GPIO11
C22
SMBCLK
B22
SMBDATA
A26
LINKALERT#
B25
SMLINK0
A25
SMLINK1
P5
SPI_MOSI
P2
SPI_MISO
P6
SPI_CS#
R2
SPI_CLK
P1
SPI_ARB
STRAPING:
NO REBOOT
FUNCTION
R568
DUMMY-R2
1 2
10KR2J-3-GP
R570
3
U4D
GPIO16/DPRSLPVR
GPIO33/AZ_DOCK_EN#
GPIO34/AZ_DOCK_RST#
GPIO35/SATACLKRE#
GPIO49/CPUPWRGD
ICH7-2-GP
SPK_X1
1
MMBT3904-7-F-GP
Q24
3
4 OF 64 OF 6
GPIO0/BM_BUSY#
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO18/STPPCI#
GPIO20/STPCPU#
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO32/CLKRUN#
GPIO38
GPIO39
THRM#
VRMPWRGD
MCH_SYNC#
PWRBTN#
SUS_STAT#
SUSCLK
SYS_RST#
PLTRST#
WAKE#
INTRUDER#
PWROK
RSMRST#
INTVRMEN
SPKR
SLP_S3#
SLP_S4#
SLP_S5#
TP0/BATLOW#
TP1/DPRSTP#
TP2/DPSLP#
TP3
SPK_X2
3
2
AB18
AC21
AC18
E21
E20
A20
F19
E19
R4
E22
AC22
AC20
AF21
R3
D20
A21
B21
E23
AG18
AC19
U2
AD21
AD20
AE20
AG24
AF20
AD22
AH20
C23
A28
RI#
A27
C20
A22
C26
F20
Y5
AA4
Y4
W4
A19
B24
D23
F22
C21
AF24
AH25
F21
1 2
VCC3
ICH_GP0
BACKUP_BUTTON
ICH_GPIO9
ICH_GPIO10
ICH_GPIO12
ICH_QRT0
ICH_QRT1
SPKR
1 2
33R2J-2-GP
R569
C462
SCD1U16V2ZY-2GP
12
R161
10KR2J-3-GP
ICH_GPIO6 <31,39>
FP_AUD_DETECT <31>
PME_N <38>
ICH_GPIO14
TP116
TP117
BACKUP_STATUS <42>
RAID_LED_CTRL2 <42>
TP52
TP53
ICH_GPIO38
ICH_GPIO39
H_PWRGD <9,43>
ICH_THRM_PU_N <31,38>
ICH_VRMPWRGD_PU <31,44>
ICH_SYNC_R_N
SW_ON_N <38>
ICH_RI_PU <31>
SUSCLK
FP_RST_N <9,31,43>
WAKE_N <31,35,40>
PWRGD_3V <15,38>
ICH_RSMRST_N <38>
ICH_INTVRMEN <31>
SLP_S3_N <38,48,50>
SLP_S4_N <38,47,49,50>
ICH_BATLOW_PU <31>
VCC
SPK_X3
2
SYS_STATUS <42>
SYS_ERROR <42>
PWR_LED <42>
RAID_LED_CTRL <42>
TP127 TPAD28
1
TP128 TPAD28
1
TP52 TPAD28
TP53 TPAD28
1
1
1
1
1
BUZZER
BUZ1
1
+
BUZZER
2
-
BUZZER-15-GP
2
V_3P3_STBY\G
12
12
R162
R163
10KR2J-3-GP
10KR2J-3-GP
TP116 TPAD28
TP117 TPAD28
ICH_GPIO9
TP62 TPAD28
TP121 TPAD28
1
TP63 TPAD28
TP64 TPAD28
TP65 TPAD28
TP66 TPAD28
TP_ICH_TP3 <31>
ICH_SYNC_R_N
<Variant Name>
Title
ICH7 SECTIONS 4 OF 6
Size Document Number Rev
S15
B
Date: Sheet
SA-0731-Delete
TP119 and TP120,
chagne net TP119
and TP 120 to
ICH_GPIO38 and
ICH_GPIO39 and
12
R164
pull high to VCC3
ICH_GPIO38
10KR2J-3-GP
SA-change net RESET_BUTTON
from SIO GP54 to ICH_GPIO10
MODEL_SELECT
BACKUP_BUTTON
V_3P3_STBY\G
10KR2J-3-GP
12
12
ICH_GPIO39
RESET_BUTTON <40>
ICH_GPIO12 <38>
12
R614
JP3
1 2
1R2P-2-GP
Delete TP122 and add R614, JP3
R168
0R2J-2-GP
PLTRST_N <15,35,38>
C159
SC150P-GP
R171
1 2
0R2J-2-GP
1
10KR2J-3-GP
Add R627
ICH_GPIO14
BACKUP_BUTTON <42>
ICH_SYNC_N <15>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
1
12
R615
28 50Friday, December 12, 2008
VCC3
12
R616
10KR2J-3-GP
V_3P3_STBY\G
12
R627
10KR2J-3-GP
of
-1
5
4
3
2
1
V_3P3_STBY\G
1
1
1
1
1
TP69 TPAD28
TP70 TPAD28
TP71 TPAD28
TP72 TPAD28
TP73 TPAD28
V_REF5V
V_REF5V_SUS
V_1P5_CORE_FILTERED
VCCDMI_PLL_ICH
V_ICH_CORE
V_FSB_VTT
VCC3
V_3P0_BAT_VREG
SC10U6D3V3MX-GP
V_1P5_CORE
12
C160
SCD1U50V3KX-GP
12
C161
L3
1 2
BLM18PG181SN1D-GP
V_1P5_CORE
AG11
AG14
AG17
AG20
AG25
AC11
AD11
AD15
AD19
AD23
AE11
AE13
AE18
AE21
AE24
AE25
AF11
AF27
AF28
AH23
AH27
AH12
W24
W25
W26
AA24
AA25
AA26
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
U4F
E4
C27
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
Y3
Y24
Y27
Y28
AA1
AB4
AB6
AC2
AC5
AC9
AD1
AD3
AD4
AD7
AD8
AE2
AE4
AE8
AF2
AF4
AF8
AG1
AG3
AG7
AH1
AH3
AH7
6 OF 6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A4
VSS
A23
VSS
B1
VSS
B8
VSS
B11
VSS
B14
VSS
B17
VSS
B20
VSS
B26
VSS
B28
VSS
C2
VSS
C6
VSS
D10
VSS
D13
VSS
D18
VSS
D21
VSS
D24
VSS
E1
VSS
E2
VSS
E8
VSS
E15
VSS
F3
VSS
F4
VSS
F5
VSS
F12
VSS
F27
VSS
F28
VSS
G1
VSS
G2
VSS
G5
VSS
G6
VSS
G9
VSS
G14
VSS
G18
VSS
G21
VSS
G24
VSS
G25
VSS
G26
VSS
H3
VSS
H4
VSS
H5
VSS
H24
VSS
H27
VSS
H28
VSS
J1
VSS
J2
VSS
J5
VSS
J24
VSS
J25
VSS
J26
VSS
K24
VSS
K27
VSS
K28
VSS
L13
VSS
L15
VSS
L24
VSS
L25
VSS
L26
VSS
M3
VSS
M4
VSS
M5
VSS
M12
VSS
M13
VSS
M14
VSS
M15
VSS
M16
VSS
M17
VSS
M24
VSS
M27
VSS
M28
VSS
N1
VSS
N2
VSS
N5
VSS
N6
VSS
N11
VSS
N12
VSS
N13
VSS
N14
VSS
N15
VSS
N16
VSS
N17
VSS
N18
VSS
N24
VSS
N25
VSS
N26
VSS
P3
VSS
P4
VSS
P12
VSS
P13
VSS
P14
VSS
P15
VSS
P16
VSS
P17
VSS
P24
VSS
P27
VSS
P28
VSS
R1
VSS
R11
VSS
R12
VSS
R13
VSS
V_1P5_CORE
D D
V_1P5_CORE
C C
B B
AB10
AB17
AC10
AC17
AD10
AE10
AF10
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
A1
VCC1_5_A
VCC1_5_A
VCC1_5_A
AB7
VCC1_5_A
AB8
VCC1_5_A
AB9
VCC1_5_A
VCC1_5_A
VCC1_5_A
AC6
VCC1_5_A
AC7
VCC1_5_A
AC8
VCC1_5_A
VCC1_5_A
AD6
VCC1_5_A
VCC1_5_A
AE6
VCC1_5_A
VCC1_5_A
AF5
VCC1_5_A
AF6
VCC1_5_A
AF9
VCC1_5_A
AG5
VCC1_5_A
AG9
VCC1_5_A
AH5
VCC1_5_A
AH9
VCC1_5_A
F17
VCC1_5_A
G17
VCC1_5_A
H6
VCC1_5_A
H7
VCC1_5_A
J6
VCC1_5_A
J7
VCC1_5_A
T7
VCC1_5_A
D26
VCC1_5_B
D27
VCC1_5_B
D28
VCC1_5_B
E24
VCC1_5_B
E25
VCC1_5_B
E26
VCC1_5_B
F23
VCC1_5_B
F24
VCC1_5_B
G22
VCC1_5_B
G23
VCC1_5_B
H22
VCC1_5_B
H23
VCC1_5_B
J22
VCC1_5_B
J23
VCC1_5_B
K22
VCC1_5_B
K23
VCC1_5_B
L22
VCC1_5_B
L23
VCC1_5_B
M22
VCC1_5_B
M23
VCC1_5_B
N22
VCC1_5_B
N23
VCC1_5_B
P22
VCC1_5_B
P23
VCC1_5_B
R22
VCC1_5_B
R23
VCC1_5_B
R24
VCC1_5_B
R25
VCC1_5_B
R26
VCC1_5_B
T22
VCC1_5_B
T23
VCC1_5_B
T26
VCC1_5_B
T27
VCC1_5_B
T28
VCC1_5_B
U22
VCC1_5_B
U23
VCC1_5_B
V22
VCC1_5_B
V23
VCC1_5_B
W22
VCC1_5_B
W23
VCC1_5_B
Y22
VCC1_5_B
Y23
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCCSUS3_3/VCCSUSHDA
VCCSUS3_3/VCCLAN3_3
VCCSUS3_3/VCCLAN3_3
VCCSUS3_3/VCCLAN3_3
VCCSUS3_3/VCCLAN3_3
VCCSUS1_05/VCCLAN1_05
VCCSUS1_05/VCCLAN1_05
U4E
5 OF 6
V5REF
V5REF
V5REF_SUS
VCCRTC
VCCUSBPLL
VCCSATAPLL
VCCDMIPLL
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
V_CPU_IO
V_CPU_IO
V_CPU_IO
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3/VCCHDA
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS1_05
VCCSUS1_05
VCCSUS1_05
AD17
G10
F6
W5
C1
AD2
AG28
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
AE23
AE26
AH26
A5
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
AH11
B13
B16
B27
B7
C10
D15
F9
G11
G12
G16
U6
A24
C24
D19
D22
E3
G19
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
P7
R7
V1
V5
W2
W7
AA2
C28
G20
K7
Y7
ICH7-2-GP
ICH7-2-GP
A A
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
ICH7 SECTIONS 5&6 OF 6
Size Document Number Rev
S15
C
Date: Sheet
5
4
3
2
Hsichih, Taipei
-1
of
29 50Friday, December 12, 2008
1
5
4
3
2
1
PCI
C162
1 2
D D
SCD1U10V2KX-4GP
C169
1 2
SCD1U10V2KX-4GP
C170
1 2
SCD1U10V2KX-4GP
VCC3
CLOSE TO ICH
V_1P5_CORE
C C
B B
C175
1 2
SCD1U10V2KX-4GP
C177
1 2
SCD1U10V2KX-4GP
C179
1 2
SCD1U10V2KX-4GP
CLOSE TO POWER
CORRIDORS
V_1P5_CORE
C181
1 2
SC1U10V2KX-1GP
CLOSE TO ICH
PIN AH5
V_FSB_VTT
CLOSE TO ICH
12
12
C166
SCD1U10V2KX-4GP
12
C167
V_3P0_BAT_VREG
V_REF5V
V_REF5V_SUS
C171
SCD1U10V2KX-4GP
C176
SCD1U10V2KX-4GP
C178
SCD1U10V2KX-4GP
1 2
1 2
1 2
C165
SC4D7U10V3KX-GP
SCD1U10V2KX-4GP
CLOSE TO ICH
VCC3
C183
1 2
SCD1U10V2KX-4GP
CLOSE TO ICH
PIN AH11
C185
A A
1 2
SCD1U10V2KX-4GP
CLOSE TO ICH
PIN B27
VCC3
5
DMI PLL FILTER
V_1P5_CORE VCCDMI_PLL_ICH
L4
1 2
BLM18PG181SN1D-GP
12
12
C187
C186
SC4D7U10V3KX-GP
SCD01U50V2KX-1GP
4
delete C184
3
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
MISC DECOUPLING
Size Document Number Rev
S15
B
Date: Sheet
2
Hsichih, Taipei
30 50Friday, December 12, 2008
1
-1
of
5
VCC3
12
12
R176
D D
DUMMY-R2
10KR2J-3-GP
R177
12
R178
10KR2J-3-GP
12
R179
10KR2J-3-GP
4
FP_AUD_DETECT <28>
ICH_GPIO6 <28,39>
ICH_THRM_PU_N <28,38>
ICH_VRMPWRGD_PU <28,44>
3
V_3P0_BAT_VREG
ALWAYS STUFF PULL-UP TO ENABLE INTERNAL
VRM EXTERNAL VRM IS NOT SUPPORTED ON THIS
DESIGN
R181
1 2
390KR2J-GP
ICH_INTVRMEN <28>
V_3P0_BAT_VREG
20KR2J-L2-GP
2
R180
1 2
12
C188
SC1U10V2KX-1GP
PLACE CLOSE TO ICH
1
ICH_RTCRST_PULLUP <28>
R176 change to Dummy,for VRM's power good already pull high
V_3P3_STBY\G
VCC3
5
10KR2J-3-GP
12
12
R184
R190
12
C C
B B
A A
R183
1KR2J-1-GP
DUMMY-R2
12
R185
10KR2J-3-GP
RESERVE
FOR 330R
TP_ICH_TP3 <28>
12
R186
8K2R2F-1-GP
FP_RST_N <9,28,43>
SMB_ALERT_PU <28>
ICH_RI_PU <28>
WAKE_N <28,35,40>
4
V_3P3_STBY\G
R182 10KR2J-3-GP
1 2
R187 10KR2J-3-GP
1 2
R188 10KR2J-3-GP
1 2
V_3P3_STBY\G
JP1
DVD-CON3-7-GP
MOBILE BATTERY STRAP
TP_CLRCMOS
1
2
NET_CLR_CMOS_JUMPER
3
1 - 2
2 - 3
R189
1 2
10KR2J-3-GP
1
ICH_RTCRST_PULLUP <28>
NORMAL
CLR CMOS
3
SMLALERT_ICH <28>
SMLINK0_ICH <28>
SMLINK1_ICH <28>
ICH_BATLOW_PU <28>
TP74
TPAD28
12
R191
4K7R2J-2-GP
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
ICH PULL UP
Size Document Number Rev
S15
B
Date: Sheet
2
Hsichih, Taipei
31 50Friday, December 12, 2008
1
-1
of
5
4
3
2
1
VCC VCC3
D D
C189
1 2
SCD1U10V2KX-4GP
FOR POWER PLANE CROSS CAP, PLACE CLOSE TO SPI_CLK TRACE
SPI_VCC3
V_3P3_STBY\G
C C
12
12
R195
8K2R2F-1-GP
RESERVE FOR 8.2K
SPI_MISO <28>
SPI_CS_N <28>
SPI_MOSI<28>
SPI_CLK<28>
SPI_HOLD0_N
VCC3
SA-0731-R194,R195,R196 mount 8.2K
12
R196
8K2R2F-1-GP
RESERVE FOR 8.2K
1 2
R199
1 2
RESERVE FOR 0R
R198
47R2J-2-GP
47R2J-2-GP
SKT1
5
7
8
SKT-G6179-GP-U
4
36
2
1
1 2
R200
1 2
47R2J-2-GP
R194
8K2R2F-1-GP
SPI_WP0_N
12
R192
1KR2J-1-GP
12
R197
DUMMY-R2
RESERVE FOR ENABLE
EXTERNAL FLASH PROTECT
12
R193
1KR2J-1-GP
SPI_HOLD0_N
SPI_WP0_N
R201 DUMMY-R2
B B
V_3P3_STBY\G
R202
1 2
0R2J-2-GP
SPI_VCC3
SPI_VCC3
12
C190
SC4D7U10V3KX-GP
12
C191
SCD1U10V2KX-4GP
PLACE CLOSE TO FLASH SKT
<Variant Name>
A A
Title
SPI FLASH
Size Document Number Rev
S15
B
Date: Sheet
5
4
3
2
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
32 50Friday, December 12, 2008
1
-1
5
CN6
8
D D
1
2
3
4
5
6
7
9
4
SATA_TX_DP0
SATA_TX_DN0
SATA_RX_DN0
SATA_RX_DP0
3
C192 SCD01U50V2KX-1GP
12
C193 SCD01U50V2KX-1GP
12
C194 SCD01U50V2KX-1GP
12
C195 SCD01U50V2KX-1GP
12
SATAHDR_TX0_DP <27>
SATAHDR_TX0_DN <27>
SATAHDR_RX0_DN <27>
SATAHDR_RX0_DP <27>
2
1
MLX-CON7-8-GP
CN7
8
1
2
3
C C
4
5
6
7
9
SATA_TX_DP1
SATA_TX_DN1
SATA_RX_DN1
SATA_RX_DP1
C196 SCD01U50V2KX-1GP
12
C197 SCD01U50V2KX-1GP
12
C198 SCD01U50V2KX-1GP
12
C199 SCD01U50V2KX-1GP
12
SATAHDR_TX1_DP <27>
SATAHDR_TX1_DN <27>
SATAHDR_RX1_DN <27>
SATAHDR_RX1_DP <27>
MLX-CON7-8-GP
CN8
8
1
2
3
4
5
6
B B
7
9
SATA_TX_DP2
SATA_TX_DN2
SATA_RX_DN2
SATA_RX_DP2
C200 SCD01U50V2KX-1GP
12
C201 SCD01U50V2KX-1GP
12
C202 SCD01U50V2KX-1GP
12
C203 SCD01U50V2KX-1GP
12
SATAHDR_TX2_DP <27>
SATAHDR_TX2_DN <27>
SATAHDR_RX2_DN <27>
SATAHDR_RX2_DP <27>
MLX-CON7-8-GP
CN9
8
1
2
3
4
5
6
A A
7
9
MLX-CON7-8-GP
5
4
SATA_TX_DP3
SATA_TX_DN3
SATA_RX_DN3
SATA_RX_DP3
C204 SCD01U50V2KX-1GP
12
C205 SCD01U50V2KX-1GP
12
C206 SCD01U50V2KX-1GP
12
C207 SCD01U50V2KX-1GP
12
3
SATAHDR_TX3_DP <27>
SATAHDR_TX3_DN <27>
SATAHDR_RX3_DN <27>
SATAHDR_RX3_DP <27>
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
SATA CONNECTOR
Size Document Number Rev
S15
B
Date: Sheet
2
Hsichih, Taipei
33 50Friday, December 12, 2008
1
-1
of
5
4
3
2
1
VCC3
R203 8K2R2F-1-GP
D D
VCC3
R205 8K2R2F-1-GP
P_INTA_N<26>
1 2
PCI_SERR_N<26>
PCI_DEVSEL_N<26>
PCI_IRDY_N<26>
PCI_PLOCK_N<26>
R208 8K2R2F-1-GP
P_INTB_N<26>
P_INTD_N<26>
1 2
R211 8K2R2F-1-GP
1 2
PCI_PERR_N<26>
PCI_FRAME_N<26>
PCI_TRDY_N<26>
R214 8K2R2F-1-GP
C C
P_INTC_N<26>
P_INTE_N<26>
P_INTG_N<26>
P_INTH_N<26>
1 2
R216 8K2R2F-1-GP
1 2
R219 8K2R2F-1-GP
1 2
R222 8K2R2F-1-GP
1 2
PCI_STOP_N<26>
P_REQ_N0<26>
P_REQ_N1<26>
P_REQ_N2<26>
P_REQ_N3<26>
P_REQ_N4<26>
P_REQ_N5<26>
1 2
R204 8K2R2F-1-GP
1 2
R206 8K2R2F-1-GP
1 2
R207 8K2R2F-1-GP
1 2
R209 8K2R2F-1-GP
1 2
R210 8K2R2F-1-GP
1 2
R212 8K2R2F-1-GP
1 2
R213 8K2R2F-1-GP
1 2
R215 8K2R2F-1-GP
1 2
R217 8K2R2F-1-GP
1 2
R218 8K2R2F-1-GP
1 2
R220 8K2R2F-1-GP
1 2
R221 8K2R2F-1-GP
1 2
R223 8K2R2F-1-GP
1 2
R224 8K2R2F-1-GP
B B
P_INTF_N<26>
1 2
<Variant Name>
A A
Title
PCI TERMINATION
Size Document Number Rev
S15
B
Date: Sheet
5
4
3
2
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
34 50Friday, December 12, 2008
1
-1
5
1D2V_LAN
12
C230
3D3V_LAN
R522
1 2
0R2J-2-GP
3D3V_LAN
VCC3
D D
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
PCIE_ICH_RXP5<26>
PCIE_ICH_RXN5<26>
3D3V_LAN
12
R237
10KR2J-3-GP
C C
B B
V_3P3_STBY\G
12
12
C227
C228
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
20 mils for CTRL trace
C212
C213
CTRL12
1 2
1 2
PCIE_ICH_TXN5_NIC<26>
PCIE_ICH_TXP5_NIC<26>
CK_PE_100M_LAN_DP<25>
CK_PE_100M_LAN_DN<25>
12
R236
4K7R2J-2-GP
BCP69T1-1-GP
PCIE_ICH_RXP5_LAN
PCIE_ICH_RXN5_LAN
SMB_ALERT#_LAN
LED_LAN_ACT
LAN_LINK100
LED_LAN_LINK_GIGA
LED_LAN_LINK_IND
1D2V_LAN
3
Q22
1
2
12
C229
1D8V_LAN
R521
1 2
DUMMY-R2
48
U5
49
VDD
TX_P
50
TX_N
51
NC#51
52
NC#52
53
RX_N
54
RX_P
55
REFCLKP
56
REFCLKN
57
SMALERT#
58
VDD
59
LED_ACT#
60
LED_LINK10/100#
61
VDDO_TTL
62
LED_LINK1000#
63
LED_DUPLEX#
64
SMCLK
65
GND
VDDO_TTL
88E8071-B0-GP
123456789101112131415
CTRL12
CTRL18
PLTRST_N<15,28,38>
WAKE_N<28,31,40>
LANPWR
VMAIN_AVLBL
VDD
TESTMODE
CTRL12
4
R242
VDD
VDDO_TTL
CTRL18
PERST#/TSTPT
1 2
LAN_CLKREQ#
SMDATA
WAKE#
4K7R2J-2-GP
VPD_DATA
CLKREQ#
VPD_DATA
VDD
AVDDH/3_3V
VDDO_TTL
SWITCH_VAUX
12
3D3V_LAN
3D3V_LAN
VPD_CLK
VDD
VPD_CLK
LOM_DISABLE#
SWITCH_VCC
SPI_CS
SPI_CLK
VAUX_AVLBL
VDD
R239
4K7R2J-2-GP
SPI_DI
SPI_DO
RESERVED#29
RESERVED#25
RESERVED#24
XTALO
XTALI
XTL_LAN_DP
XTL_LAN_DN
RN1
4
SRN10KJ-5-GP
(R)
Unmount
333435363738394041424344454647
VDD
NC#32
MDIN3
MDIP3
AVDD
MDIN2
MDIP2
AVDD
AVDD
MDIN1
MDIP1
AVDD
MDIN0
MDIP0
RSET
16
12
R238
4K99R2F-L-GP
23
1
VCC3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
LAN_MDI3_DN
LAN_MDI3_DP
LAN_MDI2_DN
LAN_MDI2_DP
LAN_MDI1_DN
LAN_MDI1_DP
LAN_MDI0_DN
LAN_MDI0_DP
3
1D8V_LAN
USB_BACK1_R_DP<36>
USB_BACK2_R_DP<36>
USB_BACK1_R_DN<36>
USB_BACK2_R_DN<36>
VCCUSB2
Delete C14 and R233 for EMI
Delete net 0
1D8V_LAN_CON
12
C12
SCD1U10V2KX-4GP
1D8V_LAN
12
C232
SC1U10V2KX-1GP
1D2V_LAN
12
C238
SC1U10V2KX-1GP
USB_BACK1_R_DP
USB_BACK2_R_DP
USB_BACK1_R_DN
USB_BACK2_R_DN
12
C233
SCD1U10V2KX-4GP
12
C239
SC1U10V2KX-1GP
12
12
C234
SCD1U10V2KX-4GP
12
C240
SC1U10V2KX-1GP
R231
1 2
DUMMY-R2
X3
1 2
XTAL-25MHZ-67GP
C210
SC20P50V2JN-1GP
12
C235
SC1KP50V2KX-1GP
12
C241
SC1U10V2KX-1GP
Change RJ1 Library to
RJ45+USB-20-GP,need
double check
RJ1
30
RJ45+USB-20-GP
XTL_LAN_DN
XTL_LAN_DP
GREEN
YELLOW
28
22
18
21
17
20
16
19
15
27
29
F7
FUSE-1D5A6V-7GP
EOL change to
69.50007.961
Reserved for 1M
12
C211
SC20P50V2JN-1GP
12
12
C236
C237
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
12
C242
C454
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
24
26
LED_LAN_LINK_GIGA_1
11
YELLOW
LAN_LINK100_1
12
1
2
3
4
5
6
7
8
9
10
13
LED_LAN_ACT_1
14
25
23
V_5_USB
1 2
12
12
C455
C456
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
1 2
R228 200R2J-L1-GP
1 2
1D8V_LAN_CON
1 2
F7
POLYSW-1D5A8V-GP-U
12
C484
SC1KP50V2KX-1GP
V_3P3_STBY\G
R623
200R2J-L1-GP
1 2
LAN_LINK100
R625 0R2J-2-GP
LED_LAN_LINK_GIGA
LAN_MDI0_DP
LAN_MDI0_DN
LAN_MDI1_DP
LAN_MDI1_DN
LAN_MDI2_DP
LAN_MDI2_DN
LAN_MDI3_DP
LAN_MDI3_DN
R225
200R2J-L1-GP
LED_LAN_ACT
BLM21PG600SN1-GP
1 2
12
R527
10KR2F-2-GP
12
R529
15KR2F-GP
SA-0731-R529 change from 560K to
15K from Intel feedback
LED_STATUS<42>
SA-0804-U25 AT24C08AN-1-GP
EOL change to
AT24C08BN-SH-T-GP
V_3P3_STBY\G
R624
200R2J-L1-GP
FCM2012KF-GP
1 2
V_3P3_STBY\G
100MHz 60ohm
3A,
DCR=25mohm
L28
1 2
L6
Add L6,R623,R624
VCCUSB2VCCUSB2_A
12
C481
12
C482
SC100U6D3V0MX-2GP
SC100U6D3V0MX-2GP
Remove U6 R233 C214 to
connect front LAN LED to
LED_LAN_ACT directly
LED_LAN_ACT
1
1D8V_LAN
12
C483
SCD1U16V2KX-3GP
USB_OC_BACK_12 <26>
3D3V_LAN
12
R240
12
R241
SC10U10V5KX-2GP
SCD1U10V2KX-4GP
V_3P3_STBY\G
12
12
12
12
C216
A A
SCD1U10V2KX-4GP
BC2
BC1
SC10U6D3V5KX-2GP
SC10U6D3V5KX-2GP
C217
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
20 mils for CTRL trace
5
12
C218
CTRL18
BCP69T1-1-GP
12
R235
4K7R2J-2-GP
1
SC10U10V5KX-2GP
3
2
12
C219
V_3P3_STBY\G
L5
1 2
BLM18PG600SN-2GP
12
Q21
1D8V_LAN
12
C226
SCD1U10V2KX-4GP
C220
SC22U6D3V5MX-2GP
4
12
12
C221
SCD1U16V2KX-3GP
12
C222
C223
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3D3V_LAN
12
12
C224
C225
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3
LAN_MDI0_DP
LAN_MDI0_DN
12
12
R533
R534
49D9R2F-GP
49D9R2F-GP
12
C208
SC1000P50V3JN-GP
LAN_MDI1_DP
LAN_MDI1_DN
12
12
R535
R536
49D9R2F-GP
49D9R2F-GP
12
C209
SC1000P50V3JN-GP
LAN_MDI2_DP
LAN_MDI2_DN
12
12
R537
R538
49D9R2F-GP
49D9R2F-GP
12
C215
SC1000P50V3JN-GP
LAN_MDI3_DP
LAN_MDI3_DN
12
12
R539
R540
49D9R2F-GP
49D9R2F-GP
12
C231
SC1000P50V3JN-GP
2
U25
1
A0
VCC
2
A1
WP
3
A2
SCL
4 5
GND SDA
AT24C08BN-SH-T-GP
Title
LAN 88E8071
Size Document Number Rev
S15
C
Date: Sheet
8
7
6
1
4K7R2J-2-GP
4K7R2J-2-GP
VPD_CLK
VPD_DATA
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
35 50Friday, December 12, 2008
-1
5
D D
USB_BACK1_DN<26>
1
4
USB_BACK1_DP<26>
C C
USB_BACK2_R_DN
2
L8
DLW21HN900SQ2LGP
3
USB_BACK2_R_DP
USB_BACK2_R_DN <35>
USB_BACK2_R_DP <35>
4
USB_BACK2_DN<26>
USB_BACK2_DP<26>
1
4
3
USB_BACK1_R_DN
2
L9
DLW21HN900SQ2LGP
3
USB_BACK1_R_DP
USB_BACK1_R_DN <35>
USB_BACK1_R_DP <35>
SC100U6D3V0MX-2GP
C486
2
F6
FUSE-1D5A6V-7GP
100MHz 60ohm
3A,
DCR=25mohm
BLM21PG600SN1-GP
L29
1 2
12
C487
USB_OC_BACK_34<26>
12
12
C488
SCD1U16V2KX-3GP
SC100U6D3V0MX-2GP
VCCUSB1_AVCCUSB1
EOL change to
69.50007.961
12
R525
10KR2F-2-GP
12
R526
15KR2F-GP
For 2 Port USB
F6
1 2
1
POLYSW-1D5A8V-GP-U
12
C489
SC1KP50V2KX-1GP
V_5_USB
USB_BACK3_DN<26>
1
B B
4
A A
5
USB_BACK4_R_DN
2
L10
DLW21HN900SQ2LGP
3
USB_BACK4_R_DP
4
USB_BACK4_DN<26>
USB_BACK4_DP<26>USB_BACK3_DP<26>
1
4
USB_BACK3_R_DN
2
L11
DLW21HN900SQ2LGP
3
USB_BACK3_R_DP
3
SKT2
VCCUSB1 VCCUSB1
USB_BACK3_R_DN
USB_BACK3_R_DP
<Variant Name>
Title
Size Document Number Rev
B
Date: Sheet
2
9
1
2
3
4
11
NOT SURE WHICH ONE COULD BE USED
USB CONN
S15
10
5
6
7
8
12
SKT-USB-44-GP
USB_BACK4_R_DN
USB_BACK4_R_DP
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
1
-1
of
36 50Friday, December 12, 2008
SA-0731-R526 change from 560K to 15K
5
http://hobi-elektronika.net/
CN10
8 9
D D
XTLIN XTLOUT
1 2
12
C249
C C
SC18P50V2JN-1-GP
SA-0730-X4 CHANGE TO
SMALL PACKGAE
VCC3
L12
1 2
BLM18PG600SN-2GP
B B
VCC3
L14
1 2
BLM18PG600SN-2GP
NP1
1
2
3
4
5
6
7
NP2
1011
AMP-CON7-12-GP
X4
XTAL-20MHZ-5-U1
12
C251
SC2D2U10V3KX-1GP
12
C265
12
C250
SC18P50V2JN-1-GP
SCD1U16V2KX-3GP
S1_TXP1
S1_TXN1
S1_RXN1
S1_RXP1
12
C252
12
C266
REF_CFG1
REF_CFG0
C243
1 2
C244
1 2
C245
1 2
C246
1 2
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
R249
0R2J-2-GP
VAA2_0
12
C253
SC1KP50V2KX-1GP
SCD01U16V2KX-3GP
VAA2_1
12
C267
12
C254
12
C268
S_TXP1
S_TXN1
S_RXN1
S_RXP1
12
R250
0R2J-2-GP
PCIE_ICH_RXN6_ESATA
PCIE_ICH_RXP6_ESATA
1D2V_LAN
BLM18PG600SN-2GP
VCC3
BLM18PG600SN-2GP
VCC3
L7
1 2
L15
1 2
4
R243
1 2
10KR2F-2-GP
R244
1 2
10KR2F-2-GP
PCLKP
12
R245
100R2F-L1-GP-U
PCLKN
C247
1 2
C248
1 2
PCIE_ICH_TXN6_ESATA
PCIE_ICH_TXP6_ESATA
NEED DOUBLE CHECK
V_1.2V
12
C255
SCD1U16V2KX-3GP
12
12
C269
C270
6121_HDD7
6121_HIORDY
PCLKP <25>
PCLKN <25>
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
12
C256
C257
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
VCC_33
12
C271
PCIE_ICH_RXN6 <26>
PCIE_ICH_RXP6 <26>
PCIE_ICH_TXN6_ESATA <26>
PCIE_ICH_TXP6_ESATA <26>
VDD_12
12
12
C258
C259
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
12
C272
C273
3
SC2D2U10V3KX-1GP
10KR2F-2-GP
12
C260
12
R246
TP132TPAD28
TP133TPAD28
TP82TPAD28
V_1P5_SFR
TP_ESATA_GPIO1
1
TP_ESATA_GPIO2
1
6121_TESTMODE
TP78TPAD28
TP79TPAD28
TP80TPAD28
TP81TPAD28
1
12
L13
1 2
BLM18PG600SN-2GP
TP129TPAD28
TP130TPAD28
TP131TPAD28
1
1
VAA2_1
1
1
S_RXP1
S_RXN1
VAA2_0
S_TXN1
S_TXP1
VAA1
XTLIN
XTLOUT
6121_S_ISET
6121_TP
R251
6K04R2F-GP
12
C261
1
1
1
20 77
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
R252
ORCAD SYMBOL IS 88SE6121,BOM SHOULD BE CHANGE
88SE6111
12
C262
2
VDD_12
VCC_33
H_DDIO_N
AVDDL
PCLKN
VDDIO
H_DD9
CLKP
CLKN
PCLKP
VDD_12
H_DD4
H_DD5
H_DD10
PERST_N
WAKE_N
VDD
6121_WAKE_EN
VCC3
12
R253
10KR2F-2-GP
VDD_12
VDD
H_DD3
H_DD11
H_DMARQ
H_DMACK_N
H_INTRQ
H_CS0_N
H_RST_N
CLK_CFG1
CLK_CFG0
REF_CFG0
REF_CFG1
1
6121_HIORDY
1234567891011121314151617181940
H_DD12
H_IORDY
H_DIOW_N
UAO
H_DD2
H_DD13
VDD
H_DD1
H_DD14
VDDIO
H_DD0
H_DD15
VDD
H_DA1
H_DA0
H_DA2
H_CS1_N
5756555453525150494847464544434241
ESATA_RST_N
12
R254
10KR2F-2-GP
6121_HDD7
TP_ESATA_GPIO0
TP_ESATA_ACT1
TP_ESATA_ACT0
VDD
ACT0
ACT1
GPIO0HSDACN
GPIO1 GND
GPIO2
TESTMODE
RXP1
RXN1
VAA2
TXN1
TXP1
VSS
RXP0
RXN0
VAA2
TXN0
TXP0
VAA1
XTLIN
XTLOUT
S_ISET
TP
HSDACP
ISET
39
12
6K04R2F-GP
AVDDT
12
C263
PTXN
AVDD
PCIE_ICH_RXN6_ESATA
H_CBLID_N
AVDD
PCIE_ICH_RXP6_ESATA
12
C264
H_DD8
H_DD7
AVDDT
PTXP
AVDDT
PCIE_ICH_TXN6_ESATA
H_DD6
PRXP
PRXN
PCIE_ICH_TXP6_ESATA
AVDDL
U8
88SE6121-GP-U1
76
75
74
UAI
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
TP134 TPAD28
UAO
UAI
UAO
UAI
VDD_12
VCC_33
6121_DMARQ
VDD_12
6121_INTRQ
1
1
1
R247
1 2
R248
1 2
ESATA_RST_N <38>
TP83
TPAD28
TP84
TPAD28
5K6R2J-1-GP
5K6R2J-1-GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
C276
AVDDL
SC1KP50V2KX-1GP
<Variant Name>
Wistron Incorporated
12
C277
Title
E-SATA CONTROLLER
Size Document Number Rev
S15
SC1KP50V2KX-1GP
2
B
Date: Sheet
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
37 50Friday, December 12, 2008
1
-1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC2D2U10V3KX-1GP
VCC3
L17
A A
1 2
BLM18PG600SN-2GP
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
C278
5
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C279
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
C280
VAA1
SC1KP50V2KX-1GP
12
C281
SC1KP50V2KX-1GP
VCC3
1 2
BLM18PG600SN-2GP
SC10U10V5KX-2GP
L18
12
12
C282
C283
SCD1U16V2KX-3GP
SC2D2U10V3KX-1GP
4
SCD1U16V2KX-3GP
12
C284
AVDD
SCD1U16V2KX-3GP
12
C285
SC1KP50V2KX-1GP
3
V_1P5_SFR
1 2
BLM18PG600SN-2GP
SC2D2U10V3KX-1GP
L16
12
12
C275
C274
SCD1U16V2KX-3GP
SC2D2U10V3KX-1GP
5
http://hobi-elektronika.net/
VCC3
SA-0804 Add R226
Dummy, and
connector to
ICH_GPIO12
D D
ICH_GPIO12<28>
2.5V I2C
inferface
5V I2C
inferface
R226
1 2
DUMMY-R2
mount R219,R224
OPEN R227,R228
mount R227,R228
OPEN R219,R224
SIO_SMI_N
V_3P3_STBY\G
R259 10KR2J-3-GP
1 2
R260 10KR2J-3-GP
1 2
R261 3K3R2J-3-GP
1 2
R262 3K3R2J-3-GP
1 2
delete R255,R256
R257 3K3R2J-3-GP
1 2
R258 3K3R2J-3-GP
1 2
SIO_SMI_N
PME_N
SMB_CLK_RESUME
SMB_DATA_RESUME
L_AD[3..0]<28,41>
R264,R268 reserved for 0 ohm
R2840R2J-2-GP
R2860R2J-2-GP
G1
COPPER-CLOSE
R291
L_FRAME_N<28,41>
L_DRQ_N<28>
CK_P_33M_PA<25>
SER_IRQ<27,28>
CK_14M_PA<25>
PME_N<28>
HDD1_PWR<40>
HDD3_PWR<40>
SMB_CLK_RESUME<28,40>
SMB_DATA_RESUME<28,40>
SIO_PROCHOT_N
12
12
12
12
12
12
C286SC100P50V2JN-3GP
12
C287SC100P50V2JN-3GP
12
G2
12
1 2
33R2J-2-GP
VR THERMAL THROTTLE CIRCUITRY
SIO_PROCHOT_N
R264
DUMMY-R2
SMB_CLK_MAINSMB_CLK_MAIN
SMB_CLK_AMT<43>
C C
SMB_DATA_AMT<43>
if C457 is used,vender recommend 2200pf
R292
R296
12
12
R543
1 2
DUMMY-R2
R544
1 2
DUMMY-R2
BP_THERM_DC<40>
BP_THERM_DA<40>
H_TEMP_SRC_DP_MB
H_TEMP_RET_DN_MB
B B
1K74R3F-GP
180R3F-GP
A A
C457
DUMMY-C2
VCCV_1P5_CORE
12
12
(M)
(M)
THERM_DP_NB
12
THERM_DN_NB
R293
1K24R2F-GP
R297
360R2F-GP
12
SMB_CLK_RESUME
R2650R2J-2-GP
12
R268
DUMMY-R2
SMB_DATA_MAINSMB_DATA_MAIN
12
R2700R2J-2-GP
SMB_DATA_RESUME
12
Q23
3
MMBT3904-7-F-GP
1
2
FAN_CTL3<42>
NB_FAN_PWM<40>
SYS_FAN_PWM<40>
NB_FAN_TACH<40>
SYS_FAN_TACH<40>
H_TEMP_RET_DN<9>
H_TEMP_SRC_DP<9>
VCCP
V_5P0_STBY\G
PLTRST_N<15,28,35> PLTRST_N_LPC <41>
C289 reserved for 01U16V
12
R294
2K8R2F-GP
SIO_+5VTR_IN
SIO_V_1P5_CORE_IN
SIO_+5V_IN
12
R298
1K2R2F-1-GP
V_SM
12
12
COPPER-CLOSE
need fine tune
According to SMSC5127 Anomaly
sheet,need change
the SMSC5127 0x29 register to
0x86,then the prochot will
inverter to active high to prevent
CPU throttle when booting.
5
4
SMB_DATA_MAIN
SMB_CLK_MAIN
L_AD0
L_AD1
L_AD2
L_AD3
PLTRST_N_LPC
SIO_SMI_N
DUMMY-R2
R232
1 2
R255
1 2
DUMMY-R2
SMB_DATA_MAIN
SMB_CLK_MAIN
SMB_DATA_RESUME
SIO_FAN_PWM3
R2750R2J-2-GP
SIO_FAN_PWM2
R2760R2J-2-GP
SIO_FAN_PWM1
R2770R2J-2-GP
SIO_FAN_TACH2
R2800R2J-2-GP
SIO_FAN_TACH1
R2820R2J-2-GP
H_TEMP_RET_DN_MB
H_TEMP_SRC_DP_MB
SIO_VCCP_IN
SIO_SM_IN
SIO_V_1P5_CORE_IN
SIO_+5V_IN
SIO_+5VTR_IN
PLTRST_N_LPC
C289
DUMMY-C2
1 2
SIO_PROCHOT_N
R300 reserved for
100K
4
3
V_3P3_STBY\G
VCC3
SMB_DATA_MAIN <22,25>
SMB_CLK_MAIN <22,25>
U9
14
INDEX#
5
MTR0#
7
DS0#
9
DIR#
10
STEP#
11
WDATA#
12
WGATE#
15
TRK0#
16
WRTPRT#
17
RDATA#
13
HDSEL#
6
DSKCHG#
19
LAD0
20
LAD1
21
LAD2
22
LAD3
23
LFRAME#
24
LDRQ#
25
PCI_RESET#
26
PCI_CLK
27
SER_IRQ
36
GP27/IO_SMI#/P17
18
CLOCKI
90
GP42/IO_PME#
93
GP61/LED2#
94
GP60/LED1#/WDT
104
SDA1/DDCSDA_5V
105
SCLK1/DDCSCL_5V
106
SCLK/DDCSCL_2.5V
107
SDA/DDCSDA_2.5V
108
GP16/PWM3/PROCHOT#
109
GP17/PWM3
110
PWM2
111
PWM1
112
FANTACH3
114
FANTACH2
115
FANTACH1
113
VID5
116
VID4
117
VID3
118
VID2
119
VID1
120
VID0
123
REMOTE2-
124
REMOTE2+
125
REMOTE1-
126
REMOTE1+
127
VCCP_IN
128
+2.5V_IN
1
V1_IN
2
V2_IN
3 92
VTRIP_IN PS_ON#
SCH5127-NW-GP
F_CAP
C288
SC4D7U10V5ZY-3GP
1 2
VCC
VSS VTR
FCAP
8 4
31 29
102
R299 reserved for 10K
R299
DUMMY-R2
H_PROCHOT_BASE_N
1 2
R300
DUMMY-R2
1 2
R302 reserved for 10K
R301 reserved for
130R
R302
1 2
V_3P0_BAT_VREG
32
91
72
122
VTR
VTR
VTR
VBAT
HVTR
GP57/DTR2#/SPEAKER_OUT
GP56/CTS2#/LED2
GP55/RTS2#/VID6
GP54/DSR2#/PWM2
GP53/TXD2/IRTX/VID7
GP52/RXD2/IRRX/SPEAKER_IN
GP51/DCD2#/LED1/WDT
GP50/RI2#/PWM1
IDE_RSTDRV#/GP10
PCIRST_OUT1#/GP11
PCIRST_OUT2#/GP12
PCIRST_OUT3#/GP13
PCIRST_OUT4#/GP14
GP20/SPEAKER_OUT
3VSB_GATE2#/GP41/DRVDEN0
GP15/THERM_TRIP#/V_TRIP#
VSS
VSS
AVSS
HVSS
101
34
121
Delete R295,net
H_PROCHOT_N pull
high with R11
1
(R)
V_FSB_VTT
1
GP43/FPRST#/VRD_DET
3
Q2
MMBT3904-7-F-GP
2
12
R301
3
Q3
MMBT3904-7-F-GP
2
PWRGD_CPU/SPEAKER_IN/GP40/DRVDEN0
VSS VTR
VSS
VSS
4335554474
DUMMY-R2
H_FORCEPH_BASE_N
SLCT
BUSY
ACK#
SLCTIN#
INIT#
ERROR#
ALF#
STROBE#
DCD1#
DSR1#
RXD1
RTS1#/SYSOPT
TXD1
CTS1#
DTR1#
KCLK/GP22
KDAT/GP21
MCLK/GP33
MDAT/GP32
GP36/KBDRST#
GP37/A20M
INTRD_IN#
PWRGD_PS
PWRGD_3V
3VSB_GATE1#
SLP_S5#
SLP_S3#
PB_IN#
PB_OUT#
RSMRST#
H_PROCHOT_N <9>
DUMMY-R2
H_FORCEPH_N
(R)
3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
RI1#
SA-0804-R604 change to Dummy
56
57
PE
58
59
54
53
52
51
50
49
48
47
46
45
60
61
62
64
67
65
68
66
69
70
63
80
79
SIO_GP55
78
SIO_GP54
77
SIO_GP53
76
SIO_GP52
75
73
71
SIO_KCLK
38
SIO_KDAT
37
SIO_MCLK
40
SIO_MDATSMB_CLK_RESUME
39
41
42
28
97
SIO_PLTRST2
96
95
87
30
SIO_INTRD_IN
33
FPRST_N
81
82
83
84
85
86
88
89
SIO_PB_IN
98
SIO_PB_OUT
99
SIO_RSMRST
100
103
NET H_FORCEPH_N
reserved for test
TP123 TPAD28
TP_SIO_IDE_RST
R278 33R2J-2-GP
HDD4_AMBER <40>
R283 1MR3J-L-GP
R285 10KR2J-3-GP
PWRGD_ICH_SIO
PWRGD_3V_SIO
R288 0R2J-2-GP
12
C291
SCD1U16V2KX-3GP
RXD1 <41>
TXD1 <41>
1
1
HDD2_BLUE <40>
HDD2_AMBER <40>
HDD3_BLUE <40>
HDD3_AMBER <40>
SIO_KCLK <41>
SIO_KDAT <41>
SIO_MCLK <41>
SIO_MDAT <41>
1 2
HWM_INT_N
1 2
1 2
SLP_S4_N <28,47,49,50>
SLP_S3_N <28,48,50>
1 2
PSON_L <45>
12
SCD1U16V2KX-3GP
SC10U10V5ZY-1GP
UNMOUNT LIST:
VCC3
PWRGD_ICH_SIO
PWRGD_3V_SIO
VCC3
12
R604
DUMMY-R2
Output 8mA
ICH_RSMRST_N
I/O AddressRST*1
C292
P/U
P/D
0x04E
0x02E
SIO_ADDRESS_STRAP
SA-change net RESET_BUTTON
from SIO GP54 to
ICH_GPIO10,Add SIO GP54 to
TP138
HDD1_BLUE <40>
HDD1_AMBER <40>
TP138TPAD28
R273
10KR2J-3-GP
1 2
HDD4_BLUE <40>
PLTRST_SLOTS_N <40>
ESATA_RST_N <37>
SLP_S5#:ENCORE USE ICH_S4_STATE;S21
AND DEMO BOARD USE ICH_S4_N
1 2
R289 0R2J-2-GP
R290
10KR2J-3-GP
12
12
SCD1U16V2KX-3GP
C300
C293
V_3P3_STBY\G
12
C294
SC10U10V5ZY-1GP
12
C301
SC10U10V5ZY-1GP
12
R601
DUMMY-R2
R602
DUMMY-R2
2
VCC3
R274
10KR2J-3-GP
1 2
PWRGD_PS <45,50>
12
2
R601 reserved for 1K R
R602 reserved for 33R
12
1 2
R605
1
U46
BAT54C-1-GP
(R)
3
VCC3
12
R263
DUMMY-R2
12
R266
470R2J-2-GP
KBRST_N <27>
A20GATE <27>
TP124 TPAD28
1
V_3P0_BAT_VREG
12
SCD1U16V2KX-3GP
2
V_3P3_STBY\G
SW_ON_N <28>
ICH_RSMRST_N <28>
12
C295
C296
SCD1U16V2KX-3GP
1
TP126
1 2
33R2J-2-GP
SA-0731 change R600 pin2 from net
ICH_VRMPWRGD_PU to ICH_THRM_PU_N
HWM_INT_N
12
SCD1U16V2KX-3GP
1
R603
DUMMY-R2
reserved for pull low
12
R606
10KR2J-3-GP
V_3P3_STBY\G
SW_ON_N
12
R30
10KR2J-3-GP
PWR_BUTTON
PLTRST_SLOTS_N
Add D5,R626(reserved for16.7K),C514(0.1U)
for debounce circuit
R600
1 2
DUMMY-R2
VCC3V_3P3_STBY\G
12
C297
C298
SC1U16V3ZY-GP
TP126TPAD28
C510
SC100P50V2JN-3GP
R618
4K7R2J-2-GP
1 2
SA-0804-Add R618 pull high
to V_3P3_STBY\G
V_3P3_STBY\G
R279
10KR2J-3-GP
1 2
K A
C514
DUMMY-C2
1 2
PWRGD_3V <15,28>
12
SA-0804-Add
C510
PLTRST_SLOTS_N <40>
D5
(R)
1N4148WT-7-GP
1 2
0R2J-2-GP
R626
SA-0731 delete R287
ICH_THRM_PU_N <28,31>
V_3P0_BAT_VREG
12
C299
SCD1U16V2KX-3GP
SUPER IO BYPASS CAP
<Variant Name>
Title
SUPER I/O SMSC5127
Size Document Number Rev
S15
C
Date: Sheet
1
PWR_BUTTON
12
C290
SC1U16V3ZY-GP
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
PWR_BUTTON <42>
of
38 50Friday, December 12, 2008
-1
5
http://hobi-elektronika.net/
4
3
2
1
"one CE pin" & "two CE pin" &"four CE pin" flash setup
"one CE pin" Flash memory
100MHz 60ohm
500mA DCR = 25mohm
L19
VCC3
BLM18PG600SN-2GP
1 2
R10 allocate near U4 Pin39
and same signal layer as
U4
R321
1 2
0R2J-2-GP
1
2
3
4
R324
1 2
0R2J-2-GP
12
C302
SC10U10V5KX-2GP
SM321_DP_1
L21
DLW21HN900SQ2LGP
(R)
L304 R306
Unmount
SM321_DM_1
D D
External 5V to 3.3V LDO
C C
B B
A A
Note:
1.Use 2 pcs flash or under:
Open external LDO(U1) and short SB1.
2.Use over 2 pcs flash:
Add the external LDO(U1) and open
SB1.
C313
1 2
SC27P50V3JN-GP
XTAL-12MHZ-12GP
A3.3V
1 2
SC27P50V3JN-GP
R319
200R2J-L1-GP
5
C315
1 2
nLED_1
12
LED1
A K
LED-G-98-GP
USBP8+<26>
USBP8-<26>
Change NOTE-0115
net SM321_RV5 connect to TP
and delete R758 and C682
OSCI
12
X5
R313
1MR2J-1-GP
OSCO
nLED
TPAD28
A3.3V
R314
47KR2F-GP
4
A3.3V
12
C303
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
TP94
SM321_DM_1
SM321_DP_1
R311
1 2
330R2F-GP
OSCI
OSCO
12
nRESET
12
SM321_CLKSEL
SCD1U10V2KX-4GP
C314
A3.3V
SM321_RV5
SM321_RREF
Change NOTE-0116
Delete C14,C19,L2;change
A1.8V power source form
V_FSB_VTT to SMI321 internal
power regulator
A3.3V
C304
1 2
C305
1 2
C306
1 2
C307
1 2
C309
1 2
SC10U10V5KX-2GP
403246
21
47
48
U10
VD33O
VCC5A
37
DM
38
DP
39
RREF
4
XSCI
5
XSCO
3
NC#3
34
EXRST#
26
VSS
2
NC#2
30
TEST
31
NC#31
SM321QX00LF00-CC-GP
33
V33VI
V33VI
VD33I
VD33P
VS33P
GNDA
VS33P
41
44
42
nRESET
change the SMI321 write protect from ICH_GPIO14 to
ICH_GPIO6,because of power plane issue-0811
Change NOTE-0115
Add L65 for net
A1.8V_SMI321
A1.8V
L20
1 2
BLM18PG600SN-2GP
A1.8V_SMI321
9
45
29
43
V18VI
V18VI
VD18O
VDDU/1_8V
P34/F0BUSY
P35/F1BUSY
P36/WPRO#
P37/LED#
VSS
VSS
15
R323
1 2
0R2J-2-GP
3
Close to Chip Pin43
C308 SCD1U10V2KX-4GP
1 2
C310 SC4D7U10V5KX-1GP
1 2
NC
C311 SCD1U10V2KX-4GP
1 2
NC
C312 SCD1U10V2KX-4GP
1 2
F0D0
25
FDD0
F0D1
24
FDD1
F0D2
23
FDD2
F0D3
22
FDD3
F0D4
20
FDD4
F0D5
19
FDD5
F0D6
18
FDD6
F0D7
17
FDD7
F0ALE
14
FALE
F0CLE
7
FCLE
F0RD
16
FRD#
F0WE
10
FWE#
NAND_Flash_nWP
1
FWP#
6
P10/CE0
35
P11/CE1
12
11
8
P13/CE3
36
nLED
13
27
NC#27
28
P12/CE2
Change to 321CC
ICH_GPIO6 <28,31>
setup as Following,
R1 : Short
R2 : Open
R4 : Short
R5 : Open
R6 : Short
R7 : Open
UNMOUNT LIST:
R752,R755,R757,R754,R759,R765,R764
L54
A3.3V
CE0
CE1 RB0
R317 1K5R2J-3-GP
RB0
1 2
RB1
1 2
R318 1K5R2J-3-GP
CE3
CE2
A3.3V
A3.3V
12
R312
10KR2J-3-GP
A3.3V
RB1
RB0
CE1
CE3
12
SAMSUNG K9W**** series or Hynix 2Gbit FLASH.
Setup as Following,
R303
1 2
0R2J-2-GP
R304
DUMMY-R2
R1 : Open
1 2
R305 0R2J-2-GP
1 2
1 2
R308
1 2
A3.3V
12
C316
SCD1U10V2KX-4GP
R322
10KR2J-3-GP
NF_WP#
2
RB1_A
R2 : Short
R4 : Open
R5 : Short
RB0_A
R6 : Open
R307DUMMY-R2
R7 : Short
1 2
0R2J-2-GP
CE3_A
R309DUMMY-R2
nRESET
RB0
RB1_A
RB0
F0RD
CE0
CE1
CE2
CE3
F0CLE
F0ALE
F0WE
ON BOARD FLASH USE 72.27081.A09
BOM NEED CHANGE TO VENDER DEFINE
RB0
U45
1
NC#1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
<Variant Name>
Title
Size Document Number Rev
A3
Date: Sheet
NC#48
NC#2
NC#47
NC#3
NC#46
NC#4
NC#45
NC#5
NC#6
RB#
RE#
CE#
NC#10
NC#11
VCC
VSS
NC#14
NC#15
CLE
ALE
WE#
WP#
NC#20
NC#21
NC#22
NC#23
NC#24
I/O7
I/O6
I/O5
I/O4
NC#40
NC#39
PRE
VCC
VSS
NC#35
NC#34
NC#33
I/O3
I/O2
I/O1
I/O0
NC#28
NC#27
NC#26
NC#25
HY27UF081G2M-GP
FLASH CONTROLLER SM321
S15
SAMSUNG K9MXG08 series
Setup as Following,
R1 : Open
R2 : Open
R306DUMMY-R2
R4 : Open
1 2
RB1_A
R5 : Open
R6 : Open
R7 : Open
R22 :
Short
Interleave mode setup
R3 open : Enable
R3 short :
Disable
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RB0
F0D7
F0D6
F0D5A3.3V
F0D4
F0D3
F0D2
F0D1
F0D0
A3.3V
NF_PRE
R310
1 2
DUMMY-R2
A3.3V
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
39 50Friday, December 12, 2008
1
RB1
12
1 2
R316
DUMMY-R2
R320
0R2J-2-GP
of
-1
5
4
3
2
1
V_3P3_STBY\GVCC3+12V
12
12
C318
SCD1U16V2KX-3GP
12
C319
SCD1U16V2KX-3GP
SMB_CLK_RESUME<28,38>
SMB_DATA_RESUME<28,38>
WAKE_N<28,31,35>
PCIE_ICH_TXP1_SLOT<26>
PCIE_ICH_TXN1_SLOT<26>
PCIE_ICH_TXP2_SLOT<26>
PCIE_ICH_TXN2_SLOT<26>
PCIE_ICH_TXP3_SLOT<26>
PCIE_ICH_TXN3_SLOT<26>
PCIE_ICH_TXP4_SLOT<26>
PCIE_ICH_TXN4_SLOT<26>
D D
12
E470U16VM-1-GP
12
TC2
C317
SCD1U16V2KX-3GP
PCIE SLOT BYPASS CAPS
SW1
4 3
RESET_BUTTON<28>
C C
SW-TACT-70-GP-U
V_3P3_STBY\G
Delete R551(pull high to VCC3)-0812
Delete net SDVO_CTRL_DATA,SDVO_CTRL_CLK,R325,R326
12
R229
1 2
330R2F-GP
R230
1 2
330R2F-GP
C9
DUMMY-C3
BP BOARD
CONNECTOR
CN18
R548
1 2
10KR2F-2-GP
2
4
6
8
10
DVD-CONN10D-3-GP
12
R546
10KR2F-2-GP
FAN_TACH_MB
12
R547
4K7R2F-GP
SYS_FAN_TACH<38>
SYS_FAN_PWM<38>
HDD1_PWR<38>
B B
A A
HDD3_PWR<38>
NB FAN
CONNECTOR
NB_FAN_TACH<38>
5
V_LED
1
3
3904_BASE
5
3904_EMIT
7
9
NB_FAN_PWM<38>
BP_THERM_DA <38>
BP_THERM_DC <38>
VCC+12V
12
R545
+12V
2K2R2J-2-GP
12
C458
SCD1U25V3KX-GP
DVD-CON4-18-GP
4
HDD1_PWR
HDD3_PWR
CN19
4
3
2
1
+12V VCC3+12V
VCC3
VCC
3
CN20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
MLX-CONN64-4R-GP-U
HDD1_BLUE<38>
HDD1_AMBER<38>
HDD2_BLUE<38>
HDD2_AMBER<38>
HDD3_BLUE<38>
HDD3_AMBER<38>
HDD4_BLUE<38>
HDD4_AMBER<38>
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
NP1
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
NP2
PCIE_ICH_RXP1_SLOT
PCIE_ICH_RXN1_SLOT
PCIE_ICH_RXP2_SLOT
PCIE_ICH_RXN2_SLOT
PCIE_ICH_RXP3_SLOT
PCIE_ICH_RXN3_SLOT
PCIE_ICH_RXP4_SLOT
PCIE_ICH_RXN4_SLOT
U26
1
A1
Y1
2
GND
VCC
3 4
A2 Y2
NC7WZ07P6X-1GP
U27
1
A1
Y1
2
GND
VCC
3 4
A2 Y2
NC7WZ07P6X-1GP
U28
1
A1
Y1
2
GND
VCC
3 4
A2 Y2
NC7WZ07P6X-1GP
U29
1
A1
Y1
2
GND
VCC
3 4
A2 Y2
NC7WZ07P6X-1GP
PLTRST_SLOTS_N <38>
VCC
HDD1_BLUE_R
6
5
HDD1_AMBER_R
VCC
HDD2_BLUE_R
6
5
HDD2_AMBER_R
VCC
HDD3_BLUE_R
6
5
HDD3_AMBER_R
VCC
HDD4_BLUE_R
6
5
HDD4_AMBER_R
2
CK_PE_100M_PCIE_SLOT_DP <25>
C446 SCD1U16V2KX-3GP
C447 SCD1U16V2KX-3GP
C448 SCD1U16V2KX-3GP
C449 SCD1U16V2KX-3GP
C450 SCD1U16V2KX-3GP
C451 SCD1U16V2KX-3GP
C452 SCD1U16V2KX-3GP
C453 SCD1U16V2KX-3GP
CK_PE_100M_PCIE_SLOT_DN <25>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
HDD1_BLUE_R
LED_PWR_GND
HDD2_AMBER_R
HDD3_BLUE_R
LED_PWR_GND
HDD4_AMBER_R
HDD1_BLUE_R
HDD1_AMBER_R
HDD2_BLUE_R
HDD2_AMBER_R
HDD3_BLUE_R
HDD3_AMBER_R
HDD4_BLUE_R
HDD4_AMBER_R
<Variant Name>
Title
PCIE & OTHER CONNECTOR
Size Document Number Rev
S15
A3
Date: Sheet
PCIE_ICH_RXP1 <26>
PCIE_ICH_RXN1 <26>
PCIE_ICH_RXP2 <26>
PCIE_ICH_RXN2 <26>
PCIE_ICH_RXP3 <26>
PCIE_ICH_RXN3 <26>
PCIE_ICH_RXP4 <26>
PCIE_ICH_RXN4 <26>
HDD LED
CONNECTOR
CN11
12
34
56
78
910
1112
DVD-CONN12D-5-GP
R556 470R2J-2-GP
1 2
R557 470R2J-2-GP
1 2
R558 470R2J-2-GP
1 2
R559 470R2J-2-GP
1 2
R560 470R2J-2-GP
1 2
R561 470R2J-2-GP
1 2
R562 470R2J-2-GP
1 2
R563 470R2J-2-GP
1 2
1
LED_PWR_GND
HDD1_AMBER_R
HDD2_BLUE_R
LED_PWR_GND
HDD3_AMBER_R
HDD4_BLUE_R
V_LED
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
40 50Friday, December 12, 2008
-1
5
4
VGA_5V_AUXVGA_5V_AUX
3
2
1
12
R629
10KR2F-2-GP
D D
1_KBDAT 1_KBCLK
12
R630
10KR2F-2-GP
-1B Add net 1_KBDAT,1_KBCLK pull high 10K,for reserved
V_SM
FUSE-1D1A6V-4GP-U
VCC
F1
1 2
F2
1 2
VGA_GREEN<15,21>
F3
1 2
SIO_KDAT<38>
SIO_KCLK<38>
VGA_RED<15,21>
VGA_BLUE<15,21>
ROUT
GOUT
BOUT
R327 0R2J-2-GP
KBCLK
R329 0R2J-2-GP
ROUT
R333 0R2J-2-GP
GOUT
R336 0R2J-2-GP
BOUT
R338 0R2J-2-GP
1 2
1 2
1 2
R340 150R2F-1-GP
R342 150R2F-1-GP
R344 150R2F-1-GP
1 2
1 2
1 2
1 2
1 2
VGA_5V
1_KBDATKBDAT
1_KBCLK
VGA_1.8V
1_GOUT
1_BOUT
VGA_5V_AUX
CN12
2
4
6
8
10
12
14
16
18
20
22
24
26
DVD-CONN26D-5
DDC1DATA
DDC1CLK
VGA_5V_AUX
VGA_1.8V
VGA_5V
1
3
5
1_PMCLK
7
1_DDC1DATA
9
1_DDC1CLK
11
1_SOUT11_ROUT
13
1_SIN1
15
17
19
21
23
25
R341 2K2R2F-GP
1 2
R343 2K2R2F-GP
1 2
C320 SCD1U16V2KX-3GP
1 2
C321 SCD1U16V2KX-3GP
1 2
C322 SCD1U16V2KX-3GP
1 2
R328 0R2J-2-GP
R330 0R2J-2-GP
R331 0R2J-2-GP
R332 0R2J-2-GP
R334 0R2J-2-GP
R335 0R2J-2-GP
1_VSYNC
R337 33R2J-2-GP
1_HSYNC
R339 33R2J-2-GP
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
VCC
PMDAT1_PMDAT
PMCLK
DDC1DATA
DDC1CLK
SOUT1
SIN1
VSYNC
HSYNC
SIO_MDAT <38>
SIO_MCLK <38>
MCH_DDC_DATA <15,21>
MCH_DDC_CLK <15,21>
TXD1 <38>
RXD1 <38>
VSYNC <15>
HSYNC <15>
2
3
4
5
6
7
GEN315R158-8-F-A
2
3
4
5
H1
1
8
H3
1
8
4
5
GEN315R158-8-F-A
4
5
H2
2
3
1
8
6
7
H4
2
3
1
8
V_5P0_STBY\G
C C
B B
FUSE-1D1A6V-4GP-U
FUSE-1D1A6V-4GP-U
SA-0730-change R340,R342,R344 to 150 Ohm
6
LPC Debug Port FOR MB DEBUG
R3450R2J-2-GP
PLTRST_N_LPC<38>
Change LPC reset
net from PCIRST1_N
A A
5
to
PLTRST_N_LPC(0130)
1 2
L_FRAME_N<28,38>
FWH_INIT_N<27>
L_AD3<28,38>
L_AD2<28,38>
L_AD1<28,38>
L_AD0<28,38>
TP95TPAD28
ZZ.PAD28.XXX
4
DebugLPC_RST_N
L_FRAME_N
FWH_INIT_N
L_AD3
L_AD2
L_AD1
L_AD0
EXT_FWH_N
1
CN13
2
4
6
8
10
12
14
16
1
3
5
7
9
11
13
X
15
DVD-CONN16D-FP10GP
VCC
3
VCC3
CK_P_33M_LPC <25>
2
7
GEN315R158-8-F-A
<Variant Name>
Title
DEBUG BD CONNECTOR
Size Document Number Rev
S15
B
Date: Sheet
6
7
GEN315R158-8-F-A
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
1
-1
of
41 50Friday, December 12, 2008
5
VCC
ICH_GPIO 32 ICH_GPIO 8
12
ICH_GPIO 33
D D
C326
SCD22U10V2KX-1GP
RAID_LED_CTRL<28>
PWR_BUTTON<38>
BACKUP_STATUS<28>
RAID_LED_CTRL2<28>
change CN22 Pin 13 & Pin 15
trace to 5VDUAL
VCC_USB_FRONTVCC_USB_FRONT VCC3
CN21
2
USB_FRONT2_DN_R
USB_FRONT2_DP_R
C C
B B
DVD-CONN10D-3-GP
USB_FRONT1_DP<26>
RESERVED
A A
USB_FRONT2_DP<26>
1
4
6
8
10
USB_FRONT1_DN<26>
USB_FRONT2_DN<26>
5
USB_FRONT1_DN_R
3
USB_FRONT1_DP_R
5
7
9
4
1
1
4
USB_FRONT1_DP_R
3
L23
DLW21HN181SQ2L-GP
For 1 Port USB
(Front Pannel)
2
USB_FRONT1_DN_R
USB_FRONT2_DN_R
2
L24
DLW21HN181SQ2L-GP
For 1 Port USB
(Front Pannel)
3
USB_FRONT2_DP_R
4
CN22
DVD-CONN16D-S5-GP
2
4
6
8
10
12
14
16
ICH_SATA_LED_N
1
3
5
7
9
11
13
15
4
PWR_LED <28>
BACKUP_BUTTON <28>
SYS_ERROR <28>
SYS_STATUS <28>LED_STATUS<35>
ICH_SATA_LED_N <27>
5VDUAL
12
R227
4K7R2F-GP
ICH_GPIO 25ICH_GPIO 26
ICH_GPIO 24
ICH_GPIO 20
FAN_CTL3<38>
3
V_LED
12
C459
SCD22U10V2KX-1GP
V_LED
FAN_CTL3
3
R349
280KR2F-GP
R351
1 2
82KR2F-1-GP
2
For 2 Port USB
V_5_USB
F4
1 2
FUSE-1D1A6V-4GP-U
12
C327
SC1KP50V2KX-1GP
BLM21PG600SN1-GP
L22
1 2
12
12
C323
R346
10KR2F-2-GP
SC100U6D3V0MX-2GP
R347
15KR2F-GP
R347 change from 560K to 15K on page 36
84
U12A
+
-
LM358DR-N1-GP
+12V
84
+
-
C328
SCD1U25V3KX-GP
1 2
FAN358O FAN358OO
1
U12B
7
LM358DR-N1-GP
2
SC2D2U16V3KX-GP
R350
1 2
2KR2J-1-GP
R353
1 2
2KR2F-3-GP
VCC3
12
FAN358N
12
C330
SCD1U16V2KX-3GP
+12V VCC
3
2
5
6
1
100MHz 60ohm
3A,
DCR=25mohm
VCC_USB_FRONTVCC_USB_FRONT_1
12
C324
C329
<Variant Name>
Title
FRONT IO BD CONNECTOR
Size Document Number Rev
S15
B
Date: Sheet
12
12
C325
SCD1U16V2KX-3GP
SC100U6D3V0MX-2GP
USB_OC_FRONT_12 <26>
1 2
FANFB
V_LED
12
TC21
ST10U10VAM-2-GP
Q1 Change to
84.0340P.A31
Q4
AO3409-GP
R354
1 2
1KR2F-3-GP
VDS = -30V.
Idd = -2.6
DS
A.
G
C333
1 2
SC470P50V2KX-3GP
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
1
V_LED
12
12
C331
C332
SC10U10V5KX-2GP
of
42 50Friday, December 12, 2008
SC10U10V5KX-2GP
-1
5
http://hobi-elektronika.net/
4
3
2
1
V_FSB_VTT
D D
H_BPM5_PREQ_N<9>
H_BPM4_PRDY_N<9>
H_BPM_N<3><9>
H_BPM_N<2><9>
H_BPM_N<1><9>
TP102 TPAD28
TP104 TPAD28
TP106 TPAD28
TP108 TPAD28
XDP_PWRGD
TP110 TPAD28
TP111 TPAD28
TP112 TPAD28
H_BPM_N<0><9>
H_TCK<9>
V_FSB_VTT
UNMOUNT LIST:
C C
V_FSB_VTT
B B
H_BPM_N<0>
H_BPM_N<1>
H_BPM_N<2>
H_BPM_N<3>
H_BPM4_PRDY_N
H_BPM5_PREQ_N
R366 51R2F-2-GP
1 2
R367 51R2F-2-GP
1 2
R369 51R2F-2-GP
1 2
R370 51R2F-2-GP
1 2
R371 51R2F-2-GP
1 2
R372 51R2F-2-GP
1 2
H_BPM5_PREQ_N
H_BPM4_PRDY_N
H_BPM_N<3>
H_BPM_N<2>
H_BPM_N<1>
H_BPM_N<0>
TP_XDP_P27
TP_XDP_P29
TP_XDP_P33
TP_XDP_P35
XDP_PWRGD
XDP_TESTIN_N
TP_XDP_P45
TP_XDP_P47
SMBDAT_XDP
SMBCLK_XDP
TP_XDP_P55
XDP For CPU
CN15
MH1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
MH2
SMC-CONN60A
TP_XDP_P4
TP_XDP_P6
TP_XDP_P10
TP_XDP_P12
TP_XDP_P16
TP_XDP_P18
TP_XDP_P28
TP_XDP_P30
TP_XDP_P34
TP_XDP_P36
TPEV_H_CPURST_XDP_R_N
H_TDO
H_TRST_N
H_TDI
H_TMS
SMBDAT_XDP
SMBCLK_XDP
TPEV_H_CPURST_XDP_R_N
XDP_TESTIN_N
TP96
TP97 TPAD28
TP98
TP99
TP100
TP101
TP103
TP105 TPAD28
TP107
TP109
H_TDO <9>
H_TRST_N <9>
H_TDI <9>
H_TMS <9>
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
CK_H_XDP_DP <25>
CK_H_XDP_DN <25>
V_FSB_VTT
FP_RST_N <9,28,31>
R364 0R2J-2-GP
1 2
R365 0R2J-2-GP
1 2
R368
1 2
R373 62R2J-GP
1 2
1KR2J-1-GP
V_FSB_VTT
SMB_DATA_AMT <38>
SMB_CLK_AMT <38>
H_CPURST_N <8,9,12>
H_TDI
H_TMS
H_TDO
H_TRST_N
H_TCK
R357 51R2F-2-GP
1 2
R358 51R2F-2-GP
1 2
R359 51R2F-2-GP
1 2
R360 1KR2J-1-GP
1 2
R361 DUMMY-R2
1 2
R362 51R2F-2-GP
1 2
12
XDP_PWRGD
H_PWRGD <9,28>
R363
1KR2J-1-GP
<Variant Name>
A A
Title
ITP-XDP
Size Document Number Rev
S15
B
Date: Sheet
5
4
3
2
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
43 50Friday, December 12, 2008
1
-1
5
V_FSB_VTT
C352
12
12
R377
2K2R2J-2-GP
12
R397
DUMMY-R2
2K2R2J-2-GP
DUMMY-R2
CPU_VCC
12
R378
R379
2K2R2J-2-GP
12
12
R399
R398
DUMMY-R2
12
R376
D D
R386 0R2J-2-GP
H_VID6<10>
H_VID5<10>
H_VID4<10>
H_VID3<10>
H_VID2<10>
H_VID1<10>
H_VID0<10>
C C
1 2
R387 0R2J-2-GP
1 2
R388 0R2J-2-GP
1 2
R389 0R2J-2-GP
1 2
R390 0R2J-2-GP
1 2
R393 0R2J-2-GP
1 2
R394 0R2J-2-GP
1 2
2K2R2J-2-GP
12
R396
DUMMY-R2
VCC
12
R412
2D2R2F-GP
12
SCD1U16V2KX-3GP
CLOSE TO PIN 18
B B
VCCP
TC3
TC4
12
4
12
12
R381
R380
2K2R2J-2-GP
2K2R2J-2-GP
12
12
R401
R400
DUMMY-R2
DUMMY-R2
ESR = 16m ohm
RIPPLE CURRENT = 3500mA
TC5
12
12
2K2R2J-2-GP
DUMMY-R2
12
C355
3
Add R617 and connector to
ICH_VRMPWRGD_PU
ICH_VRMPWRGD_PU<28,31>
12
12
R374
R382
DUMMY-R2
12
R402
SCD1U25V2ZY-1GP
V_FSB_VTT
12
R403
0R2J-2-GP
12
12
C10
C11
SCD1U25V2ZY-1GP
12
12
C357
C356
0R2J-2-GP
1 2
R617
VRM_PWRGD<25>
CPU_VCC OFS
1 2
RESERVE FOR 32.4KR
R395 1KR2J-1-GP
1 2
CPU_VCC
connect R406 Pin 1 from VCC to
CPU_VCC
VREG_12V_POWER
12
C358
64K9R2F-1-GP
VSS_SENSE_CPU_SKT
CN16
JWT-CONN4B-GP
12
C359
R383 DUMMY-R2
R406
1 2
RESERVE FOR 60.4KR
13
24
12
C360
VCC3
VRM_PWRGD
12
C338
SC1KP50V2KX-1GP
DUMMY-R2
1KR2J-1-GP
1 2
H_VID7_R
H_VID6_R
H_VID5_R
H_VID4_R
H_VID3_R
H_VID2_R
H_VID1_R
H_VID0_R
12
R408
R375
CPU_VCC
12
C339
SCD01U25V2KX-3GP
200KR2F-L-GP
VSS_SENSE_CPU_SKT<10>
VCC_SENSE_CPU_SKT<10>
U13
ISL6314CRZ-GP
18
VCC
1
PGOOD
5
OFS
32
VID7
25
VID6
26
VID5
27
VID4
28
VID3
29
VID2
30
VID1
31
VID0
17
EN
4
REF
3
FS
2
SS
CONNECT TO
GND THROUGH
8 VIA
12
R409
C347
1 2
DUMMY-C2
20mil trace
20mil trace
LGATE
GND
C348
1 2
DUMMY-C2
R413
1 2
2D2R2F-GP
PVCC_6314
19
PVCC
LGATE
21
RGND
LGATE
BOOT
PHASE
UGATE
ISEN+
ISENO
OCSET
VDIFF
RCOMP
COMP
VSEN
12
201133
BOOT BOOT_R
22
24
UGATE
23
16
15
ISEN-
14
13
VDIFF
10
RCOMP
8
CPUFB
9
FB
COMP
7
APA
6
APA
C342
NC#20
C344
NC_ISL6314
1 2
DUMMY-C2
C349
1 2
DUMMY-C2
Reserved C347,C348,C349 for SC1KP50V2KX-1GP
UGATE2_RUGATE
12
C353
DUMMY-C2
R422
1 2
2D2R5F-2-GP
12
C334
SC2D2U16V3KX-GP
R384
0R2J-2-GP
1 2
R404
4K02R2F-GP
12
SC1000P50V3JN-GP
Change C340 to 1000pF
SC100P50V2JN-3GP
4
2
VREG_12V_POWER
change R422 for
filter
PHASE
ISEN_N
ISENO
OCSET
change R391 to 820R to set current
to 8A
1 2
1 2
C340
VREG_12V_POWER
678
DDD
U48
AO4468-GP
SSS
GD
123
4 5
20mil trace
5
Q6
D
HAT2165H
G
S
123
SCD22U16V2ZY-1GP
C336
1 2
R391 820R2F-GP
1 2
1 2
C341 SC100P50V2JN-3GP
1 2
R407
10KR2F-2-GP
IM_R407_C343
change R407 to 10KR & C343 to 820P
change R407 to 10KR & C343 to 820P
& C341 to 100PF
12
C350
SC4D7U16V6ZY-2GP
PHASE
12
2D2R2F-GP
PHASE_R
12
12
ADD C8 BETWEEN ISEN+
C8
& ISEN- FOR REDUCE
NOISE 2008/07/29
SCD01U16V2KX-3GP
CPUFB
1 2
C343
SC820P50V2KX-1GP
12
C351
SC4D7U16V6ZY-2GP
L25
IND-1UH-25-GP
1 2
RATE CURRENT = 11A
RDC = 9m ohm
R414
C354
SC4700P50V2KX-1GP
VCCP
12
C335
SCD01U25V2KX-3GP
12
C337
SCD01U25V2KX-3GP
VCCP
1
change R385 to 22KR
2008/07/29
R385
1 2
16K9R2F-GP
12
R392
CHANGE R392 from 35.7K to 11K
2008/07/29
11KR2F-L-GP
11K3R2F-2-GP
SC1000P50V3JN-GP
12
R410
1KR2F-3-GP
VDIFF
PHASE
12
R405
change R405 to 11.3k
IM_DUMMY
12
C345
change C345 to
1000p
12
C346
SCD033U16V3KX-GP
IM_R411_C346
12
R411
90D9R3F-GP
SE560U2D5VM-1-GP
SE560U2D5VM-1-GP
SA-0804-TC3,TC4,TC5-SE560U2D5VM-GP EOL change
to SE560U2D5VM-1-GP
A A
5
SC22U6D3V5MX-2GP
SE560U2D5VM-1-GP
4
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
3
LGATE_R2
12
R415
DUMMY-R2
<Variant Name>
Title
POWER VCCP VREG CONTROLLER
Size Document Number Rev
S15
C
Date: Sheet
2
1
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
44 50Friday, December 12, 2008
-1
5
http://hobi-elektronika.net/
4
12
R628
VCC3
3
Add R628
2
1
V_5P0_STBY\G
12
D D
PSON_L<38>
C C
B B
U14
APL1085UC-GP
R416
4K7R2F-GP
12
12
C362
C363
SC470P50V-2-GP
SC1U10V2KX-1GP
SA-0806-Change the U14 power
source from V_SM to VCC3
VCC3
12
C371
SCD1U10V2KX-4GP
3
VIN
2
VOUT
1
ADJ
200R2F-L-GP
R421
1 2
R419
1 2
1KR2F-3-GP
TP113TPAD28
VCC
CN17
13
14
15
16
17
18
19
20
1
21
22
23
24
JWT-CONN24B-S-GP
V_1P5_SFR
1
2
3
4
5
6
7
8
9
10
11
12
1
TP114
TPAD28
V_1P5_SFR V_1P5_CORE
RESERVE FOR 0R
VCCVCC3VCC3-12V
R418
1 2
DUMMY-R6
+12V
V = 1.25 * ( 200/1K)
A A
5
4
SC470P50V-2-GP
12
C368
4K7R2F-GP
12
C361
SC1U10V2KX-1GP
12
C369
SCD1U10V2KX-4GP
PWRGD_PS <38,50>
V_5P0_STBY\G
12
C370
SCD1U10V2KX-4GP
3
V_5P0_STBY\G
12
R417
330R2F-GP
AK
LED2
LED-G-98-GP
BATTERY POWER
VCC VCC3 +12V -12V
SCD1U16V2KX-3GP
12
C366
12
TC6
SE100U25VM-L1-GP
SCD1U16V2KX-3GP
12
C364
12
TC7
SE100U25VM-L1-GP
SCD1U16V2KX-3GP
12
C365
POWER CONNECTOR DECOUPLINGPOWER CONNECTOR
V_3P0_BAT_VREG
D1
3
12
BAT54C-1-GP
BAT1
1 2
3
CR2032-3-GP
C372
SC1U10V2KX-1GP
<Variant Name>
Title
POWER V_1P5_SFR & BATTERY
Size Document Number Rev
S15
B
Date: Sheet
12
R420
1KR2F-3-GP
VREG_VBAT_R
V_3P3_STBY\G
1
2
2
SCD1U16V2KX-3GP
12
C367
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
45 50Friday, December 12, 2008
1
-1
5
http://hobi-elektronika.net/
VCC3
C378
VCC
12
C382
SCD1U50V3KX-GP
1 2
SCD1U50V3KX-GP
VCC3
C388
1 2
SCD1U25V2ZY-1GP
D D
C C
VCC
SCD1U50V3KX-GP
12
C383
5VDUAL
12
C377
SCD1U50V3KX-GP
-12V
12
C384
SCD1U50V3KX-GP
V_3P3_STBY\G
C375
1 2
SCD1U50V3KX-GP
12
C385
SCD1U50V3KX-GP
VCC3
SCD1U50V3KX-GP
12
C386
4
V_3P0_BAT_VREG
12
-12V
12
C376
SC470P50V-2-GP
C381
SC470P50V-2-GP
3
C373
1 2
SCD1U10V2KX-4GP
C509
1 2
SCD1U10V2KX-4GP
VCC3
5VDUAL
5VDUAL
C397
1 2
SC1U16V5KX-3GP
SIO STITCHING CAP
2
VCC
C374
1 2
SCD1U10V2KX-4GP
+12V
C380
1 2
SCD1U10V2KX-4GP
STITCHING CAPS
NET PCLKN,PCLKP,
MCH_DDC_CLK STITCHING CAP
C500
1 2
SCD1U10V2KX-4GP
C501
1 2
SCD1U10V2KX-4GP
Add stitching caps
C515,C516,C517,C518
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
V_1P5_CORE VCC3
SCD1U10V2KX-4GP
STITCHING CAPS
VCC3
VCC3
C502
1 2
SCD1U10V2KX-4GP
C515
C516
C517
C518
1
VCC3
1 2
VCC3
1 2
VCC3
1 2
1 2
VCC3
VCC3
C393
1 2
SCD1U25V2ZY-1GP
VCC3
C399
1 2
B B
SCD1U25V2ZY-1GP
VCC3
C395
1 2
SCD1U25V2ZY-1GP
V_5P0_STBY\G
CLOCK
STITCHING CAPS
C398
1 2
SCD1U25V2ZY-1GP
C493
1 2
SCD1U10V2KX-4GP
C495
1 2
SCD1U10V2KX-4GP
C497
1 2
SCD1U10V2KX-4GP
VCC3
VCC3
VCC3
C494
1 2
SCD1U10V2KX-4GP
C496
1 2
SCD1U10V2KX-4GP
C498
1 2
SCD1U10V2KX-4GP
C499
1 2
SCD1U10V2KX-4GP
VCC3
VCC3
VCC3
VCC3
VCC
C394
1 2
SCD1U50V3KX-GP
C396
1 2
SCD1U50V3KX-GP
PLACE NEAR SOUTH OF
SOUTH BRIDGE
PCIE TRACE STICHING CAP
C503
1 2
SCD1U10V2KX-4GP
C504
1 2
SCD1U10V2KX-4GP
NET
CK_H_XDP_DP,CK_H_XDP_DN
STICHING CAP
A A
VCC3VCC3
C505
1 2
SCD1U10V2KX-4GP
C506
1 2
SCD1U10V2KX-4GP
VCC3
VCC3
NET Vsync Hsync STICHING CAP
V_LED STICHING CAP
C507
1 2
SCD1U10V2KX-4GP
C508
1 2
SCD1U10V2KX-4GP
<Variant Name>
SA-0725-Add C493~C509 for EMI solution
C519
1 2
SCD1U10V2KX-4GP
5
4
3
VCC3
Add C519
2
Title
POWER DECOUPLING & STITCHING
Size Document Number Rev
S15
Custom
Date: Sheet
V_LED
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
46 50Friday, December 12, 2008
1
-1
5
http://hobi-elektronika.net/
4
3
2
1
D D
CHANGE R575 TO 3KR
12
R574
10KR2J-3-GP
12
C466
C C
15KR2F-GP
1 2
VSM_FB
12
R585
1 2
2K4R2F-GP
B B
SCD1U16V2KX-3GP
R580
SCD01U16V2KX-3GP
C469 SC47P50V2JN-3GP
1 2
1 2
R582
3KR2F-GP
C471
DUMMY-C2
V_3P3_STBY\G
R234
12
VSM_DUMMY
C468
3KR2F-GP
2K4R2F-GP
1 2
R584
1 2
DUMMY-R2
12
R575
VSM_VOS
12
R577
VSM_PG
VSM_EN
CHANGE U30 SOURCE
TO 5VDUAL
5VDUAL
12
R573
2D2R2J-GP
6
U30
9
VOS
10
PGOOD
7
COMP/EN
8
FB
ISL6341CRZ-TR-GP
5
SC1U10V2KX-1GP
VCC
GND
11
12
BOOT
UGATE
PHASE
LGATE
GND
C465
5VDUAL
5VDUALV_SMV_SM
D2
BAT54HT1G-GP
R576
K A
2D2R2J-GP
1 2
rDS = 14m ohm
R578
2D2R2J-GP
VSM_BOOT
12
22KR2F-GP
1 2
R583
1
VSM_UG
3
2
VSM_LG
4
VSM_BOOTR
ID = 11 A
VSM_UG_R
VSM_PHASE
ID = 11 A
rDS = 14m ohm
678
U34
DDD
12
C467
AO4468-GP
SSS
GD
123
4 5
AO4468-GP
GD
4 5
678
DDD
SCD1U16V2KX-3GP
R581
U35
2D2R2J-GP
1 2
SSS
12
C470
123
SC1000P50V3JN-GP
12
C463
SC1U10V2KX-1GP
DCR = 10m ohm
Irms = 11 A
L26
1 2
IND-1UH-50-GP-U
12
TC16
E2200U6D3V-GP
12
C379
SC10U6D3V3MX-GP
ADD C379, C387 FOR V_SM
12
SCD1U16V2KX-3GP
12
C387
SC10U6D3V3MX-GP
C464
V_SM
12
TC17
E2200U6D3V-GP
ESR = 0.013 ohm
Ripple current
= 2550 mA
V_SM
1
VSM_EN
3
Q8
MMBT3904-7-F-GP
(R)
2
0814-SA-Q8 OPEN
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
POWER V_SM
Size Document Number Rev
S15
B
Date: Sheet
3
2
Hsichih, Taipei
47 50Friday, December 12, 2008
1
-1
of
R622
0R2J-2-GP
SLP_S4_N<28,38,49,50>
A A
5
4K7R2J-2-GP
VSM_EN_L
3
1
C513
DUMMY-C2
Q10
2
MMBT3904-7-F-GP
4
12
1 2
5
http://hobi-elektronika.net/
4
3
2
1
V_1P5_COREV_1P5_CORE VCC
C477
1 2
R597
1 2
DUMMY-R2
V_3P3_STBY\G
4K7R2J-2-GP
SLP_S3_N_V1P5
1 2
3
1
2
12
R588
2K1R2F-GP
1P5_VOS
12
R590
2K4R2F-GP
1P5_PG
1P5_EN 1P5_PHASE
12
R599
MMBT3904-7-F-GP
1P5_EN_L
3
Q30
1
2
R620
DUMMY-R2
12
R435
15KR2F-GP
Q33
MMBT3904-7-F-GP
12
R437
(R)
7K15R2F-L-GP
12
R587
10KR2J-3-GP
R593
1 2
C478 SC47P50V2JN-3GP
R595
C480
1 2
DUMMY-C2
R619
0R2J-2-GP
C511
DUMMY-C2
1 2
12
C475
SCD1U16V2KX-3GP
SCD01U50V2KX-1GP
1 2
2K1R2F-GP
1 2
1P5_DUMMY
12
D D
12KR2J-L-GP
1P5_FB
12
R598
2K4R2F-GP
C C
SLP_S3_N<28,38,50>
LATCHED_BACKFEED_CUT<49,50>
B B
R621
0R2J-2-GP
LATCHED_BACKFEED_CUT<49,50>
12
Add control signal
U31
9
VOS
10
PGOOD
7
COMP/EN
8
FB
ISL6341CRZ-TR-GP
1
C512
DUMMY-C2
1 2
SC1U10V2KX-1GP
12
R586
2D2R2J-GP
1P5_VCC
6
SC1U10V2KX-1GP
VCC
UGATE
PHASE
LGATE
GND
GND
5
11
1P5_EN
3
Q29
MMBT3904-7-F-GP
2
12
BOOT
(R)
C474
1
3
2
4
1P5_UG
K A
1P5_BOOT
1P5_LG
24KR2F-GP
D3
BAT54HT1G-GP
R589
2D2R2J-GP
1 2
R591
2D2R2J-GP
1 2
12
R596
0814-SA-Q29 OPEN for Intel recommend
+12V
U16A
LM358-2-GP
84
3
12
C410
+
1
2
-
-12V
R439
1 2
1KR2F-3-GP
G
ID = 18 A
rDS = 7.5m
ohm
1P5_UG_R
ID = 18 A
rDS = 7.5m
ohm
V_SM V_FSB_VTTV_3P3_STBY\G
DS
0814-SA-Q33 OPEN for Intel recommend
VCC3VCC
1P5_BOOTR
678
U32
DDD
12
C476
SCD1U16V2KX-3GP
R594
1 2
2D2R2J-GP
12
C479
SC1000P50V3JN-GP
DCR = 3m ohm
Irms = 18 A
L27
1 2
IND-1UH-64-GP
V_ICH_CORE
SSS
GD
AO4430-1-GP
123
4 5
678
DDD
U33
SSS
GD
AO4430-1-GP
123
4 5
SA-0804-IND-1UH-64-GP change to
IND-1UH-41-GP-U
Because Layout Keepout issue,change back to
IND-1UH-64-GP,but BOM use IND-1UH-41-GP-U
12
C409
SC10U6D3V3MX-GP
Q9
AO3400-1-GP-U
V_ICH_CORE
12
12
TC10
C411
SC10U10V5KX-2GP
E470U16VM-1-GP
12
12
SC1U10V2KX-1GP
C472
TC18
E2200U6D3V-GP
12
C389
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
V_1P5_CORE
R434
1 2
DUMMY-R5
R436
1 2
DUMMY-R5
R438
1 2
DUMMY-R5
R440
1 2
DUMMY-R5
R441
1 2
DUMMY-R5
12
C473
SCD1U16V2KX-3GP
V_1P5_CORE
12
C390
12
TC19
ST680U4VDM-1-GP
ESR = 0.035 ohm
Ripple current
= 3000 mA
12
TC20
ST680U4VDM-1-GP
U17
3
VIN
2
VOUT
1
ADJ
APL1085UC-GP
V_3P3_STBY\G
V_5P0_STBY\G
3P3_STBY\G_ADJ
12
SCD1U16V2KX-3GP
C412
12
R442
120R2F-GP
12
R443
200R2F-L-GP
V_3P3_STBY\G
12
TC11
E470U16VM-1-GP
V_ICH_CORE (FOR 1.05 ICH CORE)
A A
<Variant Name>
Title
POWER 1P5 1P05 3P3_STB
Size Document Number Rev
S15
C
Date: Sheet
5
4
3
2
1
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
of
48 50Friday, December 12, 2008
-1
5
4
3
2
1
+12V
12
PCH_CTRL
NCH_CTRL
R448
3K74R2F-GP
5
6
123 4
8K2R2F-1-GP
V_5P0_STBY\G
VREG_5VDUAL_NCH
U36
MBT3904DW1T1-GP
12
R454
V_2P5_MCH
D D
V_3P3_STBY\G
12
R451
4K75R2F-1-GP
12
R452
15KR2F-GP
V_2P5_MCH_CNTL
12
C421
SC1U10V2KX-1GP
U20A
LM358-2-GP
+12V
84
3
+
2
-
-12V
V_2P5_MCH_CNTL_FET
1
1 2
1KR2F-3-GP
R453
VCC3
12
12
C420
C419
DS
G
SC4D7U10V3KX-GP
Q12
AO3400-1-GP-U
12
C422
SC10U10V5KX-2GP
SCD01U25V2KX-3GP
SCD1U10V2KX-4GP
12
C423
V_2P5_MCH
12
C424
SCD1U10V2KX-4GP
12
C425
SCD1U10V2KX-4GP
LATCHED_BACKFEED_CUT<48,50>
GLUE_BACKFEED_CUT_N<50>
R449
1 2
0R2J-2-GP
R455
1 2
DUMMY-R2
R450
1 2
4K7R2F-GP
VREG_5VDUAL_CTRL
R456
1 2
4K7R2F-GP
VREG_5VDUAL_PCH
VREG_5VDUAL_PCH
VREG_5VDUAL_NCH
V_5P0_STBY\G
123
45
SSS
GD
U18
P2003EVG-GP
DDD
678
678
DDD
GD
4 5
U21
SSS
123
5VDUAL
FDS6298-GP
VCC
5VDUAL VR
C C
V_SM
12
R457
1KR2F-3-GP
12
12
R459
C427
1KR2F-3-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C430
12
12
TC14
C431
ST470U6D3VDM-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C432
V_SM_VTT
12
C433
SC10U10V5KX-2GP
U20B
5
6
+12V
84
+
-
-12V
LM358-2-GP
PLACE CLOSE TO PIN 8
12
C426
SC1U16V5KX-3GP
V_1P2_MCH_CNTL_FET
7
12
C434
SC1U16V5KX-3GP
PLACE CLOSE TO PIN 4
R461
1 2
1KR2J-1-GP
V_1P5_CORE
DS
G
Q13
AO3400-1-GP-U
12
C435
SCD1U16V2KX-3GP
SC4D7U10V3KX-GP
1.1V
V_FSB_VTT
V_FSB_VTT
12
12
C436
C437
E1000U10VM-L3-GP
SC4D7U10V3KX-GP
TP135
TPAD28
1
V_SM_VTT
U22
5
NC#5
1
8
NC#8
7
NC#7
6
VCNTL
9
GND
RT9199PSP-GP-U
VIN
REFEN
VOUT
GND
REFEN_VSM_VTT
V_SM
1
3
4
2
change from VCC to
V_5P0_STBY\G
TP136
TP137
TPAD28
V_5P0_STBY\G
12
TC15
TPAD28
1
12
C429
SCD1U16V2KX-3GP
V_3P3_STBY\G
12
R458
24K3R2F-1-GP
V_1P2_MCH_CNTL
12
R460
12
C428
12K1R2F-L1-GP
SC1U10V2KX-1GP
PLACE CAP CLOSE TO OP
B B
V_2P5_MCH
V_5_USB5VDUAL
V_1P5_CORE
Delete V_5_USB control circuit and
connect to 5VDUAL directly
A A
5
4
3
1
2
D4
BAT54C-1-GP
3
Add D4 for Intel Recommend
<Variant Name>
Title
POWER VTT 5VDUAL 2P5_MCH
Size Document Number Rev
S15
Custom
Date: Sheet
2
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
49 50Friday, December 12, 2008
of
1
-1
5
4
3
2
1
PLACE REF5V
CIRCUITRY
NEAR ICH
VCC VCC3
D D
SCD1U50V3KX-GP
V_3P3_STBY\G
C C
PWRGD_PS<38,45>
V_3P3_STBY\G
12
C438
1 2
10KR2F-2-GP
12
R474
10R2F-L-GP
R476
PWRGD_PS_XSTR_INVERT
SC1U10V2KX-1GP
R479
1 2
10KR2J-3-GP
R482
1 2
4K7R2F-GP
3
Q16
1
MMBT3904-7-F-GP
2
12
C440
1234
5
6
U11
MBT3904DW1T1-GP
PWRGD_PS_BUF
REF5V_SUS
V_3P3_STBY\G
V_5P0_STBY\G
3
Q15
REMOVEREMOVE
12
12
C439
SCD1U50V3KX-GP
R475
10R2F-L-GP
change C439 & R475 power source from VCC to V_5P0_STBY\G
1
MMBT3904-7-F-GP
2
V_REF5V_SUSV_REF5V
VCC3
R492,R495,
C444change to
Dummy
PWRGD_PS_BUF
V_5P0_STBY\G
SLP_S4_N<28,38,47,49>
R492
1 2
DUMMY-R2
R503
1 2
10KR2F-2-GP
340KR2F-1-GP
R497
1 2
20KR2F-L-GP
R508
1 2
R495
DUMMY-R2
12
158KR2F-GP
R509
12
5
12
LATCHED_BACKFEED_CUT
3
Q17
1
MMBT3904-7-F-GP
12
2
C444
DUMMY-C3
1234
U43
MBT3904DW1T1-GP
6
LATCHED_BACKFEED_CUT <48,49>
C445
SC10U10V5KX-2GP
PS ON LOGIC
B B
R502
DUMMY-R2
V_3P3_STBY\G
PWRGD_PS_BUF
A A
SLP_S3_N<28,38,48>
1 2
DUMMY-R2
RESERVE FOR 2.2K
V_5P0_STBY\G
5
1 2
RESERVE FOR 4.7K
R504
GLUE_BACKFEED_CUT_N <49>
R507
1 2
DUMMY-R2
RESERVE FOR 4.7K
R510
1 2
DUMMY-R2
RESERVE FOR 4.7K
R501
DUMMY-R2
RESERVE FOR 100K
1 2
1234
U44
MBT3904DW1T1-GP
5
6
DIS_BF_CUT_N
DIS_BF_CUT_N
4
3
V_3P3_STBY\G
R513
1 2
2K2R2J-2-GP
2
LATCHED_BACKFEED_CUT
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Title
GLUE LOGIC 1 OF 3
Size Document Number Rev
S15
B
Date: Sheet
Hsichih, Taipei
50 50Friday, December 12, 2008
1
-1
of
Loading...