Wistron Queen 15 Schematic

5

4

3

2

1

Discrete/UMA Schematics Document

D D

Sandy Bridge

Intel PCH

2011-01-04 REV : A00

C C

DY :None Installed UMA:UMA ONLY installed DN15: ONLY FOR DN15 installed. DQ15:ONLY FOR DQ15 installed. PSL: KBC795 PSL circuit for 10mW solution installed. 10mW: External circuit for 10mW solution installed.

B B

MUXLESS:MUXLESS solution installed. OPTIMUS:OPTIMUS solution installed.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Cover Page

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

1 108

1

A00

5

##OnMainBoard

1.N12P-GE-A1-GP(64Mx16b*8)

D D

WKS P/N:72.51G63.H0U HYNIX WKS P/N:72.41164.I0U SAMSUNG

VRAM

1GB

88,89,90,91

DDR3 800MHz

Robson-XT& Seymour-XT& Whistler-LP& N12P-GE

ATI : Co-layout HDMI coming from UMA(default) & dGPU by reserving Resistor(0ohm) for optional selection.

NVidia : Co-layout HDMI coming from dGPU(Default) &

C C

UMA by reserving Resistor(0ohm) for optional selection.

HDMI

LCD

CRT

Left Side: USB x 1

DCIN

B B

51

49

CRT Board

Bluetooth

CAMERA

VOSTRO

Finger Print

15~25W

83.84,85,86,87

Discreet/UMA Co-lay

HDMI

LVDS(Sigal Channel)

RGB CRT

82

63

54

64

4

3

Block Diagram (Discrete/UMA co-lay)

4

PCIe x 16

(Discrete only)

USB2.0 x 5

AZALIA

FDIx4x2 (UMA only)

PCH Cougar Point

Intel CPU

Sandy Bridge

4,5,6,7,8,9,10,11,12,13

DMIx4

Intel

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6) PCIE ports (8)

LPC I/F ACPI 1.1

17,18,19,20,21,22,23,24,25,26

Project code : 91.4IE01.001 PCB P/N : 10260-1 Revision : A00

DDRIII 1066/1333 Channel A

DDRIII 1066/1333 Channel B

PCIE x 4

USB 2.0 x 3

I/O Board

SATAx1 / USB2.0x1

USB 2.0 x 1¡BPCIE X 1

USB 2.0 x 1

PCIE x 1

PCIE x 1,USB x 1

Connector

82

ESATA/USB/Powershare Combo

2

DDRIII 1066/1333

PCIE x 1 USB2.0 x 1

PCIE x 1

NEC USB3.0

UPD720200FA

VOSTRO

Express Card

(On daughter board)

Slot 0

14

Slot 1

15

RTL8111E/8105E

57

INPUTS

1D05V_VTT

Mini-Card

802.11a/b/g

10/100/ 1000 NIC

Realtek

Mini-Card

WWAN

75

SYSTEM LDO

APL5916

OUTPUTS

0D85V_S0

RJ45 CONN

USB3.0 X2 CONN

SIM

HP1 MIC IN

1

48

CPU DC/DC

ISL95831HRTZ

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51218

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51123RGER

INPUTS

DCBATOUT 5V_S5

SYSTEM DC/DC

TPS51216RUKR

INPUTS

DCBATOUT

SYSTEM DC/DC

ISL95831HRTZ

INPUTS

DCBATOUT

RT8208B

INPUTS

DCBATOUT

TI CHARGER

BQ24745

INPUTS

+DC_IN_S5

26

SYSTEM DC/DC

TPS51311

INPUTS

3D3V_S5

SYSTEM DC/DC

G9731

INPUTS OUTPUTS

26

1D5V_S3 1V_VGA_S0

OUTPUTS

VCC_CORE

OUTPUTS

1D05V_VTT

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

OUTPUTS

VCC_GFXCORE

VGA

OUTPUTS

VGA_CORE

OUTPUTS

42~43

45

41

46

44

92

40

DCBATOUT+PBATT

47

1D8V_S0

93

Switches

Internal Digital MIC

A A

2CH SPEAKER

5

58

Azalia CODEC

IDT 92HD87

SPI

Flash ROM

4MB

29

LPC Bus

60

KBC

NUVOTON

NPCE795P

Touch PAD

4

69

Int. KB

69 25

SATA x 2

LPC debug port

D/A

A/D

27

Thermal

P2800

3

CardReader

71

Realtek RTS5138

HDD

ODD

32

56

SD/MMC+/MS/ MS Pro/xD

74

Fan Control

P2793

28

55

2

Title

Size Document Number Rev

A3

Date: Sheet

Block Diagram

QUEEN 15

INPUTS OUTPUTS

1D5V_S3 5V_S5

1D5V_S0 5V_S0 3D3V_S03D3V_S5

PCB LAYER

L1:Top L2:VCC L3:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

2 108Tuesday, January 04, 2011

L4:Signal L5:GND L6:Bottom

of

A00

A

PCH Strapping

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. Leave as "No Connect".

GNT3#/GPIO55

4 4

GNT2#/GPIO53 GNT1#/GPIO51

SPI_MOSI

NV_ALE

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-k£[

No Reboot Mode with TCO Disabled:

- 10-k£[ weak pull-up resistor.

GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Enable Danbury:

Disable Danbury:

Huron River Schematic Checklist Rev.0_7

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

B

C

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

PCI-Express Static Lane Reversal

CFG[4]

CFG[6:5]

CFG[7]

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

D

Huron River Schematic Checklist Rev.0_7

Default Value

1

0

11

1

E

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.

HAD_DOCK_EN# /GPIO[33]

3 3

High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

HDA_SYNC

GPIO15

GPIO8

2 2

GPIO27

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

Voltage Rails

ACTIVE IN

S0

CPU Core Rail Graphics Core Rail

S3

AC Brick Mode only

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

USB Table

Pair

PCIE Routing

0

1

LANE1 LANE2 LANE3 LANE4

1 1

LANE5 LANE6 LANE7 LANE8 Express Card

Card Reader Mini Card1(WLAN) Mini Card2(WWAN) Onboard LAN

USB3.0

Intel GBE LAN

Dock

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD1 HDD2

N/A N/A

ODD

ESATA

2

3

4

5

6

7

8

9

10

11

12

13

Device Touch Panel / 3G SIM USB Ext. port 1 (HS)

Fingerprint

BLUETOOTH Mini Card2 (WWAN) CARD READER X X

USB Ext. port 4 / E-SATA /USB CHARGER

USB Ext. port 2 USB Ext. port 3 Mini Card1 (WLAN) CAMERA

Express Card

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery CHARGER

EC SMBus 2 PCH eDP

PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI

HURON RIVER ORB

Address Hex Bus Ref Des

BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA

SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Table of Content

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

3 108

of

A00

5

4

3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_VTT

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3:0]19

DMI_TXP[3:0]19

DMI_RXN[3:0]19

DMI_RXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19 FDI_LSYNC019

FDI_LSYNC119

0719 Modify: un-stuff R403 base on Intel James feedback list.

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

R403

1 2

10KR2J-3-GP

DY

Stuff to disable internal graphics function for power saving.

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP eDP_HPD

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interfa ce is disabled, connect it to CPU VCCIO via a 10-k£[ pull-Up resistor on the motherboard.

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

J18 J17

H20

J19

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

SANDY

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

SKT-BGA989C470395-1H180

DMI

Intel(R) FDI

eDP

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

PEG_RXN[0..15]

PEG_RXP[0..15]

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

C401 SCD22U10V2KX-1GP

1 2

MUXLESS

C402 SCD22U10V2KX-1GP

1 2

MUXLESS

C403 SCD22U10V2KX-1GP

1 2

MUXLESS

C404 SCD22U10V2KX-1GP

1 2

MUXLESS

C405 SCD22U10V2KX-1GP

1 2

MUXLESS

C406 SCD22U10V2KX-1GP

1 2

MUXLESS

C407 SCD22U10V2KX-1GP

1 2

MUXLESS

C408 SCD22U10V2KX-1GP

1 2

MUXLESS

C409 SCD22U10V2KX-1GP

1 2

MUXLESS

C410 SCD22U10V2KX-1GP

1 2

MUXLESS

C411 SCD22U10V2KX-1GP

1 2

MUXLESS

C412 SCD22U10V2KX-1GP

1 2

MUXLESS

C413 SCD22U10V2KX-1GP

1 2

MUXLESS

C414 SCD22U10V2KX-1GP

1 2

MUXLESS

C415 SCD22U10V2KX-1GP

1 2

MUXLESS

C416 SCD22U10V2KX-1GP

1 2

MUXLESS

C417 SCD22U10V2KX-1GP

1 2

MUXLESS

C418 SCD22U10V2KX-1GP

1 2

MUXLESS

C419 SCD22U10V2KX-1GP

1 2

MUXLESS

C420 SCD22U10V2KX-1GP

1 2

MUXLESS

C421 SCD22U10V2KX-1GP

1 2

MUXLESS

C422 SCD22U10V2KX-1GP

1 2

MUXLESS

C423 SCD22U10V2KX-1GP

1 2

MUXLESS

C424 SCD22U10V2KX-1GP

1 2

MUXLESS

C425 SCD22U10V2KX-1GP

1 2

MUXLESS

C426 SCD22U10V2KX-1GP

1 2

MUXLESS

C427 SCD22U10V2KX-1GP

1 2

MUXLESS

C428 SCD22U10V2KX-1GP

1 2

MUXLESS

C429 SCD22U10V2KX-1GP

1 2

MUXLESS

C430 SCD22U10V2KX-1GP

1 2

MUXLESS

C431 SCD22U10V2KX-1GP

1 2

MUXLESS

C432 SCD22U10V2KX-1GP

1 2

MUXLESS

A A

1D05V_VTT

PEG_RXN[0..15] 83

PEG_RXP[0..15] 83

PEG Static Lane Reversal

PEG_TXN[0..15]

PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

PEG_TXP[0..15]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PCIE/DMI/FDI)

QUEEN 15

PEG_TXN[0..15] 83

PEG_TXP[0..15] 83

of

4 108

A00

SSID = CPU

5

1D05V_VTT

D D

0625 Modify: Add C502 47p 0402 on H_PROCHOT#.

R501

1 2

62R2J-GP

H_PROCHOT#

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

20100622 V1.2

CRB : 47pf CEKLT:43pf

Connect EC to PROCHOT# through inverting OD buffer.

C C

R510

PLT_RST#18,27,71,75,82,83

0617 Modify: Joseph Removed U501 Buffer reset to CPU circuit.

R510

B B

0719 Modify: Add buffer for PLT_RST# based on Intel review.

Buffered reset to CPU

PLT_RST#18,27,71,75,82,83

H_SNB_IVB#18

H_PROCHOT#27,40,42

H_THERMTRIP#22,36

H_PM_SYNC19

A00 1229 EMI

H_CPUPWRGD22,36

PM_DRAM_PWRGD19,37

VDDPWRGOOD37

1 2

1K5R2F-2-GP

1

TP501TPAD14-GP TP501TPAD14-GP

1

TP502TPAD14-GP TP502TPAD14-GP

H_PECI22,27

R513

1 2

56R2J-4-GP

EC505

R503

1 2

12

R509

R509 750R2F-GP

750R2F-GP

A00 1230 EMI

0623 Modify: Reserved C501 220pF 0402 on BUF_CPU_RST#.

U501

1

IN B

VCC

2

IN A

DY

GND3OUT Y

74VHC1G09DFT2G-GP

73.01G09.AAH

12

DY

R504

1 2

0R0402-PAD

10KR2J-3-GP

R505

1 2

0R2J-2-GP

DY

12

DY

EC506

MS04A03T2V2-GP-U

1D05V_VTT

5

4

MS04A03T2V2-GP-U

12

DY

12

DY

4

SKTOCC#_R

H_CATERR#

H_PROCHOT#_R

H_CPUPWRGD_R

VDDPWRGOOD

BUF_CPU_RST#

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

R518

R518 75R2J-1-GP

75R2J-1-GP

CPU1B

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

3D3V_S0

12

C503

DY

SCD1U10V2KX-5GP

1 2

DY

R517 43R2J-GP

SANDY

MISCTHERMALPWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

SKT-BGA989C470395-1H180

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

BUF_CPU_RST#BUFO_CPU_RST#

12

R515

DY

0R2J-2-GP

3

2 OF 9

BCLK

BCLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

MISC

PRDY# PREQ#

TRST#

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

A28 A27

CLK_DP_P_R

A16

CLK_DP_N_R

A15

R8

SM_RCOMP_0

AK1

SM_RCOMP_1

A5

SM_RCOMP_2

A4

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCLK

AR26

TCK TMS

TDI

TDO

AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

R512

1 2

1KR2J-1-GP

R514

1 2

1KR2J-1-GP

R502

1 2

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

1 1

0630 Modify: Removed XDP1101 connector related circuit by layout limitation.

12

EC502

SC1KP50V2KX-1GP

CLK_EXP_P 20 CLK_EXP_N 20

1D05V_VTT

TP511 TPAD14-GPTP511 TPAD14-GP TP512 TPAD14-GPTP512 TPAD14-GP

1

TP503 TPAD14-GPTP503 TPAD14-GP

1

TP504 TPAD14-GPTP504 TPAD14-GP

1

TP505 TPAD14-GPTP505 TPAD14-GP

1

TP506 TPAD14-GPTP506 TPAD14-GP

1

TP507 TPAD14-GPTP507 TPAD14-GP

1

TP508 TPAD14-GPTP508 TPAD14-GP

1

TP509 TPAD14-GPTP509 TPAD14-GP

1

TP510 TPAD14-GPTP510 TPAD14-GP

XDP_TRST#

XDP_DBRESET#

12

EC504

0617 Modify: Joseph change RN501 to R512,R514 1K 0402 Resistor.

SM_DRAMRST# 37

SC1KP50V2KX-1GP

2

XDP_DBRESET#19

A00 1229 EMI

1 2

8 7 6

1

R516

R516 10KR2J-3-GP

10KR2J-3-GP

1D05V_VTT

3D3V_S0

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

0721 Modify: SWAP RN501 pin1,2,3 base on swap report.

RN501

XDP_TDO XDP_TMS XDP_TDI XDP_TCLK

XDP_TRST#

XDP_DBRESET#

RN501

1 2 3 4 5

SRN51J-1-GP

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

0707 Modify: Change R516 10K from 1K

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

CPU (THERMAL/CLOCK/PM )

QUEEN 15

Tuesday, January 04, 2011

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

5 108

of

A00

5

4

3

2

1

SSID = CPU

4 OF 9

3 OF 9

CPU1C

SANDY

M_A_DQ[63:0]15 M_B_DQ[63:0]14

D D

C C

B B

M_A_DQ[63:0]

M_A_BS015 M_A_BS115 M_A_BS215

M_A_CAS#15 M_A_RAS#15 M_A_WE#15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5

AK6 AK5 AH5 AH6

AK8 AK9

AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

V6

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CLK2

SA_CLK#2

SA_CKE2

SA_CLK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 15 M_A_DIM0_CLK_DDR#0 15 M_A_DIM0_CKE0 15

M_A_DIM0_CLK_DDR1 15 M_A_DIM0_CLK_DDR#1 15 M_A_DIM0_CKE1 15

M_A_DIM0_CS#0 15 M_A_DIM0_CS#1 15

M_A_DIM0_ODT0 15 M_A_DIM0_ODT1 15

M_A_DQS#[7:0] 15

M_A_DQS[7:0] 15

M_A_A[15:0] 15

M_B_DQ[63:0]

M_B_BS014 M_B_BS114 M_B_BS214

M_B_CAS#14 M_B_RAS#14 M_B_WE#14

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9 AA7

AA10

AB8 AB9

CPU1D

SANDY

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CLK2

SB_CLK#2

SB_CKE2

SB_CLK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_CLK_DDR0 14 M_B_DIM0_CLK_DDR#0 14 M_B_DIM0_CKE0 14

M_B_DIM0_CLK_DDR1 14 M_B_DIM0_CLK_DDR#1 14 M_B_DIM0_CKE1 14

M_B_DIM0_CS#0 14 M_B_DIM0_CS#1 14

M_B_DIM0_ODT0 14 M_B_DIM0_ODT1 14

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[15:0] 14

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

A A

5

3rd = 62.10055.321

A00 0103 add 3rd foxcon CPU1 at XBuild batch run A00 0103 add 3rd foxcon CPU1 at XBuild batch run

4

3

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

CPU (DDR)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

6 108

1

A00

5

4

3

2

1

SSID = CPU

0630 Modify: Reserved TP715 on CFG0.

CFG0

1

TP715TPAD14-GP TP715TPAD14-GP

D D

0707 Modify: Removed CFG1,CFG3,CFG8~17 TP.

0617 Modify: Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

M3 - Processor Generated SO-DIMM VREF_DQ

DY

R708 0R2J-2-GP

1 2

DY

M_VREF_DQ_DIMM0

C C

B B

M_VREF_DQ_DIMM1

R707 0R2J-2-GP

M_VREF_CA_DIMM0 M_VREF_CA_DIMM1

0719 Modify: Reserved EC701 0.1uF near R711(BOTTOM) for EMC NEO suggestion.

R707 0R2J-2-GP R706 0R2J-2-GP

R706 0R2J-2-GP

1D05V_VTT

12

DY

EC701

SCD1U50V3KX-GP

DY

R709 0R2J-2-GP

1 2

DY

1 2

DY

0629 Modify: Reserved R710 0ohm to GND to follow EV board schematic.

R710 0R2J-2-GP

1KR2F-3-GP

1 2

DY

M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C

R711

20 mils

CFG2 CFG4

CFG5 CFG6 CFG7

B4:VREF_DQ CHA

D1:VREF_DQ CHB

12

R712

R712 1KR2F-3-GP

1KR2F-3-GP

H_VCCP_SEL

CPU1E

AK28

CFG0

AK29

CFG1

AL26

CFG2

AL27

CFG3

AK26

CFG4

AL29

CFG5

AL30

CFG6

AM31

CFG7

AM32

CFG8

AM30

CFG9

AM28

CFG10

AM26

CFG11

AN28

CFG12

AN31

CFG13

AN26

CFG14

AM27

CFG15

AK31

CFG16

AN29

CFG17

AJ31

RSVD#AJ31

AH31

RSVD#AH31

AJ33

RSVD#AJ33

AH33

RSVD#AH33

AJ26

RSVD#AJ26

B4

RSVD#B4

D1

RSVD#D1

F25

RSVD#F25

F24

RSVD#F24

F23

RSVD#F23

D24

RSVD#D24

G25

RSVD#G25

G24

RSVD#G24

E23

RSVD#E23

D23

RSVD#D23

C30

RSVD#C30

A31

RSVD#A31

B30

RSVD#B30

B29

RSVD#B29

D30

RSVD#D30

B31

RSVD#B31

A30

RSVD#A30

C29

RSVD#C29

J20

RSVD#J20

B18

RSVD#B18

A19

RSVD#A19

J15

RSVD#J15

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

SANDY

RESERVED

SKT-BGA989C470395-1H180

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

5 OF 9

RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16

RSVD#G16

RSVD#AR35

RSVD#AT34 RSVD#AT33

RSVD#AP35

RSVD#AR34

RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35

RSVD#AJ32

RSVD#AK32

RSVD#AH27

RSVD#AN35 RSVD#AM35

RSVD#AT2 RSVD#AT1 RSVD#AR1

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

0702 Modify

TP713

AN35

TP714

AM35

AT2 AT1 AR1

CFG5 CFG6

1 1

CFG2

CFG4

DY

CFG7

TP713 TPAD14-GPTP713 TPAD14-GP TP714 TPAD14-GPTP714 TPAD14-GP

12

R702

R702 1KR2J-1-GP

1KR2J-1-GP

MUXLESS

12

DY

12

R701

R704

DY

1KR2J-1-GP

12

R705

R705 1KR2J-1-GP

1KR2J-1-GP

DY

0630 Modify: Removed CLK_XDP_ITP_P&N and reserved TP713,TP714.

PEG Static Lane Reversal

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

Display Port Presence Strap

R703

R703 3K3R2F-2-GP

3K3R2F-2-GP

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG DEFER TRAINING

CFG7

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

CPU (RESERVED)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

7 108

1

A00

5

SSID = CPU

D D

1115 X02 Modify: Reserved C802~C804,C806,C807 10uF 0603

VCC_CORE

C C

0819 De-cap

B B

A A

PROCESSOR CORE POWER

53A

12

C802

C801

QC

SC10U6D3V3MX-GP

0713 Modify: Removed C802,C811 10uf 0603 cap base on layout limitation.

12

C820

C819

12

C819

DY

SC10U6D3V3MX-GP

0713 Modify: Removed C818 10uf 0603 cap base on layout limitation.

12

C821

C816

SC10U6D3V5KX-1GP

0721 Modify: Removed C836.

C837

SC22U6D3V5MX-L2GP

5

DY

0726 Modify: un-stuff C837.

12

C803

QC

SC10U6D3V3MX-GP

12

QC

0721 Modify: Removed C822,C823,C824

SC10U6D3V5KX-1GP

12

C835

SC10U6D3V5KX-1GP

VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity

for power team fine tune Vcore quality.

X02 1115

12

C806

QC

SC10U6D3V3MX-GP

C833

SC10U6D3V5KX-1GP

12

C807

SC10U6D3V3MX-GP

0726 Modify: un-stuff C826.

12

C825

SC10U6D3V5KX-1GP

12

C832

SC10U6D3V5KX-1GP

C804

QC

SC10U6D3V3MX-GP

C817

SC10U6D3V3MX-GP

C834

SC10U6D3V5KX-1GP

12

C826

12

SC22U6D3V5MX-L2GP

C831

SC22U6D3V5MX-2GP

4

12

C827

SC22U6D3V5MX-2GP

0819 De-cap

4

VCC_CORE

CPU1F

AG35

VCC

AG34

VCC

AG33

VCC

AG32

VCC

AG31

VCC

AG30

VCC

AG29

VCC

AG28

VCC

AG27

VCC

AG26

VCC

AF35

VCC

AF34

VCC

AF33

VCC

AF32

VCC

AF31

VCC

AF30

VCC

AF29

VCC

AF28

VCC

AF27

VCC

AF26

VCC

AD35

VCC

AD34

VCC

AD33

VCC

AD32

VCC

AD31

VCC

AD30

VCC

AD29

VCC

AD28

VCC

AD27

VCC

AD26

VCC

AC35

VCC

AC34

VCC

AC33

VCC

AC32

VCC

AC31

VCC

AC30

VCC

AC29

VCC

AC28

VCC

AC27

VCC

AC26

VCC

AA35

VCC

AA34

VCC

AA33

VCC

AA32

VCC

AA31

VCC

AA30

VCC

AA29

VCC

AA28

VCC

AA27

VCC

AA26

VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

SANDY

62.10055.421

2nd = 62.10040.771

POWER

SANDY

CORE SUPPLY

3rd = 62.10055.321

3

6 OF 9

AH13

VCCIO

AH10

VCCIO

AG10

VCCIO

AC10

VCCIO

Y10

VCCIO

U10

VCCIO

P10

VCCIO

L10

VCCIO

J14

VCCIO

J13

VCCIO

J12

VCCIO

J11

VCCIO

H14

VCCIO

H12

VCCIO

H11

VCCIO

G14

VCCIO

G13

VCCIO

G12

VCCIO

F14

VCCIO

F13

VCCIO

F12

VCCIO

F11

VCCIO

E14

VCCIO

E12

VCCIO

E11

VCCIO

D14

VCCIO

D13

VCCIO

D12

VCCIO

D11

VCCIO

C14

VCCIO

PEG AND DDR

VCC_SENSE

VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

SENSE LINES SVID

3

C13

VCCIO

C12

VCCIO

C11

VCCIO

B14

VCCIO

B12

VCCIO

A14

VCCIO

A13

VCCIO

A12

VCCIO

A11

VCCIO

J23

VCCIO

AJ29

VIDALERT#

AJ30

VIDSCLK

AJ28

VIDSOUT

AJ35 AJ34

B10 A10

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

2

VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

PROCESSOR VCCIO: 8.5A

12

C805

QC

SC10U6D3V3MX-GP

0713 Modify: Removed C810,C806,C807 10uf 0603 cap base on layout limitation.

No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.

0617 Modify: Joseph Removed C812, C813,C814

For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU

12

DY

12

C809

C808

SC10U6D3V5KX-1GP

SC10U6D3V3MX-GP

12

C830

C842

SC10U6D3V5KX-1GP

H_CPU_SVIDDAT

C842

SC10U6D3V5KX-1GP

C829

SC10U6D3V5KX-1GP

20100610 V1.0

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R803 43R2J-GPR803 43R2J-GP

1 2

VCCIO_SENSE 45 VSSIO_SENSE 45

VCC_CORE

12

2

VR_SVID_ALERT# 42

H_CPU_SVIDCLK 42

H_CPU_SVIDDAT 42

R801

R801 100R2F-L1-GP-U

100R2F-L1-GP-U

R802

R802 100R2F-L1-GP-U

100R2F-L1-GP-U

12

C839

C838

SC10U6D3V5KX-1GP

1D05V_VTT

12

C844

C843

SC10U6D3V5KX-1GP

R804 130R2F-1-GPR804 130R2F- 1-GP

1 2

0705 Modify: Removed R805,R806, already PH closed PWM side.

VCCSENSE 42 VSSSENSE 42

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Tuesday, January 04, 2011

Date: Sheet

1

1D05V_VTT

12

C841

C840

SC10U6D3V5KX-1GP

C845

SC10U6D3V5KX-1GP

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_CORE)

QUEEN 15

1

of

8 108

A00

5

VAXG Output Decoupling Recommendation:

SSID = CPU

VCC_GFXCORE

D D

0713 Modify: Removed C907 10uf 0603 cap. 0726 Modify: stuff C908 10uF.

C C

2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

0721 Modify: Removed C903

12

C901

C902

SC10U6D3V5KX-1GP

0624 Modify: Removed C918,C919 10uF 0603 for VCC_GFXCORE.

12

C908

SC4D7U6D3V3KX-GP

0818 De-cap

Removed DIS_ONLY Disable Resistor. R904,R905,R901,R903

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating)

B B

if the VR is stuffed

1D8V_S0

0617 Modify: Joseph Removed TC 902, TC903 330uF cap.

PROCESSOR VCCPLL: 1.2A

12

C923

SC10U6D3V5KX-1GP

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

4

0726 Modify: un-stuff C906.

PROCESSOR VAXG: 33A

12

C904

SC10U6D3V5KX-1GP

DY

12

C922

SC1U10V2KX-1GP

C905

DY

SC10U6D3V5KX-1GP

12

C920

DY

SC10U6D3V3MX-GP

12

C924

SC1U10V2KX-1GP

12

C906

12

C921

AT24 AT23 AT21 AT20 AT18

AT17 AR24 AR23 AR21 AR20

SC10U6D3V5KX-1GP

AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24

SC10U6D3V3MX-GP

AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

B6 A6 A2

CPU1G

VAXG VAXG

SANDY

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

VCCPLL VCCPLL VCCPLL

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

3

POWER

SENSE

7 OF 9

VAXG_SENSE

VSSAXG_SENSE

LINES

AK35 AK34

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.

+V_SM_VREF_CNT should have 10 mil trace width

AL1

SM_VREF

VREFMISC

AF7

VDDQ

AF4

VDDQ

AF1

VDDQ

AC7

VDDQ

AC4

VDDQ

AC1

VDDQ

Y7

VDDQ

Y4

VDDQ

Y1

VDDQ

U7

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

1.8V RAIL

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCSA_SENSE

FC_C22

VCCSA_VID1

U4 U1 P7 P4 P1

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

+V_SM_VREF_CNT

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

12

C909

DY

PROCESSOR VCCSA: 6A

12

VCCUSA_SENSE

H_FC_C22 VCCSA_SEL

4

1

2 3

2

VCC_AXG_SENSE 42 VSS_AXG_SENSE 42

+V_SM_VREF_CNT 37

PROCESSOR VDDQ: 10A

12

C910

DY

SC10U6D3V3MX-GP

0D85V_S0

12

C915

C916

SC10U6D3V5KX-1GP

0624 Modify: Removed R902 10ohm closed CPU side. 0713 Modify: Add R908 100ohm PH to 0D85V_S0. 0714 Modify: Removed R908 PH.

H_FC_C22 48 VCCSA_SEL 48

RN901

RN901 SRN1KJ-7-GP

SRN1KJ-7-GP

0714 Modify: RN901 change to 1K PL from 10K base on Intel PDDG updated.

12

C911

SC10U6D3V3MX-GP

12

C917

VCCSA Output Decoupling Recommendation:

SC10U6D3V5KX-1GP

1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

VCCUSA_SENSE 48

VCC_GFXCORE

12

R906

R906 100R2F-L1-GP-U

100R2F-L1-GP-U

VCC_AXG_SENSE VSS_AXG_SENSE

12

R907

R907 100R2F-L1-GP-U

100R2F-L1-GP-U

20100609 V1.0

0719 Modify: Add C907,C918,C919,C925 0402 0.1 uF stitching capacitors between 1D5V_S3 & 1D5V_S0 based on Intel's review

1D5V_S0

12

TC901

C913

C912

SC10U6D3V5KX-1GP

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

12

DY

EC902

SCD1U50V3KX-GP

TC901

C914

SC10U6D3V5KX-1GP

79.33719.20L

2nd = 77.C3371.13L

0617 Modify: Joseph Removed TC902,TC903 330uF cap. 0719 Modify: Reserved EC902 0.1uF near C917 for EMC NEO suggestion.

DCBATOUT

12

1122 X02 Modify: stuff EC901 0.1uF from EMC Neo suggestion.

12

DY

C907

ST330U2VDM-4-GP

EC901

SCD1U50V3KX-GP

EC901

SCD1U50V3KX-GP

12

DY

C918

SCD1U10V2KX-5GP

1

12

DY

C919

C925

SCD1U10V2KX-5GP

1D5V_S3

SCD1U10V2KX-5GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

CPU (VCC_GFXCORE)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

9 108

1

A00

5

4

3

2

1

SSID = CPU

9 OF 9

8 OF 9

CPU1H

AT35

VSS

AT32

VSS

AT29

VSS

AT27

VSS

AT25

VSS

AT22

VSS

D D

C C

B B

AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26

K35 K32 K29 K26

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29

CPU1I

T35

VSS

T34

VSS

T33

VSS

T32

VSS

T31

VSS

T30

VSS

T29

VSS

T28

VSS

T27

VSS

T26

VSS

P9

VSS

P8

VSS

P6

VSS

P5

VSS

P3

VSS

P2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L33

VSS

L30

VSS

L27

VSS

L9

VSS

L8

VSS

L6

VSS

L5

VSS

L4

VSS

L3

VSS

L2

VSS

L1

VSS VSS VSS VSS VSS

J34

VSS

J31

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H9

VSS

H8

VSS

H7

VSS

H6

VSS

H5

VSS

H4

VSS

H3

VSS

H2

VSS

H1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

9 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 63.10055.321

A A

5

A00 0103 add 3rd foxcon CPU1 at XBuild batch run A00 0103 add 3rd foxcon CPU1 at XBuild batch run

4

3

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

CPU (VSS)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

10 108

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

XDP

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

11 108

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

12 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

13 108Tuesday, January 04, 2011

A00

5

SSID = MEMORY

0617 Modify:

DDR_VREF_S3

A00

D D

DDR_VREF_S3

A00

C C

0707 Modify: Change R1404,R1405 to 0ohm 0402 from short pad.

0D75V_S0

B B

A A

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

12

R1405

R1405 0R0402-PAD-2-GP

0R0402-PAD-2-GP

M_VREF_CA_DIMM1

12

C1423

DY

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1,

SCD1U10V2KX-5GP

M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

12

R1404

R1404 0R0402-PAD-2-GP

0R0402-PAD-2-GP

12

C1411

DY

SCD1U10V2KX-5GP

12

C1419

SC1U6D3V2KX-GP

12

C1425

SC2D2U10V3KX-1GP

M_VREF_DQ_DIMM1

12

C1412

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1420

DY

SC1U6D3V2KX-GP

5

C1424

SCD1U10V2KX-5GP

C1413

SCD1U10V2KX-5GP

C1421

SC1U6D3V2KX-GP

12

C1422

DY

M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1

DDR3_DRAMRST#15,37

M_B_DQ[63:0]6

SC1U6D3V2KX-GP

M_B_DIM0_ODT06 M_B_DIM0_ODT16

DY

M_B_BS26 M_B_BS06

M_B_BS16

12

M_B_A[15:0] 6

C1418

SC10U6D3V5KX-1GP

M_B_DQS#[7:0] 6 M_B_DQS[7:0] 6

0D75V_S0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

4

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78 79

109 108

15 17

16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68

70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10

27

45

62 135 152 169 186

12

29

47

64 137 154 171 188

116 120

126

30

203 204

H =5.2mm

4

0624 Modify: SWAP DM1 and DM2 location.

DM2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

5

DQ0

7

DQ1 DQ2 DQ3

4

DQ4

6

DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA

1

VREF_DQ RESET#

VTT1 VTT2

DDR3-204P-48-GP

62.10017.P61

2nd = 62.10017.N41

3rd = 62.10017.P41

4th = 62.10024.E21

NP1 NP2

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

SA0_DIM1 SA1_DIM1

3

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6

M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6

M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6

M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6

PCH_SMBDATA 15,20,79,82 PCH_SMBCLK 15,20,79,82

TS#_DIMM0_1 15

1D5V_S3

PART NUMBER

62.10017.P61

62.10017.N41(2nd)

62.10017.P41(3rd) 5.2mm REVERSED

62.10024.E21(4th) 5.2mm REVERSED

1110 X02 Modify: DM2 1st change to 62.10017.P61; 2nd change to 62.10017.N41 on ST stage from ME updated connector list.

3

12

C1402

C1401

DY

SCD1U10V2KX-5GP

1D5V_S3

SC2D2U10V3KX-1GP

Layout Note: Place these Caps near SO-DIMMA.

Height TYPE

5.2mm

5.2mm REVERSED

2

0825

SA1_DIM1 SA0_DIM1

3D3V_S0

SODIMM A DECOUPLING

0617 Modify: Joseph du mmy TC1401 defa ult un-stuff.

12

DY

12

0818 De-cap

C1403

SC10U6D3V5KX-1GP

C1415

SC1U6D3V2KX-GP

12

0818 De-cap

12

DY

ST330U2VDM-4-GP

12

TC1401

12

C1414

SCD1U10V2KX-5GP

REVERSED

2

3D3V_S0

DY

C1404

SC22U6D3V5MX-2GP

C1416

SC1U6D3V2KX-GP

12

R1402

R1402 10KR2J-3-GP

10KR2J-3-GP

12

R1401

R1401 10KR2J-3-GP

10KR2J-3-GP

12

C1405

12

1

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

Thermal EVENT

TS#_DIMM0_1

12

C1406

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

C1417

SC1U6D3V2KX-GP

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

R1403

1 2

12

C1407

C1408

DY

SC10U6D3V5KX-1GP

Tuesday, Janua r y 04, 2011

3D3V_S0

10KR2J-3-GP

12

DY

SC10U10V5ZY-1GP

DDR3-SODIMM2

QUEEN 15

C1410

C1409

DY

SC10U6D3V5KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chi h,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chi h, Taipei Hsien 221, Taiwa n, R. O . C.

Taipei Hsien 221, Taiwa n, R. O . C.

1

14 108

A00

of

5

SSID = MEMORY

M_A_A[15:0] 6

D D

M_A_DQ[63:0]6

12

C1521

SC1U6D3V2KX-GP

M_A_DIM0_ODT06 M_A_DIM0_ODT16

M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0

DDR3_DRAMRST#14,37

M_A_BS26 M_A_BS06

M_A_BS16

M_A_DQS#[7:0] 6 M_A_DQS[7:0] 6

0D75V_S0

0707 Modify: Change R1503,R1504 to 0ohm 0402 from short pad.

DDR_VREF_S3

12

A00

12

C C

DDR_VREF_S3

12

A00

12

B B

A A

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1

R1504

from net to power.

0R0402-PAD-2-GP

M_VREF_CA_DIMM0

12

C1524

C1522

C1523

DY

SCD1U10V2KX-5GP

R1503

0R0402-PAD-2-GP

12

C1515

DY

SCD1U10V2KX-5GP

0D75V_S0

12

DY

C1522

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

M_VREF_DQ_DIMM0

12

C1517

C1516

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1518

SC1U6D3V2KX-GP

12

C1519

C1520

DY

SC1U6D3V2KX-GP

5

4

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

H =9.2mm

4

0624 Modify: SWAP DM1 and DM2 location.

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-42-GP

NP1 NP2

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

62.10017.Q41

2nd = 62.10017.N11

3rd = 62.10017.N61

4th = 62.10024.D91

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

SA0_DIM0 SA1_DIM0

1D5V_S3

3

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6

M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6

M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6

M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6

PCH_SMBDATA 14,20,79,82 PCH_SMBCLK 14,20,79,82

TS#_DIMM0_1 14

12

DY

C1501

C1502

SCD1U10V2KX-5GP

1D5V_S3

Layout Note: Place these Caps near SO-DIMMB.

PART NUMBER

SODIMM B DECOUPLING

12

DY

12

0818 De-cap

Height TYPE

62.10017.Q41 9.2mm REVERSED

62.10017.N11(2nd)

62.10017.N61(3rd)

9.2mm REVERSED

62.10024.D91(4th) 9.2mm REVERSED

1110 X02 Modify: DM1 1st change to 62.10017.Q41; 2nd change to 62.10017.N11 on ST stage from ME updated connector list.

3

SC2D2U10V3KX-1GP

C1503

SC10U10V5ZY-1GP

C1511

DY

SC1U6D3V2KX-GP

12

DY

3D3V_S0

C1504

SC10U10V5ZY-1GP

C1512

SCD1U10V2KX-5GP

SA1_DIM0 SA0_DIM0

12

2

C1505

C1513

2

1

20101220 R1501 R1502 for change to parallel resistor

4

RN1501

RN1501 SRN10KJ-5-GP

SRN10KJ-5-GP

A00

1

2 3

12

C1506

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C1514

SCD01U50V2KX-1GP

12

DY

0818 De-cap

SCD01U50V2KX-1GP

C1507

12

C1508

DY

SC10U6D3V5KX-1GP

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from the Processor than SO-DIMMA

12

C1509

C1510

DY

SC10U10V5ZY-1GP

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

C1510

DY

SC10U6D3V5KX-1GP

DDR3-SODIMM1

QUEEN 15

Tuesday, Janua r y 04, 2011

QUEEN 15

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chi h,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chi h, Taipei Hsien 221, Taiwa n, R. O . C.

Taipei Hsien 221, Taiwa n, R. O . C.

of

15 108

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

16 108Tuesday, January 04, 2011

A00

5

D D

3D3V_S0

RN1701

1 2 3

SRN2K2J-1-GP

RN1702

2 3 1

SRN100KJ-6-GP

0923 SWAP

4

L_CTRL_DATA L_CTRL_CLK

L_BKLT_EN LVDS_VDD_EN

L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

Place near PCH

C C

Impedance:90 ohm

Close to PCH side

CRT_RED CRT_BLUE CRT_GREEN

B B

678

4 5

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

123

0923 SWAP

CRT_BLUE82 CRT_GREEN82 CRT_RED82

4

L_BKLT_EN27

LVDS_VDD_EN49

L_BKLT_CTRL49

LVDS_DDC_CLK_R49 LVDS_DDC_DATA_R49

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

LVDSA_CLK#49 LVDSA_CLK49

LVDSA_DATA0#49 LVDSA_DATA1#49 LVDSA_DATA2#49

LVDSA_DATA049 LVDSA_DATA149 LVDSA_DATA249

0617 Modify: Joseph Removed LVDSB related net for single LVDS channel b ase on Dell updated s pec.

0917 X01 Modify: Add R1703~R1705 on RGB signal and reserved EC1701~EC1703 0.1u from EMC Neo suggestion.

CRT_DDC_CLK82 CRT_DDC_DATA82

CRT_HSYNC82 CRT_VSYNC82

TP1701TPAD14-GP TP1701TPAD14-GP

4

RN1704

A00

0R4P2R-PAD

A00

1 2

R1703 0R0402-PAD-2-GPR1703 0R0402-PAD-2-GP

1 2

R1704 0R0402-PAD-2-GPR1704 0R0402-PAD-2-GP

1 2

R1705 0R0402-PAD-2-GPR1705 0R0402-PAD-2-GP

1KR2D-1-GP

RN

R1702

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

LVDS_VREFH

1

LVDS_VREFL

23

0712 Modify: SWAP RN1704

CRT_BLUE_N48 CRT_GREEN_P49 CRT_RED_T49

DAC_IREF_R

12

3

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

LVDS

CRT

2

4 OF 10

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

0804 Remove HDMI from PCH.

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN

SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

1

Notes: 1K 0.5% 0402.

CHIP RES 1K D 1/16W 0402

DY

EC1701

SCD1U50V3KX-GP

EC1701

SCD1U50V3KX-GP

12

DY

EC1702

SCD1U50V3KX-GP

EC1702

SCD1U50V3KX-GP

12

DY

CRT_BLUE CRT_GREEN

CRT_RED

EC1703

SCD1U50V3KX-GP

EC1703

SCD1U50V3KX-GP

12

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

PCH (LVDS/CRT/DDI)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

17 108

1

A00

5

SSID = PCH

0709 Modify: Removed INT_PIRQH# on RN1801 pin1.

D D

3D3V_S0

INT_PIRQB# INT_PIRQF#

R1801 4K7R2J-2-GP

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC 0 1 Reserved

B B

0617 Modify: Joseph Remove PLT_RST AND gate logic IC U1801/C1802.

A A

0629 Modify: Reseved R1816 100K 0402 on PLT_RST#.

PLT_RST#5,27,71,75,82,83

20100625 V1.2

RN1801

1 2 3 4 5 6

SRN8K2J-2-GP-U

12

DY

override/Top-Block Swap Override enabled High = Default

R1802

1 2

DY

1KR2J-1-GP

R1803

1 2

DY

1KR2J-1-GP

BOOT BIOS Strap

11

1 2

12

R1816

DY

100KR2J-1-GP

5

10

INT_PIRQD#

9

INT_PIRQE#

8

INT_PIRQC#INT_PIRQA#

7

INT_PIRQG#

PCI_GNT3#

BBS_BIT1 BBS_BIT0

Reserved 01

SPI(Default)

R1807

0R0402-PAD-2-GP

12

C1801

C1801 SC220P50V2KX-3GP

SC220P50V2KX-3GP

A00

3D3V_S0

BBS_BIT0 21

0709 Modify: Add R1817 0ohm and connect to KB_LED_BL_DET. (5V Tolerance High Active)

CLK_PCI_LPC71 CLK_PCI_KBC27

PCI_PLTRST#

0908 X01 Modify: Add R1818 10K PL on FFS_INT2_R(GPIO14)

DGPU_HOLD_RST#83

DGPU_PWR_EN#93

4

DGPU_HOLD_RST# DGPU_PWR_EN#

TP1806TPAD14-GP TP1806TPAD14-GP

HDD_FALL_INT179

SATA_ODD_DA#56

USB30_SMI#82

KB_LED_BL_DET69

EC1802

1 2

DY

SC4D7P50V2CN-1GP

R1818 10KR2J-3-GPR1818 10KR2J-3-GP

1 2

4

RN1803

1 2 3

SRN10KJ-5-GP

3D3V_S0

R1814

R1814 8K2R2J-3-GP

8K2R2J-3-GP

1 2

1

TP1807TPAD14-GP TP1807TPAD14-GP

DGPU_PWM_SELECT#

1

R1804 22R2J-2-GPR1804 22R2J-2-GP R1805 22R2J-2-GPR1805 22R2J-2-GP R1806 22R2J-2-GPR1806 22R2J-2-GP

12

EC1801

DGPU_PWR_EN#

1 2 1 2 1 2

EC1803

1 2

DY

SC10P50V2JN-4GP

SC4D7P50V2CN-1GP

TP1801TPAD14-GP TP1801TPAD14-GP

R1812 0R0402-PADR1812 0R0402-PAD

1 2

R1813 0R0402-PADR1813 0R0402-PAD

1 2

R1815 0R0402-PADR1815 0R0402-PAD

1 2

R1817 0R0402-PADR1817 0R0402-PAD

1 2

TP1802TPAD14-GP TP1802TPAD14-GP

KBC CLK EMI

FFS_INT2_R

3

PCH1E

Cougar

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

H3

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

3D3V_S5

BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

G38

G42 G40

K40 K38 H38

C46 C44 E40

D47 E42 F46

C42 D44

K10

H49 H43

K42 H40

C6

J48

4

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

DGPU_SELECT#

BBS_BIT1 PCI_GNT3#

1

PCI_PME#

1

PCI_PLTRST#

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

0628 Modify: Add EC1803 4.7pF 0402 on CLK_PCI_LPC base on EMC NEO suggestion. 0707 Modify: Change R1815,R1812,R1813 to 0ohm 0402 from short pad. 0719 Modify: Reserved TP on CLKOUT_PCI3,4 from vender feedback.

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME# PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGAR-GP-U2-NF

USB_OC#2_3

3

RSVD

PCI

NVRAM

USBP10N

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

RN1802

SRN8K2J-2-GP-U

USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USB

1 2 3 4 5 6

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD RSVD RSVD

RSVD RSVD

RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

10

USB_OC#12_13

9

USB_OC#8_9USB_OC#6_7

8

USB_OC#10_11USB_OC#0_1

7

USB_OC#4_5

0719 Modify: DF_TVS (NV_CLE) connect PROC_SELECT# (H_SNB_IVB#) with R1808 2.2K¡Ó5% pull up resistor to PCH VCCPNAND rail and a R1809 1K¡Ó5% series resistor base on Intel feedback.

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1

NV_RCOMP

AV10 AT8 AY5

BA2 AT12

USB Ext. port 1 (HS)

BF3

External debug port use on Huron river platform

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC#0_1

A14

USB_OC#2_3

K20

USB_OC#4_5

B17

USB_OC#6_7

C16

USB_OC#8_9

L16

USB_OC#10_11

A16

USB_OC#12_13

D14 C14

2

TP1803 TPAD14-GPTP1803 TPAD14-GP

1

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

FFS_INT2_R 79

USB_PN0 49 USB_PP0 49 USB_PN1 82 USB_PP1 82 USB_PN2 64 USB_PP2 64 USB_PN3 63 USB_PP3 63 USB_PN4 82 USB_PP4 82 USB_PN5 32 USB_PP5 32

USB_PN8 57 USB_PP8 57

USB_PN11 82 USB_PP11 82 USB_PN12 49 USB_PP12 49 USB_PN13 75 USB_PP13 75

USB_OC#0_1 61

USB_OC#8_9 61CLK_PCI_FB20

NV_CLE

1 2

DMI & FDI Termination Voltage

NV_CLE

Danbury Technology: Disabled when Low. Enable when High.

USB Table

Pair

Touch Panel / 3G SIM

0

USB Ext. port 1 (HS)

1

Fingerprint

2

BLUETOOTH

3

Mini Card2 (WWAN)

4

CARD READER

5

X

6

X

7

USB Ext. port 4 / E-SATA /USB CHARGE

8

USB Ext. port 2

9

USB Ext. port 3

10

Mini Card1 (WLAN)

11

CAMERA

12

Express Card

13

1120 X02 Modify: Reserved USB_OC#0_1 connect from PCH GPIO59.

0908

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

Wistron Corporation

3D3V_S5

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

PCH (PCI/USB/NVRAM)

QUEEN 15

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

1D8V_S0

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

R1809

1KR2J-1-GP

H_SNB_IVB# 5

Set to Vss when LOW

Set to Vcc when HIGH

1D8V_S0

DY

NV_ALE

Device

of

18 108

1

12

R1810

R1810 1KR2J-1-GP

1KR2J-1-GP

A00

5

4

3

2

1

SSID = PCH

Signal Routing Guideline:

D D

DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP R1902 750R2F-GPR1902 750R2F-GP

20100628 V1.3

SYS_PWROK

R1926

XDP_DBRESET#5

S0_PWR_GOOD27,36

PM_PWRBTN#27

DY

R1926

PWROK

R1904

0707 Modify: stuff R1925 and un-stuff R1905.

3D3V_S0

SYS_PWROK36

R1924 0R0402-PADR1924 0R0402-PAD

RUNPWROK45,46,47,93

3D3V_S5

5

1 2

0907 X01 SWAP RN1901

RN1901

8 7 6

SRN10KJ-6-GP

1 2

R1909 100KR2J-1-GPR1909 100KR2J-1-GP

R1922 10KR2J-3-GP

R1922 10KR2J-3-GP R1920 10KR2J-3-GP

R1920 10KR2J-3-GP

DY

DY DY

DY

R1908

10KR2J-3-GP

1 2

10KR2J-3-GP

C C

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

B B

A A

1 2

100KR2J-1-GP

PM_DRAM_PWRGD5,37

SUS_PWR_ACK27

AC_PRESENT27,86

DMI_RXN[3:0]4

DMI_RXP[3:0]4

DMI_TXN[3:0]4

DMI_TXP[3:0]4

DMI_RXN04 DMI_RXN14 DMI_RXN24 DMI_RXN34

DMI_RXP04 DMI_RXP14 DMI_RXP24 DMI_RXP34

DMI_TXN04 DMI_TXN14 DMI_TXN24 DMI_TXN34

DMI_TXP04 DMI_TXP14 DMI_TXP24 DMI_TXP34

1 2

1 2 1 2

DY

10KR2J-3-GP

PWROK

R1907

1 2

0R2J-2-GP

DY

BATLOW# PM_RI# PCH_WAKE#

SUS_PWR_ACK

DMI_COMP_R RBIAS_CPY

R1905

R1923

1 2

0R2J-2-GP

DY

R1906 0R0402-PADR1906 0R0402-PAD

1 2

MEPWROK

PM_RSMRST#

BATLOW#

PM_RI#

1 2 1 2

0628 Modify: Change R1904 to 100K 0402 from 10K and default stuff. 0629 Modify: R1926 connect to SYS_PWROK. 0707 Modify: Change R1903 change to 0ohm 0402 from short pad.

R1903 0R0402-PADR1903 0R0402-PAD

R1925 0R0402-PADR1925 0R0402-PAD

1 2 3 45

BC24

BE20 BG18 BG20

BE24 BC20

BJ18

BJ20

AW24 AW20

BB18

AV18

AY24

AY20

AY18 AU18

BJ24 BG25 BH21

SUSACK#SUS_PWR_ACK

SYS_RESET#

PCIE_WAKE# CRB : 1K

C12

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

CEKLT: 10K

AC_PRESENT

12 12

12

PM_PWRBTN# PM_SLP_LAN#

PM_RSMRST#

0920 X01 Modify: move PCH_WAKE# to RN1901 pin4 Add R1909 PH on AC_PRESENT.

0719 Modify: Change R1908 to 10K ohm based on Intel review:

8.2K to 10K pull-down is recommended.

4

PCH1C

DMI0RXN

Cougar

DMI1RXN

Point

DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP DMI_IRCOMP DMI2RBIAS

SUSACK#

K3

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPIO72

RI#

COUGAR-GP-U2-NF

3 OF 10

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

DMI

System Power Management

FDI_RXP6

FDI

FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_LAN#/GPIO29

0621 Modify: Joseph removed Q1901/R1909/R1916 3V_5V_POK and PM_R SMRST # related control circuit.

FDI_RXP7

FDI_INT

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DSWODVREN

PCH_DPWROK

PM_SUS_STAT#

SUS_CLK

PM_SLP_S5#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

3

FDI_TXN[7:0] 4 FDI_TXP[7:0] 4

FDI_TXN0 4 FDI_TXN1 4 FDI_TXN2 4 FDI_TXN3 4 FDI_TXN4 4 FDI_TXN5 4 FDI_TXN6 4 FDI_TXN7 4

FDI_TXP0 4 FDI_TXP1 4 FDI_TXP2 4 FDI_TXP3 4 FDI_TXP4 4 FDI_TXP5 4 FDI_TXP6 4 FDI_TXP7 4

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

DY

1

PM_RSMRST#

R1910 0R0402-PADR1910 0R0402-PAD

1 2

R1911 10KR2J-3-GP

1 2

PCH_WAKE# 27

PM_CLKRUN# 27

TP1901 TPAD14-GPTP1901 TPAD14-GP

R1913 0R0402-PADR1913 0R0402-PAD

1 2

TP1902 TPAD14-GPTP1902 TPAD14-GP

TP1903TPAD14-GPTP1903TPAD14-GP

TP1904TPAD14-GPTP1904TPAD14-GP

H_PM_SYNC 5

TP1905TPAD14-GPTP1905TPAD14-GP

R1912

1 2

0R0402-PAD

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# a re left as ¡¥no connect¡¦

4.SUSWARN# used as SUSPWRDNACK/GPIO30

PM_RSMRST#

RSMRST#_KBC 27

PCH_SUSCLK_KBC

EC1901

1 2

DY

SC4D7P50V2CN-1GP

RTC_AUX_S5

PCH_SUSCLK_KBC 27

PM_SLP_S4# 27,46,75

PM_SLP_S3# 27,36,37,47,75

0625 Modify: Reserved EC1901 on PCH_SUSCLK_KBC for EMC NEO suggestion.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

2

Date: Sheet

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

Tuesday, January 04, 2011

R1918 330KR2J-L1-GP

1 2

DY

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (DM I/FDI/PM)

QUEEN 15

19 108

1

RTC_AUX_S5

3D3V_S0

of

A00

5

SSID = PCH

1112 X02 Modify: Dell required us to disable PCIE port of WWAN slot ,If PCIE port 1 is disabled, it will cause all PCIE port disabled,so change WWAN to PCIE port 3 from port1

D D

C C

::$1&/.

20100614 V1.1

:/$1&/.

0623 Modify: SWAP WLAN CLK and LAN CLK routing each other. 0716 Modify: Rename PCIE_CLK_LAN_RQ1# to PCIE_CLK_LAN_REQ#.

20100614 V1.1

/$1&/.

B B

86%&/.

PCIECLKRQ1# and PCIECLKRQ2# Support S0 power only

1(:&$5'&/.

A A

1 2

DY

SC4D7P50V2CN-1GP

at ST stage.

PCIE_RXN282

PCIE_RXP282 PCIE_TXN282 PCIE_TXP282

PCIE_RXN382

PCIE_RXP382 PCIE_TXN382 PCIE_TXP382

PCIE_RXN482

PCIE_RXP482 PCIE_TXN482 PCIE_TXP482

PCIE_RXN582

PCIE_RXP582 PCIE_TXN582 PCIE_TXP582

PCIE_RXN875

PCIE_RXP875 PCIE_TXN875 PCIE_TXP875

CLK_PCIE_WWAN#82 CLK_PCIE_WWAN82

CLK_PCIE_LAN#82 CLK_PCIE_LAN82

0623 Modify: Change PCIE_CLK_RQ2#&CLK_PCIE_WLAN_REQ# pull high power to 3D3V_S0 from 3D3V_S5.(add RN2018)

RN2018

1 2 3

SRN10KJ-5-GP

CLK_PCIE_NEW#75 CLK_PCIE_NEW75

CLK_PCIE_NEW# CLK_PCIE_NEW

EC2004

EC2005

1 2

DY

SC4D7P50V2CN-1GP

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

X02 1115

C2011 SCD1U10V2KX-5GPC2011 SCD1U10V2KX-5GP

1 2

C2012 SCD1U10V2KX-5GPC2012 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

C2009 SCD1U10V2KX-5GPC2009 SCD1U10V2KX-5GP

1 2

C2010 SCD1U10V2KX-5GPC2010 SCD1U10V2KX-5GP

1 2

C2004 SCD1U10V2KX-5GPC2004 SCD1U10V2KX-5GP

1 2

C2003 SCD1U10V2KX-5GPC2003 SCD1U10V2KX-5GP

1 2

CLK_PCIE_WWAN_REQ#82

CLK_PCIE_WLAN#82 CLK_PCIE_WLAN82

CLK_PCIE_WLAN_REQ#82

PCIE_CLK_LAN_REQ#82

CLK_PCIE_USB3#82

CLK_PCIE_USB382

USB3_PEGB_CLKREQ#82

20100614 V1.1

PCIE_CLK_RQ2#

4

CLK_PCIE_WLAN_REQ#

CLK_PCIE_NEW_REQ#75

0913 X01 Modify: Reserved EC2004,EC2005 on CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.

5

CLK_PCH_48M

EC2003

1 2

DY

SC4D7P50V2CN-1GP

A00

RN2011

4

0R4P2R-PAD

4

0R4P2R-PAD

RN2014

4

0R4P2R-PAD

RN2013

4

0R4P2R-PAD

A00

RN2015

4

0R4P2R-PAD

TP2005TPAD14-GP TP2005TPAD14-GP TP2006TPAD14-GP TP2006TPAD14-GP

0630 Modify: Removed XDP CLOCK and reserved TP2005,TP2006.

RN

A00

RN2012

A00

RN

A00

RN

23 1

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN5_C PCIE_TXP5_C

PCIE_TXN8_C PCIE_TXP8_C

CLK_PCH_SRC0_N CLK_PCH_SRC0_P

0630 SWAP RN2012

CLK_PCH_SRC1_N

1 23

PCIE_CLK_RQ2#

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

CLK_PCH_SRC4_N CLK_PCH_SRC4_P

PCIE_CLK_REQ5#

PEG_B_CLKRQ#

PCIE_CLK_REQ6# CLK_PCH_SRC7_N

CLK_PCH_SRC7_P CLK_PCIE_NEW_REQ#

ITPXDP_N

1

ITPXDP_P

1

¡V Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 ¡V Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed.

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

COUGAR-GP-U2-NF

4

Cougar

Cougar Point

Point

Card Reader

LAN

W-WAN

WLAN

USB3.0

PCI-E*

Intel GBE LAN

Dock

NEW CARD

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

Link

PEG_A_CLKRQ#/GPIO47

CLOCKS

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

FLEX CLOCKS

2 OF 10

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

3

E12 H14 C9

A12 C8 G12

C13 E14 M16

M7

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43 F47 H47 K49

3

PEG_CLKREQ#_R

XCLK_RCOMP

DGPU_PRSNT#

EC_SWI# SMB_CLK SMB_DATA

DRAMRST_CNTRL_PCH SML0_CLK SML0_DATA

PCH_GPIO74 SML1_CLK SML1_DATA

CL_CLK

1

CL_DATA

1

CL_RST#

1

For DIS_PX mode or MXM mode.

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_PCLK_PCH_SRC1_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

1 2

R2007

R2007 90D9R2F-1-GP

90D9R2F-1-GP

JTAG_TCK

1 2

DY

R2001

CLK_48_USB30 CLK_27M_VGA_R

R2001

EC_SWI# 27 SMB_CLK 75 SMB_DATA 75

DRAMRST_CNTRL_PCH 37

SML1_CLK 27,86 SML1_DATA 27,86

TP2001 TPAD14-GPTP2001 TPAD14-GP

TP2002 TPAD14-GPTP2002 TPAD14-GP

TP2003 TPAD14-GPTP2003 TPAD14-GP

DY

R2003

1 2

0R2J-2-GP

RN

1

4

RN2016

23

0R4P2R-PAD

RN

1

4

RN2010

23

0R4P2R-PAD

0630 SWAP RN2010,RN2016

RN2008

2 3

1

SRN10KJ-5-GP

PL 10K FOR Integrated CLOCK GEN mode.

CLK_PCI_FB 18

+VCCDIFFCLKN

22R2J-2-GP

R2016 22R2J-2-GPR2016 22R2J-2-GP

1 2

R2002

1 2

DY

0908

0R2J-2-GP

0630 Modify: Removed LAN_XI for LAN 25MHZ and reserved TP2004. 0707 Modify: Removed R2002 for USB3.0 48MHZ. 0709 Modify: Add R2002 22ohm for CLK_27M_VGA. 0717 Modify: default stuff R2002 22ohm for CLK_27M_VGA.

PEG_CLKREQ# 83

A00

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

A00

CLK_EXP_N 5 CLK_EXP_P 5

0712 Modify: SWAP RN2008

4

0712 Modify: SWAP RN2020

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

0712 Modify: SWAP RN2019

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_REF14

JTAG_TCK_VGA 86

CLK_PCH_48M 32

2

3D3V_S5

DY

PEG_CLKREQ#_R

SMB_DATA

SMB_CLK

X02 1118

SRN10KJ-5-GP

SRN10KJ-5-GP RN2020

RN2020

2 3 1

4

RN2021 SRN10KJ-5-GPRN2021 SRN10KJ-5-GP

1

4

2 3

RN2019

2 3 1

4

SRN10KJ-5-GP

R2008

1 2

10KR2J-3-GP

For VGA_ 27M

CLK_27M_VGA 83

2

1

0705 Modify: Add R2004 from RN2001.

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

0915 SWAP

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

RN2007

2 3 1

SRN2K2J-1-GP

2nd = 84.DM601.03F

84.2N702.A3F

2N7002KDW-GP

6 5

Q2001

XTAL25_IN

XTAL25_OUT

20100621 V1.2

3D3V_S03D3V_S0

12

R2012

12

R2010

DY

0705 Modify: Separate RN2009 10K to RN2019, RN2021,R2008 for layout routing.

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

SMB_CLK SMB_DATA

SML0_CLK SML0_DATA

SML1_CLK SML1_DATA

PCIE_CLK_REQ6# PCH_GPIO74

DRAMRST_CNTRL_PCH

4

4 2 3

1 1

2 3

R2009

1 2

1KR2J-1-GP

0719 Modify: R2009 change to 1K from 10K base on Intel James feedback list.

CRB : 1K CEKLT: 10K

1 2 34

1118 X02 Modify: Change X2001 to 82.30020.D41 from 82.30020.851 from Sourcer Dick updated.

X2001

R2006

R2006 1M1R2J-GP

1M1R2J-GP

2 3

1 2

82.30020.D41

2nd = 82.30020.G71

3rd = 82.30020.G61

12

R2013

UMA

UMA_DIS# DGPU_PRSNT#

10KR2J-3-GP

12

R2011

MUXLESS

10KR2J-3-GP

3D3V_S53D3V_S0

QUEEN 15

Tuesday, January 04, 2011

QUEEN 15

PCH_SMBDATA 14,15,79,82

PCH_SMBCLK 14,15,79,82

41

XTAL-25MHZ-155-GP

SC12P50V2JN-3GP

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 Optimus(Muxless) : 1 0

UMA_DIS# 22

RN2001

1 2 3 4 5

SRN10KJ-6-GP

SRN10KJ-6-GP RN2002

RN2002

1 2 3 4 5

SRN10KJ-6-GP

0625 Modify: Move R2014 to RN2002.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

RN2003

1

SRN2K2J-1-GP

23

RN2004

23

SRN2K2J-1-GP

1

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

C2008

12

SC12P50V2JN-3GP

C2007

12

0712 Modify: SWAP RN2001 PIN6,7,8

8

PCIE_CLK_LAN_REQ#

7

CLK_PCIE_WWAN_REQ#

6

USB3_PEGB_CLKREQ#

EC_SWI#

8

PCIE_CLK_REQ5#

7

CLK_PCIE_NEW_REQ#

6

PEG_B_CLKRQ#

of

20 108

3D3V_S5

A00

5

SSID = PCH

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

D D

12

C2101

SC15P50V2JN-2-GP

HDA_CODEC_SYNC29

HDA_CODEC_RST#29 HDA_CODEC_BITCLK29

C C

HDA_CODEC_SDOUT29

X2101

1 4

32

0805

X-32D768KHZ-67-GP

82.30001.A81

2nd = 82.30001.691

3rd = 82.30001.861

20101220 R2123 R2124 for change to parallel resistor

RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

0720 Modify: un-stuff R2122 33ohm.

R212233R2J-2-GP

12

DY

0707 Modify: Change RN2101 to R2122,R2123 33ohm 0402.

RN2102

1

4

2 3

SRN33J-5-GP-U

HDA_SYNC HDA_SYNC_R

2 3 1

RN2105

4

SRN33J-5-GP-U

HDA_SYNC

HDA_RST# HDA_BITCLK

HDA_SDOUT

RTC_AUX_S5

1 2 1 2

SC1U6D3V2KX-GP

A00

Flash Descriptor Security Overide

Low = Default High = Enable

No Reboot Strap

Low = Default High = No Reboot

HDA_SYNC

HDA_SDOUT

HDA_SPKR

HDA_SDOUT

HDA_SPKR

+3VS_+1.5VS_HDA_IO

DY

R2102 1KR2J-1-GP

1 2

3D3V_S0

B B

NO REBOOT STRAP

DY

R2106 1KR2J-1-GP

1 2

+3VS_+1.5VS_HDA_IO

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

1 2

PLL ODVR VOLTAGE

HDA_SYNC

RUN_ENABLE

A A

R2117

R2117 100KR2J-1-GP

100KR2J-1-GP

1 2

0707 Modify: Reserved Q2101 for isolate CODE and PCH base on design guide update 1.01. 0712 Modify: Add R2124 between HDA_SYNC_R and HDA_SYNC.

Low = 1.8V (Default) High = 1.5V

2N7002K-2-GP

G

D

S

Q2101

84.2N702.J31

2ND = 84.2N702.031

5

0625 Modify: Reserved EC2102,EC2103 on HDA_CODEC_BITCLK&HDA_CODEC_SDOUT for

HDA_SYNC_R SATA_DET#0

0720 Modify: Add R2117 100K and stuff Q2101,R2124.

EMC NEO suggestion.

R2115

R2115 20KR2J-L2-GP

20KR2J-L2-GP

R2116

R2116 20KR2J-L2-GP

20KR2J-L2-GP

C2104

4

0630 modify: Change RN2104 PH 20K to R2115,R2216 20K 0402.

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

G2101

12

GAP-OPEN

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

RTC_AUX_S5

HDA_SPKR29

HDA_SDIN029

1M1R2J-GP

R2104

1 2

R2105

330KR2F-L-GP

12

3

RTC_X1 RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK HDA_SYNC

HDA_RST#

Notes: ME_UNLOCK (HDA_SDO) connect to EC. Make sure EC drive this pin "low" all the time.

R2107 1KR2J-1-GPR2107 1KR2J-1-GP

ME_UNLOCK27

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

EC2102

1 2

DY

SC4D7P50V2CN-1GP

4

DY

1 2

SPI_CLK_R27,60 SPI_CS0#_R27,60

SPI_SI_R27,60

SPI_SO_R27,60

EC2103

SC4D7P50V2CN-1GP

HDA_SDOUT

TP2105TPAD14-GP TP2105TPAD14-GP

TP2101TPAD14-GP TP2101TPAD14-GP TP2102TPAD14-GP TP2102TPAD14-GP TP2103TPAD14-GP TP2103TPAD14-GP TP2104TPAD14-GP TP2104TPAD14-GP

1 2

R2108 33R2J-2-GPR2108 33R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 33R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

SPI_CS0#_RHDA_CODEC_BITCLK HDA_CODEC_SDOUTHDA_CODEC_SYNC

EC2101

1 2

DY

0625 Modify: Reserved EC2101 on SPI_CSO#_R for EMC NEO suggestion.

SC4D7P50V2CN-1GP

PCH_GPIO33

1

PCH_JTAG_TCK_BUF

1

PCH_JTAG_TMS

1

PCH_JTAG_TDI

1

PCH_JTAG_TDO

1

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_SI

3

PCH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGAR-GP-U2-NF

INT_SERIRQ

S_GPIO22

FP_DET#22 PSW_CLR#22

Cougar

Cougar Point

Point

RTCIHDA

JTAG

SPI

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA 6G

SATA

SATAICOMPO

SATA3RCOMPO

SATA0GP/GPIO21 SATA1GP/GPIO19

RN2103

1 2 3 4 5

SRN10KJ-6-GP

SRN10KJ-6-GP RN2104

RN2104

4

SRN10KJ-5-GP

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LDRQ0#

SERIRQ

SATA0RXN

SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA1RXP SATA1TXN SATA1TXP

SATA2RXN

SATA2RXP SATA2TXN SATA2TXP

SATA3RXN

SATA3RXP SATA3TXN SATA3TXP

SATA4RXN

SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

8 7 6

1 23

2

LPC_AD[0..3]

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37 D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

3D3V_S0

0916 X01 Modify: Add RN2104 instead of R2111 10K.

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_DET#0 BBS_BIT0

2

1

LPC_AD[0..3] 27,71

LPC_FRAME# 27,71

KB_DET# 69

INT_SERIRQ 27

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

0709 Modify: KB_DET# connect to GPIO23.(inter PH 20K)

20100625 V1.2

SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56

0629 Modify: Move All of 0.01uF cap closed to all connector base on Layout guideline.

SATA_RXN4 56 SATA_RXP4 56 SATA_TXN4 56 SATA_TXP4 56

SATA_RXN5 57 SATA_RXP5 57 SATA_TXN5 57 SATA_TXP5 57

1D05V_VTT

1 2

SATA_LED# 68

BBS_BIT0 18

PCH (SPI/RTC/LPC/SATA/I HDA)

Tuesday, January 04, 2011

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

QUEEN 15

21 108

1

HDD1

HDD2

ODD

ESATA

of

A00

5

4

3

2

1

3D3V_S0

1 2

3D3V_S0

D D

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

C C

1120 X02 Modify: Rename PCH_GPIO12 to RTC_DET# on GPIO12.

B B

A A

0712 Modify: SWAP RN2203

RN2203

2 3 1

SRN10KJ-5-GP

3D3V_S0

0701 Modify: Separate PCH_TEMP_ALERT# from RN2201 to R2222 10K base on layout limitation.

PCH_TEMP_ALERT#

MFG_MODE

EC_SMI# EC_SCI#

DGPU_HPD_INTR#

DBC_EN

0923 SWAP 1118 X02 Modify:

RTC_DET# USB2_CRT_ON#

PCH_GPIO15

3G_EN

20100625 V1.2

0629 Modify: Add R2221 10K 0402 on PCH_GPIO24(ANNIE updated) 0709 Modify: Rename PCH_GPIO24 to 3G_EN on R2221.

0719 Modify: Change R2202 to 100K from 200K.

R2202

100KR2J-1-GP

0629 Modify: Stuff R2202 200K 0402 1%(ANNIE updated)

4

R2220 10KR2J-3-GPR2220 10KR2J-3-GP

1 2

R2222 10KR2J-3-GPR2222 10KR2J-3-GP

1 2

R2223 10KR2J-3-GPR2223 10KR2J-3-GP

1 2

RN2201

1 2 3 4 5

SRN10KJ-6-GP

5

H_A20GATE H_RCIN#

PCH_GPIO48

8 7 6

RN2204

4

SRN10KJ-5-GP

SRN10KJ-5-GP R2201

R2201

1 2

R2221

1 2

10KR2J-3-GP

SATA_ODD_PRSNT#

1 23

1KR2J-1-GP

Note: For PCH debug with XDP, need to NO STUFF R2218

20100625 V1.2

1120 X02 Modify: Rename PCH_GPIO12 to RTC_DET# on GPIO12.

0908 X01 Modify: change FFS_INT2_R from PCH GPIO48 to GPIO14 Keep PCH_GPIO5 PH R2201,PCH_GPIO48 PH R2220

0720 Modify: Removed DBC_EN on GPIO22.

3D3V_S0

0701 Modify: Separate MFG_MODE from RN2202 to R2223 10K base on layout limitation.

0916 X01 Modify: Move EC_SCI#,DBC_EN to RN2201. Move S_GPIO to RN2103. Move PSW_CLR# to RN2104.

1118 X02 Modify: Rename USB3_PWR_ON to PCH_GPIO57. 1120 X02 Modify: Reserved USB2_CRT_ON# to control U6102 USB power switch from PCH GPIO57.

3D3V_S5

0709 Modify: Rename PCH_GPIO22 to DBC_EN. Rename PCH_GPIO24 to 3G_EN.

SSID = PCH

S_GPIO GPIO0

S_GPIO21

EC_SMI#27

EC_SCI#27

RTC_DET#60

SATA_ODD_PRSNT#56

DGPU_PWROK83,92,93

TPAD14-GP

PSW_CLR#21

GAP-OPEN

21

G2201

Rename GFX_CRB_DET to GSENSOR_DET on GPIO39.

USB2_CRT_ON#61

0714 Modify: Add TP2206~TP2209 on PCH NCTF pin.

[VRAM_SIZE1:VRAM_SIZE2] LL=512M / HL=1G / LH=2G

0705 Modify: Removed R2214~R2217 10K 0402 on VRAM_SIZE1&2.

4

R2213 0R0402-PADR2213 0R0402-PAD

TP2210

3G_EN82

TP2203

PSW_CLR#

FP_DET#21

TP2206TPAD14-GP TP2206TPAD14-GP

TP2207TPAD14-GP TP2207TPAD14-GP TP2208TPAD14-GP TP2208TPAD14-GP

TP2209TPAD14-GP TP2209TPAD14-GP

1 2

1

1 1

1

R2218

1 2

100R2J-2-GP

EC_SMI# DGPU_HPD_INTR# EC_SCI# ICC_EN#

RTC_DET#

PCH_GPIO15

DGPU_PWROK

1

PCH_GPIO27

1

PLL_ODVR_EN

DMI_OVRVLTG FDI_OVRVLTG MFG_MODE

GSENSOR_DET

PCH_GPIO48

PCH_TEMP_ALERT#

USB2_CRT_ON#

PCH_NCTF_1

PCH_NCTF_2 PCH_NCTF_3

PCH_NCTF_4

PCH_GPIO16

DBC_EN

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

6 OF 10

A20GATE

PECI

RCIN#

INIT3_3V#

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14

AH8 AK11 AH10 AK10 P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

UMA_DIS# VRAM_SIZE1 VRAM_SIZE2

TS_VSS

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

PROCPWRGD

GPIO

THRMTRIP#

CPU/MISC

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4 NCTF_VSS#BJ44 NCTF_VSS#BJ45 NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

D1,D49,E1,E49,F1,F49

NCTF_VSS#F49

PLL ON DIE VR ENABLE



NOTE:This signal has a weak internal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

PLL_ODVR_EN

3

1 2

DY

R2212

1KR2J-1-GP

SATA_ODD_PWRGT 56 UMA_DIS# 20

TP2204

TPAD14-GP

1 1

H_PECI_R

PCH_THERMTRIP_R INIT3_3V#

1 2

R2219 0R0402-PADR2219 0R0402-PAD

0707 Modify: Change R2219 change to 0ohm 0402 from short pad.

3D3V_S0

12

R2207

R2207 10KR2J-3-GP

10KR2J-3-GP

DY

FDI_OVRVLTG

12

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

TPAD14-GP

TP2205

TPAD14-GP

H_A20GATE 27

R2203

1 2

DY

0R2J-2-GP

H_RCIN# 27

R2204 390R2J-1-GPR2204 390R2J-1-GP

TP2201

1

0R2J-2-GP

H_CPUPWRGD 5,36

1 2

TPAD14-GP

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

DMI TERMINATION VOLTAGE OVERRIDE

3D3V_S0

ICC_EN#

12

R2209

R2209 10KR2J-3-GP

10KR2J-3-GP

DY

12

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

R2211

1 2

DMI_OVRVLTG

1KR2J-1-GP

2

GPIO36 (DMI_OVRVLTG)

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Integrated Clock Chip Enable

ICC_EN#

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

GSENSOR_ST GSENSOR_ADI

R2205 DY 10K

R2206 100K DY

3D3V_S0

DY

H_PECI 5,27

DY

H_THERMTRIP# 5,36

0625 Modify: Change PL 100K 0402 from PH on GFX_CRB_DET.

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (GPIO/CPU)

QUEEN 15

Tuesday, January 04, 2011

QUEEN 15

1

12

R2205

R2205 10KR2J-3-GP

10KR2J-3-GP

GSENSOR_DET

12

R2206

R2206 100KR2J-1-GP

100KR2J-1-GP

of

22 108

A00

5

1D05V_VTT

(1uFx3)

1D05V_VTT

6A

12

C2301

12

C2305

C2306

SC10U6D3V5KX-1GP

1.3A(Total current of VCCCORE)

12

SC10U6D3V5KX-1GP

TP2301TPAD14-GP TP2301TPAD14-GP

12

SC1U6D3V2KX-GP

0818 De-cap

0.266A (Totally VCC3_3 current)

12

C2302

2.925A(Total current of VCCIO)

C2303

SC1U6D3V2KX-GP

C2307

SC1U6D3V2KX-GP

1D05V_VTT

1

(10uF x1)

12

C2308

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

3D3V_S0

SSID = PCH

D D

(10uFx1_0603)

(1uF x4)

C C

(0.1uF x1)

0.159A(Totally current of VCCVRM)

B B

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop

1D5V_S0

TP2302TPAD14-GP TP2302TPAD14-GP

1D05V_VTT

1

0.042A (Totally current of VCCDMI)

4

12

C2304

SC1U6D3V2KX-GP

VCCAPLLEXP

12

C2309

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCFDIPLL

+1.05VS_VCC_DMI

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

NAND / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

VCC3_3

VCCVRM

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

3

0.001A

+VCCA_DAC_1_2

U48

U47

0.001A

+3VS_VCCA_LVDS

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

0.16A

VCCVRM

AT16

0.042A

+1.05VS_VCC_DMI

AT20

AB36

0.02A

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

(0.1uF/0.01uF x1) (10uF x1_0603)

12

C2313

0.06A

+1.8VS_VCCTX_LVDS

0.266A

12

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

0.19A

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

0.02A

12

C2314

SCD01U16V2KX-3GP

12

C2316

(0.1uFx1)

R2308

1 2

0R0402-PAD-2-GP

A00

1 2

R2306

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

A00

1 2

R2307

0R0402-PAD-2-GP

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

A00 1228

R2301

1 2

0R0402-PAD-2-GP

1111 X02 Modify: Change VCCADAC power source to 3D3V_DAC_S0 from 3D3V_S0.

12

C2315

SCD1U10V2KX-5GP

12

SCD01U16V2KX-3GP

0R0402-PAD-2-GP

0917 X01 Modify: Change R2304 to 0R0603

SC10U6D3V5KX-1GP

short pad from 0ohm.

12

C2318

C2317

SCD01U16V2KX-3GP

3D3V_S0

A00

1D5V_S0

1D05V_VTT

(1uF x1)

1D05V_VTT

(1uFx1) (10uFx1)

3D3V_S5

(1uFx1)

2

3D3V_DAC_S0

3D3V_S0

L2301

1 2

DY

HCB1608KF-181-GP

68.00214.051

2nd = 68.00206.041

3rd = 68.00335.081

R2304

1 2

0R0603-PAD

R2305

1 2

0R0805-PAD

SC10U6D3V5KX-1GP

1119 X02 Modify: Reserved R2308 on VCCVRM power rail.

(0.01uF x2) (22uF x1)

1D8V_S0

3D3V_S0

1D8V_S0

(0.1uFx1)

1

Refer to NPCE795 shared SPI flash architecture

3.3V CRT LDO

3D3V_S05V_S5 3D3V_DAC_S0

U2301

1

1122 X02 Modify: Removed U2302 LDO for VCCVRM.

A A

C2311

12

20100621 V1.2

SC1U10V2KX-1GP

5

4

A00 1229 add 3rd Richtek(74.09198.G7F) on U2301 at XBuild batch run config

3

VIN

2

GND EN3NC#4

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

3rd = 74.07716.A7F

1117 X02 Modify: Add G9091 LDO circuit for CRT DAC power to avoid monitor noise issue. 1122 X02 Modify: base on layout condition change 3D3V_DAC_S0 circuit.

Current Limit=360mA

5

VOUT

4

12

C2312

SC1U6D3V2KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

PCH (POWER1)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

23 108

1

A00

5

4

3

2

1

SSID = PCH

1

TP2405TPAD14-GP TP2405TPAD14-GP

1

(10uFx1)

1

12

C2415

12

(1uFx1)

TP2406TPAD14-GP TP2406TPAD14-GP

VCCACLK

+VCCPDSW

DCPSUSBYP

1

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS1

12

C2407

1D5V_S0

C2408

SC1U6D3V2KX-GP

0818 De-cap

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

+VCCDIFFCLK

0.095A

+V1.05S_SSCVCC

(1uFx1)

+VCCSST

12

DCPSUS

1

C2418

SCD1U10V2KX-5GP

12

C2422

C2421

SCD1U10V2KX-5GP

TP2401TPAD14-GP TP2401TPAD14-GP

0.002A

3D3V_S0

(10uFx1)

D D

C C

1D05V_VTT

2nd = 68.1001E.10N

B B

1D05V_VTT

A A

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001E.10N

L2402

1 2

IND-10UH-218-GP

68.10050.10Y

L2403

1 2

IND-10UH-218-GP

68.10050.10Y

R2404

1 2

0R0402-PAD-2-GP

A00

R2405

1 2

0R0402-PAD-2-GP

0.08A

+1.05VS_VCCA_A_DPL

12

C2443

DY

0.08A

+1.05VS_VCCA_B_DPL

12

C2444

DY

A00

+VCCDIFFCLK

12

SC1U6D3V2KX-GP

+V1.05S_SSCVCC

12

SC1U6D3V2KX-GP

5

(1uFx1)

+V3.3S_VCC_CLKF33

C2401

12

(22uFx2_0603) (1uFx3)

(1uFx1) (220uFx1)

12

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

12

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

C2412

C2413

12

C2402

C2402 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

1D05V_VTT

(1uFx1) (220uFx1)

SCD1U10V2KX-5GP

1D05V_VTT

(1uFx1)

3D3V_S5

(0.1uFx1)

1.01A (Total current of VCCASW)

C2404

C2403

12

0714 Modify: Reserved C2443,C2444 on +1.05VS_VCCA_A_DPL, +1.05VS_VCCA_B_DPL same as DG15.

0617 Modify: Joseph Rename 1D5V_S0_1D8V_S0 to 1D5V_S0 for VCCVRM.

C2411

1D05V_VTT

(0.1uFx2) (4.7uFx1_0603)

RTC_AUX_S5

(0.1uFx2) (1uFx1)

C2404

12

SC10U6D3V5KX-1GP

+VCCRTCEXT

12

(0.1uFx1)

R2406

1 2

0R0603-PAD

C2414

SC1U6D3V2KX-GP

(0.1uFx1)

(1uFx1)

0.001A

C2417

SC4D7U6D3V3KX-GP

6uA

R2403

1 2

0R0603-PAD

TP2404TPAD14-GP TP2404TPAD14-GP

1D05V_VTT

TP2402TPAD14-GP TP2402TPAD14-GP

12

C2406

SC1U6D3V2KX-GP

0.16A (Totally current of VCCVRM

+VCCDIFFCLKN

0.055A

12

SCD1U10V2KX-5GP

0714 Modify: Removed C2419 1uF base on Annie updated schematic.

12

4

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

PCI/GPIO/LPCMISC

SATA USB

CPURTC

HDA

3

10 OF 10

VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCC3_3 VCC3_3 VCC3_3

VCC3_3

VCCIO

VCCIO VCCIO

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO VCCIO VCCIO

VCCASW

VCCSUSHDA

N26 P26 P28 T27 T29

0.097A (Totally current of VCCSUS3_3)

T23 T24 V23 V24 P24

T26

M26

AN23 AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

T21

V21

T19

P32

1D05V_VTT

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

+5VS_PCH_VCC5REF

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

1D5V_S0

SCD1U10V2KX-5GP

1D05V_VTT

SCD1U10V2KX-5GP

0.01A

C2433

SCD1U10V2KX-5GP

C2433

3D3V_S5

0818 De-cap

12

DY

12

C2428

12

C2430

12

C2429

12

C2432

12

C2435

+3VS_+1.5VS_HDA_IO

(0.1uFx1)

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2434

DY

C2423

C2423 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1

C2437

C2437 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

2

1D05V_VTT

(1uFx1)

0818 De-cap

3D3V_S5

(0.1uFx1)

3D3V_S5

(0.1uFx1)

TP2403 TPAD14-GPTP2403 TPAD14-GP

0.001A

3D3V_S5

(1uFx1)

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

(0.1uFx1)

R2411

1 2

DY

0R3J-0-U-GP

1D05V_VTT

(1uFx1)

3D3V_S5

2nd = 83.R2004.B8F

21

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

1 2

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R2408

5V_S5

(0.1uFx1)

0.001A

3D3V_S0

21

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

2nd = 83.R2004.B8F

3D3V_S0

83.R0304.A8F

12

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

10R2J-2-GP

(0.1uFx2)

3D3V_S0

1D05V_VTT

(1uFx1)

1D05V_VTT

(10uFx1)

+3VS_+1.5VS_HDA_IO

R2409

1 2

0R0603-PAD

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

PCH (POWER2)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

R2407

5V_S0

(1uFx1)

24 108

1

3D3V_S5

A00

of

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

PCH (VSS)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

25 108

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Reserved

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

26 108

1

A00

SSID = KBC

3D3V_AUX_KBC

1 2 12

D D

0708 Modify: Rename EG_EN to MEDIA_BTN2# on GPIO96. 0702 Modify: Rename CHARGE_LED# to CHG_AMBER_LED# Rename DC_BATFULL# to BATT_WHITE_LED#.

0702 Modify: Rename EC_GPIO6 to PSL_IN2 0707 Modify: Rename DISCRETE# to MODEL_ID_DET. Rename EC_GPIO36 for MEDIA_BTN3#.

1 2

0628 Modify: Move R2771 to closed 3D3V_AUX_KBC power

R2771

rail base on layout placement.

2D2R3-1-U-GP

12

C2704

C2701

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

0720 Modify: Stuff C2714 0.1uF on AD_IA.

0629 Modify: Rename TP_LOCK_LED#&BATT_WHITE_LED# 0702 Modify: Rename EC_GPIO70 to PSL_IN1 Rename EC_GPIO71 to PSL_OUT

C C

0604 Modify: RN2704 pull-Low 10K Resistor to DY on BLUETOOTH_EN.

5

R2702

R2702 0R0603-PAD

0R0603-PAD

12

C2705

C2706

DY

SCD1U10V2KX-5GP

C2714 SCD 1U10V2KX-5GPC2714 SCD1U10V2KX-5G P

EC_AGND

FAN1_DAC28

SUS_PWR_ACK19

USBCHARGER_CB057

USB3_PWR_ON82

BATT_WHITE_LED#68

S5_ENABLE36

LID_CLOSE#70

RSMRST#_KBC19

PM_SLP_S4#19,46,75

ME_UNLOCK21

WIFI_RF_EN82 BLUETOOTH_EN63,82 S0_PWR_GOOD19,36

TP_LOCK_LED#68

USB_PWR_EN#61

AC_PRESENT19,86

IMVP_PWRGD36,42

0706 Modify: KBC GPIO7 change to DISCRETE# KBC GPIO97 change to IMVP_PWRGD.

0714 Modify: Change C2709,C2710 to EC_AGND from GND.

12

C2708

SCD1U10V2KX-5GP

C2709

EC_AGND

R2762

1 2

A00

0R0402-PAD-2-GP

KBC_VCORF

12

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

12

SC2D2U10V3KX-1GP

PCB_VER_AD

MEDIA_BTN2#

USB3_PWR_ON

PSL_IN2 MODEL_ID_DET

ECSMI#_KBC

PSL_IN1 PSL_OUT EC_GPIO72

12

C2707

SCD1U10V2KX-5GP

AD_IA40

1 2

PSID_EC82

CPU_THRM28

LCD_TST49

SYS_THRM28

CAP_LED69

MEDIA_BTN3#82

BAT_IN#39

RCID82

C2712 Need very close to EC

SCD1U10V2KX-5GP

C2710

EC_GPIO97

VBAT

3D3V_AUX_KBC_VCC

U2701A

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

79

GPIO2

95

GPIO3/AD6

96

GPIO4/AD5

108

GPIO5/AD4

93

PSL_IN2#_GPIO6

94

GPIO7/AD7

114

GPIO16

6

GPIO24

109

GPIO30

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

23

GPIO46/CIRRXM/TRST#

26

GPIO51

73

PSL_IN1_GPIO70

74

PSL_OUT_GPIO71

75

VBKUP

82

GPIO75

83

GPO76/SHBM

84

GPIO77

91

GPIO81

110

GPO82/IOX_LDSH/TEST#

112

GPIO84/IOX_SCLK/XORTR#

107

GPIO97

44

VCORF

NPCE795PA0DX-GP-U

VCC19VCC46VCC76VCC88VCC

GND18GND45GND78GND89GND

115

GND

5

116

ROSA Multi GPIO setting

0719 Modify: Reserved 0.1uF on all of ADC input pins base on NUVOTON feedback list.(C2717~C2721)

C2719 SCD 1U10V2KX-5GP

CPU_THRM USB3_PWR_ON SYS_THRM

L_BKLT_EN17

12

DY

C2720 SCD 1U10V2KX-5GP

12

DY

C2721 SCD 1U10V2KX-5GP

12

DY

PANEL_BLEN

1 2

R2761 0R0402- PADR2761 0R0402-PAD

0630 Modify: Removed R2762 100K 0402.

EC_AGND

20100712 V1.5

EC_SWI#20

EC_SCI#22

B B

0714 Modify: Un-stuff D2701,D2704 and Add R2758,R2759 ohm confirm with NUVOTON and SW.

RN2706

4

SRN10KJ-5-GP

EC_SWI#20

EC_SCI#22

3D3V_AUX_S5

1

KBC_ON#_GATE

23

SCD1U10V2KX-5GP

PSL_IN2

BAT54CPT-GP

KBC_PWRBTN#68

3

D2702

2ND = 83.00054.Q81

83.R2003.E81

AC_IN#_KBC

A A

R2704

1

1 2

330KR2J-L1-GP

83.R2003.E81

2ND = 83.00054.Q81

2

KBC_ON#

2

10mW

1

BAT54CPT-GP

330KR2J-L1-GP

KBC_ON#_R

D2703

3

0902 X01 Modify: Add C2722 0.1uF between Q2703 G&S pin for fixed leakage voltage to 3D3V_AUX_KBC under DC mode. 0916 X01 Modify: Add Q2706 2N7002 to avoid leakage loop from 3D3V_S5 to 3D3V_AUX_KBC issue when 10mW latched fail timing.

EC_GPIO72

AC_IN# 40

5

R2711 0R0402- PADR2711 0R0402-PAD

D2701

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

D2704

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

R2758

1 2

0R0402-PAD-2-GP

A00

R2759

1 2

0R0402-PAD-2-GP

3D3V_AUX_S5

C2722

1 2

SCD1U10V2KX-5GP

G

12

C2713

DY

2N7002K-2-GP

G

S

Q2706

84.2N702.J31

2ND = 84.2N702.031

102

AVCC

GPIO11/CLKRUN#

GPIO67/PWUREQ#

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

1 2

ECSWI#_KBC

3

ECSCI#_KBC

3

ECSWI#_KBC

ECSCI#_KBC

S

G

D

3D3V_AUX_KBC

S5_ENABLE

D

4

SCD1U10V2KX-5GP

4

1 OF 2

VDD

LRESET#

LCLK

LFRAME#

LAD3 LAD2 LAD1 LAD0

SERIRQ

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO85/GA20

KBRST#/GPIO86

GPIO27/PSDAT2

GPIO26/PSCLK2

GPIO35/PSDAT1

GPIO37/PSCLK1

GPIO17/SCL1

GPIO22/SDA1

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

F_CS0#

F_SCK

F_SDI/F_SDIO1

F_SDIO/F_SDIO0

AGND

103

EC_AGND

Q2703

Q2703 DMP2130L-7-GP

DMP2130L-7-GP

2ND = 84.03413.A31

84.02130.031

4

3D3V_AUX_KBC

0719 Modify: Reserved 0.1uF on all of ADC input pins base on

3D3V_S0

NUVOTON feedback list.(C2717~C2721)

12

C2702

7 2 3 1 128 127 126 125 8 9 29 124 123 121 122

27 25 11 10 71 72

70 69 67 68 119 120 24 28

90 92 86 87

C2703

DY

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

C2711

DY

1 2

SC220P50V2KX-3GP

A00

R2735

PLT_RST#_EC

1 2

0R0402-PAD-2-GP

CLK_PCI_KBC 18

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

PANEL_BLEN

ECSCI#_KBC ECSWI#_KBC

AD_IA_HW2

MEDIA_BTN1#

EC_ENABLE#_1

PROCHOT_EC

EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C EC_SPI_DO_C

NOTE: Locate resistors R2736,R2719 and R2722 close to the NPCE795P.

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.

LPC_FRAME# 21,71

H_A20GATE 22 H_RCIN# 22

BLON_OUT 49

AD_IA_HW2 40

PCH_WAKE# 19

TPDATA 69 TPCLK 69

BAT_SCL 39,40 BAT_SDA 39,40 SML1_CLK 20,86 SML1_DATA 20,86

PM_LAN_ENABLE 82

LCD_TST_EN 49

A00

R2737 0R 0402-PAD-2-GPR2737 0R0402-PAD-2-GP

1 2

R2722 33R2J - 2-GPR2722 33R2J-2-GP

INT_S ERIRQ 21 PM_CLKRUN# 19

HDMI_ IN# 5 1

12 12

12

EC_GPIO47 High Active

PROCHOT_EC

12

R2732

G

S

100KR2J-1-GP

A00 1222

PCB_VER_AD MODEL_ID_DET

PLT_RST# 5,18,71,75,82,83

LPC_AD[0..3] 21,71

<------ TP

33R2J-2-GPR2736 33R 2J-2-GPR 2736 33R2J-2-GPR2719 33R 2J-2-GPR 2719

2N7002K-2-GP

Q2702

84.2N702.J31

2ND = 84.2N702.031

12

R2724

R2724 47KR2F-GP

47KR2F-GP

12

R2726

R2726 100KR2F-L1-GP

C2717

<------ BATTERY / CHARGER <------PCH / eDP

100KR2F-L1-GP

1 2

EC_AGND

0707 Modify: Rename PCH_TEMP_ALERT# for HDMI_IN#

0702 Modify: Rename CHARGE_LED# to CHG_AMBER_LED# Rename DC_BATFULL# to BATT_WHITE_LED#.

0709 Modify: EC_GPIO27 change to PCH_WAKE# to PCH. 0709 Modify: KB_DET# rename to MEDIA_BTN1# on KBC GPIO26.

0629 Modify: Rename PWRLED#&PWR_BTN_LED#&CHARGE_LED#. 0715 Modify: Removed PWR_BTN_LED# on KBC GPIO45. 0720 Modify: Change MEDIA_LED2# to KBC GPIO45. Add AD_IA_HW on KBC GPIO66.

SPI_CS0#_R 21,60 SPI_CLK_R 21,60 SPI_SO_R 21,60

SPI_SI_R 21,60

EC_SPI_DI_C

12

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

0604 Modify: Add Pull down 100k ohm at F_SDI for Power consumption concern.

H_PROCHOT#_EC

D

R2733 0R0402- PADR2733 0R0402-PAD

PSL SOLUTION

0712 Modify: default stuff R2756, un-stuff R2734.

A00 1228

EC_GPIO72

R2756

1 2

10mW

0R0402-PAD-2-GP

AC_OK

AC_OK40

PSL_OUT

NOTES: Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.

1 2

PSL

DY

R2767

1 2

G

PSL

S

Q2705

Q2705 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

A00 1228

R2768

0R2J-2-GP

KBC_ON#_R

0R2J-2-GP

D

0702 Modify: Rename EC_GPIO71 to PSL_OUT

PSL_IN1

PSL

12

R2769

R2769 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_KBC

3

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X01 X02

A00 Reserved Reserved

100.0KX00

100.0K

Reserved 100.0K 215.0K 1.048V

NOTES: The NPCE795P GPIO/PWM outputs that are connected to LEDs have high drive buffers (20mA) and can be connected directly to the LEDs.

0707 Modify: KBC_GPIO14 change to PCIE_WAKE#.

FAN_TACH128

PM_PWRBTN#19

PCIE_WAKE#75,82 PM_SLP_S3#19,36,37,47,75

CHG_AMBER_LED#68

KBC_BEEP29

MEDIA_LED1#82

KB_BL_CTRL69

AD_IA_HW40 MEDIA_LED3#82 MEDIA_LED2#82

PWRLED#68

E51_RxD82

E51_TxD82

AMP_MUTE#29

PCH_SUSCLK_KBC19

1D05V_VTT

H_PECI5,22

R2721 43R 2J-GPR2721 43R2J-GP

Need very close to EC

PURE_HW_SHUTDOWN#28,36,86

1 2

H_PROCHOT # 5,40,42

10mW SOLUTION

3D3V_AUX_KBCRTC_AUX_S5

R2734

1 2

DY

R2763

AC_IN#_KBC

10mW

0R0402-PAD-2-GP

0702 Modify: Rename EC_GPIO70 to PSL_IN1

EC_ENABLE#_1

R2766

VBACKUP

EC_GPIO72

0R2J-2-GP

A00 1228

PSL_IN1

12

2N7002K-2-GP

G

10mW

D

S

Q2704

84.2N702.J31

2ND = 84.2N702.031

12

10mW

0R0402-PAD-2-GP

A00 1228

PSL_IN1

PSL_OUT

KBC_ON#

KBC_ON#_RKBC_ON#

3

ECRST#

1 2 1 2

R2720 0R0402- PADR2720 0R0402-PAD

3D3V_AUX_S5

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K100.0K 1.358VReserved

174.0KReserved 100.0K 1.204V

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

SCD1U10V2KX-5GP

20100609 V1.0

U2701B

31

GPIO56/TA1

117

GPIO20/TA2

63

GPIO14/TB1

64

GPIO01/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM

85

EC_VTT

C2716

SCD1U16V2KX-3GP

12

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

0621 Modify: Removed R2723

PECI

12

VCC_POR#

113

GPIO87/CIRRXM/SIN_CR

111

GPIO83/SOUT_CR/TRIST#

30

GPIO55/CLKOUT/IOX_DIN_DIO

77

GPIO00/EXTCLK

13

PECI

12

VTT

NPCE795PA0DX-GP- U

KBSOUT15/GPIO61/XOR_OUT

12

E

MMBT3906-4-GP

B

DY

Q2701

C

84.T3906.A11

2nd = 84.03906.F11

EC GPIO standard PH/PL

BAT_SCL BAT_SDA

BAT_IN# AC_IN#_KBC

0630 Modify: Removed LID_CLOSE# PH 10K on RN2705.

S5_ENABLE ECRST#

EC_ENABLE#_1

0623 Modify: Change RN2702 to R2712 10K 0402 Resistor on FAN_TACH1.

FAN_TACH128

FAN_TACH1

E51_RxD

BLUETOOTH_EN

0623 Modify: Change RN2704 to R2708 10K 0402

0604 Modify: RN2704 pull-Low 10K Resistor to DY on BLUETOOTH_EN.

Resistor on BLUETOOTH_EN.

ECRST#

3D3V_AUX_KBC

2

12

R2710

64.33025.6DL

C2718

0707 Modify: Rename DISCRETE# to MODEL_ID_DET. Change R2739 to 100K 0402 from 10K.

KBSOUT0/JENK#

KBSOUT4/JEN0#

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK KBSOUT11/P80_DAT

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

C2715

SC1U6D3V2KX-GP

RN2701

4

SRN4K7J-8-GP

SRN4K7J-8-GP RN2703

RN2703

4

SRN100KJ-6-GP

RN2705

8 7 6

SRN10KJ-6-GP

1 2

R2712 10KR2J- 3-GPR2712 10KR2J-3-GP

DY

1 2

R2708 10KR2J- 3-GP

DY

1 2

R2709 10KR2J- 3-GP

R2710 33KR2F-GP

33KR2F-GP

0728

Ventura need to change t o 215K(64.21535.6DL)

1 2

EC_AGND

2 OF 2

53 52

KBSOUT1/TCK

51

KBSOUT2/TMS

50

KBSOUT3/TDI

49 48

KBSOUT5/TDO

47

KBSOUT6/RDY#

43

KBSOUT7

42

KBSOUT8

41 40 39 38 37 36 35 34 33

54

KBSIN0

55

KBSIN1

56

KBSIN2

57

KBSIN3

58

KBSIN4

59

KBSIN5

60

KBSIN6

61

KBSIN7

0714 Modify: Add USB_DET# on KBC GPIO57/KBSOUT17.

3D3V_AUX_KBC

23 1

1 23

1 2 3 45

0628 Modify: Stuff R2712 and Removed R2805.

3D3V_S0

2

MODEL_ID_DET(GPIO07)

DQ15_ATI DQ15_NVIDIA DN15_UMA DN15_ATI DQ13_UMA DQ13_ATI DN13_UMA DN13_ATI DQ15_Ventura 100.0K 215.0K 1.048V

Notes:

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

215K=64.21535.6DL

1

100.0KDQ15_UMA 3.0V

100.0K

10.0K

20.0K

33.0K

47.0K

64.9K

76.8K

100.0K

143.0K100.0K 1.358V

174.0K100.0K

The total SPI interface signal between EC and PCH can¡¦t not exceed 6500mil. The mismatch between SPI signal must be wit h i n 500mil

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

USB_DET#

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL[0..16] 69

A00 R2739 R2774 for change to parallel resistor

KROW[0..7] 69

0709 Modify: Add R2774,R2775 PH 100K to 3D3V_AUX_KBC for MEDIA_BTN2#,MEDIA_BTN3#. Add R2776 100K to 3D3V_AUX_KBC for PCIE_WAKE# from DEVICE to KBC. KB_DET# rename to MEDIA_BTN1# on KBC GPIO26.

USB_DET# MEDIA_BTN1#

MEDIA_BTN3# PCIE_WAKE#

0722 Modify: Add R2757 0ohm only for DQ15 stuff, change D2706 only for DN15 stuff.

INSTANT_ON#82

0712 Modify: Add D2706 connect to MEDIA BUTTON Instant_on#. 0713 Modify: Add R2772,D2707 for USBCHARGER DETECT Function.

0723 Modify: Add R2764,D2708 Base on Dell Peter request, both 13¡¨/15¡¨ Media BTN 2(Recovery Button) need support bootable capability.

USBDET_CON#57

DATA_RECOVERY#82

Title

Size Document Number Rev

Size Document Number Rev A2

A2

A2 Date: Sheet

Date: Sheet

MEDIA_BTN2# MODEL_ID_DET

A00

4

SRN100KJ-6-GP

0709 Modify: Removed R2772 10K PH on EC_GPIO27. 0714 Modify: Un-stuff D2705 and Add R2760 between EC_SMI# and ECSMI#_KBC already confirm with NUVOTON and SW.

EC_SMI#22

MEDIA BUTTON CONTROL

1 2

R2772 100KR2J-1-GPR2772 100KR2J-1-GP

1 2

R2770 100KR2J-1-GPR2770 100KR2J-1-GP

1 2

R2775 100KR2J-1-GPR2775 100KR2J-1-GP

1 2

R2776 100KR2J-1-GPR2776 100KR2J-1-GP

R2757

DQ15

1 2

INSTANT_ON#

3

USBDET_CON#

3

DATA_RECOVERY#

3

KBC Nuvoton NPCE795

QUEEN 15

Tuesday, January 04, 2011

3D3V_AUX_KBC

RN2707

1 23

D2705

1

DY

ECSMI#_KBC

3

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

A00

R2760

ECSMI#_KBC

1 2

0R0402-PAD-2-GP

3D3V_AUX_KBC

0R2J-2-GP

BAT54CPT-GP

MEDIA_BTN1#

1

83.R2003.E81

DN15

2ND = 83.00054.Q81

KBC_ON#_R

2

D2706

D2706 BAT54CPT-GP

BAT54CPT-GP

USB_DET#

1

83.R2003.E81

2ND = 83.00054.Q81

KBC_ON#_R

2

D2707

BAT54CPT-GP

MEDIA_BTN2#

1

83.R2003.E81

2ND = 83.00054.Q81

KBC_ON#_R

2

D2708

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

27 108

1

EC_AGND

of

2.75V100.0K

2.48V100.0K

2.24V

2.0V

1.87V

1.65V

1.204V

A00

5

SSID = Thermal

1119 X02 Modify: Change U2801,U2804,U2805 VCC power to 3D3V_DAC_S0 from 3D3V_S0.

D D

R2808

R2808 NTC-100K-8-GP

C C

B B

NTC-100K-8-GP

3D3V_DAC_S0

12

C2802

SCD1U10V2KX-5GP

12

C2806

C2806 SC470P50V3JN-2GP

1

SC470P50V3JN-2GP

DY

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

12

2ND = 84.03904.P11

3

84.03904.L06

Q2801

PMBS3904-1-GP

2

2.System Sensor, Put on palm rest

Thermal sensor P2800

P2800_DXP

12

C2807

C2807 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

P2800_DXN

1117 X02 Modify: Rename U2801&U2804 pin 8 to THERM_SYS_SHDN#_OTZ from THERM_SYS_SHDN#.

4

12

R2803

P2800A1

107KR2F-GP

87.1 Degree

ADJ

12

P2800A1

R2804

R2804 226KR2F-GP

226KR2F-GP

SCD1U10V2KX-5GP

THERM_SYS_SHDN#_OTZ

1.H/W T8 Shutdown

12

C2805

P2800A1

P2800EA1-GP

5

VCC

6

DXP

7

DXN

8

OTZ

U2801

74.02800.A71

3

A00 1227

1111 X02 Modify: ADJ&ADJ_VGA power source change to 3D3V_DAC_S0 from 3D3V_S0 to solve T8 shut down issue.

1227 A00 Modify: If stuff P2800EA1 then must stuff R2803,R2804,C2805 but if stuff P28003B0 should be unstuff.

TDR TDL

GND

ADJ

4 3 2

ADJ

1

SYS_THRM 27 CPU_THRM 27

FAN_TACH127

AFTP2801AFTP2801 AFTP2802AFTP2802

1117 X02 Modify: Add R2805 0hm between THERM_SYS_SHDN#_OTZ and THERM_SYS_SHDN#.

PURE_HW_SHUTDOW N#27,36,86

0705 Modify: R2802 change to 0ohm 0402 from short pad and default un-stuff.

1 2

R2807 0R0402-PADR2807 0R0402-PAD

FAN_TACH1_C

1

FAN_VCC

1

EMI/ESD

FAN_VCC

X02 1118

2

Fan controller P2793

U2802

R2802 0R2J-2-GP

1 2

DY

5V_S0

FAN1_DAC27

*Layout* 10 mil

For linear FAN

0628 Modify: Stuff R2712 and Removed R2805.

FAN_TACH1_C

*Layout* 15 mil

12

C2809

0724 Modify: Removed C2808 0.1uF.

SC4D7U6D3V3KX-GP

R2805

THERM_SYS_SHDN#_OTZ

12

C2811

DY

R2805

1 2

Q2802

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

FAN_VCC

A00 1224

0R2J-2-GP

S

G

U2802

FON#

1

FON#

2

VIN

3

VO

4

VSET

G991P11U-GP

74.00991.031

2nd = 74.02793.A31

3rd = 74.05606.A71

0614 Modify: Change FAN1 connector part number to

20.D0210.103 base on ME EMN and DXF. 0712 Modify: Change FAN1 part number to 20.F1639.004 from 20.D0210.103 base on latest EMN and DXF.

21

D2802

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

A00 1228

THERM_SYS_SHDN#

1

8

GND

7

GND

6

GND

5

GND

3

FAN_VCC

12

C2810

DY

SC2200P50V2KX-2GP

3D3V_S0

0709 Modify: Removed R2811 and connect 3D3V_S0 to Q2802.G directly.

2 1

0831

2nd = 20.F1841.003

1110 X02 Modify: Add 2nd 20.F1841.003 on FAN1 from ME updated connector list.

12

R2809

R2809 100KR2J-1-GP

100KR2J-1-GP

5V_S03D3V_DAC_S0

12

C2803

5

4

FAN1

FAN1 ACES-CON3-11-GP

ACES-CON3-11-GP

20.F0772.003

12

C2804

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

12

EC2801

DY

SCD1U16V2KX-3GP

A00 1228 Cancel VGA Thermal sensor P2800 circuit

A A

5

4

3

X02 1111

A00 1228 un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805

1 2

THERM_SYS_SHDN#

20101019 X01: Reserve U2804 for PURE_HW_SHUTDOWN# test. 20101020 X01: Reserve R2810 to 3D3V_S0 and R2811 to GND for HYST.

1111 X02 Modify: ADJ&ADJ_VGA power source change to 3D3V_DAC_S0 from 3D3V_S0 to solve T8 shut down issue.

24K3R2F-1-GP

R2806

DY

1 2

R2812 0R2J-2-GP

2

SCD1U10V2KX-5GP

1 2

DY

U2805

SET GND OUT#3HYST

G709T1UF-GP

74.00709.A7F

VCC

DY

Title

Thermal P2800/Fan Controllor P2793

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

1111 X02 Modify: Reserved G709T1UF for T8 solution sync with DN13.

U2805_5U2805_1

5 4

DY

QUEEN 15

R2801

12

DY

12

U2805_4

DY

0R2J-2-GP

DY

150R2F-1-GP

C2817

C2817 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_DAC_S0

R2810

12

DY

R2811

0R2J-2-GP

12

Hysterisis: 10C for HYST= VCC 2C for HYST=GND

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_DAC_S0

A00 1224

of

28 108

A00

5

SSID = AUDIO

D D

Close to codec

12

C2903

1 2

SC1U6D3V2KX-GP

C C

3D3V_S0

12

R2908

R2908 10KR2J-3-GP

10KR2J-3-GP

AMP_MUTE# AUD_VREFOUT_B HDA_CODEC_BITCLK

12

C2923

SC1U10V2KX-1GP

B B

12

C2907

DY

SC4D7P50V2CN-1GP

For EMI

C2902

C2904

1 2

SCD1U10V2KX-5GP

AUD_DMIC_CLK AUD_DMIC_IN0

12

EC2901

EC2902

SC22P50V2JN-4GP

1122 X02 Modify: change R2920,R2921 to 22ohm from 0ohm and stuff EC2901,EC2902 22p from EMC Neo updated.

HDA_CODEC_SDOUT21 HDA_CODEC_BITCLK21

HDA_SDIN021

HDA_CODEC_SYNC21 HDA_CODEC_RST#21

SCD1U10V2KX-5GP

A00

AUD_DMIC_IN049 AUD_DMIC_CLK49

20101220 R2920 R2921 for change to parallel resistor

1 2 3

SRN22J-7-GP

AUD_PC_BEEP Trace width>15 mils

4

AMP_MUTE#27

Close to codec

AUD_DVDDCORE

12

C2901

C2901 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

AUD_DMIC_CLK_R AUD_DMIC_IN0_R3D3V_S0 HDA_CODEC_SDOUT HDA_CODEC_BITCLK HDA_CODEC_SDIN0

R2901

1 2

33R2J-2-GP

0707 Modify: updated U2901 part number from data base.

HDA_CODEC_SYNC HDA_CODEC_RST# AUD_PC_BEEP

2010/06/30 Change to 92HD87 (71.92H87.A03)

RN2902

AUD_PC_BEEP

AUD_DMIC_IN0_R

4

AUD_DMIC_CLK_R

C2912 SCD1U10V2KX-5GPC2912 SCD1U10V2KX-5GP C2913 SCD1U10V2KX-5GPC2913 SCD1U10V2KX-5GP

G2901

G2901 DUMMY-C2

DUMMY-C2

1 2

AMP_MUTE#

U2901

1

DVDD_LV

2

DMIC_CLK/GPIO_1

3

DMIC_0/GPIO_2

4

SDATA_OUT

5

BITCLK

6

SDATA_IN

7

DVDD

8

SYNC

9

RESET#

10

PCBEEP

92HD87B1A5NDGXTBX8-GP

12 12

+PVDD

39

38

40

41

EAPD

PVDD

THERMAL_PAD

71.92H87.A03

SENSE_A11SENSE_B12PORTF_L13PORTF_R14PORTC_L15PORTC_R16VREFFILT17CAP218VREFOUT_A19VREFOUT_C

AUD_SENSE_A

AUD_SENSE_B

SB_SPKR_R KBC_BEEP_R

3

AUD_SPK_R+ AUD_SPK_RAUD_SPK_LAUD_SPK_L+

+AVDD

AUD_VREG

33

36

34

37

31

32

35

PVSS

PVDD

AVDD2

PORTD_-L

PORTD_-R

PORTD_+L

PORTD_+R

AUD_PC_BEEP

120KR2J-L-GP

R2910 470KR2J-2-GPR2910 470KR2J-2-GP

AUD_CAP2

AUD_VREFFLT

R2909

1 2 1 2

VREG/+2_5V

PORTB_R

PORTA_R

20

AUD_VREFOUT_B

CAP+

CAP-

AVSS2

PORTB_L

AVSS2

PORTA_L

AVDD1

From SB

From EC

AUD_SPK_R+ 58 AUD_SPK_L- 58

30 29 28

V-

27 26 25 24 23 22 21

HDA_SPKR 21

KBC_BEEP 27

AUD_SPK_R- 58 AUD_SPK_L+ 58

PUMP_CAPP

PUMP_CAPN AUD_V_B

AUD_HP1_JACK_R AUD_HP1_JACK_L

AUD_EXT_MIC_R AUD_EXT_MIC_L

+AVDD

C2905

1 2

SCD1U10V2KX-5GP

C2914

C2914 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

1 2

R2906 60D4R2F-GPR2906 60D4R2F-GP

1 2

R2905 60D4R2F-GPR2905 60D4R2F-GP

1 2

C2922 SC1U10V3KX-3GPC2922 SC1U10V3KX-3GP C2921 SC1U10V3KX-3GPC2921 SC1U10V3KX-3GP

Put C2921 and C2922 close to codec

0707 Modify: Change R2911,R2914,R2917 change to 0ohm 0603 from short pad. 0726 Modify: Removed all of AUD_AGND and R2911,R2914,R2917.

2

R2902

1 2

0R0603-PAD

C2906

SC1U10V2KX-1GP

0R0603-PAD

12

CLOSE TO CODEC

12 12

5V_S0 +PVDD

1 2

AUD_HP1_JACK_R2 82

AUD_HP1_JACK_L2 82 MIC_IN_R 82

MIC_IN_L 82

12

C2908

SCD1U10V2KX-5GP

AUD_CAP2 AUD_VREFFLT AUD_V_B AUD_VREG

12

C2909

SC1U10V2KX-1GP

12

C2917

1

1 2

C2910

SC4D7U6D3V3KX-GP

1 2

SC10U6D3V5MX-3GP

12

C2918

SC10U6D3V5MX-3GP

R2903

R2903 0R0603-PAD

0R0603-PAD

R2904

R2904 0R0603-PAD

0R0603-PAD

12

Close to codec

0719 Modify: Move RN2901 to closed AUDIO CODEC from speaker connector.

0,&,1

AUD_VREFOUT_B

1

23

RN2901

SRN4K7J-8-GP

4

5V_S0

12

C2915

C2916

SC10U6D3V5MX-3GP

SC1U6D3V2KX-GP

$]DOLD,)(0,

HDA_CODEC_SDOUT

12

R2912

R2912 47R2J-2-GP

47R2J-2-GP

DY

PCH_AZ_CODEC_SDOUT1

A A

12

C2920

DY

SCD1U10V2KX-5GP

5

AUD_SENSE_A

+AVDD

12

R2915

R2915 2K49R2F-GP

2K49R2F-GP

12

C2919

C2919 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

Close to Pin13

4

R2913

1 2

20KR2F-L-GP

R2919

39K2R2F-L-GP

AUD_HP1_JD# 82

AUD_SENSE_B

12

EXT_MIC_JD# 82

Close to Pin14

3

+AVDD

12

R2916

R2916 2K49R2F-GP

2K49R2F-GP

R2918

R2918 20KR2F-L-GP

20KR2F-L-GP

2

MIC_IN_L82

MIC_IN_R82

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Audio Codec 92HD87B1

Taipei Hsien 221, Taiwan, R.O.C.

QUEEN 15

of

29 108Tuesday, January 04, 2011

1

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

30 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

31 108Tuesday, January 04, 2011

A00

5

D D

4

3

2

1

SSID = SDIO

48MHz clock input trace of characteristic impedance (Zo) must be 50

¡Ó15%.

ٝٝٝٝ

CLK_PCH_48M20

PCH GPIO67(48M) confirm with SW

C C

3D3V_S0

MAX 0.4A

3D3V_CARD_S0

12

DY

C3204

C3203

SCD1U10V2KX-4GP

1 2

C3204

SC4D7U6D3V3KX-GP

C3201

RREF

1 2

DY

SC100P50V2JN-3GP

R3201

1 2

6K2R2F-GP

USB_PN5_R USB_PP5_R

V18

12

C3202

C3202 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2 3 4 5 6

25

RREF DM DP 3V3_IN CARD_3V3 V18

GND

23

24

CLK_IN

XD_CD#7SP18SP29SP310SP411SP5

The maximum range of the PMOS output current

1. xD-Picture Card: 250mA

B B

2. SD/MMC Card: 250mA

3. MS/MSPRO/Duo-HG: 250mA

XD_D7 SP14 SP13 SP12 SP11

U3201

U3201 RTS5138-GR-GP

RTS5138-GR-GP

22

SP1119SP1220SP1321SP14

SP10

XD_D7

GPIO0

SP9 SP8 SP7 SP6

71.05138.003

12

SP5 SP4 SP3 SP2 SP1 XD_CD#

XD_D7 74 SP14 74 SP13 74 SP12 74 SP11 74

18 17 16 15 14 13

SP10 SP9

SP8 SP7 SP6

SP5 74 SP4 74 SP3 74 SP2 74 SP1 74 XD_CD# 74

SP10 74 SP9 74

SP8 74 SP7 74 SP6 74

3D3V_CARD_S0

12

C3206

C3206 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C3207

SC4D7U6D3V3KX-GP

Close to chip

The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout with differential characteristic impedance (Zdiff) is 90£[¡Ó

POWER TRACE

1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum).

2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum).

3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum). Keep the trace routing lengths as short as possible.

4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum).

5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace.

USB_PP518

10%

R3211

1 2

0R0402-PAD-2-GP

A00 1229

USB_PP5_R

0917 X01 Modify: stuff TR3201 and un-stuff R3211,R3210 at X01 stage from EMC Neo suggestion.

6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.

7.It is recommended that use of ferrites bead on power trace.

8.Via size: Pad>=32 mils, Finished hole>=16 mils.

A A

5

4

3

USB_PN518

R3210

1 2

0R0402-PAD-2-GP

2

USB_PN5_R

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Card Reader-RTS5138

Size Document Number Rev

A3

Date: Sheet of

Date: Sheet

Card Reader-RTS5138

Taipei Hsien 221, Taiwan, R.O.C.

QUEEN 15

32 108Tuesday, January 04, 2011

1

A00

of

A00

A

4 4

3 3

B

C

D

E

(Blanking)

2 2

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

E

of

33 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

34 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

35 108Tuesday, January 04, 2011

A00

5

0628 Modify: Removed R3609,R3610,R3613,C3613 and Stuff R3614.

IMVP_PWRGD27,42

SSID = Reset.Suspend

D D

A00 1228 stuff Q3603

S0_PWR_GOOD19,27

PS_S3CNTRL

ROSA Run Power

15V_S5

C C

3D3V_AUX_S5

R3606

1 2

2nd = 84.DM601.03F

B B

PM_SLP_S3#19,27,37,47,75

RUN_ENABLE

PS_S3CNTRL

100KR2J-1-GP

Q3602

2N7002KDW-GP

84.2N702.A3F

5

6

123 4

GGDD

S

PS_S3CNTRL 37

S

R3604

R3604 100KR2J-1-GP

100KR2J-1-GP

1 2

4

Q3603

G

S

2N7002K-2-GP

3

D3602

BAS16-6-GP

83.00016.K11

2ND = 83.00016.F11

R3605

1 2

10KR2J-3-GP

R3607

1 2

10KR2J-3-GP

A00

2

1

R3614

1 2

0R0402-PAD-2-GP

SCD01U50V2KX-1GP

D

84.2N702.J31

2nd = 84.2N702.031

0628 Modify: Utilize D3602 Diode instead of U3603 AND GATE for SYS_PWROK sequnece control.

5V_RUN_ENABLE

3.3V_RUN_ENABLE

SCD01U50V2KX-1GP

Rds(on) = 18.5mOhm

2nd = 84.08882.037

5V_S5 5V_S0

12

C3608

C3608 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

Rds(on) = 18.5mOhm AO4468 MAX 11.6A

2nd = 84.08882.037

3D3V_S5

12

C3605

C3605 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

0615 Modify: Removed R3626,R3628 0ohm 0805 Resistor, they are unnecessary for this power rail. Removed R3627,R3629 0ohm 0805 Resistor for 1D5V_DDR_S0.

SYS_PWROK

12

C3612

DY

Power Sequence

AO4468 MAX 9A

84.04468.037

AO4468-GP

6

D

7

D

8

D

U3601

84.04468.037

AO4468-GP

GD

D

D D

D

U3602

GD S

S S

S

6 7 8

3

SYS_PWROK 19

45

GD

3

S

2

S

1

S

3D3V_S0

45 3 2 1

+5V_RUN Comsumption Peak current 7.73A

12

C3603

C3603 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

+3.3V_RUN Comsumption Peak current 8.14A

12

C3604

C3604 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

5V_S0

3D3V_S0

2

1D05V_VTT

H_PWRGD_R

R3601

DY

12

R3602

1 2

DY

200KR2J-L1-GP

3D3V_S0

12

DY

EC3601

1KR2J-1-GP

2ND = 83.00016.F11

83.00016.K11

BAS16-6-GP

2

1

D3601

1 2

R3603 1KR2J-1-GPR3603 1KR2J-1-GP

0621 Modify: Change R3603 to 1K from 2K 0402.

0719 Modify: Reserved EC3601 0.1uF near C3604 for EMC NEO suggestion.

SCD1U50V3KX-GP

H_CPUPWRGD5,22

3V_5V_EN41

0723 Modify: Default stuff R3622 PH Resistor to fix Annie demo board abnormal issue from Annie team updated.

R3622

12

56R2J-4-GP

C3602

3

B

DY

12

DY

SCD1U10V2KX-5GP

E

Q3601

CHT2222APT-GP

C

1

H_THERMTRIP# 5,22

PURE_HW_SHUTDOW N# 27,28,86

S5_ENABLE 27

1.5V_RUN for VGA Comsumption Peak current 7.39A

+1.5V_RUN_CPU Comsumption Peak current 3A

+1.5V_RUN for Mini-Card Comsumption Peak current 1A

A A

5

R3630

1 2

SCD01U50V2KX-1GP

4

1D5V_S3 1D5V_S0

TPCA8062-H-GP MAX 28A Rds(on) = 4.1~5.4m OHM

U3606

D

8

D

7

D

6

TPCA8062-H-GP

1.5V_RUN_ENABLE

10KR2J-3-GP

C3610

12

TPCA8062-H-GP

84.08062.037

2nd = 84.00460.037

3rd = 84.00312.037

0713 Modify: Change U3606 part number to 84.08062.037 from 84.04468.037. 0827 Add 2nd and 3rd.

S

1

S

2

S

3

GD

45

1D5V_S0

MAX Current ? mA Design Current ? mA

Total= 11.39A

12

C3609

C3609 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

Power Plane Ena b le

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

36 108

1

A00

5

Close to CPU

D D

S3 Power Reduction Circuit Processor VREF_DQ Implementation

M_VREF_DQ_DIMM0

R3708 0R0402-PADR3708 0R0402-PAD

4

1 2

0706 Modify: Removed Q3707,R3717 and connect RUN_ENABLE to Q3708.G directly same as EV board.

+V_SM_VREF

R3707

R3707 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q3708

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

G

RUN_ENABLE

R3705

R3705 100KR2J-1-GP

100KR2J-1-GP

1 2

3

+V_SM_VREF_CNT 9

2

Close to DIMM S3 Power Reduction Circuit SM_DRAMPWROK

1D5V_S00D75V_S0

12

R3703

R3703 22R2J-2-GP

22R2J-2-GP

Q3701_D

D

S

G

PS_S3CNTRL36

2

Q3701

Q3701 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

PS_S3CNTRL

G

12

DY

Q3702_D

D

DY

R3704

R3704 220R2J-L2-GP

220R2J-L2-GP

0629 Modify0629 Modify

S

Q3702

Q3702 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

1

C C

S3 Power Reduction X01 20091111

5

2N7002K-2-GP

G

D

S

Q3704

84.2N702.J31

2ND = 84.2N702.031

PM_SLP_S3#19,27,36,47,75

Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK

3D3V_S0

PUSH PULL

U3701

1 2 3

TC7SZ08FU-2-GP

73.7SZ08.EAH

2nd = 73.01G08.L04

3rd = 73.7SZ08.DAH

5

VDDPWRGOOD_R

4

0709 Modify:

U3701 change to OD type 73.01G09.AAH.

0723 Modify:

Change U3701 to push pull type 73.01G08.L04.

R3720 change to 910ohm 0402.

R3719 change to 750ohm 0402.

default un-stuff R3702.

4

0D75V_EN

A00

1 2

DY

R3716 22R2J-2-GP

DY

1D5V_S0

CEKLT V1.0: PCH to 1K,CUP to 200R

12

R3702

200R2F-L-GP

DY

R3719

1 2

910R2F-GP

3D3V_S0

12

R3713

PS_S3CNTRL36

200R2F-L-GP

0D75V_EN

X02 1111

0730

B B

0709 Modify: Change U3701 pin1,5 to 3D3V_S0 from 3D3V_S5.

PM_DRAM_PWRGD5,19

0920

A A

R3717

PM_DRAM_PWRGD5,19

1 2

0827

SM_DRAMPWROK must have a maximum of 15ns rise or fall time over VDDQ * 0.55¡Ó 200mV and the edge must be monotonic

5

DY

0R2J-2-GP

VDDPWRGOOD_R

1.05VTT_PWRGD 45,48

12

R3710

0R0402-PAD-2-GP

12

C3705

C3705 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

R3720

R3720 750R2F-GP

750R2F-GP

0908 X01 Modify: Stuff Q3704,R3710; un-stuff R3716. U3701 pin2 change to 1.05VTT_PWRGD from RUNPWROK.

0D75V_EN 46

VDDPWRGOOD 5

1110 X02 Modify: Change U3701 1st to 73.7SZ08.EAH;2nd to

73.01G08.L04;3rd to 73.7SZ08.DAH from Sourcer Eason updated.

3

SM_DRAMRST#5

Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK

R3709

1 2

DY

Q3703

Q3703 2N7002K-2-GP

2N7002K-2-GP

S

G

84.2N702.J31

2ND = 84.2N702.031

SCD047U16V2KX-1-GP

2

1D5V_S3

12

R3706

R3706 1KR2J-1-GP

1KR2J-1-GP

0R2J-2-GP

C3703

12

DN15ATI

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

S3 Power Reduction Circuit SM_DRAMRST#

SM_DRAMRST#_D

D

DRAMRST_CNTRL_PCH

Tuesday, January 04, 2011

12

C3702

C3702 SC100P50V2JN-3GP

SC100P50V2JN-3GP

1 2

R3718

1KR2J-1-GP

DRAMRST_CNTRL_PCH 20

ADAPTER

QUEEN 15

DDR3_DRAMRST# 14,15

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

37 108

1

A00

5

4

3

2

1

SSID = PWR.Support

D D

C C

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

DCIN

QUEEN 15

of

38 108Tuesday, January 04, 2011

1

A00

5

4

3

2

1

D D

BATT_SENSE40

C C

BT+

BAT_SCL27,40 BAT_SDA27,40 BAT_IN#27

G3901

GAP-CLOSE-PWR-3-GP

0714 Modify: Merge R3902~R3904 to PRN3901 33ohm.

12

0701 Modify: Removed D3904 ESD Diode on BAT_IN#.

SCD1U50V3KX-GP

1 2 3 4 5

SRN33J-7-GP

C3902

PN3901

12

8 7 6

EC3901

DY

AFTP3902AFTP3902 AFTP3903AFTP3903 AFTP3904AFTP3904 AFTP3905AFTP3905

12

C3901

C3901 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

A00 1224

AFTP3901AFTP3901

EC3902

12

DY

SC10P50V2JN-4GP

1 1 1 1

PBAT_PRES1# PBAT_SMBDAT1 PBAT_SMBCLK1 BT+

KA

DY

PBAT_SMBCLK1 PBAT_SMBDAT1 PBAT_PRES1#

BAT_ALERT

1

PD3902

1SMA18AT3G-GP

Batt Connecter

BATT1

10

1 2

3 4 5 6 7 8 9

11

ALP-CON9-2-GP-U

20.81316.009

2nd = 20.81440.009

3rd = 20.81328.009

DCBATOUT

EC3903

SCD1U50V3KX-GP

EC3903

SCD1U50V3KX-GP

12

1122 X02 Modify: stuff EC3903 0.1uF from EMC Neo suggestion.

For actual location, need to be swap all pin

Close to Batt Connector

B B

BAT_IN#

3

D3902

D3902 BAV99-5-GP-U

BAV99-5-GP-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

A A

5

0930 X01 Modify: Change D3901~D3903 main source to 83.00099.T11 for 83.BAV99.D11 shortage issue.

4

BAT_SDA

3

D3903

D3903 BAV99-5-GP-U

BAV99-5-GP-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

BAT_SCL

3

D3901

D3901 BAV99-5-GP-U

BAV99-5-GP-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

3

3D3V_AUX_KBC

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

BATT CONN

39 108Tuesday, January 04, 2011

1

A00

of

A00

5

SSID = Charger

PU4002

D

AD+

D D

AD+

12

PR4009

316KR3F-2-GP

PR4009

316KR3F-2-GP

0702 Modify: Change PR4014 from 48.7K to 49.9K

C C

B B

This Resistor must be 1% tolerance.

0402 base on power team suggest.

12

PC4010

49K9R2F-L-GP

CHG_AGND

1 2

20KR2J-L2-GP

PC4010

SCD01U50V2KX-1GP

PR4001

PR4025

12

DY

0625 Modify: Reserved EC4003,EC4004 on DC_IN_D&PWR_CHG_ACOK for EMC NEO suggestion. 0719 Modify: Reserved EC4005 0.1uF near PR4004 for EMC NEO suggestion. Reserved EC4008 0.1uF near PC4017 for EMC NEO suggestion.

PR4014

AD_IA27

8

D

7

D

6

AO4407A-GP

84.04407.F37

2nd = 84.04835.H37

PR4004

10KR2J-3-GP

DC_IN_D

1 2

PQ4001

PWR_CHG_ACOK

3 4 2 1

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

0818

0827

AC_OK

0720 Modify: Change PR4001 to 20K from 0ohm base on power team Brian updated.

12

PR4021

4K7R2J-2-GP

12

PC4024

8K45R2F-2-GP

SC220P50V2JN-3GP

1 2

PC4021

PC4021 SC150P50V2JN-3GP

SC150P50V2JN-3GP

PWR_CHG_FBO1

12

PC4026

DY

SCD1U50V3KX-GP

Id=-12A Qg=-25nC Rdson=10~38mohm

S

1

S

2

S

3

GD

45

AD+_G_2

5 6

PR4033

1 2

20R5F-1GP

3D3V_AUX_KBC

12

PC4001

PC4001 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

CHG_AGND

BAT_SCL27,39

BAT_SDA27,39

PR4022

PR4022 200KR2F-L-GP

200KR2F-L-GP

1 2

PC4022

SC2200P50V2KX-2GP

12

PC4027

SCD01U50V2KX-1GP

SC56P50V2JN-2GP

DY

PR4526_01

12

0720 Modify: Add AD_IA_HW related circuit from TOM suggestion.

PR4003

100KR2J-1-GP

2N7002K-2-GP

PR4005

AD+_G_1

1 2

10KR2F-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

A00 1222

AD_IA_HW27

1 2

0707 Modify: Change PR4012 change to 0ohm 0402 from short pad.

PG4007 GAP-CLOSE-PWR-3-GPPG4007 GAP-CLOSE-PWR-3-GP

PG4008 GAP-CLOSE-PWR-3-GPPG4008 GAP-CLOSE-PWR-3-GP

PR4026

PR4026 7K5R2F-1-GP

7K5R2F-1-GP

PC4025

1 2

DY

PC4028

SCD01U50V2KX-1GP

1 2

0R0402-PAD-2-GP

PC4003

SCD47U50V5KX-1GP

PR4012

1 2

0R0402-PAD

12

1 2

12

PC4029

0917 X01 Modify: Change PR4027 to 0R0402 short pad from 0ohm.

84.2N702.J31

2ND = 84.2N702.031

EMI/ESD

DC_IN_D PWR_CHG_ACOK

A A

EC4004

1 2

DY

SC4D7P50V2CN-1GP

1 2

DY

5

EC4003

SC4D7P50V2CN-1GP

AD+ BT+

EC4005

SCD1U50V3KX-GP

EC4005

SCD1U50V3KX-GP

12

DY

AD_IA_HW227

EC4008

SCD1U50V3KX-GP

EC4008

SCD1U50V3KX-GP

12

4

A00 1222

PQ4003

PQ4003_G

PR4034

PWR_CHG_DCIN PWR_CHG_ACIN

PWR_CHG_ACOK

PWR_CHG_SCL

PWR_CHG_SDA

CHG_AGND

PWR_CHG_VICM PWR_CHG_FBO

PWR_CHG_EAI PWR_CHG_EAO PWR_CHG_REF

PWR_CHG_CE

PR4027

PR4027 0R0402-PAD

0R0402-PAD

12

DY

SC1U6D3V2KX-GP

PQ4004

2N7002K-2-GP

A00 1222

PR4037

1 2

0R0402-PAD-2-GP

PWR_CHG_REF

4

PQ4003_D

300KR2F-L-GP

D

S

G

CHG_AGND

22

2

11

13

10

9

14

8

6 5 4 3 7

12

PC4030

BQ24745RHDR-GP

SCD1U10V2KX-5GP

PQ4004_D

D

G

PQ4004_G

CHG_AGND

A00 1222

12

PR4035

A00 1222

12

PR4031

PR4031 150KR2F-L-GP

150KR2F-L-GP

CHG_AGND

DCIN ACIN VDDSMB

ACOK

SCL

SDA

NC#14

VICM

FBO EAI EAO VREF CE GND

PU4001

S

PR4011

10KR2F-2-GP

GAP-CLOSE-PWR-3-GP

PWR_CHG_REF

12

PR4047

PR4047 174KR2F-GP

174KR2F-GP

0917 X01 Modify: Change PR4008,PR4010 to 0R0402 short pad from 0ohm.

ICREF

1

ICREF

GND

29

12

CHG_AGND

PR4036

PR4036 76K8R2F-GP

76K8R2F-GP

A00 1222

0916 X01 Modify: Reserved PQ4004,PR4036,PR4037 for AD_IA_HW2 function.

ICREF

A00 1222

1 2

PC4002

PC4002 SCD1U50V3KX-GP

SCD1U50V3KX-GP

CHG_AGND

CSSP

CSSN

ICOUT

BOOT VDDP

UGATE

PHASE

LGATE

PGND CSOP CSON

NC#16

VFB

PR4029

1 2

0R0402-PAD

PG4002

28

27 26

25 21

24

23

20

19 18 17

16

15

A00 1222

AC_OK

12

AC_OK 27

AD+_TO_SYS

PR4002

1 2

D01R2512F-4-GP

12

DY

PR4007

PR4007 0R2J-2-GP

0R2J-2-GP

PR4533_02

12

PR4008

PR4008 0R0402-PAD

0R0402-PAD

PWR_CHG_CSSP

SCD1U50V3KX-GP

PWR_CHG_CSSN PWR_CHG_ICOUT

PWR_CHG_BOOT PWR_CHG_VDDP

PWR_CHG_UGATE

PWR_CHG_PHASE

PWR_CHG_LGATE

PWR_CHG_CSOP

PWR_CHG_CSON

PWR_CHG_VFB

DY

CHG_AGND

3

12

PG4003

GAP-CLOSE-PWR-3-GP

PR4524_03

12

PR4010

PR4010 0R0402-PAD

0R0402-PAD

PC4005

1 2

PWR_CHG_BST1

PR4017

1 2

0R0603-PAD

PR4018

1 2

0R0603-PAD

PR4028

1 2

0R0402-PAD

12

PC4032

DY

CHG_AGND

SCD1U25V2KX-GP

0701 Modify: Change PQ4002 to single 2N7002.

AC_IN# to KBC

AC_IN#27

SCD1U10V2KX-5GP

3

0719 Modify: Reserved EC4006 0.1uF near PR4002 for EMC NEO suggestion. 0719 Modify:

DCBATOUT

EC4007

EC4006

SCD1U50V3KX-GP

EC4006

SCD1U50V3KX-GP

12

0723 Modify: Removed PR4038 PH.

H_PROCHOT#5,27,42

A00 1222

PR4032

0R0402-PAD-2-GP

PC4004

1 2

SCD1U50V3KX-GP

CHG_AGND

PD4001

K A

SD103AWS-1-GP

1 2

PC4012

PC4012 SCD1U50V3KX-GP

SCD1U50V3KX-GP

1 2

DY

PC4014

PC4014 SC220P50V2JN-3GP

SC220P50V2JN-3GP

1 2

PC4020

SCD1U50V3KX-GP

CHG_AGND

BATT_SENSE 39

12

PR4030

1K8R6J-GP

PC4033

PU4004

12

Id=12A Qg=3.8nC Rdson=24~30mohm

12

DY

PR4013

PC4023

12

DY

33R3J-2-GP

CHG_AGND

1 2

PC4011

PC4011 SCD1U50V3KX-GP

SCD1U50V3KX-GP

83.1R504.A8F

2nd = 83.1R504.B8F

DY

84.00412.037

2nd = 84.08061.A37

1 2

SCD1U50V3KX-GP

Q4001

D

DY

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

Reserved EC4007 0.1uF near PG4006 for EMC NEO suggestion.

SCD1U50V3KX-GP

1 2

PG4001

12

PC4006

12

PC4013

PC4013 SC3300P50V3KX-1GP

SC3300P50V3KX-1GP

1 2

PG4004

PG4006

GAP-CLOSE-PWR-3-GP

PWR_DCBATOUT_CHG

678

DDD

SC1U6D3V2KX-GP

GD

123

4 5

84.00412.037

2nd = 84.08061.A37

PWR_CHG_LX1

678

DDD

GD

123

4 5

PR4023

PR4023 0R0402-PAD

0R0402-PAD

0707 Modify: Change PR4023 change to 0ohm 0402 from short pad.

0721 Modify: Change PU4005 to 84.00412.037 from power team Brian updated.

CHG_AGND

S

AC_OK

G

2

1 2

PG4005

GAP-CLOSE-PWR-3-GP

PWR_DCBATOUT_CHG

12

PC4007

PU4004

SSS

SIS412DN-T1-GE3-GP

1 2

68.5R610.10X Id=5.5A DCR=39~42mohm

PU4005

Size=6.6X7.3X3

SSS

84.00412.037 Id=12A

SIS412DN-T1-GE3-GP

Qg=3.8nC Rdson=24~30mohm

PR4020

1 2

0R0402-PAD

2

1

PU4003

S

D

S

1 2

AD+

12

PR4006

470KR2J-2-GP

12

PC4009

PC4008

SCD1U50V3KX-GP

SC10U25V6KX-1GP

PL4001

IND-5D6UH-48-GP-U1

68.5R610.10X

2nd = 68.5R610.10U

PWR_CHG_CSOP_1

Charger Current=1.4~3.6A

0603 Modify: change PL4001 to 68.5R610.10X.

BT+_R

PR4019

1 2

D01R2512F-4-GP

1 2

PG4010

GAP-CLOSE-PWR-3-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

3 4 5

Id=-12A Qg=-25nC Rdson=10~38mohm

12

EC4001

DY

SC2200P50V2KX-2GP

1 2

PG4009

GAP-CLOSE-PWR-3-GP

PG4009_1

PR4024

PR4024 0R0402-PAD

0R0402-PAD

1 2

DY

1 2

CHG_AGND

CHARGER BQ24745

QUEEN 15

D

S

S S

S GD

GD

AO4407A-GP

84.04407.F37

2nd = 84.04835.H37

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

8

D

7

D

6

12

EC4002

SCD1U25V2KX-GP

12

PC4015

PC4016

SC10U25V6KX-1GP

0629 Modify

BT+

PC4031

0603 Modify: Add PC4034 to 78.10622.52L.

SCD1U50V3KX-GP

1

BT+

12

PC4017

12

PC4034

SC10U25V6KX-1GP

40 108

12

PC4018

SC10U25V6KX-1GP

of

PC4019

SCD1U50V3KX-GP

A00

A

SSID = PWR.Plane.Regulator_5v3p3v

B

C

D

E

PG4101

GAP-CLOSE-PWR-3-GP

1 2

PD4104

BZT52C15S-GP

83.15R03.C3F

PWR_5V_DC B ATOUT

PC4116

PC4114

12

SC10U25V6KX-1GP

PL4102

1 2

IND-2D2UH-46-GP-U

68.2R210.20B

12

2nd = 68.2R21B.10J

PR4108

PR4108 2D2R5F-2-GP

2D2R5F-2-GP

PWR_5V_SNUB

12

PC4123

PC4123 SC560P50V-GP

SC560P50V-GP

PR4114

0R2J-2-GP

PC4128

PWR_3D3V_LGAT E2_1

SC1KP50V2KX-1GP

PC4104

12

PD4103

BAT54S-7F-GP

15V_PWR

A K

PC4117

12

SC10U25V6KX-1GP

SCD1U50V3KX-GP

12

DY

PWR_5V_FB1_R

12

DY

SCD1U25V3KX-GP

12

3

1

2

83.00054.Y81

2nd = 83.0R203.081

PC4108_1

0629 Modify

12

PC4107

SC1U25V3KX-1-GP

Design Current = 8A

12.6A<OCP< 14.6A

PG4114

PC4120

GAP-CLOSE-PWR-3-GP

12

SCD1U10V2KX-4GP

12

PR4115

PR4115 33KR2F-GP

33KR2F-GP

12

PR4119

PR4119 21K5R2F-GP

21K5R2F-GP

SCD1U25V3KX-GP

PC4102

12

PD4101_3PD4103_3

0629 Modify0629 Modify

3

1

2

12

PC4108

SCD1U25V3KX-GP

5V_PWR

77.53371.04L

2nd = 77.93371.011

12

PT4104

A00 1224

08040804

SE330U6D3VM-15-GP

PC4103

DY

123

PD4101

PD4101 BAT54S-7F-GP

BAT54S-7F-GP

83.00054.Y81

2nd = 83.0R203.081

5V_S515V_S5

12

SCD1U25V3KX-GP

0719 Modify: Reserved EC417 0.1uF for EMC NEO suggestion.

EC4107

12

SCD1U50V3KX-GP

PC4109

PD4102

PD4102 BAT54-7-F-GP

BAT54-7-F-GP

0810

DCBATOUT

PG4105 GAP-CLOS E -PWRPG4105 GAP-C LOSE-PWR

1 2

PG4106 GAP-CLOS E -PWRPG4106 GAP-C LOSE-PWR

1 2

PG4127 GAP-CLOS E -PWRPG4127 GAP-C LOSE-PWR

1 2

PG4128 GAP-CLOS E -PWRPG4128 GAP-C LOSE-PWR

1 2

0721 Modify: Add PG4127,PG4128 from power team Brian updated.

5V_PWR

5V_S5

PG4107 GAP-CLOSE-P W RPG4107 GAP-CLO S E-PWR

1 2

PG4109 GAP-CLOSE-P W RPG4109 GAP-CLO S E-PWR

1 2

PG4111 GAP-CLOSE-P W RPG4111 GAP-CLO S E-PWR

1 2

PG4115 GAP-CLOSE-P W RPG4115 GAP-CLO S E-PWR

1 2

PG4117 GAP-CLOSE-P W RPG4117 GAP-CLO S E-PWR

1 2

PG4119 GAP-CLOSE-P W RPG4119 GAP-CLO S E-PWR

1 2

PG4121 GAP-CLOSE-P W RPG4121 GAP-CLO S E-PWR

1 2

PG4123 GAP-CLOSE-P W RPG4123 GAP-CLO S E-PWR

1 2

5V_S5

12

DY

0719 Modify: Reserved EC4101~EC4106 0.1uF near PTC4101,PC4119 for EMC NEO suggestion.

12

EC4103

EC4101

EC4103

EC4102

SCD1U50V3KX-GP

PWR_5V_DCBATOUT

PWR_3D3V_LGAT E2

4 4

DCBATOUT

PWR_3D3V_D C BATOUT

PG4102 GAP-CLOS E -PWRPG4102 GAP-C LOSE-PWR

1 2

PG4103 GAP-CLOS E -PWRPG4103 GAP-C LOSE-PWR

1 2

PG4104 GAP-CLOS E -PWRPG4104 GAP-C LOSE-PWR

1 2

3 3

2 2

Design Current = 9.2A

14.5A<OCP< 17A

3D3V_S5

3D3V_PWR

PG4108 GAP-CLOSE-P W RPG4108 GAP-CLO S E-PWR

1 2

PG4110 GAP-CLOSE-P W RPG4110 GAP-CLO S E-PWR

1 2

PG4112 GAP-CLOSE-P W RPG4112 GAP-CLO S E-PWR

1 2

PG4116 GAP-CLOSE-P W RPG4116 GAP-CLO S E-PWR

1 2

PG4118 GAP-CLOSE-P W RPG4118 GAP-CLO S E-PWR

1 2

PG4120 GAP-CLOSE-P W RPG4120 GAP-CLO S E-PWR

1 2

PG4122 GAP-CLOSE-P W RPG4122 GAP-CLO S E-PWR

1 2

PG4124 GAP-CLOSE-P W RPG4124 GAP-CLO S E-PWR

1 2

PG4126 GAP-CLOSE-P W RPG4126 GAP-CLO S E-PWR

1 2

0909 X01 Modify: Change PL4101,PL4102 to 68.2R210.20B from 68.2R210.20Q base on Brian updated. Add 2nd source 68.2R21B.10J on PL4101, PL4102 base on updated 2nd excel file.

3D3V_PWR

77.53371.04L

2nd = 77.93371.011

A00 1224

12

PT4102

SCD1U10V2KX-4GP

PC4119

SE330U6D3VM-15-GP

Mag. 2.20uH 6.5*6.9*3 DCR=18~20mohm Idc=8A, Isat=14A

PR4111

6K65R2F-GP

PR4116

10KR2F-2-GP

PWR_3D3V_D C BATOUT

PC4110

PC4111

12

SC10U25V6KX-1GP

SCD1U50V3KX-GP

68.2R210.20B

PL4101

1 2

IND-2D2UH-46-GP-U

2nd = 68.2R21B.10J

PR4107

PG4113

2D2R5F-2-GP

GAP-CLOSE-PWR-3-GP

12

PC4121

SC330P50V3KX-GP

12

PR4112

PR4112 0R2J-2-GP

0R2J-2-GP

DY

PWR_3D3V_FB 2_R

12

PC4124

PC4124 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

DY

12

PC4112

12

Close to VFB Pin (pin5) Close to VFB Pin (pin2)

0914 X01 Modify: Un-stuff PU4101,PD4105,PR4124, PR4125,PR4101 at X01 stage.

12

PR4124

PR4124 40K2R2F-GP

40K2R2F-GP

DY

PU4101_5

12

PR4125

PR4125 750KR2F-GP

750KR2F-GP

DY

1 1

DY

PU4101

DY

6

2N7002KDW-G P

84.2N702.A3F

2345 1

DCBATOUTDCBATOUT

Vz=5.1V

PWR_5V3D3V_EN 0

PU4101_2

0629 Modify

PD4105

DY

MMPZ5231BPT-GP

83.5R103.E3F

2nd = 83.PDZ51.AVF

1 2 12

PR4101

DY

100KR2F-L1-GP

84.00412.037 Id=12A Qg=3.8nC Rdson=24~30mohm

12

SC10U25V6KX-1GP

678

DDD

SSS

GD

SSS

GD

123

4 5

12

DY

678

DDD

SSS

GD

SSS

GD

123

4 5

PWR_3D3V_SNUB

12

84.07716.037

DY

Id=16A Qg=7.3nC Rdson=13.5~16.5mohm

3D3V_AUX_S5

PWR_5V3D3V_VR EF

3D3V_AUX_S5

0604 Modify: Change PU4103 to 74.8223.A73. 0714 Modify: Change PU4103 to TPS51123 from RT8223MGQW. 0720 Modify: Change PR4105 to 2.2ohm from 0ohm from

power team Brian updated.

0913 X01 Modify: Add 2nd source 84.08061.A37 on PU4102, PU4104 base on Brian updated 2nd soruce excel file.

PU4102

PU4102 SIS412DN-T1-GE3-GP

SIS412DN-T1-GE3-GP

84.00412.037

2nd = 84.08061.A37

PC4115

PWR_3D3V_BOO T1

12

SCD1U25V3KX-GP

PU4106

PU4106 SI7716ADN-T1-GE3-GP

SI7716ADN-T1-GE3-GP

84.07716.037

2nd = 84.08065.B37

1 2

2D2R3-1-U-GP

1 2

DY

PR4109 820KR2F-G P

PWR_5V3D3V_VR EF

SCD22U10V2KX-1GP

12

PR4117

12

DY

0R2J-2-GP

PR4118

1 2

0R0402-PAD

PR4120

12

DY

0R2J-2-GP

PR4121

1 2

0R0402-PAD

PR4123

12

DY

0R2J-2-GP

TONSEL

GND

VREF

VREG3 or VREG5

PR4105

PC4122

PWR_3D3V_BOO T2 PWR_3D3V_U G ATE2 PWR_3D3V_PHASE2 PWR_3D3V_LGAT E2

PWR_3D3V_VOU T2 PWR_3D3V_FB 2

PWR_5V3D3V_EN 0 PWR_3D3V_EN TRIP2

PWR_5V3D3V_T O NSEL

PWR_5V3D3V_SKIPSEL

TPS51123RGER-GP

74.51123.073

3D3V_AUX_S5

GAP-CLOSE-PWR-3-GP

200kHz

300kHz

400kHz

9 10 11 12

7

5

13

6

3

4

14

PG4125

1 2

250kHz

375kHz

500kHz

CH2CH1

PWR_5V_ENT R IP1

PC4105

SC18P50V2JN-1-GP

DCBATOUT

PU4103

VBST2 DRVH2 LL2 DRVL2

VO2 VFB2

EN0 TRIP2 VREF TONSEL

SKIPSEL

VREG3

8

PWR_5V3D3V_VREG3

12

PC4125

SC4D7U25V5KX-GP

DY

PC4101

12

DY

16

VIN

VBST1

DRVH1

LL1

DRVL1

VO1

VFB1

PGOOD

TRIP1

GND GND

ENC

VREG5

17

12

PC4126

SKIPSEL

Operating Mode

12

SC10U25V6KX-1GP

SC10U6D3V5KX-1GP

PWR_3D3V_EN TRIP2

12

PC4113

12

22 21 20 19

24 2

23 1 15 25

18

5V_AUX_S5

12

DY

PC4106

SC18P50V2JN-1-GP

PR4104

147KR2F-GP

SCD01U50V2KX-1GP

0721 Modify: Change PR4106 to 0ohm 0603 from

2.2ohm from power team Brian updated.

PWR_5V_BOOT 1 PWR_5V_UGAT E1 PWR_5V_PHASE1 PWR_5V_LGATE1

PWR_5V_VOUT 1 PWR_5V_FB1

PWR_5V_ENT R IP1

PWR_5V3D3V_EN C

PR4113

PR4113 0R0402-PAD

0R0402-PAD

1 2

PC4127

0701 Modify:

SC22U6D3V5MX-2GP

PC4127 Default un-stuff.

OOA Auto Skip Auto Skip

12

DY

PR4103

187KR2F-GP

0603 Modify: Change PR4103 to 187K from 100K.

0804 Change MOS follow Brian. 0901 PU4104 and PU 4105 horizontally mirror.

PWR_5V_VBST1_1

PR4106

1 2

0R0603-PAD

3D3V_S5

12

PR4110

PR4110 100KR2J-1-GP

100KR2J-1-GP

3V_5V_POK

3V_5V_EN 36

VREF(2V)

ROSA team

0721 Modify: Change PU4104 to 84.04800.D37 from power team Brian updated.

PU4104

SIS412DN-T1-GE3-GP

84.00412.037

2nd = 84.08061.A37

SCD1U25V3KX-GP

SCD1U25V3KX-GP PC4118

PC4118

1 2

PU4105

SI7716ADN-T1-GE3-GP

84.07716.037

2nd = 84.08065.B37

GNDVREG3 or VREG5

PWM only

PR4102

1 2

0R0402-PAD

2nd = 83.15R03.E3F

678

DDD

SSS

GD

SSS

GD

123

4 5

678

DDD

DY

SSS

GD

SSS

GD

123

4 5

DY

SC18P50V2JN-1-GP

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 2.2UH FDVE0630-2R2M=P3 TOKO 21mohm Isat =8.7Arms 68.2R21B.10A O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L H/S: FDSS8884 SO-8/ 23mohm/30mOhm@4.5Vgs/ 84.08884.037 L/S: FDS6690AS SO-8/ 12mohm/15mOhm@4.5Vgs/ 84.06690.E37

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Tuesday, January 04, 2011

Date: Sheet

A

B

C

D

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

5V/3D3V(TPS51123RGER)

QUEEN 15

E

41 108

of

A00

5

SSID = CPU.Regulator

12

PR4208

PR4208 8K06R2F-GP

8K06R2F-GP

PC4208

D D

Only for Dual-core, Qual-core stuff 22KR (64.22025.6DL)

0707 Modify: Removed PR4240 GND to 95831_AGND.

C C

H_CPU_SVIDCLK8

D85V_PWRGD48

Only for Dual-core, Qual-core stuff 18K2R (64.18225.LDL)

B B

A A

A00 1227

0707 Modify: Change all of 9531_AGND to GND for vender suggest.

Place near high side MOSFET of Phase1

DC&QC

5

H_CPU_SVIDDAT8

VR_SVID_ALERT#8

95831_IMON

12

PR4207

PR4207 22KR2F-GP

22KR2F-GP

VSSSENSE

PC4208

PR4237

1 2

SC39P50V2JN-1GP

1 2

PC4211

DUMMY-R2

1 2

SC150P50V2KX-GP

95831_IMONG

12

PR4202

PR4202 22KR2F-GP

22KR2F-GP

VSS_AXG_SENSE

0707 Modify: Updated IMONG and IMON circuit from power team Brian.

0707 Modify: Removed PR4233.

PR4203

1 2

0R0402-PAD

12

PC4203

SCD01U50V2KX-1GP

H_PROCHOT#5,27,40

PR4206

1 2

DUMMY-R2

PC4207

ISEN3

1 2

SC150P50V2KX-GP

DUMMY-C2

PC4230

PR4214_1

1 2

SC560P50V-GP

0921 X01 Modify: Add PR4214,PC4230 from vender suggestion.

0629 Modify

PC4211_2

12

PC4205

PR4231

1 2

0R0402-PAD

PR4204

1 2

0R0402-PAD

12

PC4210

PR4214

1 2

2KR2F-3-GP

PC4202

PC4202 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

1 2

PR4210

1 2

475KR2F-GP

SCD047U25V2KX-GP

1 2

12

3D3V_S0

IMVP_PWRGD27,36

1D05V_VTT

PG4203

1 2

DUMMY-C2

PR4229

NTC-470K-9-GP

3K83R2F-GP

PR4228_1

0629 Modify

PR4205

1 2

8K06R2F-GP

PC4209

1 2

SC39P50V2JN-1GP

PR4209

1 2

PC4210_2

316KR2F-GP

0629 Modify

VCCSENSE8 VSSSENSE8

0920 X01 Modify: Change PR4213 to 3.6K from 3.16K from Brian updated.

4

PC4221

PR4211

1 2

422R2F-2-GP

PR4236

1 2

3K01R2F-3-GP

1D05V_VTT

1 2

SCD1U10V2KX-4GP

12

PR4232

PR4244

75R2F-2-GP

130R2F-1-GP

PR4235 1K91R2F-1-GPPR4235 1K91R2F-1-GP

1 2

PR4201

1 2

75R2F-2-GP

PR4215

1 2

0R0402-PAD

PR4247

1 2

69.60013.141

2nd = 69.60037.021

PR4228

1 2

27K4R2F-GP

PC4206

PC4206 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

PR4212

1 2

499R2F-2-GP

A00 1227

4

PC4221

PC4221_1

0629 Modify

SC680P50V2KX-2GP

0920 X01 Modify: Change PR4236 to 3.01K from 3.32K from Brian updated.

PC4214

Close to CPU

12

PR4234

54D9R2F-L1-GP

1K91R2F-1-GP

DY

12

95831_NTC

0629 Modify

0707 Modify: Stuff PR4247 NTC Resistor.

0629 Modify

95831_COMP 95831_FB

PC4213_1

0629 Modify

PR4213

1 2

2K37R2F-GP

DC&QC

0629 Modify

95831_VWG

0629 Modify

95831_COMPG 95831_FBG

1 2

3D3V_S0

12

PR4230

0629 Modify

95831_PGOODG

95831_SDA 95831_SCLK

IMVP_VR_ON

H_PROCHOT#_C

0629 Modify

PC4204

PC4204 SC47P50V2JN-3GP

SC47P50V2JN-3GP

PC4213

1 2

SC470P50V-2-GP

Only for Dual-core, Qual-core stuff 3K6R(64.36015.6DL)

0721 Modify: Change PR4213 to 3.16K from 2.32K from power team Brian updated.

1 2 3 4 5 6 7 8

9 10 11 12

ISL95831HRTZ-T-GP

SCD22U10V2KX-1GP

VSUM-

SCD22U10V2KX-1GP

PC4219

1 2

SC330P50V2KX-3GP

PC4223

1 2

SC1000P50V3JN-GP-U

PU4201

VWG IMONG PGOODG SDA ALERT# SCLK VR_ON PGOOD IMON VR_HOT# NTC VW

PC4215

1 2

PC4216

1 2

PC4217

1 2

DY

49

48

GND

COMPG

COMP13FB14ISEN3/FB215ISEN216ISEN117VSEN18RTN19ISUMN20ISUMP21VDD22VIN23PROG1

3

PR4216

1 2

2KR2F-3-GP

12

PC4212

PC4212 SCD068U10V2KX-1GP

SCD068U10V2KX-1GP

NTCG

PR4239

1 2

16K5R2F-2-GP

0629 Modify

95831_PROG2

38

45

43

47

46

44

FBG

ISPG

RTNG

VSENG

ISEN3

ISEN2

ISEN1

Only for Dual-core, Qual-core stuff 1K27R (64.12715.6DL)

12

PC4224

SC330P50V2KX-3GP

3

37

42

39

41

40

LGG

PHG

UGG

ISNG

NTCG

PROG2

BOOTG

BOOT2

BOOT1

24

0629 Modify

95831_ISUMN

0721 Modify: Change PC4227 to 33uF from 47uF from power team Brian updated. Change PC4225 to 0.033uF from 0.068uF from power team Brian updated.

A00 1230

PR4217

1 2

845R2F-GP

PG4201

1 2

DUMMY-C2

0721 Modify: Change PR4217 to 1K from 698ohm from power team Brian updated.

PC4231

PR4216_1

SC330P50V2KX-3GP

PC4220

1 2

DY

SC330P50V2KX-3GP

PC4222

1 2

SC1000P50V3JN-GP-U

36 35

UG2

34

PH2

33

VSSP2

32

LG2

31

VDDP

30

PWM3

29

LG1

28

VSSP1

27

PH1

26

UG1

25

0629 Modify

95831_PROG1

0629 Modify

95831_VIN

0629 Modify

95831_VDD

12

PC4226

SC1U10V2KX-1GP

12

PC4227

SCD33U6D3V2KX-1-GP

A00 1227

DC&QC

PR4218

PR4218_2

DUMMY-R2

0629 Modify

1 2

ISPG 44 ISNG 44

1

BOOT2 UGATE2 PHASE2

LGATE2

LGATE1 PHASE1

UGATE1 BOOT195831_VW

TP4202 TPAD14-GPTP4202 TPAD14-GP

BOOTG 44 UGATEG 44 PHASEG 44 LGATEG 44

0901

1

PC4201

2

SCD22U25V3KX-GP

12

PC4225

SCD033U16V2KX-GP

12

2

0921 X01 Modify: Add PR4216,PC4231 from vender suggestion.

VCC_AXG_SENSE 9

VSS_AXG_SENSE 9

0719 Modify: Stuff PR4246 NTC resistor.

PR4246

1 2

NTC-470K-9-GP

69.60013.141

2nd = 69.60037.021

NTC place near high side MOSFET of Phase1

BOOT2 43 UGATE2 43 PHASE2 43

LGATE2 43

95831_PWM3

LGATE1 43

0629 Modify

PHASE1 43 UGATE1 43 BOOT1 43

PR4226

1 2

5K62R2F-GP

PR4225

1 2

0R0402-PAD

PR4224

1 2

1R2F-GP

Change PU4201 VDD power source to 5V_S5 from 5V_S0 to avoid abnormal MVP_PWRGD waveform.

12

PR4241

12

11KR2F-L-GP

12

PWR_VCCCORE1_DCBATOUT

5V_S5

VSUM+ 43

PR4242

PR4242 2K61R2F-1-GP

2K61R2F-1-GP

0629 Modify

PR4242_2

PR4245

PR4245 NTC-10K-27-GP

NTC-10K-27-GP

69.60013.131

2nd = 69.60011.201

PC4218

PC4218 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

2

0921

Place near choke of Phase1

VSUM- 43

PR4220

27K4R2F-GP

PR4222

PR4222 0R0402-PAD

0R0402-PAD

1 2

95831_VDDP

0629 Modify

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

PG4202

12

DUMMY-C2

PR4219

3K83R2F-GP

0629 Modify

PR4220_1

12

PWM3 43

PR4223

1 2

DY

0R2J-2-GP

12

PC4228

ISEN143 ISEN243 ISEN343

ISL95831_CPU_CORE(1/3)

QUEEN 15

Tuesday, January 04, 2011

QUEEN 15

1

0719 Modify: Reserved EC4201~EC4203 0.1uF near PR4246(TOP) for EMC NEO suggestion. 0721 Modify: Removed EC4201~EC4203.

12

5V_S0

PR4243

PR4243 0R0402-PAD

0R0402-PAD

1 2

12

PC4229

SC1U10V2KX-1GP

0719 Modify: Reserved EC4204~EC4207 0.1uF near C1403(TOP),C1507,C1509,C1406, TP_LOCK_LED1 for EMC NEO suggestion.

ISEN1 ISEN2 ISEN3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

VCC_GFXCORE

42 108

1

DY

of

12

EC4209

SCD1U50V3KX-GP

A00

5

84.00462.037 SIR462DP

5V_S0

12

PC4301

SC1U10V2KX-1GP

PR4302

1 2

2D2R3-1-U-GP

D D

PR4301

PU4301

0R0402-PAD

1 2

PWM342

0705 Modify

PWR_VCCCORE3_DCBATOUTDCBATOUT_IMVP7

PG4319

1 2

GAP-CLOSE-PWR

PG4320

1 2

GAP-CLOSE-PWR

PG4321

C C

B B

A A

PG4321

1 2

GAP-CLOSE-PWR

PG4322

1 2

GAP-CLOSE-PWR

PG4323

1 2

GAP-CLOSE-PWR

PG4324

1 2

GAP-CLOSE-PWR

BOOT242

0705 Modify

DCBATOUT_IMVP7

UGATE242 PHASE242 LGATE242

1 2

GAP-CLOSE-PWR

1 2

GAP-CLOSE-PWR

1 2

GAP-CLOSE-PWR

1 2

GAP-CLOSE-PWR

1 2

GAP-CLOSE-PWR

1 2

GAP-CLOSE-PWR

2

PWM

PWR_FCCM

6

FCCM

ISL6208CRZ-TGP-U

84.00462.037 SIR462DP Id=30A, Qg=8.8nC, Rdson=7.9~10 mohm

PR4308

PWR_VCCCORE_BOOT2_1

1 2

2D2R3-1-U-GP

UGATE2 PHASE2 LGATE2

PWR_VCCCORE2_DCBATOUT

PG4311

PG4312

PG4313

PG4314INS43029

PG4315

PG4316

5

2D2R3-1-U-GP

PWR_VCCCORE_BOOT3

SCD22U25V3KX-GP

5

1

VCC

BOOT PHASE

UGATE

LGATE

GND

3

9

SIR462DP-T1-GE3-GP

SCD22U25V3KX-GP

2nd = 84.08059.037

84.00460.037 SIR460DP Id=40A,Qg=16.8nC, Rdson=4.7~6.1mohm

0719 Modify: Change PU4305 part number to 84.00172.037 from

84.07686.037 base on power team Brian suggestion. 0726 Modify: Brian updatede PU4305 change to 84.00462.037.

Id=30A, Qg=8.8nC, Rdson=7.9~10 mohm

PWR_VCCCORE_BOOT3_1

PU4302

12

PC4302

PWR_VCCCORE_PH3

7

PWR_VCCCORE_HG3

8 4

PC4312

84.00460.037

PU4303

QC

84.00460.037

2nd = 84.08059.037

0719 Modify: Change PU4302 part number to 84.00172.037 from

84.07686.037 base on power team Brian suggestion. 0726 Modify: Brian updatede PU4302 change to 84.00462.037.

PU4305

12

PU4306

QC

PWR_VCCCORE_LG3

84.00460.037 SIR460DP Id=40A,Qg=16.8nC, Rdson=4.7~6.1mohm

678

DDD

SSS

GD

SSS

GD

123

4 5

678

DDD

D

DDD

D

QC

SSS

G

123

4 5

4

12

PC4303

678

DDD

SSS

GD

SSS

GD

4 5

678

DDD

G

4 5

QC

84.00462.037

2nd = 84.08064.A37

PU4307

SIR460DP-T1-GE3-GP

84.00460.037

2nd = 84.08059.037

SC4D7U25V5KX-GP

123

SIR462DP-T1-GE3-GP

84.00462.037

2nd = 84.08064.A37

D

PU4304

SIR460DP-T1-GE3-GP

SSS

4 5

123

84.00460.037

2nd = 84.08059.037

12

PC4307

PC4308

SC4D7U25V5KX-GP

678

DDD

D

DDD

D

SSS

G

123

4 5

4

12

PC4304

SC4D7U25V5KX-GP

678

DDD

D

DDD

D

SIR460DP-T1-GE3-GP

SSS

G

123

12

PC4309

SC4D7U25V5KX-GP

PL4302

1 2

L-D36UH-1-GP

68.R3610.20A

2nd = 68.R3610.20C

SIR460DP-T1-GE3-GP

PG4303

1 2

GAP-CLOSE-PWR-3-GP

PWR_VCCCORE_VSUM+_2

10KR2F-2-GP

3K65R2F-1-GP

PWR_VCCCORE3_DCBATOUT

PC4305

SC4D7U25V5KX-GP

PL4301

1 2

L-D36UH-1-GP

68.R3610.20A

2nd = 68.R3610.20C

PG4301

1 2

PWR_VCCCORE_VSUM+_3

1 2

GAP-CLOSE-PWR-3-GP

PWR_VCCCORE_VSUM-_3

PR4306

10KR2F-2-GP

PR4307

3K65R2F-1-GP

PWR_VCCCORE2_DCBATOUT

12

PC4310

SC4D7U25V5KX-GP

0809

PG4304

1 2

PR4309

1 2

DY

1R2F-GP

PR4310

GAP-CLOSE-PWR-3-GP

1 2

DY

1R2F-GP

PR4311

PWR_VCCCORE_VSUM-_2

1 2

1R2F-GP

PR4312

12

PR4313

12

0719 Modify: Change PU4308 part number to 84.00172.037 from

84.07686.037 base on power team Brian suggestion. 0726 Modify: Brian updatede PU4308 change to 84.00462.037.

12

PC4306

PC4306 SC4D7U25V5KX-GP

SC4D7U25V5KX-GP

68.R3610.20A

0.36uH, Idc=20A, Isat=25A DCR=1.4 +/-7% mohm

A00 1224

0809

PG4302

79.33719.20L

2nd = 77.C3371.13L

PR4303

1 2

DY

1R2F-GP

1R2F-GP PR4304

PR4304

1 2

DY

1R2F-GP

1R2F-GP PR4305

PR4305

1 2

1R2F-GP

12

ISEN3 42

12

VSUM+ 42

12

PC4311

0705 Modify

VCC_CORE

SC4D7U25V5KX-GP

PT4303

PT4304

12

ST330U2VDM-4-GP

79.33719.20L

2nd = 77.C3371.13L

ISEN1 42

ISEN3 42

VSUM- 42

ISEN2 42

VSUM+ 42

3

BOOT142

80.3371V.A2L 330uF, 2.5V, B2 ESR=9m£[, Iripple= 3. 073A

12

ISEN1 42

ISEN2 42

VSUM- 42

VCC_CORE

PT4308

ST330U2VDM-4-GP

0705 Modify

PT4309

12

79.33719.20L

2nd = 77.C3371.13L

ST330U2VDM-4-GP

Vcc_core Iomax=53A OCP>97.5A

0705 Modify 0705 Modify

DCBATOUT DCBATOUT_IMVP7

A00 1223 no co-lay

PR4320

1 2

D004R3720F-GP

PR4321

PR4321 10R2F-L-GP

10R2F-L-GP

VENTURA

U4306_VIN+

1 2

PC4319

1 2

VENTURA

A00 1224

79.33719.20L

2nd = 77.C3371.13L

ST330U2VDM-4-GP

HPA00900AIDCNR-GP

74.00900.079

3

VENTURA

SCD1U25V2KX-GP

1

VIN+

VENTURA

U4306

8

Would be instead of INA219 by HPA00900

PR4314

PWR_VCCCORE_BOOT1_1

1 2

2D2R3-1-U-GP

UGATE142 PHASE142

84.00462.037 SIR462DP Id=30A, Qg=8.8nC, Rdson=7.9~10 mohm

LGATE142

PR4322

PR4322 10R2F-L-GP

10R2F-L-GP

VENTURA

U4306_VIN-

1 2

4

2

3

VS

VIN-

GND

3K3R2J-3-GP

SCL5SDA6A07A1

R4344

VENTURA

INA_A0 INA_A1

R4347

R4347 3K3R2J-3-GP

3K3R2J-3-GP

DY

2

12

PC4313

SSS

123

D

SSS

123

2nd = 84.08059.037

SC4D7U25V5KX-GP

84.00462.037

2nd = 84.08064.A37

678

DDD

D

DDD

D

SIR460DP-T1-GE3-GP

PU4310

SSS

G

123

4 5

84.00460.037

SIR462DP-T1-GE3-GP

PC4318

SCD22U25V3KX-GP

PC4318

84.00460.037

2nd = 84.08059.037

PU4308

678

DDD

12

GD

4 5

678

DDD

PU4309

QC

G

4 5

84.00460.037 SIR460DP Id=40A,Qg=16.8nC, Rdson=4.7~6.1mohm

FOR NVIDIA VENTURA

0708 Modify: PR4320 change to BIG SIZE footprint for CPU VENTURA. 0705 Modify: R4346 change to PR4320 4m ohm sense Resistor from 3m ohm.

0705 Modify: Removed R4347 sense Resistor base on VENTURA SPEC.

0705 Modify: Add PR4321,PR4322,PC4319.

3D3V_VGA_S0

0702 Modify: Change U4306 power source to 3D3V_VGA_S0 from 3D3V_S0.

12

C4301

VENTURA

SCD1U10V2KX-5GP

12

R4345

R4345 3K3R2J-3-GP

3K3R2J-3-GP

VENTURA

0712 Modify: Change VENTURA solution part number to

74.00900.079 from 74.00219.079.

12

R4346

R4346 3K3R2J-3-GP

3K3R2J-3-GP

DY

0728

SMBC_INA219 85,92 SMBD_INA219 85,92

2

DN15ATI

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

PWR_VCCCORE1_DCBATOUT

12

PC4315

PC4314

SC4D7U25V5KX-GP

PL4303

1 2

L-D36UH-1-GP

68.R3610.20A

2nd = 68.R3610.20C

SIR460DP-T1-GE3-GP

PG4318

PG4317

1 2

GAP-CLOSE-PWR-3-GP

10KR2F-2-GP

PWR_VCCCORE_VSUM+_1

10KR2F-2-GP

3K65R2F-1-GP

0719 Modify: Reserved PTC4307 47uF. 0721 Modify: Removed PTC4307.

ISL95831_CPU_CORE ( 2 of 3 )

QUEEN 15

1

12

PC4316

PC4317

QC

PR4318

PR4319

PC4317

SC4D7U25V5KX-GP

PT4301

0809

79.33719.20L

1 2

2nd = 77.C3371.13L

PR4315

1 2

DY

1R2F-GP

1R2F-GP PR4316

PR4316

1 2

DY

1R2F-GP

1R2F-GP PR4317

PR4317

PWR_VCCCORE_VSUM-_1

1 2

1R2F-GP

12

ISEN1 42

12

VSUM+ 42

0705 Modify

DCBATOUT_IMVP7

PG4305

1 2

GAP-CLOSE-PWR

PG4306

1 2

GAP-CLOSE-PWR

PG4307

1 2

GAP-CLOSE-PWR

PG4308

1 2

GAP-CLOSE-PWR

PG4309

1 2

GAP-CLOSE-PWR

PG4310

1 2

GAP-CLOSE-PWR

DCBATOUT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

0705 Modify

VCC_CORE

A00 1224

PT4302

12

ST330U2VDM-4-GP

79.33719.20L

2nd = 77.C3371.13L

ISEN2 42

ISEN3 42

VSUM- 42

PWR_VCCCORE1_DCBATOUT

12

A00 1224

PT4306

PT4306 SE47U25VM-11-GP

SE47U25VM-11-GP

79.47612.3FL

2nd = 79.47612.60L

of

43 108Tuesday, January 04, 2011

A00

5

D D

84.00462.037 SIR462DP-T1-GE3-GP Id=30A, Qg=8.8nC, Rdson=7.9 mohm

PR4401

BOOTG42

UGATEG42 PHASEG42

C C

B B

LGATEG42

1 2

1R3J-L1-GP

PWR_GFXCORE_BOOT_1

PC4407

SCD22U25V3KX-GP

84.00460.037

2nd = 84.08059.037

4

0719 Modify: Change PU4401 part number to 84.00172.037 from

84.07686.037 base on power team Brian suggestion. 0720 Modify: Change PU4401 part number to 84.00462.037 from

84.00172.037 base on power team Brian suggestionl.

678

DDD

12

GD

123

4 5

678

DDD

PU4404

PU4403

84.03503.037 BSZ035N03MS Id=18A,Qg=27~35nC, Rdson=3.4~4.3mohm

PU4404

G

123

4 5

84.00460.037

2nd = 84.08059.037

PWR_GFXCORE_DCBATOUT

0624 Modify: Removed PU4402 MOSFET.

SSS

PU4401

SIR462DP-T1-GE3-GP

84.00462.037

2nd = 84.08064.A37

678

DDD

D

DDD

D

SIR460DP-T1-GE3-GP

SSS

D

SSS

G

123

4 5

0721 Modify: Removed PC4401

PL4401

1 2

L-D36UH-1-GP

68.R3610.20A

2nd = 68.R3610.20C

SIR460DP-T1-GE3-GP

PG4401

1 2

GAP-CLOSE-PWR-3-GP

PWR_GFXCORE_ISP_R

2nd = 69.60011.201

PR4408

10KR2F-2-GP

3

12

PC4402

SC4D7U25V5KX-GP

1 2

GAP-CLOSE-PWR-3-GP

PWR_GFXCORE_ISN_R

1 2

NTC-10K-27-GP

69.60013.131

12

PC4403

SC4D7U25V5KX-GP

68.R3610.20A

0.36uH, Idc=20A, Isat=25A DCR=1.4 +/-7% mohm

PG4402

0809

PR4403

12

1R2F-GP

PR4405

0629 Modify

PR4405_2

12

7K5R2F-1-GP

12

PC4404

SC4D7U25V5KX-GP

SCD1U10V2KX-4GP

0629 Modify

PR4403_2

12

PR4407

0705 Modify

PC4405

PR4406

0920 X01 Modify: Change PC4410 to 0.01u from 0.022uF from Brian updated.

DCBATOUT_IMVP7

12

PC4406

SC4D7U25V5KX-GP

79.33719.20L

2nd = 77.C3371.13L

11KR2F-L-GP

12

PC4409

PC4410

12

SCD01U16V2KX-3GP

PT4401

12

PC4411

1 2

PG4403 GAP-CLOSE-PWRPG4403 GAP-CLOSE-PWR

1 2

PG4404 GAP-CLOSE-PWRPG4404 GAP-CLOSE-PWR

1 2

PG4405 GAP-CLOSE-PWRPG4405 GAP-CLOSE-PWR

1 2

PG4406 GAP-CLOSE-PWRPG4406 GAP-CLOSE-PWR

1 2

PG4407 GAP-CLOSE-PWRPG4407 GAP-CLOSE-PWR

1 2

PG4408 GAP-CLOSE-PWRPG4408 GAP-CLOSE-PWR

1 2

PG4409 GAP-CLOSE-PWRPG4409 GAP-CLOSE-PWR

1 2

VCC_GFXCORE

A00 1224

PT4402

12

ST330U2VDM-4-GP

PC4408

SCD068U16V2KX-GP

1 2

SCD068U16V2KX-GP

2

PWR_GFXCORE_DCBATOUT

79.33719.20L

2nd = 77.C3371.13L

PT4403

80.3371V.A2L

12

330uF, 2.5V, B2 ESR=9m£[, Iripple=3.073A

79.33719.20L

2nd = 77.C3371.13L

ST330U2VDM-4-GP

0629 Modify

DY

12

PR4404

768R2F-1-GP

PR4402

PC4408_1

1 2

DY

549R2F-GP

0721 Modify: Change PR4404 to 768ohm from 549ohm from power team Brian updated.

ISPG 42

1

VCC_GFXCORE Iomax=33A OCP>50A

ISNG 42

EMI/ESD

VCC_CORE VCC_CORE PWR_VCCCORE1_DCBATOUT PWR_VCCCORE2_DCBATOUT PWR_VCCCORE3_DCBATOUT VCC_GFXCORE PWR_GFXCORE_DCBATOUT

EC4405

SCD1U50V3KX-GP

EC4405

EC4401

SCD1U50V3KX-GP

EC4401

SCD1U50V3KX-GP

EC4402

SCD1U50V3KX-GP

EC4402

DY

SCD1U50V3KX-GP

12

DY

A A

DY

5

EC4403

SCD1U50V3KX-GP

EC4403

SCD1U50V3KX-GP

12

SCD1U50V3KX-GP

12

4

0715 Modify: Add EC4401~EC4410 for EMC NEO suggestion.

EC4407

SCD1U50V3KX-GP

EC4407

SCD1U50V3KX-GP

12

DY

12

EC4408

EC4409

SCD1U50V3KX-GP

EC4409

SCD1U50V3KX-GP

12

EC4410

SCD1U50V3KX-GP

EC4410

SCD1U50V3KX-GP

12

DN15ATI

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

3

2

Date: Sheet

ISL95831_CPU_CORE(3/3)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

44 108

1

A00

5

4

3

2

1

DCBATOUT PWR_1D05V_DCBATOUT

PG4501 GAP-CLOSE-PWRPG4501 GAP-CLOSE-PWR

1 2

PG4502 GAP-CLOSE-PWRPG4502 GAP-CLOSE-PWR

1 2

D D

PG4503 GAP-CLOSE-PWRPG4503 GAP-CLOSE-PWR

1 2

PG4504 GAP-CLOSE-PWRPG4504 GAP-CLOSE-PWR

1 2

84.00172.037 BSZ115N03MSC Id=20A, Qg=9.8nC, Rdson=8.9 mohm

TPS51218 for 1D05V

SIR172DP-T1-GE3-GP

PR4516

1123 X02 Modify: Change PR4501 to 75K from 45.3K for 1.05V OCP set to 20A from Brian.

PR4502

RUNPWROK19,46,47,93

C C

B B

PR4502

3D3V_S0

1.05VTT_PWRGD37,48

1 2

0R0402-PAD-2-GP

SC1KP50V2KX-1GP

PR4501

1 2

75KR2F-GP

12

PC4501

DY

A00 1224

12

10KR2J-3-GP

PWR_1D05V_TRIP

PWR_1D05V_EN

PWR_1D05V_CCM

12

PR4503

PR4503 470KR2F-GP

470KR2F-GP

PU4501

1

PGOOD

2

TRIP

3

EN

4

VFB

5

CCM

TPS51218DSCR-GP-U1

GND

VBST

DRVH

V5IN

DRVL

SW

11

PWR_1D05V_VBST

10

PWR_1D05V_DRVH

9

PWR_1D05V_SWPWR_1D05V_VFB

8 7

PWR_1D05V_DRVL

6

0721 Modify: Change PR4504 to 2.2ohm from 0ohm from power team Brian updated.

PR4504

1 2

2D2R3-1-U-GP

PC4503

Id=26.5A Qg=40.6~61nC, Rdson=2.6~3.2mohm

SIR172DP-T1-GE3-GP

PWR_1D05V_VBST_R

5V_S5

0809

12

SC1U10V2KX-1GP

0719 Modify: Change PU4502 part number to 84.00172.037 from

84.07686.037 base on power team Brian suggestion.

PWR_1D05V_DCBATOUT

12

PC4504

SC4D7U25V5KX-GP

Mag. 2.20uH 10*11.5*4 DCR=6.7~7mohm Idc=12A, Isat=27A

PR4514

DY

2D2R5F-2-GP

DY

PR4509

1 2

0R0402-PAD

12

PC4510

DY

SC1000P50V3JN-GP-U

PR4510

1 2

0R0402-PAD

0727 Modify: PR4505,PR4508 change to 100ohm from 10ohm. stuff PR4509,PR4510 0ohm from Brian updated.

PU4502

GD

4 5

PC4502

PC4502 SCD1U25V3KX-GP

SCD1U25V3KX-GP

12

DDD

G

4 5

678

DDD

SSS

123

84.00172.037

2nd = 84.08065.037

0909 X01 Modify: Change PL4501 to 68.2R210.20C from IND-D56UH-27-GP base on Brian updated.

678

D

PU4503

SIR460DP-T1-GE3-GP

SSS

123

84.00460.037

2nd = 84.08059.037

0721 Modify: Brian suggest change PU4503 to 84.00460.037. Change PR4506 to 9.76K from 10K from power team Brian updated.

VTT_SENSE_L

VSS_SENSE_L

12

PC4505

PC4506

SC4D7U25V5KX-GP

PL4501

1 2

COIL-2D2UH-11-GP

12

68.2R210.20C

2nd = 68.2R21B.10I

PWR_1D05V_SNUB

12

PC4509

PC4509 SC560P50V-GP

SC560P50V-GP

12

PC4507

SCD1U25V3KX-GP

PR4505

100R2F-L1-GP-U

VTT_SENSE_L

PR4506

9K76R2F-1-GP

PWR_1D05V_VFB

PR4507

20KR2F-L-GP

0921

VSS_SENSE_L

VCCIO_SENSE 8

VSSIO_SENSE 8

1122 X02 Modify: stuff EC4501 0.1uF from EMC Neo suggestion.

12

EC4501

SCD1U50V3KX-GP

Design Current = 9.9A

15.6A<OCP< 18.3A

1D05V_PWR

SE390U2D5VM-7GP

12

PR4508

PR4508 100R2F-L1-GP-U

100R2F-L1-GP-U

A00 1224A00 1224

12

PC4508

SCD1U10V2KX-4GP

PC4511

12

DY

0920 X01 Modify: Change PR4507 to 20K from 20.5K from Brian updated.

79.3971V.30L

SCD1U10V2KX-4GP

2nd = 77.93971.02L

PT4502

12

SE390U2D5VM-7GP

DY

12

PTC4509

Vout=0.704V*(R1+R2)/R2

0617 Modify: Joseph Change PTC4502 to 330uF from 390uF base on layout placement status. 0721 Modify: Brian Add PC4511 1uF. Change PTC4502 to 330u 79.33719.L01.

0901 X01 Modify: Change PTC4502 to 79.3971V.30L from

79.33719.L01 from power team Brian updated. 0913 X01 Modify: Add 2nd source 77.93971.02L on PTC4502 base on Brian updated 2nd soruce excel file.

1D05V_VTT1D05V_PWR

PG4505 GAP-CLOSE-PWRPG4505 GAP-CLOSE-PWR

1 2

PG4506 GAP-CLOSE-PWRPG4506 GAP-CLOSE-PWR

1 2

PG4507 GAP-CLOSE-PWRPG4507 GAP-CLOSE-PWR

1 2

PG4508 GAP-CLOSE-PWRPG4508 GAP-CLOSE-PWR

1 2

PG4509 GAP-CLOSE-PWRPG4509 GAP-CLOSE-PWR

1 2

PG4510 GAP-CLOSE-PWRPG4510 GAP-CLOSE-PWR

SCD1U25V3KX-GP

1 2

PG4511 GAP-CLOSE-PWRPG4511 GAP-CLOSE-PWR

1 2

PG4512 GAP-CLOSE-PWRPG4512 GAP-CLOSE-PWR

1 2

PG4513 GAP-CLOSE-PWRPG4513 GAP-CLOSE-PWR

1 2

PG4514 GAP-CLOSE-PWRPG4514 GAP-CLOSE-PWR

1 2

PG4515 GAP-CLOSE-PWRPG4515 GAP-CLOSE-PWR

1 2

PG4516 GAP-CLOSE-PWRPG4516 GAP-CLOSE-PWR

1 2

0719 Modify: Reserved EC4502,EC4503 0.1uF near PG4516(TOP) for EMC NEO suggestion.

DY

12

EC4502

SCD1U50V3KX-GP

A A

5

4

3

2

DN15ATI

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

TPS51218_+1.05V_VTT

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

45 108

1

A00

5

4

SSID = PWR.Plane.Regulator_1p5v0p75v

3

2

1D5V_PWR 1D5V_S3

1

5V_S5

D D

0721 Modify: Removed PR4615,PR4616 and connect 0D75V_EN to VTTEN directly.

C C

RUNPWROK19,45,47,93

12

PR4603

PR4603 10KR2F-2-GP

10KR2F-2-GP

12

1 2

PC4603

SCD1U25V3KX-GP

0928 Change PR4606 to 4.02K from 240ohm for fine tune 1.5V output Voltage.

PR4601

PC4602

SCD01U16V2KX-3GP

4K02R2F-GP

3D3V_S0

12

PR4604

PR4604 20KR2J-L2-GP

20KR2J-L2-GP

0D75V_EN37

PWR_1D5V_EN PWR_1D5V_VREF

0721 Modify: Change PR4602 to 68K from 6.2K from power team Brian updated.

PWR_1D5V_REFIN

PWR_1D5V_MODE

47KR2F-GP

PR4601_1

1 2 12

PR4606

PR4608

1 2

PWR_1D5V_TRIP

12

PWR_1D5V_VTTREF

200KR2F-L-GP

12

PR4602

110KR2F-GP

PC4610

PC4610 SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

0920 X01 Modify: Change PR4602 to 110K from 68K from Brian updated.

0630 Modify: Change PC4610 to 0.22u 0402 from 0603 from Brian.

PU4601

20

PGOOD

17

VTTEN

16

EN/PSV

6

VREF

8

REFIN

19

MODE

18

TRIP

5

VTTREF

21

GND

7

GND

TPS51216RUKR-GP

74.51216.073

0630 Modify: Change 1D5V power soluiton to TPS51216 from TPS51116 follow power team Brian suggest.

V5IN

VBST

DRVH

SW

DRVL

PGND

VDDQS

VTTIN

VTT

VTTS

VTTGND

12

PWR_1D5V_VBST

15

PWR_1D5V_DRVH

14

PWR_1D5V_SW

13

TPS51216_DRVL

11 10

PWR_1D5V_VDDQS

9 2 3 1 4

PC4615

State S3 S5 VDDR VTTREF VTT

S0

B B

S3

S4/S5

Hi Hi

Lo Lo

On

HiLo

On Off Off Off

On On

On

Off(Hi-Z)

MODE

PR5003 200k ohm 100k ohm 68k ohm 47k ohm 400kHz

Frequency Discharge Mode 400kHz 300kHz 300kHz

Tracking Discharge

Non-tracking Discharge

84.00172.037

12

BSZ115N03MSC

PC4601

Id=20A, Qg=9.8nC,

SC1U10V3KX-3GP

Rdson=8.9 mohm

PR4605

1 2

2D2R3J-2-GP

84.00460.037 SiR460DP-T1-GE3 Id=40A, Qg=16.8nC, Rdson=4.7~6.1 mohm

+0D75V_DDR_P

12

DY

PC4617

PC4616

SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP

0721 Modify: un-stuff PC4617 from power team Brian updated.

+0D75V_DDR_P 0D75V_S0

1 2

GAP-CLOSE-PWR

1 2

GAP-CLOSE-PWR

PWR_1D5V_VTTREF

0702 Modify: Add PR4611 0ohm 0603 pad on PWR_1D5V_VTTREF.

0719 Modify: Change PU4602 part number to 84.00172.037 from

84.07686.037 base on power team Brian suggestion.

678

DDD

0630 modify

PC4619

PC4619 SCD1U25V3KX-GP

SCD1U25V3KX-GP

PR4605_2

1 2

12

SC10U6D3V5MX-3GP

PG4601

PG4602

DDR_VREF_S3

PR4611

1 2

0R0603-PAD

PU4602

DDD

SIR172DP-T1-GE3-GP

SSS

GD

SSS

GD

84.00172.037

2nd = 84.08065.037

123

4 5

678

DDD

D

DDD

D

PU4603

SIR460DP-T1-GE3-GP

SSS

G

123

4 5

84.00460.037

2nd = 84.08059.037

12

PC4604

SC1U10V3KX-3GP

PM_SLP_S4#19,27,75

DY

1D5V_PWR

0630 Modify: ADD PC4604 1uF0603 on PWR_1D5V_VTTIN.

PC4609

1 2

SC10U25V6KX-1GP

12

PR4612

DY

2D2R5F-2-GP

TPS51216_PHS_SET

12

PC4622

PC4622 SC330P50V2KX-3GP

SC330P50V2KX-3GP

+PWR_SRC_1D5V

PC4611

1 2

A00 1224

1 2

SC10U25V6KX-1GP

PL4601

1 2

IND-D68UH-51-GP-U

68.R6810.20G

2nd = 68.R681A.10Q

68.R6810.20G Id=22~39A DCR=2.4~2.7mohm Size=10X11.5X4

0721 Modify: Removed PR4615,PR4616 and connect 0D75V_EN to VTTEN directly.

PR4607

1 2

0R0402-PAD-2-GP

12

PC4612

PC4613

1 2

SCD1U50V3KX-GP

SC10U25V6KX-1GP

0913 X01 Modify: Add 2nd source 68.R681A.10Q on PL4601 base on Brian updated 2nd soruce excel file.

SCD1U50V3KX-GP

1 2

PG4607

GAP-CLOSE-PWR-3-GP

PWR_1D5V_VDDQS

12

DY

DCBATOUT

PC4614

SC4D7U25V5KX-GP

12

PC4620

SC4D7U6D3V5KX-3GP

PWR_1D5V_EN

PC4606

PC4606 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Design Current = 14.45A

22.71A<OCP< 26.84A

12

0902 X01 Modify: Change PTC4602 to 79.3971V.30L from

79.22719.20L sync with DQ15-NV Add 2nd source 77.93971.02L on PTC4602.

+PWR_SRC_1D5V

PG4603

12

GAP-CLOSE-PWR

PG4604

12

GAP-CLOSE-PWR

PG4605

12

GAP-CLOSE-PWR

PG4606

12

GAP-CLOSE-PWR

1D5V_PWR

A00 1224

12

PT4602

PC4621

SCD1U10V2KX-4GP

SE390U2D5VM-7GP

79.3971V.30L

2nd = 77.93971.02L

79.3971V.30L 390uF, 2.5V,6.3X5.7 ESR=10m£[, Iripple=3.87A

DY

12

PG4608

PG4608 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4609

PG4609 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4610

PG4610 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4611

PG4611 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4612

PG4612 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4613

PG4613 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4614

PG4614 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4615

PG4615 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4616

PG4616 GAP-CLOSE-PWR

GAP-CLOSE-PWR

EC4601

PG4617

PG4617 GAP-CLOSE-PWR

GAP-CLOSE-PWR

SCD1U50V3KX-GP

PG4618

PG4618 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4619

PG4619 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4620

PG4620 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4621

PG4621 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4622

PG4622 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4623

PG4623 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4624

PG4624 GAP-CLOSE-PWR

GAP-CLOSE-PWR

PG4625

PG4625 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

TPS51116_+1.5V_SUS

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

46 108

1

A00

5

4

3

2

1

SSID = PWR.Plane.Regulator_1D8V_S0

D D

3D3V_S5

TPS51311 PWM for 1D8V_S0

12

PC4709

SCD1U25V3KX-GP

3D3V_S5

PU4702

C C

PC4701 SC100P50V2JN-3GPPC4701 SC100P50V2JN-3GP

1 2

PR4709

1 2

5K9R2F-GP

12

DY

PR4708

PR4708 57K6R2F-GP

57K6R2F-GP

PM_SLP_S3#19,27,36,37,75

B B

0902 X01 Modify: Change PR4712 to 10K from 0ohm and stuff PC4717 for fine tune 1D8V_S0 ramp up sequence.

PR4709_1

0629 Modify

RUNPWROK19,45,46,93

PC4710

12

SC2200P50V2KX-2GP

3D3V_S0

PR4712

1 2

10KR2J-3-GP

51331_FB_1 51331_COMP

51331_PS

1 2

DY

51331_EN

12

PC4717

PC4717 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

PR4714100KR2J-1-GPDYPR4714100KR2J-1-GP

PU4702

12

VDD

11

AGND

17

PGND

10

FB

9

COMP

2

RES

8

MODE

3

PGOOD

1

EN

TPS51311RGTR-GP

74.51311.073

PGND

VBST

SW#5 SW#6 SW#7

13

VIN

14

VIN

15 16

51331_VBST 51331_VBST_1

4

51331_SW

5 6 7

12

PC4713

SCD1U25V3KX-GP

PR4710

1 2

0R0603-PAD

SCD1U25V3KX-GP

12

PC4711

1 2

SC2200P50V2KX-2GP

51331_FB_1 51331_FB

1 2

PG4702

PG4702 GAP-CLOSE-PWR

GAP-CLOSE-PWR

12

PC4716

PC4718

SC10U6D3V5MX-3GP

PL4701

IND-2D2UH-46-GP-U

68.2R210.20B

2nd = 68.2R21B.10J

PG4710_1

12

PC4712

0629 Modify

PC4712_1

12

PR4713

40D2R2F-GP

10KR2F-2-GP

SC10U6D3V5MX-3GP

1 2

PG4710

GAP-CLOSE-PWR-3-GP

12

PR4701

PR4701 20KR2F-L-GP

20KR2F-L-GP

12

PR4711

1D8V_RUN_PWR

12

PC4715

SC10U6D3V5MX-3GP

SC22U6D3V5MX-2GP

PC4714

12

0920 X01 Modify: stuff PC4714 22uF from Brian updated.

+1.8V_RUN Design current = 2.7985A

1D8V_RUN_PWR 1D8V_S0

PG4706

1 2

GAP-CLOSE-PWR

PG4707

1 2

GAP-CLOSE-PWR

PG4708

1 2

GAP-CLOSE-PWR

PG4709

1 2

GAP-CLOSE-PWR

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

TPS51311 for 1D8V_S0

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

47 108

1

A00

5

TPS51461 for VCCSA

1112 X02 Modify: set TPS51461 PWM solution dummy field for

D D

VCCSA_PWM and APL5916 LDO solution dummy field for VCCSA_LDO. defualt stuff VCCSA_LDO at ST stage.

5V_S5

VCCSA_PWM

12

PC4807

VCCSA_PWM

PC4807

VID0

C C

B B

A A

5

4

5V_S5

12

PC4814

SC1U10V2KX-1GP

12

PC4816

VCCSA_PWM

SC2D2U10V3KX-1GP

PWR_VCCSA_V5DRV

12

PC4812

SC4D7U25V5KX-GP

VCCSA_PWM

TPS51461RGER-GP

74.51461.043

VCCSA

0.9V

0.725V

0.675V

D85V_PWRGD42

1 2

PR4817 0R2J-2- GP

VCCSA_LDO

SC1U6D3V2KX-GP

SC1U10V2KX-1GP

VCCSA_PWM

20100614 V1.1 for CRB board

PR4819

4K7R2J-2-GP

VCCSA_LDO

PC4821

PR4806

PR4806 1R2F-GP

1R2F-GP

VCCSA_PWM

PCB Footprint = QFN24-G2D25H40

12

PC4813

PC4815

SC4D7U25V5KX-GP

SCD1U25V3KX-GP

VCCSA_PWM

VID1

L

L 0.8V

H

1112 X02 Modify: CO-LAY APL5916 related circuit for VCCSA LDO solution.

L

H

L

H

APL5916 for VCCSA

1.05VTT_PWRG D37,45

Vout=0.8*(1+R1/R2)

4

19 20 21 22 23 24 25

3D3V_S0

PU4801

PGND PGND PGND VIN VIN VIN GND

12

SC1U6D3V2KX-GP

APL5916_EN

12

DY

L

H

3D3V_S0

12

VCCSA_PWM

PR4809

PR4809 4K7R2J-2-GP

4K7R2J-2-GP

PR4808

1 2

0R0402-PAD

VCCSA_PWM

PWR_VCCSA_VID1

PWR_VCCSA _PGOOD

PWR_VCCSA_VID0

PWR_VCCSA_EN

18

17

15

13

16

EN

VID014VID1

V5FILT

V5DRV

PGOOD

BST SW#11 SW#10

SW#9 SW#8 SW#7

VCCSA_PWM

GND1VREF2COMP3SLEW4VOUT5MODE

6

PWR_VCCSA_VREF

PWR_VCCSA_COMP

PWR_VCCSA_VOUT

PWR_VCCSA_SLEW

12

PR4802

PR4802 4K99R2F-L-GP

4K99R2F-L-GP

VCCSA_PWM

PWR_VCCSA_COMP_1

12

PC4817

PC4817 SC3300P50V3KX-1GP

SC3300P50V3KX-1GP

VCCSA_PWM

PC4802

PC4802 SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

1 2

VCCSA_PWM

5V_S5

12

PC4824

7

POK

8

EN

VCCSA_LDO

PU4802

PU4802 APL5916KAI-TRL-GP

APL5916KAI-TRL-GP

74.05916.031

VCCSA_PWRVCCSA_SEL

D85V_PWRGD 42

1 2 1 2

12

SC1U6D3V2KX-GP

PWR_VCCSA_BST

12 11 10 9 8

PWR_VCCSA_SW

7

PC4801

PC4801 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

1 2

VCCSA_PWM

VCCSA_LDO

6

VIN VIN

VCNTL

VOUT VOUT

FB

GND

1

0.9V

0.8V

PR4812

1 2

DY

1KR2F-3-GP

1KR2F-3-GP PR4804

PR4804 0R0402-PAD

0R0402-PAD PR4805

PR4805 0R0402-PAD

0R0402-PAD

PR4801

1 2

0R0402-PAD

DY

PC4810

PR4807

1 2

0R0603-PAD

VCCSA_PWM

1 2

0D85V_S0

12

DY

5 9

3 4

2

VCCSA_LDO

3

VCCSA_PWM

VCCSA_SEL 9 H_FC_C22 9

VCCSA_PWM

PWR_VCCSA_BST_R

PR4811

100R2F-L1-GP-U

100R2F-L1-GP-U PR4810

PR4810

VCCSA_PWM

0R0402-PAD

VCCSA_PWM

PWR_VCCSA_VIN

EC4801

SCD1U50V3KX-GP

PC4822

12

VCCSA_LDO

SC10U6D3V5MX-3GP

R1

PR4814

10KR2F-2-GP

VCCSA_LDO

PWR_VCCSA_FB

R2

PR4815

80K6R2F-GP

2nd = 84.DM601.03F

3

1.05VTT_PWRG D 37,45

PC4811

SCD1U25V3KX-GP

1 2

VCCSA_PWM

12

PR4803

PR4803 2D2R5F-2-GP

2D2R5F-2-GP

DY

0D85V_S0

VCCUSA_SENSE 9

GAP-CLOSE-PWR

12

PWR_VCCSA_SNUB

12

PC4809

DY

SC560P50V-GP

1D05V_VTT

PG4801

1 2

VCCSA_LDO

PG4802

1 2

VCCSA_LDO

PG4809

1 2

VCCSA_LDO

PG4810

1 2

VCCSA_LDO

PG4811

1 2

VCCSA_LDO

PG4812

1 2

VCCSA_LDO

PC4820

12

VCCSA_LDO

SC10U6D3V5MX-3GP

VCCSA_LDO

12

PC4818

SC100P50V2JN-3GP

VCCSA_LDO

12

PR4816

80K6R2F-GP

DY

PQ4801_D

5

6

PQ4801

DY

2N7002KDW-G P

84.2N702.A3F

123 4

1118 X02 Modify: Change PTC4801 to 100u(77.21071.07L) from 150u from power team Brian updated. 1122 X02 Modify: Updated VCCSA_LDO circuit from Power team Brian updated.

68.R4710.10M Id=17.5~26A DCR=4~4.2mohm Size=6.5X6.9X3

PL4801

1 2

IND-D47UH-22-GP

VCCSA_PWM

68.R4710.10M

2nd = 68.R4710.10V

VCCSA_PWM

Iomax=6A OCP>9A VCCSA=0.85V

VCCSA_PWR

12

PC4819

PC4825

SC10U6D3V5MX-3GP

VCCSA_LDO

PQ4801_5

3D3V_S0

12

PR4818

10KR2F-2-GP

DY

PQ4801_G

PC4803

PC4804

SC22U6D3V5MX-2GP

12

VCCSA_PWM

12

PTC4801

DY

ST100U6D3VBM-7GP

PR4813

1 2

DY

12

10KR2J-3-GP

DY

PC4826

PC4826 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

2

Design Current = 4.2A

6.6A<OCP< 7.8A

0D85V_S0

PC4805

PC4806

SC22U6D3V5MX-2GP

12

PC4808

DY

VCCSA_PWM

0D85V_S0

PG4803

1 2

VCCSA_LDO

GAP-CLOSE-PWR

PG4804

1 2

VCCSA_LDO

GAP-CLOSE-PWR

PG4805

1 2

VCCSA_LDO

GAP-CLOSE-PWR

PG4806

1 2

VCCSA_LDO

GAP-CLOSE-PWR

PG4807

1 2

VCCSA_LDO

GAP-CLOSE-PWR

PG4808

1 2

VCCSA_LDO

GAP-CLOSE-PWR

VCCSA_SEL 9

2

1

SCD1U25V3KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Tuesday, January 04, 2011

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

TPS51461_VCCSA

QUEEN&NIRVANA 15

1

48 108

A00

of

SSID = VIDEO

3D3V_S0

0909 X01 Modify: Change LCD1 to 20.F1816.030 for 30pin Re-assign LCD1 pin define base on Roy updated cable pin define list.

LVDS CONNECTOR

LCD1

31

NP1

NP2

32

PS-CON30-GP

20.F1816.030

2nd = 20.F1860.030

DCBATOUT_LCD DCBATOUT

12

EC4909

DCBATOUT_LCD

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

USB_PN1218

USB_PP1218

12

C4904

SCD1U50V3KX-GP

SC1KP50V2KX-1GP

F4902

1 2

0R0603-PAD

LCD_BRIGHTNESS

USB_CAMERA# USB_CAMERA

BLON_OUT_C

LCD_TST_C

12

DY

F4901

POLYSW-1D1A24V-GP-U

69.50007.A31

1 2

C4905

2nd = 69.50007.A41

SCD1U50V3KX-GP

Camera Power

12

EC4903

DY

SCD1U10V2KX-5GP

R4902 33R2J-2-GPR4902 33R2J-2-GP

3D3V_CAMERA_S0

AUD_DMIC_CLK 29

AUD_DMIC_IN0 29

LVDSA_CLK 17 LVDSA_CLK# 17

LVDSA_DATA2 17 LVDSA_DATA2# 17

LVDSA_DATA1 17 LVDSA_DATA1# 17

LVDSA_DATA0 17 LVDSA_DATA0# 17 LVDS_DDC_DATA_R 17 LVDS_DDC_CLK_R 17

3D3V_S0

LCDVDD

C4902

C4901

SC1U6D3V2KX-GP

1 2

SCD1U10V2KX-5GP

69.10103.041

2nd = 69.10084.071

FILTER-4P-6-GP

3 4

TR4902

1122 X02 Modify: Change TR4902 CM choke to 69.10103.041 and un-stuff R4908,R4909 from EMC Neo Suggestion.

12

3D3V_CAMERA_S03D3V_S0

12

DY

C4903

C4903 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

LVDS_DDC_CLK_R17 LVDS_DDC_DATA_R17

12

1

12

EC4906

SCD1U50V3KX-GP

EC4906

SCD1U50V3KX-GP

1

SRN2K2J-1-GP

RN9403

4

L_BKLT_CTRL 17

A00 0103 not co-lay

TP4904TPAD14-GPTP4904TPAD14-GP

USB_CAMERA# USB_CAMERA

LCD_BRIGHTNESS LCD_TST_C

LVDSA_CLK# LVDSA_CLK

EC4904

23

For EMI request

Close to LVDS connector

12

EC4901

EC4905

DY

SC5D6P50V2CN-1GP

0913 X01 Modify: Reserved EC4910~EC4915 on LVDS signal for EMC suggestion.

LVDSA_DATA0 LVDSA_DATA0# LVDSA_DATA1 LVDSA_DATA1# LVDSA_DATA2 LVDSA_DATA2#

12

EC4902

EC4910

DY

SC33P50V2JN-3GP

DY

SC5D6P50V2CN-1GP

12

EC4911

EC4912

DY

SC5D6P50V2CN-1GP

12

EC4913

DY

SC33P50V2JN-3GP

12

EC4914

EC4915

DY

SC33P50V2JN-3GP

SSID = VIDEO

LCD POWER for ROSA

BAT54CPT-GP

LVDS_VDD_EN17

LCD_TST_EN27

0916 X01 Modify: Change TPNL1 to 20.F1621.004 from Double updated EMN&DXF. 0917 X01 Modify: Add 2nd source 20.F1561.004;3rd source

20.F1686.004 on TPNL1 from updated connector list.

1

2

D4901

83.R2003.E81

2ND = 83.00054.Q81

CLOSED TO LVDS CONN LCD1

TPNL1

5 1

TPNL

2 3 4

6

ACES-CON4-17-GP-U

20.F1621.004

2nd = 20.F1561.004

3rd = 20.F1686.004

LCDVDD_EN

3

R4907

1 2

100KR2J-1-GP

BLON_OUT_C LCD_TST_C

USB_PN0_C USB_PP0_C

1122 X02 Modify: stuff C4908 0.1uF from EMC Neo suggestion.

LCDVDD 3D3V_S0

Layout 40 mil

12

C4908

SC4D7U6D3V3KX-GP

R4905

SC4D7U6D3V3KX-GP

49K9R2F-L-GP

RN4901

1

4

2 3

SRN100J-3-GP

1122 X02 Modify: Change RN4901 to 100ohm 4p from 8p for improve layout place.

TOUCH PANEL

TPNL

12

C4911

SC10U6D3V5KX-1GP

USB_PN018

USB_PP018

DN15ATI Whistler

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

DY

TPNL

12

SCD1U50V3KX-GP

EC4908

0902 X01 Modify: Add 2nd source 74.09724.09F on U4901 sync with Annie.

U4901

1

EN

IN#5

2

GND

12

Tuesday, January 04, 2011

OUT3IN#4

G5285T11U-GP

SCD1U50V3KX-GP

EC4907

74.05285.07F

2nd = 74.09724.09F

1122 X02 Modify: stuff EC4907 0.1uF from EMC Neo suggestion.

BLON_OUT 27

LCD_TST 27

5V_S0TPNL_5V

R4904

1 2

TPNL

12

0R0402-PAD-2-GP

A00 1230

C4910

SCD1U10V2KX-4GP

TR4901

1 2

TPNL

FILTER-4P-6-GP

69.10103.041

2nd = 69.10084.071

1122 X02 Modify: Swap TR4901 pin4,3 and pin2,1 each other base on Connie swap report. Change TR4901 CM choke to 69.10103.041 and un-stuff R4911,R4912 from EMC Neo Suggestion. Change R4911,R4912 to 0603 from 0402.

LCD Connector

QUEEN 15

5 4

12

C4907

SC4D7U6D3V3KX-GP

USB_PN0_C USB_PP0_C

34

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00 1229

of

49 108

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

CRT Connector

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

50 108

1

A00

5

SSID = VIDEO

R5101

HDMI_CLK_R_C

D D

HDMI_DATA0_R_C

C C

R5101

1 2

0R0402-PAD-2-GP

R5102

1 2

0R0402-PAD-2-GP

0R0402-PAD-2-GP R5104

R5104

1 2

0R0402-PAD-2-GP

R5103

1 2

0R0402-PAD-2-GP

HDMI_CLK_R_C_CON

HDMI_CLK_R_C#_CONHDMI_CLK_R_C#

HDMI_DATA0_R_C_CON

HDMI_DATA0_R_C#_CONHDMI_DATA0_R_C#

HDMI_CLK#85 HDMI_CLK85

HDMI_DATA0#85 HDMI_DATA085

HDMI_DATA1#85 HDMI_DATA185

HDMI_DATA2#85 HDMI_DATA285

HDMI Level Shifter & CONNECTOR

R5106

1 2

0R0402-PAD-2-GP

R5105

1 2

0R0402-PAD-2-GP

R5108

1 2

0R0402-PAD-2-GP

R5107

1 2

0R0402-PAD-2-GP

1 2 1 2

HDMI_CLK# HDMI_CLK

HDMI_DATA0# HDMI_DATA0

HDMI_DATA1# HDMI_DATA1

HDMI_DATA2# HDMI_DATA2

HDMI_DATA1_R_C

HDMI_DATA2_R_C

C5103 SCD1U10V2KX-5GPC5103 SCD1U10V2KX-5GP C5104 SCD1U10V2KX-5GPC5104 SCD1U10V2KX-5GP

C5105 SCD1U10V2KX-5GPC5105 SCD1U10V2KX-5GP C5106 SCD1U10V2KX-5GPC5106 SCD1U10V2KX-5GP

C5110 SCD1U10V2KX-5GPC5110 SCD1U10V2KX-5GP C5107 SCD1U10V2KX-5GPC5107 SCD1U10V2KX-5GP

C5108 SCD1U10V2KX-5GPC5108 SCD1U10V2KX-5GP C5109 SCD1U10V2KX-5GPC5109 SCD1U10V2KX-5GP

Close to HDMI Connector

B B

3D3V_S0

12

R5109

DY

20KR2J-L2-GP

HDMI_OE#

D

Q5101

S

G

5

Q5101 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

DY

HPD_HDMI_CON

A A

X02 1110

0714 Modify: Stuff R5109 20K PH to 3D3V_S0.

1 2

R5127 0R0402-PADR5127 0R0402-PAD

0707 Modify: Add Q5101,R5109,R5127 for HDMI_IN# to KBC.

0630 SWAP RN5106

HDMI_PLL_GND

HDMI_IN# 27

4

A00 1229

HDMI_DATA1_R_C_CON

0913 X01 Modify: Add R5101~R5108and reserved TR5101~TR5104 on all of HDMI differential pair for EMC suggestion.

0806

RN5106

RN5106 SRN470J-5-GP

SRN470J-5-GP

3D3V_VGA_S0

12

DY

678

123

R5113

R5113 100KR2J-1-GP

100KR2J-1-GP

HDMI_CLK_R_C# HDMI_CLK_R_C

HDMI_DATA0_R_C# HDMI_DATA0_R_C

HDMI_DATA1_R_C# HDMI_DATA1_R_C

HDMI_DATA2_R_C# HDMI_DATA2_R_C

RN5107

RN5107 SRN470J-5-GP

SRN470J-5-GP

0630 SWAP RN5107

4 5

0726 For NV

HDMI_DATA1_R_C#_CONHDMI_DATA1_R_C#

HDMI_DATA2_R_C_CON

HDMI_DATA2_R_C#_CONHDMI_DATA2_R_C#

678

123

4 5

Routing Guidelines: CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm). The total dela y on CTRLDATA should be longer than CTRLCLK.

4

HDMI_PLL_GND

D

G

3

DY

1 2

Q5103

Q5103 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

GPU_HDMI_CLK85

GPU_HDMI_DATA85

3

R5123

0R2J-2-GP

HDMI CONN

3D3V_VGA_S0 5V_S0

0927

R5114

0R0402-PAD-2-GP

A00

HDMI1

22 20 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23

SKT-HDMI23-2-GP-U1

22.10296.331

2nd = 22.10296.311

12

R5115

DY

0R2J-2-GP

1 2

1

23

RN5116

RN5116 SRN2K2J-1-GP

SRN2K2J-1-GP

Optimus

4

2

0721 Modify: Change HDMI1 part number to 22.10296.271 from

22.10296.211 base on ME latest EMN and DXF.

0831 X01 Modify: Change HDMI1 part number to 22.10296.311 from

22.10296.271 base on ME Double updated. 0910 X01 Modify: Change HDMI1 part number to 22.10296.331 from

22.10296.311 base on ME Double updated.

HDMI_DATA2_R_C_CON

HDMI_DATA2_R_C#_CON HDMI_DATA1_R_C_CON

HDMI_DATA1_R_C#_CON HDMI_DATA0_R_C_CON

HDMI_DATA0_R_C#_CON HDMI_CLK_R_C_CON

HDMI_CLK_R_C#_CON

DDC_CLK_HDMI DDC_DATA_HDMI

12

C5102

HDMI_IN#27

HPD_HDMI_CON

1 2

R5111 1KR2F-L-GPR5111 1KR2F-L-GP

12

R5110

1MR2F-GP

0629 Modify: Utilize Q5104 2N7002 instead of PCA9509 Level shifter base on Intel DG recommand on HDMI DDC.

GPU_HDMI_DATA

2

3D3V_S0

SCD1U10V2KX-5GP

HDMI_HPD_B

84.03904.L06

2nd = 84.03904.P11

3rd = 84.03904.T11

0810

3D3V_VGA_S0

Q5104

5 6

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

12

6

123 4

34 2 1

1

DDC_DATA_HDMI

1

5V_CRT_S0_R

AFTP5101TPAD14-GP AFTP5101TPAD14-GP

0716 Modify: Add F5101 1A FUSE for DELL suggesiton. 0720 Modify: Stuff F5101 FUSE from DELL suggestion.

A00 1223 HDMI leakage

X02 10.28

R5112

R5112 10KR2J-3-GP

10KR2J-3-GP

5

Q5105

Q5105 2N7002KDW-GP

2N7002KDW-GP

GPU_HDMI_HPD 85

3D3V_S0

R5116 1KR2F-L-GPR5116 1KR2F-L-GP

3

DY

Q5102

1

PMBS3904-1-GP

2

HDMI_HPD_E

12

R5117

R5117 10KR2J-3-GP

10KR2J-3-GP

DY

5V_CRT_S0_R

DDC_CLK_HDMIGPU_HDMI_CLK

DDC_DATA_HDMI

HDMI Level Shifter/Connector

QUEEN 15

Tuesday, January 04, 2011

QUEEN 15

12

0629 Modify

1 2

R5125 0R2F-N1-GP

DY

A00 1228

4

RN5101

RN5101 SRN2K2J-1-GP

SRN2K2J-1-GP

0923 SWAP

1

2 3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

51 108

1

PEX_RST# 83,85,86

HDMI_HPD_DET 85

A00

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

52 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

LVDS_Switch

53 108Tuesday, January 04, 2011

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

54 108Tuesday, January 04, 2011

A00

5

4

3

2

1

SSID = User.Interface

D D

C C

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ITP/Fan Connector

Size Document Number Rev

A3

Date: Sheet

ITP/Fan Connector

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

55 108Tuesday, January 04, 2011

1

A00

SSID = SATA

1123 X02 Modify: stuff EC5601 180pF from RF fine tune result.

3D3V_S0

12

EC5601

EC5601 SC180P50V2JN-1GP

SC180P50V2JN-1GP

3D3V_S0

SATA HDD Connector

0629 Modify: Move All of 0.01uF cap closed to HDD

20100625 V1.2

12

C5604

DY

SC10U6D3V5KX-1GP

SATA_TXN021

SATA_RXN021

SATA_RXP021

12

C5601

connector base on Layout guideline.

SATA_TXP021

DY

5V_S0

SCD1U10V2KX-5GP

C5616 SCD01U16V2KX-3GPC5616 SCD01U16V2KX-3GP

1 2

C5615 SCD01U16V2KX-3GPC5615 SCD01U16V2KX-3GP

1 2

12

C5605

C5606

FFS_INT279

SC10U10V5ZY-1GP

SCD1U10V2KX-5GP

HDD1

23

NP1

HDD1_20 HDD1_21 HDD1_22

1 2

3 4 5 6 7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

NP2

24

TYCO-CON22-1-GP-U2

20.F1011.022

2nd = 62.10065.081

0810 0901 Add 2nd. 0906 Add 3rd.

A00 delete 62.10065.121

SATA_TXP0_C

C5614SCD01U16V2KX-3GP C5614SCD01U16V2KX-3GP

12

SATA_TXN0_C

C5613SCD01U16V2KX-3GP C5613SCD01U16V2KX-3GP

12

SATA_RXN0_C SATA_RXP0_C

TP5601TPAD14-GP TP5601TPAD14-GP

1

TP5602TPAD14-GP TP5602TPAD14-GP

1

TP5603TPAD14-GP TP5603TPAD14-GP

1

ODD Connector

ODD1

8 NP1 S1

SATA_TXP4_C

S2

SATA_TXN4_C

S3 S4

SATA_RX4-_C

S5

SATA_RX4+_C

S6 S7

P1 P2 P3 P4 P5 P6 NP2 9

SKT-SATA7P-6P-40-GP-U

62.10065.E01

2nd = 62.10065.D01

3rd = 62.10065.D61

0614 Modify: Change ODD1 connector part number to

22.10300.421 base on ME EMN and DXF. 0707 Modify: Change ODD1 connector part number to

62.10065.E01 base on latest EMN and DXF.

SATA_RX- and SATA_RX+ Trace Length match within 20 mil

Mars: Exchange ODD and ESATA differential pair each other.

C5612 SCD01U16V2KX-3GPC5612 SCD01U16V2KX-3GP

1 2

C5611 SCD01U16V2KX-3GPC5611 SCD01U16V2KX-3GP

1 2

C5607 SCD01U16V2KX-3GPC5607 SCD01U16V2KX-3GP

1 2

C5608 SCD01U16V2KX-3GPC5608 SCD01U16V2KX-3GP

1 2

SATA_ODD_PRSNT# 22

SATA_ODD_DA#_C

12

R5604

R5604 10KR2J-3-GP

10KR2J-3-GP

DY

0629 Modify: Move All of 0.01uF cap closed to ODD

20100625 V1.2

SATA_ODD_PWRGT SATA_ODD_DA#

connector base on Layout guideline.

SATA_TXP4 21

SATA_TXN4 21

SATA_RXN4 21 SATA_RXP4 21

ODD_PWR_5V

R56020R2J-2-GP

12

DY

0629 Modify: Move R5601 PH 10K to RN5601 PH.

RN5601

SRN10KJ-5-GP

1 23

4

SUPPORT ZERO SATA ODD

SATA_ODD_DA# 18

3D3V_S0

When the drive is powered on, the FET to the MD/DA pin drive is OFF. When the drive is powered off, the FET to the MD/DA pin is ON

5V_S0

R5605

R5605 100KR2J-1-GP

100KR2J-1-GP

1 2

ODD_PWRGT#

SATA_ODD_DA#_C

5

6

Q5601

0707 Modify: Change Q5601 to DUAL 2N7002 for isolate MD/DA signal between PCH and ODD.

SATA_ODD_PWRGT SATA_ODD_DA#

123 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

SATA Zero Power ODD

0629 Modify: Move R5601 PH 10K to RN5601 PH.

SATA_ODD_PWRGT22

U5601

U5601 G547F1P81U-GP

5V_S0

12

C5609

C5609 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

G547F1P81U-GP

OUT#6 OUT#7 OUT#8

5 6 7 8

SC10U6D3V5KX-1GP

EN/EN#4OC#

3

IN#3

2

IN#2

1

GND

74.00547.C79

2ND = 74.02191.079

ƵƌƌĞŶƚůŝŵŝƚ ĐƚŝǀĞ,ŝŐŚ ƚǇƉсхϮ

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

HDD/ODD

QUEEN 15

ODD_PWR_5V

C5610

56 108

100 mil

12

of

A00

5

SSID = ESATA

4

3

2

1

D D

0809

1122 X02 Modify: Change TR5701CM choke to 69.10103.041 and un-stuff R5718,R5719 from EMC Neo Suggestion. 1123 X02 Modify: Change R5718,R5719 to 0603 from 0402.

C C

USB_PN8_R

USB_PP8_R

B B

A00 1229

TR5701

1 2

34

FILTER-4P-6-GP

69.10103.041

2nd = 69.10084.071

USB_PN8_C

AFTE14P-GP

AFTE14P-GP AFTE14P-GP

AFTE14P-GP

USB CHARGER

0629 Modify

U5702

1

USB_PP8_R USB_PN8_R

0806

S0 S1 00 001 1

11

close to ESATA1

AFTP5716

AFTP5715

AFTP5715 AFTP5703

AFTP5703

S0

2

D+

3

D-

4

GND

5

A+

PI5USB14550AZEE-GP

Auto

D+/- connects to Y+/-

SATA_TXP521 SATA_TXN521

SATA_RXP521 SATA_RXN521

5V_USB1_S3

1

USB_PN8_C

1

USB_PP8_C

1

GND

VDD

0803 Modify: Change U5702 USB CHARGER circuit to PI5USB14550 from MAX14556.

0R0402-PAD

11

CB

10

S1

9

Y+

8

Y-

7 6

A-

1 2

R5721

C5701

0R0402-PAD

1 2

USB_PP8 18

USB_PN8 18

5V_S5

USBCHARGER_CB0 27

0809

Switch Control B it: CB=0 (AM):auto detection charger identification active. CB=1 (PM):connect DP/DM to TDP/TDM.

SCD1U10V2KX-4GP

ESATA CONN

0831

5V_USB1_S3

USB_PP8_C USB_PN8_C

SATA_TXP5_C SATA_TXN5_C

SATA_RXP5_C SATA_RXN5_C

C5707 SCD01U16V2KX-3GPC5707 SCD01U16V2KX-3GP

1 2

C5708 SCD01U16V2KX-3GPC5708 SCD01U16V2KX-3GP

1 2

C5705 SCD01U16V2KX-3GPC5705 SCD01U16V2KX-3GP

1 2

C5702 SCD01U16V2KX-3GPC5702 SCD01U16V2KX-3GP

1 2

0629 Modify: Move All of 0.01uF cap closed to ESATA connector base on Layout guideline. 0706 Modify: Change ESATA1 part number to 22.10321.F71 base on latest EMN and DXF. 0713 Modify: Add USBDET_CON# on ESATA1 pin15 for USB temporary detect solution ESATA1 CONN should be searched for detect type connector. 0719 Modify: ME Double provide temporary foxconn ESATA conn

22.10290.141 for SSI stage function test.

ESATA1

1

VBUS

6

A+

7

AB+10GND

9

B-

3

D+

2

D-

SKT-ESATA-USB-11P-6-GP-U

22.10321.W11

2nd = 22.10339.261

E-SATA USB 2.0 Combo CE/H=-0.16/2.83mm with detect function

DT1 DT2

GND GND GND

GND GND GND GND

ESATA1_D1USB_PP8_C

12 13

4 5 8 11 14 15 16 17

1

AFTP5717

AFTP5717 AFTE14P-GP

AFTE14P-GP

1 2

R5722 0R0402-PADR5722 0R0402-PAD

USBDET_CON# 27

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

ESATA

QUEEN 15

1

of

57 108Tuesday, January 04, 2011

A00

5

4

3

2

1

SSID = AUDIO

D D

6SHDNHU&RQQHFWRU

ACES-CON4-7-GP-U

R5801 0R0402-PAD-2-GPR5801 0R0402-PAD-2-GP

C C

AUD_SPK_L-29 AUD_SPK_L+29 AUD_SPK_R-29

AUD_SPK_R+29

1 2

R5802 0R0402-PAD-2-GPR5802 0R0402-PAD-2-GP

1 2

R5803 0R0402-PAD-2-GPR5803 0R0402-PAD-2-GP

1 2

R5804 0R0402-PAD-2-GPR5804 0R0402-PAD-2-GP

1 2

A00

1 2

1122 X02 Modify: stuff EC5801~EC5804 470pF from EMC Neo suggestion.

1 2

EC5801

EC5802

SC470P50V-2-GP

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C

AUD_SPK_R+_C

1 2

EC5803

SC470P50V-2-GP

1 2

EC5804

SC470P50V-2-GP

2nd = 20.F1804.004

1110 X02 Modify: Add 2nd 20.F1804.004 on SPK1 from ME updated connector list.

ACES-CON4-7-GP-U

SPK1

6

5

4 3 2

1

20.F0772.004

0913 X01 Modify: Change SPK1 to 20.F0772.004 from

20.F1647.004 from Double updated. 0914 X01 Modify: Re-assign SPK1 pin define base on Roy updated excel file for 20.F0772.004

B B

AFTP5801TPAD14-GP AFTP5801TPAD14-GP AFTP5802TPAD14-GP AFTP5802TPAD14-GP AFTP5803TPAD14-GP AFTP5803TPAD14-GP AFTP5804TPAD14-GP AFTP5804TPAD14-GP

A A

5

4

AUD_SPK_L-_C

1

AUD_SPK_L+_C

1

AUD_SPK_R-_C

1

AUD_SPK_R+_C

1

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

SPEAKER CONN

Size Document Number Rev

A4

Date: Sheet

2

QUEEN 15

SPEAKER CONN

58 108Tuesday, January 04, 2011

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

59 108Tuesday, January 04, 2011

A00

5

SSID = Flash.ROM

SPI FLASH ROM (4M byte) for PCH

D D

R6003

4K7R2J-2-GP

SPI_CS0#_R21,27

SPI_SO_R21,27

C C

1 2

R6001 33R2J-2-GPR6001 33R2J-2-GP

EC6002

SC4D7P50V2CN-1GP

EC6002

DY

12

4

3D3V_S5

0701 Modify: Change RN6001 4.7K to R6003,R6004,R6005

4.7K 0402 for layout routing.

R6004

R6004 4K7R2J-2-GP

4K7R2J-2-GP

1 2

SPI_SO

SPI_WP#

0629 Modify: Change U6001 part number to 72.25320.C01 base on Sourcer provide recommand ROM list.

R6005

R6005 4K7R2J-2-GP

4K7R2J-2-GP

1 2

U6001

1

CS#

2

DO WP# VSS

HOLD#

3 4

W25Q32BVSSIG-1-GP

72.25Q32.A01

2nd = 72.25320.C01

3rd = 72.25P32.C01

SPI_HOLD_0#

VCC

CLK

DI

3

2

1

Notes: The total SPI interface signal between EC and PCH can¡¦t not exceed 6500mil. The mismatch between

3D3V_S5

12

DY

3D3V_S5

8 7 6 5

12

DY

EC6001

EC6003

SC4D7P50V2CN-1GP

EC6001 SC10P50V2JN-4GP

SC10P50V2JN-4GP

0917 X01 Modify: EC6001 change to 10p from 4.7p and default stuff from Neo suggestion.

12

C6002

C6001

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

SPI_CLK_R 21,27 SPI_SI_R 21,27

SPI signal must be within 500mil

X02

SSID = RBATT

3D3V_AUX_S5

B B

A A

RTC_AUX_S5

C6003

SC1U6D3V2KX-GP

1111 X02 Modify: Add Q6002,R6007 fo FACTORY RTC detect function

RTC_PWRRTC_PWRRTC_PWRRTC_PWR

12

R6007

R6007 10MR2J-L-GP

10MR2J-L-GP

Q6001

3

CH715FPT-GP

1 2

83.R0304.B81

2nd = 83.00040.E81

R6006

1 2

DY

100R2J-2-GP

2N7002K-2-GP

G

S

Q6002

84.2N702.J31

2ND = 84.2N702.031

5

2

1

Width=20mils

D

RTC_PWR

X02 1111

1 2

TP6002TPAD14-GP TP6002TPAD14-GP

+RTC_VCC

R6002

R6002 1KR2J-1-GP

1KR2J-1-GP

TP6001TPAD14-GP TP6001TPAD14-GP

+RTC_VCC

1

RTC_DET# 22

A00 1224 Update RTC1

RTC1

1

PWR

2

GND

NP1

NP2

1

BAT-330DG02PSS0301CE-GP-U

NP2

62.70001.051

2nd = 62.70014.001

3rd = 62.70001.061

0615 Modify: Change RTC1 connector part number to 62.70001.051 base on ME EMN and DXF.

4

VccRTC is now connected to VccDSW3_3 through the Schottky diode instead of the 3.3V Sus well.

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Flash/RTC

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

60 108

1

A00

5

SSID = USB

D D

C C

CRT Board and COMBO USB Power

C6103

1123 X02 Modify: Removed C6105,C6103.

4

12

C6101

SCD1U10V2KX-5GP

5V_S5

12

Support 2A

U6101

at least 160 mil

USB_PWR_EN#27 USB2_CRT_ON#22

1122 X02 Modify: Change U6101 to dual USB power switch from single for Layout limitation and placement. 1123 X02 Modify: Change U6101 1st(74.02182.071);2nd(74.00546.A7D) ;3rd(74.02062.079) from Sourcer Harrison suggestion.

1

GND

2

IN

3

EN1# EN2#4FLG2

AP2182SG-13-GP

74.02182.071

2nd = 74.00546.A7D

3rd = 74.02062.079

FLG1 OUT1 OUT2

3

USB_OC#8_9 18

8 7 6 5

at least 80 mil

SC1U10V2KX-1GP

5V_USB2_S3

C6102

at least 80 mil

USB_OC#0_1 18

SC1U10V2KX-1GP

C6104

12

2

5V_USB1_S3

12

TC6102

SC10U6D3V5KX-1GP

A00 1221

12

TC6101

TC6101 ST100U6D3VAM-3-GP

ST100U6D3VAM-3-GP

80.10715.B1L

2nd = 77.C1071.20L

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

QUEEN&NIRVANA 15

Taipei Hsien 221, Taiwan, R.O.C.

USB Power SW

1

of

61 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

62 108Tuesday, January 04, 2011

A00

5

4

3

2

1

SSID = User.Interface

R6303

1 2

DY

0R2J-2-GP

Q6301

D D

C C

BT_LED

WLAN_W W AN_LED#68,82

Q6301

G

DY

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

0722 Modify: Add Q6301 and combine BT_LED to WLAN_WWAN_LED#.

USB_PP318

USB_PN318

BT_ACT82

BLUETOOTH_EN27,82

WLAN_ACT82

WLAN_W W AN_LED#

D

DY

AFTP6301AFTP6301

AFTP6302AFTP6302 AFTP6304AFTP6304

AFTP6305AFTP6305 AFTP6307AFTP6307

12

Bluetooth Module conn.

BLUETOOTH_DET#

12

DY

R6301

100KR2J-1-GP

1

WLAN_ACT BDC_ON

1

BLUETOOTH_EN BT_LED

1

BLUETOOTH_GPIO3

1

BLUETOOTH_GPIO5

1

BT_ACT BLUETOOTH_EN WLAN_ACT

12

EC6301

DY

R6302

10KR2J-3-GP

SC220P50V2KX-3GP

1 3

DY

5 7

9 11 13

HRS-CONN14D-GP-U1

20.F0987.014

2nd = 20.F1500.014

0709 Modify: PM confirmed there is no stand-alone BT module, so DY BT1 connector, add BT enable signal and 5V_S5 power option on WLAN connector pin 51. 0712 Modify: Stuff BT relatek component to verify function.

BT1

15 NP1 2

4 6 8 10 12 14 NP2 16

A00 1224 Update BT1

BT_ACT

USB_PP3 USB_PN3

1

AFTP6306AFTP6306

AFTP6309AFTP6309 AFTP6310AFTP6310 AFTP6308AFTP6308 AFTP6311AFTP6311 AFTP6312AFTP6312 AFTP6313AFTP6313

WLAN_ACT

1

BLUETOOTH_EN

1

BT_ACT

1

3D3V_S0

1

USB_PP3

1

USB_PN3

1

3D3V_S0

x01 change tolerant 20091118

12

C6301

C6301 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

0721 Modify: Change C6301 to 78.22510.5BL follow common parts data base.

DY

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Bluetooth

1

of

63 108Tuesday, January 04, 2011

A00

5

D D

4

3

2

1

Finger Printer Connector

0707 Modify: Add FP_DET# signal on FP1 pin1. 0715 Modify: Add FP_DET# signal on FP1 pin1. 0806 Swap pin. 0810 Change to 4 pin. 0827 Change to 6 pin.

C C

1123 X02 Modify: Add C6402 0.1uF,C6403 180pF and stuff C6401 47pF from RF fine tune result.

3D3V_S0

12

EC6401

Biometric_USBPN Biometric_USBPP

12

EC6402

SC47P50V2JN-3GP

SCD1U10V2KX-4GP

12

EC6403

SC180P50V2JN-1GP

FP1

7 1 2

3 4

DN15

5 6

8

ACES-CON6-13-GP

20.K0320.006

2nd = 20.K0382.006

DN15

R6403

USB_PN218

0917 X01 Modify: stuff TR6401 and un-stuff R6403,R6404 at X01 stage from EMC Neo suggestion.

B B

A A

5

USB_PP218

4

1 2

A00 1229

R6404

1 2

DN15

0R2J-2-GP

Biometric_USBPN

Biometric_USBPP

3

AFTP42DYAFTP42 AFTP43DYAFTP43 AFTP44DYAFTP44

DY DY DY

3D3V_S0

1

Biometric_USBPN

1

Biometric_USBPP

1

0615 Modify: Change FP1 connector part number to 20.K0320.004 base on ME EMN and DXF. 0630 Modify: Change FP1 connector part number to 20.K0320.006 base on ME EMN and DXF. 0707 Modify: Reassign Figer print pin define base on EXCEL FILE. 0713 Modify: Reassign Figer print pin define base on EXCEL FILE. Removed FP_DET# on FP1.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

RESERVED

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

64 108Tuesday, January 04, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

RESERVED

1

of

65 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

66 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

67 108Tuesday, January 04, 2011

A00

5

4

3

2

1

SSID = User.Interface

0706 Modify:

FRONT POWER LED

Need change to LOW actived from KBC GPIO

PWRLED#_C

D D

RN6802

PWRLED#27

SATA_LED#21

1 2 3

4

SRN15KJ-3-GP

SATA_LED#_C

SATA HDD LED(White)

C C

Battery LED2(WHITE_LED)

Need change to LOW actived from KBC GPIO

0702 Modify: Rename CHARGE_LED# to CHG_AMBER_LED# Rename DC_BATFULL# to BATT_WHITE_LED#.

BATT_WHITE_LED#27

CHG_AMBER_LED#27

RN6801

1 2 3

SRN15KJ-3-GP

WHITE_LED_BAT#

4

AMBER_LED_BAT#

Q6801

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

Q6805

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

E C

5V_S5

12

EC6801

DY

SC220P50V2KX-3GP

5V_S0

SATA_LED_R

Battery LED1(AMBER_LED)

Need change to LOW actived from KBC GPIO

TPLOCK LED

B B

0629 Modify

R6807

TP_LOCK_LED#27

1 2

15KR2J-1-GP

Q6804_B

Need change to LOW actived from KBC GPIO

A A

0715 Modify: Removed PWR_BTN_LED# control circuit base on Dell feedback.

5

Q6804

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

5V_S0

E

TP_LOCK_LED_R TP_LOCK_LED_A

C

KBC_PWRBTN#27

4

NEED confirm with ME actual FPOWER_LED part number.

1 2

R6806 390R2J-1-GPR6806 390R2J-1-GP

1 2

R6808 1KR2J-1-GPR6808 1KR2J-1-GP

1 2

R6811 1KR2J-1-GPR6811 1KR2J-1-GP

FPOWER_LED_ALED_PWR

POWER_SW _LED_B

POWER_SW _LED_C

X02 1116

1 2

R6812 390R2J-1-GPR6812 390R2J-1-GP

12

DY

EC6810

SC220P50V2KX-3GP

Q6807

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

Q6808

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

A00 20110103

12

DY

EC6803

SC220P50V2KX-3GP

0706 Modify: Change TP_LOCK_LED1 part number to

83.19217.J70 base on latest EMN and DXF.

5V_S5

E

WHITE_LED_BAT BAT_WHITE

C

5V_S5

E C

R6813

1 2

390R2J-1-GP

0923 X01 Modify: Add 2nd source 83.00190.Z70 on TPLOCKLED1 TPLOCKLED2 from Sourcer Anya suggestion.

1 2

R6802 100R2J-2-GPR6802 100R2J-2-GP

FPLED1

AK

1 2

83.01221.R70

2nd = 83.00110.R70

HDLED1

HDD_LED_A

DY

1 2

83.01221.R70

A00 1229 delete Liteon for package

1 2

R6801 390R2J-1-GPR6801 390R2J-1-GP

12

EC6807

SC220P50V2KX-3GP

1 2

R6803 390R2J-1-GPR6803 390R2J-1-GP

12

EC6809

DY

SC220P50V2KX-3GP

NEED confirm with ME actual HDD_LED part number.

KBC_PWRBTN#_C POWER_SW _LED_C POWER_SW _LED_B

Change FPOWER_LED part number to

83.01221.R70 base on latest EMN and DXF.

A00 1223

3

LED-W-27-GP

A00 1229 delete Liteon for package

NEED confirm with ME actual HDD_LED part number.

A00 1223

3

AK

LED-W-27-GP

2nd = 83.00110.R70

0706 Modify: Change HDD_LED part number to

83.01221.R70 base on latest EMN and DXF.

0923 X01 Modify: Add 2nd source 83.00110.J70 on FPOWERLED1 HDDLED1,WLANLED1 from Sourcer Anya suggestion.

NEED confirm with ME actual HDD_LED part number.

A00 1223

CHLED1

+

2

+

1

LED-OW-8-GP

83.01222.X80

BAT_AMBERAMBER_LED_BAT

TPLED2

A K

DN15

LED-Y-57-GP

83.01921.P70

2nd = 83.00190.S7A

TPLED1

A K

DQ15

LED-Y-57-GP

83.01921.P70

2nd = 83.00190.S7A

PWRBT1

5 1 2

DQ15

3 4

6

ACES-CON4-10-GP-U

20.K0320.004

2nd = 20.K0382.004

3

83.01222.X80

2nd = 83.00327.D70

0923 X01 Modify: Add 2nd source 83.00327.D70 on CHARGERLED1from Sourcer Anya suggestion.

0706 Modify: Change TP_LOCK_LED part number to

83.19217.J70 base on latest EMN and DXF.

A00 20110103

A00 1223

WHITE

-

3

ORANGE

A00 delete 83.01108.070

0706 Modify: Add PWRBTN2 for DQ15,PWRBTN1 FOR DN15.

KBC_PWRBTN#_C POWER_SW _LED_C POWER_SW _LED_B

WLAN_LED

0706 Modify: WLAN__LED# rename to WLAN_WWAN_LED#.

R6814

WLAN_W W AN_LED#63,82

A00 1223

PWRBT2

5 1 2

DN15

3 4

6

ACES-CON4-10-GP-U

20.K0320.004

2nd = 20.K0382.004

AFTP6801AFTP6801

1

AFTP6802AFTP6802

1

AFTP6803AFTP6803

1

2

1 2

LED-W-27-GP

83.01221.R70

2nd = 83.00110.R70

A00 1229 delete Liteon for package

0706 Modify: Change WLAN_LED part number to

83.01221.R70 base on latest EMN and DXF.

0923 X01 Modify: Add 2nd source 83.00110.J70 on FPOWERLED1 HDDLED1,WLANLED1 from Sourcer Anya suggestion.

Q6806

0629 Modify

15KR2J-1-GP

WLED1

3

AK

12

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Q6806

R2

Q6806_B

A00 1223

WLAN_LED_A WLAN_LED_R

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

1 2

R6815

R6815 390R2J-1-GP

390R2J-1-GP

LED Bard/Power Button

QUEEN 15

5V_S0

E C

12

DY

EC6811

SC220P50V2KX-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

68 108

1

A00

5

4

3

2

1

SSID = KBC

Internal KeyBoard Connector

0630 Modify:

D D

C C

CAP_LED:(Default HIGH actived) Connect to KB driving internal LED directly.(MAX 25mA)

B B

Change KB1 part number to 20.K0565.030 base on ME updated EMN and DXF.

KB1

31 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32

JAE-CON30-7-GP

20.K0565.030

2nd = 20.K0592.030

0915 X01 Modify: un-stuff R6907 and stuff R6905,Q6902,R6906 for 5V drive CAP LED.

KROW7 KROW6 KROW4 KROW2 KROW5 KROW1 KROW3 KROW0 KCOL5 KCOL4 KCOL7 KCOL6 KCOL8 KCOL3 KCOL1 KCOL2 KCOL0 KCOL12 KCOL16 KCOL15 KCOL13 KCOL14 KCOL9 KCOL11 KCOL10

CAP_LED27

1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

High Active from KBC GPIO.

AFTP45AFTP45

AFTP46AFTP46 AFTP47AFTP47 AFTP48AFTP48 AFTP49AFTP49 AFTP50AFTP50 AFTP51AFTP51 AFTP52AFTP52 AFTP53AFTP53 AFTP54AFTP54 AFTP55AFTP55 AFTP56AFTP56 AFTP57AFTP57 AFTP58AFTP58 AFTP59AFTP59 AFTP60AFTP60 AFTP61AFTP61 AFTP62AFTP62 AFTP63AFTP63 AFTP64AFTP64 AFTP65AFTP65 AFTP66AFTP66 AFTP68AFTP68 AFTP67AFTP67 AFTP69AFTP69 AFTP70AFTP70

1

1 2

CAP_LED_R

AFTP72AFTP72

R6905

15KR2J-1-GP

KROW[0..7] 27

KCOL[0..16] 27

KB_DET# 21

CAP_LED_R

CAP LED CONTROL

Q6902

Q6902_B

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

5V_S5

R2

E C

1 2

DY

R6907 100R2J-2-GP

X02 1116

1 2

R6906 1KR2J-1-GPR6906 1KR2J-1-GP

CAP_LED_R

CAP_LED_RCAP_LED_Q

SSID = Touch.Pad

0624 Modify: Removed TP LOCKED CONTROL combin with KEYBOARD Function KEY.

0713 Modify: Change TPAD1 power source to 3D3V_S0 from 5V_S0 base on DELL latest spec A02.

TouchPad Connector

TP_VDD

0721 Modify: SWAP RN6901

1

23

RN6901

RN6901 SRN10KJ-5-GP

SRN10KJ-5-GP

4

TPCLK27

TPDATA27

12

DY

C6902

SC33P50V2JN-3GP

C6902

DY

C6903

C6903 SC33P50V2JN-3GP

SC33P50V2JN-3GP

0927

AFTP73AFTP73 AFTP74AFTP74 AFTP75AFTP75

TP_VDD

AFTP71AFTP71

TP_VDD

1

TPCLK

1

TPDATA

1

0630 Modify: Change TPAD1 part number to 20.K0320.006 base on ME updated EMN&DXF. 0712 Modify: Change TPAD1 part number to 20.K0320.004 from 20.K0320.006.

12

C6901

C6901 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

TPAD1

6 4

3 2

1 5

1

ACES-CON4-10-GP-U

20.K0320.004

2nd = 20.K0382.004

0707 Modify: Change TPAD1 pin define to follow TOUCH PAD DATASHEET. 0713 Modify: Change TPAD1 pin define to follow TOUCH PAD DATASHEET.

0715 Modify: Add R6908,R6909 for TPAD1 co-lay power option.

R6908

1 2

DY

0R2J-2-GP

0R2J-2-GP R6909

R6909

1 2

0R2J-2-GP

5V_S0TP_VDD

3D3V_S0

KB Backlight Connector

+5V_KB_BL5V_S0

F6901

1 2

DY

FUSE-D5A6V-2-GP

R6902

DN15

KB_LED_BL_DET18

R6902 0R2J-2-GP

0R2J-2-GP

KB_BL_CTRL27

1 2

0624 Modify: Change KB Backlight control all of related circuit component column to VOSTRO from DY. 0708 Modify: R6904 change to 51K 0402 from 100ohm for KB_LED_BL_DET to PCH GPIO. updated KBLIT1 pin define base on KB DATA SHEET.

A A

5

12

DN15

1 2

12

C6905

C6905 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DN15

R6904

DN15

51KR2J-1-GP

R6903

100KR2J-1-GP

12

DN15

4

KB_LED_DET_C

12

C6906

DY

R6901

R6901 100KR2J-1-GP

100KR2J-1-GP

MAX 260mA

KB_BL_CTRL#

SCD1U10V2KX-5GP

ACES-CON4-34-GP

DS

Q6901

Q6901 P8503BMG-GP

G

P8503BMG-GP

DN15

84.P8503.031

2nd = 84.03404.C31

KBLIT1

5 1

2

DN15

3 4 6

20.K0589.004

2nd = 20.K0613.004

+5V_KB_BL

KB_LED_DET_C

KB_BL_CTRL#

1

1 1 1

AFTP82AFTP82

AFTP76AFTP76 AFTP77AFTP77 AFTP78AFTP78

0901 X01 Modify: Change KBLIT1 to 20.K0320.004 from

20.K0218.004 base on ME updated X01 DXF&EMN. Re-assign KBLIT1 pin define sync with DQ15_NV. 0914 X01 Modify: Add 2nd source 20.K0382.004 on KBLIT1 base on updated connector list. 0923 X01 Modify: Change KBLIT1 part number to 20.K0589.004 and re-assign pin define base on Roy updated.

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

Key Board/Touch Pad

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

69 108

1

A00

5

D D

C C

4

TCN-CONN10C-GP

AFTP83 AFTE14P-GPAFTP83 AFTE14P-GP

3D3V_S5

1

LID_CLOSE#

1

AFTP84 AFTE14P-GPAFTP84 AFTE14P-GP

TCN-CONN10C-GP

1110 X02 Modify: Add 2nd 20.F0962.010 on HALL1 from ME updated connector list.

3

HALL1

12

NP1NP2

13 10

9 8 7

16

20.F1655.010

2nd = 20.F0962.010

11 1 2

3 4 56

14

15

0729

LID_CLOSE# 27

3D3V_S5

AFTP85

1

AFTE14P-GP

0804 swap

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Hall Sensor

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

70 108

1

A00

5

D D

4

3

2

1

3D3V_S0

LPC_AD021,27 LPC_AD121,27 LPC_AD221,27

C C

B B

LPC_AD321,27

LPC_FRAME#21,27

PLT_RST#5,18,27,75,82,83

CLK_PCI_LPC18

A00 1229 DB1 change to ZZ.00PAD.Y41(solder kmask type) and keep un-stuffat X-Build stage

DB1

11

1 2

3 4 5

DY

6 7 8

9 10 12

PAD-10P-177042-GP

ZZ.00PAD.Y41

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Dubug connector

of

71 108Tuesday, January 04, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

72 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

73 108Tuesday, January 04, 2011

A00

5

SSID = SDIO

4

3

2

1

3D3V_CARD_S0

D D

C C

DY

12

Close to CARD1

12

DY

C7401

SCD1U10V2KX-5GP

12

C7402

SCD1U10V2KX-5GP

12

C7403

C7404

SCD01U16V2KX-3GP

12

C7405

DY

SC10U6D3V5MX-3GP

SC2D2U6D3V3MX-1-GP

SD/XD/MS/MMC+ Card Reader

0906 X01 Modify: Change CARD1 to 20.I0129.001 from 62.10051.931

3D3V_CARD_S0

SP432 SP332 SP1332 SP1232

SP832 SP632 SP132 SP1032

SP1432 SP232 SP132

SP932 SP1232 SP832 SP532

SP1132 SP932 SP732 SP532

from ME double updated latest DXF&EMN on X01.

CARD1

P13

SD_VCC

P22

MS_VCC

18

XD_VCC

P4

SD_DAT0

P3

SD_DAT1

P25

SD_DAT2

P23

SD_DATA3

P10

SD_CLK

P1

SD_CD

P2

SD_WP

P19

SD_CMD

P9

MS_BS

P16

MS_INS

P20

MS_SCLK

P12

MS_DATA0

P11

MS_DATA1

P14

MS_DATA2

P18

MS_DATA3

P21

MMC_DATA4

P17

MMC_DATA5

P8

MMC_DATA6

P5

MMC_DATA7

CARD-PUSH-46P-1-GP-U

20.I0129.001

2nd = 20.I0135.001

SD_WP_COM/SDIO_GND

SD_CD_COM/SDIO_GND

XD_CD

XD_R/B

XD_RE

XD_CE XD_CLE XD_ALE

XD_WE

XD_WP_IN

XD_D0

XD_D1

XD_D2

XD_D3

XD_D4

XD_D5

XD_D6

XD_D7

SD_GND SD_GND

MS_GND MS_GND

XD_GND XD_GND

NP1 NP2

1119 X02 Modify: Add 2nd 20.I0135.001 on HALL1 from ME updated connector list.

1 2 3 4 5 6 7 8

10 11 12 13 14 15 16 17

P26 P27 P7 P15

P6 P24

9 19

NP1 NP2

XD_CD# 32 SP1 32 SP2 32 SP3 32 SP4 32 SP5 32 SP6 32 SP7 32

SP8 32 SP9 32 SP10 32 SP11 32 SP12 32 SP13 32 SP14 32 XD_D7 32

B B

For EMI Reserved

SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 SP13 SP14 XD_D7 XD_CD#

12

EC7404

SC220P50V2KX-3GP

DY

12

EC7405

12

DY

EC7406

SC220P50V2KX-3GP

12

DY

A A

5

DY

EC7402

SC220P50V2KX-3GP

DY

EC7403

SC220P50V2KX-3GP

4

12

DY

EC7407

EC7408

SC220P50V2KX-3GP

DY

12

EC7409

12

DY

EC7410

SC220P50V2KX-3GP

3

12

DY

EC7411

SC220P50V2KX-3GP

12

DY

EC7412

SC220P50V2KX-3GP

12

DY

EC7413

SC220P50V2KX-3GP

12

DY

EC7414

SC220P50V2KX-3GP

12

DY

EC7415

SC220P50V2KX-3GP

12

DY

EC7416

SC220P50V2KX-3GP

12

EC7417

2

SC220P50V2KX-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

SD/XD/MS/MMC Card CONN

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

QUEEN 15

of

74 108Tuesday, January 04, 2011

1

A00

5

D D

1122 X02 Modify: Change TR7501 CM choke to 69.10103.041 and un-stuff R7501,R7502 from EMC Neo Suggestion. Change R7501,R7502 to 0603 from 0402.

USB_PP1318

C C

USB_PN1318

3D3V_S5

AFTE14P-GP

AFTP107

AFTE14P-GP

AFTP108

AFTE14P-GP

AFTP109

AFTE14P-GP

AFTP110

AFTE14P-GP

AFTP111

AFTE14P-GP

AFTP112

AFTE14P-GP

AFTP113

AFTE14P-GP

AFTP114

AFTE14P-GP

AFTP115

AFTE14P-GP

AFTP116

B B

AFTE14P-GP

AFTE14P-GP AFTE14P-GP

AFTE14P-GP

AFTP116 AFTP117

AFTP117 AFTP118

AFTP118 AFTP119

AFTP119 AFTP120

AFTP120 AFTP121

AFTP121 AFTP122

AFTP122 AFTP123

AFTP123 AFTP124

AFTP124

1

3D3V_S0

1

1D5V_S0

1

USB_PN13_R

1

USB_PP13_R

1

CLK_PCIE_NEW_REQ#_CON

1

SMB_CLK

1

SMB_DATA

1

PM_SLP_S3#

1

PM_SLP_S4#

1

PLT_RST#

1

CLK_PCIE_NEW#_C

1

CLK_PCIE_NEW_C

1

PCIE_TXN8_CON

1

PCIE_TXP8_CON

1

PCIE_RXN8_CON

1

PCIE_RXP8_CON

1

PCIE_WAKE#_CON

1

4

69.10103.041

2nd = 69.10084.071

FILTER-4P-6-GP

DN15

3 4

TR7501

3

0824 X01 Modify: Due to our NEW1 change to Express card to

1D5V_S0_CARD Max. 650mA, Average 500mA. 3D3V_S0_CARD Max. 1300mA, Average 1000mA 3D3V_S5_CARDAUX Max. 275mA

bottom side so re-assign NEW1 pin define same as DQ15-NV. 0906 X01 Modify: Add 2nd source 20.K0382.026 on NEW1 base on updated connector list.

SB-25

1 2

DN15

PCIE_TXP820 PCIE_TXN820

PCIE_RXP820 PCIE_RXN820

CLK_PCIE_NEW20 CLK_PCIE_NEW#20

CLK_PCIE_NEW_REQ#20

3D3V_S0

USB_PP13_R

A00 1229

12

USB_PN13_R

PM_SLP_S4#19,27,46 PM_SLP_S3#19,27,36,37,47 PLT_RST#5,18,27,71,82,83

3D3V_S5

PCIE_WAKE#27,82

1D5V_S0

SMB_DATA20 SMB_CLK20

0913 X01 Modify: Rename NEW1 pin24,25 to USB_PP13_R&USB_PN13_R. Rename NEW1 pin8,9 to CLK_PCIE_NEW_C&CLK_PCIE_NEW#_C

DN15

R7505 0R2J-2-GP

1 2

DN15

R7506 0R2J-2-GP

1 2

DN15

R7508 0R2J-2-GP

1 2

DN15

R7507 0R2J-2-GP

1 2

DN15

R7503 0R2J-2-GP

1 2

DN15

R7504 0R2J-2-GP

1 2

DN15

R7509 0R2J-2-GP

1 2

DN15

R7510 0R2J-2-GP

SMB_DATA SMB_CLK PM_SLP_S4# PM_SLP_S3#

PLT_RST#

USB_PP13_R USB_PN13_R

PCIE_TXP8_CON PCIE_TXN8_CON

PCIE_RXP8_CON PCIE_RXN8_CON

CLK_PCIE_NEW_C CLK_PCIE_NEW#_C

CLK_PCIE_NEW_REQ#_CON

PCIE_WAKE#_CON

2

NEW1

27

1 2

3 4 5 6 7 8

9 10 11 12 13

DN15

14 15 16 17 18 19 20 21 22 23 24 25 26

28

ACES-CON26-6GP-U

20.K0320.026

2nd = 20.K0382.026

1

For EMI

CLK_PCIE_NEW#_C CLK_PCIE_NEW_C PCIE_TXN8_CON

EC7501

EC7502

1 2

DY

SC4D7P50V2CN-1GP

0913 X01 Modify: Add R7503,R7504 and reserved EC7501,EC7502 on CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion. 0921 X01 Modify: Add R7505~R7508 0ohm and reserved EC7503~EC7506 on PCIE_TX8&RX8 signal base on EMC Lance suggestion. Add R7509,R7510 0ohm and reserved EC7507,EC7508 on CLK_PCIE_NEW_REQ#&PCIE_WAKE# signal base on EMC Lance suggestion.

EC7502

1 2

DY

SC4D7P50V2CN-1GP

EC7505

1 2

DY

1 2

DY

SC4D7P50V2CN-1GP

EC7503

EC7506

1 2

DY

SC4D7P50V2CN-1GP

PCIE_TXP8_CON

PCIE_RXP8 PCIE_RXN8

EC7504

1 2

DY

SC4D7P50V2CN-1GP

DY

CLK_PCIE_NEW_REQ# PCIE_WAKE#

EC7507

EC7508

1 2

SC4D7P50V2CN-1GP

EC7508

1 2

DY

SC4D7P50V2CN-1GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Express Card

75 108Tuesday, January 04, 2011

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

76 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

77 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

78 108Tuesday, January 04, 2011

A00

5

SSID = User.Interface

4

3

2

1

D D

PCH_SMBCLK14,15,20,82 PCH_SMBDATA14,15,20,82

3D3V_S0

C C

09/0422 (#1) Just pull +3.3V_RUN ~ Ref. Rothschild (#2) FAE/ DY is ok, chip internal pull-up resistors (#3) From spec, Slave ADdress(SAD) is 001110xb Pull HIGH SAD is 0011101b Pull GND SAD is 0011100b

B B

Free Fall Sensor

3D3V_S0

12

DY

12

C7902

DY

SCD1U10V2KX-4GP

6

VDD

DY

1

VDD_IO

U7901

14

SCL/SPC

13

SDA/SDI/SDO

12

SDO

7

CS

3

RESERVED#3

11

RESERVED#11

DE351DLTR8-GP

74.00351.0B3

0701 Modify: Change G-SENSOR U7901 back to DE351DLTR8. 0705 Modify: Change DUMMY column to:MAIN source->ADI solution. second source->ST solution.

C7901

SC10U6D3V5MX-3GP

PCH_SMBDATA

R7901

DY

HDD_FALL_SDO

100KR2J-1-GP

1 2

INT1 INT2

GND GND GND GND

8 9

2 4 5 10

3D3V_S0

DY

12

R7902

R7902 100KR2J-1-GP

100KR2J-1-GP

HDD_FALL_INT1PCH_SMBCLK

Note

- no via, trace, under the sensor (keep out area around 2mm)

- stay away from the screw hole or metal shield soldering joints

- design PCB pad based on our sensor LGA pad size (add 0.1mm)

- solder stencil opening to 90% of the PCB pad size

- mount the sensor near the center of mass of the NB as possible as you can

3D3V_S0

Q7901

DY

12

R7903

R7903 100KR2J-1-GP

100KR2J-1-GP

FALL_INT2

2

34

5

1 2

DY

1

DY

6

R7905

R7905 0R2J-2-GP

0R2J-2-GP

DY

5V_S03D3V_S0

12

R7906

R7906 10KR2J-3-GP

10KR2J-3-GP

0802

FFS_INT2 56

FFS_INT2_R 18

HDD_FALL_INT1 18

12

2nd = 84.DM601.03F

R7904

DY

100KR2J-1-GP

0706 Modify: R2220 and R7904 double PH.

FFS_INT2_R

2N7002KDW-GP

84.2N702.A3F

Note (1) Keep all signals are the same trace width. (included VDD, GND). (2) No VIA under IC bottom.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Free Fall Sensor

79 108Tuesday, January 04, 2011

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

80 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

81 108Tuesday, January 04, 2011

A00

5

IO Board CONN 80 pin

:/$186%

::$186%

D D

C C

::$1:/$160%86

B B

A A

A00 1229

86%3&,( 86%3&,(

1112 X02 Modify: Dell required us to disable PCIE port of WWAN slot ,If PCIE port 1 is disabled, it will cause all PCIE port disabled,so change WWAN to PCIE port 3 from port1 at ST stage.

CLK_PCIE_WWAN_REQ#20

USB_PP1118 USB_PN1118

PCIE_CLK_LAN_REQ#20

USB_PP418

::$13&,(

X02 1116

::$13&,(

/$13&,(

:/$13&,( :/$13&,(

86%3&,(

5

USB_PN418

PCIE_TXP320 PCIE_TXN320

PCIE_RXN320 PCIE_RXP320

PCIE_TXN220 PCIE_TXP220

PCIE_RXP220 PCIE_RXN220

PCIE_RXN420 PCIE_RXP420

PCIE_TXP420 PCIE_TXN420

PCIE_RXN520 PCIE_RXP520

PCIE_TXP520 PCIE_TXN520

3D3V_S5

USB30_SMI#18

WLAN_ACT63

USB3_PEGB_CLKREQ#20

PCH_SMBDATA14,15,20,79

USB3_PWR_ON27

PCH_SMBCLK14,15,20,79

0906 X01 Modify: Add 2nd source 20.F0085.040 on CRTBD1 base on updated connector list. 0915 X01 Modify: Re-assign CRTBD1 pin define base on EMC suggestion.

5V_CRT_S0_R

3D3V_S0

CRT_HSYNC_CON CRT_VSYNC_CON

PSID_EC27

RCID27

USB_PN118 USB_PP118

0625 Modify: Change CRTBD1 part number to 20.F0957.030 from 20.F1521.030 base on EMN updated part number. 0720 Modify: Change CRTBD1 connector to 20.F1121.040 from 30pin base on ME Double provide final solution. 0721 Modify: re-assign CRTBD1 pin define to follow Joseph release PIN define.

CRT Board Connector

4

2 4

6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80

ACES-CONN80D-1-GP

20.F1849.080

2nd = 20.F1908.080

CRTBD1

2 4

6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 46

ACES-CONN40D-GP

20.F1121.040

2nd = 20.F0085.040

3rd = 20.F1932.040

4

82 NP1 1

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 NP2 81

IOBD1

42

NP1NP2

4143 1

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 44

45

1120 X02 Modify: Reserved R8211,R8212 0ohm 0805 on CRTBD1 pin37,39 to separate EATA and CRT USB power in ST build.

A00 0103 add 3rd T-conn(20.F1932.040) at XBuild batch run

A00

R8206

1 2

0R0603-PAD-2-GP

A00

R8207

1 2

0R0603-PAD-2-GP

AUD_AGND

0913 X01 Modify: Change R8201~R8203 to 470ohm from 100ohm. Add RN8209 PH 5V_S5 on MEDIA_LED1~3# for PWM OD mode.

AFTP8201AFTP8201 AFTP8202AFTP8202 AFTP8203AFTP8203 AFTP8204AFTP8204 AFTP8205AFTP8205 AFTP8206AFTP8206 AFTP8207AFTP8207

CRT_BLUE

CRT_GREEN CRT_RED

AD+AD+

CRT_DDC_CLK CRT_DDC_DATA

5V_S5 3D3V_S5 5V_USB2_S3

1123 X02 Modify: Removed R8211,R8212 and connect 5V_USB2_S3 to CRTBD1 pin 37 directly.

2nd = 20.K0465.008

0810

CRT_DDC_DATA17 CRT_DDC_CLK17

CRT_RED17 CRT_GREEN17 CRT_BLUE17

3

CLK_PCIE_LAN 20 CLK_PCIE_LAN# 20 CLK_PCIE_WWAN 20 CLK_PCIE_WWAN# 20

CLK_PCIE_WLAN 20 CLK_PCIE_WLAN# 20 CLK_PCIE_USB3 20 CLK_PCIE_USB3# 20

3G_EN 22

3D3V_S0

1D5V_S0 5V_S5

CLK_PCIE_WLAN_REQ# 20

E51_TXD 27

E51_RXD 27

WIFI_RF_EN 27

WLAN_W W AN_LED# 63,68

PM_LAN_ENABLE 27 PLT_RST# 5,18,27,71,75,83

PCIE_WAKE# 27,75

BLUETOOTH_EN 27,63 BT_ACT 63

AUD_HP1_JD# 29

EXT_MIC_JD# 29

MIC_IN_L 29

MIC_IN_R 29

AUD_HP1_JACK_L2 29

AUD_HP1_JACK_R2 29

X02 1122

MEDIA1_1

1

MEDIA1_2

1

MEDIA1_3

1

5V_S5

1

INSTANT_ON#

1

DATA_RECOVERY#

1

MEDIA_BTN3#

1

MEDIA1

9 1

MEDIA1_1

2

MEDIA1_2

3

MEDIA1_3

4 5 6 7 8

10

ACES-CON8-19-GP

20.K0320.008

5V_CRT_S0_R

CRT_DDC_DATA CRT_DDC_CLK

CRT_RED

CRT_GREEN

CRT_BLUE

3

/$1&/.

::$1&/.

:/$1&/. 86%&/.

0916 X01 Modify: Keep original X00 IOBD1 pin define. 0917 X01 Modify: Change IOBD1 part number to 20.F1849.080 base on Double updated latest DXF&EMN. 0920 X01 Modify: Re-assign IOBD1 pin define due to updated connector pin define is different as before. Add R8206,R8207 to isolated AGND and DGND.

1122 X02 Modify: stuff EC8201,EC8202 0.1u(closed H3) between GND and GND from EMC Neo suggestion. stuff EC8206 between 3D3V_S5 and GND from EMC Neo suggestion.

EC8201

SCD1U50V3KX-GP

EC8201

SCD1U50V3KX-GP

12

MEDIA_LED1# MEDIA_LED2#

R8204 10KR2J-3-GP

MEDIA_LED3#

R8205 10KR2J-3-GP

R8205 10KR2J-3-GP R8208 10KR2J-3-GP

1119 X02 Modify: Reserved EC8203~EC8205 470p on all of MEDIA_LED# signal from EMC Neo suggestion.

5V_S5

R8201

1 2

1KR2J-1-GP

1 2 3

RN8201

RN8201 SRN1KJ-7-GP

SRN1KJ-7-GP

20101220 R8202 R8203 for change to parallel resistor

1110 X02 Modify: Add 2nd 20.K0465.008 on MEDIA1 from ME updated connector list. 1112 X02 Modify: change Media resistor from 430 ohm to 1K on both DQ/DN15(R8201, R8202, R8203) for Media button LED light spot issue

A00 1224

R8211

1 2

DY

0R3J-0-U-GP

1 2

F8201

FUSE-1D1A6V-4GP-U

69.50007.691

2nd = 69.50007.771

1122 X02 Modify: Swap RN8205 pin4,3 and pin2,1 each other base on Connie swap report.

R8208 10KR2J-3-GP

MEDIA_LED1# MEDIA_LED2#

EC8203 SC470P50V-2-GPEC8203 SC470P50V-2-GP

MEDIA_LED3#

EC8204 SC470P50V-2-GPEC8204 SC470P50V-2-GP EC8205 SC470P50V-2-GPEC8205 SC470P50V-2-GP

A00

4

5V_CRT_S0 5V_S0

2 1

CRT_VSYNC17 CRT_HSYNC17

3D3V_S5

EC8202

SCD1U50V3KX-GP

EC8202

SCD1U50V3KX-GP

EC8206

SCD1U50V3KX-GP

EC8206

12

1 2

DY

1 2

DY

1 2

DY

1 2 1 2 1 2

High active

MEDIA_LED1# 27 MEDIA_LED2# 27 MEDIA_LED3# 27 INSTANT_ON# 27

DATA_RECOVERY# 27

MEDIA_BTN3# 27

D8201

CH551H-30PT-GP

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

83.R5003.C8F

SCD1U50V3KX-GP

12

5V_S5

RN8205

1 2 3

SRN22-3-GP

2

0814

CRT_VSYNC_CON

4

CRT_HSYNC_CON

A00 1224

1120 X02 Modify: Add RN8205 base on HSYNC&VSYNC report.

2

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

IO Board Connector

Size Document Number Rev

A3

Date: Sheet

IO Board Connector

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

82 108Tuesday, January 04, 2011

1

A00

5

Optumus

1 2

R8323

A00

0R0402-PAD-2-GP

B A GND

VCC

DY

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Optimus Optimus

Optimus

Y

5 4

PEX_RST#

1 2 1 2

3D3V_S5

0927

PEX_RST#

DY

R8314 100KR2J-1- GP

1 2

NV_PEG_CLKREQ#

R8315 200R2F-L-GP

DY

PEXTSTCLK_OUT

1 2

PEXTSTCLK_OUT#

C8337 SCD1U10V2KX-5GP

C8337 SCD1U10V2KX-5GP C8333 SCD1U10V2KX-5GP

C8333 SCD1U10V2KX-5GP

C8336 SCD1U10V2KX-5GP

C8336 SCD1U10V2KX-5GP C8335 SCD1U10V2KX-5GP

C8335 SCD1U10V2KX-5GP

C8332 SCD1U10V2KX-5GP

C8332 SCD1U10V2KX-5GP C8328 SCD1U10V2KX-5GP

C8328 SCD1U10V2KX-5GP

C8331 SCD1U10V2KX-5GP

C8331 SCD1U10V2KX-5GP C8327 SCD1U10V2KX-5GP

C8327 SCD1U10V2KX-5GP

C8329 SCD1U10V2KX-5GP

C8329 SCD1U10V2KX-5GP C8325 SCD1U10V2KX-5GP

C8325 SCD1U10V2KX-5GP

C8324 SCD1U10V2KX-5GP

C8324 SCD1U10V2KX-5GP C8322 SCD1U10V2KX-5GP

C8322 SCD1U10V2KX-5GP

C8323 SCD1U10V2KX-5GP

C8323 SCD1U10V2KX-5GP C8320 SCD1U10V2KX-5GP

C8320 SCD1U10V2KX-5GP

C8319 SCD1U10V2KX-5GP

C8319 SCD1U10V2KX-5GP C8318 SCD1U10V2KX-5GP

C8318 SCD1U10V2KX-5GP

C8316 SCD1U10V2KX-5GP

C8316 SCD1U10V2KX-5GP C8315 SCD1U10V2KX-5GP

C8315 SCD1U10V2KX-5GP

C8314 SCD1U10V2KX-5GP

C8314 SCD1U10V2KX-5GP C8313 SCD1U10V2KX-5GP

C8313 SCD1U10V2KX-5GP

C8312 SCD1U10V2KX-5GP

C8312 SCD1U10V2KX-5GP C8310 SCD1U10V2KX-5GP

C8310 SCD1U10V2KX-5GP

C8311 SCD1U10V2KX-5GP

C8311 SCD1U10V2KX-5GP C8309 SCD1U10V2KX-5GP

C8309 SCD1U10V2KX-5GP

C8308 SCD1U10V2KX-5GP

C8308 SCD1U10V2KX-5GP C8306 SCD1U10V2KX-5GP

C8306 SCD1U10V2KX-5GP

C8307 SCD1U10V2KX-5GP

C8307 SCD1U10V2KX-5GP C8305 SCD1U10V2KX-5GP

C8305 SCD1U10V2KX-5GP

C8304 SCD1U10V2KX-5GP

C8304 SCD1U10V2KX-5GP C8302 SCD1U10V2KX-5GP

C8302 SCD1U10V2KX-5GP

C8303 SCD1U10V2KX-5GP

C8303 SCD1U10V2KX-5GP C8301 SCD1U10V2KX-5GP

C8301 SCD1U10V2KX-5GP

PQ8309

PQ8309 2N7002K-2-GP

2N7002K-2-GP

DY

G

D

S

84.2N702.J31

2ND = 84.2N702.031

PEG_C_RXP0 PEG_C_RXN0

PEG_C_RXP1 PEG_C_RXN1

PEG_C_RXP2 PEG_C_RXN2

PEG_C_RXP3 PEG_C_RXN3

PEG_C_RXP4 PEG_C_RXN4

PEG_C_RXP5 PEG_C_RXN5

PEG_C_RXP6 PEG_C_RXN6

PEG_C_RXP7 PEG_C_RXN7

PEG_C_RXP8 PEG_C_RXN8

PEG_C_RXP9 PEG_C_RXN9

PEG_C_RXP10 PEG_C_RXN10

PEG_C_RXP11 PEG_C_RXN11

PEG_C_RXP12 PEG_C_RXN12

PEG_C_RXP13 PEG_C_RXN13

PEG_C_RXP14 PEG_C_RXN14

PEG_C_RXP15 PEG_C_RXN15

U8301

DGPU_HOLD_RST#18

PLT_RST#5,18,27,71,75,82

D D

PEG_RXP[0..15]4 PEG_RXN[0..15]4

PEG_TXP[0..15]4 PEG_TXN[0..15]4

C C

B B

A A

PLT_RST#

CLK_PCIE_VGA20

CLK_PCIE_VGA#20

1 2 3

74LVC1G08GW-1- GP

73.01G08.L04

2nd = 73.7SZ08.DAH

PEG_RXP0 PEG_RXN0

PEG_TXP0 PEG_TXN0

PEG_RXP1 PEG_RXN1

PEG_TXP1 PEG_TXN1

PEG_RXP2 PEG_RXN2

PEG_TXP2 PEG_TXN2

PEG_RXP3 PEG_RXN3

PEG_TXP3 PEG_TXN3

PEG_RXP4 PEG_RXN4

PEG_TXP4 PEG_TXN4

PEG_RXP5 PEG_RXN5

PEG_TXP5 PEG_TXN5

PEG_RXP6 PEG_RXN6

PEG_TXP6 PEG_TXN6

PEG_RXP7 PEG_RXN7

PEG_TXP7 PEG_TXN7

PEG_RXP8 PEG_RXN8

PEG_TXP8 PEG_TXN8

PEG_RXP9 PEG_RXN9

PEG_TXP9 PEG_TXN9

PEG_RXP10 PEG_RXN10

PEG_TXP10 PEG_TXN10

PEG_RXP11 PEG_RXN11

PEG_TXP11 PEG_TXN11

PEG_RXP12 PEG_RXN12

PEG_TXP12 PEG_TXN12

PEG_RXP13 PEG_RXN13

PEG_TXP13 PEG_TXN13

PEG_RXP14 PEG_RXN14

PEG_TXP14 PEG_TXN14

PEG_RXP15 PEG_RXN15

PEG_TXP15 PEG_TXN15

DGPU_PWROK22,92,93

5

PEX_RST# 51,85,86

AM16

AR13

AJ17 AJ18

AR16 AR17

AL17

AM17

AP17 AN17

AM18 AM19

AN19 AP19

AL19 AK19

AR19 AR20

AL20

AM20

AP20 AN20

AM21 AM22

AN22 AP22

AL22 AK22

AR22 AR23

AL23

AM23

AP23 AN23

AM24 AM25

AN25 AP25

AL25 AK25

AR25 AR26

AL26

AM26

AP26 AN26

AM27 AM28

AN28 AP28

AL28 AK28

AR28 AR29

AK29 AL29

AP29 AN29

AM29 AM30

AN31 AP31

AM31 AM32

AR31 AR32

AN32 AP32

AR34 AP34

DY

R8322

1 2

0R2J-2-GP

VGA2A

PEX_RST# PEX_CLKREQ#

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

PEX_REFCLK PEX_REFCLK#

PEX_TX0 PEX_TX0#

PEX_RX0 PEX_RX0#

PEX_TX1 PEX_TX1#

PEX_RX1 PEX_RX1#

PEX_TX2 PEX_TX2#

PEX_RX2 PEX_RX2#

PEX_TX3 PEX_TX3#

PEX_RX3 PEX_RX3#

PEX_TX4 PEX_TX4#

PEX_RX4 PEX_RX4#

PEX_TX5 PEX_TX5#

PEX_RX5 PEX_RX5#

PEX_TX6 PEX_TX6#

PEX_RX6 PEX_RX6#

PEX_TX7 PEX_TX7#

PEX_RX7 PEX_RX7#

PEX_TX8 PEX_TX8#

PEX_RX8 PEX_RX8#

PEX_TX9 PEX_TX9#

PEX_RX9 PEX_RX9#

PEX_TX10 PEX_TX10#

PEX_RX10 PEX_RX10#

PEX_TX11 PEX_TX11#

PEX_RX11 PEX_RX11#

PEX_TX12 PEX_TX12#

PEX_RX12 PEX_RX12#

PEX_TX13 PEX_TX13#

PEX_RX13 PEX_RX13#

PEX_TX14 PEX_TX14#

PEX_RX14 PEX_RX14#

PEX_TX15 PEX_TX15#

PEX_RX15 PEX_RX15#

N12P-GE-A1-GP

NV_PEG_CLKREQ#

4

PCI_EXPRESS

OPTIMUS

PEG_CLKREQ# 20

0728

4

1 OF 16

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_SVDD_3V3

NC#F7

NC#A2

NC#A7 NC#AA4 NC#AB4 NC#AB7 NC#AC5 NC#AD6 NC#AF6 NC#AG6

NC#AJ5

NC#AK15

NC#AL7

NC#B7

NC#C7 NC#D5 NC#D6 NC#D7

NC#E5

NC#E7

NC#F4

NC#G5

NC#H32

NC#P6

NC#U7

NC#V6

NC#Y4

VDD33

VDD_SENSE#D35

VDD_SENSE#P7 VDD_SENSE#AD20 GND_SENSE#AD19

GND_SENSE#R7

GND_SENSE#E35

PEX_PLLVDD

NC#AG20

PEX_TERMP

TESTMODE

Near BALLS Near BGA

AK16 AK17

12

C8342

AK21 AK24 AK27

0818

AG11

De-cap

AG12 AG13 AG15 AG16

Optimus

AG17 AG18 AG22 AG23 AG24

12

C8326

AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22

Optimus

AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16

Near BALLS

AG19 F7

A2 A7 AA4 AB4 AB7 AC5 AD6 AF6 AG6 AJ5 AK15 AL7 B7 C7 D5 D6 D7 E5 E7 F4 G5 H32 P6 U7 V6

Near BALLS

Y4

Optimus

J10 J11

12

C8341

J12 J13 J9

D35 P7 AD20 AD19 R7 E35

1V_VGA_S0

12

C8338

C8339

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

DY

Optimus

1V_VGA_S0

12

C8334

C8321

SCD1U10V2KX-5GP

DY

Optimus

0818 De-cap

3D3V_VGA_S0 3D3V_VGA_S0

12

C8330

SCD1U10V2KX-5GP

DY

Optimus

12

C8344

C8351

SCD1U10V2KX-5GP

DY

VGA_SENSE 92

GND_SENSE 92

120mA

Optimus

12

C8340

SCD1U10V2KX-5GP

PEX_PLLVDD

12

C8357

SC1U6D3V2KX-GP

Optimus

EBMS160808A121-GP

12

C8358

SC4D7U6D3V3KX-GP

68.00375.101

2ND = 68.00119.101

Optimus

AG14

Near BALLS Near BGA

AG20

PEX_TERMP

AG21

AP35

Optimus

PEX_TESTMODE

R8313

10KR2J-3-GP

0xDF5

12

R8301

R8301 2K49R2F-GP

2K49R2F-GP

Optimus

12

STRAP 2: DIS_DID_L N12P-GE PH = NC, PL = 30K(64.30025.6DL) N12P-GV1 PH = NC, PL = 15K(64.15025.6DL) N12M-GE PH = TBD, PL = TBD N11P-GE-A1 PH = TBD, PL = 10K N11P-GS-A1 PH= NC, PL = 4.99K

0818 De-cap

12

SC1U6D3V2KX-GP

Optimus

12

C8349

SCD1U10V2KX-5GP

Optimus

0728

12

C8363

SC1U6D3V2KX-GP

0723

Optimus

L8303

1 2

C8347

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

0728

Optimus

12

C8352

Optimus

DY

12

C8364

SC1U6D3V2KX-GP

Optimus

3

12

C8362

SC4D7U6D3V3KX-GP

12

C8350

SC4D7U6D3V3KX-GP

3D3V_VGA_S0

12

C8359

SC4D7U6D3V3KX-GP

1009

1V_VGA_S0

3

Optimus

1V_VGA_S0

C8348

C8356

SC22U6D3V5MX-2GP

12

SC10U6D3V3MX-GP

DY

12

C8317

SC4D7U6D3V3KX-GP

0818 De-cap

Logical Strap Bit Mapping Resistor Pull-up Pull-down 5Kohms 1000 0000 10Kohms 1001 0001 15Kohms 1010 0010 20Kohms 1011 0011 25Kohms 1100 0100 30Kohms 1101 0101 35Kohms 1110 0110 45Kohms 1111 0111

12

C8361

SC10U6D3V5KX-1GP

Optimus

STRAP0

STRAP1

STRAP2

PCI_DEVID[0]=0 PCI_DEVID[1]=0 PCI_DEVID[2]=1 PCI_DEVID[3]=0

0723

CLK_27M_VGA20

3D3V_VGA_S0

40K2R2F-GP

USER[0]=1 USER[1]=1 USER[2]=1 USER[3]=1

3GIO_PADCFG[0]=0 3GIO_PADCFG[1]=1 3GIO_PADCFG[2]=1 3GIO_PADCFG[3]=0

GPU_ROM_SCLK: DIS_DID_H N12P-GE PH = 15K(64.15025.6DL), PL = NC N12P-GV1 PH = 15K(64.15025.6DL), PL = NC N12M-GE PH = TBD, PL = TBD N11P-GE-A1 PH = 15K(64.15025.6DL), PL = NC N11P-GS-A1 PH = 15K(64.15025.6DL), PL = NC

Optiums

Optimus

L8301

1 2

0R0603-PAD-2-GP

A00

X02 11/29

12

R8306

R8306 10KR2J-3-GP

10KR2J-3-GP

Optimus

R8303

Optimus

SC10U6D3V3MX-GP

12

Optimus

12

C8345

C8360

SCD1U10V2KX-4GP

DY

1 2

CEC

STRAP_3V3 STRAP_MIOB

12

R8304

R8304 40K2R2F-GP

40K2R2F-GP

Optimus

Need check panel resolution 1366x768

Optimus

VIO_PLLVDD

12

C8355

C8346

SCD1U10V2KX-4GP

R8318

10KR2J-3-GP

Optimus

R8302

DY

0R2J-2-GP

C8354 SC 15P50V2JN-2-GP

12

Optimus

82.30034.641

2nd = 82.30034.651

3rd = 82.30034.681

C8353 SC15P 50V2JN-2-GP

12

Optimus

VGA2M

J26

NC#J26

J25

NC#J25

AB5

CEC

N9

MULTI_STRAP_REF0_GND

M9

MULTI_STRAP_REF1_GND

N12P-GE-A1-GP

150mA

12

C8343

SCD1U10V2KX-4GP

XTALSSIN

12

41

MUXLESS

MISC2

MULTI_STRAP_REF1_GND MULTI_STRAP_REF0_GND

Notebook configure.

N12P-GE N12P-GV1 N12M-GE N11P-GE N11P-GS [0] 1 1 TBD 1 0 [1] 0 1 0 0 [2] 1 1 0 0 [3] 0 0 0 0

STRAP1 STRAP2

R8309

3D3V_VGA_S0

1 2

DY

1 2

DY

1 2

Optimus

10KR2F-2-GP

10KR2F-2-GP R8326

R8326 34K8R2F-1-GP

34K8R2F-1-GP R8307

R8307 45K3R2F-L-GP

45K3R2F-L-GP

2

2 3

OPTIMUS

VGA2N

AE9

PLLVDD

AD9

VID_PLLVDD

AF9

SP_PLLVDD

D2

XTAL_SSIN

B1

XTAL_IN

N12P-GE-A1-GP

OPTIMUS

XTALIN

X8301

X8301 XTAL-27MHZ-85-GP

XTAL-27MHZ-85-GP

ROM_SCLK

13 OF 16

ROM_CS#

ROM_SI

ROM_SO

STRAP0 STRAP1 STRAP2

I2CH_SCL I2CH_SDA

NC#A5

BUFRST#

NC#C5

GND GND

12

1MR2F-GP

1MR2F-GP R8320

R8320

XTALOUT_R

C3 D3

C4 D4

W5 W7 V7

F6 G6

A5 A4

C5

AK14 K9

XTAL_PLL

1 2

GPU_ROM_CS# GPU_ROM_SI

GPU_ROM_SO GPU_ROM_SCLK

STRAP0 STRAP1 STRAP2

HDCP_CLK HDCP_SDA

14 OF 16

D1

B2

XTAL_OUT

XTALOUT

Stuff PD on XTAL_SSIN and XTAL_OUTBUFF when EXT_SS is not used.

10KR2J-3-GP

Optimus

RN8301

SRN4K7J-8-GP

HDCP_CLK HDCP_SDA

R8321

R8321 0R2J-2-GP

0R2J-2-GP

Optimus

12

XTAL_OUTBUFF

R8324

XTALOUTBUFF

3D3V_VGA_S0

4

Optimus

1

2 3

1

12

R8319

R8319 10KR2J-3-GP

10KR2J-3-GP

Optimus

STRAPPING MODE TABLE

PIN NAME MULTI-LEVEL BINARY PRODUCTION BINARY BRINGUP

1 2

DIS_DID_L

1 2

Optimus

1 2

DY

GPU_ROM_SI Hynix 64x16 = PL 15K Samsung 64x16 = PL 20K

2

40.2K TO GND

GPU_ROM_SI

for Hynix VRAM (64Mx16) (0x2) RAM_CFG[0]=0 RAM_CFG[1]=1 RAM_CFG[2]=0 RAM_CFG[3]=0

GPU_ROM_SO

GPU_ROM_SCLK

PEX_PLL_EN_TERM =0 SLOT_CLK_CFG =1 SUB_VENDOR =0 PCI_DEVID[4] =1

0901

R8305

R8305 30KR2F-GP

30KR2F-GP R8308

R8308 34K8R2F-1-GP

34K8R2F-1-GP R8325

R8325

2KR2J-1-GP

40.2K TO GND NC

for Samsung VRAM (64Mx16) (0x3) RAM_CFG[0]=1 RAM_CFG[1]=1 RAM_CFG[2]=0 RAM_CFG[3]=0

VGA_DEVICE =1 SMB_ALT_ADDR =0 FB_0_BAR_SIZE =0 XCLK_417 =0

N12P-GE N12P-GV1 N12M-GE N11P-GE N11P-GS [4] 1 1 TBD 1 1

3D3V_VGA_S0

for Hynix VRAM (128Mx16) (0x6) RAM_CFG[0]=0 RAM_CFG[1]=1 RAM_CFG[2]=1 RAM_CFG[3]=0

GPU_ROM_SISTRAP0 GPU_ROM_SO GPU_ROM_SCLK

1 2

15KR2F-GP

DIS_DID_H

1 2

10KR2F-2-GP

DY

1 2

2KR2J-1-GP

DY

Title

Size Document Number Rev

Size Document Number Rev A2

A2

A2 Date: Sheet

Date: Sheet

R8310

R8317

R8327

N12P(1/6)_PEG

NC NC

for Samsung VRAM (128Mx16) (0x7) RAM_CFG[0]=1 RAM_CFG[1]=1 RAM_CFG[2]=1 RAM_CFG[3]=0

R8311

1 2

15KR2F-GP

DY

Optimus

DIS_SAM_HYX

QUEEN 15

R8316

1 2

10KR2F-2-GP

R8312

1 2

15KR2F-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

1

A00

83 108Tuesday, January 04, 2011

A00

of

5

VGA2B

FBAD[0..31]88

D D

FBAD[32..63]89

C C

FBADQM088 FBADQM188 FBADQM288 FBADQM388 FBADQM489 FBADQM589 FBADQM689 FBADQM789

FBADQSP088 FBADQSP188 FBADQSP288 FBADQSP388 FBADQSP489

B B

FBADQSP589 FBADQSP689 FBADQSP789

FBADQSN088 FBADQSN188 FBADQSN288 FBADQSN388 FBADQSN489 FBADQSN589 FBADQSN689 FBADQSN789

Differential write clocks for GDDR5 for Frame Buffers. Reference for read and write data.

TP8415

TPAD14-GP

A A

TPAD14-GP

1

FB_VREF

5

FBAD0 FBAD1 FBAD2 FBAD3 FBAD4 FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17 FBAD18 FBAD19 FBAD20 FBAD21 FBAD22 FBAD23 FBAD24 FBAD25 FBAD26 FBAD27 FBAD28 FBAD29 FBAD30 FBAD31 FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63

AG30 AG32 AH31 AF31 AF30 AE30 AC32 AD30 AN33

AL31

AM33

AL33 AK30 AK32

AJ30 AH30 AH33 AH35 AH34 AH32

AJ33

AL35 AM34 AM35 AF33 AE32 AF34 AE35 AE34 AE33 AB32 AC35

AF32

AL32

AL34 AF35

AE31

AJ32

AJ34 AC33

AD32

AJ31

AJ35 AC34

AG29 AH29 AD29 AE29

L32

N33

L33 N34 N35 P35 P33 P34 K35 K33 K34 H33 G34 G33 E34 E33 G31

F30 G30 G32 K30 K32 H30 K31

L31

L30 M32 N30 M30 P31 R32 R30

P32 H34

J30 P30

L34 H35

J32 N31

L35 G35 H31 N32

P29 R29

L29 M29

J27

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_WCK0 FBA_WCK0# FBA_WCK1 FBA_WCK1# FBA_WCK2 FBA_WCK2# FBA_WCK3 FBA_WCK3#

NC#J27

N12P-GE-A1-GP

OPTIMUS

FBA

FBA_DEBUG0 FBA_DEBUG1

4

2 OF 16

AA27

FBVDDQ

AA29

FBVDDQ

AA31

FBVDDQ

AB27

FBVDDQ

AB29

FBVDDQ

AC27

FBVDDQ

AD27

FBVDDQ

AE27

FBVDDQ

AJ28

FBVDDQ

B18

FBVDDQ

E21

FBVDDQ

G17

FBVDDQ

G18

FBVDDQ

G22

FBVDDQ

G8

FBVDDQ

G9

FBVDDQ

H29

FBVDDQ

J14

FBVDDQ

J15

FBVDDQ

J16

FBVDDQ

J17

FBVDDQ

J20

FBVDDQ

J21

FBVDDQ

J22

FBVDDQ

J23

FBVDDQ

J24

FBVDDQ

J29

FBVDDQ

Mode E is necessary for DDR3 that require compatibility with previous generation GPUs (GB1-128) and only applies to GB2-128 package.

U30

FBA_CMD0

V30

FBA_CMD1

U31

FBA_CMD2

V32

FBA_CMD3

T35

FBA_CMD4

U33

FBA_CMD5

W32

FBA_CMD6

W33

FBA_CMD7

W31

FBA_CMD8

W34

FBA_CMD9

U34

FBA_CMD10

U35

FBA_CMD11

U32

FBA_CMD12

T34

FBA_CMD13

T33

FBA_CMD14

W30

FBA_CMD15

AB30

FBA_CMD16

AA30

FBA_CMD17

AB31

FBA_CMD18

AA32

FBA_CMD19

AB33

FBA_CMD20

Y32

FBA_CMD21

Y33

FBA_CMD22

AB34

FBA_CMD23

AB35

FBA_CMD24

Y35

FBA_CMD25

W35

FBA_CMD26

Y34

FBA_CMD27

Y31

FBA_CMD28

Y30

FBA_CMD29

W29

FBA_CMD30

Y29

FBA_CMD31

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

FB_DLLAVDD FB_PLLAVDD

FBA_CLK0

T32

FBA_CLK0#

T31

FBA_CLK1

AC31

FBA_CLK1#

AC30

FBA_DEBUG0

T30

FBA_DEBUG1 FBC_DEBUG1

T29

AG27 AF27

J19 J18

4

Optimus

12

C8425

Optimus

FB_PLLAVDD0

FB_PLLAVDD1

3

VGA2C

FBBD0 FBBD1 FBBD2 FBBD3 FBBD4 FBBD5 FBBD6 FBBD7 FBBD8 FBBD9 FBBD10 FBBD11 FBBD12 FBBD13 FBBD14 FBBD15 FBBD16 FBBD17 FBBD18 FBBD19 FBBD20 FBBD21 FBBD22 FBBD23 FBBD24 FBBD25 FBBD26 FBBD27 FBBD28 FBBD29 FBBD30 FBBD31 FBBD32 FBBD33 FBBD34 FBBD35 FBBD36 FBBD37 FBBD38 FBBD39 FBBD40 FBBD41 FBBD42 FBBD43 FBBD44 FBBD45 FBBD46 FBBD47 FBBD48 FBBD49 FBBD50 FBBD51 FBBD52 FBBD53 FBBD54 FBBD55 FBBD56 FBBD57 FBBD58 FBBD59 FBBD60 FBBD61 FBBD62 FBBD63

B13

D13

A13 A14

C16

B16

A17 D16 C13

B11 C11

A11 C10

C8

B8 A8 E8 F8

F10

F9

F12

D8

D11

E11 D12

E13

F13

F14

F15

E16

F16

F17 D29

F27

F28

E28 D26

F25 D24

E25

E32

F32 D33

E31 C33

F29 D30

E29

B29 C31 C29

B31 C32

B32

B35

B34

A29

B28

A28 C28 C26 D25

B25

A25

A16 D10

F11 D15 D27 D34

A34 D28

C14

A10

E10 D14

E26 D32

A32

B26

B14

B10

D9 E14 F26

D31

A31 A26

G14 G15 G11 G12 G27 G28 G24 G25

VGA2C

FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7

FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7

FBB_WCK0 FBB_WCK0# FBB_WCK1 FBB_WCK1# FBB_WCK2 FBB_WCK2# FBB_WCK3 FBB_WCK3#

0818 De-cap

Optimus

12

SC1U6D3V2KX-GP

12

C8419

12

C8424

C8422

C8423

SCD01U50V2KX-1GP

SCD1U10V2KX-5GP

1 1

SCD01U50V2KX-1GP

SCD1U10V2KX-4GP

DY

Optimus

12

C8409

SCD01U50V2KX-1GP

0818

0723

De-cap

0818 De-cap

FBA_CMD_0 88 FBA_CMD_2 88

FBA_CMD_3 88 FBA_CMD_4 88,89 FBA_CMD_5 88,89 FBA_CMD_6 88,89 FBA_CMD_7 88,89 FBB_CMD_7 90,91 FBA_CMD_8 88,89 FBA_CMD_9 88,89 FBA_CMD_10 88,89 FBA_CMD_11 88,89 FBA_CMD_12 88 FBA_CMD_13 88,89 FBA_CMD_14 89 FBA_CMD_15 88,89 FBA_CMD_16 89

FBA_CMD_18 89 FBA_CMD_19 89 FBA_CMD_20 88,89 FBA_CMD_21 88,89 FBA_CMD_22 88,89 FBA_CMD_23 88,89 FBA_CMD_24 88,89 FBA_CMD_25 88,89 FBA_CMD_26 88,89 FBA_CMD_27 88 FBA_CMD_28 88,89 FBA_CMD_29 88,89 FBA_CMD_30 89

FBA_CLK0 88 FBA_CLK0# 88 FBA_CLK1 89 FBA_CLK1# 89

TP8411 TPAD14-GPTP8411 TPAD14-GP TP8412 TPAD14-GPTP8412 TPAD14-GP

Optimus

C8417

SCD1U10V2KX-5GP

12

1D5V_VGA_S0

Optimus

12

C8420

0818 De-cap

Optimus

12

C8411

C8414

SCD1U10V2KX-5GP

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

Near BALLS

Near BGA

Optimus

12

C8421

SCD1U10V2KX-5GP

C8426

SC1U6D3V2KX-GP

12

C8410

SC4D7U6D3V3KX-GP

DY

ODTx & CKEx & RST termination.

FBA_CMD_16

4 5

FBA_CMD_19

3

FBA_CMD_3

2

FBA_CMD_0

FBA_CMD_20

1 2

1

1 2

L8401

0R0603-PAD-2-GP

C8412

SC1U6D3V2KX-GP

0802 swap

Optimus

C8413

12

SC4D7U6D3V3KX-GP

RN8401

SRN10KJ-6-GP

SRN10KJ-6-GP R8401

R8401

10KR2J-3-GP

Optimus

FBBDQM090 FBBDQM190 FBBDQM290 FBBDQM390 FBBDQM491 FBBDQM591 FBBDQM691 FBBDQM791

FBBDQSP090 FBBDQSP190 FBBDQSP290 FBBDQSP390 FBBDQSP491 FBBDQSP591 FBBDQSP691 FBBDQSP791

FBBDQSN090 FBBDQSN190 FBBDQSN290 FBBDQSN390 FBBDQSN491 FBBDQSN591 FBBDQSN691 FBBDQSN791

Optimus

A00

FBBD[0..31]90

FBBD[32..63]91

Optimus

6 7 8

1V_VGA_S0

1009

Optimus

12

C8418

Optimus

SCD1U10V2KX-5GP

12

C8415

SC1U6D3V2KX-GP

Optimus

C8416

12

L8402

1 2

SC4D7U6D3V3KX-GP

0R0603-PAD-2-GP

Optimus

1V_VGA_S0

A00

N12P-GE-A1-GP

OPTIMUS

2

3 OF 16

FBB

3 OF 16

FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ

N27 P27 R27 T27 U27 U29 V27 V29 V34 W27 Y27

1D5V_VGA_S0

0810

ODTx & CKEx & RST termination.

FBB_CMD_16 FBB_CMD_19 FBB_CMD_20 FBB_CMD_0

FBB_CMD_3

F18

FBB_CMD0

E19

FBB_CMD1

D18

FBB_CMD2

C17

FBB_CMD3

F19

FBB_CMD4

C19

FBB_CMD5

B17

FBB_CMD6

E20

FBB_CMD7

B19

FBB_CMD8

D20

FBB_CMD9

A19

FBB_CMD10

D19

FBB_CMD11

C20

FBB_CMD12

F20

FBB_CMD13

B20

FBB_CMD14

G21

FBB_CMD15

F22

FBB_CMD16

F24

FBB_CMD17

F23

FBB_CMD18

C25

FBB_CMD19

C23

FBB_CMD20

F21

FBB_CMD21

E22

FBB_CMD22

D21

FBB_CMD23

A23

FBB_CMD24

D22

FBB_CMD25

B23

FBB_CMD26

C22

FBB_CMD27

B22

FBB_CMD28

A22

FBB_CMD29

A20

FBB_CMD30

G20

FBB_CMD31

FBB_CLK0

E17

FBB_CLK0

FBB_CLK0#

FBB_CLK1

FBB_CLK1#

FBB_DEBUG0 FBB_DEBUG1

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

D17 D23 E23

G19 G16

K27 L27 M27

FBB_CLK0# FBB_CLK1 FBB_CLK1#

FBC_DEBUG0

FBCAL_PD_VDDQ FBCAL_PU_GND FB_CAL_TERM_GND

GB1-128 do not need.

3

2

1

RN8402

Optimus

4 5 3 2 1

1 2

FBB_CMD_0 90 FBB_CMD_2 90

FBB_CMD_3 90 FBB_CMD_4 90,91 FBB_CMD_5 90,91 FBB_CMD_6 90,91

FBB_CMD_8 90,91 FBB_CMD_9 90,91 FBB_CMD_10 90,91 FBB_CMD_11 90,91 FBB_CMD_12 90 FBB_CMD_13 90,91 FBB_CMD_14 91 FBB_CMD_15 90,91 FBB_CMD_16 91

FBB_CMD_18 91 FBB_CMD_19 91 FBB_CMD_20 90,91 FBB_CMD_21 90,91 FBB_CMD_22 90,91 FBB_CMD_23 90,91 FBB_CMD_24 90,91 FBB_CMD_25 90,91 FBB_CMD_26 90,91 FBB_CMD_27 90 FBB_CMD_28 90,91 FBB_CMD_29 90,91 FBB_CMD_30 91

FBB_CLK0 90 FBB_CLK0# 90 FBB_CLK1 91 FBB_CLK1# 91

TP8413 TPAD14-GPTP8413 TPAD14-GP

1

TP8414 TPAD14-GPTP8414 TPAD14-GP

1

1 2

R8404 40D2R2F-GP

1 2

R8405 40D2R2F-GP

1 2

R8402 60D4R2F-GP

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

Optimus

6 7 8

SRN10KJ-6-GP

SRN10KJ-6-GP R8403

R8403

10KR2J-3-GP

Optimus

1D5V_VGA_S0

Optimus

Optimus Optimus

Optimus

N12P(2/6)_MEMORY

QUEEN 15

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

84 108Tuesday, January 04, 2011

1

A00

5

If a DAC interface is not required, it should be disabled by:

1. Adding a pull-down to the DACx_VDD with a 10 kilohm resistor to GND.

2. All other DAC I/O pins can be left floating.

VGA2D

DACA

R8503

R8503 10KR2J-3-GP

10KR2J-3-GP

AJ12 AK12 AK13

12

Optimus

D D

In Optimus mode the GPU does not drive certain interfaces. These interfaces should be treated as unused and appropriate terminations per the GPU design guide should be applied th the signal or the power supply block.

The following guidelines only apply to a fully unused IFP macro:

1. Pull down IFPxy_IOVDD with 10 kilohm resistor.

2. Pull down IFPxy_PLLVDD with 10 kilohm resistor.

3. The other IO pins can be NC; this includes unused data lines.

DACA_VDD DACA_VREF DACA_RSET

N12P-GE-A1-GP

OPTIMUS

VGA2G

DACA

4

4 OF 16

I2CA_SCL

I2CA_SDA

DACA_HSYNC DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

IFPAB

G1 G4

AM13 AL13

AM15 AM14 AL14

NV_I2CA_SCL NV_I2CA_SDA

7 OF 16

RN8501

NV_I2CA_SDA NV_I2CA_SCL

RN8501

1 2 3

SRN2K2J-1-GP

Optimus

0723 NV suggest un-used I2C pull-up.

0804 swap

4

3D3V_VGA_S0

3

VGA2F

DACB

DACB_VDD DACB_VREF DACB_RSET

N12P-GE-A1-GP

OPTIMUS

DACB

Optimus

DACB_VDDDACA_VDD

12

R8507

R8507 10KR2J-3-GP

10KR2J-3-GP

AG7 AK6 AH7

VGA2I

DACB_GREEN

IFPEF

6 OF 16

I2CB_SCL

I2CB_SDA

DACB_HSYNC DACB_VSYNC

DACB_RED

DACB_BLUE

2

G3 G2

AM1 AM2

AK4 AL4 AJ4

R8514

2K2R2J-2-GP

VENTURA

SMBC_INA219_C SMBD_INA219_C

3D3V_VGA_S0

1 2

A00

VENTURA

10.28

R8515

R8515 2K2R2J-2-GP

2K2R2J-2-GP

VENTURA

R8511 0R0402-PAD- 2- GP

1 2

R8512 0R0402-PAD- 2- GP

1 2

VENTURA

SMBC_INA219 43,92 SMBD_INA219 43,92

Ventura I2C must connect to I2CB_SCL & I2CB_SDA.

9 OF 16

1

AL8

IFPA_TXD0#

AM8

IFPA_TXD0

AM9

IFPA_TXD1#

AM10

IFPC_AUX_I2CW_SDA#

IFPC_AUX_I2CW_SCL

U8501_2

IFPA_TXD1

AL10

IFPA_TXD2#

AK10

IFPA_TXD2

AL11

IFPA_TXD3#

AK11

IFPA_TXD3

AM12

IFPA_TXC#

AM11

IFPA_TXC

AP8

IFPB_TXD4#

AN8

IFPB_TXD4

AN10

IFPB_TXD5#

AP10

IFPB_TXD5

AR10

IFPB_TXD6#

AR11

IFPB_TXD6

AP11

IFPB_TXD7#

AN11

IFPB_TXD7

AN13

IFPB_TXC#

AP13

IFPB_TXC

K1

GPIO0

8 OF 16

AN3 AP2

AR2

IFPC_L3#

AP1

IFPC_L3

AM4

IFPC_L2#

AM3

IFPC_L2

AM5

IFPC_L1#

AL5

IFPC_L1

AM6

IFPC_L0#

AM7

IFPC_L0

K2

GPIO1

DY

U8501

1

B

VCC

2

A

Y

3

GND

74LVC1G08GW-1- GP

73.01G08.L04

2ND = 73.7SZ08.DAH

NEED CHECK PAGE 51.

0927

3D3V_S0

5

GPU_HDMI_HPD

4

DY

20101220 R8504 R8506 for change to parallel resistor

GPU_HDMI_DATA 51 GPU_HDMI_CLK 51

HDMI_CLK# 51 HDMI_CLK 51

HDMI_DATA0# 51 HDMI_DATA0 51

HDMI_DATA1# 51 HDMI_DATA1 51

HDMI_DATA2# 51 HDMI_DATA2 51

GPU_HDMI_HPD 51

R8505

R8505 100KR2J-1-GP

100KR2J-1-GP

1 2

IFPAB_PLLVDD

C C

Optimus

B B

3D3V_VGA_S0

A00

Optimus

220mA

L8503

1 2

IFPAB_IOVDD

4

RN8503

RN8503 SRN10KJ-5-GP

SRN10KJ-5-GP

A00

1

2 3

20101220 R8501 R8502 for change to parallel resistor

Optimus

12

0R0603-PAD-2-GP

C8508

12

C8507

C8506

SCD1U10V2KX-5GP

DY

300ohm@100MHz ESR=0.25

280mA

1V_VGA_S0

A00

Optimus

L8502

1 2

0R0603-PAD-2-GP

Optimus

12

C8512

Optimus

SCD1U10V2KX-5GP

12

C8505

220ohm@100MHz ESR=0.05

1009

A A

5

Optimus

12

C8516

SC1U6D3V2KX-GP

Optimus

12

C8511

SC1U6D3V2KX-GP

X02 1110

9025_PGOOD_1V93 PEX_RST#51,83,86

IFPAB_PLLVDD

IFPAB_IOVDD IFPAB_IOVDD

IFPCD_PLLVDD

IFPC_RSET

SC4D7U6D3V3KX-GP

12

IFPCD_IOVDD

SC4D7U6D3V3KX-GP

AK9

IFPAB_PLLVDD

AJ11

IFPAB_RSET

AG9

IFPA_IOVDD

AG10

IFPB_IOVDD

N12P-GE-A1-GP

OPTIMUS

VGA2H

AJ9

IFPC_PLLVDD

AK7

IFPC_RSET

R8509

R8509 1KR2F-3-GP

1KR2F-3-GP

Optimus

AJ8

IFPC_IOVDD

N12P-GE-A1-GP

OPTIMUS

If either IFPC or IFPD is used, then the whole IFPCD interface is considered as being used. This is because IFPC and IFPD share one macro design so one IO interface cannot be independently disabled.

HDMI_HPD_DET51

DY

DY DY

DY

Optimus systems with HDMI connected to GPU. (Option A).

R8510

12

0R2J-2-GP

0R2J-2-GP R8513

R8513

12

0R2J-2-GP

0927

IFPC

4

Optimus

IFPEF_PLLVDD

A00

IFPEF_IOVDD

4

RN8502

RN8502 SRN10KJ-5-GP

SRN10KJ-5-GP

1

2 3

3

Optimus

IFPEF_PLLVDD

IFPEF_IOVDD

IFPCD_PLLVDD IFPD_RSET

12

IFPCD _IOVD D

R8508

R8508 1KR2F-3-GP

1KR2F-3-GP

AJ6 AL1

AE7

AD7

AC6 AB6

AK8

IFPEF_PLLVDD IFPEF_RSET

IFPE_IOVDD

IFPF_IOVDD

N12P-GE-A1-GP

OPTIMUS

VGA2E

IFPD_PLLVDD IFPD_RSET

IFPD_IOVDD

N12P-GE-A1-GP

OPTIMUS

IFPD

IFPE_AUX_I2CY_SDA#

IFPE_AUX_I2CY_SCL

IFPF_AUX_I2CZ_SDA#

IFPF_AUX_I2CZ_SCL

IFPD_AUX_I2CX_SDA#

IFPD_AUX_I2CX_SCL

2

IFPE_L3#

IFPE_L3

IFPE_L2#

IFPE_L2

IFPE_L1#

IFPE_L1

IFPE_L0#

IFPE_L0

GPIO15

IFPF_L3#

IFPF_L3

IFPF_L2#

IFPF_L2

IFPF_L1#

IFPF_L1

IFPF_L0#

IFPF_L0

GPIO21

5 OF 16

IFPD_L3#

IFPD_L3

IFPD_L2#

IFPD_L2

IFPD_L1#

IFPD_L1

IFPD_L0#

IFPD_L0

GPIO19

AD4 AE4

AE5 AE6

AF5 AF4

AG4 AH4

AH5 AH6

L1

AF2 AF3

AH3 AH2

AH1 AJ1

AJ2 AJ3

AL3 AL2

K6

AN4 AP4

AR4 AR5

AP5 AN5

AN7 AP7

AR7 AR8

L7

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

A2 Date: Sheet

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

N12P(3/6)_DAC

QUEEN 15

1

A00

85 108Tuesday, January 04, 2011

A00

of

5

3D3V_VGA_S0

R8601 0R2J-2-GP

D D

DY

1 2

12

R8603

R8603 10KR2J-3-GP

10KR2J-3-GP

MIOA_VDDQ

Optimus

12

C8602

SCD1U10V2KX-4GP

DY

0728 Reserve for N12M.

C C

3D3V_VGA_S0

R8602 0R2J-2-GP

DY

1 2

R8605

10KR2J-3-GP

Optimus

MIOB_VDDQ

12

C8601

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

DY

0728 Reserve for N12M.

B B

P9 R9 T9 U9

U5 T5

N5

VGA2K

AA9 AB9

W9

Y9

AA7 AA6

AF1

N12P-GE-A1-GP

VGA2J

NC#P9 NC#R9 NC#T9 NC#U9

NC#U5 NC#T5

NC#N5

N12P-GE-A1-GP

NC#AA9 NC#AB9 NC#W9 NC#Y9

NC#AA7 NC#AA6

NC#AF1

OPTIMUS

MIOA/B Support

A A

Package

GB1-192

GB2-128

MIOA MIOB

15-bit, available TBD

Not available Not available

5

4

10 OF 16

N1

NC#N1

P4

NC#P4

P1

NC#P1

P2

NC#P2

P3

NC#P3

T3

NC#T3

T2

NC#T2

T1

NC#T1

U4

NC#U4

U1

NC#U1

U2

NC#U2

U3

NC#U3

R6

NC#R6

T6

NC#T6

N6

NC#N6

P5

NC#P5

N3

NC#N3

L3

NC#L3

N2

NC#N2

R4

NC#R4

T4

NC#T4 NC#N4

11 OF 16

NC#Y1 NC#Y2

NC#Y3 NC#AB3 NC#AB2 NC#AB1 NC#AC4 NC#AC1 NC#AC2 NC#AC3 NC#AE3 NC#AE2

NC#U6

NC#W6

NC#Y6

NC#W3 NC#W1 NC#W2

NC#Y5

NC#V4

NC#W4

NC#AE1

PURE_HW_SHUTDOW N#27,28,36

4

N4

Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6

W3 W1 W2 Y5

V4 W4

MIOB_CLKIN_NC

AE1

MIOA_CLKIN_NC

D

JTAG_TCK_VGA20

MIOA_CLKIN_NC MIOB_CLKIN_NC

1

23

RN8606

RN8606 SRN10KJ-5-GP

SRN10KJ-5-GP

Optimus

4

MIOx_CLKIN signals should have 10K pull-down resistors.

2ND = 84.2N702.031

84.2N702.J31

2N7002K-2-GP

DY

Q8602

G

S

3

Q8602_G

NV_OVERTEMP#

3

RN8603

RN8603 SRN2K2J-1-GP

SRN2K2J-1-GP

Optimus

R8606

12

C8603

DY

SCD1U10V2KX-4GP

JTAG_TCK_VGA

23

4

1

2 3

12

P2800_VGA_DXN

1

TP8611

P2800_VGA_DXP

1

TP8612

JTAG_TRST#

1

4

TPAD14-GP

A00 1231 add probe point

TPAD14-GP

TP8608TPAD14-GP TP8608TPAD14-GP

1

TP8609TPAD14-GP TP8609TPAD14-GP

1

TP8610TPAD14-GP TP8610TPAD14-GP

1

Optimus

DY

0R2J-2-GP

0915

B4

B5

AP14

NV_TMS

AR14

NV_TDI

AN14

NV_TDO

AN16 AP16

RN8602

RN8602 SRN10KJ-5-GP

SRN10KJ-5-GP

3D3V_VGA_S0

SMBC_THERM_NV

SMBD_THERM_NV

PEX_RST# 51,83,85

VGA2L

THERMDN

THERMDP

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST#

N12P-GE-A1-GP

2

NV_OVERTEMP# NV_GPIO9

0915

MISC1

OPTIMUS

PWR_LEVEL

0723

Q8601

Optimus

1

6

2

5

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

2

1

RN8601

1

4

2 3

SRN10KJ-5-GP

Optimus

12 OF 16

SMBC_THERM_NV

E2

I2CS_SCL I2CS_SDA

I2CC_SCL I2CC_SDA

GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14

GPIO16 GPIO17 GPIO18

GPIO20 GPIO22

GPIO23 GPIO24

3D3V_VGA_S0

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

12

R8604

R8604 10KR2J-3-GP

10KR2J-3-GP

SMBD_THERM_NV

E1

NV_LCD_EDID_CLK

E3

NV_LCD_EDID_DAT

E4

K3 H3 H2

PWRCNTL_0

H1

PWRCNTL_1

H4 H5 H6 J7 K4 K5 H7 J4 J6

L2 L4 M4

L5 L6

M6 M7

Optimus

3D3V_VGA_S0

RN8605

4

SRN2K2J-1-GP

Optimus

NV_GPIO7 NV_OVERTEMP# NV_GPIO9

PWR_LEVEL

TP8601 TPAD14-GPTP8601 TPAD14-GP

1

0728

GPU_GPIO23

TP8606 TPAD14-GPTP8606 TPAD14-GP

1

GPIO12 1 - > AC mode. 0 -> Battery mode.

D8601

1

3

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

SML1_CLK 20,27

SML1_DATA 20,27

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

N12P(5/6)_MIO/ GPIO

QUEEN 15

1

3D3V_VGA_S0

1 23

PWRCNTL_0 92 PWRCNTL_1 92

0915

AC_PRESENT 19,27

86 108Tuesday, January 04, 2011

A00

of

A00

5

15 OF 16

VGA2O

AA11

GND

AA12

GND

AA13

GND

AA14

GND

AA15

GND

AA16

GND

AA17

GND

AA18

GND

AA19

GND

D D

C C

B B

A A

AA2 AA20 AA21 AA22 AA23 AA24 AA25 AA34

AA5 AB12 AB14 AB16 AB18 AB20 AB22 AB24

AC9 AD11 AD13 AD15 AD17

AD2 AD21 AD23 AD25 AD31 AD34

AD5 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25

AG2 AG31 AG34

AG5

AK2 AK31 AK34

AK5

AL12 AL15 AL18 AL21 AL24 AL27 AL30

AL6

AL9

AN2 AN34 AP12 AP15 AP18 AP21 AP24 AP27

AP3 AP30 AP33

AP6

AP9

B12

B15

B21

B24

B27

B30

B33

C34

E12

B3

B6 B9 C2

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

N12P-GE-A1-GP

OPTIMUS

5

GND

15 OF 16

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

E15 E18 E24 E27 E30 E6 E9 F2 F31 F34 F5 J2 J31 J34 J5 L9 M11 M13 M15 M17 M19 M2 M21 M23 M25 M31 M34 M5 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R31 R34 R5 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V12 V14 V16 V18 V2 V20 V22 V24 V31 V5 V9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25

4

VGA_CORE VGA_CORE

4

AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24

M12 M14 M16 M18 M20 M22 M24

L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25

P11 P13 P15 P17 P19

VGA2P

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

N12P-GE-A1-GP

OPTIMUS

NVVDD

16 OF 16

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24

3

VGA_CORE

3

Optimus

12

C8704

Optimus

12

Optimus

12

DY

12

DY

Optimus

12

C8713

SCD1U10V2KX-5GP

Optimus

12

C8716

SCD1U10V2KX-5GP

Optimus

12

C8708

C8705

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

Optimus

12

C8711

C8717

SCD1U10V2KX-5GP

Optimus

12

C8703

SCD1U10V2KX-5GP

C8707

SCD047U25V2KX-GP

Optimus

12

C8701

C8718

SCD1U10V2KX-5GP

12

C8709

SCD1U10V2KX-5GP

DY

Optimus

12

C8712

SCD1U10V2KX-5GP

Optimus

12

C8706

SC1U6D3V2KX-GP

Optimus

12

C8702

SCD1U10V2KX-4GP

Under GPU

Optimus

12

C8715

C8719

SCD1U10V2KX-5GP

DY

0818 De-cap

Optimus

12

C8714

SCD1U10V2KX-5GP

2

Optimus

12

C8721

C8720

SCD1U10V2KX-5GP

0728

2

1

VGA_CORE

Near GPU

C8722

12

DY

C8724

12

Optimus

12

C8710

SC4D7U10V3KX-GP

Optimus

0818 De-cap

12

SC10U6D3V3MX-GP

C8723

SC4D7U6D3V3KX-GP

Optimus

C8725

SC22U6D3V5MX-2GP

12

Optimus

0728

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

N12P(6/6)_POWER

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

87 108Tuesday, January 04, 2011

1

A00

of

A00

5

4

Frame Buffer Patition A Lower 32 bits.

3

2

1

1D5V_VGA_S0

D D

1D5V_VGA_S0

C8801

Optimus

SCD01U50V2KX-1GP

FBA_VREF12

12

Optimus

CMD25 CMD23 CMD2 CMD0 CMD10 CMD26 CMD14 CMD7 CMD1 CMD22 CMD20 CMD24 CMD18 CMD9 CMD29 CMD8 CMD27 CMD15 CMD11 CMD16 CMD28

CMD17 CMD5 CMD4 CMD21 CMD6 CMD13 CMD19 CMD12 CMD30

12

FBA_ZQ0 FBA_ZQ1

FBA_CMD_7 FBA_CMD_10 FBA_CMD_24 FBA_CMD_6 FBA_CMD_22 FBA_CMD_26 FBA_CMD_5 FBA_CMD_21 FBA_CMD_8 FBA_CMD_4 FBA_CMD_25 FBA_CMD_23 FBA_CMD_9 FBA_CMD_12

0729

FBA_CMD_29 FBA_CMD_13 FBA_CMD_27

160R3F-1-GP

R8807

1 2

FBA_CMD_3

FBA_CMD_28 FBA_CMD_15 FBA_CMD_11

GB2-128

Mode E CMD0

CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD21CMD3 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30

5

Optimus

R8804

243R2F-2-GP

FBA_CMD_784,89 FBA_CMD_1084,89 FBA_CMD_2484,89 FBA_CMD_684,89 FBA_CMD_2284,89 FBA_CMD_2684,89 FBA_CMD_584,89

C C

B B

A A

FBA_CMD_2184,89 FBA_CMD_884,89 FBA_CMD_484,89 FBA_CMD_2584,89 FBA_CMD_2384,89 FBA_CMD_984,89 FBA_CMD_1284

FBA_CMD_2984,89

FBA_CMD_1384,89 FBA_CMD_2784

FBA_CLK0#84

FBA_CMD_384

FBA_CMD_1184,89

FBA_CLK084

FBADQM184 FBADQM284

FBA_CMD_2884,89 FBA_CMD_1584,89

GB1-128 Mode C

Single Rank

FBRAM1

ODT

CS#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

FBAD22 FBAD18 FBAD23 FBAD17 FBAD21 FBAD19 FBAD20 FBAD16

FBAD13 FBAD11 FBAD14 FBAD8 FBAD12 FBAD10 FBAD15 FBAD9

FBA_CMD_0

FBA_CMD_2

FBA_CMD_20

0729

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

Optimus

H5TQ2G63BFR-11C-GP

72.52G63.A0U

2nd = 72.41164.I0U

PCB Footprint = BGA96D0913H48

1112 X02 Modify: All of VRAM PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from BGA96D0913H48

DRAM Function

32..63

0..31 ODT CS1* CS0*

CKE

A11

A9

A7

A6

BA1

A3 A0 A12 A8

A8

A12

A0

A1

A2

RAS*

A13

A14 A3

BA1

A13

A14

CAS*

CKE CS1* CS0* ODT RST

RST

A6

A7

A5

A4

A9

A11

A1

A2

WE*

A10 A5

A4 A15

BA2

A10

WE*

BA0

BA2

A15

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

RESET#

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBAD[0..31] 84

0730 swap pin

FBADQSP1 84 FBADQSN1 84

FBADQSP2 84 FBADQSN2 84

FBA_CMD_0 84

FBA_CMD_2 84

FBA_CMD_20 84,89

4

Optimus

R8803

FBA_CMD_784,89 FBA_CMD_1084,89 FBA_CMD_2484,89 FBA_CMD_684,89 FBA_CMD_2284,89 FBA_CMD_2684,89 FBA_CMD_584,89 FBA_CMD_2184,89 FBA_CMD_884,89 FBA_CMD_484,89 FBA_CMD_2584,89 FBA_CMD_2384,89 FBA_CMD_984,89 FBA_CMD_1284

FBA_CMD_2984,89

FBA_CMD_1384,89 FBA_CMD_2784

FBA_CLK084

FBA_CLK0#84

FBA_CMD_384

FBADQM084 FBADQM384

FBA_CMD_2884,89 FBA_CMD_1584,89

FBA_CMD_1184,89

1D5V_VGA_S0

12

R8801

R8801 1K05R2F-GP

1K05R2F-GP

12

R8802

R8802 1K05R2F-GP

1K05R2F-GP

FBA_VREF12

1D5V_VGA_S0

FBA_VREF12

12

243R2F-2-GP

FBA_CMD_7 FBA_CMD_10 FBA_CMD_24 FBA_CMD_6 FBA_CMD_22 FBA_CMD_26 FBA_CMD_5 FBA_CMD_21 FBA_CMD_8 FBA_CMD_4 FBA_CMD_25 FBA_CMD_23 FBA_CMD_9 FBA_CMD_12

FBA_CMD_29 FBA_CMD_13 FBA_CMD_27

FBA_CMD_3

FBA_CMD_28 FBA_CMD_15 FBA_CMD_11

12

Optimus

C8839

C8839 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

0729

FBRAM2

ODT

CS#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

FBAD26 FBAD29 FBAD24 FBAD30 FBAD25 FBAD31 FBAD28 FBAD27

FBAD4 FBAD3 FBAD7 FBAD0 FBAD5 FBAD2 FBAD6 FBAD1

FBA_CMD_0

FBA_CMD_2

FBA_CMD_20

0729

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

Optimus

H5TQ2G63BFR-11C-GP

72.52G63.A0U

2nd = 72.41164.I0U

PCB Footprint = BGA96D0913H48

1112 X02 Modify: All of VRAM PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from BGA96D0913H48

3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

RESET#

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

Modified in SB

12

TC8802

TC8802 ST100U6D3VBM-16GP

ST100U6D3VBM-16GP

DY

FBAD[0..31] 84

1D5V_VGA_S0

FBADQSP0 84 FBADQSN0 84

FBADQSP3 84 FBADQSN3 84

FBA_CMD_0 84

FBA_CMD_2 84

FBA_CMD_20 84,89

1D5V_VGA_S01D5V_VGA_S0

2

Optimus

12

C8803

C8802

SC1U6D3V2KX-GP

Optimus

12

C8813

C8812

SCD1U10V2KX-5GP

0818 De-cap

Optimus

12

C8821

C8829

SC4D7U6D3V3KX-GP

DY

0818 De-cap

Optimus

12

C8831

SC10U6D3V3MX-GP

0818 De-cap

12

TC8801

TC8801 ST100U6D3VBM-16GP

ST100U6D3VBM-16GP

DY

Optimus

12

C8804

C8805

SC1U6D3V2KX-GP

DY

Optimus

12

C8814

C8815

SC1U6D3V2KX-GP

Optimus

12

C8823

C8824

SC1U6D3V2KX-GP

DY

Optimus

12

C8834

C8833

C8832

SC4D7U6D3V3KX-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

Optimus

12

C8806

C8807

SC1U6D3V2KX-GP

Optimus

12

C8816

C8817

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

0818 De-cap

Optimus

12

C8826

C8825

SC1U6D3V2KX-GP

DY

Optimus

12

C8835

SC10U6D3V3MX-GP

0818 De-cap

VRAM(1/4)

QUEEN 15

C8836

Optimus

12

C8809

C8808

SC1U6D3V2KX-GP

Optimus

12

C8818

C8819

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

Optimus

12

C8828

C8827

SC1U6D3V2KX-GP

DY

Optimus

12

C8837

C8838

SC4D7U6D3V3KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

Optimus

12

C8811

C8810

SC1U6D3V2KX-GP

Optimus

12

C8820

C8822

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

DY

0818 De-cap

Optimus

12

C8840

SCD1U10V2KX-4GP

SCD01U50V2KX-1GP

0818 De-cap

SC10U6D3V3MX-GP

of

88 108Tuesday, January 04, 2011

C8830

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD01U16V2KX-3GP

A00

5

4

3

2

1

Frame Buffer Patition A Upper 32 bits.

FBRAM4

FBRAM3

1D5V_VGA_S0

D D

1D5V_VGA_S0

Optimus

C8901

FBA_VREF34

12

SCD01U50V2KX-1GP

FBA_ZQ2

R8903

12

Optimus

243R2F-2-GP

FBA_CMD_984,88 FBA_CMD_2484,88 FBA_CMD_1084,88 FBA_CMD_1384,88 FBA_CMD_2684,88 FBA_CMD_2284,88

C C

0730 swap pin

B B

FBA_CMD_2184,88 FBA_CMD_584,88 FBA_CMD_884,88 FBA_CMD_2384,88 FBA_CMD_2884,88 FBA_CMD_484,88 FBA_CMD_784,88 FBA_CMD_1484

FBA_CMD_2984,88 FBA_CMD_684,88 FBA_CMD_3084

Optimus

FBA_CLK184 FBA_CLK1#84

FBA_CLK1#84

FBA_CMD_1684

FBADQM684 FBADQM484

FBA_CMD_2584,88 FBA_CMD_1584,88 FBA_CMD_1184,88

FBA_CMD_9 FBA_CMD_24 FBA_CMD_10 FBA_CMD_13 FBA_CMD_26 FBA_CMD_22 FBA_CMD_21 FBA_CMD_5 FBA_CMD_8 FBA_CMD_23 FBA_CMD_28 FBA_CMD_4 FBA_CMD_7 FBA_CMD_14

FBA_CMD_29 FBA_CMD_6 FBA_CMD_30

160R3F-1-GP

R8904

FBA_CMD_16

FBA_CMD_25 FBA_CMD_15 FBA_CMD_11

0729

1 2

FBRAM3

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

Optimus

RAS#

H5TQ2G63BFR-11C-GP

72.52G63.A0U

2nd = 72.41164.I0U

PCB Footprint = BGA96D0913H48

1112 X02 Modify: All of VRAM PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from BGA96D0913H48

Optimus

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

RESET#

NC#T7

NC#L9 NC#L1 NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1D5V_VGA_S0

12

R8901

R8901 1K05R2F-GP

1K05R2F-GP

12

R8902

R8902 1K05R2F-GP

1K05R2F-GP

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

ODT

CS#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

FBAD33

E3

FBAD35

F7

FBAD32

F2

FBAD39

F8

FBAD34

H3 H8

FBAD36

G2

FBAD38

H7

FBAD48

D7

FBAD52

C3

FBAD50

C8

FBAD55

C2

FBAD51

A7

FBAD54

A2

FBAD49

B8

FBAD53

A3 C7

B7 F3

G3

FBA_CMD_19

K1

FBA_CMD_18

L2

FBA_CMD_20

T2

T7

0729

L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

FBA_VREF34

Optimus

12

FBAD[32..63] 84

0730 swap pin 0802 swap pin

FBADQSP6 84 FBADQSN6 84

FBADQSP4 84 FBADQSN5 84 FBADQSN4 84

FBA_CMD_19 84

FBA_CMD_18 84 FBA_CMD_20 84,88

C8902

C8902 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

0730 swap pin

R8905

243R2F-2-GP

Optimus

FBA_CMD_984,88 FBA_CMD_2484,88 FBA_CMD_1084,88 FBA_CMD_1384,88 FBA_CMD_2684,88 FBA_CMD_2284,88 FBA_CMD_2184,88 FBA_CMD_584,88 FBA_CMD_884,88 FBA_CMD_2384,88 FBA_CMD_2884,88 FBA_CMD_484,88 FBA_CMD_784,88 FBA_CMD_1484

FBA_CMD_2984,88 FBA_CMD_684,88 FBA_CMD_3084

FBA_CMD_1684

FBA_CMD_2584,88 FBA_CMD_1584,88 FBA_CMD_1184,88

Optimus

FBA_CLK184

FBADQM784 FBADQM584

1D5V_VGA_S0

FBA_VREF34 FBA_ZQ3

12

FBA_CMD_9 FBA_CMD_24 FBA_CMD_10 FBA_CMD_13 FBA_CMD_26 FBA_CMD_22 FBA_CMD_21 FBA_CMD_5 FBA_CMD_8 FBA_CMD_23 FBA_CMD_28 FBA_CMD_4 FBA_CMD_7 FBA_CMD_14

FBA_CMD_29 FBA_CMD_6 FBA_CMD_30

FBA_CMD_16

FBA_CMD_25 FBA_CMD_15 FBA_CMD_11

0729

FBRAM4

ODT

CS#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

FBAD43 FBAD45 FBAD46 FBAD40 FBAD44 FBAD41 FBAD47FBAD37 FBAD42

FBAD56 FBAD63 FBAD57 FBAD62 FBAD58 FBAD59 FBAD61 FBAD60

FBA_CMD_19

FBA_CMD_18 FBA_CMD_20

0729

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

Optimus

RAS#

H5TQ2G63BFR-11C-GP

72.52G63.A0U

2nd = 72.41164.I0U

PCB Footprint = BGA96D0913H48

1112 X02 Modify: All of VRAM PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from BGA96D0913H48

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

RESET#

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBAD[32..63] 84

0730 swap pin

FBADQSP7 84 FBADQSN7 84

FBADQSP5 84

FBA_CMD_19 84

FBA_CMD_18 84 FBA_CMD_20 84,88

0730 swap pin

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

VRAM(2/4)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

89 108Tuesday, January 04, 2011

1

A00

5

4

3

2

1

Frame Buffer Patition B Lower 32 bits.

FBRAM6

FBRAM5

1D5V_VGA_S0

D D

1D5V_VGA_S0

Optimus

C9001

FBB_VREF12

12

SCD01U50V2KX-1GP

FBB_ZQ0

R9002

12

243R2F-2-GP

Optimus

FBB_CMD_784,91 FBB_CMD_1084,91 FBB_CMD_2484,91 FBB_CMD_684,91 FBB_CMD_2284,91

C C

B B

A A

FBB_CMD_2684,91 FBB_CMD_584,91 FBB_CMD_2184,91 FBB_CMD_884,91 FBB_CMD_484,91 FBB_CMD_2584,91 FBB_CMD_2384,91 FBB_CMD_984,91 FBB_CMD_1284

FBB_CMD_2984,91

FBB_CMD_1384,91 FBB_CMD_2784

Optimus

FBB_CLK084

FBB_CLK0#84

FBB_CMD_384

FBBDQM284

FBB_CMD_2884,91 FBB_CMD_1584,91

FBB_CMD_1184,91

FBB_CMD_7 FBB_CMD_10 FBB_CMD_24 FBB_CMD_6 FBB_CMD_22 FBB_CMD_26 FBB_CMD_5 FBB_CMD_21 FBB_CMD_8 FBB_CMD_4 FBB_CMD_25 FBB_CMD_23 FBB_CMD_9 FBB_CMD_12

0729 0729

FBB_CMD_29 FBB_CMD_13 FBB_CMD_27

160R3F-1-GP

R9005

1 2

FBB_CMD_3

FBB_CMD_28 FBB_CMD_15 FBB_CMD_11

FBRAM5

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

Optimus

H5TQ2G63BFR-11C-GP

72.52G63.A0U

2nd = 72.41164.I0U

PCB Footprint = BGA96D0913H48

1112 X02 Modify: All of VRAM PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from BGA96D0913H48

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

RESET#

NC#T7

NC#L9 NC#L1 NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

ODT

CS#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

FBBD21 FBBD18 FBBD17 FBBD20 FBBD16 FBBD23 FBBD19 FBBD22

FBBD6 FBBD1 FBBD5 FBBD7 FBBD3 FBBD2 FBBD4 FBBD0

FBB_CMD_0

FBB_CMD_2

FBB_CMD_20

0729

FBBD[0..31] 84

FBBDQSP0 84 FBBDQSP1 84

FBBDQSP2 84 FBBDQSN2 84

FBB_CMD_0 84

FBB_CMD_2 84

FBB_CMD_20 84,91

Optimus

0730 swap pin

0730 swap pin0730 swap pin

1D5V_VGA_S0

12

R9003

R9003 1K05R2F-GP

1K05R2F-GP

12

R9004

R9004 1K05R2F-GP

1K05R2F-GP

FBB_VREF12

FBB_CMD_784,91 FBB_CMD_1084,91 FBB_CMD_2484,91 FBB_CMD_684,91 FBB_CMD_2284,91 FBB_CMD_2684,91 FBB_CMD_584,91 FBB_CMD_2184,91 FBB_CMD_884,91 FBB_CMD_484,91 FBB_CMD_2584,91 FBB_CMD_2384,91 FBB_CMD_984,91 FBB_CMD_1284

FBB_CMD_2984,91

FBB_CMD_1384,91 FBB_CMD_2784

FBB_CLK084

FBB_CLK0#84

FBB_CMD_384

FBBDQM184FBBDQM084 FBBDQM384

FBB_CMD_2884,91 FBB_CMD_1584,91

FBB_CMD_1184,91

12

Optimus

C9002

C9002 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

R9001

Optimus

1D5V_VGA_S0

FBB_VREF12 FBB_ZQ1

12

243R2F-2-GP

FBB_CMD_7 FBB_CMD_10 FBB_CMD_24 FBB_CMD_6 FBB_CMD_22 FBB_CMD_26 FBB_CMD_5 FBB_CMD_21 FBB_CMD_8 FBB_CMD_4 FBB_CMD_25 FBB_CMD_23 FBB_CMD_9 FBB_CMD_12

FBB_CMD_29 FBB_CMD_13 FBB_CMD_27

FBB_CMD_3

FBB_CMD_28 FBB_CMD_15 FBB_CMD_11

1D5V_VGA_S0

FBRAM6

ODT

CS#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

FBBD26 FBBD25 FBBD30 FBBD28 FBBD29 FBBD27 FBBD31 FBBD24

FBBD14 FBBD11 FBBD15 FBBD8 FBBD13 FBBD10 FBBD12 FBBD9

FBB_CMD_0

FBB_CMD_2

FBB_CMD_20

0729

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

Optimus

RAS#

H5TQ2G63BFR-11C-GP

72.52G63.A0U

2nd = 72.41164.I0U

PCB Footprint = BGA96D0913H48

1112 X02 Modify: All of VRAM PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from BGA96D0913H48

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

RESET#

NC#T7 NC#L9 NC#L1

NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

0802 swap

FBBDQSN1 84FBBDQSN0 84 FBBDQSP3 84

FBBDQSN3 84

FBB_CMD_0 84

FBB_CMD_2 84

FBB_CMD_20 84,91

FBBD[0..31] 84

0730 swap pin

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

VRAM(3/4)

Taipei Hsien 221, Taiwan, R.O.C.

QUEEN 15

A00

of

90 108Tuesday, January 04, 2011

1

A00

5

4

3

2

1

Frame Buffer Patition B Upper 32 bits.

FBRAM8

FBRAM7

D D

Optimus

C9101

FBB_VREF34

12

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP R9105

R9105

243R2F-2-GP

Optimus

FBB_CLK1#84

FBB_CLK184

FBBDQM684 FBBDQM484

Optimus

R9103

FBB_CMD_984,90 FBB_CMD_2484,90 FBB_CMD_1084,90

C C

0730 swap pin

B B

FBB_CMD_1384,90 FBB_CMD_2684,90 FBB_CMD_2284,90 FBB_CMD_2184,90 FBB_CMD_584,90 FBB_CMD_884,90 FBB_CMD_2384,90 FBB_CMD_2884,90 FBB_CMD_484,90 FBB_CMD_784,90 FBB_CMD_1484

FBB_CMD_2984,90 FBB_CMD_684,90 FBB_CMD_3084

FBB_CMD_1684

FBB_CMD_2584,90 FBB_CMD_1584,90 FBB_CMD_1184,90

1D5V_VGA_S0

FBB_ZQ2

12

FBB_CMD_9 FBB_CMD_24 FBB_CMD_10 FBB_CMD_13 FBB_CMD_26 FBB_CMD_22 FBB_CMD_21 FBB_CMD_5 FBB_CMD_8 FBB_CMD_23 FBB_CMD_28 FBB_CMD_4 FBB_CMD_7 FBB_CMD_14

FBB_CMD_29 FBB_CMD_6 FBB_CMD_30

160R3F-1-GP

1 2

FBB_CMD_16

FBB_CMD_25 FBB_CMD_15 FBB_CMD_11

0729

FBRAM7

ODT

CS#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

FBBD35 FBBD37 FBBD34 FBBD36 FBBD33 FBBD38 FBBD32 FBBD39

FBBD48 FBBD53 FBBD50 FBBD54 FBBD51 FBBD52 FBBD49 FBBD55

FBB_CMD_19

FBB_CMD_18 FBB_CMD_20

0729

Optimus

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

Optimus

CAS#

J3

RAS#

H5TQ2G63BFR-11C-GP

72.52G63.A0U

2nd = 72.41164.I0U

PCB Footprint = BGA96D0913H48

1112 X02 Modify: All of VRAM PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from BGA96D0913H48

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

RESET#

NC#T7

NC#L9 NC#L1 NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1D5V_VGA_S0

FBBD[32..63] 84

0730 swap pin 0802 swap pin

FBBDQSP6 84 FBBDQSN7 84 FBBDQSN6 84

FBBDQSP4 84 FBBDQSN4 84

FBB_CMD_19 84

FBB_CMD_18 84 FBB_CMD_20 84,90

12

R9104

R9104 1K05R2F-GP

1K05R2F-GP

12

R9102

R9102 1K05R2F-GP

1K05R2F-GP

FBB_VREF34

0730 swap pin

12

Optimus

C9102

C9102 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

R9101

243R2F-2-GP

Optimus

FBB_CMD_984,90 FBB_CMD_2484,90 FBB_CMD_1084,90 FBB_CMD_1384,90 FBB_CMD_2684,90 FBB_CMD_2284,90 FBB_CMD_2184,90 FBB_CMD_584,90 FBB_CMD_884,90 FBB_CMD_2384,90 FBB_CMD_2884,90 FBB_CMD_484,90 FBB_CMD_784,90 FBB_CMD_1484

FBB_CMD_2984,90 FBB_CMD_684,90 FBB_CMD_3084

FBB_CMD_1684

FBB_CMD_2584,90 FBB_CMD_1584,90 FBB_CMD_1184,90

Optimus

FBB_CLK184

FBB_CLK1#84

FBBDQM784 FBBDQM584

1D5V_VGA_S0

FBB_VREF34 FBB_ZQ3

12

FBB_CMD_9 FBB_CMD_24 FBB_CMD_10 FBB_CMD_13 FBB_CMD_26 FBB_CMD_22 FBB_CMD_21 FBB_CMD_5 FBB_CMD_8 FBB_CMD_23 FBB_CMD_28 FBB_CMD_4 FBB_CMD_7 FBB_CMD_14

0729

FBB_CMD_29 FBB_CMD_6 FBB_CMD_30

FBB_CMD_16

FBB_CMD_25 FBB_CMD_15 FBB_CMD_11

FBRAM8

ODT

CS#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

FBBD44 FBBD40 FBBD43 FBBD42 FBBD45 FBBD41 FBBD46 FBBD47

FBBD59 FBBD58 FBBD61 FBBD62 FBBD57 FBBD63 FBBD56 FBBD60

FBB_CMD_19

FBB_CMD_18 FBB_CMD_20

0729

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

Optimus

RAS#

H5TQ2G63BFR-11C-GP

72.52G63.A0U

2nd = 72.41164.I0U

PCB Footprint = BGA96D0913H48

1112 X02 Modify: All of VRAM PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from BGA96D0913H48

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

RESET#

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBBD[32..63] 84

0730 swap pin

FBBDQSP7 84

FBBDQSP5 84 FBBDQSN5 84

FBB_CMD_19 84

FBB_CMD_18 84 FBB_CMD_20 84,90

0730 swap pin

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

VRAM(4/4)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

91 108Tuesday, January 04, 2011

1

A00

10

9

8

7

6

5

4

3

2

1

SSID = PWR.Plane.Regulator_GFX

J J

MUXLESS

12

PC9214

PC9213

SC4D7U25V5KX-GP

MUXLESS

1 2

L-D36UH-1-GP

68.R3610.20A

2nd = 68.R3610.20C

Modify to PCMC135T-R36MF

PWR_VGA_CORE_VOUT

VGA_SENSE83

PWR_VGA_CORE_FB

PR9228

PR9228 100KR2J-1-GP

100KR2J-1-GP

PWR_VGA_CORE_EN_R#

5

6

DY

123 4

DCBATOUT_GPU

12

PC9202

SC4D7U25V5KX-GP

MUXLESS

PL9201

PR9211

1 2

0R0402-PAD

10KR2F-2-GP

12

PR9209

PR9209 300KR2F-GP

300KR2F-GP

MUXLESS

PWR_VGA_CORE_D0

12

PC9203

PC9205

SC4D7U25V5KX-GP

MUXLESS

0927 PL9201 change like CPU core power choke.

PG9205

12

GAP-CLOSE-PWR-3-GP

PR9203

MUXLESS

10R2J-2-GP

VGA_SENSE_R

12

PR9208

MUXLESS

12

PR9210

PR9210 82KR2F-1-GP

82KR2F-1-GP

MUXLESS

PR9216

1 2

GND_SENSE_1

12

0R0402-PAD

PR9207

PR9207 10R2J-2-GP

10R2J-2-GP

MUXLESS

VGA_CORE

PR9229

PR9229 100R2J-2-GP

100R2J-2-GP

DY

1 2

Vout=0.75V*(R1+R2)/R2

Design Current = 32A 45<OCP<50A

VGA_CORE

ST470U2VDM-6-GP-U

MUXLESS

PC9209

12

DY

SC10P50V2JN-4GP

12

PC9208

PC9210

12

DY

12

PT9202

MUXLESS

SCD1U10V2KX-4GP

77.24771.15L

2nd = 79.47719.9BL

SC10P50V2JN-4GP

12

R9213

R9213 75KR2F-GP

75KR2F-GP

MUXLESS

PWR_VGA_CORE_D1

GND_SENSE 83

ST470U2VDM-6-GP-U

3

0928 Follow Brian suggestion.

0923 Update value of PR9210, PR9209 and PR9213 for N12P.

ST470U2VDM-6-GP-U

12

PT9203

3

MUXLESS

77.24771.15L

2nd = 79.47719.9BL

ST470U2VDM-6-GP-U

12

A00 1224

PT9204

3

MUXLESS

77.24771.15L

2nd = 79.47719.9BL

MUXLESS

1

2345

6

DDD

D

DDD

D

PU9202

5V_S5

I I

SC1U10V2KX-1GP

MUXLESS

PR9201

1 2

PR9204 6K2R2F- GP

12

MUXLESS

H H

G G

F F

E E

D D

C C

B B

MUXLESS

SC1U10V2KX-1GP

PC9207

MUXLESS

20100702_PWR

8209A_PGOOD_VGA

SC100P50V2JN-3GP

3D3V_VGA_S0

PC9212

MUXLESS

PC9201

12

10R2F-L-GP

PWR_VGA_CORE_VDD

8209A_PGOOD_VGA PWR_VGA_CORE_CS

8209A_EN/DEM_VGA

3D3V_VGA_S0

DGPU_PWR _EN93

12

PR9212

PR9212 10KR2J-3-GP

10KR2J-3-GP

MUXLESS

PR9214

1 2

12

DY

12

0R0402-PAD

MUXLESS

PWR_VGA_CORE_TON

PU9201

16

TON

9

VDDP

2

VDD

4

PGOOD

10

CS

15

EM/DEM

17

GND

RT8208BGQW- GP

MUXLESS

PR9206 10KR2J-3-GP

1 2

PD9201

2 1

CH551H-30PT-GP

PWRCNTL_0 PWRCNTL_1

0728 0805

DGPU_PWR OK 22,83,93

BOOT

UGATE PHASE LGATE

VOUT

DY

MUXLESS

G0 FB G1 D1 D0

MUXLESS

PR9202 249KR2F-GP

1 2

PR9205

MUXLESS

PWR_VGA_CORE_BOOT PWR_VGA_CORE_BOOT_C

13

PWR_VGA_CORE_UGATE

12

PWR_VGA_CORE_PHASE

11

PWR_VGA_CORE_LGATE

8 7

PWR_VGA_CORE_FB

3 14

PWR_VGA_CORE_D1

5

PWR_VGA_CORE_D0

6

PWR_VGA_CORE_VOUT

1

8209A_EN/DEM_VGA

12

PC9211

PC9211 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

PR9225

PR9225 10KR2J-3-GP

10KR2J-3-GP

MUXLESS

12

PR9227

PR9227 10KR2J-3-GP

10KR2J-3-GP

DY

3D3V_VGA_S0

0728

3K3R2J-3-GP

DY

3K3R2J-3-GP

VENTURA

12

R9227

R9228

PR9224

PR9224 10KR2J-3-GP

10KR2J-3-GP

PR9226

PR9226 10KR2J-3-GP

10KR2J-3-GP

1 2

2D2R3-1-U-GP

PWRCNTL_0 86 PWRCNTL_1 86

DY

MUXLESS

3D3V_VGA_S0

12

PR9218

1 2

0R0402-PAD

PR9219

1 2

0R0402-PAD

HPA00900AIDCNR-GP

74.00900.079

12

R9225

R9225 3K3R2J-3-GP

3K3R2J-3-GP

DY

12

R9226

R9226 3K3R2J-3-GP

3K3R2J-3-GP

VENTURA

PC9206

MUXLESS

1 2

SCD1U25V3KX-GP

VGA_CORE_UGATE VGA_CORE_LGATE

RT8208B

P-State

P0(Cold)

PR9210//R9209//PR9213

P0(Hot)

PR9210//PR9213

ES

R9210//PR9209

P8 & P12

PR9210

PWRCNTL_1 (GPIO6) (GPIO5)

0923 update table

0705 Modify

DCBATOUT

PU9205_A1 PU9205_A0

DCBATOUT_GPU

A00 1223 not co-lay

1 2

PR9217 D004R3720F- GPPR9217 D 004R 3720F-GP

PR9215

PR9215 10R2F-L-GP

10R2F-L-GP

VENTURA

PC9217

PU9205_VIN+

1 2

VENTURA

SCD1U25V2KX-GP

1

3

4

2

VS

VIN-

GND

VIN+

VENTURA

SCL5SDA6A07A1

PU9206

8

L

HH

FOR NVIDIA VENTURA

PR9221

PR9221 10R2F-L-GP

10R2F-L-GP

VENTURA

PU9205_VIN-

1 2

PU9202 IRF6721SPBF-GP-U

IRF6721SPBF-GP-U

84.06721.030

S

G

S

G

2nd = 84.45N03.A30

MUXLESS

1

23

6

7

DDD

PU9204

PU9204 IRF6725MTRPBF-GP-U

IRF6725MTRPBF-GP-U

84.06725.030

SSGD

2nd = 84.17N03.030

4

5

MUXLESS

PWRCNTL_0

L

H

L

0705 Modify

0705 Modify: Removed PR9222 sense Resistor. Add PR9215,PR9216,PC9201

3D3V_VGA_S0

VENTURA

SMBC_INA219 43,85 SMBD_INA219 43,85

0702 Modify: Change U4306 power source to 3D3V_VGA_S0 from 3D3V_S0.

12

PC9216

PC9216 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

6

DDD

D

DDD

D

PU9203

PU9203 IRF6721SPBF-GP-U

IRF6721SPBF-GP-U

84.06721.030

S

G

S

G

2nd = 84.45N03.A30

MUXLESS

1

23

6

7

DDD

PU9205

PU9205 IRF6725MTRPBF-GP-U

IRF6725MTRPBF-GP-U

84.06725.030

SSGD

2nd = 84.17N03.030

4

5

MUXLESS

VGA_CORE_PWR

0.975V

0.954V (default boot up)

0.878VH

0.853V

Frequency setting 470K -->165KHz 200K -->323KHz 100K -->500KHz

0712 Modify: Change VENTURA solution part number to

74.00900.079 from 74.00219.079.

MUXLESS

1

2345

12

PC9215

PC9204

SC4D7U25V5KX-GP

SCD1U25V3KX-GP

MUXLESS

12

PR9230

DY

2D2R5F-2-GP

0809

PWR_VGA_SNUB

12

PC9218

PC9218 SC330P50V3KX-GP

SC330P50V3KX-GP

DY

0915

3D3V_S5

DY

1 2

PQ9206

PQ9206 DMN66D0LDW -7-GP

DMN66D0LDW -7-GP

8209A_EN/DEM_VGA PQ9206_3

0607

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

A A

10

9

8

7

6

5

4

3

Title

DC/DC_VGA CORE_RT8208A

Size Document Number Rev

Date: Sheet

2

Taipei Hsien 221, Taiw an, R.O.C.

QUEEN 15

A00

of

92 108Tuesday, January 04, 2011

of

92 108Tuesday, January 04, 2011

of

92 108Tuesday, January 04, 2011

1

5

4

3

2

1

3D3V_S0 to 3D3V_VGA_S0 Transfer

DY

PR9301

3D3V_S0

PR9316

PR9316 10KR2F-2-GP

10KR2F-2-GP

MUXLESS

D D

A00

C C

MUXLESS

1 2

MUXLESS

RUNPWROK19,45,46,47

3D3V_S0

DGPU_PWR _EN#18

dGPU mode

IGPU

IGPU with BACO

PR9319

10KR2F-2-GP

MUXLESS

1 2

PR9321

1 2

10KR2J-3-GP

DGPU_PWR_EN#

2nd = 84.DM601.03F

PR9337

100KR2J-1-GP

DY

G

S

L H

L

1 2

DMP2130L-7-GP

S

12

PC9324

SCD1U10V2KX-5GP

MUXLESS

PR9319_1

PQ9303

PQ9303 2N7002KDW-G P

2N7002KDW-G P

84.2N702.A3F

2N7002K-2-GP

MUXLESS

PQ9304

84.2N702.J31

2ND = 84.2N702.031

PQ9302_G

6

123 4

D

G

5

DGPU_PWR_EN

0R2J-2-GP

PQ9302

D

G

84.02130.031

2ND = 84.03413.A31

MUXLESS

3.3V_RUN_VGA_1

DGPU_PWR _EN 92

3D3V_VGA_S0

3D3V_VGA discharge

1 2

PR9314

PR9314 470R2J-2-GP

470R2J-2-GP

MUXLESS

NV do not need 1.8V

0628 Modify:

1D5V_VGA_S0

B B

Park_Madison Does Not Support BACO, So follow Old Sequence Seymour_Whistler_Robson Support BACO, So Change Sequence

0629 Modify: Reserved PD9301 connect DGPU_PWR_EN to PWR_1D5V_EN for power down sequence.

PD9301

DGPU_PWR _EN92

A A

2 1

CH551H-30PT-GP

DGPU_PWROK22,83,92

0628 Modify: Simplify 1D5V_ENABLE control circuit. Rmoved PQ9305,PR9327,PR9328 PQ9306.

5

change low Rds(on) MOSFET

AO4468, SO-8 Id=?A, Qg=9~12nC Rdson=17.4~22m ohm

1 2

PR9332

MUXLESS

2nd = 84.DM601.03F

PR9326

1 2

0R0402-PAD-2-GP

2nd = 84.DM601.03F

A00 1224

DY

MUXLESS

1D5V_VGA_EN#

100KR2J-1-GP

2N7002KDW-G P

84.2N702.A3F

MUXLESS

1D5V_VGA_EN

0630 Modify: Rename PWR_1D8V_EN to 1D8V_VGA_EN. Rename PWR_1D5V_EN to 1D5V_VGA_EN.

1D5V_S3 1D5V_VGA_S0

8 7 6

12

PC9327

MUXLESS

84.04468.037

2nd = 84.08882.037

SC10U6D3V3MX-GP

MUXLESS

PC9326

SCD01U50V2KX-1GP

5

PQ9305

6

123 4

15V_S5

GGDDSS

1D5V_ENABLE

Change PU9305 part number to 84.04468.037 same as U3601&U3602.

MUXLESS

PU9305

S

D

S

D

1

S

D

S

D

2

SGDD

AO4468-GP

1 2

12

20KR2F-L-GP

MUXLESS

PR9331

PR9331 100KR2J-1-GP

100KR2J-1-GP

MUXLESS

1 2

PR9330

3 45

1D5V_ENABLE_RC

12

PC9332

PC9332 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

MUXLESS

Discharge Circuit

1D5V_VGA_S03D3V_AUX_S5

12

PR9336

PR9336 470R2J-2-GP

470R2J-2-GP

MUXLESS

2ND = 84.2N702.031

84.2N702.J31

2N7002K-2-GP

DIS_1D5V_VGA_S0

D

MUXLESS

PQ9307

4

0629 Modify: Add PC9332 10uF 0603.

1D5V_VGA_EN#

G

S

G9731F11U-GP for 1V_S0

3D3V_VGA_S0 should ramp-up before VGA_Core VGA_Core should ramp-up before 1V_VGA_S0 1V_VGA_S0 should ramp up before 1D8V_VGA_S0

so 1V_VGA_S0 EN have to fine tune RC delay after VGA_Core

3D3V_VGA_S0

0629 Modify: Reserved PD9302 connect DGPU_PWR_EN to PWR_1V_EN for power down sequence.

DGPU_PWR _EN92

9025_PGOOD_1V85

0915

3D3V_S5

3

9025_PGOOD_1V PWR_1V_PGOOD

5V_S5

PR9318

1 2

100KR2J-1-GP

DY

2nd = 84.DM601.03F

DY

PR9312

1 2

MUXLESS

0R0402-PAD-2-GP

PD9302

2 1

CH551H-30PT-GP

A00 1224

PR9313

1 2

MUXLESS

0R0402-PAD-2-GP

PWR_1V_EN#

2N7002KDW-G P

84.2N702.A3F

PWR_1V_EN

0927

A00 1224

DY

PR9311

1 2

MUXLESS

0R0402-PAD-2-GP

PQ9311

0630 Modify Change PR9312 to 10K 0402 from 0ohm and stuff PC9318.

3D3V_VGA_S0

12

MUXLESS

12

PC9313

SC1U6D3V2KX-GP

MUXLESS

SC1U6D3V2KX-GP

MUXLESS

5

6

123 4

PQ9308_3

PWR_1V_EN

12

DY

PR9324

PR9324 2K2R2J-2-GP

2K2R2J-2-GP

PWR_1V_VDD

1D5V_S3

PC9314

SC10U6D3V5MX-3GP

PR9317

12

470R2J-2-GP

DY

higih-side R + low-side R

Vout = 0.8 x

SCD1U10V2KX-5GP

PC9318

12

MUXLESS

low-side R

0714 Modify: Change LDO to Max 4A.

9 8

6 5

0728

1V_VGA_S0

2

PU9303

1

GND

2

VEN

ADJ

3

POK7VO#3

4

VO#4

VPP VIN

G9731F11U-GP

MUXLESS

74.G9731.03D

2nd = 74.05930.03D

Iomax<4A

PR9315

PR9315 15KR2F-GP

15KR2F-GP

MUXLESS

1 2

PWR_1V_ADJ

MUXLESS

PR9322 4K7R2F-GP

1 2

PC9315

1 2

DY

SC100P50V2JN-3GP

Vo(cal.)=1.05V

MUXLESS

Title

Size Document Number Rev

A2

Date: Sheet

0806

GAP-CLOSE-PWR

1V_PWR 1V_VGA_S0

GAP-CLOSE-PWR

12

PC9316

PC9317

SC10U6D3V5MX-3GP

DY

SC10U6D3V5MX-3GP

DY

SC10U6D3V5MX-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

DISCRETE VGA POWER

QUEEN 15

1

PG9308

1 2

PG9307

1 2

PG9305

1 2

PG9306

1 2

A00

of

93 108Tuesday, January 04, 2011

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

LVDS_Switch

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

94 108

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

CRT_Switch

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

95 108

1

A00

5

4

3

2

1

SSID = SDIO

D D

C C

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

TOUCH PANEL

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

96 108

1

A00

5

H6

H2

H2 HOLE335R115-GP

HOLE335R115-GP

ZZ.00PAD.D01

1

DY

D D

H3

H3 HOLE256R126-GP

HOLE256R126-GP

1

ZZ.00PAD.J01

C C

DY

H4

H4 HOLE256R126-GP

HOLE256R126-GP

1

ZZ.00PAD.J01

H1

H1 HT10X10BE10R32-D-5-GP

HT10X10BE10R32-D-5-GP

DY

ZZ.00PAD.J91

1

H11

H11 HOLE256R126-GP

HOLE256R126-GP

1

ZZ.00PAD.J01

H5

H5 HT10X10BE10R32-D-5-GP

HT10X10BE10R32-D-5-GP

DY

ZZ.00PAD.J91

1

H6

HOLE237R95-GP

DY

H12

H12 HOLE256R126-GP

HOLE256R126-GP

1

H13

H13 HT10X10BE10R32-D-5-GP

HT10X10BE10R32-D-5-GP

1

0901

4

ZZ.00PAD.921

1

ZZ.00PAD.J01

DY

ZZ.00PAD.J91

H7

H7 HT10X10BE10R32-D-5-GP

HT10X10BE10R32-D-5-GP

DY

ZZ.00PAD.J91

1

3

H10

H9

H9 HOLE335R115-GP

HOLE335R115-GP

ZZ.00PAD.D01

1

DY

H10 HOLE335R115-GP

HOLE335R115-GP

ZZ.00PAD.D01

1

DY

CPU Thermal module hole

HTML1

HTML1 HOLE197R166-GP

HOLE197R166-GP

1

DY

H15

H15 HT10X10BE10R32-D-5-GP

HT10X10BE10R32-D-5-GP

HTML2

HTML2 HOLE197R166-GP

HOLE197R166-GP

DY

ZZ.00PAD.J91

1

HTML3

HTML3 HOLE197R166-GP

HOLE197R166-GP

1

DY

2

1

Check test point

0624 Modify:

stand off

0721 Modify: Removed SPR1

1

0915 X01 Modify:

RF CAP

1D5V_S3 5V_S55V_S0 5V_S0 3D3V_S5 5V_S5DCBATOUT

1D5V_S3 3D3V_S5 3D3V_S5 3D3V_S0 3D3V_S0

EC9734

SCD1U50V3KX-GP

EC9734

SCD1U50V3KX-GP

EC9716

SCD1U50V3KX-GP

EC9716

SCD1U50V3KX-GP

12

DY

DCBATOUT DCBATOUT 3D3V_S5 3D3V_S51D05V_VTT5V_S5 3D3V_S0 3D3V_S01D5V_S3 5V_S0 5V_S0

EC9728

SCD1U50V3KX-GP

EC9728

SCD1U50V3KX-GP

12

DY

12

DY

EC9723

SCD1U50V3KX-GP

EC9723

SCD1U50V3KX-GP

12

DY

12

Reserved EC9701~EC9723 0.1uF for RF suggestion.

EC9718

SCD1U50V3KX-GP

EC9718

SCD1U50V3KX-GP

EC9719

SCD1U50V3KX-GP

EC9719

SCD1U50V3KX-GP

EC9736

SCD1U50V3KX-GP

EC9736

12

DY

EC9724

EC9731

SCD1U50V3KX-GP

EC9731

SCD1U50V3KX-GP

12

DY

SCD1U50V3KX-GP

DY

SCD1U50V3KX-GP

12

DY

EC9727

SCD1U50V3KX-GP

EC9727

SCD1U50V3KX-GP

12

DY

EC9720

SCD1U50V3KX-GP

EC9720

SCD1U50V3KX-GP

12

EC9729

12

SC470P50V-2-GP

Removed AFTP1,AFTP7~AFTP13.

SC47P50V3JN-GP

EC9717

SCD1U50V3KX-GP

EC9717

DY

12

SCD1U50V3KX-GP

12

EC9732

EC9730

SC470P50V-2-GP

EC9730

SC470P50V-2-GP

12

DY

12

SCD1U50V3KX-GP

DY

EC9735

SC47P50V3JN-GP

EC9737

12

EC9733

SCD1U50V3KX-GP

EC9733

SCD1U50V3KX-GP

12

DY

SCD22U50V3ZY-1GP

EC9722

SCD1U50V3KX-GP

EC9722

12

DY

EC9725

SCD1U50V3KX-GP

EC9725

SCD1U50V3KX-GP

12

DY

SCD1U50V3KX-GP

EC9726

12

EC9738

EC9721

SCD1U50V3KX-GP

EC9721

SCD1U50V3KX-GP

12

DY

3D3V_S0

SC47P50V3JN-GP

EC9739

SCD1U50V3KX-GP

12

3D3V_S0 1D8V_S0

B B

12

DY

SCD1U10V2KX-4GP

EC9701

DY

SCD1U10V2KX-4GP

12

EC9702

12

EC9703

DY

SCD1U10V2KX-4GP

DCBATOUT DCBATOUT

DY

12

EC9704

SCD1U50V3KX-GP

1D8V_S0

12

DY

SCD1U50V3KX-GP

EC9705

12

EC9706

DY

SCD1U50V3KX-GP

12

EC9707

DY

SCD1U50V3KX-GP

12

EC9708

DY

SCD1U50V3KX-GP

12

EC9709

DY

SCD1U50V3KX-GP

12

EC9710

DY

SCD1U50V3KX-GP

DCBATOUT

12

DY

3D3V_S0

EC9711

SCD1U50V3KX-GP

1D5V_S3 1D5V_S3 1D5V_S3 1D5V_S0

12

EC9712

DY

SCD1U10V2KX-4GP

12

EC9713

DY

SCD1U10V2KX-4GP

12

EC9714

DY

SCD1U10V2KX-4GP

12

EC9715

DY

SCD1U10V2KX-4GP

0802 For EMI/ESD.

HHD1

HHD1 STF237R117H83-1-GP

STF237R117H83-1-GP

A A

5

4

1

34.4CK01.001

2nd = 34.4CK01.401

3rd = 34.4CK01.501

A00 0103 add 3rd LIDON(34.4CK01.501) on HDD1,HDD4,HGPU1,HGPU2 at XBuild batch run

GPU Thermal module hole

HGPU1

HGPU1 STF237R117H83-1-GP

STF237R117H83-1-GP

1

34.4CK01.001

2nd = 34.4CK01.401

3rd = 34.4CK01.501

HGPU2

HGPU2 STF237R117H83-1-GP

STF237R117H83-1-GP

1

34.4CK01.001

2nd = 34.4CK01.401

3rd = 34.4CK01.501

3

HHD4

HHD4 STF237R117H83-1-GP

STF237R117H83-1-GP

1

34.4CK01.001

2nd = 34.4CK01.401

3rd = 34.4CK01.501

HBT1

HBT1 STF237R117H123-GP

STF237R117H123-GP

DY

1

34.4DM11.001

2nd = 34.4A902.001

2

0818

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitor s

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

97 108

1

A00

5

4

3

2

1

Huron River Platform Power Sequence

(AC mode)

+RTC_VCC

T1

PM_PWRBTN#

AC

>9ms

T2

3D3V_AUX_KBC

PM_PWRBTN#

T10

ALL_SYS_PWRGD=D85V_PWRGD

D85V_PWRGD

1D8V_S0

T3

T4

0D85V_S0

RTC_RST#

Within logic high level and disable if it is less than the logic low level.

D D

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

Not floating.

Sense the power button status

This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input.

C C

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

DCBATOUT

3D3V_AUX_S5

S5_ENABLE

5V_S5

3D3V_S5

PM_RSMRST#(EC Delay 40ms)

PCH_SUSCLK_KBC

AC_PRESENT

KBC_PWRBTN#

AC

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

1D5V_S3

DDR_VREF_S3(0.75V)

5V_S0

3D3V_S0

+5VS_PCH_VCC5REF

1D5V_S0

1D8V_S0

0D75V_S0

RUNPWROK

1D05V_VTT T21

1.05VTT_PWRGD

0D85V_S0

D85V_PWRGD

CPU SVID BUS

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

CLK_EXP_P

B B

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

PWROK

VDDPWRGOOD

H_CPUPWRGD

SYS_PWROK

PLT_RST#

DMI

T5+5VA_PCH_VCC5REFSUS

T6

>10ms

Press Power button

T11

>30us

T12

T13

T14

T15

T17

T18

T19

T24

>99ms

T27

2ms< <650ms

T29

red word: KBC GPIO

KBC GPIO34 control power on by 3V_5V_EN

>5ms

<90msT7T8

0ms<

>16ms

T9

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T16

T20

>0us

T28

>1ms

T30

>2ms

T31

5ms< <650ms

T32

KBC GPIO43 to PCH PCH to KBC GPIO00 KBC GPO84 to P CH

Platform to KBC PSL_IN2

KBC GPIO20 to PCH

PCH to KBC GPIO44 PCH to KBC GPIO01 KBC GPIO23 to LAN

Enable by PM_SLP_S4#

T22

SetVID ACK

T33

1ms<

T35

1D8V_S0 & 1D5V_S3 power ready

VT357FCX PGOOD

T23

TPS51461RGER PGOOD

<2000us50us<

T25

T26

ISL95831 PGOOD to system

<5ms

KBC GPIO77 to PCH

>0ms <100ms

T34

>1ms+60us

T36

PCH to all system

<200us

PCH to CPU

(DC mode)

Sense the power button status

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

+RTC_VCC

RTC_RST#

DCBATOUT

3D3V_AUX_S5

KBC_PWRBTN#

3D3V_AUX_KBC

S5_ENABLE

5V_S5

3D3V_S5

+5VA_PCH_VCC5REFSUS

PM_PWRBTN#

PM_RSMRST#

PCH_SUSCLK_KBC

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

1D5V_S3

DDR_VREF_S3(0.75V)

5V_S0

3D3V_S0

+5VS_PCH_VCC5REF

1D5V_S0

1D8V_S0

0D75V_S0

RUNPWROK

1D05V_VTT T21

1.05VTT_PWRGD

0D85V_S0

D85V_PWRGD

CPU SVID BUS

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

CLK_EXP_P

PWROK

VDDPWRGOOD

H_CPUPWRGD

SYS_PWROK

PLT_RST#

DMI

DC

T1

PCH_RSMRST#

red word: KBC GPIO

>9ms

T2

Press Power button

T10

T11

>30us

0D85V_S0

ALL_SYS_PWRGD=D85V_PWRGD

T27

D85V_PWRGD

2ms< <650ms

1D8V_S0

>99ms

Platform to KBC PSL_ I N2

T3

T4

T5

T6

T12

T13

T14

T15

T17

T18

T19

T24

T28

T29

EC_ENABLE#_1(GPIO31) keep low

KBC GPIO34 control power on by 3V_5V_EN

+5V_ALW & +3.3V_ALW need meet 0.7V difference

T7

>16ms

T8

>10ms

T9

>5ms

KBC GPIO20 to PCH

KBC GPIO43 to PCH PCH to KBC GPIO00

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T16

T20

SetVID ACK

>0us

>1ms

T30

>2ms

T31

5ms< <650ms

T32

PCH to KBC GPIO44 PCH to KBC GPIO01 KBC GPIO23 to LAN

Enable by PM_SLP_S4#

1D8V_S0 & 1D5V_S3 power ready

T22

T23

<2000us50us<

T25

T26

<5ms

>0ms

T33

<100ms

1ms<

T35

VT357FCX PGOOD

TPS51461RGER PGOOD

ISL95831 PGOOD to system

KBC GPIO77 to PCH

PCH to CPU

>1ms+60us

T34

PCH to all system

<200us

T36

N12P-GE Power-Up/Down Sequence

DGPU_PWR_EN#(Discrete only)

3D3V_VGA_S0(VDD33)

8209A_EN/DEM_VGA(Discrete only)

VGA_CORE(NVVDD)

A A

DGPU_PWROK(Discrete only)

1D5V_VGA_S0(FBVDDQ)

First rail to power down

Last rail to power down

3D3V_S0

tPOWER-OFF

<10ms

tNVVDD

>0ms

tNV-FBVDDQ

>0ms

For power-down, reversing the ramp-up sequence is recommended.

5

PCH GPIO54 output

VGA_CORE,1V_VGA_S0 1D5V_VGA_S0,3D3V_VGA_S0

4

RT8208 PGOOD

Title

Size Document Number Rev

A1

Tuesday, January 04, 2011

Date: Sheet

Tuesday, January 04, 2011

Date: Sheet

Tuesday, January 04, 2011

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Power Sequence

QUEEN 15

A00

98

of

108

5

4

3

2

1

Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

AC

Adapter in

D D

PWR_CHG_ACOK

DC Battery

C C

BT+

Page39

Page38

SWITCH

BQ24745 Charger

Page40

-1

Power Button

AD+

Page40

DCBATOUT

ACOK

5V_S5 DCBATOUT

-6.1

-4

AC_IN#

KBC_PWRBTN#

PM_SLP_S4#

PM_SLP_S3#

-3.1 -3.1 -3.1

1

PWR_5V3D3V_ENC

ENC

RT8223MGQW DC/DC (3V/5V)

VIN

-3

3D3V_AUX_KBC

GPIO70

KBC

GPIO6

NPCE795P

GPIO44 GPIO01

GPIO34

GPIO43 GPIO20

Page27

GPIO77

LL1 LL2

VREG5 VREG3

PGOOD

Page41

-3.2

5V_S5 3D3V_S5

5V_AUX_S5 3D3V_AUX_S5

3V_5V_POK

-3.1

S5_ENABLE

-2.1

PM_RSMRST#

PM_PWRBTN#

S0_PWR_GOOD

SYS_PWROK

2

3V_5V_EN S5_ENABLE

-3.3

15V_S5

PUMP

-5

-2

BJT

SLP_S4# SLP_S3#

RSMRST#

PWRBTN#

Cougar Point

3

PM_SLP_S4#

4

PM_SLP_S3#

DRAMPWRGD

PROCPWRGD

PCH

APWROK

PWROK

SYS_PWROK

PLTRST#

10

11

12

13

PLT_RST#

SWITCH

Page37

SWITCH

Page37

SWITCH

Page37

5V_S0

3D3V_S0

1D5V_S0

0D75V_EN

PM_DRAM_PWRGD

H_CPUPWRGD

AND GATE

B

A

Y

VDDPWRGOOD

H_CPUPWRGD_R

BUF_CPU_RST#

SM_DRAMPWROK

UNCOREPWRGOOD

Sandy Bridge CPU

RSTIN#

SVID

3

PM_SLP_S4#

4

PM_SLP_S3#

SVID

8

-6

DCBATOUT5V_S5

VDDP VIN

EN

TPS51116RGER

Page46

5V_S5 3D3V_S5

VDD VIN

TPS53311RGTR

EN

Page47

VOUT

REF

VTT

PGD

VOUT

PGD

1D5V_S3

DDR_VREF_S3

0D75V_S0

RUNPWROK

5

1D8V_S0

RUNPWROK

5

B B

5

RUNPWROK

5a

1.05VTT_PWRGD

8

A A

6

D85V_PWRGD

SVID

7

IMVP_VR_ON

5

V5IN VIN

TPS51218DSCR

EN

Page45

DCBATOUT

5V_S5

VIN

VDDP

RT8208BGQW

EN

Page48

DCBATOUT

VIN

VR

OUTPUT

SVID

ISL95831HRTZ

VR_ON

Page42 & 43 & 44

PGOOD

VOUT

PGOOD

VOUT

PGOOD

1D05_VTT

1.05VTT_PWRGD

5a

0D85_S0

D85V_PWRGD

6

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

Y

10

SYS_PWROK

-7

RTC_AUX_S5

-5

3D3V_AUX_S5

-8

+RTC_VCC

RTC battery

Power Up Sequence: -8 ~ 13

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet

Tuesday, January 04, 2011

2

Tuesday, January 04, 2011

Taipei Hsien 221, Taiw an, R.O.C.

Power Sequence Diagram

QUEEN 15

1

99

of

A00

108

S0_PWR_GOOD

IMVP_PWRGD

AND GATE

A

B

9

4

5

4

3

2

1

D D

RT8208B

Adapter

DCBATOUT TPS51216RUKR

VGA_CORE

ISL95831HRTZ

For Discrete

TPS51218DSCR

AO4407A

1V_VGA_S0

0D75V_S0DDR_VREF_S3

RT9025

1D5V_S3

Charger

VCC_GFXCORE

For UMA

1D05V_VTT

TPCA8062

AO4468

Battery

BQ24745

+PBATT

VCC_CORE

APL5916KAI

1D5V_S0

C C

0D85V_S0

1D5V_DDR_S0

TPS51123RGER

For Discrete

15V_S5

3D3V_AUX_S5

DMP2130L

3D3V_AUX_KBC

B B

5V_AUX_S5

5V_S5

AO4468

5V_S0

G547F2P81U

5V_USB1_S3

CRT Board USB Power

AO4468

3D3V_S0

3D3V_S5

TPS51311RGTR

1D8V_S0

PA102FMG

3D3V_LAN_S5

1D8V_VGA_S0

LCDVDD

RTS5138

3D3V_CARD_S0

DMP2130LG5285T11UAO4468

3D3V_VGA_S0

RTL8111E

+1.2V_LOM

For Discrete For Discrete

Power Shape

A A

5

4

Regulator LDO Switch

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

Power Block Diagram

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

100 108Tuesday, January 04, 2011

1

A00

Wistron Queen 15 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual