Wistron Queen 15 Schematic

5

4

3

2

1

Discrete/UMA Schematics Document

D D

Sandy Bridge

Intel PCH

2011-01-04 REV : A00

C C

DY :None Installed UMA:UMA ONLY installed DN15: ONLY FOR DN15 installed. DQ15:ONLY FOR DQ15 installed. PSL: KBC795 PSL circuit for 10mW solution installed. 10mW: External circuit for 10mW solution installed.

B B

MUXLESS:MUXLESS solution installed. OPTIMUS:OPTIMUS solution installed.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Cover Page

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

1 108

1

A00

5

##OnMainBoard

1.N12P-GE-A1-GP(64Mx16b*8)

D D

WKS P/N:72.51G63.H0U HYNIX WKS P/N:72.41164.I0U SAMSUNG

VRAM

1GB

88,89,90,91

DDR3 800MHz

Robson-XT& Seymour-XT& Whistler-LP& N12P-GE

ATI : Co-layout HDMI coming from UMA(default) & dGPU by reserving Resistor(0ohm) for optional selection.

NVidia : Co-layout HDMI coming from dGPU(Default) &

C C

UMA by reserving Resistor(0ohm) for optional selection.

HDMI

LCD

CRT

Left Side: USB x 1

DCIN

B B

51

49

CRT Board

Bluetooth

CAMERA

VOSTRO

Finger Print

15~25W

83.84,85,86,87

Discreet/UMA Co-lay

HDMI

LVDS(Sigal Channel)

RGB CRT

82

63

54

64

4

3

Block Diagram (Discrete/UMA co-lay)

4

PCIe x 16

(Discrete only)

USB2.0 x 5

AZALIA

FDIx4x2 (UMA only)

PCH Cougar Point

Intel CPU

Sandy Bridge

4,5,6,7,8,9,10,11,12,13

DMIx4

Intel

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6) PCIE ports (8)

LPC I/F ACPI 1.1

17,18,19,20,21,22,23,24,25,26

Project code : 91.4IE01.001 PCB P/N : 10260-1 Revision : A00

DDRIII 1066/1333 Channel A

DDRIII 1066/1333 Channel B

PCIE x 4

USB 2.0 x 3

I/O Board

SATAx1 / USB2.0x1

USB 2.0 x 1¡BPCIE X 1

USB 2.0 x 1

PCIE x 1

PCIE x 1,USB x 1

Connector

82

ESATA/USB/Powershare Combo

2

DDRIII 1066/1333

PCIE x 1 USB2.0 x 1

PCIE x 1

NEC USB3.0

UPD720200FA

VOSTRO

Express Card

(On daughter board)

Slot 0

14

Slot 1

15

RTL8111E/8105E

57

INPUTS

1D05V_VTT

Mini-Card

802.11a/b/g

10/100/ 1000 NIC

Realtek

Mini-Card

WWAN

75

SYSTEM LDO

APL5916

OUTPUTS

0D85V_S0

RJ45 CONN

USB3.0 X2 CONN

SIM

HP1 MIC IN

1

48

CPU DC/DC

ISL95831HRTZ

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51218

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51123RGER

INPUTS

DCBATOUT 5V_S5

SYSTEM DC/DC

TPS51216RUKR

INPUTS

DCBATOUT

SYSTEM DC/DC

ISL95831HRTZ

INPUTS

DCBATOUT

RT8208B

INPUTS

DCBATOUT

TI CHARGER

BQ24745

INPUTS

+DC_IN_S5

26

SYSTEM DC/DC

TPS51311

INPUTS

3D3V_S5

SYSTEM DC/DC

G9731

INPUTS OUTPUTS

26

1D5V_S3 1V_VGA_S0

OUTPUTS

VCC_CORE

OUTPUTS

1D05V_VTT

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

OUTPUTS

VCC_GFXCORE

VGA

OUTPUTS

VGA_CORE

OUTPUTS

42~43

45

41

46

44

92

40

DCBATOUT+PBATT

47

1D8V_S0

93

Switches

Internal Digital MIC

A A

2CH SPEAKER

5

58

Azalia CODEC

IDT 92HD87

SPI

Flash ROM

4MB

29

LPC Bus

60

KBC

NUVOTON

NPCE795P

Touch PAD

4

69

Int. KB

69 25

SATA x 2

LPC debug port

D/A

A/D

27

Thermal

P2800

3

CardReader

71

Realtek RTS5138

HDD

ODD

32

56

SD/MMC+/MS/ MS Pro/xD

74

Fan Control

P2793

28

55

2

Title

Size Document Number Rev

A3

Date: Sheet

Block Diagram

QUEEN 15

INPUTS OUTPUTS

1D5V_S3 5V_S5

1D5V_S0 5V_S0 3D3V_S03D3V_S5

PCB LAYER

L1:Top L2:VCC L3:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

2 108Tuesday, January 04, 2011

L4:Signal L5:GND L6:Bottom

of

A00

A

PCH Strapping

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. Leave as "No Connect".

GNT3#/GPIO55

4 4

GNT2#/GPIO53 GNT1#/GPIO51

SPI_MOSI

NV_ALE

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-k£[

No Reboot Mode with TCO Disabled:

- 10-k£[ weak pull-up resistor.

GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Enable Danbury:

Disable Danbury:

Huron River Schematic Checklist Rev.0_7

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

B

C

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

PCI-Express Static Lane Reversal

CFG[4]

CFG[6:5]

CFG[7]

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

D

Huron River Schematic Checklist Rev.0_7

Default Value

1

0

11

1

E

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.

HAD_DOCK_EN# /GPIO[33]

3 3

High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

HDA_SYNC

GPIO15

GPIO8

2 2

GPIO27

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

Voltage Rails

ACTIVE IN

S0

CPU Core Rail Graphics Core Rail

S3

AC Brick Mode only

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

USB Table

Pair

PCIE Routing

0

1

LANE1 LANE2 LANE3 LANE4

1 1

LANE5 LANE6 LANE7 LANE8 Express Card

Card Reader Mini Card1(WLAN) Mini Card2(WWAN) Onboard LAN

USB3.0

Intel GBE LAN

Dock

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD1 HDD2

N/A N/A

ODD

ESATA

2

3

4

5

6

7

8

9

10

11

12

13

Device Touch Panel / 3G SIM USB Ext. port 1 (HS)

Fingerprint

BLUETOOTH Mini Card2 (WWAN) CARD READER X X

USB Ext. port 4 / E-SATA /USB CHARGER

USB Ext. port 2 USB Ext. port 3 Mini Card1 (WLAN) CAMERA

Express Card

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery CHARGER

EC SMBus 2 PCH eDP

PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI

HURON RIVER ORB

Address Hex Bus Ref Des

BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA

SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Table of Content

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

3 108

of

A00

5

4

3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_VTT

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3:0]19

DMI_TXP[3:0]19

DMI_RXN[3:0]19

DMI_RXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19 FDI_LSYNC019

FDI_LSYNC119

0719 Modify: un-stuff R403 base on Intel James feedback list.

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

R403

1 2

10KR2J-3-GP

DY

Stuff to disable internal graphics function for power saving.

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP eDP_HPD

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interfa ce is disabled, connect it to CPU VCCIO via a 10-k£[ pull-Up resistor on the motherboard.

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

J18 J17

H20

J19

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

SANDY

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

SKT-BGA989C470395-1H180

DMI

Intel(R) FDI

eDP

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

PEG_RXN[0..15]

PEG_RXP[0..15]

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

C401 SCD22U10V2KX-1GP

1 2

MUXLESS

C402 SCD22U10V2KX-1GP

1 2

MUXLESS

C403 SCD22U10V2KX-1GP

1 2

MUXLESS

C404 SCD22U10V2KX-1GP

1 2

MUXLESS

C405 SCD22U10V2KX-1GP

1 2

MUXLESS

C406 SCD22U10V2KX-1GP

1 2

MUXLESS

C407 SCD22U10V2KX-1GP

1 2

MUXLESS

C408 SCD22U10V2KX-1GP

1 2

MUXLESS

C409 SCD22U10V2KX-1GP

1 2

MUXLESS

C410 SCD22U10V2KX-1GP

1 2

MUXLESS

C411 SCD22U10V2KX-1GP

1 2

MUXLESS

C412 SCD22U10V2KX-1GP

1 2

MUXLESS

C413 SCD22U10V2KX-1GP

1 2

MUXLESS

C414 SCD22U10V2KX-1GP

1 2

MUXLESS

C415 SCD22U10V2KX-1GP

1 2

MUXLESS

C416 SCD22U10V2KX-1GP

1 2

MUXLESS

C417 SCD22U10V2KX-1GP

1 2

MUXLESS

C418 SCD22U10V2KX-1GP

1 2

MUXLESS

C419 SCD22U10V2KX-1GP

1 2

MUXLESS

C420 SCD22U10V2KX-1GP

1 2

MUXLESS

C421 SCD22U10V2KX-1GP

1 2

MUXLESS

C422 SCD22U10V2KX-1GP

1 2

MUXLESS

C423 SCD22U10V2KX-1GP

1 2

MUXLESS

C424 SCD22U10V2KX-1GP

1 2

MUXLESS

C425 SCD22U10V2KX-1GP

1 2

MUXLESS

C426 SCD22U10V2KX-1GP

1 2

MUXLESS

C427 SCD22U10V2KX-1GP

1 2

MUXLESS

C428 SCD22U10V2KX-1GP

1 2

MUXLESS

C429 SCD22U10V2KX-1GP

1 2

MUXLESS

C430 SCD22U10V2KX-1GP

1 2

MUXLESS

C431 SCD22U10V2KX-1GP

1 2

MUXLESS

C432 SCD22U10V2KX-1GP

1 2

MUXLESS

A A

1D05V_VTT

PEG_RXN[0..15] 83

PEG_RXP[0..15] 83

PEG Static Lane Reversal

PEG_TXN[0..15]

PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

PEG_TXP[0..15]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PCIE/DMI/FDI)

QUEEN 15

PEG_TXN[0..15] 83

PEG_TXP[0..15] 83

of

4 108

A00

SSID = CPU

5

1D05V_VTT

D D

0625 Modify: Add C502 47p 0402 on H_PROCHOT#.

R501

1 2

62R2J-GP

H_PROCHOT#

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

20100622 V1.2

CRB : 47pf CEKLT:43pf

Connect EC to PROCHOT# through inverting OD buffer.

C C

R510

PLT_RST#18,27,71,75,82,83

0617 Modify: Joseph Removed U501 Buffer reset to CPU circuit.

R510

B B

0719 Modify: Add buffer for PLT_RST# based on Intel review.

Buffered reset to CPU

PLT_RST#18,27,71,75,82,83

H_SNB_IVB#18

H_PROCHOT#27,40,42

H_THERMTRIP#22,36

H_PM_SYNC19

A00 1229 EMI

H_CPUPWRGD22,36

PM_DRAM_PWRGD19,37

VDDPWRGOOD37

1 2

1K5R2F-2-GP

1

TP501TPAD14-GP TP501TPAD14-GP

1

TP502TPAD14-GP TP502TPAD14-GP

H_PECI22,27

R513

1 2

56R2J-4-GP

EC505

R503

1 2

12

R509

R509 750R2F-GP

750R2F-GP

A00 1230 EMI

0623 Modify: Reserved C501 220pF 0402 on BUF_CPU_RST#.

U501

1

IN B

VCC

2

IN A

DY

GND3OUT Y

74VHC1G09DFT2G-GP

73.01G09.AAH

12

DY

R504

1 2

0R0402-PAD

10KR2J-3-GP

R505

1 2

0R2J-2-GP

DY

12

DY

EC506

MS04A03T2V2-GP-U

1D05V_VTT

5

4

MS04A03T2V2-GP-U

12

DY

12

DY

4

SKTOCC#_R

H_CATERR#

H_PROCHOT#_R

H_CPUPWRGD_R

VDDPWRGOOD

BUF_CPU_RST#

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

R518

R518 75R2J-1-GP

75R2J-1-GP

CPU1B

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

3D3V_S0

12

C503

DY

SCD1U10V2KX-5GP

1 2

DY

R517 43R2J-GP

SANDY

MISCTHERMALPWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

SKT-BGA989C470395-1H180

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

BUF_CPU_RST#BUFO_CPU_RST#

12

R515

DY

0R2J-2-GP

3

2 OF 9

BCLK

BCLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

MISC

PRDY# PREQ#

TRST#

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

A28 A27

CLK_DP_P_R

A16

CLK_DP_N_R

A15

R8

SM_RCOMP_0

AK1

SM_RCOMP_1

A5

SM_RCOMP_2

A4

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCLK

AR26

TCK TMS

TDI

TDO

AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

R512

1 2

1KR2J-1-GP

R514

1 2

1KR2J-1-GP

R502

1 2

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

1 1

0630 Modify: Removed XDP1101 connector related circuit by layout limitation.

12

EC502

SC1KP50V2KX-1GP

CLK_EXP_P 20 CLK_EXP_N 20

1D05V_VTT

TP511 TPAD14-GPTP511 TPAD14-GP TP512 TPAD14-GPTP512 TPAD14-GP

1

TP503 TPAD14-GPTP503 TPAD14-GP

1

TP504 TPAD14-GPTP504 TPAD14-GP

1

TP505 TPAD14-GPTP505 TPAD14-GP

1

TP506 TPAD14-GPTP506 TPAD14-GP

1

TP507 TPAD14-GPTP507 TPAD14-GP

1

TP508 TPAD14-GPTP508 TPAD14-GP

1

TP509 TPAD14-GPTP509 TPAD14-GP

1

TP510 TPAD14-GPTP510 TPAD14-GP

XDP_TRST#

XDP_DBRESET#

12

EC504

0617 Modify: Joseph change RN501 to R512,R514 1K 0402 Resistor.

SM_DRAMRST# 37

SC1KP50V2KX-1GP

2

XDP_DBRESET#19

A00 1229 EMI

1 2

8 7 6

1

R516

R516 10KR2J-3-GP

10KR2J-3-GP

1D05V_VTT

3D3V_S0

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

0721 Modify: SWAP RN501 pin1,2,3 base on swap report.

RN501

XDP_TDO XDP_TMS XDP_TDI XDP_TCLK

XDP_TRST#

XDP_DBRESET#

RN501

1 2 3 4 5

SRN51J-1-GP

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

0707 Modify: Change R516 10K from 1K

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

CPU (THERMAL/CLOCK/PM )

QUEEN 15

Tuesday, January 04, 2011

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

5 108

of

A00

5

4

3

2

1

SSID = CPU

4 OF 9

3 OF 9

CPU1C

SANDY

M_A_DQ[63:0]15 M_B_DQ[63:0]14

D D

C C

B B

M_A_DQ[63:0]

M_A_BS015 M_A_BS115 M_A_BS215

M_A_CAS#15 M_A_RAS#15 M_A_WE#15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5

AK6 AK5 AH5 AH6

AK8 AK9

AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

V6

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CLK2

SA_CLK#2

SA_CKE2

SA_CLK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 15 M_A_DIM0_CLK_DDR#0 15 M_A_DIM0_CKE0 15

M_A_DIM0_CLK_DDR1 15 M_A_DIM0_CLK_DDR#1 15 M_A_DIM0_CKE1 15

M_A_DIM0_CS#0 15 M_A_DIM0_CS#1 15

M_A_DIM0_ODT0 15 M_A_DIM0_ODT1 15

M_A_DQS#[7:0] 15

M_A_DQS[7:0] 15

M_A_A[15:0] 15

M_B_DQ[63:0]

M_B_BS014 M_B_BS114 M_B_BS214

M_B_CAS#14 M_B_RAS#14 M_B_WE#14

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9 AA7

AA10

AB8 AB9

CPU1D

SANDY

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CLK2

SB_CLK#2

SB_CKE2

SB_CLK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_CLK_DDR0 14 M_B_DIM0_CLK_DDR#0 14 M_B_DIM0_CKE0 14

M_B_DIM0_CLK_DDR1 14 M_B_DIM0_CLK_DDR#1 14 M_B_DIM0_CKE1 14

M_B_DIM0_CS#0 14 M_B_DIM0_CS#1 14

M_B_DIM0_ODT0 14 M_B_DIM0_ODT1 14

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[15:0] 14

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

A A

5

3rd = 62.10055.321

A00 0103 add 3rd foxcon CPU1 at XBuild batch run A00 0103 add 3rd foxcon CPU1 at XBuild batch run

4

3

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

CPU (DDR)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

6 108

1

A00

5

4

3

2

1

SSID = CPU

0630 Modify: Reserved TP715 on CFG0.

CFG0

1

TP715TPAD14-GP TP715TPAD14-GP

D D

0707 Modify: Removed CFG1,CFG3,CFG8~17 TP.

0617 Modify: Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

M3 - Processor Generated SO-DIMM VREF_DQ

DY

R708 0R2J-2-GP

1 2

DY

M_VREF_DQ_DIMM0

C C

B B

M_VREF_DQ_DIMM1

R707 0R2J-2-GP

M_VREF_CA_DIMM0 M_VREF_CA_DIMM1

0719 Modify: Reserved EC701 0.1uF near R711(BOTTOM) for EMC NEO suggestion.

R707 0R2J-2-GP R706 0R2J-2-GP

R706 0R2J-2-GP

1D05V_VTT

12

DY

EC701

SCD1U50V3KX-GP

DY

R709 0R2J-2-GP

1 2

DY

1 2

DY

0629 Modify: Reserved R710 0ohm to GND to follow EV board schematic.

R710 0R2J-2-GP

1KR2F-3-GP

1 2

DY

M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C

R711

20 mils

CFG2 CFG4

CFG5 CFG6 CFG7

B4:VREF_DQ CHA

D1:VREF_DQ CHB

12

R712

R712 1KR2F-3-GP

1KR2F-3-GP

H_VCCP_SEL

CPU1E

AK28

CFG0

AK29

CFG1

AL26

CFG2

AL27

CFG3

AK26

CFG4

AL29

CFG5

AL30

CFG6

AM31

CFG7

AM32

CFG8

AM30

CFG9

AM28

CFG10

AM26

CFG11

AN28

CFG12

AN31

CFG13

AN26

CFG14

AM27

CFG15

AK31

CFG16

AN29

CFG17

AJ31

RSVD#AJ31

AH31

RSVD#AH31

AJ33

RSVD#AJ33

AH33

RSVD#AH33

AJ26

RSVD#AJ26

B4

RSVD#B4

D1

RSVD#D1

F25

RSVD#F25

F24

RSVD#F24

F23

RSVD#F23

D24

RSVD#D24

G25

RSVD#G25

G24

RSVD#G24

E23

RSVD#E23

D23

RSVD#D23

C30

RSVD#C30

A31

RSVD#A31

B30

RSVD#B30

B29

RSVD#B29

D30

RSVD#D30

B31

RSVD#B31

A30

RSVD#A30

C29

RSVD#C29

J20

RSVD#J20

B18

RSVD#B18

A19

RSVD#A19

J15

RSVD#J15

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

SANDY

RESERVED

SKT-BGA989C470395-1H180

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

5 OF 9

RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16

RSVD#G16

RSVD#AR35

RSVD#AT34 RSVD#AT33

RSVD#AP35

RSVD#AR34

RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35

RSVD#AJ32

RSVD#AK32

RSVD#AH27

RSVD#AN35 RSVD#AM35

RSVD#AT2 RSVD#AT1 RSVD#AR1

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

0702 Modify

TP713

AN35

TP714

AM35

AT2 AT1 AR1

CFG5 CFG6

1 1

CFG2

CFG4

DY

CFG7

TP713 TPAD14-GPTP713 TPAD14-GP TP714 TPAD14-GPTP714 TPAD14-GP

12

R702

R702 1KR2J-1-GP

1KR2J-1-GP

MUXLESS

12

DY

12

R701

R704

DY

1KR2J-1-GP

12

R705

R705 1KR2J-1-GP

1KR2J-1-GP

DY

0630 Modify: Removed CLK_XDP_ITP_P&N and reserved TP713,TP714.

PEG Static Lane Reversal

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

Display Port Presence Strap

R703

R703 3K3R2F-2-GP

3K3R2F-2-GP

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG DEFER TRAINING

CFG7

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

CPU (RESERVED)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

7 108

1

A00

5

SSID = CPU

D D

1115 X02 Modify: Reserved C802~C804,C806,C807 10uF 0603

VCC_CORE

C C

0819 De-cap

B B

A A

PROCESSOR CORE POWER

53A

12

C802

C801

QC

SC10U6D3V3MX-GP

0713 Modify: Removed C802,C811 10uf 0603 cap base on layout limitation.

12

C820

C819

12

C819

DY

SC10U6D3V3MX-GP

0713 Modify: Removed C818 10uf 0603 cap base on layout limitation.

12

C821

C816

SC10U6D3V5KX-1GP

0721 Modify: Removed C836.

C837

SC22U6D3V5MX-L2GP

5

DY

0726 Modify: un-stuff C837.

12

C803

QC

SC10U6D3V3MX-GP

12

QC

0721 Modify: Removed C822,C823,C824

SC10U6D3V5KX-1GP

12

C835

SC10U6D3V5KX-1GP

VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity

for power team fine tune Vcore quality.

X02 1115

12

C806

QC

SC10U6D3V3MX-GP

C833

SC10U6D3V5KX-1GP

12

C807

SC10U6D3V3MX-GP

0726 Modify: un-stuff C826.

12

C825

SC10U6D3V5KX-1GP

12

C832

SC10U6D3V5KX-1GP

C804

QC

SC10U6D3V3MX-GP

C817

SC10U6D3V3MX-GP

C834

SC10U6D3V5KX-1GP

12

C826

12

SC22U6D3V5MX-L2GP

C831

SC22U6D3V5MX-2GP

4

12

C827

SC22U6D3V5MX-2GP

0819 De-cap

4

VCC_CORE

CPU1F

AG35

VCC

AG34

VCC

AG33

VCC

AG32

VCC

AG31

VCC

AG30

VCC

AG29

VCC

AG28

VCC

AG27

VCC

AG26

VCC

AF35

VCC

AF34

VCC

AF33

VCC

AF32

VCC

AF31

VCC

AF30

VCC

AF29

VCC

AF28

VCC

AF27

VCC

AF26

VCC

AD35

VCC

AD34

VCC

AD33

VCC

AD32

VCC

AD31

VCC

AD30

VCC

AD29

VCC

AD28

VCC

AD27

VCC

AD26

VCC

AC35

VCC

AC34

VCC

AC33

VCC

AC32

VCC

AC31

VCC

AC30

VCC

AC29

VCC

AC28

VCC

AC27

VCC

AC26

VCC

AA35

VCC

AA34

VCC

AA33

VCC

AA32

VCC

AA31

VCC

AA30

VCC

AA29

VCC

AA28

VCC

AA27

VCC

AA26

VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

SANDY

62.10055.421

2nd = 62.10040.771

POWER

SANDY

CORE SUPPLY

3rd = 62.10055.321

3

6 OF 9

AH13

VCCIO

AH10

VCCIO

AG10

VCCIO

AC10

VCCIO

Y10

VCCIO

U10

VCCIO

P10

VCCIO

L10

VCCIO

J14

VCCIO

J13

VCCIO

J12

VCCIO

J11

VCCIO

H14

VCCIO

H12

VCCIO

H11

VCCIO

G14

VCCIO

G13

VCCIO

G12

VCCIO

F14

VCCIO

F13

VCCIO

F12

VCCIO

F11

VCCIO

E14

VCCIO

E12

VCCIO

E11

VCCIO

D14

VCCIO

D13

VCCIO

D12

VCCIO

D11

VCCIO

C14

VCCIO

PEG AND DDR

VCC_SENSE

VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

SENSE LINES SVID

3

C13

VCCIO

C12

VCCIO

C11

VCCIO

B14

VCCIO

B12

VCCIO

A14

VCCIO

A13

VCCIO

A12

VCCIO

A11

VCCIO

J23

VCCIO

AJ29

VIDALERT#

AJ30

VIDSCLK

AJ28

VIDSOUT

AJ35 AJ34

B10 A10

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

2

VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

PROCESSOR VCCIO: 8.5A

12

C805

QC

SC10U6D3V3MX-GP

0713 Modify: Removed C810,C806,C807 10uf 0603 cap base on layout limitation.

No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.

0617 Modify: Joseph Removed C812, C813,C814

For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU

12

DY

12

C809

C808

SC10U6D3V5KX-1GP

SC10U6D3V3MX-GP

12

C830

C842

SC10U6D3V5KX-1GP

H_CPU_SVIDDAT

C842

SC10U6D3V5KX-1GP

C829

SC10U6D3V5KX-1GP

20100610 V1.0

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R803 43R2J-GPR803 43R2J-GP

1 2

VCCIO_SENSE 45 VSSIO_SENSE 45

VCC_CORE

12

2

VR_SVID_ALERT# 42

H_CPU_SVIDCLK 42

H_CPU_SVIDDAT 42

R801

R801 100R2F-L1-GP-U

100R2F-L1-GP-U

R802

R802 100R2F-L1-GP-U

100R2F-L1-GP-U

12

C839

C838

SC10U6D3V5KX-1GP

1D05V_VTT

12

C844

C843

SC10U6D3V5KX-1GP

R804 130R2F-1-GPR804 130R2F- 1-GP

1 2

0705 Modify: Removed R805,R806, already PH closed PWM side.

VCCSENSE 42 VSSSENSE 42

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Tuesday, January 04, 2011

Date: Sheet

1

1D05V_VTT

12

C841

C840

SC10U6D3V5KX-1GP

C845

SC10U6D3V5KX-1GP

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_CORE)

QUEEN 15

1

of

8 108

A00

5

VAXG Output Decoupling Recommendation:

SSID = CPU

VCC_GFXCORE

D D

0713 Modify: Removed C907 10uf 0603 cap. 0726 Modify: stuff C908 10uF.

C C

2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

0721 Modify: Removed C903

12

C901

C902

SC10U6D3V5KX-1GP

0624 Modify: Removed C918,C919 10uF 0603 for VCC_GFXCORE.

12

C908

SC4D7U6D3V3KX-GP

0818 De-cap

Removed DIS_ONLY Disable Resistor. R904,R905,R901,R903

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating)

B B

if the VR is stuffed

1D8V_S0

0617 Modify: Joseph Removed TC 902, TC903 330uF cap.

PROCESSOR VCCPLL: 1.2A

12

C923

SC10U6D3V5KX-1GP

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

4

0726 Modify: un-stuff C906.

PROCESSOR VAXG: 33A

12

C904

SC10U6D3V5KX-1GP

DY

12

C922

SC1U10V2KX-1GP

C905

DY

SC10U6D3V5KX-1GP

12

C920

DY

SC10U6D3V3MX-GP

12

C924

SC1U10V2KX-1GP

12

C906

12

C921

AT24 AT23 AT21 AT20 AT18

AT17 AR24 AR23 AR21 AR20

SC10U6D3V5KX-1GP

AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24

SC10U6D3V3MX-GP

AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

B6 A6 A2

CPU1G

VAXG VAXG

SANDY

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

VCCPLL VCCPLL VCCPLL

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

3

POWER

SENSE

7 OF 9

VAXG_SENSE

VSSAXG_SENSE

LINES

AK35 AK34

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.

+V_SM_VREF_CNT should have 10 mil trace width

AL1

SM_VREF

VREFMISC

AF7

VDDQ

AF4

VDDQ

AF1

VDDQ

AC7

VDDQ

AC4

VDDQ

AC1

VDDQ

Y7

VDDQ

Y4

VDDQ

Y1

VDDQ

U7

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

1.8V RAIL

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCSA_SENSE

FC_C22

VCCSA_VID1

U4 U1 P7 P4 P1

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

+V_SM_VREF_CNT

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

12

C909

DY

PROCESSOR VCCSA: 6A

12

VCCUSA_SENSE

H_FC_C22 VCCSA_SEL

4

1

2 3

2

VCC_AXG_SENSE 42 VSS_AXG_SENSE 42

+V_SM_VREF_CNT 37

PROCESSOR VDDQ: 10A

12

C910

DY

SC10U6D3V3MX-GP

0D85V_S0

12

C915

C916

SC10U6D3V5KX-1GP

0624 Modify: Removed R902 10ohm closed CPU side. 0713 Modify: Add R908 100ohm PH to 0D85V_S0. 0714 Modify: Removed R908 PH.

H_FC_C22 48 VCCSA_SEL 48

RN901

RN901 SRN1KJ-7-GP

SRN1KJ-7-GP

0714 Modify: RN901 change to 1K PL from 10K base on Intel PDDG updated.

12

C911

SC10U6D3V3MX-GP

12

C917

VCCSA Output Decoupling Recommendation:

SC10U6D3V5KX-1GP

1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

VCCUSA_SENSE 48

VCC_GFXCORE

12

R906

R906 100R2F-L1-GP-U

100R2F-L1-GP-U

VCC_AXG_SENSE VSS_AXG_SENSE

12

R907

R907 100R2F-L1-GP-U

100R2F-L1-GP-U

20100609 V1.0

0719 Modify: Add C907,C918,C919,C925 0402 0.1 uF stitching capacitors between 1D5V_S3 & 1D5V_S0 based on Intel's review

1D5V_S0

12

TC901

C913

C912

SC10U6D3V5KX-1GP

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

12

DY

EC902

SCD1U50V3KX-GP

TC901

C914

SC10U6D3V5KX-1GP

79.33719.20L

2nd = 77.C3371.13L

0617 Modify: Joseph Removed TC902,TC903 330uF cap. 0719 Modify: Reserved EC902 0.1uF near C917 for EMC NEO suggestion.

DCBATOUT

12

1122 X02 Modify: stuff EC901 0.1uF from EMC Neo suggestion.

12

DY

C907

ST330U2VDM-4-GP

EC901

SCD1U50V3KX-GP

EC901

SCD1U50V3KX-GP

12

DY

C918

SCD1U10V2KX-5GP

1

12

DY

C919

C925

SCD1U10V2KX-5GP

1D5V_S3

SCD1U10V2KX-5GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

CPU (VCC_GFXCORE)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

9 108

1

A00

5

4

3

2

1

SSID = CPU

9 OF 9

8 OF 9

CPU1H

AT35

VSS

AT32

VSS

AT29

VSS

AT27

VSS

AT25

VSS

AT22

VSS

D D

C C

B B

AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26

K35 K32 K29 K26

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29

CPU1I

T35

VSS

T34

VSS

T33

VSS

T32

VSS

T31

VSS

T30

VSS

T29

VSS

T28

VSS

T27

VSS

T26

VSS

P9

VSS

P8

VSS

P6

VSS

P5

VSS

P3

VSS

P2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L33

VSS

L30

VSS

L27

VSS

L9

VSS

L8

VSS

L6

VSS

L5

VSS

L4

VSS

L3

VSS

L2

VSS

L1

VSS VSS VSS VSS VSS

J34

VSS

J31

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H9

VSS

H8

VSS

H7

VSS

H6

VSS

H5

VSS

H4

VSS

H3

VSS

H2

VSS

H1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

9 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 63.10055.321

A A

5

A00 0103 add 3rd foxcon CPU1 at XBuild batch run A00 0103 add 3rd foxcon CPU1 at XBuild batch run

4

3

SANDY

62.10055.421

2nd = 62.10040.771

3rd = 62.10055.321

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

CPU (VSS)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

10 108

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

XDP

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

11 108

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

12 108Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

13 108Tuesday, January 04, 2011

A00

5

SSID = MEMORY

0617 Modify:

DDR_VREF_S3

A00

D D

DDR_VREF_S3

A00

C C

0707 Modify: Change R1404,R1405 to 0ohm 0402 from short pad.

0D75V_S0

B B

A A

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

12

R1405

R1405 0R0402-PAD-2-GP

0R0402-PAD-2-GP

M_VREF_CA_DIMM1

12

C1423

DY

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1,

SCD1U10V2KX-5GP

M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

12

R1404

R1404 0R0402-PAD-2-GP

0R0402-PAD-2-GP

12

C1411

DY

SCD1U10V2KX-5GP

12

C1419

SC1U6D3V2KX-GP

12

C1425

SC2D2U10V3KX-1GP

M_VREF_DQ_DIMM1

12

C1412

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1420

DY

SC1U6D3V2KX-GP

5

C1424

SCD1U10V2KX-5GP

C1413

SCD1U10V2KX-5GP

C1421

SC1U6D3V2KX-GP

12

C1422

DY

M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1

DDR3_DRAMRST#15,37

M_B_DQ[63:0]6

SC1U6D3V2KX-GP

M_B_DIM0_ODT06 M_B_DIM0_ODT16

DY

M_B_BS26 M_B_BS06

M_B_BS16

12

M_B_A[15:0] 6

C1418

SC10U6D3V5KX-1GP

M_B_DQS#[7:0] 6 M_B_DQS[7:0] 6

0D75V_S0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

4

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78 79

109 108

15 17

16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68

70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10

27

45

62 135 152 169 186

12

29

47

64 137 154 171 188

116 120

126

30

203 204

H =5.2mm

4

0624 Modify: SWAP DM1 and DM2 location.

DM2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

5

DQ0

7

DQ1 DQ2 DQ3

4

DQ4

6

DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA

1

VREF_DQ RESET#

VTT1 VTT2

DDR3-204P-48-GP

62.10017.P61

2nd = 62.10017.N41

3rd = 62.10017.P41

4th = 62.10024.E21

NP1 NP2

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

SA0_DIM1 SA1_DIM1

3

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6

M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6

M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6

M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6

PCH_SMBDATA 15,20,79,82 PCH_SMBCLK 15,20,79,82

TS#_DIMM0_1 15

1D5V_S3

PART NUMBER

62.10017.P61

62.10017.N41(2nd)

62.10017.P41(3rd) 5.2mm REVERSED

62.10024.E21(4th) 5.2mm REVERSED

1110 X02 Modify: DM2 1st change to 62.10017.P61; 2nd change to 62.10017.N41 on ST stage from ME updated connector list.

3

12

C1402

C1401

DY

SCD1U10V2KX-5GP

1D5V_S3

SC2D2U10V3KX-1GP

Layout Note: Place these Caps near SO-DIMMA.

Height TYPE

5.2mm

5.2mm REVERSED

2

0825

SA1_DIM1 SA0_DIM1

3D3V_S0

SODIMM A DECOUPLING

0617 Modify: Joseph du mmy TC1401 defa ult un-stuff.

12

DY

12

0818 De-cap

C1403

SC10U6D3V5KX-1GP

C1415

SC1U6D3V2KX-GP

12

0818 De-cap

12

DY

ST330U2VDM-4-GP

12

TC1401

12

C1414

SCD1U10V2KX-5GP

REVERSED

2

3D3V_S0

DY

C1404

SC22U6D3V5MX-2GP

C1416

SC1U6D3V2KX-GP

12

R1402

R1402 10KR2J-3-GP

10KR2J-3-GP

12

R1401

R1401 10KR2J-3-GP

10KR2J-3-GP

12

C1405

12

1

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

Thermal EVENT

TS#_DIMM0_1

12

C1406

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

C1417

SC1U6D3V2KX-GP

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

R1403

1 2

12

C1407

C1408

DY

SC10U6D3V5KX-1GP

Tuesday, Janua r y 04, 2011

3D3V_S0

10KR2J-3-GP

12

DY

SC10U10V5ZY-1GP

DDR3-SODIMM2

QUEEN 15

C1410

C1409

DY

SC10U6D3V5KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chi h,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chi h, Taipei Hsien 221, Taiwa n, R. O . C.

Taipei Hsien 221, Taiwa n, R. O . C.

1

14 108

A00

of

5

SSID = MEMORY

M_A_A[15:0] 6

D D

M_A_DQ[63:0]6

12

C1521

SC1U6D3V2KX-GP

M_A_DIM0_ODT06 M_A_DIM0_ODT16

M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0

DDR3_DRAMRST#14,37

M_A_BS26 M_A_BS06

M_A_BS16

M_A_DQS#[7:0] 6 M_A_DQS[7:0] 6

0D75V_S0

0707 Modify: Change R1503,R1504 to 0ohm 0402 from short pad.

DDR_VREF_S3

12

A00

12

C C

DDR_VREF_S3

12

A00

12

B B

A A

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1

R1504

from net to power.

0R0402-PAD-2-GP

M_VREF_CA_DIMM0

12

C1524

C1522

C1523

DY

SCD1U10V2KX-5GP

R1503

0R0402-PAD-2-GP

12

C1515

DY

SCD1U10V2KX-5GP

0D75V_S0

12

DY

C1522

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

0617 Modify: Joseph Cha nge M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 from net to power.

M_VREF_DQ_DIMM0

12

C1517

C1516

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1518

SC1U6D3V2KX-GP

12

C1519

C1520

DY

SC1U6D3V2KX-GP

5

4

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

H =9.2mm

4

0624 Modify: SWAP DM1 and DM2 location.

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-42-GP

NP1 NP2

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

62.10017.Q41

2nd = 62.10017.N11

3rd = 62.10017.N61

4th = 62.10024.D91

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

SA0_DIM0 SA1_DIM0

1D5V_S3

3

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6

M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6

M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6

M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6

PCH_SMBDATA 14,20,79,82 PCH_SMBCLK 14,20,79,82

TS#_DIMM0_1 14

12

DY

C1501

C1502

SCD1U10V2KX-5GP

1D5V_S3

Layout Note: Place these Caps near SO-DIMMB.

PART NUMBER

SODIMM B DECOUPLING

12

DY

12

0818 De-cap

Height TYPE

62.10017.Q41 9.2mm REVERSED

62.10017.N11(2nd)

62.10017.N61(3rd)

9.2mm REVERSED

62.10024.D91(4th) 9.2mm REVERSED

1110 X02 Modify: DM1 1st change to 62.10017.Q41; 2nd change to 62.10017.N11 on ST stage from ME updated connector list.

3

SC2D2U10V3KX-1GP

C1503

SC10U10V5ZY-1GP

C1511

DY

SC1U6D3V2KX-GP

12

DY

3D3V_S0

C1504

SC10U10V5ZY-1GP

C1512

SCD1U10V2KX-5GP

SA1_DIM0 SA0_DIM0

12

2

C1505

C1513

2

1

20101220 R1501 R1502 for change to parallel resistor

4

RN1501

RN1501 SRN10KJ-5-GP

SRN10KJ-5-GP

A00

1

2 3

12

C1506

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C1514

SCD01U50V2KX-1GP

12

DY

0818 De-cap

SCD01U50V2KX-1GP

C1507

12

C1508

DY

SC10U6D3V5KX-1GP

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from the Processor than SO-DIMMA

12

C1509

C1510

DY

SC10U10V5ZY-1GP

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

C1510

DY

SC10U6D3V5KX-1GP

DDR3-SODIMM1

QUEEN 15

Tuesday, Janua r y 04, 2011

QUEEN 15

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chi h,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsi chi h, Taipei Hsien 221, Taiwa n, R. O . C.

Taipei Hsien 221, Taiwa n, R. O . C.

of

15 108

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

16 108Tuesday, January 04, 2011

A00

5

D D

3D3V_S0

RN1701

1 2 3

SRN2K2J-1-GP

RN1702

2 3 1

SRN100KJ-6-GP

0923 SWAP

4

L_CTRL_DATA L_CTRL_CLK

L_BKLT_EN LVDS_VDD_EN

L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

Place near PCH

C C

Impedance:90 ohm

Close to PCH side

CRT_RED CRT_BLUE CRT_GREEN

B B

678

4 5

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

123

0923 SWAP

CRT_BLUE82 CRT_GREEN82 CRT_RED82

4

L_BKLT_EN27

LVDS_VDD_EN49

L_BKLT_CTRL49

LVDS_DDC_CLK_R49 LVDS_DDC_DATA_R49

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

LVDSA_CLK#49 LVDSA_CLK49

LVDSA_DATA0#49 LVDSA_DATA1#49 LVDSA_DATA2#49

LVDSA_DATA049 LVDSA_DATA149 LVDSA_DATA249

0617 Modify: Joseph Removed LVDSB related net for single LVDS channel b ase on Dell updated s pec.

0917 X01 Modify: Add R1703~R1705 on RGB signal and reserved EC1701~EC1703 0.1u from EMC Neo suggestion.

CRT_DDC_CLK82 CRT_DDC_DATA82

CRT_HSYNC82 CRT_VSYNC82

TP1701TPAD14-GP TP1701TPAD14-GP

4

RN1704

A00

0R4P2R-PAD

A00

1 2

R1703 0R0402-PAD-2-GPR1703 0R0402-PAD-2-GP

1 2

R1704 0R0402-PAD-2-GPR1704 0R0402-PAD-2-GP

1 2

R1705 0R0402-PAD-2-GPR1705 0R0402-PAD-2-GP

1KR2D-1-GP

RN

R1702

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

LVDS_VREFH

1

LVDS_VREFL

23

0712 Modify: SWAP RN1704

CRT_BLUE_N48 CRT_GREEN_P49 CRT_RED_T49

DAC_IREF_R

12

3

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

LVDS

CRT

2

4 OF 10

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

0804 Remove HDMI from PCH.

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN

SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

1

Notes: 1K 0.5% 0402.

CHIP RES 1K D 1/16W 0402

DY

EC1701

SCD1U50V3KX-GP

EC1701

SCD1U50V3KX-GP

12

DY

EC1702

SCD1U50V3KX-GP

EC1702

SCD1U50V3KX-GP

12

DY

CRT_BLUE CRT_GREEN

CRT_RED

EC1703

SCD1U50V3KX-GP

EC1703

SCD1U50V3KX-GP

12

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

PCH (LVDS/CRT/DDI)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

17 108

1

A00

5

SSID = PCH

0709 Modify: Removed INT_PIRQH# on RN1801 pin1.

D D

3D3V_S0

INT_PIRQB# INT_PIRQF#

R1801 4K7R2J-2-GP

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC 0 1 Reserved

B B

0617 Modify: Joseph Remove PLT_RST AND gate logic IC U1801/C1802.

A A

0629 Modify: Reseved R1816 100K 0402 on PLT_RST#.

PLT_RST#5,27,71,75,82,83

20100625 V1.2

RN1801

1 2 3 4 5 6

SRN8K2J-2-GP-U

12

DY

override/Top-Block Swap Override enabled High = Default

R1802

1 2

DY

1KR2J-1-GP

R1803

1 2

DY

1KR2J-1-GP

BOOT BIOS Strap

11

1 2

12

R1816

DY

100KR2J-1-GP

5

10

INT_PIRQD#

9

INT_PIRQE#

8

INT_PIRQC#INT_PIRQA#

7

INT_PIRQG#

PCI_GNT3#

BBS_BIT1 BBS_BIT0

Reserved 01

SPI(Default)

R1807

0R0402-PAD-2-GP

12

C1801

C1801 SC220P50V2KX-3GP

SC220P50V2KX-3GP

A00

3D3V_S0

BBS_BIT0 21

0709 Modify: Add R1817 0ohm and connect to KB_LED_BL_DET. (5V Tolerance High Active)

CLK_PCI_LPC71 CLK_PCI_KBC27

PCI_PLTRST#

0908 X01 Modify: Add R1818 10K PL on FFS_INT2_R(GPIO14)

DGPU_HOLD_RST#83

DGPU_PWR_EN#93

4

DGPU_HOLD_RST# DGPU_PWR_EN#

TP1806TPAD14-GP TP1806TPAD14-GP

HDD_FALL_INT179

SATA_ODD_DA#56

USB30_SMI#82

KB_LED_BL_DET69

EC1802

1 2

DY

SC4D7P50V2CN-1GP

R1818 10KR2J-3-GPR1818 10KR2J-3-GP

1 2

4

RN1803

1 2 3

SRN10KJ-5-GP

3D3V_S0

R1814

R1814 8K2R2J-3-GP

8K2R2J-3-GP

1 2

1

TP1807TPAD14-GP TP1807TPAD14-GP

DGPU_PWM_SELECT#

1

R1804 22R2J-2-GPR1804 22R2J-2-GP R1805 22R2J-2-GPR1805 22R2J-2-GP R1806 22R2J-2-GPR1806 22R2J-2-GP

12

EC1801

DGPU_PWR_EN#

1 2 1 2 1 2

EC1803

1 2

DY

SC10P50V2JN-4GP

SC4D7P50V2CN-1GP

TP1801TPAD14-GP TP1801TPAD14-GP

R1812 0R0402-PADR1812 0R0402-PAD

1 2

R1813 0R0402-PADR1813 0R0402-PAD

1 2

R1815 0R0402-PADR1815 0R0402-PAD

1 2

R1817 0R0402-PADR1817 0R0402-PAD

1 2

TP1802TPAD14-GP TP1802TPAD14-GP

KBC CLK EMI

FFS_INT2_R

3

PCH1E

Cougar

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

H3

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

3D3V_S5

BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

G38

G42 G40

K40 K38 H38

C46 C44 E40

D47 E42 F46

C42 D44

K10

H49 H43

K42 H40

C6

J48

4

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

DGPU_SELECT#

BBS_BIT1 PCI_GNT3#

1

PCI_PME#

1

PCI_PLTRST#

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

0628 Modify: Add EC1803 4.7pF 0402 on CLK_PCI_LPC base on EMC NEO suggestion. 0707 Modify: Change R1815,R1812,R1813 to 0ohm 0402 from short pad. 0719 Modify: Reserved TP on CLKOUT_PCI3,4 from vender feedback.

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME# PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGAR-GP-U2-NF

USB_OC#2_3

3

RSVD

PCI

NVRAM

USBP10N

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

RN1802

SRN8K2J-2-GP-U

USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USB

1 2 3 4 5 6

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD RSVD RSVD

RSVD RSVD

RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

10

USB_OC#12_13

9

USB_OC#8_9USB_OC#6_7

8

USB_OC#10_11USB_OC#0_1

7

USB_OC#4_5

0719 Modify: DF_TVS (NV_CLE) connect PROC_SELECT# (H_SNB_IVB#) with R1808 2.2K¡Ó5% pull up resistor to PCH VCCPNAND rail and a R1809 1K¡Ó5% series resistor base on Intel feedback.

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1

NV_RCOMP

AV10 AT8 AY5

BA2 AT12

USB Ext. port 1 (HS)

BF3

External debug port use on Huron river platform

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC#0_1

A14

USB_OC#2_3

K20

USB_OC#4_5

B17

USB_OC#6_7

C16

USB_OC#8_9

L16

USB_OC#10_11

A16

USB_OC#12_13

D14 C14

2

TP1803 TPAD14-GPTP1803 TPAD14-GP

1

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

FFS_INT2_R 79

USB_PN0 49 USB_PP0 49 USB_PN1 82 USB_PP1 82 USB_PN2 64 USB_PP2 64 USB_PN3 63 USB_PP3 63 USB_PN4 82 USB_PP4 82 USB_PN5 32 USB_PP5 32

USB_PN8 57 USB_PP8 57

USB_PN11 82 USB_PP11 82 USB_PN12 49 USB_PP12 49 USB_PN13 75 USB_PP13 75

USB_OC#0_1 61

USB_OC#8_9 61CLK_PCI_FB20

NV_CLE

1 2

DMI & FDI Termination Voltage

NV_CLE

Danbury Technology: Disabled when Low. Enable when High.

USB Table

Pair

Touch Panel / 3G SIM

0

USB Ext. port 1 (HS)

1

Fingerprint

2

BLUETOOTH

3

Mini Card2 (WWAN)

4

CARD READER

5

X

6

X

7

USB Ext. port 4 / E-SATA /USB CHARGE

8

USB Ext. port 2

9

USB Ext. port 3

10

Mini Card1 (WLAN)

11

CAMERA

12

Express Card

13

1120 X02 Modify: Reserved USB_OC#0_1 connect from PCH GPIO59.

0908

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

Wistron Corporation

3D3V_S5

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

PCH (PCI/USB/NVRAM)

QUEEN 15

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

1D8V_S0

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

R1809

1KR2J-1-GP

H_SNB_IVB# 5

Set to Vss when LOW

Set to Vcc when HIGH

1D8V_S0

DY

NV_ALE

Device

of

18 108

1

12

R1810

R1810 1KR2J-1-GP

1KR2J-1-GP

A00

5

4

3

2

1

SSID = PCH

Signal Routing Guideline:

D D

DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP R1902 750R2F-GPR1902 750R2F-GP

20100628 V1.3

SYS_PWROK

R1926

XDP_DBRESET#5

S0_PWR_GOOD27,36

PM_PWRBTN#27

DY

R1926

PWROK

R1904

0707 Modify: stuff R1925 and un-stuff R1905.

3D3V_S0

SYS_PWROK36

R1924 0R0402-PADR1924 0R0402-PAD

RUNPWROK45,46,47,93

3D3V_S5

5

1 2

0907 X01 SWAP RN1901

RN1901

8 7 6

SRN10KJ-6-GP

1 2

R1909 100KR2J-1-GPR1909 100KR2J-1-GP

R1922 10KR2J-3-GP

R1922 10KR2J-3-GP R1920 10KR2J-3-GP

R1920 10KR2J-3-GP

DY

DY DY

DY

R1908

10KR2J-3-GP

1 2

10KR2J-3-GP

C C

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

B B

A A

1 2

100KR2J-1-GP

PM_DRAM_PWRGD5,37

SUS_PWR_ACK27

AC_PRESENT27,86

DMI_RXN[3:0]4

DMI_RXP[3:0]4

DMI_TXN[3:0]4

DMI_TXP[3:0]4

DMI_RXN04 DMI_RXN14 DMI_RXN24 DMI_RXN34

DMI_RXP04 DMI_RXP14 DMI_RXP24 DMI_RXP34

DMI_TXN04 DMI_TXN14 DMI_TXN24 DMI_TXN34

DMI_TXP04 DMI_TXP14 DMI_TXP24 DMI_TXP34

1 2

1 2 1 2

DY

10KR2J-3-GP

PWROK

R1907

1 2

0R2J-2-GP

DY

BATLOW# PM_RI# PCH_WAKE#

SUS_PWR_ACK

DMI_COMP_R RBIAS_CPY

R1905

R1923

1 2

0R2J-2-GP

DY

R1906 0R0402-PADR1906 0R0402-PAD

1 2

MEPWROK

PM_RSMRST#

BATLOW#

PM_RI#

1 2 1 2

0628 Modify: Change R1904 to 100K 0402 from 10K and default stuff. 0629 Modify: R1926 connect to SYS_PWROK. 0707 Modify: Change R1903 change to 0ohm 0402 from short pad.

R1903 0R0402-PADR1903 0R0402-PAD

R1925 0R0402-PADR1925 0R0402-PAD

1 2 3 45

BC24

BE20 BG18 BG20

BE24 BC20

BJ18

BJ20

AW24 AW20

BB18

AV18

AY24

AY20

AY18 AU18

BJ24 BG25 BH21

SUSACK#SUS_PWR_ACK

SYS_RESET#

PCIE_WAKE# CRB : 1K

C12

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

CEKLT: 10K

AC_PRESENT

12 12

12

PM_PWRBTN# PM_SLP_LAN#

PM_RSMRST#

0920 X01 Modify: move PCH_WAKE# to RN1901 pin4 Add R1909 PH on AC_PRESENT.

0719 Modify: Change R1908 to 10K ohm based on Intel review:

8.2K to 10K pull-down is recommended.

4

PCH1C

DMI0RXN

Cougar

DMI1RXN

Point

DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP DMI_IRCOMP DMI2RBIAS

SUSACK#

K3

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPIO72

RI#

COUGAR-GP-U2-NF

3 OF 10

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

DMI

System Power Management

FDI_RXP6

FDI

FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_LAN#/GPIO29

0621 Modify: Joseph removed Q1901/R1909/R1916 3V_5V_POK and PM_R SMRST # related control circuit.

FDI_RXP7

FDI_INT

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DSWODVREN

PCH_DPWROK

PM_SUS_STAT#

SUS_CLK

PM_SLP_S5#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

3

FDI_TXN[7:0] 4 FDI_TXP[7:0] 4

FDI_TXN0 4 FDI_TXN1 4 FDI_TXN2 4 FDI_TXN3 4 FDI_TXN4 4 FDI_TXN5 4 FDI_TXN6 4 FDI_TXN7 4

FDI_TXP0 4 FDI_TXP1 4 FDI_TXP2 4 FDI_TXP3 4 FDI_TXP4 4 FDI_TXP5 4 FDI_TXP6 4 FDI_TXP7 4

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

DY

1

PM_RSMRST#

R1910 0R0402-PADR1910 0R0402-PAD

1 2

R1911 10KR2J-3-GP

1 2

PCH_WAKE# 27

PM_CLKRUN# 27

TP1901 TPAD14-GPTP1901 TPAD14-GP

R1913 0R0402-PADR1913 0R0402-PAD

1 2

TP1902 TPAD14-GPTP1902 TPAD14-GP

TP1903TPAD14-GPTP1903TPAD14-GP

TP1904TPAD14-GPTP1904TPAD14-GP

H_PM_SYNC 5

TP1905TPAD14-GPTP1905TPAD14-GP

R1912

1 2

0R0402-PAD

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# a re left as ¡¥no connect¡¦

4.SUSWARN# used as SUSPWRDNACK/GPIO30

PM_RSMRST#

RSMRST#_KBC 27

PCH_SUSCLK_KBC

EC1901

1 2

DY

SC4D7P50V2CN-1GP

RTC_AUX_S5

PCH_SUSCLK_KBC 27

PM_SLP_S4# 27,46,75

PM_SLP_S3# 27,36,37,47,75

0625 Modify: Reserved EC1901 on PCH_SUSCLK_KBC for EMC NEO suggestion.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

2

Date: Sheet

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

Tuesday, January 04, 2011

R1918 330KR2J-L1-GP

1 2

DY

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (DM I/FDI/PM)

QUEEN 15

19 108

1

RTC_AUX_S5

3D3V_S0

of

A00

5

SSID = PCH

1112 X02 Modify: Dell required us to disable PCIE port of WWAN slot ,If PCIE port 1 is disabled, it will cause all PCIE port disabled,so change WWAN to PCIE port 3 from port1

D D

C C

::$1&/.

20100614 V1.1

:/$1&/.

0623 Modify: SWAP WLAN CLK and LAN CLK routing each other. 0716 Modify: Rename PCIE_CLK_LAN_RQ1# to PCIE_CLK_LAN_REQ#.

20100614 V1.1

/$1&/.

B B

86%&/.

PCIECLKRQ1# and PCIECLKRQ2# Support S0 power only

1(:&$5'&/.

A A

1 2

DY

SC4D7P50V2CN-1GP

at ST stage.

PCIE_RXN282

PCIE_RXP282 PCIE_TXN282 PCIE_TXP282

PCIE_RXN382

PCIE_RXP382 PCIE_TXN382 PCIE_TXP382

PCIE_RXN482

PCIE_RXP482 PCIE_TXN482 PCIE_TXP482

PCIE_RXN582

PCIE_RXP582 PCIE_TXN582 PCIE_TXP582

PCIE_RXN875

PCIE_RXP875 PCIE_TXN875 PCIE_TXP875

CLK_PCIE_WWAN#82 CLK_PCIE_WWAN82

CLK_PCIE_LAN#82 CLK_PCIE_LAN82

0623 Modify: Change PCIE_CLK_RQ2#&CLK_PCIE_WLAN_REQ# pull high power to 3D3V_S0 from 3D3V_S5.(add RN2018)

RN2018

1 2 3

SRN10KJ-5-GP

CLK_PCIE_NEW#75 CLK_PCIE_NEW75

CLK_PCIE_NEW# CLK_PCIE_NEW

EC2004

EC2005

1 2

DY

SC4D7P50V2CN-1GP

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

X02 1115

C2011 SCD1U10V2KX-5GPC2011 SCD1U10V2KX-5GP

1 2

C2012 SCD1U10V2KX-5GPC2012 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

C2009 SCD1U10V2KX-5GPC2009 SCD1U10V2KX-5GP

1 2

C2010 SCD1U10V2KX-5GPC2010 SCD1U10V2KX-5GP

1 2

C2004 SCD1U10V2KX-5GPC2004 SCD1U10V2KX-5GP

1 2

C2003 SCD1U10V2KX-5GPC2003 SCD1U10V2KX-5GP

1 2

CLK_PCIE_WWAN_REQ#82

CLK_PCIE_WLAN#82 CLK_PCIE_WLAN82

CLK_PCIE_WLAN_REQ#82

PCIE_CLK_LAN_REQ#82

CLK_PCIE_USB3#82

CLK_PCIE_USB382

USB3_PEGB_CLKREQ#82

20100614 V1.1

PCIE_CLK_RQ2#

4

CLK_PCIE_WLAN_REQ#

CLK_PCIE_NEW_REQ#75

0913 X01 Modify: Reserved EC2004,EC2005 on CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.

5

CLK_PCH_48M

EC2003

1 2

DY

SC4D7P50V2CN-1GP

A00

RN2011

4

0R4P2R-PAD

4

0R4P2R-PAD

RN2014

4

0R4P2R-PAD

RN2013

4

0R4P2R-PAD

A00

RN2015

4

0R4P2R-PAD

TP2005TPAD14-GP TP2005TPAD14-GP TP2006TPAD14-GP TP2006TPAD14-GP

0630 Modify: Removed XDP CLOCK and reserved TP2005,TP2006.

RN

A00

RN2012

A00

RN

A00

RN

23 1

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN5_C PCIE_TXP5_C

PCIE_TXN8_C PCIE_TXP8_C

CLK_PCH_SRC0_N CLK_PCH_SRC0_P

0630 SWAP RN2012

CLK_PCH_SRC1_N

1 23

PCIE_CLK_RQ2#

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

CLK_PCH_SRC4_N CLK_PCH_SRC4_P

PCIE_CLK_REQ5#

PEG_B_CLKRQ#

PCIE_CLK_REQ6# CLK_PCH_SRC7_N

CLK_PCH_SRC7_P CLK_PCIE_NEW_REQ#

ITPXDP_N

1

ITPXDP_P

1

¡V Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 ¡V Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed.

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

COUGAR-GP-U2-NF

4

Cougar

Cougar Point

Point

Card Reader

LAN

W-WAN

WLAN

USB3.0

PCI-E*

Intel GBE LAN

Dock

NEW CARD

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

Link

PEG_A_CLKRQ#/GPIO47

CLOCKS

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

FLEX CLOCKS

2 OF 10

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

3

E12 H14 C9

A12 C8 G12

C13 E14 M16

M7

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43 F47 H47 K49

3

PEG_CLKREQ#_R

XCLK_RCOMP

DGPU_PRSNT#

EC_SWI# SMB_CLK SMB_DATA

DRAMRST_CNTRL_PCH SML0_CLK SML0_DATA

PCH_GPIO74 SML1_CLK SML1_DATA

CL_CLK

1

CL_DATA

1

CL_RST#

1

For DIS_PX mode or MXM mode.

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_PCLK_PCH_SRC1_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

1 2

R2007

R2007 90D9R2F-1-GP

90D9R2F-1-GP

JTAG_TCK

1 2

DY

R2001

CLK_48_USB30 CLK_27M_VGA_R

R2001

EC_SWI# 27 SMB_CLK 75 SMB_DATA 75

DRAMRST_CNTRL_PCH 37

SML1_CLK 27,86 SML1_DATA 27,86

TP2001 TPAD14-GPTP2001 TPAD14-GP

TP2002 TPAD14-GPTP2002 TPAD14-GP

TP2003 TPAD14-GPTP2003 TPAD14-GP

DY

R2003

1 2

0R2J-2-GP

RN

1

4

RN2016

23

0R4P2R-PAD

RN

1

4

RN2010

23

0R4P2R-PAD

0630 SWAP RN2010,RN2016

RN2008

2 3

1

SRN10KJ-5-GP

PL 10K FOR Integrated CLOCK GEN mode.

CLK_PCI_FB 18

+VCCDIFFCLKN

22R2J-2-GP

R2016 22R2J-2-GPR2016 22R2J-2-GP

1 2

R2002

1 2

DY

0908

0R2J-2-GP

0630 Modify: Removed LAN_XI for LAN 25MHZ and reserved TP2004. 0707 Modify: Removed R2002 for USB3.0 48MHZ. 0709 Modify: Add R2002 22ohm for CLK_27M_VGA. 0717 Modify: default stuff R2002 22ohm for CLK_27M_VGA.

PEG_CLKREQ# 83

A00

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

A00

CLK_EXP_N 5 CLK_EXP_P 5

0712 Modify: SWAP RN2008

4

0712 Modify: SWAP RN2020

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

0712 Modify: SWAP RN2019

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_REF14

JTAG_TCK_VGA 86

CLK_PCH_48M 32

2

3D3V_S5

DY

PEG_CLKREQ#_R

SMB_DATA

SMB_CLK

X02 1118

SRN10KJ-5-GP

SRN10KJ-5-GP RN2020

RN2020

2 3 1

4

RN2021 SRN10KJ-5-GPRN2021 SRN10KJ-5-GP

1

4

2 3

RN2019

2 3 1

4

SRN10KJ-5-GP

R2008

1 2

10KR2J-3-GP

For VGA_ 27M

CLK_27M_VGA 83

2

1

0705 Modify: Add R2004 from RN2001.

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

0915 SWAP

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

RN2007

2 3 1

SRN2K2J-1-GP

2nd = 84.DM601.03F

84.2N702.A3F

2N7002KDW-GP

6 5

Q2001

XTAL25_IN

XTAL25_OUT

20100621 V1.2

3D3V_S03D3V_S0

12

R2012

12

R2010

DY

0705 Modify: Separate RN2009 10K to RN2019, RN2021,R2008 for layout routing.

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

SMB_CLK SMB_DATA

SML0_CLK SML0_DATA

SML1_CLK SML1_DATA

PCIE_CLK_REQ6# PCH_GPIO74

DRAMRST_CNTRL_PCH

4

4 2 3

1 1

2 3

R2009

1 2

1KR2J-1-GP

0719 Modify: R2009 change to 1K from 10K base on Intel James feedback list.

CRB : 1K CEKLT: 10K

1 2 34

1118 X02 Modify: Change X2001 to 82.30020.D41 from 82.30020.851 from Sourcer Dick updated.

X2001

R2006

R2006 1M1R2J-GP

1M1R2J-GP

2 3

1 2

82.30020.D41

2nd = 82.30020.G71

3rd = 82.30020.G61

12

R2013

UMA

UMA_DIS# DGPU_PRSNT#

10KR2J-3-GP

12

R2011

MUXLESS

10KR2J-3-GP

3D3V_S53D3V_S0

QUEEN 15

Tuesday, January 04, 2011

QUEEN 15

PCH_SMBDATA 14,15,79,82

PCH_SMBCLK 14,15,79,82

41

XTAL-25MHZ-155-GP

SC12P50V2JN-3GP

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 Optimus(Muxless) : 1 0

UMA_DIS# 22

RN2001

1 2 3 4 5

SRN10KJ-6-GP

SRN10KJ-6-GP RN2002

RN2002

1 2 3 4 5

SRN10KJ-6-GP

0625 Modify: Move R2014 to RN2002.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

RN2003

1

SRN2K2J-1-GP

23

RN2004

23

SRN2K2J-1-GP

1

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

C2008

12

SC12P50V2JN-3GP

C2007

12

0712 Modify: SWAP RN2001 PIN6,7,8

8

PCIE_CLK_LAN_REQ#

7

CLK_PCIE_WWAN_REQ#

6

USB3_PEGB_CLKREQ#

EC_SWI#

8

PCIE_CLK_REQ5#

7

CLK_PCIE_NEW_REQ#

6

PEG_B_CLKRQ#

of

20 108

3D3V_S5

A00

5

SSID = PCH

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

D D

12

C2101

SC15P50V2JN-2-GP

HDA_CODEC_SYNC29

HDA_CODEC_RST#29 HDA_CODEC_BITCLK29

C C

HDA_CODEC_SDOUT29

X2101

1 4

32

0805

X-32D768KHZ-67-GP

82.30001.A81

2nd = 82.30001.691

3rd = 82.30001.861

20101220 R2123 R2124 for change to parallel resistor

RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

0720 Modify: un-stuff R2122 33ohm.

R212233R2J-2-GP

12

DY

0707 Modify: Change RN2101 to R2122,R2123 33ohm 0402.

RN2102

1

4

2 3

SRN33J-5-GP-U

HDA_SYNC HDA_SYNC_R

2 3 1

RN2105

4

SRN33J-5-GP-U

HDA_SYNC

HDA_RST# HDA_BITCLK

HDA_SDOUT

RTC_AUX_S5

1 2 1 2

SC1U6D3V2KX-GP

A00

Flash Descriptor Security Overide

Low = Default High = Enable

No Reboot Strap

Low = Default High = No Reboot

HDA_SYNC

HDA_SDOUT

HDA_SPKR

HDA_SDOUT

HDA_SPKR

+3VS_+1.5VS_HDA_IO

DY

R2102 1KR2J-1-GP

1 2

3D3V_S0

B B

NO REBOOT STRAP

DY

R2106 1KR2J-1-GP

1 2

+3VS_+1.5VS_HDA_IO

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

1 2

PLL ODVR VOLTAGE

HDA_SYNC

RUN_ENABLE

A A

R2117

R2117 100KR2J-1-GP

100KR2J-1-GP

1 2

0707 Modify: Reserved Q2101 for isolate CODE and PCH base on design guide update 1.01. 0712 Modify: Add R2124 between HDA_SYNC_R and HDA_SYNC.

Low = 1.8V (Default) High = 1.5V

2N7002K-2-GP

G

D

S

Q2101

84.2N702.J31

2ND = 84.2N702.031

5

0625 Modify: Reserved EC2102,EC2103 on HDA_CODEC_BITCLK&HDA_CODEC_SDOUT for

HDA_SYNC_R SATA_DET#0

0720 Modify: Add R2117 100K and stuff Q2101,R2124.

EMC NEO suggestion.

R2115

R2115 20KR2J-L2-GP

20KR2J-L2-GP

R2116

R2116 20KR2J-L2-GP

20KR2J-L2-GP

C2104

4

0630 modify: Change RN2104 PH 20K to R2115,R2216 20K 0402.

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

G2101

12

GAP-OPEN

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

RTC_AUX_S5

HDA_SPKR29

HDA_SDIN029

1M1R2J-GP

R2104

1 2

R2105

330KR2F-L-GP

12

3

RTC_X1 RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK HDA_SYNC

HDA_RST#

Notes: ME_UNLOCK (HDA_SDO) connect to EC. Make sure EC drive this pin "low" all the time.

R2107 1KR2J-1-GPR2107 1KR2J-1-GP

ME_UNLOCK27

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

EC2102

1 2

DY

SC4D7P50V2CN-1GP

4

DY

1 2

SPI_CLK_R27,60 SPI_CS0#_R27,60

SPI_SI_R27,60

SPI_SO_R27,60

EC2103

SC4D7P50V2CN-1GP

HDA_SDOUT

TP2105TPAD14-GP TP2105TPAD14-GP

TP2101TPAD14-GP TP2101TPAD14-GP TP2102TPAD14-GP TP2102TPAD14-GP TP2103TPAD14-GP TP2103TPAD14-GP TP2104TPAD14-GP TP2104TPAD14-GP

1 2

R2108 33R2J-2-GPR2108 33R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 33R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

SPI_CS0#_RHDA_CODEC_BITCLK HDA_CODEC_SDOUTHDA_CODEC_SYNC

EC2101

1 2

DY

0625 Modify: Reserved EC2101 on SPI_CSO#_R for EMC NEO suggestion.

SC4D7P50V2CN-1GP

PCH_GPIO33

1

PCH_JTAG_TCK_BUF

1

PCH_JTAG_TMS

1

PCH_JTAG_TDI

1

PCH_JTAG_TDO

1

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_SI

3

PCH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGAR-GP-U2-NF

INT_SERIRQ

S_GPIO22

FP_DET#22 PSW_CLR#22

Cougar

Cougar Point

Point

RTCIHDA

JTAG

SPI

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA 6G

SATA

SATAICOMPO

SATA3RCOMPO

SATA0GP/GPIO21 SATA1GP/GPIO19

RN2103

1 2 3 4 5

SRN10KJ-6-GP

SRN10KJ-6-GP RN2104

RN2104

4

SRN10KJ-5-GP

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LDRQ0#

SERIRQ

SATA0RXN

SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA1RXP SATA1TXN SATA1TXP

SATA2RXN

SATA2RXP SATA2TXN SATA2TXP

SATA3RXN

SATA3RXP SATA3TXN SATA3TXP

SATA4RXN

SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

8 7 6

1 23

2

LPC_AD[0..3]

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37 D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

3D3V_S0

0916 X01 Modify: Add RN2104 instead of R2111 10K.

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_DET#0 BBS_BIT0

2

1

LPC_AD[0..3] 27,71

LPC_FRAME# 27,71

KB_DET# 69

INT_SERIRQ 27

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

0709 Modify: KB_DET# connect to GPIO23.(inter PH 20K)

20100625 V1.2

SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56

0629 Modify: Move All of 0.01uF cap closed to all connector base on Layout guideline.

SATA_RXN4 56 SATA_RXP4 56 SATA_TXN4 56 SATA_TXP4 56

SATA_RXN5 57 SATA_RXP5 57 SATA_TXN5 57 SATA_TXP5 57

1D05V_VTT

1 2

SATA_LED# 68

BBS_BIT0 18

PCH (SPI/RTC/LPC/SATA/I HDA)

Tuesday, January 04, 2011

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

QUEEN 15

21 108

1

HDD1

HDD2

ODD

ESATA

of

A00

5

4

3

2

1

3D3V_S0

1 2

3D3V_S0

D D

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

C C

1120 X02 Modify: Rename PCH_GPIO12 to RTC_DET# on GPIO12.

B B

A A

0712 Modify: SWAP RN2203

RN2203

2 3 1

SRN10KJ-5-GP

3D3V_S0

0701 Modify: Separate PCH_TEMP_ALERT# from RN2201 to R2222 10K base on layout limitation.

PCH_TEMP_ALERT#

MFG_MODE

EC_SMI# EC_SCI#

DGPU_HPD_INTR#

DBC_EN

0923 SWAP 1118 X02 Modify:

RTC_DET# USB2_CRT_ON#

PCH_GPIO15

3G_EN

20100625 V1.2

0629 Modify: Add R2221 10K 0402 on PCH_GPIO24(ANNIE updated) 0709 Modify: Rename PCH_GPIO24 to 3G_EN on R2221.

0719 Modify: Change R2202 to 100K from 200K.

R2202

100KR2J-1-GP

0629 Modify: Stuff R2202 200K 0402 1%(ANNIE updated)

4

R2220 10KR2J-3-GPR2220 10KR2J-3-GP

1 2

R2222 10KR2J-3-GPR2222 10KR2J-3-GP

1 2

R2223 10KR2J-3-GPR2223 10KR2J-3-GP

1 2

RN2201

1 2 3 4 5

SRN10KJ-6-GP

5

H_A20GATE H_RCIN#

PCH_GPIO48

8 7 6

RN2204

4

SRN10KJ-5-GP

SRN10KJ-5-GP R2201

R2201

1 2

R2221

1 2

10KR2J-3-GP

SATA_ODD_PRSNT#

1 23

1KR2J-1-GP

Note: For PCH debug with XDP, need to NO STUFF R2218

20100625 V1.2

1120 X02 Modify: Rename PCH_GPIO12 to RTC_DET# on GPIO12.

0908 X01 Modify: change FFS_INT2_R from PCH GPIO48 to GPIO14 Keep PCH_GPIO5 PH R2201,PCH_GPIO48 PH R2220

0720 Modify: Removed DBC_EN on GPIO22.

3D3V_S0

0701 Modify: Separate MFG_MODE from RN2202 to R2223 10K base on layout limitation.

0916 X01 Modify: Move EC_SCI#,DBC_EN to RN2201. Move S_GPIO to RN2103. Move PSW_CLR# to RN2104.

1118 X02 Modify: Rename USB3_PWR_ON to PCH_GPIO57. 1120 X02 Modify: Reserved USB2_CRT_ON# to control U6102 USB power switch from PCH GPIO57.

3D3V_S5

0709 Modify: Rename PCH_GPIO22 to DBC_EN. Rename PCH_GPIO24 to 3G_EN.

SSID = PCH

S_GPIO GPIO0

S_GPIO21

EC_SMI#27

EC_SCI#27

RTC_DET#60

SATA_ODD_PRSNT#56

DGPU_PWROK83,92,93

TPAD14-GP

PSW_CLR#21

GAP-OPEN

21

G2201

Rename GFX_CRB_DET to GSENSOR_DET on GPIO39.

USB2_CRT_ON#61

0714 Modify: Add TP2206~TP2209 on PCH NCTF pin.

[VRAM_SIZE1:VRAM_SIZE2] LL=512M / HL=1G / LH=2G

0705 Modify: Removed R2214~R2217 10K 0402 on VRAM_SIZE1&2.

4

R2213 0R0402-PADR2213 0R0402-PAD

TP2210

3G_EN82

TP2203

PSW_CLR#

FP_DET#21

TP2206TPAD14-GP TP2206TPAD14-GP

TP2207TPAD14-GP TP2207TPAD14-GP TP2208TPAD14-GP TP2208TPAD14-GP

TP2209TPAD14-GP TP2209TPAD14-GP

1 2

1

1 1

1

R2218

1 2

100R2J-2-GP

EC_SMI# DGPU_HPD_INTR# EC_SCI# ICC_EN#

RTC_DET#

PCH_GPIO15

DGPU_PWROK

1

PCH_GPIO27

1

PLL_ODVR_EN

DMI_OVRVLTG FDI_OVRVLTG MFG_MODE

GSENSOR_DET

PCH_GPIO48

PCH_TEMP_ALERT#

USB2_CRT_ON#

PCH_NCTF_1

PCH_NCTF_2 PCH_NCTF_3

PCH_NCTF_4

PCH_GPIO16

DBC_EN

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

6 OF 10

A20GATE

PECI

RCIN#

INIT3_3V#

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14

AH8 AK11 AH10 AK10 P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

UMA_DIS# VRAM_SIZE1 VRAM_SIZE2

TS_VSS

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

PROCPWRGD

GPIO

THRMTRIP#

CPU/MISC

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4 NCTF_VSS#BJ44 NCTF_VSS#BJ45 NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

D1,D49,E1,E49,F1,F49

NCTF_VSS#F49

PLL ON DIE VR ENABLE



NOTE:This signal has a weak internal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

PLL_ODVR_EN

3

1 2

DY

R2212

1KR2J-1-GP

SATA_ODD_PWRGT 56 UMA_DIS# 20

TP2204

TPAD14-GP

1 1

H_PECI_R

PCH_THERMTRIP_R INIT3_3V#

1 2

R2219 0R0402-PADR2219 0R0402-PAD

0707 Modify: Change R2219 change to 0ohm 0402 from short pad.

3D3V_S0

12

R2207

R2207 10KR2J-3-GP

10KR2J-3-GP

DY

FDI_OVRVLTG

12

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

TPAD14-GP

TP2205

TPAD14-GP

H_A20GATE 27

R2203

1 2

DY

0R2J-2-GP

H_RCIN# 27

R2204 390R2J-1-GPR2204 390R2J-1-GP

TP2201

1

0R2J-2-GP

H_CPUPWRGD 5,36

1 2

TPAD14-GP

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

DMI TERMINATION VOLTAGE OVERRIDE

3D3V_S0

ICC_EN#

12

R2209

R2209 10KR2J-3-GP

10KR2J-3-GP

DY

12

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

R2211

1 2

DMI_OVRVLTG

1KR2J-1-GP

2

GPIO36 (DMI_OVRVLTG)

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Integrated Clock Chip Enable

ICC_EN#

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

GSENSOR_ST GSENSOR_ADI

R2205 DY 10K

R2206 100K DY

3D3V_S0

DY

H_PECI 5,27

DY

H_THERMTRIP# 5,36

0625 Modify: Change PL 100K 0402 from PH on GFX_CRB_DET.

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (GPIO/CPU)

QUEEN 15

Tuesday, January 04, 2011

QUEEN 15

1

12

R2205

R2205 10KR2J-3-GP

10KR2J-3-GP

GSENSOR_DET

12

R2206

R2206 100KR2J-1-GP

100KR2J-1-GP

of

22 108

A00

5

1D05V_VTT

(1uFx3)

1D05V_VTT

6A

12

C2301

12

C2305

C2306

SC10U6D3V5KX-1GP

1.3A(Total current of VCCCORE)

12

SC10U6D3V5KX-1GP

TP2301TPAD14-GP TP2301TPAD14-GP

12

SC1U6D3V2KX-GP

0818 De-cap

0.266A (Totally VCC3_3 current)

12

C2302

2.925A(Total current of VCCIO)

C2303

SC1U6D3V2KX-GP

C2307

SC1U6D3V2KX-GP

1D05V_VTT

1

(10uF x1)

12

C2308

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

3D3V_S0

SSID = PCH

D D

(10uFx1_0603)

(1uF x4)

C C

(0.1uF x1)

0.159A(Totally current of VCCVRM)

B B

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop

1D5V_S0

TP2302TPAD14-GP TP2302TPAD14-GP

1D05V_VTT

1

0.042A (Totally current of VCCDMI)

4

12

C2304

SC1U6D3V2KX-GP

VCCAPLLEXP

12

C2309

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCFDIPLL

+1.05VS_VCC_DMI

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

NAND / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

VCC3_3

VCCVRM

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

3

0.001A

+VCCA_DAC_1_2

U48

U47

0.001A

+3VS_VCCA_LVDS

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

0.16A

VCCVRM

AT16

0.042A

+1.05VS_VCC_DMI

AT20

AB36

0.02A

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

(0.1uF/0.01uF x1) (10uF x1_0603)

12

C2313

0.06A

+1.8VS_VCCTX_LVDS

0.266A

12

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

0.19A

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

0.02A

12

C2314

SCD01U16V2KX-3GP

12

C2316

(0.1uFx1)

R2308

1 2

0R0402-PAD-2-GP

A00

1 2

R2306

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

A00

1 2

R2307

0R0402-PAD-2-GP

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

A00 1228

R2301

1 2

0R0402-PAD-2-GP

1111 X02 Modify: Change VCCADAC power source to 3D3V_DAC_S0 from 3D3V_S0.

12

C2315

SCD1U10V2KX-5GP

12

SCD01U16V2KX-3GP

0R0402-PAD-2-GP

0917 X01 Modify: Change R2304 to 0R0603

SC10U6D3V5KX-1GP

short pad from 0ohm.

12

C2318

C2317

SCD01U16V2KX-3GP

3D3V_S0

A00

1D5V_S0

1D05V_VTT

(1uF x1)

1D05V_VTT

(1uFx1) (10uFx1)

3D3V_S5

(1uFx1)

2

3D3V_DAC_S0

3D3V_S0

L2301

1 2

DY

HCB1608KF-181-GP

68.00214.051

2nd = 68.00206.041

3rd = 68.00335.081

R2304

1 2

0R0603-PAD

R2305

1 2

0R0805-PAD

SC10U6D3V5KX-1GP

1119 X02 Modify: Reserved R2308 on VCCVRM power rail.

(0.01uF x2) (22uF x1)

1D8V_S0

3D3V_S0

1D8V_S0

(0.1uFx1)

1

Refer to NPCE795 shared SPI flash architecture

3.3V CRT LDO

3D3V_S05V_S5 3D3V_DAC_S0

U2301

1

1122 X02 Modify: Removed U2302 LDO for VCCVRM.

A A

C2311

12

20100621 V1.2

SC1U10V2KX-1GP

5

4

A00 1229 add 3rd Richtek(74.09198.G7F) on U2301 at XBuild batch run config

3

VIN

2

GND EN3NC#4

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

3rd = 74.07716.A7F

1117 X02 Modify: Add G9091 LDO circuit for CRT DAC power to avoid monitor noise issue. 1122 X02 Modify: base on layout condition change 3D3V_DAC_S0 circuit.

Current Limit=360mA

5

VOUT

4

12

C2312

SC1U6D3V2KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

PCH (POWER1)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

23 108

1

A00

5

4

3

2

1

SSID = PCH

1

TP2405TPAD14-GP TP2405TPAD14-GP

1

(10uFx1)

1

12

C2415

12

(1uFx1)

TP2406TPAD14-GP TP2406TPAD14-GP

VCCACLK

+VCCPDSW

DCPSUSBYP

1

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS1

12

C2407

1D5V_S0

C2408

SC1U6D3V2KX-GP

0818 De-cap

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

+VCCDIFFCLK

0.095A

+V1.05S_SSCVCC

(1uFx1)

+VCCSST

12

DCPSUS

1

C2418

SCD1U10V2KX-5GP

12

C2422

C2421

SCD1U10V2KX-5GP

TP2401TPAD14-GP TP2401TPAD14-GP

0.002A

3D3V_S0

(10uFx1)

D D

C C

1D05V_VTT

2nd = 68.1001E.10N

B B

1D05V_VTT

A A

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001E.10N

L2402

1 2

IND-10UH-218-GP

68.10050.10Y

L2403

1 2

IND-10UH-218-GP

68.10050.10Y

R2404

1 2

0R0402-PAD-2-GP

A00

R2405

1 2

0R0402-PAD-2-GP

0.08A

+1.05VS_VCCA_A_DPL

12

C2443

DY

0.08A

+1.05VS_VCCA_B_DPL

12

C2444

DY

A00

+VCCDIFFCLK

12

SC1U6D3V2KX-GP

+V1.05S_SSCVCC

12

SC1U6D3V2KX-GP

5

(1uFx1)

+V3.3S_VCC_CLKF33

C2401

12

(22uFx2_0603) (1uFx3)

(1uFx1) (220uFx1)

12

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

12

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

C2412

C2413

12

C2402

C2402 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

1D05V_VTT

(1uFx1) (220uFx1)

SCD1U10V2KX-5GP

1D05V_VTT

(1uFx1)

3D3V_S5

(0.1uFx1)

1.01A (Total current of VCCASW)

C2404

C2403

12

0714 Modify: Reserved C2443,C2444 on +1.05VS_VCCA_A_DPL, +1.05VS_VCCA_B_DPL same as DG15.

0617 Modify: Joseph Rename 1D5V_S0_1D8V_S0 to 1D5V_S0 for VCCVRM.

C2411

1D05V_VTT

(0.1uFx2) (4.7uFx1_0603)

RTC_AUX_S5

(0.1uFx2) (1uFx1)

C2404

12

SC10U6D3V5KX-1GP

+VCCRTCEXT

12

(0.1uFx1)

R2406

1 2

0R0603-PAD

C2414

SC1U6D3V2KX-GP

(0.1uFx1)

(1uFx1)

0.001A

C2417

SC4D7U6D3V3KX-GP

6uA

R2403

1 2

0R0603-PAD

TP2404TPAD14-GP TP2404TPAD14-GP

1D05V_VTT

TP2402TPAD14-GP TP2402TPAD14-GP

12

C2406

SC1U6D3V2KX-GP

0.16A (Totally current of VCCVRM

+VCCDIFFCLKN

0.055A

12

SCD1U10V2KX-5GP

0714 Modify: Removed C2419 1uF base on Annie updated schematic.

12

4

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

PCI/GPIO/LPCMISC

SATA USB

CPURTC

HDA

3

10 OF 10

VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCC3_3 VCC3_3 VCC3_3

VCC3_3

VCCIO

VCCIO VCCIO

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO VCCIO VCCIO

VCCASW

VCCSUSHDA

N26 P26 P28 T27 T29

0.097A (Totally current of VCCSUS3_3)

T23 T24 V23 V24 P24

T26

M26

AN23 AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

T21

V21

T19

P32

1D05V_VTT

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

+5VS_PCH_VCC5REF

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

1D5V_S0

SCD1U10V2KX-5GP

1D05V_VTT

SCD1U10V2KX-5GP

0.01A

C2433

SCD1U10V2KX-5GP

C2433

3D3V_S5

0818 De-cap

12

DY

12

C2428

12

C2430

12

C2429

12

C2432

12

C2435

+3VS_+1.5VS_HDA_IO

(0.1uFx1)

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2434

DY

C2423

C2423 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1

C2437

C2437 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

2

1D05V_VTT

(1uFx1)

0818 De-cap

3D3V_S5

(0.1uFx1)

3D3V_S5

(0.1uFx1)

TP2403 TPAD14-GPTP2403 TPAD14-GP

0.001A

3D3V_S5

(1uFx1)

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

(0.1uFx1)

R2411

1 2

DY

0R3J-0-U-GP

1D05V_VTT

(1uFx1)

3D3V_S5

2nd = 83.R2004.B8F

21

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

1 2

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R2408

5V_S5

(0.1uFx1)

0.001A

3D3V_S0

21

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

2nd = 83.R2004.B8F

3D3V_S0

83.R0304.A8F

12

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

10R2J-2-GP

(0.1uFx2)

3D3V_S0

1D05V_VTT

(1uFx1)

1D05V_VTT

(10uFx1)

+3VS_+1.5VS_HDA_IO

R2409

1 2

0R0603-PAD

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

PCH (POWER2)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

R2407

5V_S0

(1uFx1)

24 108

1

3D3V_S5

A00

of

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

2

Date: Sheet

PCH (VSS)

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

25 108

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

Reserved

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

of

26 108

1

A00

SSID = KBC

3D3V_AUX_KBC

1 2 12

D D

0708 Modify: Rename EG_EN to MEDIA_BTN2# on GPIO96. 0702 Modify: Rename CHARGE_LED# to CHG_AMBER_LED# Rename DC_BATFULL# to BATT_WHITE_LED#.

0702 Modify: Rename EC_GPIO6 to PSL_IN2 0707 Modify: Rename DISCRETE# to MODEL_ID_DET. Rename EC_GPIO36 for MEDIA_BTN3#.

1 2

0628 Modify: Move R2771 to closed 3D3V_AUX_KBC power

R2771

rail base on layout placement.

2D2R3-1-U-GP

12

C2704

C2701

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

0720 Modify: Stuff C2714 0.1uF on AD_IA.

0629 Modify: Rename TP_LOCK_LED#&BATT_WHITE_LED# 0702 Modify: Rename EC_GPIO70 to PSL_IN1 Rename EC_GPIO71 to PSL_OUT

C C

0604 Modify: RN2704 pull-Low 10K Resistor to DY on BLUETOOTH_EN.

5

R2702

R2702 0R0603-PAD

0R0603-PAD

12

C2705

C2706

DY

SCD1U10V2KX-5GP

C2714 SCD 1U10V2KX-5GPC2714 SCD1U10V2KX-5G P

EC_AGND

FAN1_DAC28

SUS_PWR_ACK19

USBCHARGER_CB057

USB3_PWR_ON82

BATT_WHITE_LED#68

S5_ENABLE36

LID_CLOSE#70

RSMRST#_KBC19

PM_SLP_S4#19,46,75

ME_UNLOCK21

WIFI_RF_EN82 BLUETOOTH_EN63,82 S0_PWR_GOOD19,36

TP_LOCK_LED#68

USB_PWR_EN#61

AC_PRESENT19,86

IMVP_PWRGD36,42

0706 Modify: KBC GPIO7 change to DISCRETE# KBC GPIO97 change to IMVP_PWRGD.

0714 Modify: Change C2709,C2710 to EC_AGND from GND.

12

C2708

SCD1U10V2KX-5GP

C2709

EC_AGND

R2762

1 2

A00

0R0402-PAD-2-GP

KBC_VCORF

12

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

12

SC2D2U10V3KX-1GP

PCB_VER_AD

MEDIA_BTN2#

USB3_PWR_ON

PSL_IN2 MODEL_ID_DET

ECSMI#_KBC

PSL_IN1 PSL_OUT EC_GPIO72

12

C2707

SCD1U10V2KX-5GP

AD_IA40

1 2

PSID_EC82

CPU_THRM28

LCD_TST49

SYS_THRM28

CAP_LED69

MEDIA_BTN3#82

BAT_IN#39

RCID82

C2712 Need very close to EC

SCD1U10V2KX-5GP

C2710

EC_GPIO97

VBAT

3D3V_AUX_KBC_VCC

U2701A

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

79

GPIO2

95

GPIO3/AD6

96

GPIO4/AD5

108

GPIO5/AD4

93

PSL_IN2#_GPIO6

94

GPIO7/AD7

114

GPIO16

6

GPIO24

109

GPIO30

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

23

GPIO46/CIRRXM/TRST#

26

GPIO51

73

PSL_IN1_GPIO70

74

PSL_OUT_GPIO71

75

VBKUP

82

GPIO75

83

GPO76/SHBM

84

GPIO77

91

GPIO81

110

GPO82/IOX_LDSH/TEST#

112

GPIO84/IOX_SCLK/XORTR#

107

GPIO97

44

VCORF

NPCE795PA0DX-GP-U

VCC19VCC46VCC76VCC88VCC

GND18GND45GND78GND89GND

115

GND

5

116

ROSA Multi GPIO setting

0719 Modify: Reserved 0.1uF on all of ADC input pins base on NUVOTON feedback list.(C2717~C2721)

C2719 SCD 1U10V2KX-5GP

CPU_THRM USB3_PWR_ON SYS_THRM

L_BKLT_EN17

12

DY

C2720 SCD 1U10V2KX-5GP

12

DY

C2721 SCD 1U10V2KX-5GP

12

DY

PANEL_BLEN

1 2

R2761 0R0402- PADR2761 0R0402-PAD

0630 Modify: Removed R2762 100K 0402.

EC_AGND

20100712 V1.5

EC_SWI#20

EC_SCI#22

B B

0714 Modify: Un-stuff D2701,D2704 and Add R2758,R2759 ohm confirm with NUVOTON and SW.

RN2706

4

SRN10KJ-5-GP

EC_SWI#20

EC_SCI#22

3D3V_AUX_S5

1

KBC_ON#_GATE

23

SCD1U10V2KX-5GP

PSL_IN2

BAT54CPT-GP

KBC_PWRBTN#68

3

D2702

2ND = 83.00054.Q81

83.R2003.E81

AC_IN#_KBC

A A

R2704

1

1 2

330KR2J-L1-GP

83.R2003.E81

2ND = 83.00054.Q81

2

KBC_ON#

2

10mW

1

BAT54CPT-GP

330KR2J-L1-GP

KBC_ON#_R

D2703

3

0902 X01 Modify: Add C2722 0.1uF between Q2703 G&S pin for fixed leakage voltage to 3D3V_AUX_KBC under DC mode. 0916 X01 Modify: Add Q2706 2N7002 to avoid leakage loop from 3D3V_S5 to 3D3V_AUX_KBC issue when 10mW latched fail timing.

EC_GPIO72

AC_IN# 40

5

R2711 0R0402- PADR2711 0R0402-PAD

D2701

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

D2704

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

R2758

1 2

0R0402-PAD-2-GP

A00

R2759

1 2

0R0402-PAD-2-GP

3D3V_AUX_S5

C2722

1 2

SCD1U10V2KX-5GP

G

12

C2713

DY

2N7002K-2-GP

G

S

Q2706

84.2N702.J31

2ND = 84.2N702.031

102

AVCC

GPIO11/CLKRUN#

GPIO67/PWUREQ#

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

1 2

ECSWI#_KBC

3

ECSCI#_KBC

3

ECSWI#_KBC

ECSCI#_KBC

S

G

D

3D3V_AUX_KBC

S5_ENABLE

D

4

SCD1U10V2KX-5GP

4

1 OF 2

VDD

LRESET#

LCLK

LFRAME#

LAD3 LAD2 LAD1 LAD0

SERIRQ

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO85/GA20

KBRST#/GPIO86

GPIO27/PSDAT2

GPIO26/PSCLK2

GPIO35/PSDAT1

GPIO37/PSCLK1

GPIO17/SCL1

GPIO22/SDA1

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

F_CS0#

F_SCK

F_SDI/F_SDIO1

F_SDIO/F_SDIO0

AGND

103

EC_AGND

Q2703

Q2703 DMP2130L-7-GP

DMP2130L-7-GP

2ND = 84.03413.A31

84.02130.031

4

3D3V_AUX_KBC

0719 Modify: Reserved 0.1uF on all of ADC input pins base on

3D3V_S0

NUVOTON feedback list.(C2717~C2721)

12

C2702

7 2 3 1 128 127 126 125 8 9 29 124 123 121 122

27 25 11 10 71 72

70 69 67 68 119 120 24 28

90 92 86 87

C2703

DY

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

C2711

DY

1 2

SC220P50V2KX-3GP

A00

R2735

PLT_RST#_EC

1 2

0R0402-PAD-2-GP

CLK_PCI_KBC 18

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

PANEL_BLEN

ECSCI#_KBC ECSWI#_KBC

AD_IA_HW2

MEDIA_BTN1#

EC_ENABLE#_1

PROCHOT_EC

EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C EC_SPI_DO_C

NOTE: Locate resistors R2736,R2719 and R2722 close to the NPCE795P.

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.

LPC_FRAME# 21,71

H_A20GATE 22 H_RCIN# 22

BLON_OUT 49

AD_IA_HW2 40

PCH_WAKE# 19

TPDATA 69 TPCLK 69

BAT_SCL 39,40 BAT_SDA 39,40 SML1_CLK 20,86 SML1_DATA 20,86

PM_LAN_ENABLE 82

LCD_TST_EN 49

A00

R2737 0R 0402-PAD-2-GPR2737 0R0402-PAD-2-GP

1 2

R2722 33R2J - 2-GPR2722 33R2J-2-GP

INT_S ERIRQ 21 PM_CLKRUN# 19

HDMI_ IN# 5 1

12 12

12

EC_GPIO47 High Active

PROCHOT_EC

12

R2732

G

S

100KR2J-1-GP

A00 1222

PCB_VER_AD MODEL_ID_DET

PLT_RST# 5,18,71,75,82,83

LPC_AD[0..3] 21,71

<------ TP

33R2J-2-GPR2736 33R 2J-2-GPR 2736 33R2J-2-GPR2719 33R 2J-2-GPR 2719

2N7002K-2-GP

Q2702

84.2N702.J31

2ND = 84.2N702.031

12

R2724

R2724 47KR2F-GP

47KR2F-GP

12

R2726

R2726 100KR2F-L1-GP

C2717

<------ BATTERY / CHARGER <------PCH / eDP

100KR2F-L1-GP

1 2

EC_AGND

0707 Modify: Rename PCH_TEMP_ALERT# for HDMI_IN#

0702 Modify: Rename CHARGE_LED# to CHG_AMBER_LED# Rename DC_BATFULL# to BATT_WHITE_LED#.

0709 Modify: EC_GPIO27 change to PCH_WAKE# to PCH. 0709 Modify: KB_DET# rename to MEDIA_BTN1# on KBC GPIO26.

0629 Modify: Rename PWRLED#&PWR_BTN_LED#&CHARGE_LED#. 0715 Modify: Removed PWR_BTN_LED# on KBC GPIO45. 0720 Modify: Change MEDIA_LED2# to KBC GPIO45. Add AD_IA_HW on KBC GPIO66.

SPI_CS0#_R 21,60 SPI_CLK_R 21,60 SPI_SO_R 21,60

SPI_SI_R 21,60

EC_SPI_DI_C

12

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

0604 Modify: Add Pull down 100k ohm at F_SDI for Power consumption concern.

H_PROCHOT#_EC

D

R2733 0R0402- PADR2733 0R0402-PAD

PSL SOLUTION

0712 Modify: default stuff R2756, un-stuff R2734.

A00 1228

EC_GPIO72

R2756

1 2

10mW

0R0402-PAD-2-GP

AC_OK

AC_OK40

PSL_OUT

NOTES: Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.

1 2

PSL

DY

R2767

1 2

G

PSL

S

Q2705

Q2705 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

A00 1228

R2768

0R2J-2-GP

KBC_ON#_R

0R2J-2-GP

D

0702 Modify: Rename EC_GPIO71 to PSL_OUT

PSL_IN1

PSL

12

R2769

R2769 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_KBC

3

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X01 X02

A00 Reserved Reserved

100.0KX00

100.0K

Reserved 100.0K 215.0K 1.048V

NOTES: The NPCE795P GPIO/PWM outputs that are connected to LEDs have high drive buffers (20mA) and can be connected directly to the LEDs.

0707 Modify: KBC_GPIO14 change to PCIE_WAKE#.

FAN_TACH128

PM_PWRBTN#19

PCIE_WAKE#75,82 PM_SLP_S3#19,36,37,47,75

CHG_AMBER_LED#68

KBC_BEEP29

MEDIA_LED1#82

KB_BL_CTRL69

AD_IA_HW40 MEDIA_LED3#82 MEDIA_LED2#82

PWRLED#68

E51_RxD82

E51_TxD82

AMP_MUTE#29

PCH_SUSCLK_KBC19

1D05V_VTT

H_PECI5,22

R2721 43R 2J-GPR2721 43R2J-GP

Need very close to EC

PURE_HW_SHUTDOWN#28,36,86

1 2

H_PROCHOT # 5,40,42

10mW SOLUTION

3D3V_AUX_KBCRTC_AUX_S5

R2734

1 2

DY

R2763

AC_IN#_KBC

10mW

0R0402-PAD-2-GP

0702 Modify: Rename EC_GPIO70 to PSL_IN1

EC_ENABLE#_1

R2766

VBACKUP

EC_GPIO72

0R2J-2-GP

A00 1228

PSL_IN1

12

2N7002K-2-GP

G

10mW

D

S

Q2704

84.2N702.J31

2ND = 84.2N702.031

12

10mW

0R0402-PAD-2-GP

A00 1228

PSL_IN1

PSL_OUT

KBC_ON#

KBC_ON#_RKBC_ON#

3

ECRST#

1 2 1 2

R2720 0R0402- PADR2720 0R0402-PAD

3D3V_AUX_S5

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K100.0K 1.358VReserved

174.0KReserved 100.0K 1.204V

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

SCD1U10V2KX-5GP

20100609 V1.0

U2701B

31

GPIO56/TA1

117

GPIO20/TA2

63

GPIO14/TB1

64

GPIO01/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM

85

EC_VTT

C2716

SCD1U16V2KX-3GP

12

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

0621 Modify: Removed R2723

PECI

12

VCC_POR#

113

GPIO87/CIRRXM/SIN_CR

111

GPIO83/SOUT_CR/TRIST#

30

GPIO55/CLKOUT/IOX_DIN_DIO

77

GPIO00/EXTCLK

13

PECI

12

VTT

NPCE795PA0DX-GP- U

KBSOUT15/GPIO61/XOR_OUT

12

E

MMBT3906-4-GP

B

DY

Q2701

C

84.T3906.A11

2nd = 84.03906.F11

EC GPIO standard PH/PL

BAT_SCL BAT_SDA

BAT_IN# AC_IN#_KBC

0630 Modify: Removed LID_CLOSE# PH 10K on RN2705.

S5_ENABLE ECRST#

EC_ENABLE#_1

0623 Modify: Change RN2702 to R2712 10K 0402 Resistor on FAN_TACH1.

FAN_TACH128

FAN_TACH1

E51_RxD

BLUETOOTH_EN

0623 Modify: Change RN2704 to R2708 10K 0402

0604 Modify: RN2704 pull-Low 10K Resistor to DY on BLUETOOTH_EN.

Resistor on BLUETOOTH_EN.

ECRST#

3D3V_AUX_KBC

2

12

R2710

64.33025.6DL

C2718

0707 Modify: Rename DISCRETE# to MODEL_ID_DET. Change R2739 to 100K 0402 from 10K.

KBSOUT0/JENK#

KBSOUT4/JEN0#

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK KBSOUT11/P80_DAT

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

C2715

SC1U6D3V2KX-GP

RN2701

4

SRN4K7J-8-GP

SRN4K7J-8-GP RN2703

RN2703

4

SRN100KJ-6-GP

RN2705

8 7 6

SRN10KJ-6-GP

1 2

R2712 10KR2J- 3-GPR2712 10KR2J-3-GP

DY

1 2

R2708 10KR2J- 3-GP

DY

1 2

R2709 10KR2J- 3-GP

R2710 33KR2F-GP

33KR2F-GP

0728

Ventura need to change t o 215K(64.21535.6DL)

1 2

EC_AGND

2 OF 2

53 52

KBSOUT1/TCK

51

KBSOUT2/TMS

50

KBSOUT3/TDI

49 48

KBSOUT5/TDO

47

KBSOUT6/RDY#

43

KBSOUT7

42

KBSOUT8

41 40 39 38 37 36 35 34 33

54

KBSIN0

55

KBSIN1

56

KBSIN2

57

KBSIN3

58

KBSIN4

59

KBSIN5

60

KBSIN6

61

KBSIN7

0714 Modify: Add USB_DET# on KBC GPIO57/KBSOUT17.

3D3V_AUX_KBC

23 1

1 23

1 2 3 45

0628 Modify: Stuff R2712 and Removed R2805.

3D3V_S0

2

MODEL_ID_DET(GPIO07)

DQ15_ATI DQ15_NVIDIA DN15_UMA DN15_ATI DQ13_UMA DQ13_ATI DN13_UMA DN13_ATI DQ15_Ventura 100.0K 215.0K 1.048V

Notes:

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

215K=64.21535.6DL

1

100.0KDQ15_UMA 3.0V

100.0K

10.0K

20.0K

33.0K

47.0K

64.9K

76.8K

100.0K

143.0K100.0K 1.358V

174.0K100.0K

The total SPI interface signal between EC and PCH can¡¦t not exceed 6500mil. The mismatch between SPI signal must be wit h i n 500mil

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

USB_DET#

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL[0..16] 69

A00 R2739 R2774 for change to parallel resistor

KROW[0..7] 69

0709 Modify: Add R2774,R2775 PH 100K to 3D3V_AUX_KBC for MEDIA_BTN2#,MEDIA_BTN3#. Add R2776 100K to 3D3V_AUX_KBC for PCIE_WAKE# from DEVICE to KBC. KB_DET# rename to MEDIA_BTN1# on KBC GPIO26.

USB_DET# MEDIA_BTN1#

MEDIA_BTN3# PCIE_WAKE#

0722 Modify: Add R2757 0ohm only for DQ15 stuff, change D2706 only for DN15 stuff.

INSTANT_ON#82

0712 Modify: Add D2706 connect to MEDIA BUTTON Instant_on#. 0713 Modify: Add R2772,D2707 for USBCHARGER DETECT Function.

0723 Modify: Add R2764,D2708 Base on Dell Peter request, both 13¡¨/15¡¨ Media BTN 2(Recovery Button) need support bootable capability.

USBDET_CON#57

DATA_RECOVERY#82

Title

Size Document Number Rev

Size Document Number Rev A2

A2

A2 Date: Sheet

Date: Sheet

MEDIA_BTN2# MODEL_ID_DET

A00

4

SRN100KJ-6-GP

0709 Modify: Removed R2772 10K PH on EC_GPIO27. 0714 Modify: Un-stuff D2705 and Add R2760 between EC_SMI# and ECSMI#_KBC already confirm with NUVOTON and SW.

EC_SMI#22

MEDIA BUTTON CONTROL

1 2

R2772 100KR2J-1-GPR2772 100KR2J-1-GP

1 2

R2770 100KR2J-1-GPR2770 100KR2J-1-GP

1 2

R2775 100KR2J-1-GPR2775 100KR2J-1-GP

1 2

R2776 100KR2J-1-GPR2776 100KR2J-1-GP

R2757

DQ15

1 2

INSTANT_ON#

3

USBDET_CON#

3

DATA_RECOVERY#

3

KBC Nuvoton NPCE795

QUEEN 15

Tuesday, January 04, 2011

3D3V_AUX_KBC

RN2707

1 23

D2705

1

DY

ECSMI#_KBC

3

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

A00

R2760

ECSMI#_KBC

1 2

0R0402-PAD-2-GP

3D3V_AUX_KBC

0R2J-2-GP

BAT54CPT-GP

MEDIA_BTN1#

1

83.R2003.E81

DN15

2ND = 83.00054.Q81

KBC_ON#_R

2

D2706

D2706 BAT54CPT-GP

BAT54CPT-GP

USB_DET#

1

83.R2003.E81

2ND = 83.00054.Q81

KBC_ON#_R

2

D2707

BAT54CPT-GP

MEDIA_BTN2#

1

83.R2003.E81

2ND = 83.00054.Q81

KBC_ON#_R

2

D2708

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

27 108

1

EC_AGND

of

2.75V100.0K

2.48V100.0K

2.24V

2.0V

1.87V

1.65V

1.204V

A00

5

SSID = Thermal

1119 X02 Modify: Change U2801,U2804,U2805 VCC power to 3D3V_DAC_S0 from 3D3V_S0.

D D

R2808

R2808 NTC-100K-8-GP

C C

B B

NTC-100K-8-GP

3D3V_DAC_S0

12

C2802

SCD1U10V2KX-5GP

12

C2806

C2806 SC470P50V3JN-2GP

1

SC470P50V3JN-2GP

DY

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

12

2ND = 84.03904.P11

3

84.03904.L06

Q2801

PMBS3904-1-GP

2

2.System Sensor, Put on palm rest

Thermal sensor P2800

P2800_DXP

12

C2807

C2807 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

P2800_DXN

1117 X02 Modify: Rename U2801&U2804 pin 8 to THERM_SYS_SHDN#_OTZ from THERM_SYS_SHDN#.

4

12

R2803

P2800A1

107KR2F-GP

87.1 Degree

ADJ

12

P2800A1

R2804

R2804 226KR2F-GP

226KR2F-GP

SCD1U10V2KX-5GP

THERM_SYS_SHDN#_OTZ

1.H/W T8 Shutdown

12

C2805

P2800A1

P2800EA1-GP

5

VCC

6

DXP

7

DXN

8

OTZ

U2801

74.02800.A71

3

A00 1227

1111 X02 Modify: ADJ&ADJ_VGA power source change to 3D3V_DAC_S0 from 3D3V_S0 to solve T8 shut down issue.

1227 A00 Modify: If stuff P2800EA1 then must stuff R2803,R2804,C2805 but if stuff P28003B0 should be unstuff.

TDR TDL

GND

ADJ

4 3 2

ADJ

1

SYS_THRM 27 CPU_THRM 27

FAN_TACH127

AFTP2801AFTP2801 AFTP2802AFTP2802

1117 X02 Modify: Add R2805 0hm between THERM_SYS_SHDN#_OTZ and THERM_SYS_SHDN#.

PURE_HW_SHUTDOW N#27,36,86

0705 Modify: R2802 change to 0ohm 0402 from short pad and default un-stuff.

1 2

R2807 0R0402-PADR2807 0R0402-PAD

FAN_TACH1_C

1

FAN_VCC

1

EMI/ESD

FAN_VCC

X02 1118

2

Fan controller P2793

U2802

R2802 0R2J-2-GP

1 2

DY

5V_S0

FAN1_DAC27

*Layout* 10 mil

For linear FAN

0628 Modify: Stuff R2712 and Removed R2805.

FAN_TACH1_C

*Layout* 15 mil

12

C2809

0724 Modify: Removed C2808 0.1uF.

SC4D7U6D3V3KX-GP

R2805

THERM_SYS_SHDN#_OTZ

12

C2811

DY

R2805

1 2

Q2802

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

FAN_VCC

A00 1224

0R2J-2-GP

S

G

U2802

FON#

1

FON#

2

VIN

3

VO

4

VSET

G991P11U-GP

74.00991.031

2nd = 74.02793.A31

3rd = 74.05606.A71

0614 Modify: Change FAN1 connector part number to

20.D0210.103 base on ME EMN and DXF. 0712 Modify: Change FAN1 part number to 20.F1639.004 from 20.D0210.103 base on latest EMN and DXF.

21

D2802

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

A00 1228

THERM_SYS_SHDN#

1

8

GND

7

GND

6

GND

5

GND

3

FAN_VCC

12

C2810

DY

SC2200P50V2KX-2GP

3D3V_S0

0709 Modify: Removed R2811 and connect 3D3V_S0 to Q2802.G directly.

2 1

0831

2nd = 20.F1841.003

1110 X02 Modify: Add 2nd 20.F1841.003 on FAN1 from ME updated connector list.

12

R2809

R2809 100KR2J-1-GP

100KR2J-1-GP

5V_S03D3V_DAC_S0

12

C2803

5

4

FAN1

FAN1 ACES-CON3-11-GP

ACES-CON3-11-GP

20.F0772.003

12

C2804

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

12

EC2801

DY

SCD1U16V2KX-3GP

A00 1228 Cancel VGA Thermal sensor P2800 circuit

A A

5

4

3

X02 1111

A00 1228 un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805

1 2

THERM_SYS_SHDN#

20101019 X01: Reserve U2804 for PURE_HW_SHUTDOWN# test. 20101020 X01: Reserve R2810 to 3D3V_S0 and R2811 to GND for HYST.

1111 X02 Modify: ADJ&ADJ_VGA power source change to 3D3V_DAC_S0 from 3D3V_S0 to solve T8 shut down issue.

24K3R2F-1-GP

R2806

DY

1 2

R2812 0R2J-2-GP

2

SCD1U10V2KX-5GP

1 2

DY

U2805

SET GND OUT#3HYST

G709T1UF-GP

74.00709.A7F

VCC

DY

Title

Thermal P2800/Fan Controllor P2793

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

1111 X02 Modify: Reserved G709T1UF for T8 solution sync with DN13.

U2805_5U2805_1

5 4

DY

QUEEN 15

R2801

12

DY

12

U2805_4

DY

0R2J-2-GP

DY

150R2F-1-GP

C2817

C2817 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_DAC_S0

R2810

12

DY

R2811

0R2J-2-GP

12

Hysterisis: 10C for HYST= VCC 2C for HYST=GND

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_DAC_S0

A00 1224

of

28 108

A00

5

SSID = AUDIO

D D

Close to codec

12

C2903

1 2

SC1U6D3V2KX-GP

C C

3D3V_S0

12

R2908

R2908 10KR2J-3-GP

10KR2J-3-GP

AMP_MUTE# AUD_VREFOUT_B HDA_CODEC_BITCLK

12

C2923

SC1U10V2KX-1GP

B B

12

C2907

DY

SC4D7P50V2CN-1GP

For EMI

C2902

C2904

1 2

SCD1U10V2KX-5GP

AUD_DMIC_CLK AUD_DMIC_IN0

12

EC2901

EC2902

SC22P50V2JN-4GP

1122 X02 Modify: change R2920,R2921 to 22ohm from 0ohm and stuff EC2901,EC2902 22p from EMC Neo updated.

HDA_CODEC_SDOUT21 HDA_CODEC_BITCLK21

HDA_SDIN021

HDA_CODEC_SYNC21 HDA_CODEC_RST#21

SCD1U10V2KX-5GP

A00

AUD_DMIC_IN049 AUD_DMIC_CLK49

20101220 R2920 R2921 for change to parallel resistor

1 2 3

SRN22J-7-GP

AUD_PC_BEEP Trace width>15 mils

4

AMP_MUTE#27

Close to codec

AUD_DVDDCORE

12

C2901

C2901 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

AUD_DMIC_CLK_R AUD_DMIC_IN0_R3D3V_S0 HDA_CODEC_SDOUT HDA_CODEC_BITCLK HDA_CODEC_SDIN0

R2901

1 2

33R2J-2-GP

0707 Modify: updated U2901 part number from data base.

HDA_CODEC_SYNC HDA_CODEC_RST# AUD_PC_BEEP

2010/06/30 Change to 92HD87 (71.92H87.A03)

RN2902

AUD_PC_BEEP

AUD_DMIC_IN0_R

4

AUD_DMIC_CLK_R

C2912 SCD1U10V2KX-5GPC2912 SCD1U10V2KX-5GP C2913 SCD1U10V2KX-5GPC2913 SCD1U10V2KX-5GP

G2901

G2901 DUMMY-C2

DUMMY-C2

1 2

AMP_MUTE#

U2901

1

DVDD_LV

2

DMIC_CLK/GPIO_1

3

DMIC_0/GPIO_2

4

SDATA_OUT

5

BITCLK

6

SDATA_IN

7

DVDD

8

SYNC

9

RESET#

10

PCBEEP

92HD87B1A5NDGXTBX8-GP

12 12

+PVDD

39

38

40

41

EAPD

PVDD

THERMAL_PAD

71.92H87.A03

SENSE_A11SENSE_B12PORTF_L13PORTF_R14PORTC_L15PORTC_R16VREFFILT17CAP218VREFOUT_A19VREFOUT_C

AUD_SENSE_A

AUD_SENSE_B

SB_SPKR_R KBC_BEEP_R

3

AUD_SPK_R+ AUD_SPK_RAUD_SPK_LAUD_SPK_L+

+AVDD

AUD_VREG

33

36

34

37

31

32

35

PVSS

PVDD

AVDD2

PORTD_-L

PORTD_-R

PORTD_+L

PORTD_+R

AUD_PC_BEEP

120KR2J-L-GP

R2910 470KR2J-2-GPR2910 470KR2J-2-GP

AUD_CAP2

AUD_VREFFLT

R2909

1 2 1 2

VREG/+2_5V

PORTB_R

PORTA_R

20

AUD_VREFOUT_B

CAP+

CAP-

AVSS2

PORTB_L

AVSS2

PORTA_L

AVDD1

From SB

From EC

AUD_SPK_R+ 58 AUD_SPK_L- 58

30 29 28

V-

27 26 25 24 23 22 21

HDA_SPKR 21

KBC_BEEP 27

AUD_SPK_R- 58 AUD_SPK_L+ 58

PUMP_CAPP

PUMP_CAPN AUD_V_B

AUD_HP1_JACK_R AUD_HP1_JACK_L

AUD_EXT_MIC_R AUD_EXT_MIC_L

+AVDD

C2905

1 2

SCD1U10V2KX-5GP

C2914

C2914 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

1 2

R2906 60D4R2F-GPR2906 60D4R2F-GP

1 2

R2905 60D4R2F-GPR2905 60D4R2F-GP

1 2

C2922 SC1U10V3KX-3GPC2922 SC1U10V3KX-3GP C2921 SC1U10V3KX-3GPC2921 SC1U10V3KX-3GP

Put C2921 and C2922 close to codec

0707 Modify: Change R2911,R2914,R2917 change to 0ohm 0603 from short pad. 0726 Modify: Removed all of AUD_AGND and R2911,R2914,R2917.

2

R2902

1 2

0R0603-PAD

C2906

SC1U10V2KX-1GP

0R0603-PAD

12

CLOSE TO CODEC

12 12

5V_S0 +PVDD

1 2

AUD_HP1_JACK_R2 82

AUD_HP1_JACK_L2 82 MIC_IN_R 82

MIC_IN_L 82

12

C2908

SCD1U10V2KX-5GP

AUD_CAP2 AUD_VREFFLT AUD_V_B AUD_VREG

12

C2909

SC1U10V2KX-1GP

12

C2917

1

1 2

C2910

SC4D7U6D3V3KX-GP

1 2

SC10U6D3V5MX-3GP

12

C2918

SC10U6D3V5MX-3GP

R2903

R2903 0R0603-PAD

0R0603-PAD

R2904

R2904 0R0603-PAD

0R0603-PAD

12

Close to codec

0719 Modify: Move RN2901 to closed AUDIO CODEC from speaker connector.

0,&,1

AUD_VREFOUT_B

1

23

RN2901

SRN4K7J-8-GP

4

5V_S0

12

C2915

C2916

SC10U6D3V5MX-3GP

SC1U6D3V2KX-GP

$]DOLD,)(0,

HDA_CODEC_SDOUT

12

R2912

R2912 47R2J-2-GP

47R2J-2-GP

DY

PCH_AZ_CODEC_SDOUT1

A A

12

C2920

DY

SCD1U10V2KX-5GP

5

AUD_SENSE_A

+AVDD

12

R2915

R2915 2K49R2F-GP

2K49R2F-GP

12

C2919

C2919 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

Close to Pin13

4

R2913

1 2

20KR2F-L-GP

R2919

39K2R2F-L-GP

AUD_HP1_JD# 82

AUD_SENSE_B

12

EXT_MIC_JD# 82

Close to Pin14

3

+AVDD

12

R2916

R2916 2K49R2F-GP

2K49R2F-GP

R2918

R2918 20KR2F-L-GP

20KR2F-L-GP

2

MIC_IN_L82

MIC_IN_R82

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Audio Codec 92HD87B1

Taipei Hsien 221, Taiwan, R.O.C.

QUEEN 15

of

29 108Tuesday, January 04, 2011

1

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

QUEEN 15

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

30 108Tuesday, January 04, 2011

A00