WinSystems PCM-A/D-16, PCM-A/D-12 Operation Manual

OP ERA TIONS MAN UAL

PCM-A/D-16
PCM-A/D-12

Win Sys tems re serves the right to make changes in the cir cuitry

© Copy right 1996 by Win Sys tems. All Rights Re served.

and speci fi ca tions at any time with out no tice.

WinSystems - "The Embedded Systems Authority"

RE VI SION HIS TORY

P/N 403- 0230- 000

ECO Num ber Date Code Rev Level
Origi nated 960206 B

97- 31 970513 B1

TA BLE OF CON TENTS

Sec tion Para graph Page
Num ber Ti tle Num ber

1 Gen eral In for ma tion

1.1 Fea tures 1-1

1.2 Gen eral De scrip tion 1-1

1.3 Speci fi ca tions 1-2
2 PCM-A/D Tech ni cal Ref er ence

2.1 In tro duc tion 2-1

2.2 I/O Ad dress Se lec tion 2-2

2.3 In ter rupt Rout ing 2-2

2.4 DC- DC Con verter Se lec tion 2-3

2.5 Mode Se lec tion 2-3

2.6 In put Con nec tor Pin Defi ni tions 2-8

2.7 PC/104 Bus Pin Defi ni tions 2-8

2.8 Con nec tor/Jumper Sum mary 2-9
3 PCM-A/D Pro gram ming Ref er ence

3.1 I/O Reg is ter Defi ni tions 3-1

3.2 Con ver sion Tech niques 3-4

3.3 PCM-A/D Dem on stra tion Pro gram 3-5

3.4 Cali bra tion Pro ce dures 3-7
AP PEN DIX A PCM-A/D Parts Place ment Guide
AP PEN DIX B PCM-A/D Parts List
AP PEN DIX C BURR- BROWN ADS7806/ADS7807 Da tasheet Re print
AP PEN DIX D PCM-A/D Demo Soft ware Source List ing
AP PEN DIX E PCM-A/D Sche matic Dia grams

1 GENERAL INFORMATION

1.1 Features

n Low Power/Low Cost PC/104 A/D Con verter Mod ule
n 16 Sin gle ended or 8 Dif fer en tial in put chan nels
n Avail able in 12- Bit or 16- Bit mod els
n 30uS Auto Con ver sion Time
n In ter rupt avail able on end of con ver sion
n In put ranges of 0-5V and +/-10V
n Out put for mat in straight Bi nary or Signed two's com ple ment Bi nary
n Ex tended in dus trial op er at ing tem pera ture range
n Op tional DC/DC con verter for +5V only op era tion

1.2 General Description

The PCM-A/D-16 and PCM-A/D-12 are low cost, gen eral pur pose, suc ces sive ap proxi ­ma tion analog- to- digital con vert ers. The PCM-A/D-16 uses the Burr- Brown ADS7807 16­ bit con verter while the PCM-A/D-12 uses the Burr- Brown ADS7806 12- bit con verter. Ap ­pen dix C con tains the da tasheet re prints on these com po nents.

The PCM-A/D sup ports 16 chan nels in a uni po lar 5V range, or a bi po lar +/-10 volt
range. Al ter nately 8 chan nels of dif fer en tial in put is sup ported in a 5 volt or 10 volt ran ge.
Re peti tive chan nel con ver sion time is 25uS and ran dom chan nel ac cess time is 30uS. The
end of con ver sion can be de ter mined via soft ware poll ing or by an in ter rupt to the CPU.

970513 PCM-A/D-12/16 OPERATIONS MANUAL Page 1-1

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1.3 Specifications

1.3.1 Electrical

Bus In ter face : PCM-A/D- XX-8 PC/104 8- Bit stack through
PCM-A/D- XX- 16 PC/104 16- Bit stack through

Power re quire ments :
+5V +/- 5% at 200mA typ. with DC- DC con verter in stalled

15mA typ. w/o DC- DC con verter in stalled

+12V +/-5% at 5mA typ. w/o DC- DC con verter in stalled

-12V +/-5% at 5mA typ. w/o DC- DC con verter in stalled

1.3.2 Mechanical

Di men sions : 3.6" X 3.8" X 0.6"
PC Board : FR4 Ep oxy glass with 2 sig nal lay ers and 2 power planes with screened

com po nent leg end and plated through holes.
Jump ers : 0.025" square posts on 0.10" cen ters.
Con nec tors :

Ana log in put : 16- pin 0.10" grid RN type IDH- 26- LP

1.3.3 Environmental

Op er at ing Tem pera ture : -40° C to +85° C
Non- condensing rela tive hu mid ity : 5% to 95%

Page 1-2 PCM-A/D-12/16 OPERATIONS MANUAL 970513

2 PCM-A/D Technical Reference

2.1 Introduction

This sec tion of the man ual is in tended to pro vide suf fi cient in for ma tion re gard ing con ­figu ra tion and us age of the PCM-A/D-16 and PCM-A/D-12 mod ules. Win Sys tems main ­tains a Tech ni cal Sup port Group to help an swer ques tions re gard ing con figu ra tion and
pro gram ming of the board. For an swers to ques tions not ade quately ad dressed in this man ­ual con tact Tech ni cal Sup port at (817) 274- 7553 be tween 8AM and 5PM Cen tral Time.
Tech ni cal Sup port may also be re quested by FAX at (817) 548- 1358.

The PCM-A/D has 16 single- ended in puts or 8 dif fer en tial in puts and con verts in 25­ 30uS. The end of con ver sion can be de ter mined in any of three ways. A soft ware timed de ­lay of 30- 35uS can be used, the status reg is ter can be polled, or an end of con ver sion in ter ­rupt can be used.

2.2 I/O Address Selection

J9

1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16
17 o o 18
19 o o 20
21 o o 22

I/O Address
Select Jumper J8

Interrupt Routing
Jumper J9

J8

1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16

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The PCM-A/D uses four con secu tive I/O ad dresses with the base ad dress de ter mined by

the set ting of the jump ers on J8. Each po si tion on the J8 jumper cor re sponds to an ad dress
bit. A jumper in stalled matches a '0' in the ad dress and a jumper left open matches a '1' in
the ad dress. The il lus tra tion be low shows the re la tion ship be tween jumper po si tions and
ad dress bits and also shows the cor rect jump er ing for a base I/O ad dress of 110H.

J8

A9

1 o o 2

A8

3 o o 4

A7

5 o o 6

A6

7 o o 8

A5

9 o o 10

A4

11 o o 12

A3

13 o o 14

A2

15 o o 16

BASE I/O ADDRESS 110H

2.3

Interrupt Routing

The end of con ver sion in ter rupt may be routed to any un used PC/104 in ter rupt line us -

ing the jumper block at J9. The il lus tra tion be low shows the re la tion ship be tween the
jumper po si tion and the in ter rupt se lected. A sam ple jump er ing for IRQ5 is also shown.

J9

IRQ15
IRQ14
IRQ12
IRQ11
IRQ10

IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2

INTERRUPT ROUTING - IRQ5

1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16
17 o o 18
19 o o 20
21 o o 22

Page 2-2 PCM-A/D-12/16 OPERATIONS MANUAL 970513

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2.4 DC-DC Converter Selection

To al low for slightly bet ter line ar ity across the full +/-10V in put range sup ported, an
op tional DC- DC con verter is popu lated at VR1. When in stalled, it pro vides +15V and -15V
to the ana log cir cuitry. This al lows the board to func tion with a +5 volt only sup ply.
Jumper blocks at J2 and J6 are jumpered to route the +12 and -12 volts from the PC/104
bus to the ana log cir cuitry when the DC- DC con verter is not in stalled.

WARN ING : The J2 and J6 jump ers should NEVER be in stalled when the DC- DC con ­verter is in stalled or dam age to the PCM-A/D board, other PC/104 mod ules, the CPU board,
or the power sup ply may re sult. Boards pro vided with DC- DC con vert ers from the fac tory
will not have the jumper posts in stalled at J2 and J6.

2.5 Input Mode Selection

J1

2 4 6

J7

1 o
2 o

o o o
o o o
1 3 5

J5

1 o
2 o
3 o

Mode configuration
jumpers J1, J4, J5, J7

J4

1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16

The PCM-A/D is jumper se lecta ble for one of 4 in put modes. The sup ported modes are.

1. 16 single- ended uni po lar chan nels of 0-5V

2. 16 single- ended bi po lar chan nels of +/-10V

3. 8 dif fer en tial chan nels of 0-5V

4. 8 dif fer en tial chan nels of +/-10V

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2.5.1

Mode 1 - 0-5V Single-Ended Unipolar

This in put mode pro vides for 16 chan nels of 0-5 volt in put range. In no case should the

in put be driven nega tive in this mode. The cor rect jump er ing for this mode is shown be low :

Each chan nel's in put is de liv ered at J3. Ref er to sec tion 2.6 for in put pin defi ni tions.

J1

2 4 6
o o o
o o o
1 3 5

1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16

0-5 Volt - Single-Ended Mode

1 o
2 o
3 o

J7J5J4

1 o
2 o

When used in mode 1, bi nary val ues from 0 to FFF0H (FFFFH) are read from the con -

verter ac cord ing to the fol low ing ta ble.

Full Scale Range: 0.0 - 5.0 Volts
Least Sig nifi cant Bit (LSB) : 76uV (16- Bit)

or 1.22mV (12- Bit)

+Full Scale (FS- 1LSB) : 4.999924V (16- Bit)

or 4.99878V (12- Bit) FFFFH
Mid scale : 2.50V 8000H
One LSB Be low Mid scale : 2.4999924V(16- Bit)

or 2.49878(12- Bit) 7FFFH

-Full Scale : 0.0V 0000H

NOTE : On the PCM-A/D-12 the lower nib ble of the hex value will al ways be 0.

Page 2-4 PCM-A/D-12/16 OPERATIONS MANUAL 970513

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2.5.2

Mode 2 - +/-10V Single-Ended Bipolar

This in put mode pro vides for 16 chan nels of +-10V in put range. The cor rect jump er ing

for this mode is shown be low :

J1

2 4 6
o o o
o o o
1 3 5

1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16

+/-10 Volt - Single Ended Bipolar Mode

1 o
2 o
3 o

J7J5J4

1 o
2 o

Each chan nel's in put is con nected to J3. Ref er to sec tion 2.6 for in put pin defi ni tions.
When used in mode 2, two's com ple ment bi nary val ues from 8000H to 7FFFH are read

from the con verter ac cord ing to the fol low ing ta ble.

Full Scale Range : +/-10.0V
Least Sig nifi cant bit : 305uV (16- Bit)

or 4.88mV (12- Bit)

+Full Scale (FS- 1LSB) : 9.999695V (16- Bit)

or 9.99512 (12- Bit) 7FFFH
Mid scale : 0.0V 0000H
One LSB be low Mid scale : -305uV (16Bit)

or -4.88mV (12- Bit) FFFFH

-Full Scale : -10.0V 8000H

NOTE: On the PCM-A/D-12 the lower nib ble of all hex val ues will be 0.

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2.5.3

Mode 3 - 0-5V Differential

This in put mode pro vides for 8 chan nels of 0- 5volt dif fer en tial in put. The cor rect jump -

er ing for this mode is shown be low :

J1

2 4 6
o o o
o o o
1 3 5

1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16

0-5 Volt - Differential Mode

1 o
2 o
3 o

J7J5J4

1 o
2 o

Each chan nel's in put is con nected to J3. Ref er to sec tion 2.6 for the in put pin defi ni -

tions.

When used in mode 3, bi nary val ues range from 0 to FFFFH as shown in the fol low ing

ta ble.

Full Scale Range : 0.0 - 5.0 Volts
Least Sig nifi cant Bit (LSB) : 76uV (16- Bit)

or 1.22mV (12- Bit)

+Full Scale (FS- 1LSB) : 4.999924V(16- Bit)

or 4.99878V (12- Bit) FFFFH
Mid scale : 2.50V 8000H
One LSB Be low Mid scale : 2.4999924V(16- Bit)

or 2.49878(12- Bit) 7FFFH

-Full Scale 0.0V 0000H

NOTE : On the PCM-A/D-12 the lower nib ble of the hex value will al ways be 0.

Page 2-6 PCM-A/D-12/16 OPERATIONS MANUAL 970513

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2.5.4

Mode 4 - +/-10 Volt differential/Bipolar

This mode pro vides 8 chan nels of dif fer en tial in put with 2 im por tant limi ta tions.

1. The maxi mum dif fer en tial volt age be tween the two legs is 10V.

2. Nei ther in put leg can be, as ref er enced to ground, greater than +10V nor less than -10V.

The jump er ing for this mode is as shown be low :

J1

2 4 6
o o o
o o o
1 3 5

1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16

+/-10 Volt - Differential/Bipolar Mode

1 o
2 o
3 o

J7J5J4

1 o
2 o

Each chan nel's in put volt age is ap plied to J3 as ref er enced in sec tion 2.6. Be sure to use

the dif fer en tial pin defi ni tions when us ing this mode.

Two's com ple ment bi nary val ues are read from the con verter per the fol low ing ta ble.

Full Scale Range : +/-10.0V
Least Sig nifi cant bit : 305uV (16- Bit)

or 4.88mV (12- Bit)

+Full Scale (FS- 1LSB) : 9.999695V (16- Bit)

or 9.99512 (12- Bit) 7FFFH
Mid scale : 0.0V 0000H
One LSB be low Mid scale : -305uV (16Bit)

or -4.88mV (12- Bit) FFFFH

-Full Scale : -10.0V 8000H

NOTE: On the PCM-A/D-12 the lower nib ble of all hex val ues will be 0.

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2.6 Input Connector Pin definitions

In put to the PCM-A/D board is made via J3. When used in the single- ended mode, 16­ channels are avail able and when used in a dif fer en tial mode, 8 chan nels are avail able. The
il lus tra tion be low shows the pin defi ni tions for each case.

J3

1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16
17 o o 18
19 o o 20
21 o o 22
23 o o 24
25 o o 26

CH0­CH1­GND
CH2­GND
CH3­GND
CH4­GND
CH5­GND
CH6­CH7-

2.7

J3

1 o o 2

CH0

3 o o 4

CH1

5 o o 6

GND

7 o o 8

CH2

9 o o 10

GND

11 o o 12

CH3

13 o o 14

GND

15 o o 16

CH4

17 o o 18

GND

19 o o 20

CH5

21 o o 22

GND

23 o o 24

CH6

25 o o 26

CH7

Single-Ended Input Channels

CH8
CH9
GND
CH10
GND
CH11
GND
CH12
GND
CH13
GND
CH14
CH15

PC/104 Bus Pin Definitions

CH0+
CH1+

GND

CH2+

GND

CH3+

GND

CH4+

GND

CH5+

GND
CH6+
CH7+

Differential Input Channels

The PC/104 con nec tors at J10 and J11 are shown here with the sig nal des ig na tions.

GND

RESET

+5V

IRQ9

-5V

DRQ2

-12V

0WS

+12V

GND

MEMW

MEMR

IOW

IOR

DACK3

DRQ3

DACK1

DRQ1

REFRESH

SYSCLK

IRQ7
IRQ6
IRQ5
IRQ4
IRQ3

DACK2

TC

BALE

+5V

OSC
GND
GND

B1 o o A1
B2 o o A2
B3 o o A3
B4 o o A4
B5 o o A5
B6 o o A6
B7 o o A7
B8 o o A8
B9 o o A9
B10 o o A10
B11 o o A11
B12 o o A12
B13 o o A13
B14 o o A14
B15 o o A15
B16 o o A16
B17 o o A17
B18 o o A18
B19 o o A19
B20 o o A20
B21 o o A21
B22 o o A22
B23 o o A23
B24 o o A24
B25 o o A25
B26 o o A26
B27 o o A27
B28 o o A28
B29 o o A29
B30 o o A30
B31 o o A31
B32 o o A32

IOCHK
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
GND

GND

SBHE

LA23
LA22
LA21
LA20
LA19
LA18
LA17

MEMR

MEMW

SD8

SD9
SD10
SD11
SD12
SD13
SD14
SD15

KEY

C0 o o D0
C1 o o D1
C2 o o D2
C3 o o D3
C4 o o D4
C5 o o D5
C6 o o D6
C7 o o D7
C8 o o D8
C9 o o D9
C10 o o D10
C11 o o D11
C12 o o D12
C13 o o D13
C14 o o D14
C15 o o D15
C16 o o D16
C17 o o D17
C18 o o D18
C19 o o D19

GND
MEMCS16
IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DACK0
DRQ0
DACK5
DRQ5
DACK6
DRQ6
DACK7
DRQ7
+5V
MASTER
GND
GND

Page 2-8 PCM-A/D-12/16 OPERATIONS MANUAL 970513

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2.8 Connector/Jumper Summary

Con nec tor/ De scrip tion Page
Jumper Ref er ence

J1 Mode Se lect, dif fer en tial or single- ended 2-3
J2 DC- DC Con verter En able 2-3
J3 Ana log in put con nec tor 2-8
J4 In put range se lect jumper 2-3
J5 Mode se lect, dif fer en tial vs. single- ended 2-3
J6 DC- DC Con verter En able 2-3
J7 Mode Se lect, bi nary vs. two's com ple ment 2-3
J8 I/O Ad dress Se lect 2-2
J9 In ter rupt Rout ing Se lect 2-2
J10 PC/104-8 Con nec tor 2-8
J11 PC/104- 16 Con nec tor 2-8

970513 PCM-A/D-12/16 OPERATIONS MANUAL Page 2-9

3 PCM-A/D Programming Reference

3.1 I/O Register Definitions

The PCM-A/D uses 4 con secu tive I/O ad dresses be gin ning with a base ad dress se lected
via jumper block J8. See Sec tion 2.1 for I/O ad dress se lec tion de tails. The four al lo cated I /O
ad dresses are used as shown here :

AD DRESS Write Reg is ter Read Reg is ter

—————————————————————————————————————-

BASE Chan nel Se lect Status Reg is ter

BASE+1 Chan nel Se lect/Con ver sion Start LSB Data

BASE+2 Con ver sion Start Only MSB Data

BASE+3 Re served Re served

Each Reg is ter will be ex am ined in more de tail.

3.1.1 Base Address

Write Reg is ter - Chan nel Se lect

D7 - N/A
D6 - N/A
D5 - N/A
D4 - N/A
D3 - Bit 3 of se lect nib ble
D2 - Bit 2 of se lect nib ble
D1 - Bit 1 of se lect nib ble
D0 - Bit 0 of se lect nib ble

Writ ing a value to the BASE I/O port will cause the on board mul ti plex ers to se lect a new
in put chan nel. The chan nel number se lected is the bi nary value of the lower 4 bits. No con ­ver sion is started and a de lay of ap proxi mately 6uS for mul ti plexer set tling is re quired be f ­ore be gin ning a con ver sion.

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Read Reg is ter - Con ver sion Status

D7 - N/A
D6 - N/A
D5 - N/A
D4 - N/A
D3 - N/A
D2 - N/A
D1 - Busy 0 = Con verter busy, 1 = Con ver sion com plete
D0 - In ter rupt 0 = Con ver sion in prog ress, 1 = Con ver sion com plete

This status reg is ter in di cates when a con ver sion is com plete. It is rec om mended that

soft ware rou tines wait un til both the Con ver sion com plete and the In ter rupt bits are both
set bef ore read ing the con ver sion data.

3.1.2 Base + 1 Address

Write Reg is ter - Se lect Chan nel/Start Con ver sion

D7 - N/A
D6 - N/A
D5 - N/A
D4 - N/A
D3 - Bit 3 of se lect nib ble
D2 - Bit 2 of Se lect nib ble
D1 - Bit 1 of se lect nib ble
D0 - Bit 0 of se lect nib ble

Writ ing a value to the BASE + 1 I/O ad dress not only se lects the chan nel number as en -

coded in bits 3-0 but af ter a hard ware set tling de lay of ap proxi mately 6uS starts a con ver ­sion. This is the nor mal method to be gin a con ver sion as the chan nel se lec tion and
con ver sion start are auto mated into a sin gle write.

Read Reg is ter - LSB Data

D7 - D7 of con ver sion data
D6 - D6 “ ” “
D5 - D5 “ ” “
D4 - D4 “ ” “
D3 - D3 “ ” “
D2 - D2 “ ” “
D1 - D1 “ ” “
D0 - D0 “ ” “

Read ing of I/O base ad dress + 1 will pres ent the lower 8- bits of the 16- bit con ver sion

data. Note that on the 12- Bit con verter mod ule, the lower 4 bits of this reg is ter will al ways
read as 0. This al lows soft ware to trans par ently use ei ther the 12- bit or the 16- bit mod ule .

Page 3-2 PCM-A/D-12/16 OPERATIONS MANUAL 970513

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Note that the data is only valid if both the BUSY and IN TER RUPT bits are both set to 1 in
the status reg is ter.

3.1.3 Base + 2 Address

Write Reg is ter - Start Con ver sion

D7 = N/A
D6 = N/A
D5 = N/A
D4 = N/A
D3 = N/A
D2 = N/A
D1 = N/A
D0 = N/A

A write to this reg is ter with any value will start the A/D con verter on what ever chan nel
was pre vi ously se lected by the Chan nel Se lect Reg is ter or the Chan nel Se lect/Start Con ver ­sion reg is ter. This method of start ing the con verter al lows for maxi mum through put when
re peti tively con vert ing on the same chan nel as no mul ti plexer set tling time is re quired.

Read Reg is ter - MSB Data

D7 = D15 of con ver sion data
D6 = D14 “ ” “
D5 = D13 “ ” “
D4 = D12 “ ” “
D3 = D11 “ ” “
D2 = D10 “ ” “
D1 = D9 “ ” “
D0 = D8 “ ” “

Read ing from this reg is ter gives the up per 8- bits of the 16- bit con ver sion data. This data
is only valid if both the BUSY and IN TER RUPT bits are set to 1 in the status reg is ter.

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3.2 Conversion Techniques

The PCM-A/D can be pro grammed in any lan guage sup port ing port I/O in struc tions.

The code snip pet be low is in the 'C' lan guage and dem on strates a sim ple func tion that takes
as an ar gu ment the chan nel number and re turns a 16- bit un signed value cor re spond ing to
the cur rent con ver sion value. The next sec tion de scribes a sam ple/test/cali bra tion pro gram
in cluded with the PCM-A/D board both in ex ecu ta ble and source form.

#de fine BASE_AD DRESS 0x110

un signed con vert(int chan nel_number)
{
un signed re turn_value;

/* Start the con ver sion by writ ing to the Se lect/Start con ver sion Reg is ter */
out portb(BASE_AD DRESS + 1, chan nel_number);
/* Now wait for the con ver sion to com plete */
while((in portb(BASE_AD DRESS) & 0x03) != 3)

;
/* Now read out the 2 bytes that make up the value */
re turn_value = in portb(BASE_AD DRESS + 2);

/* Shift the MSB value up 8 bits in prepa ra tion for the LSB */
re turn_value = re turn_value < 8;
/* Read the LSB value and 'OR' it into the pre pared MSB value */
re turn_value = re turn_value | in portb(BASE_AD DRESS + 1);
re turn re turn_value;

}

Page 3-4 PCM-A/D-12/16 OPERATIONS MANUAL 970513

WinSystems - "The Embedded Systems Authority"

3.3 PCM-A/D Demonstration Program

In cluded on a 3 1/2" disk ette with the PCM-A/D board is a sam ple pro gram in both 'C'
source code and in MS- DOS ex ecu ta ble for mat. The PCMAD12.EXE file was cre ated us ing
Bor land C/C++ Ver sion 3.1. This demo pro gram may be used as a di ag nos tic/cali bra tion
pro gram or por tions of its source code may be used in a user's ap pli ca tion pro gram. The pro ­gram's source code dem on strates both in ter rupt driven and polled- mode con verter tech ­niques. PCMAD12.EXE is exe cuted from the MS- DOS com mand line with:

PCMAD12 <En ter>

A screen dis play like that shown be low should be dis played and the in ter rupt coun ter in
the lower right cor ner should be count ing con ver sions.

Chan nel RAW HIGH LOW DATA CUR RENT MAX MIN VOLT A GE

Num ber DATA DATA DATA DEV. VOLT AGE VOLT AGE VOLT AGE DE VIA TION

——————————————————————————-—————————————————-

00 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

01 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

02 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

03 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

04 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

05 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

06 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

07 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

08 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

09 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

10 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

11 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

12 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

13 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

14 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

15 FFFF FFFF FFFF 0000 5.0000 5.0000 5.0000 0.0000

—————————————————————————---—————————————————

'T' Tog gle Scale, 'B' Con verter tog gle 'M' In ter rupt Mode tog gle, 'R' Re set Val ues

————————————————————---——————————————————————-

Scale : +0 to +5 Volts - Single- Ended 12- Bit In ter rupt Mode 34256

NOTE: The PCMAD12.EXE pro gram as sumes that a base ad dress of 110H has been se ­lected and the IRQ5 is also se lected. Ref er to Sec tion 2 of this man ual for hard ware se lec ­tion de tails.

970513 PCM-A/D-12/16 OPERATIONS MANUAL Page 3-5

WinSystems - "The Embedded Systems Authority"

There are 5 key strokes rec og nized by PCMAD12.EXE. They are as fol lows :
'T' - Tog gles the in put mode through the 4 sup ported modes :

+0 to +5 Volts - Sin gle Ended

-10 to +10 Volts - Sin gle Ended
+0 to +5 Volts - Dif fer en tial

-10 to +10 Volts - Dif fer en tial

NOTE : Press ing 'T' only changes the soft ware's in ter pre ta tion of the mode be ing used.

The val ues dis played will be mean ing less in any mode ex cept for the one for which the
board has been jumpered for.

'B' - Tog gles the con verter type be tween 12- bit and 16- bit.
'M ' - Tog gle the con ver sion mode

This key tog gles the con ver sion mode be tween “In ter rupt Mode” and “Polled Mode”.

When in the “In ter rupt Mode” a coun ter in the lower right cor ner will dis play the number
of in ter rupts re ceived since the last 'M', 'T', or 'R' com mand.

'R' - Re set Val ues
Press ing the 'R' key re sets the High, Low and De via tion val ues to 0. This may be de sir -

able af ter chang ing modes or in put volt ages to check the sta bil ity of the PCM-A/D or the in ­put source.

'E SCAPE' - Exit to DOS
Press ing 'E SCAPE' will un hook the cur rent in ter rupt vec tors and re turn the sys tem to

the DOS prompt.

Page 3-6 PCM-A/D-12/16 OPERATIONS MANUAL 970513

WinSystems - "The Embedded Systems Authority"

3.4 Calibration Procedures

1. Jumper the board for 0-5 Volt Single- Ended Mode. Base Ad dress 110H and IRQ5.

2. Run the PCMAD12.EXE pro gram.

3. Ap ply a pre ci sion (+/-1.5mV) in put source to chan nel 0. Set the source to 0.00V

4. Turn R3 and R4 pots full clock wise. Clear val ues by press ing the 'R' key.

5. Ad just R3 slowly counter- clockwise for a sta ble zero volt age read ing on chan nel 0. Ig nore other chan -

nel val ues.

6. Set the pre ci sion in put source to 4.99 volts and again clear cur rent val ues by press ing th e 'R' key.

7. Ad just R4 counter- clockwise for a read ing cor re spond ing to the in put source. Some lower b it de via tion

may be ex pe ri enced and is nor mal.

8. Set the in put source to 5.00 volts. Hit 'R' to clear the cur rent val ues. Look for a solid 5.0 0 Volt read ing.
If the dis play is not sta ble at 5.00V, re peat steps 3 through 8. If the value can not be sta bi lized af ter re peat ing
the steps, slowly turn R4 clock wise up to one full turn to achieve ac cept able re sults. Turn ing be yond this
point will de stroy board line ar ity. If the volt ages can not be sta bi lized the board is not fu nc tion ing prop erly and
will need to be re paired.

970513 PCM-A/D-12/16 OPERATIONS MANUAL Page 3-7

4 APPENDIX A

PCM-A/D Parts Place ment Guide

5 APPENDIX B

PCM-A/D Parts List

07/06/00 BOM for Manuals PAGE 1
08:04:44 WinSystems, Inc.
ASSM ITEM FROM: PCM-A/D12-16 ASSM ITEM THRU: PCM-A/D12-16
PARENT LOC FROM: <FIRST> DEFAULT COMPONENT LOCATION: ARLIN PARENT LOC THRU: <LAST>
===================================================================================================================================
ITEM QTY
LVL ITEM KEY ITEM DESCRIPTION BOM COMMENT TYPE REQUIRED
===================================================================================================================================
PCM-A/D12-16 PC/104, 12-BIT A/D CONVERTER PC/104, 12-BIT A/D CONVERTER F 1.0
1 999-9999-001 SPECIAL NOTES 11-30-95 MEB (NEW) I 1.0
1 0230-200-0000 ASSY PCM-A/D12-16 REV.B1 ASSY PCM-A/D12-16 REV.B1 F 1.0
2 CONTRACT LABOR OUTSIDE CONTRACT LABOR OUTSIDE CONTRACT LABOR L 3.0
2 999-9999-001 SPECIAL NOTES 01-08-96 MEB ECBOM(U1,U3 P/N) I 1.0
2 999-9999-001 SPECIAL NOTES 10-03-95 MEB ECO 95-89 I 1.0
2 999-9999-001 SPECIAL NOTES 08-15-95 MEB ECO 95-75 I 1.0
2 999-9999-001 SPECIAL NOTES 08-15-95 MEB ECBOM I 1.0
2 603-1047-803 CAP .1uF 50v 20% CER 0805 C1,C3,C4,C5,C7,C11,C12,C13,C14,C15,C17, I 15.0
2 999-9999-001 SPECIAL NOTES C18,C19,C21,C22 I 1.0
2 603-1065-82D CAP 10uF 25v 20% TAN 6032 C2,C8,C10,C16,C24 I 5.0
2 603-2255-72B CAP 2.2uF 25v 10% TAN 3528 C6,C9 I 2.0
2 603-1027-703 CAP 1000pF 50v 10% CER 0805 C20,C23,C25 I 3.0
2 124-0006-000 DIODE BAT47/BAT48 D1 I 1.0
2 121-0103-050 RN SIP 9P 8 RES 10K L091S103 (BKMN) RP1 I 1.0
2 113-0503-201 POT 50K 15 TURN BECKMAN 64ZR50K R3,R4 I 2.0
2 601-0333-503 RES 33K Ohm 5% 1/10w 0805 R6 I 1.0
2 601-0201-503 RES 200 Ohm 5% 1/10w 0805 R7 I 1.0
2 601-0101-503 RES 100 Ohm 5% 1/10w 0805 R8,R9 I 2.0
2 601-0105-503 RES 1M Ohm 5% 1/10W 0805 R10 I 1.0
2 601-0100-507 RES 10 Ohm 5% 1w 2512 R11,R12 I 2.0
2 601-0103-503 RES 10K Ohm 5% 1/10W 0805 R13,R14 I 2.0
2 601-0102-503 RES 1K Ohm 5% 1/10W 0805 R16 I 1.0
2 601-0222-503 RES 2.2K Ohm 5% 1/10w 0805 R15 I 1.0
2 200-0163-100 SOCKET 16 PIN 316-AG19DC (1040) U1,U3 I 2.0
2 200-0083-100 SOCKET 8 PIN 308-AG19DC (2080) U2 I 1.0
2 200-0328-100 SOCKET, 28 P .3 PRCICNTC LT0328TBB (17) U4 I 1.0
2 611-0175-002 IC, 74HC175D S0-16 U5 I 1.0
2 200-0243-100 SOCKET 24 P .3 324-AG19DC (425) U6 I 1.0
2 612-0245-002 IC, 74HCT245DW (SM) U7 I 1.0
2 611-0221-002 IC, 74HC221D SO-16 U8 I 1.0
2 612-0688-002 IC, 74HCT688AF (SM) U9 I 1.0
2 200-0064-100 SCKT 64 POS STK QPHF2-64-020-1Z (PLAST) J10 CLIP PIN B10, MUST BE HAND SOLDERED I 1.0
2 200-0040-100 SCKT 40 POS STK QPHF2-40-020-1Z (PLSTRN) J11 CLIP PIN C19, MUST BE HAND SOLDERED I 1.0
2 201-0072-120 HDR 2X36 UN TSW-136-07-G-D J1=2X3 J4,J8=2X8 J9=2X11 I .8
2 201-0036-010 HDR 1X36 UN TSW-136-07-G-S (SAM) J2,J6,J7=2X1 J5=1X3 I .2
2 201-0026-121 HDR 26 P RA 636-2607 (2500) J3 I 1.0
2 400-0230-000B PCB, PCM-A/D12 REV.B PCB, PCM-A/D12 REV.B I 1.0
2 999-9999-001 SPECIAL NOTES MASK THE FOLLOWING: R1,R2,R5,VR1 I 1.0

----------------------------------------------------------------------------------------------------------------------------------­SUB-ASSEMBLY TOTAL: 0230-200-0000 ARLIN - 36 Items

----------------------------------------------------------------------------------------------------------------------------------­ 1 0230-300-0000 SUB ASSY PCM-A/D12 REV.B SUB ASSY PCM-A/D12 REV.B F 1.0
2 999-9999-001 SPECIAL NOTES 08-15-95 MEB ECO 95-75 I 1.0
2 999-9999-001 SPECIAL NOTES 08-15-95 MEB ECBOM I 1.0
2 730-0085-000 IC, INA111AP BURR-BROWN U2 I 1.0

07/06/00 BOM for Manuals PAGE 2
08:04:45 WinSystems, Inc.
ASSM ITEM FROM: PCM-A/D12-16 ASSM ITEM THRU: PCM-A/D12-16
PARENT LOC FROM: <FIRST> DEFAULT COMPONENT LOCATION: ARLIN PARENT LOC THRU: <LAST>
===================================================================================================================================
ITEM QTY
LVL ITEM KEY ITEM DESCRIPTION BOM COMMENT TYPE REQUIRED
===================================================================================================================================
2 730-0005-000 IC, DG408DJ (Harris) (Siliconix) U1,U3 I 2.0
2 730-0086-000 IC, ADS7806P (13) BURR-BROWN U4 I 1.0
2 901-0011-000 IC, PALC22V10-35PC (15,TI) (17,CYP) U6 CS=8D0E \SPRINT\PCMAD12\_____\ I 1.0
2 201-0002-000 PLUG JUMPER 999-19-310-00 J1=1-2 5-6 I 16.0
2 999-9999-001 SPECIAL NOTES J2=1-2 I 1.0
2 999-9999-001 SPECIAL NOTES J4=3-4 7-8 11-12 15-16 I 1.0
2 999-9999-001 SPECIAL NOTES J5=3-4 I 1.0
2 999-9999-001 SPECIAL NOTES J6=1-2 I 1.0
2 999-9999-001 SPECIAL NOTES J8=1-2 5-6 7-8 9-10 13-14 15-16 I 1.0
2 999-9999-001 SPECIAL NOTES J9=15-16 I 1.0
2 KIT-PCM-STANDOFF-2 PC/104 STANDOFF KIT CONSISTING OF 2 ** DO NOT SEND TO ASSY ** F 1.0
3 CONTRACT LABOR OUTSIDE CONTRACT LABOR L .1
3 999-9999-001 SPECIAL NOTES 04-28-95 MEB (NEW BOM) I 1.0
3 500-0200-091 SPACER M/F RAF 4000-440-N-MODL.600 SPACER M/F RAF 4000-440-N-MODL.600 I 2.0
3 500-0200-033 SCREW PPH 4-40 X 1/4" SCREW PPH 4-40 X 1/4" I 2.0
3 500-0200-092 NUT HEX NYLON 4-40 NUT HEX NYLON 4-40 I 2.0

3 525-0304-001 SIZE 3 COIN ENVLPE 2.5" X 4.25" 50260 SIZE 3 COIN ENVELOPE 2 1/2 X 4 1/4 I 1.0

----------------------------------------------------------------------------------------------------------------------------------­SUB-ASSEMBLY TOTAL: KIT-PCM-STANDOFF-2 ARLIN - 6 Items

-----------------------------------------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------------------------------------------­SUB-ASSEMBLY TOTAL: 0230-300-0000 ARLIN - 14 Items

----------------------------------------------------------------------------------------------------------------------------------­ 1 910-0024-000 LABEL, STATIC SENSITIVE 130-02 LABEL, STATIC SENSITIVE 130-02 I 1.0
1 950-0001-000 BAG STATIC BARRIER 07-0610 6X10 BAG STATIC BARRIER 07-0610 I 1.0
1 KIT-PCM-STANDOFF-2 PC/104 STANDOFF KIT CONSISTING OF 2 PC/104 STANDOFF KIT CONSISTING OF 2 F 1.0
2 CONTRACT LABOR OUTSIDE CONTRACT LABOR L .1
2 999-9999-001 SPECIAL NOTES 04-28-95 MEB (NEW BOM) I 1.0
2 500-0200-091 SPACER M/F RAF 4000-440-N-MODL.600 SPACER M/F RAF 4000-440-N-MODL.600 I 2.0
2 500-0200-033 SCREW PPH 4-40 X 1/4" SCREW PPH 4-40 X 1/4" I 2.0
2 500-0200-092 NUT HEX NYLON 4-40 NUT HEX NYLON 4-40 I 2.0
2 525-0304-001 SIZE 3 COIN ENVLPE 2.5" X 4.25" 50260 SIZE 3 COIN ENVELOPE 2 1/2 X 4 1/4 I 1.0

----------------------------------------------------------------------------------------------------------------------------------­SUB-ASSEMBLY TOTAL: KIT-PCM-STANDOFF-2 ARLIN - 6 Items

----------------------------------------------------------------------------------------------------------------------------------­===================================================================================================================================
TOP ASSEMBLY TOTAL: PCM-A/D12-16 ARLIN - 6 Items
===================================================================================================================================

REPORT RECAP

-----------­ 0 WARNING(S)

07/06/00 BOM for Manuals PAGE 3
08:04:45 WinSystems, Inc.
ASSM ITEM FROM: PCM-A/D12-16 ASSM ITEM THRU: PCM-A/D12-16
PARENT LOC FROM: <FIRST> DEFAULT COMPONENT LOCATION: ARLIN PARENT LOC THRU: <LAST>
===================================================================================================================================
ITEM QTY
LVL ITEM KEY ITEM DESCRIPTION BOM COMMENT TYPE REQUIRED
===================================================================================================================================
PARAMETER RECAP

--------------­PARAMETER KEY : 10 BOM with Ref. Desc.
REPORT TITLE : BOM for Manuals

ASSM ITEM RANGE : PCM-A/D12-16 THRU PCM-A/D12-16 COSTING METHOD : A
PARENT LOC RANGE : <FIRST> THRU <LAST> QUANTITY TO EXPLODE : 1
PRODUCT KEY RANGE : <FIRST> THRU <LAST> USE SCRAP FACTOR (Y/N) : N
COMMODITY KEY RANGE : <FIRST> THRU <LAST> UPDATE INV STD COST : N
NO. LEVELS TO EXPLODE : 999
DEFAULT COMP LOC : ARLIN COLUMNS OF DESC TEXT : 42
BOM STATUS PRIORITY : A SHORT OR LONG (S/L) : S
PRINT ITEM DESC (Y/N) : Y

6 APPENDIX C

BURR- BROWN ADS7806/ADS7807 Da tasheet Re print

®

ADS7806

Low-Power 12-Bit Sampling CMOS
ANALOG-to-DIGITAL CONVERTER

FEATURES

● 35mW max POWER DISSIPATION

µW POWER DOWN MODE

● 50

µs max ACQUISITION AND

● 25

CONVERSION

±1/2LSB max INL AND DNL

●

● 72dB min SINAD WITH 1kHz INPUT

±10V, 0V TO +5V, AND 0V TO +4V INPUT

●

RANGES

● SINGLE +5V SUPPLY OPERATION

● PARALLEL AND SERIAL DATA OUTPUT

● PIN-COMPATIBLE WITH 16-BIT ADS7807

● USES INTERNAL OR EXTERNAL

REFERENCE

● 28-PIN 0.3" PLASTIC DIP AND SOIC

Clock

R1

R2

40kΩ



IN



IN

10kΩ

CAP

20kΩ

40kΩ

Buffer

CDAC

DESCRIPTION

The ADS7806 is a low-power 12-bit sampling analog­to-digital using state-of-the-art CMOS structures. It
contains a complete 12-bit, capacitor-based, SAR A/D
with S/H, clock, reference, and microprocessor inter­face with parallel and serial output drivers.

The ADS7806 can acquire and convert to full 12-bit
accuracy in 25µs max while consuming only 35mW
max. Laser-trimmed scaling resistors provide standard
industrial input ranges of ±10V and 0V to +5V. In
addition, a 0V to +4V range allows development of
complete single supply systems.

The 28-pin ADS7806 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –40°C to +85°C temperature range.

Successive Approximation Register and Control Logic

Parallel

Comparator

Serial

Data

and

Out

R/C
CS
BYTE
Power
Down

BUSY
Serial Data

Clock

Serial Data

Parallel Data

8

REF

International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706

Tel: [phone] • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

©

1992 Burr-Brown Corporation PDS-1158C Printed in U.S.A. November, 1994

6kΩ

Internal

+2.5V Ref

Reference
Power
Down

SPECIFICATIONS

ELECTRICAL

At TA = –40°C to +85°C, fS = 40kHz, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 * Bits

ANALOG INPUT

Voltage Ranges ±10, 0 to +5, 0 to +4 V
Impedance (See Table II)
Capacitance 35 * pF

THROUGHPUT SPEED

Conversion Time 20 * µs
Complete Cycle Acquire and Convert 25 * µs
Throughput Rate 40 * kHz

DC ACCURACY

Integral Linearity Error ±0.15 ±0.9 * ±0.45 LSB
Differential Linearity Error ±0.15 ±0.9 * ±0.45 LSB
No Missing Codes
Transition Noise
Gain Error ±0.2 ±0.1 %
Full Scale Error
Full Scale Error Drift ±7 ±5 ppm/°C
Full Scale Error
Full Scale Error Drift Ext. 2.5000V Ref ±0.5 * ppm/°C
Bipolar Zero Error
Bipolar Zero Error Drift ±10V Range ±0.5 * ppm/°C
Unipolar Zero Error

(2)

(3,4)

(3,4)

(3)

(3)

Unipolar Zero Error Drift 0V to 5V, 0V to 4V Ranges ±0.5 * ppm/°C
Recovery Time to Rated Accuracy 2.2µF Capacitor to CAP 1 * ms

from Power Down

(5)

Power Supply Sensitivity +4.75V < VS < +5.25V ±0.5 * LSB

(V

= V

ANA

= VS)

DIG

AC ACCURACY

Spurious-Free Dynamic Range f
Total Harmonic Distortion f
Signal-to-(Noise+Distortion) f
Signal-to-Noise f
Usable Bandwidth

(7)

Full Power Bandwidth (-3dB) 600 * kHz

SAMPLING DYNAMICS

Aperture Delay 40 * ns
Aperture Jitter 20 * ps
Transient Response FS Step 5 * µs
Overvoltage Recovery

(8)

REFERENCE

Internal Reference Voltage No Load 2.48 2.5 2.52 * * * V
Internal Reference Source Current 1 * µA

(Must use external buffer.)

Internal Reference Drift 8 * ppm/°C
External Reference Voltage Range 2.3 2.5 2.7 * * * V

for Specified Linearity

External Reference Current Drain Ext. 2.5000V Ref 100 * µA

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format
Data Coding

V

OL

V

OH

Leakage Current High-Z State, ±5*µA

Output Capacitance High-Z State 15 * pF

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

ADS7806

= V

DIG

= +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.

ANA

ADS7806P, U ADS7806PB, UB

(1)

Guaranteed

* Bits

0.1 * LSB

±0.5 ±0.25 %

Ext. 2.5000V Ref ±0.5 ±0.25 %

±10V Range ± 10 * mV

0V to 5V, 0V to 4V Ranges ±3*mV

= 1kHz, ±10V 80 90 * * dB

IN

= 1kHz, ±10V –90 –80 * * dB

IN

= 1kHz, ±10V 70 73 72 * dB

IN

= 1kHz, ±10V 70 73 72 * dB

IN

130 * kHz

(6)

750 * ns

–0.3 +0.8 * * V

+2.0 VD +0.3V * * V
VIL = 0V ±10 * µA
VIH = 5V ±10 * µA

Parallel 12-bits in 2-bytes; Serial

Binary Two’s Complement or Straight Binary

I

= 1.6mA +0.4 * V

SINK

I

= 500µA+4 * V

SOURCE

V

= 0V to V

OUT

DIG

2

SPECIFICATIONS (CONT)

ELECTRICAL

At TA = –40°C to +85°C, fS = 40kHz, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
DIGITAL TIMING

Bus Access Time R
Bus Relinquish Time R

POWER SUPPLIES

Specified Performance

V

DIG

V

ANA

I

DIG

I

ANA

Power Dissipation V

TEMPERATURE RANGE

Specified Performance –40 +85 * * °C
Derated Performance –55 +125 * * °C
Storage –65 +150 * * °C
Thermal Resistance (

Plastic DIP 75 * °C/W
SOIC 75 * °C/W

NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range is 4.88mV. (2) Typical rms noise at worst case transition. (3) As measured with
fixed resistors shown in Figure 7b. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed
deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5)
This is the time delay after the ADS7806 is brought out of Power Down Mode until all internal settling occurs and the analog input is acquired to rated accuracy.
A Convert Command after this delay will yield accurate results. (6) All specifications in dB are referred to a full-scale input. (7) Usable Bandwidth defined as Full­Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB. (8) Recovers to specified performance after 2 x FS input overvoltage.

θ

)

JA

= V

DIG

= +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.

ANA

ADS7806P, U ADS7806PB, UB

= 3.3kΩ, CL = 50pF 83 * ns

L

= 3.3kΩ, CL = 10pF 83 * ns

L

Must be ≤ V

= V

ANA

DIG

REFD HIGH 23 * mW

PWRD and REFD HIGH 50 * µW

ANA

= 5V, fS = 40kHz 28 35 * * mW

+4.75 +5 +5.25 * * * V
+4.75 +5 +5.25 * * * V

0.6 * mA

5.0 * mA

ABSOLUTE MAXIMUM RATINGS

Analog Inputs: R1IN........................................................................... ±25V

Ground Voltage Differences: DGND, AGND1, and AGND2 .............±0.3V

V

ANA

V

to V

DIG

V

........................................................................................................ 7V

DIG

Digital Inputs .............................................................. –0.3V to V

Maximum Junction Temperature ................................................... +165°C

Internal Power Dissipation ............................................................. 825mW

Lead Temperature (soldering, 10s)................................................ +300°C

R2

........................................................................... ±25V

IN

CAP .................................... V

REF .........................................Indefinite Short to AGND2,

....................................................................................................... 7V

......................................................................................+0.3V

ANA

+0.3V to AGND2 –0.3V

ANA

Momentary Short to V

DIG

ANA

+0.3V

Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr­Brown Corporation recommends that this integrated circuit
be handled and stored using appropriate ESD protection
methods.

ELECTROSTATIC
DISCHARGE SENSITIVITY

ORDERING INFORMATION

MAXIMUM MINIMUM

INTEGRAL SIGNAL-TO- SPECIFICATION

MODEL ERROR (LSB) RATIO (dB) RANGE PACKAGE

ADS7806P ±0.9 70 –40°C to +85°C Plastic DIP
ADS7806PB ±0.45 72 –40°C to +85°C Plastic DIP
ADS7806U ±0.9 70 –40°C to +85°C SOIC
ADS7806UB ±0.45 72 –40°C to +85°C SOIC

LINEARITY (NOISE + DISTORTION) TEMPERATURE

PACKAGE INFORMATION

MODEL PACKAGE NUMBER

PACKAGE DRAWING

ADS7806P Plastic DIP 246
ADS7806PB Plastic DIP 246
ADS7806U SOIC 217
ADS7806UB SOIC 217

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.

(1)

®

3

ADS7806

PIN # NAME I/O DESCRIPTION

DIGITAL

1R1
2 AGND1 Analog Sense Ground.
3R2
4 CAP Reference Buffer Output. 2.2µF tantalum capacitor to ground.

IN

IN

Analog Input. See Figure 7.

Analog Input. See Figure 7.

5 REF Reference Input/Output. 2.2µF tantalum capacitor to ground.
6 AGND2 Analog Ground.
7 SB/BTC I Selects Straight Binary or Binary Two’s Complement for Output Data Format.
8 EXT/INT I External/Inter nal data clock select.
9 D7 O Data Bit 3 if BYTE is HIGH. Data bit 11 (MSB) if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Leave

unconnected when using serial output.
10 D6 O Data Bit 2 if BYTE is HIGH. Data bit 10 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
11 D5 O Data Bit 1 if BYTE is HIGH. Data bit 9 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
12 D4 O Data Bit 0 (LSB) if BYTE is HIGH. Data bit 8 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
13 D3 O LOW if BYTE is HIGH. Data bit 7 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
14 DGND Digital Ground.
15 D2 O LOW if BYTE is HIGH. Data bit 6 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
16 D1 O LOW if BYTE is HIGH. Data bit 5 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
17 D0 O LOW if BYTE is HIGH. Data bit 4 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
18 DATACLK I/O Data Clock Output when EXT/INT is LOW. Data clock input when EXT/INT is HIGH.
19 SDATA O Serial Output Synchronized to DATACLK.
20 TAG I Serial Input When Using an External Data Clock.
21 BYTE I Selects 8 most significant bits (LOW) or 4 least significant bits (HIGH) on parallel output pins.
22 R/C I With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C

enables the parallel output.
23 CS I Internally OR’d with R/C. If R/C is LOW, a falling edge on CS initiates a new conversion. If EXT/INT is LOW, this same

falling edge will start the transmission of serial data results from the previous conversion.
24 BUSY O At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs

have been updated.
25 PWRD I PWRD HIGH shuts down all analog circuitry except the reference. Digital circuitry remains active.
26 REFD I REFD HIGH shuts down the internal reference. External reference will be required for conversions.
27 V
28 V

ANA

DIG

Analog Supply. Nominally +5V. Decouple with 0.1µF ceramic and 10µF tantalum capacitors.

Digital Supply. Nominally +5V. Connect directly to pin 27. Must be ≤ V

ANA

.

TABLE I. Pin Assignments.

PIN CONFIGURATION

1



R1

IN

2

AGND1

3



R2

IN

4

CAP

5

REF

6

AGND2

DGND

D7
D6
D5
D4
D3

7



8



9
10
11
12
13
14

SB/BTC

EXT/INT

ADS7806

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V



DIG



V

ANA

REFD
PWRD
BUSY
CS
R/C
BYTE
TAG
SDATA
DATACLK
D0
D1
D2

ANALOG CONNECT R1INCONNECT R2

INPUT VIA 200Ω VIA 100Ω

IN

RANGE TO TO IMPEDANCE

±10V V
0V to 5V AGND V
0V to 4V V

IN

IN

CAP 45.7kΩ

IN

V

IN

20.0kΩ

21.4kΩ

TABLE II. Input Range Connections. See also Figure 7.

®

ADS7806

4

TYPICAL PERFORMANCE CURVES

A.C. PARAMETERS vs TEMPERATURE

(f

IN

= 1kHz, 0dB)

110
105
100

95
90
85
80
75
70
65
60



–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110

SFDR, SNR, and SINAD (dB)

THD (dB)

–75 –50 –25 0 25 50 75 100 125 150

Temperature (°C)

SFDR

SNR and SINAD

THD

TA = +25°C, fS = 40kHz, V

DIG

= V

= +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.

ANA

FREQUENCY SPECTRUM

(8192 Point FFT; f

0

–20

–40

–60

Amplitude (dB)

–80

–100

–120

0 5 10 15 20

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) 

90
80
70
60
50
40

SINAD (dB)

30
20
10

100 1k 10k 100k 1M

vs INPUT FREQUENCY (f

Input Signal Frequency (Hz)

= 1kHz, 0dB)

IN

= 0dB)

IN

FREQUENCY SPECTRUM

(8192 Point FFT; f

0

–20

–40

–60

–80

Amplitude (dB)

–100

–120

0 5 10 15 20

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY AND INPUT AMPLITUDE

90
80
70
60
50
40

SINAD (dB)

30
20
10

0

02468101214161820

Input Signal Frequency (kHz)

= 15kHz, 0dB)

IN



0dB

–20dB

–60dB



SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE

74.0

73.9

73.8

SINAD (dB)

73.7

73.6
–75 –50 –25 0 25 50 75 100 125 150

= 1kHz, 0dB; fS = 10kHz to 40kHz)

(f

IN

Temperature (°C)

10kHz

40kHz

20kHz

30kHz

®

5

ADS7806

TYPICAL PERFORMANCE CURVES (CONT)

CONVERSION TIME vs TEMPERATURE

15.10

15.00

14.90

14.80

14.70

14.60

14.50

14.40

14.30

14.20


–75 –50 –25 0 25 50 75 100 125 150

Temperature (°C)





Conversion Time (µs)

TA = +25°C, fS = 40kHz, V

0.10

DIG

= V

= +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.

ANA

1

POWER SUPPLY RIPPLE SENSITIVITY

INL/DNL DEGRADATION PER LSB OF P-P RIPPLE

0

12-Bit LSBs

–0.10

12-Bit LSBs
–0.10

All Codes INL

0

Decimal Code

0.10
All Codes DNL

0

0 4095358430722560

Decimal Code

ENDPOINT ERRORS (20V BIPOLAR RANGE)

3

BPZ Error

2
1
0

–1

mV From Ideal

–2

0.20

+FS Error

0

Percent

From Ideal

–0.20

10–1

10–2

204815361024512

204815361024512

30722560

40953584

10–3

10–4

Linearity Degradation (LSB/LSB)

–5

10

1

10

ENDPOINT ERRORS (UNIPOLAR RANGES)

3

UPO Error

2
1
0

–1

mV From Ideal

–2

0.40
+FS Error (4V Range)

0.20

Percent

From Ideal

0

2

10

10

Power Supply Ripple Frequency (Hz)

INL

DNL

3

4

10

5

10

6

10

7

10

0.20
–FS Error

0

Percent

–0.20

From Ideal

–75

–50 –25 0 25

Temperature (°C)

INTERNAL REFERENCE VOLTAGE vs TEMPERATURE

2.520

2.515

2.510

2.505

2.500

2.495



2.490

Internal Reference (V)

2.485

2.480



–75 –50 –25 0 25 50 75 100 125 150

Temperature (°C)

®

ADS7806

50 75 100 125

150

0.40
+FS Error (5V Range)

0.20

Percent

0

From Ideal

–75

–50 –25 0 25

Temperature (°C)

50 75 100 125

150

6

BASIC OPERATION

PARALLEL OUTPUT

Figure 1a) shows a basic circuit to operate the ADS7806
with a ±10V input range and parallel output. Taking R/C
(pin 22) LOW for 40ns (12µs max) will initiate a conver­sion. BUSY (pin 24) will go LOW and stay LOW until the
conversion is completed and the output register is updated.
If BYTE (pin 21) is LOW, the 8 most significant bits will be
valid when BUSY rises; if BYTE is HIGH, the 4 least
significant bits will be valid when BUSY rises. Data will be
output in Binary Two’s Complement format. BUSY going
HIGH can be used to latch the data. After the first byte has
been read, BYTE can be toggled allowing the remaining
byte to be read. All convert commands will be ignored while
BUSY is LOW.

The ADS7806 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com­mands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com­pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).

SERIAL OUTPUT

Figure 1b) shows a basic circuit to operate the ADS7806
with a ±10V input range and serial output. Taking R/C (pin

22) LOW for 40ns (12µs max) will initiate a conversion and

output valid data from the previous conversion on SDATA
(pin 19) synchronized to 12 clock pulses output on
DATACLK (pin 18). BUSY (pin 24) will go LOW and stay
LOW until the conversion is completed and the serial data
has been transmitted. Data will be output in Binary Two’s
Complement format, MSB first, and will be valid on both the
rising and falling edges of the data clock. BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.

The ADS7806 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com­mands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com­pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).

STARTING A CONVERSION

The combination of CS (pin 23) and R/C (pin 22) LOW for
a minimum of 40ns immediately puts the sample/hold of the
ADS7806 in the hold state and starts conversion ‘n’. BUSY
(pin 24) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be
ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without suffi­cient time to acquire a new signal.

Parallel Output

200Ω

±10V

66.5kΩ

2.2µF

+5V

B10 B7

(MSB)

B2 LOW

B9 B8B11

B1 B0B3Pin 21

(LSB)

Pin 21

LOW

HIGH

NOTE: (1) SDATA (pin 19) is always active.

100Ω

2.2µF

++

1
2
3
4
5
6
7



8



9
10
11
12
13
14

ADS7806

28

0.1µF

27
26
25
24
23
22
21
20

(1)

19

NC

18
17
16
15

B6 B5 B4

LOW LOW LOW

+

BYTE

10µF

BUSY



+

R/C

+5V

Convert Pulse

40ns min

FIGURE 1a. Basic ±10V Operation, both Parallel and Serial

Output.

Serial Output

200Ω

±10V

+5V

66.5kΩ

2.2µF

1
2
3

100Ω

4

2.2µF

5

++

6
7

ADS7806



8

(1)





NC

9

(1)



NC

10

(1)



NC

11

(1)



NC

12

(1)

NC

13
14

NOTE: (1) These pins should be left
unconnected.They will be active when
R/C is HIGH.

28

0.1µF

10µF

27

+

26
25
24
23
22
21
20
19
18

(1)

NC

17

(1)

NC

16

(1)

NC

15

+

BUSY

SDATA

DATACLK

+5V

Convert Pulse

R/C

40ns min

FIGURE 1b. Basic ±10V Operation with Serial Output.

®

7

ADS7806

The ADS7806 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com­mands assures accurate acquisition of a new signal. Refer to
Tables III and IV for a summary of CS, R/C, and BUSY
states and Figures 2 through 6 for timing diagrams.

CS R/C BUSY OPERATION

1 X X None. Databus is in Hi-Z state.
↓ 0 1 Initiates conversion “n”. Databus remains

0 ↓ 1 Initiates conversion “n”. Databus enters Hi-Z

01↑Conversion “n” completed. Valid data from

↓ 1 1 Enables databus with valid data from

↓ 1 0 Enables databus with valid data from

0 ↑ 0 Enables databus with valid data from

00↑New conversion initiated without acquisition

X X 0 New convert commands ignored. Conversion

NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion “n-1”.

in Hi-Z state.

state.

conversion “n” on the databus.

conversion “n”.

(1)

conversion “n-1”

conversion “n-1”

of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.

“n” in progress.

. Conversion n in progress.

(1)

. Conversion “n” in progress.

Table III. Control Functions When Using Parallel Output

(DATACLK tied LOW, EXT/INT tied HIGH).

CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input. If EXT/INT
(pin 8) is LOW when initiating conversion ‘n’, serial data
from conversion ‘n-1’ will be output on SDATA (pin 19)
following the start of conversion ‘n’. See Internal Data
Clock in the Reading Data section.

To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output and the serial
output (only when using an external data clock) will be
affected whenever R/C goes HIGH. Refer to the Reading
Data section.

READING DATA

The ADS7806 outputs serial or parallel data in Straight
Binary or Binary Two’s Complement data output format. If
SB/BTC (pin 7) is HIGH, the output will be in SB format,
and if LOW, the output will be in BTC format. Refer to
Table V for ideal output codes.

The parallel output can be read without affecting the internal
output registers; however, reading the data through the serial

CS R/C BUSY EXT/INT DATACLK OPERATION

↓ 0 1 0 Output Initiates conversion “n”. Valid data from conversion “n-1” clocked out on SDATA.
0 ↓ 1 0 Output Initiates conversion “n”. Valid data from conversion “n-1” clocked out on SDATA.
↓ 0 1 1 Input Initiates conversion “n”. Internal clock still runs conversion process.
0 ↓ 1 1 Input Initiates conversion “n”. Internal clock still runs conversion process.

↓ 1 1 1 Input Conversion “n” completed. Valid data from conversion “n” clocked out on SDATA synchronized

↓ 1 0 1 Input Valid data from conversion “n-1” output on SDATA synchronized to external data clock.

0 ↑ 0 1 Input Valid data from conversion “n-1” output on SDATA synchronized to external data clock.

00↑X X New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C

X X 0 X X New convert commands ignored. Conversion “n” in progress.

NOTE: (1) See Figures 4, 5, and 6 for constraints on data valid from conversion “n-1”.

to external data clock.

Conversion “n” in progress.

Conversion “n” in progress.

must be HIGH when BUSY goes HIGH.

Table IV. Control Functions When Using Serial Output.

DESCRIPTION ANALOG INPUT

Full-Scale Range ±10 0V to 5V 0V to 4V
Least Significant Bit (LSB) 4.88mV 1.22mV 976µV

+Full Scale (FS – 1LSB) 9.99512V 4.99878V 3.999024V 0111 1111 1111 1111 7FF 1111 1111 1111 1111 FFF
Midscale 0V 2.5V 2V 0000 0000 0000 0000 000 1000 0000 0000 0000 800
One LSB Below Midscale –4.88mV 2.49878V 1.999024V 1111 1111 1111 1111 FFF 0111 1111 1111 1111 7FF
–Full Scale –10V 0V 0V 1000 0000 0000 0000 800 0000 0000 0000 0000 000

BINARY TWO’S COMPLEMENT STRAIGHT BINARY

(SB/BTC LOW) (SB/BTC HIGH)

BINARY CODE CODE BINARY CODE CODE

DIGITAL OUTPUT

HEX HEX

Table V. Output Codes and Ideal Input Voltages.

®

ADS7806

8

port will shift the internal output registers one bit per data

t

10

BUSY

R/C

MODE

Acquire

Convert

t

11

t

7

t

6

t

3

t

4

t

1

Acquire Convert

t

8

t

6

t

3

Parallel

Data Bus

Previous

High Byte Valid

t

12

Hi-Z Not Valid

t

2

t

9

High Byte

Valid

t

12

t

9

t

12

BYTE

t

1

Previous Low

Byte Valid

Previous High

Byte Valid

Low Byte

Valid

High Byte

Valid

t

12

Hi-Z

t

12

t

12

t

5

clock pulse. As a result, data can be read on the parallel port
prior to reading the same data on the serial port, but data
cannot be read through the serial port prior to reading the
same data on the parallel port.

PARALLEL OUTPUT

To use the parallel output, tie EXT/INT (pin 8) HIGH and
DATACLK (pin 18) LOW. SDATA (pin 19) should be left
unconnected. The parallel output will be active when R/C
(pin 22) is HIGH and CS (pin 23) is LOW. Any other
combination of CS and R/C will tri-state the parallel output.
Valid conversion data can be read in two 8-bit bytes on D7­D0 (pins 9-13 and 15-17) . When BYTE (pin 21) is LOW,
the 8 most significant bits will be valid with the MSB on D7.
When BYTE is HIGH, the 4 least significant bits will be
valid with the LSB on D4. BYTE can be toggled to read both
bytes within one conversion cycle.

Upon initial power up, the parallel output will contain
indeterminate data.

PARALLEL OUTPUT (After a Conversion)

After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13
and 15-17). BUSY going high can be used to latch the data.
Refer to Table VI and Figures 2 and 3 for timing constraints.

PARALLEL OUTPUT (During a Conversion)

After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until BUSY
(pin 24) goes HIGH; this may result in reading invalid data.
Refer to Table VI and Figures 2 and 3 for timing constraints.

FIGURE 2. Conversion Timing with Parallel Output (CS and DATACLK tied LOW, EXT/INT tied HIGH).

t

21

R/C

t

FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.

CS

BUSY

BYTE

DATA

BUS

t

21

1

t

3

t

4

Hi-Z State

t

21

t

21

High Byte

t

12

9

t

21

t

21

Hi-Z State Low Byte Hi-Z State

t

9

t

21

t

21

t

12

t

21

t

21

t

9

ADS7806

®

SERIAL OUTPUT

Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful
with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as
these pins will come out of Hi-Z state whenever CS (pin 23)
is LOW and R/C (pin 22) is HIGH. The serial output can not
be tri-stated and is always active.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

t

15

t

16

t

17

t

18

t

19

t

20

t

21

t

22

+ t

t

7

8

Convert Pulse Width 0.04 12 µs

Data Valid Delay after R/C LOW 14.7 20 µs

BUSY Delay from 85 ns

Start of Conversion

BUSY LOW 14.7 20 µs

BUSY Delay after 90 ns

End of Conversion

Aperture Delay 40 ns

Conversion Time 14.7 20 µs

Acquisition Time 5 µs

Bus Relinquish Time 10 83 ns

BUSY Delay after Data Valid 20 60 ns

Previous Data Valid 12 14.7 µs

after Start of Conversion

Bus Access Time and BYTE Delay 83 ns

Start of Conversion 1.4 µs
to DATACLK Delay

DATACLK Period 1.1 µs

Data Valid to DATACLK 20 75 ns

HIGH Delay

Data Valid after DATACLK 400 600 ns

LOW Delay

External DATACLK Period 100 ns

External DATACLK LOW 40 ns
External DATACLK HIGH 50 ns

CS and R/C to External 25 ns

DATACLK Setup Time
R/C to CS Setup Time 10 ns

Valid Data after DATACLK HIGH 25 ns

Throughput Time 25 µs

INTERNAL DATA CLOCK (During A Conversion)

To use the internal data clock, tie EXT/INT (pin 8) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7806 will output 12
bits of valid data, MSB first, from conversion ‘n-1’ on
SDATA (pin 19), synchronized to 12 clock pulses output on
DATACLK (pin 18). The data will be valid on both the
rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After
the 12th clock pulse, DATACLK will remain LOW until the
next conversion is initiated, while SDATA will go to what­ever logic level was input on TAG (pin 20) during the first
clock pulse. Refer to Table VI and Figure 4.

EXTERNAL DATA CLOCK

To use an external data clock, tie EXT/INT (pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7806, CS (pin 23) must be LOW and R/C (pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion ‘n’ can be output on
SDATA (pin 19) after conversion ‘n’ is completed or during
conversion ‘n + 1’.

An obvious way to simplify control of the converter is to tie
CS LOW and use R/C to initiate conversions. While this is
perfectly acceptable, there is a possible problem when using
an external data clock. At an indeterminate point from 12µs
after the start of conversion 'n' until BUSY rises, the internal
logic will shift the results of conversion 'n' into the output
register. If CS is LOW, R/C is HIGH, and the external clock
is HIGH at this point, data will be lost. So, with CS LOW,
either R/C and/or DATACLK must be LOW during this
period to avoid losing valid data.

TABLE VI. Conversion and Data Timing. TA = –40°C to

+85°C.

(1)

CS or R/C

t

14

1

t

DATACLK

SDATA

BUSY

NOTE: (1) If controlling with CS, tie R/C LOW. Data bus pins will remain Hi-Z at all times.
If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected.

13

t

15

MSB Valid

2 3 11 12

t

16

Bit 10 Valid Bit 1 ValidBit 9 Valid LSB Valid

(Results from previous conversion.)

FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).

®

ADS7806

t

7

10

+ t

8

1

MSB Valid

2

Bit 10 Valid

20

t

Tag 1

19

t

17

t

18

t

12 311121314

0

Tag 0

Tag 13 Tag 14

Bit 0 (LSB)

Bit 10 Bit 1

Tag 1 Tag 2 Tag 11 Tag 12

Bit 11 (MSB)

22

t

20

t

21

t

Tag 0

FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT Tied HIGH) Read after Conversion.

EXTERNAL

DATACLK

3

R/C

11

t

BUSY

SDATA

TAG

®

ADS7806

1

t

21

t

CS

EXTERNAL
DATACLK

CS

R/C

BUSY

t

17

t18t

19

t

20

t

22

t

21

t

20

t

1

t

3

t

11

DATA

TAG

Tag 0

Bit 11 (MSB)

Tag 1 Tag 12

Bit 0 (LSB)

Tag 0

Tag 13 Tag 14

Tag 1

FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion.

EXTERNAL DATA CLOCK
(After a Conversion)

After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. With CS
LOW and R/C HIGH, valid data from conversion ‘n’ will be
output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB will be valid
on the first falling edge and the second rising edge of the
external data clock. The LSB will be valid on the 12th falling
edge and 13th rising edge of the data clock. TAG (pin 20)
will input a bit of data for every external clock pulse. The

TAG FEATURE

TAG (Pin 20) inputs serial data synchronized to the external
or internal data clock.

When using an external data clock, the serial bit stream input
on TAG will follow the LSB output on SDATA until the
internal output register is updated with new conversion
results. See Table VI and Figures 5 and 6.

The logic level input on TAG for the first rising edge of the
internal data clock will be valid on SDATA after all 12 bits
of valid data have been output.

first bit input on TAG will be valid on SDATA on the 13th
falling edge and the 14th rising edge of DATACLK; the
second input bit will be valid on the 14th falling edge and the
15th rising edge, etc. With a continuous data clock, TAG
data will be output on SDATA until the internal output
registers are updated with the results from the next conver­sion. Refer to Table VI and Figure 5.

EXTERNAL DATA CLOCK
(During a Conversion)

After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to clock out
data from 12µs after the start of conversion ‘n’ until BUSY
(pin 24) rises; this will result in data loss. NOTE: For the
best possible performance when using an external data
clock, data should not be clocked out during a conversion.
The switching noise of the asynchronous data clock can
cause digital feedthrough degrading the converter’s perfor-

INPUT RANGES

The ADS7806 offers three input ranges: standard ±10V and
0-5V, and a 0-4V range for complete, single supply systems.
Figures 7a and 7b show the necessary circuit connections for
implementing each input range and optional offset and gain
adjust circuitry. Offset and full scale error
are tested and guaranteed with the fixed resistors shown in
Figure 7b. Adjustments for offset and gain are described in
the Calibration section of this data sheet.

The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com­pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).

The input impedance, summarized in Table II, results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external resistors

(1)

specifications

mance. Refer to Table VI and Figure 6.

®

ADS7806

NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.

12

200Ω

1

2

3

4

5

6

AGND2

REF

CAP

R2

IN

AGND1

R1

IN

+

+

2.2µF

2.2µF

33.2kΩ

100Ω

V

IN

1MΩ

+5V

50kΩ

50kΩ

used for each input range (see Figure 8). The input resistor
divider network provides inherent overvoltage protection
guaranteed to at least ±25V.

Analog inputs above or below the expected range will yield
either positive full scale or negative full scale digital outputs
respectively. There will be no wrapping or folding over for
analog inputs outside the nominal range.

INPUT RANGE RANGE (mV) RANGE (mV)

OFFSET ADJUST GAIN ADJUST

±10V ±15 ±60
0 to 5V ±4 ±30
0 to 4V ±3 ±30

TABLE VII. Offset and Gain Adjust Ranges for Hardware

Calibration (see Figure 7a).

CALIBRATION

HARDWARE CALIBRATION

To calibrate the offset and gain of the ADS7806 in hard­ware, install the resistors shown in Figure 7a. Table VII lists
the hardware trim ranges relative to the input for each input
range.

SOFTWARE CALIBRATION

To calibrate the offset and gain in software, no external
resistors are required. However, to get the data sheet speci-

±10V 0-5V 0-4V

200Ω

33.2kΩ

100Ω

50kΩ

+5V

50kΩ

+5V

1MΩ

V

IN

2.2µF

2.2µF

1

R1

IN

2

AGND1

3

R2

IN

4

CAP

+

5

REF

+

6

AGND2

50kΩ

V

+5V

50kΩ

fications for offset and gain, the resistors shown in Figure 7b
are necessary. See the No Calibration section for more
details on the external resistors. Refer to Table VIII for the
range of offset and gain errors with and without the external
resistors.

NO CALIBRATION

See Figure 7b for circuit connections. Note that the actual
voltage dropped across the external resistors is at least two
orders of magnitude lower than the voltage dropped across
the internal resistor divider network. This should be consid-

200Ω

33.2kΩ

IN

100Ω

1MΩ

2.2µF

2.2µF

1

R1

IN

2

AGND1

3

R2

IN

4

CAP

+

5

REF

+

6

AGND2

FIGURE 7a. Circuit Diagrams (With Hardware Trim).

±10V 0-5V 0-4V

200Ω

V

IN

66.5kΩ

+5V

100Ω

2.2µF

FIGURE 7b. Circuit Diagrams (Without Hardware Trim).

2.2µF

1

R1

2

AGND1

3

R2

4

CAP

+

5

REF

+

6

AGND2

IN

200Ω

33.2kΩ

IN

V

IN

100Ω

2.2µF

2.2µF

1

R1

IN

2

AGND1

3

R2

IN

4

CAP

+

5

REF

+

6

AGND2

13

33.2kΩ

200Ω

V

IN

100Ω

2.2µF

2.2µF

ADS7806

1

R1

IN

2

AGND1

3

R2

IN

4

CAP

+

5

REF

+

6

AGND2

®

ered when choosing the accuracy and drift specifications of
the external resistors. In most applications, 1% metal-film
resistors will be sufficient.

The external resistors shown in Figure 7b may not be
necessary in some applications. These resistors provide
compensation for an internal adjustment of the offset and
gain which allows calibration with a single supply. Not
using the external resistors will result in offset and gain
errors in addition to those listed in the electrical specifica­tions section. Offset refers to the equivalent voltage of the
digital output when converting with the input grounded. A
positive gain error occurs when the equivalent output volt­age of the digital output is larger than the analog input. Refer
to Table VIII for nominal ranges of gain and offset errors
with and without the external resistors. Refer to Figure 8 for
typical shifts in the transfer functions which occur when the
external resistors are removed.

To further analyze the effects of removing any combination
of the external resistors, consider Figure 9. The combination
of the external and the internal resistors form a voltage
divider which reduces the input signal to a 0.3125V to

2.8125V input range at the CDAC. The internal resistors are
laser trimmed to high relative accuracy to meet full specifi­cations. The actual input impedance of the internal resistor
network looking into pin 1 or pin 3 however, is only accurate
to ±20% due to process variations. This should be taken into
account when determining the effects of removing the exter­nal resistors.

REFERENCE

The ADS7806 can operate with its internal 2.5V reference or
an external reference. By applying an external reference to

INPUT
RANGE W/ RESISTORS W/OUT RESISTORS W/ RESISTORS W/OUT RESISTORS

(V) RANGE (mV) RANGE (mV) TYP (mV) RANGE (% FS) RANGE (% FS) TYP

±10 –10 ≤ BPZ ≤ 10 0 ≤ BPZ ≤ 35 +15 –0.4 ≤ G ≤ 0.4 –0.3 ≤ G ≤ 0.5 +0.05

0 to 5 –3 ≤ UPO ≤ 3 –12 ≤ UPO ≤ –3 –7.5 –0.4 ≤ G ≤ 0.4 –1.0 ≤ G ≤ 0.1 –0.2

0 to 4 –3 ≤ UPO ≤ 3 –10.5 ≤ UPO ≤ –1.5 –6 –0.4 ≤ G ≤ 0.4 –1.0 ≤ G ≤ 0.1 –0.2

Note: (1) High Grade.

OFFSET ERROR GAIN ERROR

0.15 ≤ G

0.15 ≤ G

–0.15 ≤ G

(1)

≤ 0.15 –0.1 ≤ G

(1)

≤ 0.15 –0.55 ≤ G

(1)

≤ 0.15 –0.55 ≤ G

(1)

≤ 0.2 +0.05

(1)

≤ –0.05 –0.2

(1)

≤ –0.05 –0.2

TABLE VIII. Range of Offset and Gain Errors with and without External Resistors

(a) Bipolar

Digital Output

+Full Scale

(b) Unipolar

Digital Output

+Full Scale

–Full Scale

FIGURE 8. Typical Transfer Functions With and Without External Resistors.

®

ADS7806

Analog Input

Typical Transfer Functions
With External Resistors

Typical Transfer Functions
Without External Resistors

–Full Scale

Analog Input

14

V

IN

39.8kΩ200Ω
CDAC (High Impedance)

(0.3125V to 2.8125V)

+5V

V

V

66.5kΩ

100Ω

+2.5V

33.2kΩ

100Ω

IN

+2.5V

IN

33.2kΩ

100Ω

+2.5V

9.9kΩ

39.8kΩ200Ω

9.9kΩ

39.8kΩ200Ω

9.9kΩ

20kΩ

20kΩ

20kΩ

FIGURE 9. Circuit Diagrams Showing External and Internal Resistors.

+2.5V

+2.5V

+2.5V

40kΩ

40kΩ

40kΩ

CDAC (High Impedance)
(0.3125V to 2.8125V)

CDAC (High Impedance)



(0.3125V to 2.8125V)

pin 5, the internal reference can be bypassed; REFD (pin 26)
tied HIGH will power-down the internal reference reducing
the overall power consumption of the ADS7806 by approxi­mately 5mW.

The internal reference has approximately an 8 ppm/°C drift
(typical) and accounts for approximately 20% of the full
scale error (FSE = ±0.5% for low grade, ±0.25% for high
grade).

The ADS7806 also has an internal buffer for the reference
voltage. See Figure 10 for characteristic impedances at the
input and output of the buffer with all combinations of
power down and reference down.

REF

REF (pin 5) is an input for an external reference or the output
for the internal 2.5V reference. A 2.2µF tantalum capacitor
should be connected as close as possible to the REF pin from
ground. This capacitor and the output resistance of REF
create a low pass filter to bandlimit noise on the reference.
Using a smaller value capacitor will introduce more noise to
the reference, degrading the SNR and SINAD. The REF pin
should not be used to drive external AC or DC loads. See
Figure 10.

The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size of
the converter which can improve the SNR.

Z

CAP

(Pin 4)

REF

(Pin 5)

(Ω) 1 1 200 200

Z

CAP

(Ω) 6k 100M 6k 100M

Z

REF

CAP

CDAC

Buffer

Internal

Z

REF

PWRD 0 PWRD 0 PWRD 1 PWRD 1

REFD 0 REFD 1 REFD 0 REFD 1

Reference

FIGURE 10. Characteristic Impedances of Internal Buffer.

CAP

CAP (pin 4) is the output of the internal reference buffer. A

2.2µF tantalum capacitor should be placed as close as
possible to the CAP pin from ground to provide optimum
switching currents for the CDAC throughout the conversion
cycle. This capacitor also provides compensation for the

15

ADS7806

®

output of the buffer. Using a capacitor any smaller than 1µF
can cause the output buffer to oscillate and may not have
sufficient charge for the CDAC. Capacitor values larger than

2.2µF will have little affect on improving performance. See
Figures 10 and 11.

The output of the buffer is capable of driving up to 1mA of
current to a DC load. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degra­dation of the converter.

7000

6000

5000

4000

µs

3000

2000

1000

0

0.1 1 10 100
“CAP” Pin Value (µF)

FIGURE 11. Power-Down to Power-Up Time vs Capacitor

Value on CAP.

REFERENCE
AND POWER DOWN

The ADS7806 has analog power down and reference power
down capabilities via PWRD (pin 25) and REFD (pin 26)
respectively. PWRD and REFD HIGH will power down all
analog circuitry maintaining data from the previous conver­sion in the internal registers, provided that the data has not
already been shifted out through the serial port. Typical
power consumption in this mode is 50µW. Power recovery
is typically 1ms, using a 2.2µF capacitor connected to CAP.
See Figure 11 for power-down to power-up recovery time
relative to the capacitor value on CAP. With +5V applied to

, the digital circuitry of the ADS7806 remains active at

V

DIG

all times, regardless of PWRD and REFD states.

PWRD

PWRD HIGH will power down all of the analog circuitry
except for the reference. Data from the previous conversion
will be maintained in the internal registers and can still be
read. With PWRD HIGH, a convert command yields mean­ingless data.

REFD

REFD HIGH will power down the internal 2.5V reference.
All other analog circuitry, including the reference buffer,
will be active. REFD should be HIGH when using an
external reference to minimize power consumption and the

®

ADS7806

loading effects on the external reference. See Figure 10 for
the characteristic impedance of the reference buffer’s input
for both REFD HIGH and LOW. The internal reference
consumes approximately 5mW.

LAYOUT

POWER

For optimum performance, tie the analog and digital power
pins to the same +5V power supply and tie the analog and
digital grounds together. As noted in the electrical specifica­tions, the ADS7806 uses 90% of its power for the analog
circuitry. The ADS7806 should be considered as an analog
component.

The +5V power for the A/D should be separate from the +5V
used for the system’s digital logic. Connecting V
directly to a digital supply can reduce converter performance
due to switching noise from the digital logic. For best
performance, the +5V supply can be produced from what­ever analog supply is used for the rest of the analog signal
conditioning. If +12V or +15V supplies are present, a simple
+5V regulator can be used. Although it is not suggested, if
the digital supply must be used to power the converter, be
sure to properly filter the supply. Either using a filtered
digital supply or a regulated analog supply, both V

should be tied to the same +5V source.

V

ANA

GROUNDING

Three ground pins are present on the ADS7806. D
digital supply ground. A

is the ground to which all analog signals internal to

A

GND1

the A/D are referenced. A

is the analog supply ground.

GND2

is more susceptible to current

GND1

induced voltage drops and must have the path of least
resistance back to the power supply.

All the ground pins of the A/D should be tied to an analog
ground plane, separated from the system’s digital logic
ground, to achieve optimum performance. Both analog and
digital ground planes should be tied to the “system” ground
as near to the power supplies as possible. This helps to
prevent dynamic digital ground currents from modulating
the analog ground through a common impedance to power
ground.

SIGNAL CONDITIONING

The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injec­tion which can cause the driving op amp to oscillate. The
amount of charge injection due to the sampling FET switch
on the ADS7806 is approximately 5-10% of the amount on
similar ADCs with the charge redistribution DAC (CDAC)
architecture. There is also a resistive front end which attenu­ates any charge which is released. The end result is a
minimal requirement for the drive capability on the signal
conditioning preceding the A/D. Any op amp sufficient for
the signal in an application will be sufficient to drive the
ADS7806.

16

DIG

(pin 28)

DIG

is the

GND

and

The resistive front end of the ADS7806 also provides a
guaranteed ±25V overvoltage protection. In most cases, this
eliminates the need for external over voltage protection
circuitry.

INTERMEDIATE LATCHES

The ADS7806 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversion, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.

Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7806 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance. The effects of this phenomenon will
be more obvious when using the pin-compatible ADS7807
or any of the other 16-bit converters in the ADS Family. This
is due to the smaller internal LSB size of 38µV.

APPLICATIONS INFORMATION

QSPI INTERFACING

Figure 12 shows a simple interface between the ADS7806
and any QSPI equipped microcontroller. This interface as­sumes that the convert pulse does not originate from the
microcontroller and that the ADS7806 is the only serial
peripheral.

Before enabling the QSPI interface, the microcontroller
must be configured to monitor the slave select line. When a
transition from LOW to HIGH occurs on Slave Select (SS)
from BUSY (indicating the end of the current conversion),
the port can be enabled. If this is not done, the microcontroller
and the and the A/D may be “out-of-sync.”

Figure 13 shows another interface between the ADS7806
and a QSPI equipped microcontroller. The interface allows
the microcontroller to give the convert pulses while also
allowing multiple peripherals to be connected to the serial

Convert Pulse

QSPI

PCS0/SS

MOSI

SCK

CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data valid on falling edge)
QSPI port is in slave mode.

ADS7806

R/C
BUSY
SDATA
DATACLK
CS
EXT/INT
BYTE

bus. This interface and the following discussion assume a
master clock for the QSPI interface of 16.78MHz. Notice
that the serial data input of the microcontroller is tied to the
MSB (D7) of the ADS7806 instead of the serial output
(SDATA). Using D7 instead of the serial port offers tri-state
capability which allows other peripherals to be connected to
the MISO pin. When communication is desired with those
peripherals, PCS0 and PCS1 should be left HIGH; that will
keep D7 tri-stated and prevent a conversion from taking
place.

In this configuration, the QSPI interface is actually set to do
two different serial transfers. The first, an eight bit transfer,
causes PCS0 (R/C) and PCS1 (CS) to go LOW starting a
conversion. The second, a twelve bit transfer, causes only
PCS1 (CS) to go LOW. This is when the valid data will be
transferred.

QSPI

PCS0
PCS1

SCK

MISO

CPOL = 0
CPHA = 0

ADS7806

R/C
CS
DATACLK
D7 (MSB)


BYTE

+5V

EXT/INT

FIGURE 13. QSPI Interface to the ADS7806. Processor

Initiates Conversions.

For both transfers, the DT register (delay after transfer) is
used to cause a 19µs delay. The interface is also set up to
wrap to the beginning of the queue. In this manner, the QSPI
is a state machine which generates the appropriate timing for
the ADS7806. This timing is thus locked to the crystal based
timing of the microcontroller and not interrupt driven. So,
this interface is appropriate for both AC and DC measure­ments.

For the fastest conversion rate, the baud rate should be set to
two (4.19MHz SCK), DT set to ten, the first serial transfer
set to eight bits, the second set to twelve bits, and DSCK
disabled (in the command control byte). This will allow for
a 23kHz maximum conversion rate. For slower rates, DT
should be increased. Do not slow SCK as this may increase
the chance of affecting the conversion results or accidently
initiating a second conversion during the first eight bit
transfer.
In addition, CPOL and CPHA should be set to zero (SCK
normally LOW and data captured on the rising edge). The
command control byte for the eight bit transfer should be set
to 20H and for the twelve bit transfer to 61H.

FIGURE 12. QSPI Interface to the ADS7806.

17

®

ADS7806

SPI INTERFACE

The SPI interface is generally only capable of 8-bit data
transfers. For some microcontrollers with SPI interfaces, it
might be possible to receive data in a similar manner as
shown for the QSPI interface in Figure 12. The
microcontroller will need to fetch the 8 most significant bits
before the contents are overwritten by the least significant
bits.

A modified version of the QSPI interface shown in Figure 13
might be possible. For most microcontrollers with SPI inter­face, the automatic generation of the start-of-conversion
pulse will be impossible and will have to be done with
software. This will limit the interface to ‘DC’ applications
due to the insufficient jitter performance of the convert pulse
itself.

the pulse width is (0.7)RC. Choosing a pulse width as close
to the minimum value specified in this data sheet will offer
the best performance. See the Starting A Conversion sec­tion of this data sheet for details on the conversion pulse
width.

The maximum conversion rate for a 20.48MHz DSP56000
is 35.6kHz. If a slower oscillator can be tolerated on the
DSP56000, a conversion rate of 40kHz can be achieved by
using a 19.2MHz clock and a prescale modulus of four.

Convert Pulse

DSP56000

ADS7806

DSP56000 INTERFACING

The DSP56000 serial interface has an SPI compatibility
mode with some enhancements. Figure 14 shows an inter­face between the ADS7806 and the DSP56000 which is very
similar to the QSPI interface seen in Figure 12. As men­tioned in the QSPI section, the DSP56000 must be pro­grammed to enable the interface when a LOW to HIGH
transition on SC1 is observed (BUSY going HIGH at the end
of conversion).
The DSP56000 can also provide the convert pulse by includ­ing a monostable multi-vibrator as seen in Figure 15. The
receive and transmit sections of the interface are decoupled
(asynchronous mode) and the transmit section is set to
generate a word length frame sync every other transmit
frame (frame rate divider set to two). The prescale modulus
should be set to five.

The monostable multi-vibrator in this circuit will provide
varying pulse widths for the convert pulse. The pulse width
will be determined by the external R and C values used with
the multi-vibrator. The 74HCT123N data sheet shows that

DSP56000

+5V

SC2

74HCT123N

B1

CLR1

R/C

SC1
SRD
SCO

SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD1 = 0 (SC1 is an input)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 12 bits)

BUSY
SDATA
DATACLK
CS
EXT/INT
BYTE

FIGURE 14. DSP56000 Interface to the ADS7806.

+5V

R

EXT1

C

EXT1

R

C

ADS7806

SC0

SRD

FIGURE 15. DSP56000 Interface to the ADS7806. Processor Initiates Conversions.

®

ADS7806

A1

SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD2 = 1 (SC2 is an output)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 16 bits)

Q1

18

R/C

DATACLK
SDATA
CS
EXT/INT
BYTE

®

ADS7807

Low-Power 16-Bit Sampling CMOS
ANALOG-to-DIGITAL CONVERTER

FEATURES

● 35mW max POWER DISSIPATION

µW POWER DOWN MODE

● 50

µs max ACQUISITION AND

● 25

CONVERSION

±1.5LSB max INL

●

● DNL: 16 bits “No Missing Codes”

● 86dB min SINAD WITH 1kHz INPUT

±10V, 0V TO +5V, AND 0V TO +4V INPUT

●

RANGES

● SINGLE +5V SUPPLY OPERATION

● PARALLEL AND SERIAL DATA OUTPUT

● PIN-COMPATIBLE WITH 12-BIT ADS7806

● USES INTERNAL OR EXTERNAL

REFERENCE

● 28-PIN 0.3" PLASTIC DIP AND SOIC

Clock

DESCRIPTION

The ADS7807 is a low-power, 16-bit, sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 16-bit, capacitor-based, SAR A/D with S/H,
clock, reference, and microprocessor interface with
parallel and serial output drivers.

The ADS7807 can acquire and convert 16-bits to
within ±1.5LSB in 25µs max while consuming only
35mW max. Laser-trimmed scaling resistors provide
standard industrial input ranges of ±10V and 0V to
+5V. In addition, a 0V to +4V range allows develop­ment of complete single supply systems.

The 28-pin ADS7807 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –40°C to +85°C temperature range.

Successive Approximation Register and Control Logic

R/C
CS
BYTE
Power
Down

40kΩ

R1



IN



R2

IN

International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706

Tel: [phone] • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

©

1992 Burr-Brown Corporation PDS-1159C Printed in U.S.A. November, 1994

10kΩ

CAP

REF

20kΩ

40kΩ

Buffer

6kΩ

CDAC

+2.5V Ref

Internal

Comparator

Reference

Power

Down

Parallel

and

Serial

Data

Out

BUSY
Serial Data

Clock

Serial Data

Parallel Data

8

SPECIFICATIONS

ELECTRICAL

At TA = –40°C to +85°C, fS = 40kHz, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 16 * Bits
ANALOG INPUT

Voltage Ranges ±10, 0 to +5, 0 to +4 V
Impedance (See Table II)
Capacitance 35 * pF

THROUGHPUT SPEED

Conversion Time 20 * µs
Complete Cycle Acquire and Convert 25 * µs
Throughput Rate 40 * kHz

DC ACCURACY

Integral Linearity Error ±3 ±1.5 LSB
Differential Linearity Error +3, –2 +1.5, –1 LSB
No Missing Codes 15 16 Bits
Transition Noise
Gain Error ±0.2 ±0.1 %
Full Scale Error
Full Scale Error Drift ±7 ±5 ppm/°C
Full Scale Error
Full Scale Error Drift Ext. 2.5000V Ref ±0.5 * ppm/°C
Bipolar Zero Error
Bipolar Zero Error Drift ±10V Range ±0.5 * ppm/°C
Unipolar Zero Error

(2)

(3,4)

(3,4)

(3)

(3)

Unipolar Zero Error Drift 0V to 5V, 0V to 4V Ranges ±0.5 * ppm/°C
Recovery Time to Rated Accuracy 2.2µF Capacitor to CAP 1 * ms

from Power Down

(5)

Power Supply Sensitivity +4.75V < VS < +5.25V ±8 * LSB

(V

= V

ANA

= VS)

DIG

AC ACCURACY

Spurious-Free Dynamic Range f
Total Harmonic Distortion f
Signal-to-(Noise+Distortion) f

Signal-to-Noise f
Usable Bandwidth

(7)

Full Power Bandwidth (–3dB) 600 * kHz

SAMPLING DYNAMICS

Aperture Delay 40 * ns
Aperture Jitter 20 * ps
Transient Response FS Step 5 * µs
Overvoltage Recovery

(8)

REFERENCE

Internal Reference Voltage No Load 2.48 2.5 2.52 * * * V
Internal Reference Source Current 1 * µA

(Must use external buffer.)

Internal Reference Drift 8 * ppm/°C
External Reference Voltage Range 2.3 2.5 2.7 * * * V

for Specified Linearity

External Reference Current Drain Ext. 2.5000V Ref 100 * µA

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format
Data Coding

V

OL

V

OH

Leakage Current High-Z State, ±5*µA

Output Capacitance High-Z State 15 * pF

= V

DIG

= +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.

ANA

ADS7807P, U ADS7807PB, UB

(1)

0.8 * LSB

±0.5 ±0.25 %

Ext. 2.5000V Ref ±0.5 ±0.25 %

±10V Range ± 10 * mV

0V to 5V, 0V to 4V Ranges ±3*mV

= 1kHz, ±10V 90 100 96 * dB

IN

= 1kHz, ±10V –100 –90 * –96 dB

IN

= 1kHz, ±10V 83 88 86 * dB

IN

–60dB Input 30 32 dB

= 1kHz, ±10V 83 88 86 * dB

IN

130 * kHz

(6)

750 * ns

–0.3 +0.8 * * V

+2.0 VD +0.3V * * V
VIL = 0V ±10 * µA
VIH = 5V ±10 * µA

Parallel 16 bits in 2-bytes; Serial

Binary Two’s Complement or Straight Binary

I

= 1.6mA +0.4 * V

SINK

I

= 500µA+4 * V

SOURCE

V

= 0V to V

OUT

DIG

®

ADS7807

2

®

SPECIFICATIONS (CONT)

ELECTRICAL

At TA = –40°C to +85°C, fS = 40kHz, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
DIGITAL TIMING

Bus Access Time R
Bus Relinquish Time R

POWER SUPPLIES

Specified Performance

V

DIG

V

ANA

I

DIG

I

ANA

Power Dissipation V

TEMPERATURE RANGE

Specified Performance –40 +85 * * °C
Derated Performance –55 +125 * * °C
Storage –65 +150 * * °C
Thermal Resistance (

Plastic DIP 75 * °C/W
SOIC 75 * °C/W

NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range is 305µV. (2) Typical rms noise at worst case transition. (3) As measured with
fixed resistors shown in Figure 7b. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed
deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5)
This is the time delay after the ADS7807 is brought out of Power Down Mode until all internal settling occurs and the analog input is acquired to rated accuracy.
A Convert Command after this delay will yield accurate results. (6) All specifications in dB are referred to a full-scale input. (7) Usable Bandwidth defined as Full­Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB. (8) Recovers to specified performance after 2 x FS input overvoltage.

θ

)

JA

= V

DIG

= +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.

ANA

ADS7807P, U ADS7807PB, UB

= 3.3kΩ, CL = 50pF 83 * ns

L

= 3.3kΩ, CL = 10pF 83 * ns

L

Must be ≤ V

= V

ANA

DIG

REFD HIGH 23 * mW

PWRD and REFD HIGH 50 * µW

ANA

= 5V, fS = 40kHz 28 35 * * mW

+4.75 +5 +5.25 * * * V
+4.75 +5 +5.25 * * * V

0.6 * mA

5.0 * mA

ABSOLUTE MAXIMUM RATINGS

Analog Inputs: R1IN........................................................................... ±25V

Ground Voltage Differences: DGND, AGND1, and AGND2 .............±0.3V

V

ANA

V

to V

DIG

V

........................................................................................................ 7V

DIG

Digital Inputs .............................................................. –0.3V to V

Maximum Junction Temperature ................................................... +165°C

Internal Power Dissipation ............................................................. 825mW

Lead Temperature (soldering, 10s)................................................ +300°C

R2

........................................................................... ±25V

IN

CAP .................................... V

REF .........................................Indefinite Short to AGND2,

....................................................................................................... 7V

......................................................................................+0.3V

ANA

+0.3V to AGND2 –0.3V

ANA

Momentary Short to V

DIG

ANA

+0.3V

Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr­Brown Corporation recommends that this integrated circuit
be handled and stored using appropriate ESD protection
methods.

ELECTROSTATIC
DISCHARGE SENSITIVITY

ORDERING INFORMATION

MAXIMUM GUARANTEED MINIMUM

INTEGRAL NO MISSING SIGNAL-TO- SPECIFICATION

MODEL ERROR (LSB) (LSB) RATIO (dB) RANGE PACKAGE

ADS7807P ± 3 15 83 –40°C to +85°C Plastic DIP
ADS7807PB ±1.5 16 86 –40°C to +85°C Plastic DIP
ADS7807U ±3 15 83 –40°C to +85°C SOIC
ADS7807UB ±1.5 16 86 –40°C to +85°C SOIC

LINEARITY CODE LEVEL (NOISE + DISTORTION) TEMPERATURE

PACKAGE INFORMATION

MODEL PACKAGE NUMBER

PACKAGE DRAWING

ADS7807P Plastic DIP 246
ADS7807PB Plastic DIP 246
ADS7807U SOIC 217
ADS7807UB SOIC 217

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.

(1)

3

ADS7807

PIN # NAME I/O DESCRIPTION

DIGITAL

1R1
2 AGND1 Analog Sense Ground.
3R2
4 CAP Reference Buffer Output. 2.2µF tantalum capacitor to ground.

IN

IN

Analog Input. See Figure 7.

Analog Input. See Figure 7.

5 REF Reference Input/Output. 2.2µF tantalum capacitor to ground.
6 AGND2 Analog Ground.
7 SB/BTC I Selects Straight Binary or Binary Two’s Complement for Output Data Format.
8 EXT/INT I External/Inter nal data clock select.
9 D7 O Data Bit 7 if BYTE is HIGH. Data bit 15 (MSB) if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Leave

unconnected when using serial output.
10 D6 O Data Bit 6 if BYTE is HIGH. Data bit 14 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
11 D5 O Data Bit 5 if BYTE is HIGH. Data bit 13 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
12 D4 O Data Bit 4 if BYTE is HIGH. Data bit 12 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
13 D3 O Data Bit 3 if BYTE is HIGH. Data bit 11 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
14 DGND Digital Ground.
15 D2 O Data Bit 2 if BYTE is HIGH. Data bit 10 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
16 D1 O Data Bit 1 if BYTE is HIGH. Data bit 9 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
17 D0 O Data Bit 0 (LSB) if BYTE is HIGH. Data bit 8 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
18 DATACLK I/O Data Clock Output when EXT/INT is LOW. Data clock input when EXT/INT is HIGH.
19 SDATA O Serial Output Synchronized to DATACLK.
20 TAG I Serial Input When Using an External Data Clock.
21 BYTE I Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH) on parallel output pins.
22 R/C I With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C

enables the parallel output.
23 CS I Internally OR’d with R/C. If R/C is LOW, a falling edge on CS initiates a new conversion. If EXT/INT is LOW, this same

falling edge will start the transmission of serial data results from the previous conversion.
24 BUSY O At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs

have been updated.
25 PWRD I PWRD HIGH shuts down all analog circuitry except the reference. Digital circuitry remains active.
26 REFD I REFD HIGH shuts down the internal reference. External reference will be required for conversions.
27 V
28 V

ANA

DIG

Analog Supply. Nominally +5V. Decouple with 0.1µF ceramic and 10µF tantalum capacitors.

Digital Supply. Nominally +5V. Connect directly to pin 27. Must be ≤ V

ANA

.

TABLE I. Pin Assignments.

PIN CONFIGURATION

1



R1

IN

2

AGND1

3



R2

IN

4

CAP

5

REF

6

AGND2

D7
D6
D5
D4
D3

DGND

7



8

9
10
11
12
13
14

SB/BTC

EXT/INT

ADS7807

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V



DIG



V

ANA

REFD
PWRD
BUSY
CS
R/C
BYTE
TAG
SDATA
DATACLK
D0
D1
D2

ANALOG CONNECT R1INCONNECT R2

INPUT VIA 200Ω VIA 100Ω

IN

RANGE TO TO IMPEDANCE

±10V V
0V to 5V AGND V
0V to 4V V

IN

IN

CAP 45.7kΩ

IN

V

IN

20.0kΩ

21.4kΩ

TABLE II. Input Range Connections. See also Figure 7.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

ADS7807

4

®

TYPICAL PERFORMANCE CURVES

FREQUENCY SPECTRUM

(8192 Point FFT; f

IN

= 15kHz, 0dB)

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100
–110
–120
–130

0 5 10 15 20

Amplitude (dB)

Frequency (kHz)

At TA = +25°C, fS = 40kHz, V

DIG

= V

= +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.

ANA

FREQUENCY SPECTRUM

0
–10
–20
–30
–40
–50
–60
–70
–80

Amplitude (dB)

–90

–100
–110
–120
–130

0 5 10 15 20



100

90
80
70
60



50

SINAD (dB)

40
30
20
10

100 1k 10k 100k 1M

(8192 Point FFT; f

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) 

vs INPUT FREQUENCY (f

Input Signal Frequency (Hz)

= 1kHz, 0dB)

IN



= 0dB)

IN



100

90
80
70
60
50

SINAD (dB)

40
30
20
10

02468101214161820

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY AND INPUT AMPLITUDE

0dB

–20dB

–60dB

Input Signal Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE

100

95

90

85

SINAD (dB)

80

75

–75 –50 –25 0 25 50 75 100 125 150

= 1kHz, 0dB; fS = 10kHz to 40kHz)

(f

IN

Temperature (°C)

10kHz

20kHz

30kHz

40kHz

A.C. PARAMETERS vs TEMPERATURE

110

105

100

95

90

85

SFDR, SINAD, and SNR (dB)

80

SFDR

SNR

SINAD

–75 –50 –25 0 25 50 75 100 125 150

5

= 1kHz, 0dB)

(f

IN

Temperature (°C)

ADS7807

THD

–80

–85

–90

–95

THD (dB)

–100

–105

–110

CONVERSION TIME vs TEMPERATURE

Temperature (°C)

–75 –50 –25 0 25 50 75 100 125 150



19.4


19.2


19



18.8


18.6


Conversion Time (µs)

POWER SUPPLY RIPPLE SENSITIVITY

INL/DNL DEGRADATION PER LSB OF P-P RIPPLE

Power Supply Ripple Frequency (Hz)

10

1

10

2

10

3

10

4

10

5

10

6

10

7

1

10–1

10–2

10–3

10

–4



10

–5

Linearity Degradation (LSB/LSB)

INL

DNL

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, fS = 40kHz, V

3

All Codes INL

2
1
0

–1

16 Bit LSBs

–2
–3

0

3

All Codes DNL

2
1
0

–1

16 Bit LSBs

–2
–3

0 65535573444915240960

DIG

= V

= +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.

ANA

3276824576163848192

4915240960

6553557344

Decimal Code

3276824576163848192

Decimal Code

ENDPOINT ERRORS (20V BIPOLAR RANGE)

3

BPZ Error

2
1
0

–1

mV From Ideal

–2

0.20
+FS Error

0

Percent

From Ideal

–0.20

0.20

–FS Error

0

Percent

–0.20

From Ideal

–75

–50 –25 0 25

50 75 100 125

Temperature (°C)

INTERNAL REFERENCE VOLTAGE vs TEMPERATURE

2.520

2.515

2.510

2.505

2.500

2.495

Internal Reference (V)

2.490

2.485

2.480
–75 –50 –25 0 25 50 75 100 125 150

Temperature (°C)

®

ADS7807

ENDPOINT ERRORS (UNIPOLAR RANGES)

3

UPO Error

2
1
0

–1

mV From Ideal

–2

0.40
+FS Error (4V Range)

0.20

Percent

From Ideal

0

0.40

+FS Error (5V Range)

0.20

Percent

0

From Ideal

150

–75

–50 –25 0 25

50 75 100 125

150

Temperature (°C)

6

®

BASIC OPERATION

PARALLEL OUTPUT

Figure 1a) shows a basic circuit to operate the ADS7807
with a ±10V input range and parallel output. Taking R/C
(pin 22) LOW for a minimum of 40ns (12µs max) will
initiate a conversion. BUSY (pin 24) will go LOW and stay
LOW until the conversion is completed and the output
register is updated. If BYTE (pin 21) is LOW, the 8 most
significant bits will be valid when BUSY rises; if BYTE is
HIGH, the 8 least significant bits will be valid when BUSY
rises. Data will be output in Binary Two’s Complement
format. BUSY going HIGH can be used to latch the data.
After the first byte has been read, BYTE can be toggled
allowing the remaining byte to be read. All convert com­mands will be ignored while BUSY is LOW.

The ADS7807 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com­mands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com­pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).

SERIAL OUTPUT

Figure 1b) shows a basic circuit to operate the ADS7807
with a ±10V input range and serial output. Taking R/C (pin

22) LOW for 40ns (12µs max) will initiate a conversion and

output valid data from the previous conversion on SDATA
(pin 19) synchronized to 16 clock pulses output on
DATACLK (pin 18). BUSY (pin 24) will go LOW and stay
LOW until the conversion is completed and the serial data
has been transmitted. Data will be output in Binary Two’s
Complement format, MSB first, and will be valid on both the
rising and falling edges of the data clock. BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.

The ADS7807 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com­mands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com­pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).

STARTING A CONVERSION

The combination of CS (pin 23) and R/C (pin 22) LOW for
a minimum of 40ns puts the sample/hold of the ADS7807 in
the hold state and starts conversion ‘n’. BUSY (pin 24) will
go LOW and stay LOW until conversion ‘n’ is completed
and the internal output register has been updated. All new
convert commands during BUSY LOW will be ignored. CS
and/or R/C must go HIGH before BUSY goes HIGH or a
new conversion will be initiated without sufficient time to
acquire a new signal.

Parallel Output

200Ω

±10V

66.5kΩ

2.2µF

+5V

B14 B11

(MSB)

B6 B3

B13 B12B15

B5 B4B7Pin 21

Pin 21

LOW

HIGH

NOTE: (1) SDATA (pin 19) is always active.

100Ω

2.2µF

++

1
2
3
4
5
6
7

ADS7807



8



9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19

NC

18
17
16
15

B10 B9 B8

B2 B1 B0

(1)

0.1µF
+

BYTE

10µF

BUSY

(LSB)

+

R/C

+5V

Convert Pulse

40ns min

FIGURE 1a. Basic ±10V Operation, both Parallel and Serial

Output.

Serial Output

200Ω

±10V

+5V

66.5kΩ

2.2µF

1
2
3

100Ω

4

2.2µF

5

++

6
7

ADS7807



8

(1)





NC

9

(1)



NC

10

(1)



NC

11

(1)



NC

12

(1)

NC

13
14

NOTE: (1) These pins should be left
unconnected.They will be active when
R/C is HIGH.

28

0.1µF

10µF

27

+

26
25
24
23
22
21
20
19
18

(1)

NC

17

(1)

NC

16

(1)

NC

15

+

BUSY

SDATA

DATACLK

+5V

Convert Pulse

R/C

40ns min

FIGURE 1b. Basic ±10V Operation with Serial Output.

7

ADS7807

The ADS7807 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com­mands assures accurate acquisition of a new signal. Refer to
Tables III and IV for a summary of CS, R/C, and BUSY
states and Figures 2 through 6 for timing diagrams.

CS R/C BUSY OPERATION

1 X X None. Databus is in Hi-Z state.
↓ 0 1 Initiates conversion “n”. Databus remains

0 ↓ 1 Initiates conversion “n”. Databus enters Hi-Z

01↑Conversion “n” completed. Valid data from

↓ 1 1 Enables databus with valid data from

↓ 1 0 Enables databus with valid data from

0 ↑ 0 Enables databus with valid data from

00↑New conversion initiated without acquisition

X X 0 New convert commands ignored. Conversion

NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion “n-1”.

in Hi-Z state.

state.

conversion “n” on the databus.

conversion “n”.

(1)

conversion “n-1”

conversion “n-1”

of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.

“n” in progress.

. Conversion n in progress.

(1)

. Conversion “n” in progress.

Table III. Control Functions When Using Parallel Output

(DATACLK tied LOW, EXT/INT tied HIGH).

CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input. If EXT/INT
(pin 8) is LOW when initiating conversion ‘n’, serial data
from conversion ‘n-1’ will be output on SDATA (pin 19)
following the start of conversion ‘n’. See Internal Data
Clock in the Reading Data section.

To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output and the serial
output (only when using an external data clock) will be
affected whenever R/C goes HIGH. Refer to the Reading
Data section.

READING DATA

The ADS7807 outputs serial or parallel data in Straight
Binary or Binary Two’s Complement data output format. If
SB/BTC (pin 7) is HIGH, the output will be in SB format,
and if LOW, the output will be in BTC format. Refer to
Table V for ideal output codes.

The parallel output can be read without affecting the internal
output registers; however, reading the data through the serial

CS R/C BUSY EXT/INT DATACLK OPERATION

↓ 0 1 0 Output Initiates conversion “n”. Valid data from conversion “n-1” clocked out on SDATA.
0 ↓ 1 0 Output Initiates conversion “n”. Valid data from conversion “n-1” clocked out on SDATA.
↓ 0 1 1 Input Initiates conversion “n”. Internal clock still runs conversion process.
0 ↓ 1 1 Input Initiates conversion “n”. Internal clock still runs conversion process.

↓ 1 1 1 Input Conversion “n” completed. Valid data from conversion “n” clocked out on SDATA synchronized

↓ 1 0 1 Input Valid data from conversion “n-1” output on SDATA synchronized to external data clock.

0 ↑ 0 1 Input Valid data from conversion “n-1” output on SDATA synchronized to external data clock.

00↑X X New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C

X X 0 X X New convert commands ignored. Conversion “n” in progress.

NOTE: (1) See Figures 4, 5, and 6 for constraints on data valid from conversion “n-1”.

to external data clock.

Conversion “n” in progress.

Conversion “n” in progress.

must be HIGH when BUSY goes HIGH.

Table IV. Control Functions When Using Serial Output.

DESCRIPTION ANALOG INPUT

Full-Scale Range ±10 0V to 5V 0V to 4V
Least Significant Bit (LSB) 305µV76µV61µV

+Full Scale (FS – 1LSB) 9.999695V 4.999924V 3.999939V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF
Midscale 0V 2.5V 2V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000
One LSB Below Midscale –305µV 2.499924V 1.999939V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF
–Full Scale –10V 0V 0V 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000

BINARY TWO’S COMPLEMENT STRAIGHT BINARY

(SB/BTC LOW) (SB/BTC HIGH)

BINARY CODE CODE BINARY CODE CODE

DIGITAL OUTPUT

HEX HEX

Table V. Output Codes and Ideal Input Voltages.

®

ADS7807

8

®

port will shift the internal output registers one bit per data

t

10

BUSY

R/C

MODE

Acquire

Convert

t

11

t

7

t

6

t

3

t

4

t

1

Acquire Convert

t

8

t

6

t

3

Parallel

Data Bus

Previous

High Byte Valid

t

12

Hi-Z Not Valid

t

2

t

9

High Byte

Valid

t

12

t

9

t

12

BYTE

t

1

Previous Low

Byte Valid

Previous High

Byte Valid

Low Byte

Valid

High Byte

Valid

t

12

Hi-Z

t

12

t

12

t

5

clock pulse. As a result, data can be read on the parallel port
prior to reading the same data on the serial port, but data
cannot be read through the serial port prior to reading the
same data on the parallel port.

PARALLEL OUTPUT

To use the parallel output, tie EXT/INT (pin 8) HIGH and
DATACLK (pin 18) LOW. SDATA (pin 19) should be left
unconnected. The parallel output will be active when R/C
(pin 22) is HIGH and CS (pin 23) is LOW. Any other
combination of CS and R/C will tri-state the parallel output.
Valid conversion data can be read in two 8-bit bytes on D7­D0 (pins 9-13 and 15-17) . When BYTE (pin 21) is LOW,
the 8 most significant bits will be valid with the MSB on D7.
When BYTE is HIGH, the 8 least significant bits will be
valid with the LSB on D0. BYTE can be toggled to read both
bytes within one conversion cycle.

Upon initial power up, the parallel output will contain
indeterminate data.

PARALLEL OUTPUT (After a Conversion)

After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13
and 15-17). BUSY going high can be used to latch the data.
Refer to Table VI and Figures 2 and 3 for timing constraints.

PARALLEL OUTPUT (During a Conversion)

After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until BUSY
(pin 24) goes HIGH; this may result in reading invalid data.
Refer to Table VI and Figures 2 and 3 for timing constraints.

FIGURE 2. Conversion Timing with Parallel Output (CS and DATACLK tied LOW, EXT/INT tied HIGH).

t

21

R/C

t

FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.

CS

BUSY

BYTE

DATA

BUS

t

21

1

t

3

t

4

Hi-Z State

t

21

t

21

High Byte

t

12

9

t

21

t

21

Hi-Z State Low Byte Hi-Z State

t

9

t

21

t

21

t

12

t

21

t

21

t

9

ADS7807

SERIAL OUTPUT

Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful
with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as
these pins will come out of Hi-Z state whenever CS (pin 23)
is LOW and R/C (pin 22) is HIGH. The serial output can not
be tri-stated and is always active. Refer to the Applications
Information section for specific serial interfaces.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

t

15

t

16

t

17

t

18

t

19

t

20

t

21

t

22

+ t

t

7

8

Convert Pulse Width 0.04 12 µs

Data Valid Delay after R/C LOW 19 20 µs

BUSY Delay from 85 ns

Start of Conversion

BUSY LOW 19 20 µs

BUSY Delay after 90 ns

End of Conversion

Aperture Delay 40 ns

Conversion Time 19 20 µ s

Acquisition Time 5 µs

Bus Relinquish Time 10 83 ns

BUSY Delay after Data Valid 20 60 ns

Previous Data Valid 12 19 µs

after Start of Conversion

Bus Access Time and BYTE Delay 83 ns

Start of Conversion 1.4 µs
to DATACLK Delay

DATACLK Period 1.1 µs

Data Valid to DATACLK 20 75 ns

HIGH Delay

Data Valid after DATACLK 400 600 ns

LOW Delay

External DATACLK Period 100 ns

External DATACLK LOW 40 ns

External DATACLK HIGH 50 ns

CS and R/C to External 25 ns

DATACLK Setup Time
R/C to CS Setup Time 10 ns

Valid Data after DATACLK HIGH 25 ns

Throughput Time 25 µs

INTERNAL DATA CLOCK (During a Conversion)

To use the internal data clock, tie EXT/INT (pin 8) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7807 will output 16
bits of valid data, MSB first, from conversion ‘n-1’ on
SDATA (pin 19), synchronized to 16 clock pulses output on
DATACLK (pin 18). The data will be valid on both the
rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After
the 16th clock pulse, DATACLK will remain LOW until the
next conversion is initiated, while SDATA will go to what­ever logic level was input on TAG (pin 20) during the first
clock pulse. Refer to Table VI and Figure 4.

EXTERNAL DATA CLOCK

To use an external data clock, tie EXT/INT (pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7807, CS (pin 23) must be LOW and R/C (pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion ‘n’ can be output on
SDATA (pin 19) after conversion ‘n’ is completed or during
conversion ‘n + 1’.

An obvious way to simplify control of the converter is to tie
CS LOW and use R/C to initiate conversions.

While this is perfectly acceptable, there is a possible prob­lem when using an external data clock. At an indeterminate
point from 12µs after the start of conversion ‘n’ until BUSY
rises, the internal logic will shift the results of conversion ‘n’
into the output register. If CS is LOW, R/C HIGH, and the
external clock is HIGH at this point, data will be lost. So,
with CS LOW, either R/C and/or DATACLK must be LOW
during this period to avoid losing valid data.

TABLE VI. Conversion and Data Timing. TA = –40°C to

+85°C.

(1)

CS or R/C

t

14

1

t

DATACLK

SDATA

BUSY

NOTE: (1) If controlling with CS, tie R/C LOW. Data bus pins will remain Hi-Z at all times.
If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected.

13

t

15

MSB Valid

2 3 15 16

t

16

Bit 14 Valid Bit 1 ValidBit 13 Valid LSB Valid

(Results from previous conversion.)

FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).

®

ADS7807

10

t

+ t

7

8

1

MSB Valid

2

Bit 14 Valid

®

20

t

Tag 1

Tag 0

Tag 17 Tag 18

Bit 0 (LSB)

Bit 14 Bit 1

Tag 1 Tag 2 Tag 15 Tag 16

1 2 3 4 16 17 18

19

t

17

t

18

t

0

22

t

20

t

21

t

Bit 15 (MSB)

Tag 0

FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT Tied HIGH) Read after Conversion.

EXTERNAL

DATACLK

3

R/C

t

11

BUSY

SDATA

TAG

ADS7807

1

t

21

t

CS

EXTERNAL
DATACLK

CS

R/C

BUSY

t

17

t18t

19

t

20

t

22

t

21

t

20

t

1

t

3

t

11

DATA

TAG

Bit 15 (MSB)

Tag 1 Tag 16 Tag 17 Tag 18Tag 0

Bit 0 (LSB) Tag 0 Tag 1

FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion.

EXTERNAL DATA CLOCK
(After a Conversion)

After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. With CS
LOW and R/C HIGH, valid data from conversion ‘n’ will be
output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB will be valid
on the first falling edge and the second rising edge of the
external data clock. The LSB will be valid on the 16th falling
edge and 17th rising edge of the data clock. TAG (pin 20)
will input a bit of data for every external clock pulse. The

TAG FEATURE

TAG (Pin 20) inputs serial data synchronized to the external
or internal data clock.

When using an external data clock, the serial bit stream input
on TAG will follow the LSB output on SDATA until the
internal output register is updated with new conversion
results. See Table VI and Figures 5 and 6.

The logic level input on TAG for the first rising edge of the
internal data clock will be valid on SDATA after all 16 bits
of valid data have been output.

first bit input on TAG will be valid on SDATA on the 17th
falling edge and the 18th rising edge of DATACLK; the
second input bit will be valid on the 18th falling edge and the
19th rising edge, etc. With a continuous data clock, TAG
data will be output on SDATA until the internal output
registers are updated with the results from the next conver­sion. Refer to Table VI and Figure 5.

EXTERNAL DATA CLOCK
(During a Conversion)

After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to clock out
data from 12µs after the start of conversion ‘n’ until BUSY
(pin 24) rises; this will result in data loss. NOTE: For the
best possible performance when using an external data
clock, data should not be clocked out during a conversion.
The switching noise of the asynchronous data clock can
cause digital feedthrough degrading the converter’s perfor-

INPUT RANGES

The ADS7807 offers three input ranges: standard ±10V and
0-5V, and a 0-4V range for complete, single supply systems.
Figures 7a and 7b show the necessary circuit connections for
implementing each input range and optional offset and gain
adjust circuitry. Offset and full scale error
are tested and guaranteed with the fixed resistors shown in
Figure 7b. Adjustments for offset and gain are described in
the Calibration section of this data sheet.

The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com­pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).

The input impedance, summarized in Table II, results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external resistors

(1)

specifications

mance. Refer to Table VI and Figure 6.

®

ADS7807

NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.

12

®

used for each input range (see Figure 8). The input resistor

200Ω

1

2

3

4

5

6

AGND2

REF

CAP

R2

IN

AGND1

R1

IN

+

+

2.2µF

2.2µF

33.2kΩ

100Ω

V

IN

1MΩ

+5V

50kΩ

50kΩ

divider network provides inherent overvoltage protection
guaranteed to at least ±25V.

Analog inputs above or below the expected range will yield
either positive full scale or negative full scale digital outputs
respectively. Wrapping or folding over for analog inputs
outside the nominal range will not occur.

INPUT RANGE RANGE (mV) RANGE (mV)

OFFSET ADJUST GAIN ADJUST

±10V ±15 ±60
0 to 5V ±4 ±30

0 to 4V ±3 ±30

TABLE VII. Offset and Gain Adjust Ranges for Hardware

Calibration (see Figure 7a).

CALIBRATION

HARDWARE CALIBRATION

To calibrate the offset and gain of the ADS7807 in hard­ware, install the resistors shown in Figure 7a. Table VII lists
the hardware trim ranges relative to the input for each input
range.

SOFTWARE CALIBRATION

To calibrate the offset and gain in software, no external
resistors are required. However, to get the data sheet speci­fications for offset and gain, the resistors shown in Figure 7b
are necessary. See the No Calibration section for more

±10V 0-5V 0-4V

200Ω

33.2kΩ

100Ω

50kΩ

+5V

50kΩ

+5V

1MΩ

V

IN

2.2µF

2.2µF

1

R1

IN

2

AGND1

3

R2

IN

4

CAP

+

5

REF

+

6

AGND2

50kΩ

V

+5V

50kΩ

details on the external resistors. Refer to Table VIII for the
range of offset and gain errors with and without the external
resistors.

NO CALIBRATION

See Figure 7b for circuit connections. Note that the actual
voltage dropped across the external resistors is at least two
orders of magnitude lower than the voltage dropped across
the internal resistor divider network. This should be consid­ered when choosing the accuracy and drift specifications of
the external resistors. In most applications, 1% metal-film
resistors will be sufficient.

200Ω

33.2kΩ

IN

100Ω

1MΩ

2.2µF

2.2µF

1

R1

IN

2

AGND1

3

R2

IN

4

CAP

+

5

REF

+

6

AGND2

FIGURE 7a. Circuit Diagrams (With Hardware Trim).

±10V 0-5V 0-4V

200Ω

V

IN

66.5kΩ

+5V

100Ω

2.2µF

FIGURE 7b. Circuit Diagrams (Without Hardware Trim).

2.2µF

1

R1

2

AGND1

3

R2

4

CAP

+

5

REF

+

6

AGND2

IN

200Ω

33.2kΩ

IN

V

IN

100Ω

2.2µF

2.2µF

1

R1

IN

2

AGND1

3

R2

IN

4

CAP

+

5

REF

+

6

AGND2

13

33.2kΩ

200Ω

V

IN

100Ω

2.2µF

2.2µF

ADS7807

1

R1

IN

2

AGND1

3

R2

IN

4

CAP

+

5

REF

+

6

AGND2

The external resistors shown in Figure 7b may not be
necessary in some applications. These resistors provide
compensation for an internal adjustment of the offset and
gain which allows calibration with a single supply. Not
using the external resistors will result in offset and gain
errors in addition to those listed in the electrical specifica­tions section. Offset refers to the equivalent voltage of the
digital output when converting with the input grounded. A
positive gain error occurs when the equivalent output volt­age of the digital output is larger than the analog input. Refer
to Table VIII for nominal ranges of gain and offset errors
with and without the external resistors. Refer to Figure 8 for
typical shifts in the transfer functions which occur when the
external resistors are removed.

To further analyze the effects of removing any combination
of the external resistors, consider Figure 9. The combination
of the external and the internal resistors form a voltage

divider which reduces the input signal to a 0.3125V to

2.8125V input range at the CDAC. The internal resistors are
laser trimmed to high relative accuracy to meet full scale
specifications. The actual input impedance of the internal
resistor network looking into pin 1 or pin 3 however, is only
accurate to ±20% due to process variations. This should be
taken into account when determining the effects of removing
the external resistors.

REFERENCE

The ADS7807 can operate with its internal 2.5V reference or
an external reference. By applying an external reference to
pin 5, the internal reference can be bypassed; REFD (pin 26)
tied HIGH will power-down the internal reference reducing

INPUT
RANGE W/ RESISTORS W/OUT RESISTORS W/ RESISTORS W/OUT RESISTORS

(V) RANGE (mV) RANGE (mV) TYP (mV) RANGE (% FS) RANGE (% FS) TYP

±10 –10 ≤ BPZ ≤ 10 0 ≤ BPZ ≤ 35 15 –0.4 ≤ G ≤ 0.4 –0.3 ≤ G ≤ 0.5 +0.05

0 to 5 –3 ≤ UPO ≤ 3 –12 ≤ UPO ≤ –3 –7.5 –0.4 ≤ G ≤ 0.4 –1.0 ≤ G ≤ 0.1 –0.2

0 to 4 –3 ≤ UPO ≤ 3 –10.5 ≤ UPO ≤ –1.5 –6 –0.4 ≤ G ≤ 0.4 –1.0 ≤ G ≤ 0.1 –0.2

Note: (1) High Grade.

OFFSET ERROR GAIN ERROR

0.15 ≤ G

0.15 ≤ G

–0.15 ≤ G

(1)

≤ 0.15 –0.1 ≤ G

(1)

≤ 0.15 –0.55 ≤ G

(1)

≤ 0.15 –0.55 ≤ G

(1)

≤ 0.2 +0.05

(1)

≤ –0.05 –0.2

(1)

≤ –0.05 –0.2

TABLE VIII. Range of Offset and Gain Errors with and without External Resistors.

(a) Bipolar

Digital Output

+Full Scale

(b) Unipolar

Digital Output

+Full Scale

–Full Scale

FIGURE 8. Typical Transfer Functions With and Without External Resistors.

®

ADS7807

Analog Input

Typical Transfer Functions
With External Resistors

Typical Transfer Functions
Without External Resistors

–Full Scale

Analog Input

14

®

V

IN

39.8kΩ200Ω
CDAC

(0.3125V to 2.8125V)

+5V

V

V

66.5kΩ

100Ω

+2.5V

33.2kΩ

100Ω

IN

+2.5V

IN

33.2kΩ

100Ω

+2.5V

9.9kΩ

39.8kΩ200Ω

9.9kΩ

39.8kΩ200Ω

9.9kΩ

20kΩ

20kΩ

20kΩ

FIGURE 9. Circuit Diagrams Showing External and Internal Resistors.

40kΩ

+2.5V

CDAC
(0.3125V to 2.8125V)

40kΩ

+2.5V

CDAC
(0.3125V to 2.8125V)

40kΩ

+2.5V

the overall power consumption of the ADS7807 by approxi­mately 5mW.

The internal reference has approximately an 8 ppm/°C drift
(typical) and accounts for approximately 20% of the full
scale error (FSE = ±0.5% for low grade, ±0.25% for high
grade).

The ADS7807 also has an internal buffer for the reference
voltage. See Figure 10 for characteristic impedances at the
input and output of the buffer with all combinations of
power down and reference down.

REF

REF (pin 5) is an input for an external reference or the output
for the internal 2.5V reference. A 2.2µF tantalum capacitor
should be connected as close as possible to the REF pin from
ground. This capacitor and the output resistance of REF
create a low pass filter to bandlimit noise on the reference.
Using a smaller value capacitor will introduce more noise to
the reference, degrading the SNR and SINAD. The REF pin
should not be used to drive external AC or DC loads. See
Figure 10.

The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size of
the converter which can improve the SNR.

Z

CAP

(Pin 4)

REF

(Pin 5)

(Ω) 1 1 200 200

Z

CAP

(Ω) 6k 100M 6k 100M

Z

REF

CAP

CDAC

Buffer

Internal

Z

REF

PWRD 0 PWRD 0 PWRD 1 PWRD 1

REFD 0 REFD 1 REFD 0 REFD 1

Reference

FIGURE 10. Characteristic Impedances of Internal Buffer.

CAP

CAP (pin 4) is the output of the internal reference buffer. A

2.2µF tantalum capacitor should be placed as close as
possible to the CAP pin from ground to provide optimum
switching currents for the CDAC throughout the conversion

15

ADS7807

cycle. This capacitor also provides compensation for the
output of the buffer. Using a capacitor any smaller than 1µF
can cause the output buffer to oscillate and may not have
sufficient charge for the CDAC. Capacitor values larger than

2.2µF will have little affect on improving performance. See
Figures 10 and 11.

The output of the buffer is capable of driving up to 1mA of
current to a DC load. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degra­dation of the converter.

7000

6000

5000

4000

µs

3000

2000

1000

0

0.1 1 10 100
“CAP” Pin Value (µF)

FIGURE 11. Power-Down to Power-Up Time vs Capacitor

Value on CAP.

REFERENCE
AND POWER DOWN

The ADS7807 has analog power down and reference power
down capabilities via PWRD (pin 25) and REFD (pin 26)
respectively. PWRD and REFD HIGH will power down all
analog circuitry maintaining data from the previous conver­sion in the internal registers, provided that the data has not
already been shifted out through the serial port. Typical
power consumption in this mode is 50µW. Power recovery
is typically 1ms, using a 2.2µF capacitor connected to CAP.
See Figure 11 for power-down to power-up recovery time
relative to the capacitor value on CAP. With +5V applied to

, the digital circuitry of the ADS7807 remains active at

V

DIG

all times, regardless of PWRD and REFD states.

PWRD

PWRD HIGH will power down all of the analog circuitry
except for the reference. Data from the previous conversion
will be maintained in the internal registers and can still be
read. With PWRD HIGH, a convert command yields mean­ingless data.

REFD

REFD HIGH will power down the internal 2.5V reference.
All other analog circuitry, including the reference buffer,
will be active. REFD should be HIGH when using an
external reference to minimize power consumption and the

loading effects on the external reference. See Figure 10 for
the characteristic impedance of the reference buffer’s input
for both REFD HIGH and LOW. The internal reference
consumes approximately 5mW.

LAYOUT

POWER

For optimum performance, tie the analog and digital power
pins to the same +5V power supply and tie the analog and
digital grounds together. As noted in the electrical specifica­tions, the ADS7807 uses 90% of its power for the analog
circuitry. The ADS7807 should be considered as an analog
component.

The +5V power for the A/D should be separate from the +5V
used for the system’s digital logic. Connecting V
directly to a digital supply can reduce converter performance
due to switching noise from the digital logic. For best
performance, the +5V supply can be produced from what­ever analog supply is used for the rest of the analog signal
conditioning. If +12V or +15V supplies are present, a simple
+5V regulator can be used. Although it is not suggested, if
the digital supply must be used to power the converter, be
sure to properly filter the supply. Either using a filtered
digital supply or a regulated analog supply, both V

should be tied to the same +5V source.

V

ANA

GROUNDING

Three ground pins are present on the ADS7807. D
digital supply ground. A

is the ground to which all analog signals internal to

A

GND1

the A/D are referenced. A

is the analog supply ground.

GND2

is more susceptible to current

GND1

induced voltage drops and must have the path of least
resistance back to the power supply.

All the ground pins of the A/D should be tied to an analog
ground plane, separated from the system’s digital logic
ground, to achieve optimum performance. Both analog and
digital ground planes should be tied to the “system” ground
as near to the power supplies as possible. This helps to
prevent dynamic digital ground currents from modulating
the analog ground through a common impedance to power
ground.

SIGNAL CONDITIONING

The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injec­tion which can cause the driving op amp to oscillate. The
amount of charge injection due to the sampling FET switch
on the ADS7807 is approximately 5-10% of the amount on
similar ADCs with the charge redistribution DAC (CDAC)
architecture. There is also a resistive front end which attenu­ates any charge which is released. The end result is a
minimal requirement for the drive capability on the signal
conditioning preceding the A/D. Any op amp sufficient for
the signal in an application will be sufficient to drive the
ADS7807.

DIG

GND

(pin 28)

and

DIG

is the

®

ADS7807

16

®

The resistive front end of the ADS7807 also provides a

52

FFFEH

173

FFFFH

581

0000H

176

0001H180002H000003HFFFDH

guaranteed ±25V overvoltage protection. In most cases, this
eliminates the need for external over voltage protection
circuitry.

INTERMEDIATE LATCHES

The ADS7807 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversion, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.

Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7807 has an internal LSB size of 38µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance.

APPLICATIONS INFORMATION

TRANSITION NOISE

Apply a DC input to the ADS7807 and initiate 1000 conver­sions. The digital output of the converter will vary in output
codes due to the internal noise of the ADS7807. This is true
for all 16-bit SAR converters. The transition noise specifica­tion found in the electrical specifications section is a statis­tical figure which represents the one sigma limit or rms
value of these output codes.

Using a histogram to plot the output codes, the distribution
should appear bell-shaped with the peak of the bell curve
representing the nominal output code for the input voltage
value. The ±1σ, ±2σ, and ±3σ distributions will represent

68.3%, 95.5%, and 99.7% of all codes. Multiplying TN by
6 will yield the ±3σ distribution or 99.7% of all codes.
Statistically, up to 3 codes could fall outside the 5 code
distribution when executing 1000 conversions. The ADS7807
has a TN of 0.8 LSBs which yields 5 output codes for a ±3σ
distribution. See Figures 12 and 13 for 1000 and 10,000
conversion histogram results.

AVERAGING

The noise of the converter can be compensated by averaging
the digital codes. By averaging conversion results, transition
noise will be reduced by a factor of 1/√n where n is the
number of averages. For example, averaging four conver­sion results will reduce the TN by 1/2 to 0.4 LSBs. Averag­ing should only be used for input signals with frequencies
near DC.

For AC signals, a digital filter can be used to lowpass filter
and decimate the output codes. This works in a similar
manner to averaging: for every decimation by two, the
signal-to-noise ratio will improve 3dB.

QSPI INTERFACING

Figure 14 shows a simple interface between the ADS7807
and any QSPI equipped microcontroller. This interface as-

FIGURE 12. Histogram of 1000 Conversions with Input

Grounded.

5671

2010

176

0001H

182

0002H

018

0003HFFFDH

438

FFFEH

1681

FFFFH

0000H

FIGURE 13. Histogram of 10,000 Conversions with Input

Grounded.

sumes that the convert pulse does not originate from the
microcontroller and that the ADS7807 is the only serial
peripheral.

Before enabling the QSPI interface, the microcontroller
must be configured to monitor the slave select line. When a
transition from LOW to HIGH occurs on Slave Select (SS)
from BUSY (indicating the end of the current conversion),
the port can be enabled. If this is not done, the microcontroller
and the A/D may be “out-of-sync”.

17

ADS7807

Figure 15 shows another interface between the ADS7807
and a QSPI equipped microcontroller which allows the
microcontroller to give the convert pulses while also allow­ing multiple peripherals to be connected to the serial bus.
This interface and the following discussion assume a master
clock for the QSPI interface of 16.78MHz. Notice that the
serial data input of the microcontroller is tied to the MSB
(D7) of the ADS7807 instead of the serial output (SDATA).
Using D7 instead of the serial port offers tri-state capability
which allows other peripherals to be connected to the MISO
pin. When communication is desired with those peripherals,
PCS0 and PCS1 should be left HIGH; that will keep D7 tri­stated.

Convert Pulse

QSPI

PCS0
PCS1

SCK

MISO

CPOL = 0
CPHA = 0

ADS7807

R/C
CS
DATACLK
D7 (MSB)


BYTE

+5V

EXT/INT

FIGURE 15. QSPI Interface to the ADS7807. Processor

Initiates Conversions.

QSPI

PCS0/SS

MOSI

SCK

CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data valid on falling edge)
QSPI port is in slave mode.

ADS7807

R/C
BUSY
SDATA
DATACLK
CS
EXT/INT
BYTE

FIGURE 14. QSPI Interface to the ADS7807.

In this configuration, the QSPI interface is actually set to do
two different serial transfers. The first, an eight bit transfer,
causes PCS0 (R/C) and PCS1 (CS) to go LOW starting a
conversion. The second, a sixteen bit transfer, causes only
PCS1 (CS) to go LOW. This is when the valid data will be
transferred.

For both transfers, the DT register (delay after transfer) is
used to cause a 19µs delay. The interface is also set up to
wrap to the beginning of the queue. In this manner, the QSPI
is a state machine which generates the appropriate timing for
the ADS7807. This timing is thus locked to the crystal based
timing of the microcontroller and not interrupt driven. So,
this interface is appropriate for both AC and DC measure­ments.

For the fastest conversion rate, the baud rate should be set to
two (4.19MHz SCK), DT set to ten, the first serial transfer
set to eight bits, the second set to 16 bits, and DSCK
disabled (in the command control byte). This will allow for
a 23kHz maximum conversion rate. For slower rates, DT
should be increased. Do not slow SCK as this may increase
the chance of affecting the conversion results or accidently

initiating a second conversion during the first eight bit
transfer.

In addition, CPOL and CPHA should be set to zero (SCK
normally LOW and data captured on the rising edge). The
command control byte for the eight bit transfer should be set
to 20H and for the sixteen bit transfer to 61H.

SPI INTERFACE

The SPI interface is generally only capable of 8-bit data
transfers. For some microcontrollers with SPI interfaces, it
might be possible to receive data in a similar manner as
shown for the QSPI interface in Figure 14. The
microcontroller will need to fetch the 8 most significant bits
before the contents are overwritten by the least significant
bits.

A modified version of the QSPI interface shown in Figure 15
might be possible. For most microcontrollers with SPI inter­face, the automatic generation of the start-of-conversion
pulse will be impossible and will have to be done with
software. This will limit the interface to ‘DC’ applications
due to the insufficient jitter performance of the convert pulse
itself.

DSP56000 INTERFACING

The DSP56000 serial interface has SPI compatibility mode
with some enhancements. Figure 16 shows an interface
between the ADS7807 and the DSP56000 which is very
similar to the QSPI interface seen in Figure 14. As men­tioned in the QSPI section, the DSP56000 must be pro­grammed to enable the interface when a LOW to HIGH
transition on SC1 is observed (BUSY going HIGH at the end
of conversion).

The DSP56000 can also provide the convert pulse by includ­ing a monostable multi-vibrator as seen in Figure 17. The
receive and transmit sections of the interface are decoupled
(asynchronous mode) and the transmit section is set to
generate a word length frame sync every other transmit
frame (frame rate divider set to two). The prescale modulus
should be set to three.

®

ADS7807

18

®

The monostable multi-vibrator in this circuit will provide
varying pulse widths for the convert pulse. The pulse
width will be determined by the external R and C values
used with the multi-vibrator. The 74HCT123N data sheet
shows that the pulse width is (0.7) RC. Choosing a pulse

Convert Pulse

width as close to the minimum value specified in this data
sheet will offer the best performance. See the Starting A
Conversion section of this data sheet for details on the
conversion pulse width.

The maximum conversion rate for a 20.48MHz DSP56000
is exactly 40kHz. Note that this will not be the case for
the ADS7806. See the ADS7806 data sheet for more
information.

DSP56000

SC1
SRD
SCO

SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD1 = 0 (SC1 is an input)
SHFD = 0 (Shift MSB first)
WL1 = 1 WL0 = 0 (Word length = 16 bits)

ADS7807

R/C
BUSY
SDATA
DATACLK
CS
EXT/INT
BYTE

FIGURE 16. DSP56000 Interface to the ADS7807.

DSP56000

SC2

+5V

B1

CLR1

74HCT123N

+5V

R

EXT1

C

EXT1

R

C

ADS7807

SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD2 = 1 (SC2 is an output)
SHFD = 0 (Shift MSB first)
WL1 = 1 WL0 = 0 (Word length = 16 bits)

FIGURE 17. DSP56000 Interface to the ADS7807. Processor Initiates Conversions.

SC0

SRD

A1

19

Q1

R/C

DATACLK
SDATA
CS
EXT/INT
BYTE

ADS7807

7 APPENDIX D

PCM-A/D Demo Soft ware Source List ing

/* pcmad.c Copyright 1996 WinSystems. All Rights Reserved */
/***************************************************************************
*
* Project : PCM-AD12
*
* Purpose : Test, Example code, calibration code
*
* Revision : 1.02
*
* Date : January 15, 1996
*
* Author : Steve Mottin
*
*****************************************************************************
*
* Changes :
*
* Revision Date Desciption
* -------- ------

--------------------------------------------­* 1.00 10/22/95 Original
* 1.01 01/15/96 Removed swap code for REV A board deficiency.
* 1.02 02/07/96 Clean-up and comments for release.
*
******************************************************************************
*/

/* Permission is hereby granted to users of the Winsystems PCM-A/D-12 and
PCM-A/D-16 boards to freely use this source code as-is or in any user
modified form for personal or commercial use. WinSystems provides this
sample source code on an as-is basis and makes no warranty as to fitness
of purpose. In no event shall WinSystems be liable for consequential,
incidental or special damages of any kind through the use of this
software source code or works derived thereof.
*/

#include <stdio.h>
#include <dos.h>
#include <conio.h>

/* The BASE address of the board is assumed to be at 110H. Change this define
to change the base address.
*/

#define AD_BASE 0x110

/* The interrupt used is assumed to be IRQ5. The vector for IRQ5 is 8 + 5 = 13.
The mask for IRQ5 is (1 << 5) = 0x20. Change these two appropriately for a
different interrupt.
*/

#define IRQ_VECTOR 0x0d
#define IRQ_MASK 0x20

/* Function prototypes for functions used in this module */

void wait_complete(void);
void interrupt (*old_isr)();
void interrupt ad_isr();

/* These four arrays, store the low, high, and current values for each

printf("Channel RAW HIGH LOW DATA CURRENT MAX MIN

printf("Number DATA DATA DATA DEV. VOLTAGE VOLTAGE VOLTAGE

of the 16 channels. There are more elegant ways to code this but this
is the ultimate in simplicity.
*/
unsigned current_val[16];
unsigned high_val[16];
unsigned low_val[16];
char flag[16];

/* Various global variables used to keep track of the current channel
and the floating point values used in calculating voltages.
*/
unsigned channel_number;
float full_scale = 5.00;
float offset_val = 0.00;
unsigned full_count = 65520;
int max_channel = 16;
int interrupt_mode = 1;
long interrupt_count = 0;
int mode = 0;

/* Program entry point */

void main()
{
unsigned char lsb,msb;
char c;
unsigned low,high,current;
int channel;

channel_number = 0;

/* To start we, will install our interrupt handler, saving the old handler
for when we exit.

*/

disable();
old_isr = getvect(IRQ_VECTOR);
setvect(IRQ_VECTOR,ad_isr);
enable();

/* This is the restart point whenever we change modes. I usually go to
extreme efforts to avoid using "goto" in C, but in this case it is
only used for a special occasion and it's not to hard to follow
*/

restart:

/* Clear the screen and display the the headers */

clrscr(); /* Clear the screen */
window(1,1,80,25 );

VOLTAGE \n");

DEVIATION\n");

printf

("-----------------------------------------------------------------------------

\n");

/* Display all of the channel numbers and clear the flags */

for(channel = 0; channel < max_channel; channel++)
{

flag[channel] = 0;
gotoxy(1,channel + 4);
printf(" %02d",channel);

}

/* Display the screen footer */

gotoxy(1,21);

printf
("----------------------------------------------------------------------------­\n");

printf("'T' Toggle Scale, 'B' Converter toggle 'M' Interrupt toggle, 'R'
Reset values\n");

printf
("----------------------------------------------------------------------------­\n");

/* Display mode dependent screen information */

gotoxy(1,25);

switch(mode)

{

case 0:

printf("Scale : +0 to +5 Volts - Single-Ended");
break;

case 1:

printf("Scale : -10 to +10 Volts - Single-Ended");
break;

case 2:

printf("Scale : +0 to +5 Volts - Differential");
break;

case 3:

printf("Scale : -10 to +10 Volts - Differential");

break;
}
if(full_count == 65535)

printf(" 16-Bit");

else

printf(" 12-Bit");

gotoxy(48,25);
if(interrupt_mode)

printf("Interrupt Mode");

else

printf("Polled Mode ");

/* Enable and unmask interrupts as specified by the "interrupt_mode"
variable.
*/

interrupt_count = 0;

/* Jump start the background task

*/

if(!interrupt_mode)

outportb(0x21,inportb(0x21) | IRQ_MASK);
else
{

outportb(0x21,inportb(0x21) & ~IRQ_MASK);

outportb(AD_BASE+1,channel_number);

}

/* This loop runs until we exit or until we change modes */

while(1)
{

if(kbhit())

{

/* If a kestroke detected, see what is is and handle it
accordingly.

The keys recognized are :

r - reset deviation values.
t - toggle voltage mode.
m - toggle betweent interrupt and polled mode.

*/

c = getch();
if(c == 'r')
{

for(channel = 0; channel < max_channel; channel++)

flag[channel] = 0;
}
else if(c == 't')
{

mode++;
mode = mode & 3;
if(mode == 0) /* 0-5V Single-Ended */
{

max_channel = 16;

offset_val = 0.0;

full_scale = 5.0;

goto restart;

}
if(mode == 1) /* +-10V Single Ended */
{

max_channel = 16;

offset_val = 10.0;

full_scale = 20.0;

goto restart;

}
if(mode == 2) /* 0-5V Differential */
{

max_channel = 8;

offset_val = 0.0;

full_scale = 5.0;

goto restart;

}
if(mode == 3) /* +-10V differential */

{

/* assemble the word result

/* from the two byte values

max_channel = 8;

offset_val = 10.0;

full_scale = 20.0;

goto restart;

}

}
else if(c == 'm')
{

interrupt_mode++;
interrupt_mode = interrupt_mode & 1;

goto restart;
}
else if(c == 'b')
{

full_count = full_count ^ 0x000f;

goto restart;
}
else

break;

}

/* Go through channel by channel displaying the current value */

for(channel = 0; channel < max_channel; channel++)
{

/* If we're not in interrupt mode. We must poll the channel
before displaying it's value.
*/

if(!interrupt_mode)
{

conversion */

complete */

*/

read */

this channel */

channel */

correctly */

[channel] ^ 0x8000))

outportb(AD_BASE+1,channel); /* Start the

wait_complete(); /* wait for the channel to

lsb = inportb(AD_BASE+1);

msb = inportb(AD_BASE+2);

current_val[channel] = (msb << 8) | lsb;

if(!flag[channel]) /* If this is the first time for

{

high_val[channel] = current_val[channel];
low_val[channel] = current_val[channel];
flag[channel]++; /* Set the flag, we've don this

}

if(mode & 1) /* If a signed mode, do the compare

{

if((current_val[channel] ^ 0x8000) < (low_val

low_val[channel] = current_val[channel];

if((current_val[channel] ^ 0x8000) > (high_val

printf("%8.4f ",(((float)(current_val[channel] ^ 0x8000)

[channel] ^ 0x8000))

high_val[channel] = current_val[channel];
}
else
{

if(current_val[channel] < low_val[channel])

low_val[channel] = current_val[channel];

if(current_val[channel] > high_val[channel])

high_val[channel] = current_val[channel];
}

}

gotoxy(10,channel + 4);
printf("%04X %04X %04X ",current_val[channel],high_val

[channel],low_val[channel]);

printf("%04X ",high_val[channel] - low_val[channel]);
if(mode & 1) /* If signed mode, adjust values when printing */
{

/ (float)full_count) * full_scale) - offset_val);

printf("%8.4f ",(((float)(high_val[channel] ^ 0x8000) /

(float)full_count) * full_scale) - offset_val);

printf("%8.4f ",(((float)(low_val[channel] ^ 0x8000) /

(float)full_count) * full_scale) - offset_val);

printf("%8.4f ",((float)((high_val[channel] ^ 0x8000) -

(low_val[channel]) ^ 0x8000) / (float)full_count) * full_scale);

}
else
{

printf("%8.4f ",(((float)current_val[channel] / (float)

full_count) * full_scale) - offset_val);

printf("%8.4f ",(((float)high_val[channel] / (float)

full_count) * full_scale) - offset_val);

printf("%8.4f ",(((float)low_val[channel] / (float)

full_count) * full_scale) - offset_val);

printf("%8.4f ",((float)(high_val[channel] - low_val

[channel]) / (float)full_count) * full_scale);

}
if(channel < (max_channel-1))

printf(" ");

/* In interrupt mode, display a counter of the number of
interrupts that have occured.
*/
if(interrupt_mode)
{

}

}

}

/* Be sure to restore the original interrupt state before exit */

disable();
outportb(0x21,inportb(0x21) | IRQ_MASK);
setvect(IRQ_VECTOR,old_isr);
enable();

gotoxy(65,25);
printf("%ld",interrupt_count);

clrscr();

}

/* This function polls the AD chip awaiting the completion of the conversion
in progress.
*/

void wait_complete()
{
int stat;

while(1)
{

stat = inportb(AD_BASE); /* Read status */
if((stat & 0x03) == 3)

break;

if(kbhit()) /* We allow a keystroke to also get us out */

break;

}

}

/* This is the interrupt service routine. It reads the current channel,
compares it against maximum deviation values and stores the results
in the arrays for display by the foreground routine.
*/

void interrupt ad_isr()
{
int temp;
unsigned char lsb,msb;
unsigned current;

*/

++interrupt_count;
temp = channel_number;

lsb = inportb(AD_BASE+1);
msb = inportb(AD_BASE+2);

++channel_number;
if(channel_number > (max_channel-1))

channel_number = 0;

outportb(AD_BASE+1,channel_number); /* start next channel converting

current = (msb << 8) | lsb;

current_val[temp] = current; /* Store the current reading */

if(!flag[temp])
{

high_val[temp] = current;
low_val[temp] = current;
flag[temp]++;

}

if(mode & 1) /* If a signed mode, do the comparisons correctly */
{

if((current ^ 0x8000) < (low_val[temp] ^ 0x8000))

low_val[temp] = current;

if((current ^ 0x8000) > (high_val[temp] ^ 0x8000))

high_val[temp] = current;
}
else
{

if(current < low_val[temp])

low_val[temp] = current;

if(current > high_val[temp])

high_val[temp] = current;
}

/* Send the EOI to the interrupt controller to re-arm for next interrupt */
outportb(0x20,0x20);

}

8 APPENDIX E

PCM-A/D Sche matic Dia grams

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

|LINK
|PCMAD122.sch

+

ECO 95-75
8-11-95 REV. TO B

B

WINSYSTEMS

401-0230-000B

Thursday, July 06, 2000

1 2

B

PCM-A/D12

<Cage Code>

Size

Scale

CAGE Code

DWG NO

Rev

Sheet

of

RST

IRQ2

BD3
BD2
BD1
BD0

/MBUSY
/IOW
/IOR

IRQ7
IRQ6
IRQ5
IRQ4
IRQ3

A1
A0

/BUSY

RST DIR

/CLK
/IOW /RST
/IOR INTRQ

A1
A0

BD0
IRQ10 BD1
IRQ11 /MBUSY
IRQ12
IRQ15
IRQ14

GND

IRQ2
IRQ3
IRQ4
IRQ5 BD0
IRQ6
IRQ7 BD1
IRQ10
IRQ11 BD2
IRQ12
IRQ14 BD3
IRQ15

/CLK

INTRQ

/RST

DIR

MA0
MA1
MA2
MA3

/CS

BD0

BD1

BD2

BD3

BD4

BD5

BD6

BD7

/MA3

-V
+V

/BUSY

BA0

/CONV

VCC VCC

VCC

VCC VCC

VCC

VCC

VCC

C24
10 TANT

C19
.1

12

C22
.1

12

C13
.1

12

C18
.1

12

C21
.1

12

J10

PC104

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

IOCHCK

SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0

IOCHRDY

AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10

SA9

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

GND

GND
RESET
+5V
IRQ2

-5V
DRQ2

-12V
OWS
+12V
GND
SMEMW
SMEMR
IOW
IOR
DACK3
DRQ3
DACK1
DRQ1
DACK0
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2
T/C
BALE
+5V
OSC
GND
GND

U6

22V10

1
2
3
4
5
6
7
8

9
10
11 13

14

15

16

17

18

19

20

21

22

23

CLK
I
I
I
I
I
I
I
I
I
I I

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

J11

PC104-16

C0
C1
C2
C3
C4
C5
C6
C7
C8

C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19

D0
D1
D2
D3
D4
D5
D6
D7

D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19

D8

GND
SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MEMR
MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
KEY

GND

MEMCS16

IOCS16

IRQ10
IRQ11
IRQ12
IRQ15
IRQ14

DRQ0

DACK5

DRQ5

DACK6

DRQ6

DACK7

DRQ7

VCC

MASTER

GND
GND

DACK0

R16

1k

C25
.001

D1
BAT47

U9

74HCT688

2
4
6

8
11
13
15
17

3

5

7

9
12
14
16
18

1

19

P0
P1
P2
P3
P4
P5
P6
P7

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

G

P=Q

U8A

74HC221

14

15

1
2
3

13
4

CEXT

REXT/CEXT
A

B
CLR

Q
Q

U8B

74HC221

6

7

9
10
11

5
12

CEXT

REXT/CEXT
A

B
CLR

Q
Q

C20
.001

12

C23
.001

12

U7

74HCT245

2
3
4
5
6
7
8
9

19

1

18
17
16
15
14
13
12
11

A1
A2
A3
A4
A5
A6
A7
A8

G
DIR

B1
B2
B3
B4
B5
B6
B7
B8

R14
10K

J8

1
3
5
7
9
11
13
15

2
4
6

8
10
12
14
16

R15

2.2K

J9

1

3

5

7

9

11

13

15

2

4

6

8

10

12

14

16

17

19

21

18

20

22

U5

74HC175

4

5
12
13

9

1

2
3
7
6
10
11
15
14

D1
D2
D3
D4

CLK
CLR

Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4

RP1

10K 9P 8R

1 2

3456789

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+

+

+

+

+

+

A

WINSYSTEMS

401-0230-000B

Thursday, July 06, 2000

2 2

B

PCM-A/D12

<Cage Code>

Size

Scale

CAGE Code

DWG NO

Rev

Sheet

of

R1IN
R2IN

CH0
CH1
CH2

GND CH3

CH4
CH5
CH6
CH7

GND MA0

V+ MA1
V- MA2

CAP

GND

CH0 CH8
CH1 CH9

GND GND GND

VIN CH2 CH10

GND GND
CH3 CH11
GND GND

V+ CH4 CH12

GND GND

V- CH5 CH13

GND GND

CH6 CH14
CH8 CH7 CH15
CH9

CH10
CH11
CH12
CH13
CH14
CH15

MA0

V+ MA1
V- MA2

VIN R1IN

R2IN

CAP

V+

V-

MA0
MA1
MA2

/MA3
MA3

BD0

BD1

BD2

BD3

BD4

BD5

BD6

BD7

/CS

/BUSY

BA0

/MA3

+V

-V

/CONV

VCC

VCC

VCC

VCC

VCC

VCC

VCC

J3
1
3
5
7
9

11
13
15
17
19
21
23
25

2
4
6
8
10
12
14
16
18
20
22
24
26

U1

508A

4
5
6
7
12
11
10
9

1
16
15
214

3

13

8

IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8

A0
A1
A2
ENGND

V-

V+

OUT

R1

RESERVED

U3

508A

4
5
6
7
12
11
10
9

1
16
15
214

3

13

8

IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8

A0
A1
A2
ENGND

V-

V+

OUT

J7

1 2

C14
.1

12

R2

RESERVED

C15
.1

12

U2

INA111

3
1
8
2

6
5
7
4

VIN+

RG
RG

VIN-

VO
REF
V+
V-

R13

10K

U4

ADS7806

1

3
22
23
21
25
24

9
10
11
12
13
15
16
17

7
26

5

4
20

8
18
19 14

6

2

28

27

R1IN
R2IN
R/C
/CS
BYTE
PWRD
/BUSY

D7
D6
D5
D4
D3
D2
D1
D0

SB/BTC
REFD
REF
CAP
TAG
EXT/INT
DATACLK
SDATA DGND

AGND2

AGND1

VDIG

VANA

J1
1
3
5

2
4
6

J4

HEADER 2X8

1
3
5
7

9
11
13
15

2
4
6
8
10
12
14
16

R10

1MEG

1

R4
50K

J5

1
2
3

1
2
3

C9

2.2 TANT

C4
.1

12

C3
.1

12

R7

200

C10
10 TANT

C1
.1

12

C5
.1

12

C7
.1

12

R5

RESERVED

VR1

2CCR0515DX

1

3
10
12
13

11
14

15
22

2
23

VCC

GND
GND
GND
GND

+15V
+15V

COM
COM

-15V

-15V

R9

100

J2

1 2

R6
33K

J6

1 2

C16

10 TANT

1

R3

R12

10

C17
.1

12

R11

10

R8

100

C2

10 TANT

C12
.1

12

C11
.1

12

C8

10 TANT

C6

2.2 TANT

Telephone: [phone] . . Fax: [phone]

http://www.winsystems.com . . E-mail: [e-mail]

WARRANTY

WinSystems warrants that for a period of two (2) years from the date of shipment any Products and Software
purchased or licensed hereunder which have been developed or manufactured by WinSystems shall be free of any
material defects and shall perform substantially in accordance with WinSystems' specifications therefore. With
respect to any Products or Software purchased or licensed hereunder which have been developed or manufactured
by others, WinSystems shall transfer and assign to Custo mer any warranty of such manufacturer or developer held
by WinSystems, provided that the warranty, if any, may be assigned. The sole obligation of WinSyste ms for any
breach of warranty contained herein shall be, at its option, either (i) to repair or replace at its expense any materially
defective Products or Software, or (ii) to take back such Products and Software and refund the Customer the
purchase price and any license fees paid for the same. Customer shall pay all freight, duty, broker's fees, insurance
changes and other fees and charges for the return of any Products or Software to WinSystems under this warranty.
WinSystems shall p ay freight and insurance charges for any repaired or replaced Products or Software thereafter
delivered to Customer within the United States. All fees and costs for shipment outside of the United States shall be
paid by Customer. The foregoing warranty shall not apply to any Products or Software which have been subject to
abuse, misuse, vandalism, accidents, alteration, neglect, unauthorized repair or improper installations.

THERE ARE NO WAR RANTIES BY WINSYS TEMS EXCEPT AS STA TED HEREIN. THERE AR E NO
OTHER WARRANTIES EXPRESS OR IM PLIED IN CLUD ING, B UT NOT LIMIT ED TO, TH E IM PLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, IN NO
EVENT SHALL WINSYSTEMS BE LIABLE FOR CONSEQUENTIAL, INCIDENTAL, OR SPECIAL
DAMAGES INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR LOSS OF DATA, PROFITS OR
GOODWILL. WINSYSTEMS' MAXIMUM LIABILITY FOR ANY B REACH OF THIS AGREEM ENT OR
OTHER CLAIM RELATED TO ANY PRODUCTS, SOFTWARE, OR THE SUBJECT MATTER
HEREOF, SHALL NOT EXCEED THE PURCHASE PRICE OR LICENSE FEE PAID BY CUSTOMER
TO WINSYSTEMS FOR THE PRODUCTS OR SOFTWARE OR PORTION THEREOF TO WHICH
SUCH BREACH OR CLAIM PERTAINS.

WARRANTY SERVICE

All products returned to WinSyste ms must be assigned a Return Material Authorizatio n (RMA) number. To obtain
this number, please call or FAX WinSystems' factory in Arlington, Texas and provide the following information:

1. Description and quantity of the product(s) to be returned including its serial number.

2. Reason for the return.

3. Invoice number and date of purchase (if available), and original purchase order number.

4. Name, address, telephone and FAX number of the person making the request.

5. Do not debit WinSystems for the repair. WinSystems does not authorize d e bits.
After the RMA number is issued, please return the products promptly. Make sure the RMA number is visible on the
outside of the shipping package.

The customer must send the product freight prepaid and insured. The product must be enclosed in an anti-static bag
to protect it from damage caused by static electricity. Each bag must be completely sealed. Packing material must
separate each unit returned and placed as a cushion between the unit(s) and the sides and top of the shipping
container. WinSystems is not responsible for any damage to the product due to inadequate packaging or static
electricity.