WinSystems EBC-LP Operation Manual

OPERATIONS MANUAL

EBC-LP

NOTE: This manual has been designed and created for use as part of the WinSystems’ Technical Manuals

CD and/or the WinSystems’ website. If this manual or any portion of the manual is downloaded, co emailed, the links to additional information ( i.e. software, c able drawings) will be inopera ble.

WinSystems reserves the right to make changes in the circuitry

and specifications at any time without notice.

ied or

RE VI SION HIS TORY

P/N 403- 0306- 000B

ECO Num ber Date Code Rev Level

ORIGI NATED 030110 B 03-59 030530 B1

TABLE OF CONTENTS

Section Paragraph Title Page

Visual Index – Quick Reference i

1 General Information 1-1

1.1 Features 1-1

1.2 General Description 1-1

1.3 Specifications 1-2

2 EBC-LP Technical Reference 2-1

2.1 Introduction 2-1

2.2 Intel FW82439TX Chipset 2-1

2.3 CPU Speed Selection 2-2

2.4 Memory Installation 2-3

2.5 Interrupt Routing 2-3

2.6 Power/Reset Connections 2-4

2.7 Mouse Interface 2-4

2.8 Real Time Clock/Calendar 2-5

2.9 Keyboard Interface 2-5

2.10 Serial Interface 2-6

2.11 Parallel Printer Port 2-13

2.12 Speaker/Sound Interface 2-14

2.13 PC/104 Interface 2-14

2.14 PC/104-Plus Bus Interface 2-15

2.15 Floppy Interface 2-16

2.16 IDE Hard Disk Interface 2-16

2.17 Watchdog Timer Configuration 2-17

2.18 Status LED 2-18

2.19 Battery Selection Control 2-18

2.20 DiskOnChip Configuration 2-18

2.21 Parallel I/O 2-19

2.22 VGA Configuration 2-22

2.23 Flat Panel Output Connection 2-24

2.24 Ethernet Controller 2-25

2.25 Fan Power Connector 2-25

2.26 Multi-I/O Connector 2-26

2.27 USB Connector 2-26

Section Paragraph Title Page

3 Award BIOS Configuration 3-1

3.1 General Information 3-1

3.2 Entering Setup 3-1

3.3 Setup Main Menu 3-1

3.4 Standard CMOS Setup 3-2

3.5 BIOS Features Setup 3-7

3.6 Chipset Features Setup 3-11

3.7 Power Management 3-14

3.8 PnP/PCI Configuration 3-19

3.9 Load BIOS Defaults 3-20

3.10 Load Setup Defaults 3-21

3.11 Password Setting 3-21

3.12 IDE HDD Auto Detection 3-21

3.13 Save & Exit Setup 3-21

3.14 Exit without Saving 3-21

4 DiskOnChip Configuration 4-1

4.1 DiskOnChip Usage 4-1

5 WS16C48 Programming Reference 5-1

5.1 Introduction 5-1

5.2 Function Definitions 5-1

5.3 Sample Programs 5-6

APPENDIX A I/O Port Map APPENDIX B Interrupt Map APPENDIX C EBC-LP Mechanical Drawing APPENDIX D WS16C48 I/O Routines and Sample Program Listings APPENDIX E Cable Drawings and Software Drivers & Examples

Warranty and Repair Information

Visual Index – Quick Reference

For the convenience of the user, a copy of the Visual Index has been provided with direct links to connector and jumper configuration data.

J15 J16 PC/104

J17 Interrupt Routing Header

J28

Floppy Drive

J29 Primary Hard Drive

J32 USB

J30 Secondary Hard Drive

J27 Multi I/O

J7 Fan Power

Connectors

J4 VGA Video

FP/100

J1 RJ45 EthernetJ2 J3

PC/104 Plus

J8 Flat Panel Power

J19 J20 Parallel I/O

J25 COM3/COM4 I/O

Power Reset

J23 Mouse

J18

i EBC-LP OPERATIONS MANUAL 030530

Visual Index – Quick Reference

For the convenience of the user, a copy of the Visual Index has been provided with direct links to connector and jumper configuration data.

J11 J12 COM1 Configuration

J13 J14 COM2 Configuration

J26 Parallel I/O VCC Selection

J31 Parallel I/O Selection

J6 CPU Configuration

J5 Panel Backlight Enable

J10 Master Battery Selection

J21 COM3/4 Enable

J22 DiskOnChip Address Selection

ii EBC-LP OPERATIONS MANUAL 030530

J24 DiskOnChip Enable

1 Gen eral In for ma tion

1.1 Fea tures

n In tel Pen tium 166MMX or 266MMX CPU n PC Com pati ble uses In tel 430TX chip set n EBX- compliant board n 512KB of pipe line burst L2 cache n Up to 256MB of SDRAM n Socket for up to 288MB boota ble Disk On Chip or DIP

socket for BIOS ex ten sion sup port of Flash or ROM

n On board high reso lu tion video con trol ler with CRT on n Flat panel video support n Sup ports reso lu tions up to 1280 x 1024 n Si mul ta ne ous CRT and LCD op era tion n PC/104-Plus and PC/104 ex pan sion buses n 10/100 Mbps Eth er net us ing In tel 82559 n 4 RS-232 se rial ports with FIFO, COM1 & COM2

supports op tional RS- 422/485/J1708 sup port

n Bi- directional LPT port sup ports EPP/ECP n 48 bi- directional TTL digi tal I/O lines n USB support

1.2 Gen eral De scrip tion

The EBC-LP is a small, high- performance, em beddable com puter sys tem on a sin gle board. It in te grates a number of popu lar I/O op tions in clud ing VGA, Eth er net, Solid- State Disk, and High Density Par al lel I/O. Four PC com pati ble se rial ports are stan dard, as are the floppy, hard disk, and par al lel printer in ter faces. The EBC-LP is popu lated with ei ther an In tel Pen tium 166MMX or Intel Pentium 266MMX processor. Up to 256Mbytes of user instal la ble DIMM mem ory is sup ported. 512KB of pipe line burst, level two cache is also standard. A full 16- bit PC/104 ex pan sion bus is pro vided for fur ther ex pan sion to an en tire in dus try of add- on pe riph er als in clud ing sound and speech mod ules, SCSI con trol lers, ana log I/O mod ules, and lit er ally hun dreds of other op tions avail able from WinSystems and a va ri ety of ven dors sup port ing the PC/104 and PC/104-Plus stan dards. An on b oard 32-pin sili con disk socket sup port s the M-Systems Disk On Chip Flash mod ules in sizes rang ing from 8 Mega bytes to 288 Mega bytes.

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1.3 Speci fi ca tions

1.3.1 Elec tri cal

Bus In ter face : PC/104 8- Bit or 16- Bit ex pan sion bus

PC/104-Plus 32- bit ex pan sion bus

Sys tem Clock : 66MHz In ter rupts : TTL Level in put VCC : +5V +/- 5% at 1.6A typi cal with an In tel Pen tium 166MMX

proc es sor with 32Mb SDRAM +5V +/- 5% at 2.0A typi cal with an In tel Pen tium 266MMX

proc es sor with 32Mb SDRAM VCC1 : +12V +/-5% (Not re quired. PC/104 Ex pan sion, Flat Panel, use only) VCC2 : -12V +/-5% (Not required. PC/104 Ex pan sion or Flat Panel use only) VCC3 : 3.3V (Not re quired. PC/104- Plus Ex pan sion only)

1.3.2 Mem ory

Ad dress ing : 256 Mega byte ad dress ing BIOS ROM : 128K Flash Mem ory DIMM Socket : 168-pin 3.3V Dimm Mod ule; PC-66 or PC-100 SDRAM Mod ule. SSD Mem ory : One 32- pin JE DEC stan dard socket sup port ing the M- Systems 32- Pin DOC

(Disk On Chip) mod ule.

1.3.3 Me chani cal

Di men sions : 5.75 X 8.0 (with out PC/104 mod ules or ca bles) PC- Board : FR4 Ep oxy Glass with 5 sig nal lay ers and 3 power planes with screened

com po nent leg end and plated through holes. Jump ers : 0.025" square posts on 0.100" cen ters Con nec tors : Multi I/O : 50-pin RN type IDH- 50LP

COM3/COM4 : 20- pin RN type IDH- 20LP

Floppy Disk : 34-pin RN type IDH- 34- LP

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CRT : 14-pin 2mm Mo lex Type 87331-1420 Flat Panel : Two, 50-pin 2mm Mo lex type 87331-5020 Power/Re set : 9-pin in- line Mo lex type 26- 60- 7091

Fan Power : 3-pin in- line Mo lex type 22- 11- 2032

Mouse : 5-pin in- line latch ing Mo lex type 22- 11- 2052 USB : 4-pin in- line latch ing Mo lex type 22-11-2042 PC/104 Bus : 64-Pin SAM TEC type ESQ- 132- 12- G-D

40-Pin SAM TEC type ESQ- 120- 12- G-D

PC/104- Plus Bus : 120-Pin SAM TEC type TS- 30-Q

IDE : Two 40-pin 2mm Mo lex Type 70246-4021

1.3.4 En vi ron men tal :

Op er at ing Tem pera ture : -40° to +85° C us ing Pen tium 166 MHz

-40° to +60° C us ing Pen tium 266 MHz

Non- condensing rela tive hu mid ity : 5% to 95%

030530 EBC-LP OPERATIONS MANUAL Page 1-3

2 EBC-LP Tech ni cal Ref er ence

2.1 In tro duc tion

This sec tion of the man ual is in tended to pro vide suf fi cient in for ma tion re gard ing the con figu ra tion and us age of the EBC-LP board. WinSystems main tains a Tech ni cal Sup port group to help an swer ques tions re gard ing con figu ra tion, us age, or pro gram ming of the board. For an swers to ques tions not ade quately ad dressed in this man ual, con tact Tech ni cal Sup port at (817) 274- 7553 be tween 8AM and 5PM Cen tral Time.

2.2 Intel FW82439TX Chipset

The EBC-LP util izes the Intel FW82439TX Chipset which pro vides a highly- integrated, high performance back bone for full Pentium class com pati bil ity. The Chipset con tains the logic for DRAM and bus state con trol as well as the stan dard com ple ment of 'AT' class pe riph er als, in clud ing :

Two-82C37 DMA con trol lers

Two-82C59 In ter rupt controllers

82C54 Timer/Counter

Real Time Clock

En hanced Power Man age ment

Full Plug and Play compatibility

These func tional units are 100% PC/AT com pati ble and are sup ported by the Award BIOS and setup. Us ers de sir ing to ac cess these in ter nal pe riph er als di rectly should ref er to any manu fac tur ers ge neric lit era ture on the equiva lent dis crete com po nent.

There are a number of in ter nal reg is ters within the Intel TX chipset that are used by the BIOS for con trol and con figu ra tion. Ref er to the I/O map in Ap pen dix A for port us age to avoid con f licts when add ing ex ter nal I/O de vices.

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2.3 CPU Speed Se lec tion

3 2 1 o o o

CPU Speed Select Jumper J6

The EBC-LP uses a crystal controlled frequency synthesizer to control the base CPU clock

frequency. The processors available from WinSystems and the jumpering for them are shown below.

3 2 1 o o o

Pentium 166MHz MMX

3 2 1 o o o

Pentium 266MHz MMX

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2.4 Mem ory In stal la tion

The EBC-LP supports a single, user-instal la ble 168- pin stan dard DIMM. DIMM mod ules should be a minimum speed of PC-66 or PC-100 and x64 as there is no sup port for the par ity or ECC bits pro vided by x72 bit mod ules. A sin gle DIMM socket is pro vided which can sup port SDRAM sizes from 32MB to 256MB. For a list of qualified DIMMs, go to http://www.winsystems.com/memory.

In stal la tion is ac com plished with power off by in sert ing the DIMM module directly into the con nec tor at M1. The DIMM mod ule is keyed in 2 places and can not be in serted back wards with o ut ex treme force. The module is inserted un til the re tain ing clips snap into place. Re moval is the re verse pro cess. Push down on the re tain ing clips, moving them out ward. The DIMM mod ule, once re leased, will be forced up to an appropriate removal position.

2.5 In ter rupt Rout ing

21 19 17 15 13 11 9 7 5 3 1 o o o o o o o o o o o

o o o o o o o o o o o

22 20 18 16 14 12 10 8 6 4 2

J17 Interrupt Routing Header

All in ter rupts on the EBC-LP are routed to their re spec tive PC/104 bus pins. On board non-PnP pe riph er als, are routed to their typi cal us age in ter rupts us ing the jumper block at J17. This block al lows dis con nect ing or re rout ing of the on board in ter rupts. The lay out for the J17 header and the de fault jumper set tings are shown below.

J17

NC NC

22 o o 21 20 o o 19 18 o o 17 16 o o 15 14 o o 13 12 o o 11 10 o o 9 8 o o 7 6 o o 5 4 o o 3 2 o o 1

IRQ9 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 IRQ6 IRQ7 IRQ5 IRQ4 IRQ3

COM4 16C48 COM3 COM4

SECONDARYHD

PRIMARYHD

COM3

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2.6 Power/Reset Connections

J18 o 1

o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9

J23 o 1

o 2 o 3 o 4 o 5

Power is ap plied to the EBC-LP via the con nec tor at J18 (Mo lex part number 26- 60- 7091). The pin

defi ni tions for J18 are given be low. An op tional push- button- reset (Normally Open) may also be routed into J18 if de sired. Momentary closure to ground forces a hardware reset.

J18 o 1

+5V

o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9

GND GND

+12V

+3.3V

GND

-12V

PB Reset

2.7 Mouse Interface

A PS/2 mouse may be attached via the connector at J23. An adapter cable, CBL-225-1, is available

from WinSystems to adapt to a conventional PS/2 mouse connector. The pinout for J23 is shown here.

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J23

1 o 2 o 3 o 4 o 5 o

MSDATA N/C GND VCC MSCLK

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2.8 Real Time Clock/Cal en dar

J10

3 2 1 o o o

Master Battery Select Jumper J10

The EBC-LP con tains an on board Clock/Cal en dar within the PIIX4E chip. This clock is fully com pati ble with the MC146818A used in the origi nal PC- AT com put ers. This clock has a number of fea tures in clud ing pe ri odic and alarm in ter rupt ca pa bili ties. In ad di tion to the time and date keep ing func tions, the sys tem con figu ra tion is kept within the CMOS RAM con tained in the clock sec tion. This RAM holds all of the setup in for ma tion re gard ing hard and floppy disk types, video type, shad owing, wait states, etc. Ref er to the sec tion on the Award BIOS Setup for what is con fig ured via the CMOS RAM.

It may be come nec es sary at some time to make the CMOS RAM for get its cur rent con figu ra tion and to start fresh with fac tory de faults. This may be ac com plished by re mov ing power from the board . Then re move the jumper from pins 2-3 on J10 and place on pins 1-2 for 10 seconds. Re place the jumper on J10 pins 2-3, power- up, and re con fig ure the CMOS set tings as de sired.

2.9 Key board In ter face

The EBC-LP con tains an on board PS/2 style key board con trol ler. Key board con nec tion is made through the Multi-I/O con nec tor at J27. An adapter ca ble P/N CBL-2 47-1 is avail able from WinSystems to make ready ac cess to all of the de vices ter mi nated at the Multi-I/O con nec tor. Us ers de sir ing cus tom con nec tions should ref er to the Multi-I/O con nec tor pin defi ni tions given later in this man ual.

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2.10 Se rial In ter face

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J21

3 o o 1 4 o o 2

J11

U25

1 o 2 o 3 o

U28 U30U29

o o o

3 2 1

U24U26

J12

J13

1 o 2 o 3 o

o o o

3 2 1

J14

The EBC-LP pro vides four 16550 com pati ble RS- 232 se rial ports at the fol low ing ad dresses :

COM1 3F8H at IRQ 4 (PnP Device) COM2 2F8H at IRQ 3 (PnP Device) COM3 3E8H* at IRQ 5** COM4 2E8H* at IRQ 9**

*COM ports 3 and 4 can be en abled or dis abled in di vidu ally via the jumper block at J21. When J21

pins 1-2 are jumpered, COM3 is en abled. When J21 pins 3-4 are jumpered, COM4 is en abled.

**The in ter rupts are not dis con nected when COM3 or COM4 are dis abled. Use the in ter rupt

rout ing block J17 de scribed ear lier to dis con nect the de fault in ter rupts if de sired.

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The two pri mary se rial ports, COM1 and COM2 are con fig ur able for RS- 422, RS- 485 or J1708, with the ad di tion of op tional driver ICs. The con figu ra tion op tions for each of the sup ported modes are shown on the fol low ing pages. Connection to COM1 and COM2 is made through the Multi-I/O connector at J27. An adapter cable (P/N CBL-247-1) is available from WinSystems’ to adapt to standard DB9 connectors.

COM1 - RS- 232

COM1 DB9

J11 J12

3 2 1

o o o

1 2 3

o o o

U24 - In stalled U25 - Not In stalled U26 - Not In stalled

RX Data

TX Data

DTR

GND

1 o o 6 2 o o 7 3 o o 8 4 o o 9 5 o

DSR RTS CTS RI

COM2 - RS- 232

COM2 DB9

J13 J14

3 2 1

o o o

1 2 3

o o o

U28 - In stalled U29 - Not In stalled U30 - Not In stalled

RX Data

TX Data

DTR

GND

1 o o 6 2 o o 7 3 o o 8 4 o o 9 5 o

DSR RTS CTS RI

COM3/COM4 - RS- 232

COM3 and COM4 are RS- 232 only and are ter mi nated at J25. An adapter ca ble is avail able from WinSystems (P/N CBL-173-1), which adapts J25 to two stan dard DB9M con nec tors. The pin defi ni tions for J25 are shown here :

030530 EBC-LP OPERATIONS MANUAL Page 2-7

COM3 DCD

COM3 RX

COM3 TX

COM3 DTR

GND

COM4 DCD

COM4 RX

COM4 TX

COM4 DTR

GND

J25

1 o o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 11 o o 12 13 o o 14 15 o o 16 17 o o 18 19 o o 20

COM3 DSR COM3 RTS COM3 CTR COM3 RI N/C COM4 DSR COM4 RTS COM4 CTS COM4 RI N/C

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2.10.1 RS- 422 Mode Con figu ra tion

RS- 422 lev els are sup ported on both COM1 and COM2 with the in stal la tion of the op tional “Chip

Kit”, WinSystems part number CK- 75176-2. This kit pro vides the driver ICs nec es sary for a sin g le chan nel of RS- 422. If two chan nels of RS- 422 are re quired then two kits will be needed. RS- 422 is a 4- wire point-to-point full- duplex in ter face al low ing much longer ca ble runs than are pos si ble with RS-

232. The dif fer en tial trans mit ter and re ceiver twisted pairs of fer a high de gree of noise im mu nity. RS 422 usu ally re quires the lines be ter mi nated at both ends. This ter mi na tion can be ac com p lished ei ther on the ca ble or by in stall ing re sist ers on the board in lo ca tions re served for them. The method for de ter min ing the cor rect re sis tor val ues is be yond the scope of this docu ment but it is rec om mended that trial val ues of 100 ohms be used in all three lo ca tions at the re ceiver end. The fol low ing il lus tra tion shows the cor rect mode jump er ing, driver IC in stal la tion, I/O con nec tor pin defi ni tions, and ter mi na tion re sis tor lo ca tions for each of the chan nels when used in RS- 422 mode.

COM1 - RS- 422

COM1 DB9

J11 J12

3 2 1

o o o

1 2 3

o o o

U24 - Not In stalled U25 - In stalled U26 - In stalled

N/C

TX+

TX-

N/C

GND

1 o o 6 2 o o 7 3 o o 8 4 o o 9 5 o

RX+ RXN/C N/C

RS- 422 NOTE : When used in RS- 422 mode,

VCC

the trans mit ter must be en abled by set ting the RTS bit in the Mo dem Con trol Reg is ter (Bit1).

R17

RX+

R14

RX-

R11

* Important Note: All serial termination

components are surface mount 0805 packages. These should only be installed by surface mount qualified individuals.

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COM2 - RS- 422

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COM2 DB9

J13 J14

3 2 1

o o o

1 2 3

o o o

U28 - Not In stalled U29 - In stalled U30 - In stalled

N/C

TX+

TX-

N/C

GND

1 o o 6 2 o o 7 3 o o 8 4 o o 9 5 o

RX+ RXN/C N/C

RS- 422 NOTE: When used in RS- 422 mode,

VCC

the trans mit ter must be en abled by set ting the RTS bit in the Mo dem Con trol Reg is ter (Bit1).

R29

RX+

R31

TX-

R32

Important Note: All serial termination components are surface mount 0805 packages. These should only be installed by surface mount qualified individuals.

2.10.2 RS- 485 Mode Con figu ra tion

The RS- 485 Multi- drop in ter face is sup ported on both chan nels with the in stal la tion of the op tional “Chip Kit”, WinSystems’ part number CK- 75176-2. A sin gle kit is suf fi cient to con fig ure both chan nels for RS- 485. RS- 485 is a 2- wire multi- drop in ter face where only one sta tion at a time talks (trans mits) while all oth ers lis ten (re ceive). RS- 485 usu ally re quires the twisted pair be ter mi nated at each end of the run. The re quired ter mi na tion val ues are de pend ent upon a number of fac tors in clud ing: line im ped ance, line length, etc. A good trial value is 100 ohms in all three re sis tor lo ca tions. The fol low ing il lus tra tions show the cor rect jump er ing, driver IC in stal la tion, I/O con nec tor pin out, and ter mi na tion re sis tor lo ca tions for each of the chan nels when used in RS- 485 mode.

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COM1 - RS- 485

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COM1 DB9

J11 J12

3 2 1

o o o

VCC

R17

R14

R11

1 2 3

o o o

TX/RX+

TX/RX-

U24 - Not In stalled U25 - In stalled U26 - Not In stalled

N/C

TX/RX+

TX/RX-

N/C

GND

1 o o 6 2 o o 7 3 o o 8 4 o o 9 5 o

N/C N/C N/C N/C

RS- 485 NOTE : Be cause RS- 485 uses a sin gle

twisted- pair, all trans mit ters are con nected in par al lel. Only one sta tion at a time may trans mit or have its trans mit ter en abled. The trans mit ter En able/Dis able is con trolled in soft ware us ing bit 1 in the Mo dem Con trol Reg is ter (RTS). When RTS is set, the trans mit ter is en abled, and when cleared (the nor mal state) the trans mit ter is dis abled and the re ceiver is en abled. Note that it is nec es sary to al low some mini mal set tling time af ter ena bling the trans mit ter bef ore trans mit ting the first char ac ter. Like wise, fol low ing a trans mis sion, it is nec es sary to be sure that all char ac ters have been com pletely shifted out of the UART (Check Bit 6 in the Line Status Reg is ter) bef ore dis abling the trans mit ter to avoid chop ping off the last char ac ter.

Important Note: All serial termination components are surface mount 0805 packages. These

should only be installed by surface mount qualified individuals.

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COM2 - RS- 485

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COM2 DB9

J13 J14

3 2 1

o o o

VCC

R29

R31

R32

1 2 3

o o o

TX/RX+

TX/RX-

U28 - Not In stalled U29 - In stalled U30 - Not In stalled

N/C

TX/RX+

TX/RX-

N/C

GND

1 o o 6 2 o o 7 3 o o 8 4 o o 9 5 o

N/C N/C N/C N/C

RS- 485 NOTE : Be cause RS- 485 uses a sin gle

Important Note : All serial termination components are surface mount 0805 packages. These should only be installed by surface mount qualified individuals.

2.10.3 SAE J1708 Con figu ra tion

The So ci ety of Auto mo tive En gi neers (SAE) J1708 in ter face is a varia tion of the RS- 485 in ter face which is used for “Se rial Data Com mu ni ca tions be tween Mi cro com puter Sys tems in Heavy Duty Ve hi cle Ap pli ca tions”. It is be yond the scope of this docu ment to go into de tail on the J1708 speci fi ca tion. The EBC-LP may be user con fig ured for J1708 by the ad di tion of the CK- 75176-2 “Chip Kit”. One “Chip Kit” is suf fi cient to con fig ure both chan nels for J1708. The il lus tra tions that fol low show the cor rect jump er ing, driver IC in stal la tion, I/O con nec tor pin defi ni tions, and the ter mi na tion net work de tails for each of the chan nels when used in J1708 mode.

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COM1 - J1708

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COM1 DB9

J11 J12

3 2 1

o o o

VCC

R23

4.7K

R18 Absent

R22

4.7K

COM2 - J1708

1 2 3

o o o

R20 47 ohm

C46 .0022 uf C47 .0022 uf

R21 47 ohm

U24 - Not In stalled U25 - In stalled U26 - Not In stalled

TX/RX+

TX/RX-

N/C

TX/RX+

TX/RX-

N/C

GND

1 o o 6 2 o o 7 3 o o 8 4 o o 9 5 o

N/C N/C N/C N/C

R24

4.7K

R30 Absent

R26

4.7K

J13 J14

3 2 1

o o o

VCC

1 2 3

o o o

R28 47 ohm

C50 .0022 uf C49 .0022 uf

R27 47 ohm

U28 - Not In stalled U29 - In stalled U30 - Not In stalled

TX/RX+

TX/RX-

N/C

TX/RX+

TX/RX-

N/C

GND

COM2 DB9

1 o o 6 2 o o 7 3 o o 8 4 o o 9 5 o

N/C N/C N/C N/C

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2.11 Par al lel Printer Port

J27 Multi-I/O Connector

The EBC-LP sup ports a fully bi- directional par al lel printer port ca pa ble of EPP and ECP op era tions. The PnP par al lel port is mapped at 378H and is ter mi nated at the Multi-I/O con nec tor at J27 (pinout shown on page 2-26). The pin defi ni tions for the par al lel port DB25 con nec tor when us ing the CBL- 247-1 cable are shown be low:

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

ACK

SLCT

1 o o 14 2 o o 15 3 o o 16 4 o o 17 5 o o 18 6 o o 19 7 o o 20 8 o o 21 9 o o 22 10 o o 23 11 o o 24 12 o o 25 13 o

AUTOFD ERROR INIT SLIN GND GND GND GND GND GND GND GND

STROBE

BUSY

030530 EBC-LP OPERATIONS MANUAL Page 2-13

WinSystems - "The Embedded Authority"

2.12 Speaker/Sound In ter face

The EBC-LP util izes a high- impedance piezo type de vice for audio out put. BIOS beep codes, er ror

sig nal ing, or user-de fined tones can be pre sented via this de vice.

2.13 PC/104 Bus In ter face

The EBC-LP sup ports I/O ex pan sion through the stan dard PC/104 con nec tors at J15 and J16. The

EBC-LP sup ports both 8- bit and 16- bit PC/104 mod ules. The PC/104 con nec tor pin defi ni tions are pro vided here for ref er ence pur poses.

GND

RESET

+5V

IRQ9

-5V

DRQ2

-12V 0WS

+12V

GND

MEMW*

MEMR*

IOW*

IOR*

DACK3*

DRQ3

DACK1*

DRQ1

REFRESH*

SYSCLK

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3

DACK2*

BALE

+5V

OSC GND GND

J15

B1 o o A1 B2 o o A2 B3 o o A3 B4 o o A4 B5 o o A5 B6 o o A6 B7 o o A7 B8 o o A8 B9 o o A9 B10 o o A10 B11 o o A11 B12 o o A12 B13 o o A13 B14 o o A14 B15 o o A15 B16 o o A16 B17 o o A17 B18 o o A18 B19 o o A19 B20 o o A20 B21 o o A21 B22 o o A22 B23 o o A23 B24 o o A24 B25 o o A25 B26 o o A26 B27 o o A27 B28 o o A28 B29 o o A29 B30 o o A30 B31 o o A31 B32 o o A32

IOCHK* BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 GND

GND

SBHE*

LA23 LA22 LA21 LA20 LA19 LA18 LA17

MEMR*

MEMW*

SD8

SD9 SD10 SD11 SD12 SD13 SD14 SD15

KEY

J16

C0 o o D0 C1 o o D1 C2 o o D2 C3 o o D3 C4 o o D4 C5 o o D5 C6 o o D6 C7 o o D7 C8 o o D8 C9 o o D9 C10 o o D10 C11 o o D11 C12 o o D12 C13 o o D13 C14 o o D14 C15 o o D15 C16 o o D16 C17 o o D17 C18 o o D18 C19 o o D19

GND MEMCS16* IOCS16* IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0* DRQ0 DACK5* DRQ5 DACK6* DRQ6 DACK7* DRQ7 VCC MASTER* GND GND

Page 2-14 EBC-LP OPERATIONS MANUAL 030530

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2.14 PC/104-Plus Bus In ter face

The EBC-LP sup ports I/O ex pan sion through the stan dard PC/104-Plus con nec tor at J9. The EBCLP sup ports PC/104-Plus mod ules. The PC/104-Plus con nec tor pin defi ni tions are pro vided here for ref er ence pur poses.

Pin A B C D

1 GND/5.0 KEY Re served +5 AD00 2 VI/O AD02 AD01 +5V 3 AD05 GND AD04 AD03 4 C/BE0* AD07 GND AD06 5 GND AD09 AD08 GND 6 AD11 VI/O AD10 M66EN 7 AD14 AD13 GND AD06 8 +3.3V C/BE1* AD15 +3.3V

9 10 GND PERR* +3.3V SDONE 11 STOP* +3.3V LOCK* GND 12 +3.3V TRDY* GND DEVSEL* 13 FRAME* GND IRDY* +3.3V 14 GND AD16 +3.3.V 15 AD18 +3.3V AD17 GND 16 AD21 AD20 GND AD19 17 +3.3V AD23 AD22 +3.3V 18 ID SEL0 GND ID SEL1 ID SEL2 19 AD24 C/BE3* VI/O ID SEL3 20 GND AD26 AD25 GND 21 AD29 +5V AD28 AD27 22 +5V AD30 GND AD31 23 REQ0* GND REQ1* VI/O 24 GND REQ2* +5V GNT0* 25 GNT1* VI/O GNT2* GND 26 +5V CLK0 GND CLK1 27 CLK2 +5V CLK3 GND 28 GND INTD* +5V RST* 29 +12V INTA* INTB* INTC* 30 -12V Re served Re served GND/3.3V KEY

SERR*

GND SB0* PAR

C/BE3*

Notes : 1. The shaded area de notes power and ground sig nals.

030530 EBC-LP OPERATIONS MANUAL Page 2-15

WinSystems - "The Embedded Authority"

2.15 Floppy Disk In ter face

The EBC-LP sup ports up to 2 stan dard 3 1/2" or 5 1/4" PC com pati ble floppy disk drives. The drives are con nected via the I/O con nec tor at J28. Note that the in ter con nect ca ble to the drives is a stan dard floppy I/O ca ble used on desk- top PCs. The ca ble must have the twisted sec tion prior to the drive A po si tion. The pin defi ni tions for the J28 con nec tor are shown here:

J28

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

1 o o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 11 o o 12 13 o o 14 15 o o 16 17 o o 18 19 o o 20 21 o o 22 23 o o 24 25 o o 26 27 o o 28 29 o o 30 31 o o 32 33 o o 34

RPM/LC N/C N/C INDEX MTR0 DRV1 DRV0 MTR1 DIR STEP WDATA WGATE TRK0 WPRT RDATA HDSEL DSKCHG

2.16 IDE Hard Disk In ter face

The EBC-LP sup ports stan dard IDE fixed disks through the I/O con nec tors at J30 (primary) and J29 (secondary). A red ac tiv ity LED is pres ent at D6 and D8 for the primary and secondary hard drive controllers respectively. The pin defi ni tions for J29 and J30 are shown here:

J29 and J30

RST

D7 D6 D5 D4 D3 D2 D1 D0

LED

DRQ

IOW

IOR

RDY

DACK

IRQ

A1 A0

CS1

VCC

1 o o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 11 o o 12 13 o o 14 15 o o 16 17 o o 18 19 o o 20 21 o o 22 23 o o 24 25 o o 26 27 o o 28 29 o o 30 31 o o 32 33 o o 34 35 o o 36 37 o o 38 39 o o 40

GND D8 D9 D10 D11 D12 D13 D14 D15 N/C GND GND GND NC GND NC NC A2 CS3 GND

Page 2-16 EBC-LP OPERATIONS MANUAL 030530

WinSystems - "The Embedded Authority"

2.17 Watch dog Timer Con figu ra tion

The EBC-LP features a power-on voltage detect and power-down/power brown-out reset circuit to protect memory and I/O from faulty CPU operation during periods of illegal voltage levels. The supervisor circuitry also features a watchdog timer which can be used to guard against software lockups. An internal timer with a period of 1.5 seconds will, when enabled, reset the CPU if the watchdog has not been serviced within the allotted time.

The watchdog timer powers up disabled and must be enabled in software before timing will begin. Enabling is accomplished by writing a 1 to I/O port 1EEH. Writing a 0 to I/O port 1EEH will disable the watchdog. After enabling, petting may be accomplished by writing any value to port 1EFH at least every 1.5 seconds or a reset will occur. This mode of operation can be used with the BIOS or DOS provided that the watchdog is disabled before making any extensive BIOS or DOS calls, especially video or Disk I/O calls which could exceed the 1.5 seconds allowed. The drawback to this mode is that a lockup dur ing the time the watch dog is dis abled will not al low for auto- recovery and will re q uire an ex ter nal re set.

030530 EBC-LP OPERATIONS MANUAL Page 2-17

WinSystems - "The Embedded Authority"

2.18 Status LED

A green LED is popu lated on the board at D7 which can be used for any ap pli ca tion spe cific

pur pose. The LED can be turned on in soft ware by writ ing a 1 to I/O port 1EDH. The LED can be turned off by writ ing a 0 to 1EDH.

2.19 Bat tery Se lect Con trol

An on board 350mAH nomi nal ca pac ity, lith ium bat tery is pro vided for the CMOS Clock/Cal en dar.

A mas ter bat tery en able jumper is pro vided at J10. When J10 is jumpered pins 2-3, bat tery power is sup plied to the Clock/Cal en dar. When J10 is jumpered pins 1-2, the bat tery is to tally dis con nected and no cur rent will be drawn from it. Bat tery life is highly de pend ent upon duty cy cle as there is no cur rent drawn from the bat tery when +5 volts is ap plied to the board. Both stor age and op era tional tem pera tures play a promi nent fac tor in bat tery life. High tem pera tures will shorten bat tery life sig nifi cantly. J10 must be jumpered 1-2 if a bat tery is not installed.

2.20 DiskOnChip Con figu ra tion

The EBC-LP sup ports the use of M-Systems Disk On Chip (DOC) de vice to be used as Solid State

Disk (SSD) drive. Sec tion 4 of this man ual pro vides the nec es sary in for ma tion for the gen e ra tion and us age of the DOC drives. This sec tion docu ments the re quired hard ware con figu ra tions for the DOC devices. The 32- pin JE DEC mem ory sock et at U17 is used to con tain the DOC de vices used for the disk. The sili con disk ar ray is mem ory mapped into a 32Kbyte hole at seg ment D000 or D800.

2.20.1 DiskOnChip Enable

The DiskOnChip can be enabled by jumpering J22 and J24 as shown below. The jumper positions

for J22 and J24 are shown on the following page :

Note : J22 is BIOS write, and must be jumpered 1-2 at all times for proper Plug and Play

operation.

J24

2 o 1 o

DiskOnChip Enabled

J22

2 o o 1

4 o o 3

DiskOnChip Disabled

J24 2 o

1 o

J22

2 o o 1

4 o o 3

DOC at D000:0000

Page 2-18 EBC-LP OPERATIONS MANUAL 030530

DOC at D800:0000

2.21 Par al lel I/O

WinSystems - "The Embedded Authority"

J22

3 o o 1 4 o o 2

J24

o 1 o 2

DiskOnChip Enable jumpers J22 and J24

J26

o 1 o 2

J31

o 1 o 2

Parallel I/O configuration Jumpers J26 and J31

The EBC-LP util izes the WinSystems WS16C48 ASIC high- density I/O chip mapped at a base ad dress of 120H. The first 24 lines are ca pa ble of fully latched event sens ing with sense po lar ity be ing soft ware pro gram ma ble. Two, 50- pin con nec tors al low for easy mat ing with in dus try stan d ard I/O racks. The pin-out for the two connectors are shown on the next page.

2.21.1 Par al lel I/O En able

The par al lel fea tures of the EBC-LP can be en abled or dis abled us ing the jumper block at J31. When J31 is jumpered the par al lel I/O is en abled at I/O ad dress 120H. When J31 is open, the 16 ad dresses start ing at I/O ad dress 120H are free for use by other de vices.

2.21.2 Par al lel I/O Con nec tors

The 48 lines of par al lel I/O are ter mi nated through two, 50- pin con nec tors at J19 and J20. The J20 con nec tor han dles I/O ports 0-2 while J19 han dles ports 3-5. The pin defi ni tions for J19 and J20 are shown on the fol low ing page.

030530 EBC-LP OPERATIONS MANUAL Page 2-19

2.21.3

WinSystems - "The Embedded Authority"

J20

+5V

1 o o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 11 o o 12 13 o o 14 15 o o 16 17 o o 18 19 o o 20 21 o o 22 23 o o 24 25 o o 26 27 o o 28 29 o o 30 31 o o 32 33 o o 34 35 o o 36 37 o o 38 39 o o 40 41 o o 42 43 o o 44 45 o o 46 47 o o 48 49 o o 50

Port 2 Bit 7 Port 2 Bit 6 Port 2 Bit 5 Port 2 Bit 4 Port 2 Bit 3 Port 2 Bit 2 Port 2 Bit 1 Port 2 Bit 0 Port 1 Bit 7 Port 1 Bit 6 Port 1 Bit 5 Port 1 Bit 4 Port 1 Bit 3 Port 1 Bit 2 Port 1 Bit 1 Port 1 Bit 0 Port 0 Bit 7 Port 0 Bit 6 Port 0 Bit 5 Port 0 Bit 4 Port 0 Bit 3 Port 0 Bit 2 Port 0 Bit 1 Port 0 Bit 0

Par al lel I/O VCC En able

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Port 5 Bit 7 Port 5 Bit 6 Port 5 Bit 5 Port 5 Bit 4 Port 5 Bit 3 Port 5 Bit 2 Port 5 Bit 1 Port 5 Bit 0 Port 4 Bit 7 Port 4 Bit 6 Port 4 Bit 5 Port 4 Bit 4 Port 4 Bit 3 Port 4 Bit 2 Port 4 Bit 1 Port 4 Bit 0 Port 3 Bit 7 Port 3 Bit 6 Port 3 Bit 5 Port 3 Bit 4 Port 3 Bit 3 Port 3 Bit 2 Port 3 Bit 1 Port 3 Bit 0

+5V

J19

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

The I/O con nec tors can pro vide +5 volts to an I/O rack or for mis cel la ne ous pur poses by jump er ing

J26. When J26 is jumpered +5 volts is pro vided at pin 49 of both J19 and J20. It is the user's re spon si bil ity to limit cur rent to a safe value (less than 1A) to avoid dam ag ing the CPU board.

2.21.4 WS16C48 Reg is ter Defi ni tions

The EBC-LP uses the WinSystems ex clu sive ASIC de vice, the WS16C48. This de vice pro vides 48

lines of digi tal I/O. There are 17 unique reg is ters within the WS16C48. The fol low ing ta ble sum ma rizes the reg is ters and the text that fol lows pro vides de tails on each of the in ter nal reg is ters.

Page 2-20 EBC-LP OPERATIONS MANUAL 030530

WinSystems - "The Embedded Authority"

I/O Ad dress

Off set

00H Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O 01H Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O 02H Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O 03H Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O 04H Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O 05H Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O 06H Int_Pend ing Int_Pend ing Int_Pend ing Int_Pend ing 07H Page/Lock Page/Lock Page/Lock Page/Lock 08H N/A Pol_0 Enab_0 Int_ID0 09H N/A Pol_1 Enab_1 Int_ID1

0AH N/A Pol_2 Enab_2 Int_ID2

Page 0 Page 1 Page 2 Page 3

Reg is ter De tails

Port 0-5 I/O - Each I/O bit in each of the 6 ports can be in di vidu ally pro grammed for in put or

out put. Writing a ‘0’ to a bit position causes the corresponding output pin to go to a High-Impedance state (pulled high by external 10K ohm resistors). This al lows it to be used as an in put. When used in the in put mode, a read re flects the in verted state of the I/O pin, such that a high on the pin will read as a '0' in the reg is ter. Writ ing a '1' to a bit po si tion causes the out put pin to sink cur rent (up to 12mA), ef fec tively pull ing it low.

INT_PEND ING - This read- only reg is ter re flects the com bined state of the INT_ID0 through INT_ID2 reg is ters. When any of the lower 3 bits are set, it in di cates that an in ter rupt is pend ing on the I/O port cor re spond ing to the bit po si tion(s) that are set. Read ing this reg is ter al lows an In ter rupt Serv ice Rou tine to quickly de ter mine if any in ter rupts are pend ing and which I/O port has a pend ing in ter rupt.

PAGE/LOCK - This reg is ter serves two pur poses. The up per two bits se lect the reg is ter page in use as shown here:

D7 D6 Page

0 0 Page 0

0 1 Page 1

1 0 Page 2

1 1 Page 3

Bits 5-0 al low for lock ing the I/O ports. A '1' writ ten to the I/O port po si tion will pro hibit fur ther writes to the cor re spond ing I/O port.

030530 EBC-LP OPERATIONS MANUAL Page 2-21

WinSystems - "The Embedded Authority"

POL0- POL2 - These reg is ters are ac ces si ble when page 1 is se lected. They al low in ter rupt po lar ity

se lec tion on a port- by- port and bit- by- bit ba sis. Writ ing a '1' to a bit po si tion se lects the ris ing edge de tec tion in ter rupts while writ ing a '0' to a bit po si tion se lects fal ling edge de tec tion in ter rupts.

ENAB0- ENAB2 - These reg is ters are ac ces si ble when page 2 is se lected. They al low for port- by-

port and bit- by- bit ena bling of the edge de tec tion in ter rupts. When set to a '1' the edge de tec tion in ter rupt is en abled for the cor re spond ing port and bit. When cleared to a '0' the bit's edge de tec tion in ter rupt is dis abled. Note that this reg is ter can be used to in di vidu ally clear a pend ing in ter rupt by dis abling and reena bling the pend ing in ter rupt.

INT_ID0 - INT_ID2 - These reg is ters are ac ces si ble when page 3 is se lected. They are used to

iden tify cur rently pend ing edge in ter rupts. A bit when read as a '1' in di cates that an edge of the po lar ity pro grammed into the cor re spond ing po lar ity reg is ter has been rec og nized. Note that a write to this reg is ter (value ig nored) clears ALL of the pend ing in ter rupts in this reg is ter.

2.22 VGA Con figu ra tion

The EBC-LP uses a fourth generation CRT/Flat panel Super VGA controller. It supports standard

VGA output as well as a variety of Flat Panel Displays using optional Flat Panel Adapter (FPA) kits. The video on the EBC-LP uses the Asiliant 69000 series of high performance VGA controllers. The Asiliant controller supports standard and super-VGA as well as Color and Monochrome panels with 8, 9, 12, 15, 16, 18, 24 and 36-bit interfaces. WinSystems provides flat panel support through a series of Flat Panel kits. Contact your WinSystems Applications Engineer for the most current list of available FPA’s and supported panels.

Details regarding interfacing to specific Flat Panels is not provided in this manual but should be

referenced in the documentation accompanying the FPA kit. Attempted connection to any flat panel not directly supported by a WinSystems FPA module is at the user’s risk and extreme care should be exercised to avoid damaging or destroying the panel.

HAZARD WARNING: LCD panels can require a high voltage for the panel backlight. This high-

frequency voltage can exceed 1000 volts and can present a shock hazard. Care should be taken when wiring or handling the inverter output. To avoid danger of shock and to avoid damaging fragile and expensive panels, make all connection changes with power removed.

Note: J5 must be jumpered 1-2 for Sharp type panels, and 2-3 for NEC type panels. Jumper

positioning is shown on the following page. An example jumpering for NEC panels is shown below.

Page 2-22 EBC-LP OPERATIONS MANUAL 030530

o 1 o 2 o 3

Panel Backlight Enable

Panel Backlight Connector J8

1 2 3 4 5 6 7 o o o o o o o

13 11 9 7 5 3 1 o o o o o o o o o o o o o o 141210 8 6 4 2

CRT Output Connector J4

WinSystems - "The Embedded Authority"

Panel Backlight Type Jumper J5

1 o 2 o 3 o

2.22.1 CRT Out put Con nec tion

Video out put to a stan dard VGA moni tor is made via the con nec tor at J4. An adapter ca ble part number CBL- 234-1 is avail able from WinSystems’ to adapt from J4 to the stan dard DB15 VGA con nec tor. The pin defi ni tions for the J4 con nec tor are shown here :

1 o o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 11 o o 12 13 o o 14

GND GND GND GND GND GND VCC

2.22.2

RED

GREEN

BLUE

HSYNC

VSYNC

DDCDATA

DDCCLK

Panel Backlight Con nec tion Panel Backlight connection is made via the connector at J8. The pinout for J8 is shown

here for reference.

030530 EBC-LP OPERATIONS MANUAL Page 2-23

+12

+12 GND GND

ENBKL

VCC VCC

o 1 o 2 o 3 o 4 o 5 o 6 o 7

WinSystems - "The Embedded Authority"

2.23 Flat Panel Out put Con nec tion

Con nec tion to all flat pan els is made via the two 50- pin con nec tors at J2 and J3. These con nec tors are ca bled to the ap pro pri ate FPA (Flat Panel Adapter) mod ule which then breaks out the nec e s sary ca bling for at tach ment to the panel it self. The FPA mod ule also sup plies any spe cial con trols that may be needed for the panel. Ref er to the FPA docu men ta tion for spe cific hook- up in struc tions. The pin defi ni tions for J2 and J3 are shown here :

2.23.1

FP12

1 o o 2

FP13

3 o o 4

FP14

5 o o 6

FP15

7 o o 8 9 o o 10

FP16

11 o o 12

FP17 FP18

13 o o 14

FP19

15 o o 16

FP20

17 o o 18

FP21

19 o o 20 21 o o 22

FP22 FP23

23 o o 24

FP24

25 o o 26

FP25

27 o o 28

FP26

29 o o 30

FP27

31 o o 32 33 o o 34

FP28 FP29

35 o o 36

FP30

37 o o 38

FP31

39 o o 40

FP32

41 o o 42

FP33

43 o o 44 45 o o 46

FP34 FP35

47 o o 48

SWVCC

49 o o 50

Video Mode Table

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SWVCC

SW0 SW2

FPO

FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8

FP9 FP10 FP11

PCSHCLK

PCFLM

PCLP

PCM PHSYNC PVSYNC

ENVCC

ENBKL

ENVEE

+12V

SWVCC

SW1 SW3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

-12V +12V SWVCC

The EBC-LP video section supports a number of standard and extended VGA modes. The

following table extracted from the Asiliant 6900 databook shows the video modes supported.

Resolution Color depth (bpp) Re fresh Rates

640 x 480 8 60, 75, 85 640 x 480 16 60, 75, 85 640 x 480 24 60, 75, 85 800 x 600 8 60, 75, 85 800 x 600 16 60, 75, 85

800 x 600 24 60, 75, 85 1024 x 768 8 60, 75, 85 1024 x 768 16 60, 75, 85

1280 x 1024 8 60

Page 2-24 EBC-LP OPERATIONS MANUAL 030530

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2.24 Eth er net Con troller

The 82559 is part of Intel’s second generation family of fully integrated 10BASE-T/100BASE-TX LAN solutions. The 82559 consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution.

The 82559 is a 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities which enables it to perform high-speed data transfers over the PCI bus. The 82559 bus master capabilities enable the component to process high level commands and perform multiple operations off-loading communication tasks from the system CPU. Two large transmit and receive FIFOs of 3 Kbytes each help prevent data underuns and overruns, allowing the 82559 to transmit data with minimum interframe spacing (IFS).

The 82559 can operate in either full duplex or half duplex mode. In full duplex mode the 82559 adheres to the IEEE 802.3x Flow Control specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism.

The 82559 includes a simple PHY interface to the wire transformer at rates of 10BASE-T and 100 BASE-TX, and Auto-Negotiation capability for speed, duplex, and flow control. The 82559 also includes an interface to a serial (4-pin) EEPROM. The EEPROM provides power-on initialization for hardware and software configuration parameters. The 82559 is also 100% PnP compatible and is configured through this interface. Ethernet connection to the EBC-LP is made through the connector at J1.

There are Ethernet status LED’s at D1, D2, and D3. The color and function of each LED is listed below :

D1 = Eth er net 100 base TX (Red)

D2 = Eth er net ac tiv ity LED (Green)

D3 = Eth er net link LED (Yel low)

2.25 Fan Power Connector

o 3 o 2 o 1

The EBC-LP has a connector located at J7 to supply power to the processor cooling fan. The pin definitons are shown here for reference.

o 1

GND

N/C

o 2 o 3

Fan Power

030530 EBC-LP OPERATIONS MANUAL Page 2-25

WinSystems - "The Embedded Authority"

2.26 Multi I/O Con nec tor

The I/O to the pri mary se rial chan nels, the printer port, and key board are all ter mi nated via the

con nec tor at J27. An adapter ca ble, part number CBL- 247-1, is avail able from WinSystems to adapt to the con ven tional I/O con nec tors. The pin defi ni tions for J27 are shown here

J27

COM1 - DCD COM1 - RXD

COM1 - TXD

COM1 - DTR COM1 - GND COM2 - DSR

COM2 - RTS

COM2 - CTS

COM2 - RI

LPT - STROBE

LPT - PD0 LPT - PD1 LPT - PD2 LPT - PD3 LPT - PD4 LPT - PD5 LPT - PD6 LPT - PD7

LPT - ACK

LPT - BUSY

LPT - PE

LPT - SLCT

KEYBD - GND

KEYBD - KDATA

KEYBD - +5V

COM1 - DSR COM1 - RTS COM1 - CTS COM1 - RI COM2 - DCD COM2 - RSX COM2 - TXD COM2 - DTR COM2 - GND LPT - AUTOFD LPT - ERROR LPT - INIT LPT - SLCTIN LPT - GND LPT - GND LPT - GND LPT - GND LPT - GND LPT - GND LPT - GND LPT - GND KEYBD - GND KEYBD - GND KEYBD - CLK KEYBD - +5V

2.27 USB Con nec tor

A USB cable may be attached via the connector at J32. An adapter cable, CBL-249-1 is available

from WinSystems to adapt to a conventional USB Port. The pinout for J32 is shown here.

Page 2-26 EBC-LP OPERATIONS MANUAL 030530

J32

1 o 2 o 3 o 4 o

USBV0 D0D0+ USBG0

3 Award BIOS Con figu ra tion

3.1 Gen eral In for ma tion

The EBC-LP comes equipped with a stan dard Award BIOS with Setup in ROM that al lows us ers to mod ify the ba sic sys tem con figu ra tion. This type of in for ma tion is stored in battery- backed CMOS RAM so that it re tains Setup in for ma tion when power is turned off.

3.2 En ter ing Setup

To en ter setup, power on the com puter and press the DEL key im me di ate ly af ter the mes sage “Press DEL to En ter Setup” ap pears on the lower left of the screen. If the mes sage dis ap pears bef ore you re spond and you still wish to en ter setup, re start the sys tem by turn ing it OFF and then ON or by press ing the RE SET but ton, if so equipped, or by press ing the CTRL, ALT and DEL key si mul ta ne ously. Al ter nately, un der cer tain er ror con di tions of in cor rect setup the mes sage:

“Press F1 to con tinue or DEL to En ter Setup”

may ap pear. To En ter Setup at that time press the DEL key. To at tempt to con tinue, ig nor ing the er ror con di tion, press the F1 key.

3.3 Setup Main Menu

The main menu screen is dis played on the fol low ing page. Each of the op tions will be dis cussed in this sec tion. Use the ar row keys to high light the de sired se lec tion and press EN TER to en ter the sub menu or to exe cute the func tion se lected.

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ROM PCI/ISA BIOS (2A59IA2N) CMOS SETUP UTILITY Award SOFTWARE, INC.

STANDARD CMOS SETUP INTERGRATED PERIPHERALS BIOS FEATURES SETUP SUPERVISOR PASSWORD CHIPSET FEATURES SETUP USER PASSWORD PnP/PCI CONFIGURATION IDE HDD AUTO DETECTION LOAD BIOS DEFAULTS SAVE AND EXIT SETUP LOAD SETUP DEFAULTS EXIT WITHOUT SAVING

Esc : Quit :Select Item F10 : Save & Exit Setup (Shift) F2 : Change Color

Time, Date. Hard Disk, Type...

↑ ↓ → ←

3.4 Stan dard CMOS Setup

The items in the Stan dard CMOS Setup menu are di vided into sev eral cate go ries. Each cate gory

may in clude one or more setup items. Use the ar row keys to high light the item and then use the PgUp, PgDn, +.-. keys to se lect the de sired value for the item.

Date

The date for mat is <day>,< date>,< month>, <year> day = The day, from Sun to Sat, de ter mined by the BIOS and is dis play only Date = the date, from 1 to 31 (or the maxi mum for the cur rent month) month = the month, JAN through DEC year = The year, from 1900 to 2099

Time

The time is hour, minute, sec ond. The time is cal cu lated on the 24- hour, military- time clock such

that 1:00PM is 13:00:00.

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ROM PCI/ISA BIOS (2A59IA2N) STANDARD CMOS SETUP Award SOFTWARE, INC.

Date (mm:dd:yy) : Wed, Sep 25 2000 Time (hh:mm:ss): 13 : 28 : 46

HARD DISKS TYPE SIZE CYLS HEAD PRECOMP LANDZ SECTOR MODE

Primary Master : Auto 0 0 0 0 0 0 AUTO Primary Slave : Auto 0 0 0 0 0 0 AUTO Secondary Master : Auto 0 0 0 0 0 0 AUTO Secondary Slave : Auto 0 0 0 0 0 0 AUTO

Drive A : 1.44M, 3.5 in Drive B: None Floppy Mode 3 Support : Disabled Video : EGA/VGA Halt On : No Errors

Base Memory : 640K Extended Memory : 31744K Other Memory : 384K

Total Memory: 32768K

ESC : Quit : Select Item PU/PD/+/- : Modify F1 : Help (Shift) F2 : Change Color

↑ ↓ → ←

Drive C / Drive D type

This cate gory iden ti fies the type of hard disk C: or hard disk D: that has been in stalled in the sys tem. There are 46 pre de fined types and a user de fin able type. Types 1-46 are shown in the fol low ing ta ble.

Type Size Cyl in ders Heads Sec tors Pre comp Land zone

1 10 306 4 17 128 305 2 20 615 4 17 300 615 3 30 615 6 17 300 614 4 62 940 8 17 512 940 5 46 940 6 17 512 940 6 20 615 4 17 None 615 7 30 462 8 17 256 511 8 30 733 5 17 None 733

9 112 900 15 17 None 901 10 20 820 3 17 None 820 11 35 855 5 17 None 855 12 49 855 7 17 None 855

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13 20 306 8 17 128 319 14 42 733 7 17 None 733 15 Re served 16 20 612 4 17 0 663 17 40 977 5 17 300 977 18 56 977 7 17 None 977 19 59 1024 7 17 512 1023 20 30 733 5 17 300 732 21 42 733 7 17 300 732 22 30 306 5 17 300 733 23 10 977 4 17 0 336 24 40 1024 5 17 None 976 25 76 1224 9 17 None 1023 26 71 1224 7 17 None 1223 27 111 1224 11 17 None 1223 28 152 1024 15 17 None 1223 29 68 1024 8 17 None 1023 30 93 918 11 17 None 1023 31 83 925 11 17 None 1023 32 69 1024 9 17 None 926 33 85 1024 10 17 None 1023 34 102 1024 12 17 None 1023 35 110 1024 13 17 None 1023 36 119 1024 14 17 None 1023 37 17 1024 2 17 None 1023 38 136 1024 16 17 None 1023 39 114 918 15 17 None 1023 40 40 820 6 17 None 820 41 42 1024 5 17 None 1023 42 65 1024 5 26 None 1023 43 40 809 6 17 None 852 44 61 809 6 26 None 852 45 100 776 8 33 None 775 46 203 684 16 38 None 685

Press PgUp or PgDn to se lect a num bered hard disk type, or type the number and press ENTER. Most manu fac tur ers sup ply type in for ma tion with their drives that can be used to help iden t ify the proper drive type. Mod ern IDE drives sel dom fall into the pre de fined types and are usu ally best han dled with the “auto” or “user” types. The “auto” mode, reads the hard disk type in for ma tion from the drive at boot time and uses it to ac cess the drive. The “user” mode al lows for ei ther man ual or auto mat ic en try, via the setup op tion “IDE Auto De tect” of the drive pa rame ters.

If you de cide to cre ate the user type manu ally, you must sup ply the re quired pa rame ters as to Cyl in der count, Head count, Pre comp Cyl in der, Land ing Zone Cyl in der, and number of sec tors per track.

On Hard disks larger than 528MB, it will be nec es sary to choose the Logi cal Block Ad dress ing mode (LBA) if you wish the drive to be ac ces si ble as a sin gle drive let ter.

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If there is not hard disk in stalled, be sure to se lect “None”.

Drive A type/Drive B type

This cate gory iden ti fies the type of floppy drives at tached as Drive A: or Drive B:. The choices are

as fol lows :

NONE 360K, 5.25 in.

1.2M, 5.25 in. 720K, 3.5 in

1.44M, 3.5 in.

Video

This cate gory speci fies the type of video adapter used for the pri mary sys tem moni tor that matches

your video dis play board and moni tor. The avail able choices are:

EGA/VGA CGA40 CGA80 MONO

The EBC-LP has built- in VGA sup port so EGA/VGA should be se lected.

Er ror Halt

This cate gory de ter mines whether the sys tem will halt if a non- fatal er ror is de tected dur i ng the

power-up self test. The choices are:

No Er rors : The sys tem will not be stopped for any er ror that may be de tected. All Er rors : When ever the BIOS de tects a non- fatal er ror, the sys tem will be stopped and a prompt

will ap pear.

All, but Key board : The sys tem will not stop for a key board er ror, it will stop for all other er rors. All, but disk ette : The sys tem will not stop for disk er rors. All oth ers will re sult in a prompt.

All but Disk/Key : All er rors ex cept disk ette or key board will re sult in a halt and a prompt.

Mem ory

This cate gory is dis play only and is de ter mined by the BIOS POST (Power-On Self Test).

Base Mem ory

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The POST rou tines in the BIOS will de ter mine the amount of base (con ven tional) mem ory in stalled in the sys tem. The value of the base mem ory is typi cally 640K for sys tems with a Mega byte of mem ory or greater.

Ex tended Mem ory

The BIOS de ter mines how much ex tended mem ory is pres ent dur ing the POST. This is the amount of mem ory lo cated above 1MB in the CPU's mem ory ad dress space.

Other Mem ory

This re fers to mem ory lo cated in the 640K to 1024K ad dress space. This is mem ory that can be used for dif fer ent ap pli ca tions. DOS may use this area to load de vice driv ers and TSRs to keep as much base mem ory free as pos si ble for ap pli ca tion pro grams. The most com mon use of this area is for shadow RAM.

ROM PCI/ISA BIOS (2A59IA2N) BIOS FEATURES SETUP Award SOFTWARE, INC.

Virus Warning : Disabled Video BIOS Shadow : Enabled CPU Internal Cache : Enabled C8000-CBFFF Shadow : Disabled External Cache : Enabled CC000-CFFFF Shadow : Disabled Quick Power On Self Test : Enabled D0000-D3FFF Shadow : Disabled Boot Sequence : A,C,SCSI D4000-D7FFF Shadow : Disabled Swap Floppy Drive : Disabled D8000-DBFFF Shadow : Disabled Boot Up Floppy Seek : Disabled DC000-DFFFF Shadow : Disabled Boot Up NumLock Status : On Boot Up System Speed : High Gate A20 Option : Fast Typematic Rate Setting : Disabled Typematic Rate (Chars/Sec) : 6 Typematic Delay (Msec) : 250 Security Option : Setup PCI/VGA Palette Snoop : Disabled Assign IRQ For VGA : Disabled OS Select For DRAM>64MB : Non-OS2 Report No FDD For Win 95 : Yes

ESC : Quit : Select Item F1 : Help PU/PD/+/- : Modify F5 : Old Value Shift F2 : Color F6 : Load BIOS Defaults F7 : Load Setup Defaults

↑ ↓ → ←

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3.5 Bios Fea tures Setup

Vi rus Warn ing

This op tion when en abled, pro tects the boot sec tor and par ti tion ta ble of the hard disk against un au thor ized writes through the BIOS. Any at tempt to al ter these ar eas will re sult in an er ror mes sage and a prompt to author ize the ac tiv ity.

CPU In ter nal Cache

This op tion, when en abled, pro vides maxi mum per form ance by cach ing in struc tions and data us ing the on- chip cache of the Pentium or K6 proc es sor.

Ex ter nal Cache

This op tion, when en abled, fur ther en hances per form ance by cach ing recently used in struc tions and data into fast SRAM.

Quick Power On Self Test (POST)

This op tion, when en abled, speeds up the POST dur ing power up. If it is en abled, the BIOS will shorten and/or skip some items dur ing POST.

Boot Se quence

This op tion de ter mines the boot at tempt se quence for the fixed disk and floppy disk. If there is no media available at first drive choice, system automatically moves to next drive in list. The choices are:

C,A

A,C

A, C, SCSI

C, A, SCSI

C, CD ROM, A

D, A, SCSI

E, A, SCSI

F, A, SCSI

SCSI, A, C

SCSI, C, A

C ONLY

LS120, C

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Swap Floppy Drive

This op tion al lows for swap ping of the A: and B: floppy drives with out ac tu ally re lo cat ing the

drives on the ca ble.

Boot Up Floppy Seek

Dur ing POST, when this op tion is en abled, the BIOS will de ter mine if the floppy drive is 40 track or

80 tracks. If dis abled, no seek test will be per formed and no er ror can be re ported.

Boot Up Num lock Status

This al lows user se lec tion of the Num lock state at boot time.

Boot Up Sys tem Speed

This op tion al lows speci fi ca tion of the proc es sor speed at boot time. The op tions are:

HIGH LOW

Gate A20 Op tion

This op tion al lows for the se lec tion of the source for the gate A20 sig nal. The choices are:

Nor mal - Sour ced from the key board con trol ler Fast - Sour ced from the Chipset

Type matic Rate Set ting

This op tion en ables or dis ables the type matic rate pro gram ming at boot time. Type matic is the auto-

repeat func tion for the key board.

Type matic Rate

When the type matic rate set ting is en abled the type matic re peat speed is set via this op tion. The

sup ported rates are :

6 char ac ters per sec ond 8 char ac ters per sec ond 10 char ac ters per sec ond 12 char ac ters per sec ond 15 char ac ters per sec ond 20 char ac ters per sec ond 24 char ac ters per sec ond 30 char ac ters per sec ond

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Type matic De lay

When type matic rate set ting is en abled, this op tion speci fies the time in mil li sec onds bef ore auto repeat be gins. The sup ported val ues are:

250 mS

500 mS

750 mS

1000 mS

Se cu rity Op tion

This op tion al lows you to limit ac cess to the sys tem and setup, or just to setup. The choices are:

Sys tem - The sys tem will not boot and ac cess will be de nied if the cor rect pass word is not en tered at the prompt.

Setup - The sys tem will boot, but ac cess to Setup will be de nied if the cor rect pass word is not en tered at the prompt.

NOTE: To dis able se cu rity, se lect “Pass word Set ting” at the Setup Main Menu and then you will be asked to en ter a pass word. Do not type any thing, just hit EN TER. Once the se cu rity is dis abled, the sys tem will boot and you can en ter Setup freely.

PCI/VGA Palette Snoop

This option allows for enabling or disabling of the PCI/VGA Pallette snoop.

Assign IRQ for VGA

This option, when enabled, assigns an IRQ to the video adapter.

OS Select for DRAM > 64MB

This option allows selection of an operating system for DRAM greater than 64MB.

The options are:

OS2

Non-OS2

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Report No FDD for Win 95

This option, when enabled, signals Windows 95 if there is no floppy present. The options are:

Yes No

Shad ow ing Op tions

When shad ow ing for a par ticu lar ad dress range is en abled, it in structs the BIOS to copy the BIOS

lo cated in ROM into DRAM. This shad ow ing from an 8- bit EPROM into fast 32- bit DRAM re sults in a Multi- magnitude in crease in per form ance. The main BIOS is shad owed auto mati cally but there are other ar eas that may be se lected for shad ow ing as shown here:

Video BIOS Shadow - C000- C7FFF EGA/VGA BIOS ROM C8000- CBFFF CC000- CFFFF D0000- D3FFF D4000- D7FFF D8000- DBFFF DC000-DFFFF

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ROM PCI/ISA BIOS (2A59IA2N) CHIPSET FEATURES SETUP Award SOFTWARE, INC.

Auto Con figu ra tion : En abled

CPU Warning Temperature : Disabled DRAM Tim ing : 70ns Current CPU Temperature : 4°C/39°F LEAD Off Tim ing : 10/6/4 Shutdown Temperature : 60°C/140°C DRAM Read Burst : x333/x444 DRAM Write Burst Tim ing : x333 FAST EDO lead off : Dis abled Re fresh RAS# As ser tion : 5 Clks Fast RAS to CAS De lay : 3 DRAM Page Idle Timer : 2 Clks DRAM En hanced Pag ing : En abled Fast MA to RAS# De lay : 2 Clks SDRAM (CAS Lat/RAS- to- CAS) : 3/3 Sys tem BIOS Cache able : Dis abled Video BIOS Cache able : Dis abled 8 Bit I/O Reovery Time : 1 16 Bit I/O Re cov ery Time : 2 Memory HoleAt 15M-16M : Disabled PCI 2.1 Compliance : Disabled

ESC : Quit : Select Item F1 : Help PU/PD/+/- : Modify F5 : Old Value Shift) F2 : Color F6 : Load BIOS Defaults F7 : Load Setup Defaults

↑ ↓ → ←

3.6

Chipset Fea tures Setup

The op tions in this sec tion con trol the chipset pro gram ming at boot time. In most cases, the de fault set tings should be used un less you have a clear un der stand ing of the sig nifi cance of the change. It is pos si ble us ing these op tions to cre ate a sys tem that will ei ther not boot or is very un sta ble or un re li able. If this should oc cur, there are two meth ods to re turn the sys tem to a sta ble con figu ra tion. If the sys tem works well enough to get into Setup, sim ply choose the “Load BIOS De faults” op tion and then se l ect “Save and Exit Setup” to re store fac tory de faults. If the sys tem will not run well enough to run Setup, it will be nec es sary to re move the bat tery source tem po rar ily un til the CMOS mem ory de cays. Ref er to Sec tion 2.19 for de tails on re ini tial iz ing the CMOS RAM.

Each of the op tions for the Chipset Fea tures Menu will be briefly dis cussed in the sections that fol low.

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Auto Con figu ra tion

This op tion, when en abled, in structs the BIOS to auto- select the proper DRAM timing, lead Off

timing, DRAM read burst, DRAM write burst tim ing, FAST EDO lead off, Refresh RAS # Assertion, Fast RAS to CAS Delay, DRAM Page Idle Timer, DRAM Enhanced Paging, Fast MA to RAS# Delay, SDRAM (CAS Lat/RAS-to-CAS) upon the cal cu lated CPU speed. The de fault is “En abled”.

System BIOS Cacheable

This op tion enables or disables cacheability of the system BIOS.

Video BIOS Cacheable

This op tion enables or disables cacheability of the video BIOS.

8 Bit I/O Recovery

Enables and defines 8-bit I/O recovery time in number of clocks.

16 Bit I/O Recovery

Enables and defines 16-bit I/O recovery time in number of clocks.

Memory Hole At 15M-16M

Memory Hole, when enabled, disables onboard memory in the specified range.

PCI 2.1 Compliance

This option, when enabled, makes the EBC-LP PCI 2.1 compliant. The options are:

Enabled Disabled

CPU Warning Temperature

This option when enabled, allows temperature warning through ACPI capable operating systems.

The available warning temperatures, Celsius and Fahrenheit, are listed below.

50°C / 122°F 53°C / 127°F 56°C / 133°F 60°C / 140°F 66°C / 151°F 70°C / 158°F

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Current CPU Temperature

This option displays current temperature of the processor.

Shutdown Temperature

This option when enabled, allows the user to set a shutdown temperature through ACPI capable operating systems. The available shutdown temperatures, Celsius and Fahrenheit, are listed below.

60°C / 140°F

65°C / 149°F

70°C / 158°F

75°C / 167°F

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ROM PCI/ISA BIOS (2A59IA2N) POWER MANAGEMENT SETUP Award SOFTWARE, INC.

ACPI Function : En abled ** Reload Global Timer Events ** Power Management : Disabled IRQ [3-7, 9-15] ,NMI : Disabled PM Control by APM : No Primary IDE 0 : Disabled Video Off Method : Blank Screen Primary IDE 1 : Disabled Video Off After : NA Secondary IDE 0 : Disabled MODEM Use IRQ : NA Secondary IDE 1 : Disabled Doze Mode : Disabled Floppy Disk : Disabled Standby Mode : Disabled Serial Port : Disabled Suspend Mode : Disabled Parallel Port : Disabled HDD Power Down : Disabled Throttle Duty Cycle : 12.5% ZZ Active in Suspend : Disabled PCI/VGA Act-Monitor : Disabled Soft-Off by PWR-BTTN : Instant-Off CPUFAN Off In Suspend : Disabled PowerOn by Ring : Disabled Resume by Alarm : Disabled

IRQ 8 Break Suspend : Disabled

ESC : Quit : Select Item F1 : Help PU/PD/+/- : Modify F5 : Old Value Shift) F2 : Color F6 : Load BIOS Defaults F7 : Load Setup Defaults

↑ ↓ → ←

3.7

Power Management

ACPI Function

This option enables the advanced configuration and power interface.

Power Management

This option, enables advance power management on the EBC-LP.

PM Control by APM

This option allows power management control throughout the advanced power management

software interface.

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Video Off Method

There are 3 video off methods to select from when power management is enabled. The options are:

Blank Screen

V/H Sync + Blank

DPMS

Video Off After

This option, when Doze mode is enabled, will shut off video using one of the following methods:

Sus pend

Standby

Doze

MODEM Use IRQ

This option allows selection of the interrupt to use for wake up on modem activity. The interrupt choices are:

Doze Mode

This option, when power management is enabled, allows the user to select the length of time the system will wait with no activity before entering. Doze mode. The choices are:

Dis abled

1 minute

2 min utes

4 min utes

8 min utes

12 min utes

20 min utes

30 min utes

40 min utes

1 hour

Standby Mode

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This option, when power management is enabled, allows the user to select the length of time the

system will wait with no activity before entering Standby mode. The choices are:

Dis abled 1 minute 2 min utes 4 min utes 8 min utes 12 min utes 20 min utes 30 min utes 40 min utes 1 hour

Suspend Mode

This option, when power management is enabled, allows the user to select the length of time the

system will wait with no activity before entering Suspended mode. The choices are:

Dis abled 1 minute 2 min utes 4 min utes 8 min utes 12 min utes 20 min utes 30 min utes 40 min utes 1 hour

HDD Power Down

This option, when power management is enabled, allows the user to select the length of time the

system will wait with no activity before entering hard disk power down mode. The choices are:

1 minute 2 minutes 3 minutes 4 min utes 5 minutes 6 min utes 7 min utes 8 min utes 9 min utes 10 min utes 11 minutes 12 min utes 13 min utes

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14 min utes

15 mi nutes

Throttle Duty Cycle

This option selects the throttle rate of the main system clock during power management. The choices are:

12.5%

25.0%

37.5%

50.0%

62.5%

75.0%

ZZ Active in Suspend

This option, when enabled, puts the on-board L2 cache into sleep mode during power management.

PCI/VGA Act-Monitor

This option, when enabled, monitors activity of VGA for power management.

CPUFAN Off In Suspend

This option, when enabled, shuts off power to the CPU fan when the system is in suspended mode.

PowerOn by Ring

This option is not supported on the EBC-LP. Contact WinSystems’ tech support for further information

Resume by Alarm

This option, when enabled, will wake the system from power management mode.

IRQ 8 Break Suspend

This option, when enabled will wake the system from suspended mode using interrupt request 8.

IRQ [3-7, 9-15],NMI

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This option, when enabled, will reset the power management timer if any of the following are

accessed.

IRQ 3-7 IRQ 9-15 NMI

Primary IDE 0

This option, when enabled, will reset the power management timer when the primary IDE drive is

accessed.

Primary IDE 1

This option, when enabled, will reset the power management timer when the primary IDE drive is

accessed.

Secondary IDE 0

This option, when enabled, will reset the power management timer when the secondary IDE drive is

accessed.

Secondary IDE 1

This option, when enabled, will reset the power management timer when the secondary IDE drive is

accessed.

Floppy Disk

This option, when enabled, will reset the power management timer when the floppy drive is

accessed.

Serial Port

This option, when enabled, will reset the power management timer when the serial port is accessed.

Parallel Port

This op tion, when en abled, will re set the power man age ment timer when the par al lel port is

ac cessed.

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ROM PCI/ISA BIOS (2A59IA2N) PnP/PCI CONFIGURATION Award SOFTWARE, INC.

PnP OS Installed : NO PCI IDE IRQ Map : ISA Resources Controlled By : Manual Primary IDE INT# : A Reset Configuration Data : Disabled Secondary IDE INT# : A

IRQ-3 assigned to : PCI/ISA PnP IRQ-4 assigned to : PCI/ISA PnP Used MEM base addr : N/A IRQ-5 assigned to : Legacy ISA IRQ-6 assigned to : PCI/ISA PnP IRQ-7 assigned to : PCI/ISA PnP IRQ-9 assigned to : Legacy ISA IRQ-10 assigned to : Legacy ISA IRQ-11 assigned to : PCI/ISA PnP IRQ-12 assigned to : PCI/ISA PnP IRQ-14 assigned to : Legacy ISA IRQ-15 assigned to : Legacy ISA DMA-0 assigned to : PCI/ISA PnP DMA-1 assigned to : PCI/ISA PnP DMA-3 assigned to : PCI/ISA PnP DMA-5 assigned to : PCI/ISA PnP DMA-6 assigned to : PCI/ISA PnP DMA-7 assigned to : PCI/ISA PnP

ESC : Quit : Select Item F1 : Help PU/PD/+/- : Modify F5 : Old Value Shift) F2 : Color F6 : Load BIOS Defaults F7 : Load Setup Defaults

↑ ↓ → ←

3.8

PnP/PCI Configuration

PnP OS Installed

This option allows the user to assign whether the operating system is PnP. The options are:

YES

Re sources Con trolled By

This option allows the user to select resource control of the system. The options are:

Auto

Manual

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Reset Configuration Data

This option, when enabled, will reset the configuration data on power up. The options are:

En abled Disabled

IRQ3-15 / DMA 0-7

The options in this section of the manual will assign each of the interrupts to a PCI/ISA Plug and

Play device, or to a Legacy ISA device. The available options are:

PCI/ISA PnP Leg acy ISA

PCI IDE IRQ Map

This option allows the selection of the PCI IDE IRQ map. The options are:

ISA PCI- AUTO PCI- SLOT 1 PCI- SLOT 2 PCI- SLOT 3 PCI- SLOT 4

Used MEM Base Address

This option allows selection of the base address used by memory. The options are:

N/A C800 CC00 D000 D400 D800 DC00

3.9 Load BIOS Defaults

This main- menu op tion will cause the CMOS RAM to be loaded with the de fault val ues as signed by

the fac tory. These are usu ally con sid ered safe val ues and do not neces sar ily rep re sent the high est per form ance val ues.

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3.10 Load Setup Defaults

This op tion will cause the CMOS RAM to be loaded with de fault setup val ues as signed by the fac tory. These are usu ally val ues that were de ter mined to give a higher level of per form ance along with re li able op era tion.

3.11 Password Setting

This op tion al lows the set ting of the se cu rity pass word. Press ing en ter at the pass word prompt dis ables the se cu rity func tion com pletely.

3.12 IDE HDD Auto Detection

This func tion al lows mod ern IDE fixed disks to be used to their maxi mum po ten tial by in ter ro gat ing the driver as to its pre ferred con figu ra tion of tracks,heads, and sec tors; and auto mati cally load ing these pa rame ters into a “user de fined” hard disk type.

3.13 Save & Exit Setup

This func tion writes all changes to CMOS RAM and re starts the sys tem.

3.14 Exit without Saving

This op tion ex its setup with out sav ing any changes made and then re starts the sys tem.

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4 EBC-LP DiskOnChip Configuration

4.1 DiskOnChip Usage

The EBC-LP sup ports the M-Systems DISK- ON- CHIP (DOC) flash de vice in sizes rang ing from 8MB to 288MB. The DOC de vice con tains a BIOS ex ten sion, the TFFS (True Flash File Sys tem), and the Flash mem ory all in a sin gle 32- pin de vice. The DOC emu lates a hard disk and can be used as a sec on dary hard disk to a physi cal IDE drive or it can be the only hard disk in the sys tem.

The DOC is in stalled into the socket at U17. Ref er to the sec tion 2.20 for cor rect de vice jump er ing and ena bling of the DOC.

4.1.1 DOC Initialization

The DOC is ini tial ized in an iden ti cal fash ion to a fixed disk. DOS is booted (from floppy or hard disk), FDISK is run on the DOC drive (be sure to get the right drive), the sys tem is re booted and then the DOC is for mat ted us ing the DOS for mat com mand.

If the /S switch was used dur ing for mat ting and there is no other fixed disk de vice speci fied or at tached to the sys tem the DOC will be come the boot de vice. If a hard disk is pres ent, the DOC will be come a sec on dary fixed disk.

030530 EBC-LP OPERATIONS MANUAL Page 4-1

5 WS16C48 Pro gram ming Ref er ence

5.1 In tro duc tion

This sec tion pro vides ba sic docu men ta tion for the in cluded I/O rou tines. It is in tended that the ac com pa ny ing source code equip the pro gram mer with a ba sic li brary of I/O func tions for the WS16C48 or can serve as the ba sis from which ap pli ca tion spe cific code can be de rived.

5.2 Func tion Defi ni tions

This sec tion briefly de scribes each of the func tions con tained in the driver. Where nec es sary, short ex am ples will be pro vided to il lus trate us age. Any ap pli ca tion mak ing use of any of the driver func tions should in clude the header file “uio48.h”, which in cludes the func tion pro to types and the needed con stant defi ni tions.

Note that all of the func tions util ize the con cept of “bit_number”. The “bit_number” is a value from 1 to 48 (1 to 24 for in ter rupt re lated func tions) that cor re lates to a spe cific I/O pin. Bit_number 1 is port 0 bit 0 and con tin ues through to bit_number 48 at port 5 bit 7.

INIT_IO - Ini tial ize I/O, set all ports to in put

Syn tax

void init_io(un signed io_ad dress);

De scrip tion

This func tion takes a sin gle ar gu ment:

io_ad dress - The I/O ad dress of the WS16C48 chip.

There is no re turn value. This func tion ini tial izes all I/O pins for in put (Sets them high), dis ables all in ter rupt set tings, and sets the im age val ues.

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READ_BIT - Reads an I/O port Bit

Syn tax

int read_bit(int bit_number);

De scrip tion

This func tion takes a sin gle ar gu ment:

bit_number - This is a value from 1 to 48 that in di cates the I/O pin to read from.

This func tion re turns the state of the I/O pin. A '1' is re turned if the I/O pin is low and a '0' is re turned

if the pin is high.

WRITE_BIT - Write a 1 or 0 to an I/O pin

Syn tax

void write_bit(int bit_number, int value);

De scrip tion

This func tion takes two ar gu ments

bit_number - This is value from 1 to 48, which is the bit to be acted upon. Value - is ei ther 1 or 0.

This func tion al lows for writ ing of a sin gle bit to ei ther a '0' or a '1' as speci fied by the sec ond

ar gu ment. There is no re turn value and other bits in the I/O port are not af fected.

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SET_BIT - Set the speci fied I/O Bit

Syn tax

void set_bit(int bit_number);

De scrip tion

This func tion takes a sin gle ar gu ment:

bit_number - a value be tween 1 and 48 speci fy ing the port bit to be set.

This func tion sets the speci fied I/O port bit. Note that set ting a bit re sults in the I/O pin ac tu ally go ing low. There is no re turn value and other bits in the same I/O port are un af fected.

CLR_BIT - Clear the speci fied I/O Bit

Syn tax

void clr_bit(int bit_number);

De scrip tion

This func tion takes a sin gle ar gu ment:

bit_number - a value from 1 to 48 in di cates the bit number to clear.

This func tion clears the speci fied I/O bit. Note that clear ing the I/O bit re sults in the ac tual I/O pin go ing high. This func tion does not af fect any bits other than the one speci fied.

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ENAB_INT - En able Edge In ter rupt, Se lect Po lar ity

Syn tax

void enab_int(int bit_number, int po lar ity);

De scrip tion

This func tion re quires two ar gu ments:

bit_number - A value from 1 to 24 speci fy ing the ap pro pri ate bit

po lar ity - Speci fies ris ing or fal ling edge po lar ity de tect. The con stants RIS ING and FAL LING are de fined

in “uio48.h”

This func tion en ables the edge de tec tion cir cuitry for the speci fied bit at the speci fied po lar ity. It

does not un mask the in ter rupt con trol ler, in stall vec tors, or han dle in ter rupts when they oc cur. There is no re turn value and only the speci fied bit is af fected.

DISAB_INT - Dis able Edge De tect In ter rupt De tec tion

Syn tax

void disab_int(int bit_number);

De scrip tion

This func tion re quires a sin gle ar gu ment:

bit_number - A value from 1 to 24 speci fy ing the ap pro pri ate bit.

This func tion shuts down the edge de tec tion in ter rupts for the speci fied bit. There is no re turn value

and no harm is done by call ing this func tion for a bit which did not have edge de tec tion in ter rupts en abled. There is no af fect on any other bits.

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CLR_INT - Clear the speci fied pend ing in ter rupt

Syn tax

void clr_int(int bit_number);

De scrip tion

This func tion re quires a sin gle ar gu ment:

bit_number - The speci fied bit number from 1 to 24 to re set the in ter rupt.

This func tion clears a pend ing in ter rupt on the speci fied bit. It does this by dis abling and reena bling the in ter rupt. The net re sult af ter the call is that the in ter rupt is no longer pend ing and is re armed for the next tran si tion of the same po lar ity. Call ing this func tion on a bit that has not been en abled for in ter rupts will re sult in its in ter rupt be ing en abled with an un de fined po lar ity. Call ing this func tion with no in ter rupt pend ing will have no ad verse af fect. Only the speci fied bit is af fected.

GET_INT - Re trieve bit number of pend ing in ter rupt

Syn tax

int get_int(void);

De scrip tion

This func tion re quires no ar gu ments and re turns ei ther a '0' for no bit in ter rupts pend ing or a value be tween 1 and 24 rep re sent ing a bit number that has a pend ing edge de tect in ter rupt. The func tion re turns with the first in ter rupt found and be gins its search at Port 0 Bit 0 pro ceed ing through to Port 2 Bit

7. It is nec es sary to use ei ther clr_int() or disab_int() to avoid re turn ing the same bit con tinu ously. This func tion may ei ther be used in an ap pli ca tion's ISR or can be used in the fore ground to poll for bit tran si tions.

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5.3 Sam ple Pro grams

There are three sam ple pro grams in source code form in cluded on the EBC-LP disk ette in the

UIO48 di rec tory. These pro grams are not use ful by them selves but are pro vided to il lus trate the us age of the I/O func tions pro vided in UIO48C.

FLASH.C

This pro gram was com piled with Bor land C/C++ ver sion 3.1 on the com mand line with:

bcc flash.c uio48.c

This pro gram il lus trates the most ba sic us age of the WS16C48. It uses three func tions from the

driver code. The io_init() func tion is used to ini tial ize the I/O func tions and the set_bit() and clr_bit() func tions are used to se quence through all 48 bits turn ing each on and then off in turn.

POLL.C

This pro gram was com piled with Bor land C/C++ ver sion 3.1 on the com mand line with:

bcc poll.c uio48.c

This pro gram il lus trates ad di tional fea tures of the WS16C48 and the I/O li brary func tions. It

pro grams the first 24 bits for in put, arms them for fal ling edge de tec tion, and then polls us ing the li brary rou tine get_int() to de ter mine if any tran si tions have taken place.

INT.C

This pro gram was com piled with Bor land C/C++ ver sion 3.1 on the com mand line with:

bcc int.c uio48.c

This pro gram is iden ti cal in func tion to the “poll.c” pro gram ex cept that in ter rupts are ac tive and all

up dat ing of the tran si tion coun ters is ac com plished in the back ground dur ing the in ter rupt serv ice rou tine.

Sum mary

The source code for all three pro grams as well as the I/O rou tines are in cluded on the ac com pa ny ing

disk ette. The source code is also pro vided in printed form in AP PEN DIX F. These I/O rou tines along with the sam ple pro gram should pro vide for a good ba sis on which to build an ap pli ca tion us ing the fea tures of the WS16C48.

Page 5-6 EBC-LP OPERATIONS MANUAL 030530

6 AP PEN DIX A - I/O Port Map

The fol low ing is a list of PC I/O ports. Ad dresses marked with a '-' are not used on the EBC-LP but their use should be care fully quali fied so as not to con flict with other I/O boards. I/O ad dresses marked with a '+' are used on the EBC-LP board and are unique to the WinSystems’ de sign. I/O Ad dresses marked with '**' are gen er ally un used and should be the ba sis for the first choices in I/O ad d ress se lec tion.

Hex Range Us age

000- 00F 8237 DMA #1

**010- 01F FREE

020- 021 8259 PIC #1

+022- 023 Fi nali 486 Chipset Reg is ters

**024- 03F FREE

040- 043 8254 Timer

**044- 05F FREE

060- 06F 8042 Key board Con trol ler

070- 071 CMOS RAM/RTC

**072- 07F FREE

080- 08F DMA Page Reg is ters

**090- 09F FREE

0A0- 0BF 8259 PIC #2

0C0- 0DF 8237 DMA #2

**0E0- 0EF FREE

0F0- 0F1 Co proc es sor Con trol

**0F2- 11F FREE

+120- 12F WS16C48 HDIO

**130- 1DF FREE

+1E0- 1EF SSD, Led, Watch dog con trol

1F0- 1FF Fixed Disk I/O

-200- 20F Joy stick port

-210- 21F PCM SSD I/O Ports

-220- 22F Sound blas ter I/O ports

**230- 237 FREE

-238- 23B BUS Mouse

**240- 277 FREE

278- 27F LPT1

**280- 2AF FREE

-2B0 -2DF EGA Video

-2E0 -2E7 GPIP In ter face

2E8- 2EF COM4

**2F0- 2F7 FREE

2F8- 2FF COM2

-300- 31F Pro to type Card

-320- 32F XT Hard Disk

**330- 377 FREE

-378- 37F Par al lel Printer

-380 -3AF SDLC

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-3B0 -3BB DMA

-3C0 -3CF EGA 3E8- 3EF COM3 3F0- 3F6 Floppy Disk 3F8- 3FF COM1

Page 6-2 EBC-LP OPERATIONS MANUAL 030530

7 AP PEN DIX B - In ter rupt Map

No. Ad dress Type De scrip tion

0 00 CPU Di vide by 0

1 04 CPU Sin gle Step

386 De bug Ex cep tion 2 08 CPU NMI 3 0C CPU Break point 4 10 CPU Over flow 5 14 BIO Print Screen

186 Bound Ex cep tion 6 18 186 In va lid op code ex cep tion 7 1C 186 Co proc es sor un avail able 8 20 Hard ware IRQ0 - 18.2Hz heart beat

286 LIDT - Dou ble fault ex cep tion 9 24 Hard ware IRQ1 - Key board in ter rupt

286 Co proc es sor seg ment A 28 Hard ware IRQ2 - XT Re served,

AT-Slaved Con trol ler

286 In va lid TSS ex cep tion B 2C Hard ware IRQ3 - COM2

286 Seg ment not pres ent C 30 Hard ware IRQ4 - COM1

286 Stack fault ex cep tion D 34 Hard ware IRQ5 - XT Hard Disk, AT Free

286 Pro tec tion fault ex cep tion E 38 Hard ware IRQ6 - Floppy Disk In ter rupt

386 Page fault ex cep tion F 3C Hard ware IRQ7 - LPT1 10 40 BIOS Video BIOS func tions

286 Co proc es sor ex cep tion 11 44 BIOS BIOS Equip ment check

486 Align ment check ex cep tion 12 48 BIOS Mem ory Size func tion 13 4C BIOS BIOS Disk func tions 14 50 BIOS BIOS se rial func tions 15 54 BIOS Cas sette/pro tected mode

func tions 16 58 BIOS Key board BIOS func tions 17 5C BIOS BIOS printer func tions 18 60 BIOS SROM Ba sic En try point (IBM) 19 64 BIOS Boot loader func tion 1A 68 BIOS BIOS time of day func tions 1B 6C BIOS Key board break vec tor 1C 70 BIOS User chained timer tick 1D 74 BIOS Video Ini tiali za tion 1E 78 BIOS Floppy Disk pa rame ter ta ble 1F 7C BIOS CGA graphic char ac ter font

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20 80 MS- DOS Pro gram ter mi nate 21 84 MS- DOS DOS func tion call 22 88 MS- DOS Ter mi nate Ad dress 23 8C MS- DOS Ctrl- Break Ad dress 24 90 MS- DOS Fa tal Er ror Vec tor 25 94 MS- DOS Ab so lute disk read 26 98 MS- DOS Ab so lute disk write 27 9C MS- DOS Ter mi nate 28 A0 MS- DOS Idle Sig nal 29 A4 MS- DOS TTY out put 2A A8 MS- DOS MS- Net serv ices 2F BC MS- DOS Print Spool 30 C0 MS- DOS Long jump in ter face 33 CC MS- DOS Mouse func tions 3F FC MS- DOS Over lay in ter rupt 40 100 BIOS Floppy I/O when fixed disk

is pres ent 41 104 BIOS Fixed disk 1 pa rame ter ta ble 42 108 BIOS EGA Chain 43 10C BIOS EGA Pa rame ter ta ble pointer 44 110 BIOS EGA graph ics char ac ter font 4A 128 BIOS AT Alarm exit ad dress 50 140 BIOS AT Alarm in ter rupt 51 144 BIOS Mouse func tions 5A 168 NET Func tions 5B 16C NET Boot chain 5C 170 NET Net BIOS en try 67 19C MS- DOS EMS func tions 6D 1B4 VGA VGA Serv ice 70 1C0 Hard ware IRQ8 - Real Time clock 71 1C4 Hard ware IRQ9 - Re di rected IRQ2 72 1C8 Hard ware IRQ10 - Un as signed 73 1CC Hard ware IRQ11 - Un as signed 74 1D0 Hard ware IRQ12 - Un as signed 75 1D4 Hard ware IRQ13 - Un as signed 76 1D8 Hard ware IRQ14 - IDE Fixed Disk 77 1DC Hard ware IRQ15 - Un as signed 80 200 F0 3C0 Ba sic F1 3C4 FF 3FC Not Used

Page 7-2 EBC-LP OPERATIONS MANUAL 030530

APPENDIX C

Mechanical Drawing

APPENDIX D

WS16C48 I/O Routines and Sample Program Listings

/* UIO48.H

Permission is hereby granted to the purchaser of the WinSystems UIO cards and CPU products incorporating the UIO device, to distribute any binary file or files compiled using this source code directly or in any work derived by the user from this file. In no case may the source code, original or derived from this file, be distributed to any third party except by explicit permission of WinSystems. This file is distributed on an "As-is" basis and no warranty as to performance, fitness of purposes, or any other warranty is expressed or implied. In no case shall WinSystems be liable for any direct or indirect loss or damage, real or consequential resulting from the usage of this source code. It is the user's sole responsibility to determine

fitness for any considered purpose. */ /************************************************************************** * Name : uio48.h * * Project : PCM-UIO48 Software Samples/Examples * * Date : October 30, 1996 * * Revision: 1.00 * * Author : Steve Mottin * **************************************************************************** * * Changes : * * Date Revision Description * ________ ________ ______________________________________________ * 10/30/96 1.00 Created * ***************************************************************************** */

#define RISING 1 #define FALLING 0

void init_io(unsigned io_address); int read_bit(int bit_number); void write_bit(int bit_number); void set_bit(int bit_number); void clr_bit(int bit_number); void enab_int(int bit_number, int polarity); void disab_int(int bit_number); void clr_int(int bit_number); int get_int(void);

/* UIO48.C

Permission is hereby granted to the purchaser of the WinSystems

UIO cards and CPU products incorporating the UIO device, to distribute

any binary file or files compiled using this source code directly or

in any work derived by the user from this file. In no case may the

source code, original or derived from this file, be distributed to any

third party except by explicit permission of WinSystems. This file is

distributed on an "As-is" basis and no warranty as to performance,

fitness of purposes, or any other warranty is expressed or implied.

In no case shall WinSystems be liable for any direct or indirect loss

or damage, real or consequential resulting from the usage of this

source code. It is the user's sole responsibility to determine

fitness for any considered purpose. */ /************************************************************************** * Name : uio48.c * * Project : PCM-UIO48 Software Samples/Examples * * Date : October 30, 1996 * * Revision: 1.00 * * Author : Steve Mottin * **************************************************************************** * * Changes : * * Date Revision Description * ________ ________ ______________________________________________ * 10/30/96 1.00 Created * ***************************************************************************** */

#include <dos.h>

/* This global holds the base address of the UIO chip */

unsigned base_port;

/* This global array holds the image values of the last write to each I/O ports. This allows bit manipulation routines to work without having to actually do a read-modify-write to the I/O port. */

unsigned port_images[6];

/*=========================================================================== * INIT_IO * * This function take a single argument : * * * io_address : This is the base I/O address of the 16C48 UIO Chip * on the board. *

* * This function initializes all I/O pins for input, disables all interrupt * sensing, and sets the image values. * *===========================================================================*/

void init_io(unsigned io_address) { int x;

/* Save the specified address for later use */

base_port = io_address;

/* Clear all of the I/O ports. This also makes them inputs */

for(x=0; x < 7; x++)

outportb(base_port+x, 0);

/* Clear our image values as well */

for(x=0; x < 6; x++)

port_images[x] = 0;

/* Set page 2 access, for interrupt enables */

outportb(base_port+7,0x80);

/* Clear all interrupt enables */

outportb(base_port+8,0);

outportb(base_port+9,0);

outportb(base_port+0x0a,0);

/* Restore normal page 0 register access */

outportb(base_port+7,0);

}

/*=========================================================================== * * READ_BIT * * * This function takes a single argument : * * * bit_number : The integer argument specifies the bit number to read. * Valid arguments are from 1 to 48. * * return value : The current state of the specified bit, 1 or 0. * * This function returns the state of the current I/O pin specified by * the argument bit_number. * *===========================================================================*/

int read_bit(int bit_number) { unsigned port; int val;

/* Adjust the bit_number to 0 to 47 numbering */

--bit_number;

/* Calculate the I/O port address based on the updated bit_number */

port = (bit_number / 8) + base_port;

/* Get the current contents of the port */

val = inportb(port);

/* Get just the bit we specified */

val = val & (1 << (bit_number % 8));

/* Adjust the return for a 0 or 1 value */

if(val)

return 1;

return 0; }

/*=========================================================================== * * WRITE_BIT * * This function takes two arguments : * * * bit_number : The I/O pin to access is specified by bit_number 1 to 48. * * val : The setting for the specified bit, either 1 or 0. * * This function sets the specified I/O pin to either high or low as dictated * by the val argument. A non zero value for val sets the bit. * *===========================================================================*/

void write_bit(int bit_number, int val) { unsigned port; unsigned temp; unsigned mask;

/* Adjust bit_number for 0 based numbering */

--bit_number;

/* Calculate the I/O address of the port based on the bit number */

port = (bit_number / 8) + base_port;

/* Use the image value to avoid having to read the port first. */

temp = port_images[bit_number / 8]; /* Get current value */

/* Calculate a bit mask for the specified bit */

mask = (1 << (bit_number % 8));

/* Check whether the request was to set or clear and mask accordingly */

if(val) /* If the bit is to be set */

temp = temp | mask;

else

temp = temp & ~mask;

/* Update the image value with the value we're about to write */

port_images[bit_number / 8] = temp;

/* Now actually update the port. Only the specified bit is affected */

outportb(port,temp); }

/*=========================================================================== * SET_BIT * * * This function takes a single argument : * * bit_number : The bit number to set. * * This function sets the specified bit. * *===========================================================================*/

void set_bit(int bit_number) {

write_bit(bit_number,1); }

/*=========================================================================== * CLR_BIT * * * This function takes a single argument : * * bit_number : The bit number to clear. * * This function clears the specified bit. * *===========================================================================*/

void clr_bit(int bit_number) {

write_bit(bit_number,0); }

/*=========================================================================== * * ENAB_INT * * This function takes two arguments : * * bit_number : The bit number to enable intterups for. Range from 1 to 48.

* * polarity : This specifies the polarity of the interrupt. A non-zero * argument enables rising-edge interrupt. A zero argument * enables the interrupt on the flling edge. * * This function enables within the 16C48 an interrupt for the specified bit * at the specified polarity. This function does not setup the interrupt * controller, nor does it supply an interrupr handler. * *============================================================================*/

void enab_int(int bit_number, int polarity) { unsigned port; unsigned temp; unsigned mask;

/* Adjust for 0 based numbering */

--bit_number;

/* Calculate the I/O address based uppon the bit number */

port = (bit_number / 8) + base_port + 8;

/* Calculate a bit mask based on the specified bit number */

mask = (1 << (bit_number % 8));

/* Turn on page 2 access */

outportb(base_port+7,0x80);

/* Get the current state of the interrupt enable register */

temp = inportb(port);

/* Set the enable bit for our bit number */

temp = temp | mask;

/* Now update the interrupt enable register */

outportb(port,temp);

/* Turn on access to page 1 for polarity control */

outportb(base_port+7,0x40);

/* Get the current state of the polarity register */

temp = inportb(port); /* Get current polarity settings */

/* Set the polarity according to the argument in the image value */

if(polarity) /* If the bit is to be set */

temp = temp | mask;

else

temp = temp & ~mask;

/* Write out the new polarity value */

outportb(port,temp);

/* Set access back to Page 0 */

outportb(base_port+7,0x0);

}

/*=========================================================================== * * DISAB_INT * * This function takes a single argument : * * bit_number : Specifies the bit number to act upon. Range is from 1 to 48. * * This function shuts off the interrupt enabled for the specified bit. * *===========================================================================*/

void disab_int(int bit_number) { unsigned port; unsigned temp; unsigned mask;

/* Adjust the bit_number for 0 based numbering */

--bit_number;

/* Calculate the I/O Address for the enable port */

port = (bit_number / 8) + base_port + 8;

/* Calculate the proper bit mask for this bit number */

mask = (1 << (bit_number % 8));

/* Turn on access to page 2 registers */

outportb(base_port+7,0x80);

/* Get the current state of the enable register */

temp = inportb(port);

/* Clear the enable bit int the image for our bit number */

temp = temp & ~mask;

/* Update the enable register with the new information */

outportb(port,temp);

/* Set access back to page 0 */

outportb(base_port+7,0x0);

}

/*========================================================================== * * CLR_INT * * This function takes a single argument : * * bit_number : This argument specifies the bit interrupt to clear. Range * is 1 to 24. * * * This function is use to clear a bit interrupt once it has been recognized. * The interrupt left enabled. * *===========================================================================*/

void clr_int(int bit_number) { unsigned port; unsigned temp; unsigned mask;

/* Adjust for 0 based numbering */

--bit_number;

/* Calculate the correct I/O address for our enable register */

port = (bit_number / 8) + base_port + 8;

/* Calculate a bit mask for this bit number */

mask = (1 << (bit_number % 8));

/* Set access to page 2 for the enable register */

outportb(base_port+7,0x80);

/* Get current state of the enable register */

temp = inportb(port);

/* Temporarily clear only OUR enable. This clears the interrupt */

temp = temp & ~mask; /* clear the enable for this bit */

/* Write out the temporary value */

outportb(port,temp);

/* Re-enable our interrupt bit */

temp = temp | mask;

/* Write it out */

outportb(port,temp);

/* Set access back to page 0 */

outportb(base_port+7,0x0);

}

/*========================================================================== * * GET_INT * * This function take no arguments. * * return value : The value returned is the highest level bit interrupt * currently pending. Range is 1 to 24. * * This function returns the highest level interrupt pending. If no interrupt * is pending, a zero is returned. This function does NOT clear the interrupt. * *===========================================================================*/

int get_int(void) { int temp; int x;

/* read the master interrupt pending register, mask off undefined bits */

temp = inportb(base_port+6) & 0x07;

/* If there are no interrupts pending, return a 0 */

int */

if((temp & 7) == 0)

return(0);

/* There is something pending, now we need to identify what it is */

/* Set access to page 3 for interrupt id registers */

outportb(base_port+7,0xc0);

/* Read interrupt ID register for port 0 */

temp = inportb(base_port+8);

/* See if any bit set, if so return the bit number */

if(temp !=0)

{

for(x=0; x <=7; x++) {

if(temp & (1 << x)) {

outportb(base_port+7,0); /* Turn off access */ return(x+1); /* Return bitnumber with active

}

/* None in Port 0, read port 1 interrupt ID register */

int */

temp = inportb(base_port+9);

/* See if any bit set, if so return the bit number */

if(temp !=0)

{

for(x=0; x <=7; x++) {

if(temp & (1 << x)) {

outportb(base_port+7,0); /* Turn off access */ return(x+9); /* Return bitnumber with active

}

/* Lastly, read status of port 2 int id */

temp = inportb(base_port+0x0a); /* Read port 2 status */

/* If any pending, return the appropriate bit number */

if(temp !=0)

{

for(x=0; x <=7; x++) {

if(temp & (1 << x)) {

outportb(base_port+7,0); /* Turn off access */ return(x+17); /* Return bitnumber with active

}

/* We should never get here unless the hardware is misbehaving but just

to be sure. We'll turn the page access back to 0 and return a 0 for

no interrupt found.

outportb(base_port+7,0);

return 0; }

/* FLASH.C