WinSystems EBC-C384-D User Manual

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WinSystems

EBC-C384-D

Intel® ATOMTM EBX Single Board Computer

PRODUCT MANUAL

WinSystems, Inc.

715 Stadium Drive Arlington, TX 76011

http://www.winsystems.com

MANUAL REVISION HISTORY

P/N 400-384-000

Revision Date Code ECO Number

111219 Initial Release 120125 120507 120606 130405 130509 130723 140206 ECO 14-07 140703

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BEFORE YOU BEGIN 6

Visual Index - Top View (Connectors) 7

Visual Index - Top View (Jumpers & LEDs) 8

Visual Index - Bottom View 9

Jumper Reference 10

INTRODUCTION 13

FEATURES 13

System 14 Memory 14

FUNCTIONALITY 15

I/O Port Map 15 Interrupt Map 17 PCI Devices and Functions 18 DOS Legacy Memory Map 18 Watchdog Timer 20 Real-Time Clock/Calendar 21 Status LED 21

CONNECTOR REFERENCE 22

POWER 22

J6 - Power and Reset 22 J26 - Fan Power 22 J2 - Push Button Reset 22 J3 - ATX Signals 23

BATTERY BACKUP 24

J14 - External Battery 24

VIDEO 25

J19 - ANALOG VGA 25 J20 - LVDS 26 J24 - Backlight Power 26 JP13 - Panel Power 27

AUDIO 28

J16 - HD Audio 28 SP1 - Speaker 29

MULTI-I/O 30

J7 - Multi-I/O (COM1, COM2, Keyboard, LPT) 30

MOUSE 33

J1 - Mouse 33

SERIAL 34

J10 - COM3, COM4 34

USB 36

J4, J5 - USB 36

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SERIAL ATA 37

J23, J25 - SATA 37

COMPACTFLASH 37

J28 - CompactFlash 37

PARALLEL ATA 38

J11 - PATA 38

ETHERNET 39

J13, J8 - Gigabit Ethernet 39

DIGITAL I/O 40

J9, J12 - Digital I/O 40 JP5/JP8 - Digital I/O Power 40

PC/104 BUS 43

J15, J17 - PC/104 43

PC/104-Plus BUS 44

J18 - PC/104-Plus 44

MiniPCI 45

J27 - MiniPCI Socket 45 MiniPCI Device Interface (CN1) 45

BIOS SUPPLEMENTAL 46

BIOS SETTINGS STORAGE OPTIONS 69

CABLES 71

SOFTWARE DRIVERS 72

SPECIFICATIONS 73

MECHANICAL DRAWING - TOP VIEW 74

MECHANICAL DRAWING - BOTTOM VIEW 75

APPENDIX - A 76

BEST PRACTICES 76

APPENDIX - B 80

POST CODES 80

WARRANTY INFORMATION 85

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BEFORE YOU BEGIN

WinSystems offers best practice recommendations for using and handling WinSystems embedded PCs. These methods

include valuable advice to provide an optimal user experience and to prevent damage to yourself and/or the product.

YOU MAY VOID YOUR WARRANTY AND/OR DAMAGE AN EMBEDDED PC BY FAILING TO COMPLY WITH THESE

BEST PRACTICES.

Reference Appendix - A for Best Practices.

Please review these guidelines carefully and follow them to ensure you are successfully using your embedded PC.

This product ships with a heat sink. Product warranty is void if the heat sink is removed from the product.

For any questions you may have on WinSystems products, contact our Technical Support Group at (817) 274-7553, Monday

through Friday, between 8 AM and 5 PM Central Standard Time (CST).

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Visual Index - Top View (Connectors)

Power and Reset

Ethernet2

(82567V)

J13

Ethernet1

(82583V)

J11

PATA

J14

External

Battery

J16

Audio

J10

Serial I/O

COM3/4)

ATX Signals

PBRESET

PS/2 Mouse

USB

(4/5/6/7)

USB

(0/1/2/3)

Multi-I/O

(COM1/2, Keybd,

LPT)

Digital I/O

(Ports 0/1/2)

J12

Digital I/O

(Ports 3/4/5)

J18

PC/104-Plus

J15

PC/104 (C/D)

J19

Analog VGA

J20

LVDS

J24

Backlight

J26

Fan Control

J17

PC/104 (A/B)

J23

SATA 2

J25

SATA 1

RESERVED - JP1, JP2, JP3, JP4, JP12, JP14, JP17

NOTE: The reference line to each component part has been drawn to Pin 1, and is also highlighted with a square, where applicable.

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JP7

COM3

Termination

JP6

COM4

Termination

JP9 CompactFlash (Master/Slave)

D27

IDE/SATA

Activity LED

JP10

COM2

Termination

Visual Index - Top View (Jumpers & LEDs)

JP8

Digital I/O Power

(J12)

JP5

Digital I/O Power

(J9)

Status LED

JP16

EEPROM Enable

JP15

EEPROM Enable

JP11

COM1

Termination

JP13

LVDS Power

RESERVED - JP1, JP2, JP3, JP4, JP12, JP14, JP17

NOTE: The reference line to each component part has been drawn to Pin 1, and is also highlighted with a square, where applicable.

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J27

MiniPCI

Visual Index - Bottom View

J28

CompactFlash

J203

Memory1

J204

Memory2

RESERVED - JP1, JP2, JP3, JP4, JP12, JP14, JP17

NOTE: The reference line to each component part has been drawn to Pin 1, and is also highlighted with a square, where applicable.

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Jumper Reference

NOTE: Jumper Part# SAMTEC 2SN-BK-G is applicable to all jumpers. These are available in a ve piece kit from

WinSystems (Part# KIT-JMP-G-200).

JP9 - CompactFlash

JP9

□ □ 2

CompactFlash Master (default) 1-2

CompactFlash Slave 1 2

JP11 - COM1, JP10 - COM2, JP7 - COM3, JP6 - COM4

JP11

2 4 6 8

□ □ □ □

□ □ □ □ 1 3 5 7

RS-422 Termination and Biasing Resistors

TX (100): Places a 100Ω Resistor across the TX+/TX- pair 3-4

RX (100): Places a 100Ω Resistor across the RX+/RX- pair 7-8

Places a 100Ω Resistor from +5V to TX+ 1-2

TX(300):

RS-485 Termination and Biasing Resistors

TX (100): Places a 100Ω Resistor across the TX/RX+/TX/RX- pair 3-4

TX/RX(300):

Places a 100Ω Resistor between TX+ and TX- 3-4

Places a 100Ω Resistor from Ground to TX- 5-6

Places a 100Ω Resistor from +5V to TX/RX+ 1-2

Places a 100Ω Resistor between TX/RX+ and TX/RX- 3-4

Places a 100Ω Resistor from Ground to TX/RX- 5-6

JP10

2 4 6 8

□ □ □ □

□ □ □ □ 1 3 5 7

JP7

2 4 6 8

□ □ □ □

□ □ □ □ 1 3 5 7

JP6

2 4 6 8

□ □ □ □

□ □ □ □ 1 3 5 7

JP15, JP16 - EEPROM Enable

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JP15

□

JP16

□

EEPROM Enable JP15 JP16

CMOS EEPROM Enable (default) 1-2 1-2

CMOS EEPROM Disable Open Open

JP13 - Panel Power

Jumper Reference (cont’d)

JP13

□

Panel Power

JP5 - Digital I/O VCC for J9

JP5

□

+5V is provided at pin 49 of J9 1-2

No Power at Pin 49 of J9 (default) OPEN

JP8 - Digital I/O VCC for J12

JP8

□

+5V is provided at pin 49 of J12 1-2

No Power at Pin 49 of J12 (default) OPEN

Avoid Simultaneous Jumpering of pins 1-2 and 2-3.

Misjumpering panel power causes damage to the

board and/or the Flat Panel.

5V 1-2

3.3V (default) 2-3

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INTRODUCTION

This manual is intended to provide the necessary information regarding conguration and usage of the EBC-C384 single

board computer. WinSystems maintains a Technical Support Group to help answer questions not adequately addressed

in this manual. Contact Technical Support at (817) 274-7553, Monday through Friday, between 8 AM and 5 PM Central

Standard Time (CST).

FEATURES

CPU

• Intel® ATOM™ D525 (1.80 GHz) dual core

Compatible Operating Systems

• Linux, Windows Embedded Standard, and other x86 compatible OS

Memory

• Up to 4 GB of DDR3 SODIMM (Socketed) for EBC-C384-D2-1

BIOS

• Phoenix

Video

• Analog VGA resolution up to SXGA 1400x1050

• LVDS 18-bit support up to 1366x768 or 1280x800

• Simultaneous LVDS and CRT video supported

Ethernet

• 2 Intel® 10/100/1000 Mbps controllers (one using PC82574 and one using ICH8M LAN)

Storage

• 2 SATA (2.0) channels

• 1 PATA channel shared with CompactFlash socket

Digital I/O

• 48 GPIO Bidirectional lines (WS16C48)

Bus Expansion

• PC/104

• PC/104-Plus

• MiniPCI

Serial I/O

• 4 serial ports (RS-232/422/485)

Line Printer Port

• SPP/EPP supported

USB

• 8 USB 2.0 ports

Watchdog Timer

• Adjustable from 1 second to 255 minute reset

Audio

• HD Audio supported

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Power

• +5V required, 2.9A typical

Industrial Operating Temperature

• -40°C to 75°C

Mechanical

• EBX-compliant

• Dimensions: 5.75” x 8.00” (147 mm x 203 mm)

• Weight: 16 oz (453.59 g) (with heatsink)

Additional Features

• RoHS compliant

• Backlight power supported

• Custom splash screen on start-up

• Real-time clock/calendar

System

The EBC-C384 is an Intel® ATOM™ Single Board Computer (SBC) which uses either a 1.66 GHz single core Intel

N455 or 1.80 GHz dual core D525 processor paired with the ICH8M controller hub. This is an EBX-compatible unit and

incorporates two 10/100/1000 Mbps Ethernet controllers, two SATA channels, one PATA channel, 48 lines of digital I/O,

four serial RS-232/422/485 ports, watchdog timer, PS/2 keyboard and mouse controller, and LPT. The SBC also supports

HD audio, USB ports, and is equipped with a CompactFlash socket and MiniPCI card socket.

Memory

The EBC-C384-D2-1 board supports up to 4 GB DDR3 SODIMM system memory via on-board sockets located at J203

and J204.

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FUNCTIONALITY

I/O Port Map

Following is a list of I/O ports used on the EBC-C384.

NOTE: The EBC-C384 uses a PnP BIOS resource allocation. Care must be taken to avoid contention with resources

allocated by the BIOS.

HEX Range Usage

0000h-001Fh DMA Controller 82C37

0020h-0021h Interrupt Controller PIC 8259

0024h-0025h Interrupt Controller

0028h-0029h Interrupt Controller

002Ch-002Dh Interrupt Controller

002Eh-002Fh Forward to Super IO

0030h-0031h Interrupt Controller

0034h-0035h Interrupt Controller

0038h-0039h Interrupt Controller

003Ch-003Dh Interrupt Controller

0040h-0043h Timer counter 8254

004Eh-004Fh Forward to Super IO

0050h-0053h Timer counter 8254

0060h Keyboard data port

0061h NMI controller

0062h 8051 download 4K address counter

0064h Keyboard status port

0066h 8051 download 8-bit data port

0070h-0077h RTC Controller

0080h-0091h DMA Controller

0092h Reset Generator

0093h-009Fh DMA Controller

00A0h-00A1h Interrupt Controller PIC 8259

00A4h-00A5h Interrupt Controller

00A8h-00A9h Interrupt Controller

0ACh-00ADh Interrupt Controller

00B0h-00B1h Interrupt Controller

00B2h-00B3h Power Management

00B4h-00B5h Interrupt Controller

00B8h-00B9h Interrupt Controller

00C0h-00DFh DMA Controller 82C37

00F0h FERR#/IGNNE/Interrupt Controller

0120h-012Fh Digital I/O (Default)

0140h-01FFh Reserved *

0170h-0177h IDE1 Controller

0180h-01FFh Reserved

0298h-029Bh Reserved for Super I/O Conguration

029C Interrupt Status Register

029D Status LED Register

029E-029F Watchdog Timer Control

02E8h-02EFh COM4 (Default)

02F8h-02FFh COM2 (Default)

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HEX Range Usage

0340h-03E7h Reserved *

0376h IDE1 Controller

0378h-037Bh LPT (Default)

03E8h-03EFh COM3 (Default)

03F0h-03F5h Reserved

03F6h IDE0 Controller

03F8h-03FFh COM1 (Default)

04D0h-4D1h Interrupt Controller

0564h-0568h Advanced Watchdog

0CF9h Reset Generator

This product utilizes a LPC to ISA Bridge to address the PC/104 bus. The majority of legacy PC/104 modules are I/O mapped and function as expected. However, neither DMA nor memory mapped PC/104 modules are supported with this product. The PC/104-Plus PCI signals are completely supported.

* The ICH8M limits the LPC (ISA) decode ranges to four windows, two of which can be adjusted in the BIOS. For example, the 0300-033Fh range can be changed to 0600-06FFh so the full 256 bytes are available for PC/104 modules. Resources addressed internally may still exist in these ranges so please check the I/O map for availability.

The advanced watchdog timer is the only on-board device affected by adjusting LPC (ISA) decode range. It will not be available if the 0564-0568h decode range is disabled.

The default is for the PC/104 decode ranges are shown below. Please contact an Applications Engineer if you have questions regarding the decode ranges.

0100-013Fh 64 Bytes (Fixed)

0200-02FFh 256 Bytes (Fixed)

0300-033Fh 64 Bytes (BIOS Selectable)

0500-05FFh 256 Bytes (BIOS Selectable)

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Interrupt Map

Hardware Interrupts (IRQs) are supported for both PC/104 (ISA), PCI and PCIe devices. The user must reserve IRQs in

the BIOS CMOS conguration for use by legacy devices. The PCIe/PnP BIOS will use unreserved IRQs when allocating

resources during the boot process. The table below lists IRQ resources as used by the EBC-C384.

IRQ0 18.2 Hz heartbeat

IRQ1 Keyboard

IRQ2 Chained to Slave controller (IRQ9)

IRQ3 COM2 *

IRQ4 COM1 *

IRQ5 COM3 *

IRQ6 COM4 *

IRQ7 LPT *

IRQ8 Real Time Clock

IRQ9 FREE **

IRQ10 Digital I/O

IRQ11 PCI Interrupts

IRQ12 Mouse

IRQ13 Floating point processor

IRQ14 IDE

IRQ15 IDE

These IRQ references are default settings that can be changed by the user in the CMOS Settings

utility. Reference the Super I/O Control section under Intel.

IRQ9 is commonly used by ACPI when enabled and may be unavailable (depending on operating

system) for other uses.

*** IRQ15 is currently unavailable under the Windows operating systems.

Some IRQs can be freed for other uses if the hardware features they are assigned to are not being used. To free an interrupt, use the CMOS setup screens to disable any unused board features or their IRQ assignments.

Interrupt Status Register - 29CH

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N/A N/A N/A N/A COM4 COM3 COM2 COM1

Note: A 1 will be read for the device(s) with an interrupt pending.

WinSystems does not provide software support for implementing the Interrupt Status

have support for sharing serial port interrupts and examples are available. The user will

need to implement the appropriate software to share interrupts for the other devices.

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PCI Devices and Functions

Bus:Device:Function Function Description

Bus 0:Device 0:Fun: 0 Processor Host Bridge/DMI Controller

Bus 0:Device 2:Fun: 0 Processor Host Bridge/Graphics Controller

Bus 0:Device 25:Fun: 0 Internal GbE Controller

Bus 0:Device 26:Fun: 1 USB UHCI Controller

Bus 0:Device 26:Fun: 7 USB UHCI Controller

Bus 0:Device 26:Fun: 7 USB EHCI Controller

Bus 0:Device 27:Fun: 0 Intel High Denition Audio Controller

Bus 0:Device 28:Fun: 0 PCI Express Port 1

Bus 0:Device 28:Fun: 1 PCI Express Port 2

Bus 0:Device 29:Fun: 0 USB UHCI Controller

Bus 0:Device 29:Fun: 1 USB UHCI Controller

Bus 0:Device 29:Fun: 2 USB UHCI Controller

Bus 0:Device 29:Fun: 7 USB EHCI Controller

Bus 0:Device 30:Fun: 0 PCI-to-PCI Bridge

Bus 0:Device 31:Fun: 0 LPC Bridge

Bus0:Device 31:Fun: 0 IDE Controller

Bus 0:Device 31:Fun: 2 SATA Controller

Bus 0:Device 31:Fun: 3 SMBus Controller

Bus 0:Device 31:Fun: 6 ICH8M Thermal Subsystem

Bus 1:Device 0:Fun: 0 External GbE Controller

Bus 2:Device 0:Fun: 0 PCI Express MiniCard

Bus 3:Devicex:Fun: 0 PCI 2.0

DOS Legacy Memory Map

HEX Range Usage

0000:0000-0009:FFFF Main Memory (DOS area)

000A:0000-000B:FFFF Legacy Video Area (SMM Memory)

000C:0000-000D:FFFF Expansion Area

000E:0000-000E:FFFF Extended System BIOS (Lower)

000F:0000-000F:FFFF System BIOS (Upper)

0010:0000-TOM (Top of Memory) Main Memory

FEC0:0000-FEC7:FFFF IO APIC

FED0:x000-FED0:x3FF High Precision Event Timers

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Watchdog Timer

The EBC-C384 features an advanced watchdog timer which can be used to guard against software lockups. Two

interfaces are provided to the watchdog timer. The Advanced interface is the most exible and recommended for new

designs. The other interface option is provided for software compatibility with older WinSystems single board computers.

Advanced

The watchdog timer can be enabled in the BIOS Settings by entering a value for Watchdog Timeout on the Intel → Super

I/O Control screen. Any non-zero value represents the number of minutes prior to reset during system boot. Once the

operating system is loaded, the watchdog can be disabled or recongured in the application software.

NOTE: It is recommended that a long timeout be used if the watchdog is enabled when trying to boot any operating

system.

The watchdog can be enabled, disabled or reset by writing the appropriate values to the conguration registers located

at I/O addresses 565h and 566h. The watchdog is enabled by writing a timeout value other than zero to the I/O address

566h and disabled by writing 00h to this I/O address. The watchdog timer is serviced by writing the desired timeout value

to I/O port 566h. If the watchdog has not been serviced within the allotted time, the circuit resets the CPU.

The timeout value can be set from 1 second to 255 minutes. If port 565h bit 7 equals 0, the timeout value written into I/O

address 566h is in minutes. The timeout value written to address 566h is in seconds if port 565 bit 7 equals 1.

Watchdog Timer Examples

Port Address Port Bit 7 Value Port Address Value Reset Interval

565H x 566H 00h DISABLED 565H 1 566H 03h 3 SECONDS 565H 1 566H 1Eh 30 SECONDS 565H 0 566H 04h 4 MINUTES 565H 0 566H 05h 5 MINUTES

Software watchdog timer PET = PORT 566H, write the timeout value.

Standard (requires changing the default I/O ranges within in the BIOS)

The watchdog can be enabled or disabled via software by writing an appropriate timeout value to I/O port 29H. See the

chart provided below.

Port Address Value Reset Interval

00h DISABLED

29EH

29FH ANY RESET TIMER

01h 3 SECONDS 03h 30 SECONDS 05h 300 SECONDS

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Real-Time Clock/Calendar

A real-time clock is used as the AT-compatible clock/calendar. It supports a number of features including periodic and

alarm interrupt capabilities. In addition to the time and date keeping functions, the system conguration is kept in CMOS

RAM contained within the clock section. A battery must be enabled for the real-time clock to retain time and date during a

power down.

STATUS LED

D6 - Status LED

A status LED is populated on the board at D6, which can be used for any application purpose. The LED is turned on

during the boot process and can be turned off by writing a 0 to hex address 0x29D bit 0. The status LED can then be

toggled on by writing a 1 and off by writing a 0 to the same address.

D6 -- GREEN STATUS

Visual Index

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CONNECTOR REFERENCE

POWER

J6 - Power and Reset

PCB Connector: MOLEX 26-60-6092 (J6) Mating Connector: MOLEX 09-50-8093 (Housing) MOLEX 08-58-0189 (Crimp)

+5V

GND

+12V

Not Used

GND

+5V

-12V

ATX_PWRGOOD

□ □ □ □ □ □ □ □ □ 1 2 3 4 5 6 7 8 9

Visual Index

CBL-236-G-2-1.5

Power is applied to the EBC-C384 via the connector at J6. WinSystems offers the cable CBL-236-G-2-1.5 to simplify this

connection.

J26 - Fan Power

Visual Index

Mating Connector: MOLEX 22-11-2032 (J26)

J26

□

GND

□

VCC

□

TACH

J2 - Push Button Reset

Visual Index

PCB Connector: MOLEX 22-29-2021 (J2) Mating Connector: MOLEX 10-11-2023 (Housing) MOLEX 08-55-0124 (Crimp)

□

RESET

□

GND

WinSystems offers the cable CBL-RST-402-18 to simplify this connection.

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J3 - ATX Signals

Visual Index

PCB Connector: MOLEX 22-11-2042 (J3) Mating Connector: MOLEX 22-01-2045 (Housing) MOLEX 08-55-0110 or 08-55-0111 (Crimp)

□

PSON_OUT

□

+5VSB_PWR

□

PWR_BTN

□

GND

ATX signals for the power button, reset and power good are provided at J3. WinSystems offers the cable

CBL-PWR-600-14 to simplify this connection.

The EBC-C384 supports either AT (standard power supply) or ATX type power supplies. Zero load supplies are

recommended. An AT power supply is a simple on/off supply with no interaction with the single board computer. Most

embedded systems use this type of power supply and it is the default setting. The EBC-C384 power circuit will detect an

AT power supply if +5 VSB is not present at startup.

ATX type power supplies function with a “soft” on/off power button and a +5 VSB (standby). If an ATX compatible power

supply is connected, a power button (momentary contact) connected between pin 3 (power button) and pin 4 (ground)

of J3. The +5 VSB signal provides the standby voltage to the EBC-C384, but does not power any other features of the

board. When the power button is pressed, the EBC-C384 pulls PSON (Power Supply On) low and the power supply turns

on all voltages to the single board computer. When the power button is pressed again, the BIOS signals the event so

ACPI-compliant operating systems can be shutdown before the power is turned off. In ATX mode, if the power button is

held for 4 seconds, the power supply is forced off, regardless of ACPI. Since this is software driven, it is possible that

a software lockup could prevent the power button from functioning properly. The EBC-C384 will detect an ATX power

supply, if +5 VSB is present at startup.

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BATTERY BACKUP

J14 - External Battery

Visual Index

PCB Connector: MOLEX 22-11-2034 (J14) Mating Connector: MOLEX 22-01-3037 (Housing) MOLEX 08-55-0102 (Crimp)

J14

□

VBAT

□

GND

(For external battery. Provides battery backup to RTC and BIOS CMOS.)

WARNING: BAT-LTC-E-36-16-1 or BAT-LTC-E-36-27-1 must be connected at J14.

Improper installation of the battery could result in explosive failure. Please be careful to note correct connection at location J14.

An optional external battery, connected at J14, supplies the EBC-C384 board with standby power for the real-time

clock, CMOS setup RAM and SRAM (applicable models only). An extended temperature lithium battery is available

from WinSystems, part number BAT-LTC-E-36-16-1 or BAT-LTC-E-36-27-1.

A power supervisory circuit contains the voltage sensing circuit and an internal power switch to route the battery

or standby voltage to the circuits selected for backup. The battery automatically switches ON when the VCC of the

systems drops below the battery voltage and back OFF again when VCC returns to normal.

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VIDEO

J19 - ANALOG VGA

PCB Connector: MOLEX 87832-1420 (J19) Mating Connector: MOLEX 51110-1451 (Housing) MOLEX 50394-8051 (Crimp)

J19

□ □

GND

VCC

RED

GREEN

BLUE

HSYNC

VSYNC

DDCDATA

DDCCLK

Visual Index

CBL-234-G-1-1.375

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J20 - LVDS

PCB Connector: MOLEX 501571-4007 (J20) Mating Connector: MOLEX 501189-4010 (Housing) MOLEX 501193-2000 (Crimp)

J20

□

SWVDD

D0-

D1-

SWVDD

D2-

SWVDD

CLK-

DDC_CLK

DDC_DATA

SWVDD

□

Visual Index

GND

D0+

D1+

GND

D2+

GND

CLK+

GND

J24 - Backlight Power

PCB Connector: MOLEX 501131-1107 (J24) Mating Connector: MOLEX 501330-1100 (Housing) MOLEX 501334-0000 (Crimp)

J24

VCC

ENABLE (Low)

ENABLE (High)

BKLT_A

BKLT_C

LCTL_B DATA

LCTL_A CLK

HAZARD WARNING: LCD panels can require a high voltage for the panel backlight. This

high-frequency voltage can exceed 1000 volts and can present a shock hazard. Care should be taken when wiring and handling the inverter output. To avoid the danger of shock and to avoid the panel, make all connection changes with the power removed.

GND

+12V

Visual Index

□

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JP13 - Panel Power

Visual Index

JP13

□

Panel Power

Avoid Simultaneous Jumpering of pins 1-2 and 2-3.

Misjumpering panel power causes damage to the

board and/or the Flat Panel.

5V 1-2

3.3V (default) 2-3

The EBC-C384 has an integrated display controller that interfaces to both Analog VGA and at panel displays. The video

output mode is selected in the CMOS setup. Simultaneous at panel and Analog VGA mode is also supported. The

Analog VGA connector is located at J19. WinSystems offers the cable CBL-234-G-1-1.375 to simplify the connection.

The LVDS interface connector is located at J20 to interface to at panels. A backlight power connectors is located at J24.

Panel power option selection is made at JP13.

Contact your WinSystems’ Applications Engineer for information about available cable kits and supported panels.

This manual does not attempt to provide any information about how to connect to specic LCDs.

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AUDIO

J16 - HD Audio

PCB Connector: MOLEX 5020463070 (J16) Mating Connector: MOLEX 5031103000 (Housing) MOLEX 501930-1100 (Crimp)

J16

□

ADGND

CD-GND

CD-L

CD-R

ADGND

LINE-L

LINE-R

ADGND

MIC2-REAR-L

MIC2-REAR-R

ADGND

MIC1-REAR-L

MIC1-REAR-R

ADGND

□

HEADPHONE-L

□

HEADPHONE-R

□

ADGND

□

SIDE-L

□

SIDE-R

□

ADGND

□

LFE

□

CENTER

□

ADGND

□

SUR-L

□

SUR-R

□

ADGND

□

OUT-L

□

OUT-R

Visual Index

Audio External Connection

The Intel HD Audio controller is included with a Realtek ALC662 codec.

Audio connection is provided at J16. Three cables are available from WinSystems to adapt to this connector.

CBL-AUDIO7-102-12 provides full 7.1 audio support. A simplied cable, CBL-AUDIO2-102-12, provides basic Line In, Line

Out, and Microphone audio support and CBL-AUDIO5-102-12 provides 5.1 audio support.

140703

CBL-AUDIO7-102-12

CBL-AUDIO2-102-12

CBL-AUDIO5-102-12

SP1 - Speaker

Speaker

An on-board speaker, SP1, is available for sound generation.

Beep Codes

Reference the chart Appendix-B section of this manual for the appropriate beep codes.

140703

MULTI-I/O

Visual

J7 - Multi-I/O (COM1, COM2, Keyboard, LPT)

PCB Connector: TEKA SVC225C405M123-0 (J7) Mating Connector: ITW-PANCON 050-050-455A

The interface to I/O serial ports (COM1/COM2), the printer port and keyboard are all terminated via the connector at J7.

A cable, part number CBL-247-G-1-1.0, is available from WinSystems to adapt to the conventional I/O connectors. The

pinout denition for J7 is listed below.

(COM1) DSR

(COM1) RTS

(COM1) CTS

(COM1) RI

(COM2) DCD

(COM2) RXD

(COM2) TXD

(COM2) DTR

(COM2) GND

(LPT) AUTOFD

(LPT) ERROR

(LPT) INIT

(LPT) SLCTIN

(LPT) GND

(KEYBD) GND

(KEYBD) KCLK

(KEYBD) +5V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

Index

Multi-I/O

DTR (COM1)

TXD (COM1)

RXD (COM1)

DCD (COM1)

DSR (COM2)

GND (COM1)

CBL-247-G-1-1.0

RI (COM2)

RTS (COM2)

CTS (COM2)

PD2 (LPT)

PD1 (LPT)

PD0 (LPT)

STROBE (LPT)

PD5 (LPT)

PD4 (LPT)

PD3 (LPT)

PD7 (LPT)

PD6 (LPT)

ACK (LPT)

PE (LPT)

SLCT (LPT)

BUSY (LPT)

+5V (KEYBD)

GND (KEYBD)

KDATA (KEYBD)

COM1

COM2

LPT

PS/2

Keybd

140703

COM1, COM2 [DB9 Male]

Pin RS-232 RS-422 RS-485

1 DCD N/A N/A 2 RX TX+ TX/RX+ 3 TX TX- TX/RX- 4 DTR N/A N/A 5 GND GND GND 6 DSR RX+ N/A 7 RTS RX- N/A 8 CTR N/A N/A 9 RI N/A N/A

All serial ports are congured as Data Terminal Equipment (DTE). Both the send and receive registers of each port

have a 16-byte FIFO. All serial ports have 16C550-compatible UARTs. The RS-232 transceivers have charge pumps to

generate the plus and minus voltages so the EBC-Z5xx only requires +5V to operate.

Each port is setup to provide internal diagnostics such as loopback and echo mode on the data stream. An independent,

software programmable baud rate generator is selectable from 50 through 115.2 kbps. Individual modem handshake

control signals are supported for all ports.

COM1 and COM2 Conguration Options in BIOS

1. RS-232 Mode

2. RS-422 Mode with RTS transmitter enable

3. RS-422 Mode with auto transmitter enable

4. RS-485 Mode with RTS transmitter enable

5. RS-485 Mode with RTS transmitter enable and echo back

6. RS-485 Mode with auto transmitter enable

7. RS-485 Mode with auto transmitter enable and echo back

Mode(s) Conguration Note

2, 4, 5 Require the RTS bit (MCR Bit 1) to be set in order to transmit.

3, 6, 7 Require TX/RX(300) termination on one node.

4 Requires the RTS (MCR Bit 1) be de-asserted in order to receive.

* Each of the RS-422/RS-485 modes allow for jumper selection of transmit and/or receive termination and

biasing resistor(s). An 8-pin conguration jumper is provided for each port.

Termination Resistors

140703

COM1 = JP11

COM2 = JP10

□ □

RS-422 Termination and Biasing Resistors

TX (100): Places a 100Ω Resistor across the TX+/TX- pair 3-4

RX (100): Places a 100Ω Resistor across the RX+/RX- pair 7-8

Places a 100Ω Resistor from +5V to TX+ 1-2

TX(300):

RS-485 Termination and Biasing Resistors

TX (100): Places a 100Ω Resistor across the TX/RX+/TX/RX- pair 3-4

TX/RX(300):

Places a 100Ω Resistor between TX+ and TX- 3-4

Places a 100Ω Resistor from Ground to TX- 5-6

Places a 100Ω Resistor from +5V to TX/RX+ 1-2

Places a 100Ω Resistor between TX/RX+ and TX/RX- 3-4

Places a 100Ω Resistor from Ground to TX/RX- 5-6

LPT [DB25 Female]

14 25

1 13

Pin SPP Signal

1 STROBE 2-9 PD0-PD7 10 ACK 11 BUSY 12 PE 13 SLCT 14 AUTOFD 15 ERROR 16 INIT 17 SLCTIN 18-25 GND

The LPT port is a multimode parallel printer port that supports the PS/2 Standard Bidirectional Parallel Port (SPP) and

Enhanced Parallel Port (EPP) functionality. The output drivers support 8 mA per line.

The printer port can also be used as two additional general-purpose I/O ports if a printer is not required. The rst port is

congured as eight input or output only lines. The other port is congured as ve input and three output lines.

PS/2 Keyboard [6-Position]

Pin Description

1 KD ATA 2 NC 3 GND 4 +5V 5 KCLK 6 NC

This connector supports a PS/2 keyboard interface. The pinout for the cable is listed above.

140703

MOUSE

J1 - Mouse

PCB Connector: MOLEX 22-12-2054 (J1) Mating Connector: MOLEX 22-01-2057 (Housing) MOLEX 08-55-0102 (Crimp)

MSCLK

VCC

GNDNCMSDATA

□ □ □ □ □ 5 4 3 2 1

Visual Index

PS/2 Mouse [6-Position]

CBL-343-G-1-1.375

140703

SERIAL

J10 - COM3, COM4

PCB Connector: TEKA SVC210C405M123-0 (J10) Mating Connector: ITWPANCON 050-020-455A

(COM3) DSR

(COM3) RTS

(COM3) CTS

(COM3) RI

(COM4) DSR

(COM4) RTS

(COM4) CTS

(COM4) RI

2 4 6 8 10 12 14 16 18 20

J10

□ □ □ □ □ □ □ □ □ □

□ □ □ □ □ □ □ □ □ □ 1 3 5 7 9 11 13 15 17 19

Visual Index

Serial

COM3, COM4 [DB9 Male]

TXD (COM3)

RXD (COM3)

DCD (COM3)

DTR (COM3)

DCD (COM4)

GND (COM3)

DTR (COM4)

TXD (COM4)

RXD (COM4)

GND (COM4)

CBL-173-G-1-1.0

Pin RS-232 RS-422 RS-485

1 DCD N/A N/A 2 RX TX+ TX/RX+ 3 TX TX- TX/RX- 4 DTR N/A N/A 5 GND GND GND 6 DSR RX+ N/A 7 RTS RX- N/A 8 CTR N/A N/A 9 RI N/A N/A

COM3

COM4

Both ports are congured as Data Terminal Equipment (DTE). Both the send and receive registers of each port have a

16-byte FIFO. All serial ports have 16C550-compatible UARTs. The RS-232 has a charge pump to generate the plus

and minus voltages so the EBC-Z5xx only requires +5V to operate. An independent, software programmable baud rate

generator is selectable from 50 through 115.2 kbps. Individual modem handshake control signals are supported for all

ports.

140703

COM3 and COM4 Conguration Options in BIOS

1. RS-232 Mode

2. RS-422 Mode with RTS transmitter enable

3. RS-422 Mode with auto transmitter enable

4. RS-485 Mode with RTS transmitter enable

5. RS-485 Mode with RTS transmitter enable and echo back

6. RS-485 Mode with auto transmitter enable

7. RS-485 Mode with auto transmitter enable and echo back

Mode(s) Conguration Note

2, 4, 5 Require the RTS bit (MCR Bit 1) to be set in order to transmit.

3, 6, 7 Require TX/RX(300) termination on one node.

4 Requires the RTS (MCR Bit 1) be de-asserted in order to receive.

* Each of the RS-422/RS-485 modes allow for jumper selection of transmit and/or receive termination and

biasing resistor(s). An 8-pin conguration jumper is provided for each port.

RS-422 Termination and Biasing Resistors

TX (100): Places a 100Ω Resistor across the TX+/TX- pair 3-4

Termination Resistors

COM3 = JP7

COM4 = JP6

□ □

RX (100): Places a 100Ω Resistor across the RX+/RX- pair 7-8

Places a 100Ω Resistor from +5V to TX+ 1-2

TX(300):

RS-485 Termination and Biasing Resistors

TX (100): Places a 100Ω Resistor across the TX/RX+/TX/RX- pair 3-4

TX/RX(300):

Places a 100Ω Resistor between TX+ and TX- 3-4

Places a 100Ω Resistor from Ground to TX- 5-6

Places a 100Ω Resistor from +5V to TX/RX+ 1-2

Places a 100Ω Resistor between TX/RX+ and TX/RX- 3-4

Places a 100Ω Resistor from Ground to TX/RX- 5-6

140703

USB

J4, J5 - USB

PCB Connector: MOLEX 501571-2007 (J4, J5) Mating Connector: MOLEX 501189-2010 (Housing) MOLEX 501193-2000 (Crimp)

Visual Index

USB (0/1/2/3)

USBPWR0

D0-

D0+

GND

USBPWR2

D2-

D2+

GND

□

USBPWR1

□

D1-

□

D1+

□

GND

□

GND

□

GND

□

USBPWR3

□

D3-

□

D3+

□

GND

USBPWR4

D4-

D4+

GND

USBPWR6

D6-

D6+

GND

USB (4/5/6/7)

□

USBPWR5

D5-

D5+

GND

USBPWR7

D7-

D7+

GND

CBL-USB4-002-12 with ADP-10-USB-001

Up to two USB cables may be attached to the EBC-C384 via the connectors for a total of eight USB 2.0 ports.

These are terminated to 20-pin connector at J4 and J5. An adapter cable CBL-USB4-002-12 is available from

WinSystems for connection along with ADP-IO-USB-001.

140703

SERIAL ATA

J23, J25 - SATA

PCB Connector: MOLEX 67490-1220 (J23, J25)

J23, J25

□

GND

□

TX1+

□

TX1-

□

GND

□

RX1-

□

RX1+

□

GND

The EBC-C384 supports two SATA interfaces located at J23 and J25.

COMPACTFLASH

J28 - CompactFlash

Visual Index

JP9

□ □ 2

CompactFlash Master (default) 1-2

CompactFlash Slave 1 2

When using a CompactFlash device, Master/Slave selection is made using jumper eld JP9. The EBC-C384

supports solid state CompactFlash storage devices for applications where the environment is too harsh for

mechanical hard disks.

The CompactFlash socket at J28 supports modules with TrueIDE support. WinSystems offers industrial grade

CompactFlash modules that provide high performance and extended temperature operation (-40ºC to +85ºC).

140703

PARALLEL ATA

J11 - PATA

PCB Connector: SAMTEC STMM-122-02-G-D-SM-P-TR (J11) Mating Connector: SAMTEC ASP-129789-01

GND

VCC

LED

HDSC0

IRQ

DACK

RDY

IOR

IOW

DRQ

GND

43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □

J11

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □

44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

Visual Index

RESET*

GND

VCC

GND

HDSC1

GND

66/100 MHz

GND

D15

D14

D13

D12

D11

The EBC-C384 supports the PATA interface at J11 (44-pin primary).

D10

GND

140703

ETHERNET

J13, J8 - Gigabit Ethernet

Gigabit Ethernet Controllers

The EBC-C384 is equipped with two Intel Gigabit Ethernet controllers, one using the 82583 controller and the other using

the 82567 controller. Each of these provides a standard IEEE 802.3 Ethernet interface for 1000/100/10BASE-T networks.

The RJ-45 connections for each Ethernet port are available at J13 (Port 1) and J8 (Port 2). Wake On LAN is provided via

controller J8.

Visual Index

(82567V Controller)

(82583V Controller)

J13

140703

DIGITAL I/O

J9, J12 - Digital I/O

PCB Connector: TEKA SVC225C405M123-0 (J9, J12) Mating Connector: ITW-PANCON 050-050-455A (Housing)

GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

(Ports 0/1/2)

J12

(Ports 3/4/5)

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

Port 0 Bit 7

Port 1 Bit 0

Port 1 Bit 1

Port 1 Bit 2

Port 1 Bit 3

Port 1 Bit 4

Port 1 Bit 5

Port 1 Bit 6

Port 1 Bit 7

Port 2 Bit 0

Port 2 Bit 1

Port 2 Bit 2

Port 2 Bit 3

Port 2 Bit 4

Port 2 Bit 5

Port 2 Bit 6

Port 2 Bit 7

GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

GND

Port 0 Bit 4

Port 0 Bit 5

Port 0 Bit 6

GND

Port 0 Bit 1

Port 0 Bit 2

Port 0 Bit 3

GND

+3.3V/5V

Port 0 Bit 0

GND

Visual Index

+3.3V/5V

Port 3 Bit 0

Port 3 Bit 1

Port 3 Bit 2

Port 3 Bit 3

Port 3 Bit 4

Port 3 Bit 5

Port 3 Bit 6

Port 3 Bit 7

Port 4 Bit 0

Port 4 Bit 1

Port 4 Bit 2

Port 4 Bit 3

Port 4 Bit 4

Port 4 Bit 5

Port 4 Bit 6

Port 4 Bit 7

Port 5 Bit 0

Port 5 Bit 1

Port 5 Bit 2

Port 5 Bit 3

Port 5 Bit 4

Port 5 Bit 5

Port 5 Bit 6

Port 5 Bit 7

The EBC-C384 has 48 open collector digital I/O bits with a default base address of 120H. Each bit is congured as

an open collector with a 10K pullup. Each bit is able to sink up to 8mA. The rst 24 lines are capable of fully latched

event sensing with polarity being software programmable.

Digital I/O Connectors

These 48 lines of digital I/O are terminated through two 50-pin connectors at J9 and J12. The J9 connector handles

I/O ports 0 through 2 while J12 handles ports 3 through 5.

JP5/JP8 - Digital I/O Power

Visual Index

The I/O connectors can provide +5V to an I/O rack for miscellaneous purposes by jumpering JP5 and JP8. When JP5

is jumpered (1-2), +5V is provided at pin 49 of J9. When JP8 is jumpered (1-2), then +5V is provided at pin 49 of J12.

It is the user’s responsibility to limit current to a safe value (less than 400 mA) to avoid damaging the CPU board.

JP5 - Digital I/O VCC for J9

JP5

□

+5V is provided at pin 49 of J9 1-2

No Power at Pin 49 of J9 (default) OPEN

140703

JP8 - Digital I/O VCC for J12

JP8

□

+5V is provided at pin 49 of J12 1-2

No Power at Pin 49 of J12 (default) OPEN

The EBC-C384 uses the WinSystems exclusive ASIC device, the WS16C48. This device provides 48 lines of digital

I/O. There are 16 unique registers within the WS16C48. The following table summarizes the registers, and the text that

follows provides details on each of the internal registers.

I/O Address Offset Page 0 Page 1 Page 2 Page 3

00H Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O 01H Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O 02H Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O 03H Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O 04H Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O 05H Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O 06H Int_Pending Int_Pending Int_Pending Int_Pending 07H Page/Lock Page/Lock Page/Lock Page/Lock 08H Reserved Pol_0 Enab_0 Int_ID0 09H Reserved Pol_1 Enab_1 Int_ID1

0AH Reserved Pol_2 Enab_2 Int_ID2

Register Details

Port 0 through 5 I/O

Each I/O bit in each of the six ports can be individually programmed for input or output. Writing a 0 to a bit position

causes the corresponding output pin to go to a high-impedance state (pulled high by external 10 KΩ resistors). This

allows it to be used as an input. When used in the input mode, a read reects the inverted state of the I/O pin, such that a

high on the pin will read as a 0 in the register. Writing a 1 to a bit position causes that output pin to sink current (up to 12

mA), effectively pulling it low.

INT_PENDING

This read-only register reects the combined state of the INT_ID0 through INT_ID2 registers. When any of the lower

three bits are set, it indicates that an interrupt is pending on the I/O port corresponding to the bit position(s) that are set.

Reading this register allows an Interrupt Service Routine to quickly determine if any interrupts are pending and which I/O

port has a pending interrupt.

PAGE/LOCK

This register serves two purposes. The upper two bits select the register page in use as shown here:

D7 D6 Page

0 0 Page 0 0 1 Page 1 1 0 Page 2 1 1 Page 3

Bits 5-0 allow for locking the I/O ports. A 1 written to the I/O port position will prohibit further writes to the corresponding

I/O port.

140703

POL0 - POL2

These registers are accessible when Page 1 is selected. They allow interrupt polarity selection on a port–by–port and

bit-by-bit basis. Writing a 1 to a bit position selects the rising edge detection interrupts while writing a 0 to a bit position

selects falling edge detection interrupts.

ENAB0 - ENAB2

These registers are accessible when Page 2 is selected. They allow for port-by-port and bit-by-bit enabling of the edge

detection interrupts. When set to a 1, the edge detection interrupt is enabled for the corresponding port and bit. When

cleared to 0, the bit’s edge detection interrupt is disabled. Note that this register can be used to individually clear a

pending interrupt by disabling and re-enabling the pending interrupt.

INT_ID0 – INT_ID2

These registers are accessible when Page 3 is selected. They are used to identify currently pending edge interrupts. A

bit when read as a 1 indicates that an edge of the polarity programmed into the corresponding polarity register has been

recognized. Note that a write to this register (value ignored) clears ALL of the pending interrupts in this register.

140703

PC/104 BUS

J15, J17 - PC/104

Visual Index

PCB Connector: TEKA PC232-A-1BD-M (J17) TEKA PC220-A-1BD-M (J15)

The PC/104 bus is electrically equivalent to the 16-bit ISA bus. Standard PC/104 I/O cards can be populated on

EBC-C384’s connectors, located at J15 and J17. The interface does not support hot swap capability. The PC/104 bus

connector pin denitions are provided below for reference. Refer to the PC/104 Bus Specication for specic signal

and mechanical specications.

J15

(C/D)

□

GND

MEMCS16#

IOCS16#

IRQ10

IRQ11

IRQ12

IRQ15

IRQ14

DACK0#

DRQ0

DACK5#

DRQ5

DACK6#

DRQ6

DACK7#

DRQ7

+5V

MASTER#

GND

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

□

C10

□

C11

□

C12

□

C13

□

C14

□

C15

□

C16

□

C17

□

C18

□

C19

# = Active Low Signal

GND

SBHE#

LA23

LA22

LA21

LA20

LA19

LA18

LA17

MEMR#

MEMW#

SD8

SB9

SD10

SD11

SD12

SD13

SD14

SD15

KEY

IOCHK#

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

IOCHRDY

AEN

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

GND

SA9

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

(A/B)

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

J17

□

GND

□

RESET

□

+5V

□

IRQ

□

-5V

□

DRQ2

□

-12V

□

SRDY#

□

+12V

□

B10

KEY

□

B11

SMEMW#

□

B12

SMEMR#

□

B13

IOW#

□

B14

IOR#

□

B15

DACK3#

□

B16

DRQ3

□

B17

DACK1#

□

B18

DRQ1

□

B19

REFRESH#

□

B20

BCLK

□

B21

IRQ7

□

B22

IRQ6

□

B23

IRQ5

□

B24

IRQ4

□

B25

IRQ3

□

B26

DACK2#

□

B27

□

B28

BALE

□

B29

+5V

□

B30

OSC

□

B31

GND

□

B32

GND

NOTES:

1. Rows C and D are not required on 8-bit modules.

2. B10 and C19 are key locations. WinSystems uses key pins as connections to GND.

3. Signal timing and function are as specied in ISA specication.

4. Signal source/sink current differ from ISA values.

140703

PC/104-Plus BUS

J18 - PC/104-Plus

PCB Connector: TEKA 2MR430-BDWM-368-00

The PC/104-Plus is electrically equivalent to the 33 MHz PCI bus and is terminated to a 120-pin, nonstackthrough

connector. The standard PC/104-Plus I/O modules can be populated on EBC-C384’s PC104-Plus bus. The interface

does not support hot swap capability. The PC/104-Plus bus connector is located at J18. Refer to the PC/104-Plus

Bus Specication for specic signal and mechanical specications. The pin denitions are:

PIN A B C D

1 GND RESERVED +5V AD00

2 VI/O AD02 AD01 +5V

3 AD05 GND AD04 AD03

4 C/BE0# AD007 GND AD06

5 GND AD009 AD08 GND

6 AD11 VI/O AD10 M66EN

7 AD14 AD13 GND AD12

8 +3.3V C/BE1# AD15 +3.3V

9 SERR# GND RESERVED PAR

10 GND PERR# +3.3V RESERVED

11 STOP# +3.3V LOCK# GND

12 +3.3V TRDY# GND DEVSEL#

13 FRAME# GND IRDY# +3.3V

14 GND AD16 +3.3V C/BE2#

15 AD18 +3.3V AD17 GND

16 AD21 AD20 GND AD19

17 +3.3V AD23 AD22 +3.3V

18 IDSEL0 GND IDSEL1 IDSEL2

19 AD24 C/BE3# VI/O IDSEL3

20 GND AD26 AD25 GND

21 AD29 +5V AD28 AD27

22 +5V AD30 GND AD31

23 REQ0# GND REQ1# VI/O

24 GND REQ2# +5V GNT0#

25 GNT1# VI/O GNT2# GND

26 +5V CLK0 GND CLK1

27 CLK2 +5V CLK3 GND

28 GND INTD# +5V RST#

29 +12V INTA# INTB# INTC#

30 -12V REQ3# GNT3# GND

Visual Index

140703

MiniPCI

J27 - MiniPCI Socket

The EBC-C384 includes a MiniPCI socket at J27. Though the socket can support other devices, it is primarily intended

for adding a video module. WinSystems offers MPCI-VGA-Z9S to simplify the connection. Additionally, wireless activity

is optional via MiniPCI.

Visual Index

MiniPCI Device Interface (CN1)

PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL

1 N/C 2 N/C 63 3.3V 64 FRAME#

KEY KEY 65 CLKRUN# 66 TRDY#

3 N/C 4 N/C 67 SERR# 68 STOP#

5 N/C 6 N/C 69 GROUND 70 3.3V

7 N/C 8 N/C 71 PERR# 72 DEVSEL#

9 N/C 10 N/C 73 C/BE(1)# 74 GROUND

11 N/C 12 N/C 75 AD(14) 76 AD(15)

13 N/C 14 N/C 77 GROUND 78 AD(13)

15 N/C 16 RESERVED 79 AD(12) 80 AD(11)

17 INTB# 18 5V 81 AD(10) 82 GROUND

19 3.3V 20 INTA# 83 GROUND 84 AD(09)

21 RESERVED 22 RESERVED 85 AD(08) 86 C/BE(0)#

23 GROUND 24 3.3V AUX 87 AD(07) 88 3.3V

25 CLK 26 RST# 89 3.3V 90 AD(06)

27 GROUND 28 3.3V 91 AD(05) 92 AD(04)

29 REQ# 30 GNT# 93 RESERVED 94 AD(02)

31 3.3V 32 GROUND 95 AD(03) 96 AD(00)

33 AD(31) 34 PME# 97 5V 98 RESERVED_WIP

35 AD(29) 36 RESERVED 99 AD(01) 100 RESERVED_WIP

37 GROUND 38 AD(30) 101 GROUND 102 GROUND

39 AD(27) 40 3.3V 103 N/C 104 M66EN

41 AD(25) 42 AD(28) 105 N/C 106 N/C

43 RESERVED 44 AD(26) 107 N/C 108 N/C

45 C/BE(3)# 46 AD(24) 109 N/C 11 0 N/C

47 AD(23) 48 IDSEL 111 N/C 112 RESERVED_WIP5

49 GROUND 50 GROUND 113 N/C 114 GROUND

51 AD(21) 52 AD(22) 115 N/C 116 N/C

53 AD(19) 54 AD(20) 117 N/C 118 N/C

55 GROUND 56 PA R 11 9 N/C 120 N/C

57 AD(17) 58 AD(18) 121 RESERVED 122 N/C

59 C/BE(2)# 60 AD(16) 123 N/C 124 3.3V AUX

61 IRDY# 62 GROUND

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BIOS SUPPLEMENTAL

General Information

The EBC-C384 includes BIOS from Phoenix Technologies to assure full compatibility with PC operating systems and

software. The basic system conguration is stored in battery backed CMOS RAM within the clock/calendar. As an

alternative, the CMOS conguration may be stored in EEPROM for operation without a battery. For more information of

CMOS conguration, see the BIOS Settings Storage Options section of this manual. Access to this setup information is

via the Setup Utility in the BIOS.

Entering Setup

To enter setup, power up the computer and press F2 when either the splash screen is displayed or when the Press F2

for Setup message is displayed. It may take a few seconds before the main setup menu screen is displayed.

Navigation of the Menus

Use the Up and Down arrow keys to move among the selections and press Enter when a selection is highlighted to

enter a sub-menu or to see a list of choices. Following are images of each menu screen in the default conguration

along with a brief description of each option where applicable. Available options are listed in reference tables. Menu

values shown in bold typeface are factory defaults.

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Main Menu

System Time: 09:40:34

System Date: 04/09/2010

>IDE Primary Master None

>IDE Primary Slave None

>SATA Port 1 None

>SATA Port 2 None

System Memory: 633 KB

Extended Memory: 2085888 KB

Ethernet MAC Address 1: xx:xx:xx:xx:xx:xx

Ethernet MAC Address 2: xx:xx:xx:xx:xx:xx

CPU Temperature: 50 °C/132 °F

Ambient Temperature: 40 °C/104 °F

Each available option is listed in detail in the following sections.

Navigation to the screens is located at the top of each screen’s layout.

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Depending on the Primary Master Type, various Primary Master options will be available. See the following screens.

Main Menu > IDE Primary Master/Slave [None]

Type: Auto

Multi-Sector Transfers: Disabled

LBA Mode Control: Disabled

32 Bit I/O: Disabled

Options:

Disabled Enabled

Transfer Mode: FPIO 4 / DMA 2

Ultra DMA Mode: Disabled | (Mode 2 for IDE Primary Slave only)

SMART Monitoring Disabled

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Depending on the Primary Master Type, various Primary Master options will be available. See the following screens.

Main Menu > SATA Port 1 / SATA Port 2

Type: Auto

Multi-Sector Transfers: Disabled

LBA Mode Control: Disabled

32 Bit I/O: Disabled

Options:

Disabled Enabled

Transfer Mode: Standard

Ultra DMA Mode: Disabled

SMART Monitoring Disabled

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Advanced

Installed O/S: Win95

Options:

Other Win95 Win98 WinMe Win2000

Reset Conguration Data: No

Options:

No Yes

Large Disk Access Mode: DOS

Options:

Other DOS

Summary screen: Disabled

Options:

Disabled Enabled

Boot-time Diagnostic Screen: Enabled

Options:

Disabled Enabled

QuickBoot Mode: Enabled

Options:

Disabled Enabled

Extended Memory Testing: None

Options:

Normal Just zero it None

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel

> CPU Control Sub-Menu

> Video (Intel IGD) Control Sub-Menu

> ICH Control Sub-Menu

> Super I/O Control Sub-Menu

> ACPI Control Sub-Menu

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > CPU Control Sub-Menu

Hyperthreading: Enabled

Options:

Disabled Enabled

Processor Power Management: Enabled

Options:

Disabled GV3 Only C-States Only Enabled

Enhanced C-States Enable: Enabled

Options:

Disabled Enabled

Timestamp Counter Updates Enabled

Options:

Disabled Enabled

> CPU Thermal Control Sub-Menu

Set Max Ext CPUID = 3 Disabled

Options:

Disabled Enabled

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > CPU Control Sub-Menu > CPU Thermal Control Sub-Menu

Thermal Control Circuit: Disabled

Options: Disabled TM1 TM2 TM1 and TM2

DTS Enable: Disabled

Options:

Disabled Enabled

Active Trip Point: 55 C

Options:

Disabled 55 C 63 C 71 C 79 C 87 C 95 C 103 C 111 C 119 C

Passive Cooling Trip Point: 95 C

Options:

Disabled 55 C 63 C 71 C 79 C 87 C 95 C 103 C 111 C 119 C

Passive TC1 Value: 1

Passive TC2 Value: 5

Options:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

More CPU Thermal Control Sub-Menu options are continued on the next page.

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > CPU Control Sub-Menu > CPU Thermal Control Sub-Menu (continued)

Passive TSP Value: 10

Options:

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Critical Trip Point: POR

Options:

POR 15 C 23 C 31 C 39 C 47 C 55 C 63 C 71 C 79 C 87 C 95 C 103 C 111 C 119 C 127 C

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > Video (Intel IGD) Control Sub-Menu

IGD - VBIOS Boot Type: CRT

Options:

VBT Default CRT LFP CRT+LFP

> IGD - LCD Control Sub-Menu

DVMT 4.0 Mode: Auto

Options:

Fixed DVMT Auto

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > Video (Intel IGD) Control Sub-Menu > IGD - LCD Control Sub-Menu

IGD - LCD Panel Type: 3: 1024x768 LVDS

Options:

1: 640x480 LVDS 2: 800x600 LVDS 3: 1024x768 LVDS 4: 1280x1024 LVDS 5: 1400x1050LVDS1 6: 1400x1050 LVDS2 7: 1600x1200 LVDS 8: 1280x768 LVDS 9: 1680x1050 LVDS 10: 1920x1200 LVDS 11: Reserved 12: Reserved 13: Reserved 14: 1280X800 LVDS 15: 1280X600 LVDS 16: Reserved

IGD - Panel Scaling: Auto

Options:

Auto Force Scaling Off

GMCH BLC Control: GMBus

Options:

Disabled PWM GMBus

BIA Control Disabled

Options:

Automatic Disabled Level 1 Level 2 Level 3 Level 4 Level 5

Spread Spectrum Clock Chip: Off

Options:

Off Hardware Software

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > ICH Control Sub-Menu

> Integrated Device Control Sub-Menu

Serial IRQ Quiet Mode: Enabled

Options:

Disabled Enabled

Pop Up Mode Enable: Enabled

Options:

Disabled Enabled

Pop Down Mode Enable: Enabled

Options:

Disabled Enabled

LPC Decode Range 1 Base Address: 300h

LPC Decode Range 1 Size: 128 Bytes

Options:

128 Bytes 64 Bytes 32 Bytes 16 Bytes 8 Bytes 4 Bytes

LPC Decode Range 2 Base Address: 500h

LPC Decode Range 2 Size: 256 Bytes

Options:

256 Bytes 128 Bytes 64 Bytes 32 Bytes 16 Bytes 8 Bytes 4 Bytes

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > ICH Control Sub-Menu > Integrated Device Control Sub-Menu

> PCI Express Control Sub-Menu

> ICH USB Control Sub-Menu

Azalia - Device 27, Function 0: Auto

Options:

Disabled Auto

AHCI Conguration: Disabled

Options:

Disabled Enabled

Disable Vacant Ports: Disabled

Options:

Disabled Enabled

On-board LAN: Enabled

Options:

Disabled Enabled

PXE OPROM: Disabled

Options:

Disabled Enabled

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > ICH Control Sub-Menu > Integrated Device Control Sub-Menu > PCI Express Control Sub-Menu

PCI Express - Root Port 1: Enabled

Options:

Disabled Enabled Auto

PCI Express - Root Port 2: Auto

Options:

Disabled Enabled Auto

Root Port ASPM Support: Auto

Options:

Disabled Auto

ASPM Latency Checking: Auto

Options:

Disabled Auto

> PCI/PNP ISA IRQ Resource Exclusion

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > ICH Control Sub-Menu > Integrated Device Control Sub-Menu > PCI Express Control Sub-Menu

PCI/PNP ISA IRQResource Exclusion

IRQ 3: Available

Options:

Available Reserved

IRQ 4: Available

Options:

Available Reserved

IRQ 5: Available

Options:

Available Reserved

IRQ 7: Available

Options:

Available Reserved

IRQ 9: Available

Options:

Available Reserved

IRQ 10: Available

Options:

Available Reserved

IRQ 11: Available

Options:

Available Reserved

IRQ 15: Available

Options:

Available Reserved

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > ICH Control Sub-Menu > Integrated Device Control Sub-Menu > ICH USB Control Sub-Menu

USB Dev #29 Fun #0,1,2,7

Options:

Disabled Fun #0 Fun #0,1 Fun #0,1,2 Fun #0,1,2,7

USB Dev #26 Fun #0,1,7

Options:

Disabled Fun #0,7 Fun #0,1,7

Overcurrent Detection Enabled

Options:

Disabled Enabled

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > Super I/O Control Sub-Menu

Serial port 1: Enabled

Speed: Low

Base I/O address: 3F8

Interrupt: IRQ 4

Interface: RS232

Options:

Port x:

Disabled Enabled

Serial port 2: Enabled

Speed: Low

Speed:

Low High

Base I/O address:

3F8 2F8 3E8 2E8

Interrupt:

Disabled IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 9

Interface:

RS232 RS422 RTS RS422 Auto RS485 RTS RS485 RTS w/Echo RS485 Auto RS485 Auto w/Echo

Base I/O address: 2F8

Interrupt: IRQ 3

Interface: RS232

Options:

Port x:

Disabled Enabled

Serial port 3: Enabled

Speed: Low

Base I/O address: 3E8

Interrupt: IRQ 5

Interface: RS232

Options:

Port x:

Disabled Enabled

Speed:

Low High

Speed:

Low High

Base I/O address:

3F8 2F8 3E8 2E8

Base I/O address:

3F8 2F8 3E8 2E8

Interrupt:

Disabled IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 9

Interrupt:

Disabled IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7

Interface:

RS232 RS422 RTS RS422 Auto RS485 RTS RS485 RTS w/Echo RS485 Auto RS485 Auto w/Echo

Interface:

RS232 RS422 RTS RS422 Auto RS485 RTS RS485 RTS w/Echo RS485 Auto RS485 Auto w/Echo

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > Super I/O Control Sub-Menu (continued)

Serial port 4: Enabled

Speed: Low

Base I/O address: 2E8

Interrupt: IRQ 6

Interface: RS232

Options:

Port x:

Disabled Enabled

Parallel port: Enabled

Base I/O address: 378

Speed:

Low High

Base I/O address:

3F8 2F8 3E8 2E8

Interrupt:

Disabled IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7

Interface:

RS232 RS422 RTS RS422 Auto RS485 RTS RS485 RTS w/Echo RS485 Auto RS485 Auto w/Echo

Interrupt: IRQ 7

Options:

Port x:

Disabled Enabled

Digital I/O port: Enabled

DIO port address: 120

DIO IRQ: IRQ 10

Options:

Digital I/O port:

Disabled Enabled

DIO port address:

120 130 140

Base I/O address:

378 278

DIO IRQ:

Disabled IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 9 IRQ 10

Interrupt:

Disabled IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 9 IRQ 10

Watchdog: 0

Options:

{Enter any value between 0-255 for seconds.}

SIO Firmware: Rev 0003

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > ACPI Control Sub-Menu

Passive Cooling Trip Point: 55 C

Options:

Disabled 55 C 63 C 71 C 79 C 87 C 95 C 103 C 111 C 119 C

Passive Cooling Trip Point: 95 C

Options:

Disabled 55 C 63 C 71 C 79 C 87 C 95 C 103 C 111 C 119 C

Passive TC1 Value: 1

Passive TC2 Value: 5

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Passive TSP Value: 10

Options: 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Intel > ACPI Control Sub-Menu (continued)

Critical Trip Point: POR

Options:

POR 15 C 23 C 31 C 39 C 47 C 55 C 63 C 71 C 79 C 87 C 95 C 103 C 111 C 119 C 127 C

FACP - RTC S4 Flag Value: Enabled

Options:

Disabled Enabled

FACP - PM Timer Flag Value: Enabled

Options:

Disabled Enabled

HPET Support: Disabled

Options:

Disabled Enabled

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Security

Supervisor Password Is: Clear

User Password Is: Clear

Set Supervisor Password: Enter

Set User Password: Enter

Virus check reminder: Disabled

Options:

Disabled Daily Weekly Monthly

Password on boot: Disabled

Options:

Disabled Enabled

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Boot

Boot priority order:

1: 2: 3: 4: 5: 6: 7: 8:

Options:

Excluded from boot order:

Options:

All IDE HDD All USB Floppy All USB Key All USB HDD All USB CDROM All USB ZIP All USB LS120 All PCI SCSI All PCI BEV Legacy Network Card Bootable Add-in Cards

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Note: Defaults are indicated in bold for BIOS properties. Default options that cannot be user-modied are indicated with grey text.

Exit

Exit Saving Changes

Exit Saving Changes to CMOS and EEPROM

Exit Discarding Changes

Load Setup Defaults

Discard Changes

Save Changes

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BIOS SETTINGS STORAGE OPTIONS

CMOS Storage Locations

The EBC-C384’s BIOS conguration is stored in three (3) locations:

(1) CMOS RAM (nonvolatile if battery backed)

(2) EEPROM (nonvolatile storage for user defaults)

(3) FLASH PROM (nonvolatile storage for factory defaults)

Saving the CMOS Conguration

The Real-Time Clock and the CMOS RAM settings can be maintained by an optional battery when the board is powered

off. A battery is always required to maintain time and date functions when the board is powered off.

The EEPROM feature allows the user to save CMOS conguration settings to nonvolatile storage that does not require

a battery. This feature can be enabled/disabled using JP15 and JP16. When enabled, the user’s CMOS settings can

be saved to EEPROM from the BIOS utility’s Main Menu. If the board is powered off with no battery, the user’s CMOS

settings will be restored from EEPROM but time and date information will be lost and returned to default values.

JP15, JP16 - EEPROM Enable

JP15

□

JP16

□

EEPROM Enable JP15 JP16

CMOS EEPROM Enable (default) 1-2 1-2

CMOS EEPROM Disable Open Open

At system boot, the BIOS rst performs a checksum validation on the contents of the CMOS RAM. Invalid checksums

usually occur due to a low or disabled battery. If the checksum is valid, the system boots using values stored in CMOS

RAM. If a checksum error occurs, the BIOS attempts to load CMOS values from the EEPROM.

After a checksum validation, the BIOS conguration is loaded from the EEPROM and the boot process continues. If the

EEPROM is disabled or the contents of the EEPROM fail the checksum validation, the system loads the factory default

settings from the FLASH PROM and continues the boot sequence.

For applications where the battery is present, CMOS settings should be saved to both the CMOS RAM and to the

EEPROM so the system can continue to function without user interaction.

Resetting CMOS to EEPROM defaults

If a battery is present, you can reset the CMOS RAM to the values stored in EEPROM by turning the system off and

removing the external battery. Replace the battery and reboot. When power is applied to the board, the system will boot

with the CMOS settings that were stored in EEPROM.

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Resetting CMOS to EEPROM to Factory Defaults

The EBC-C384 can normally be returned to the factory default BIOS conguration by selecting option Load Setup

Defaults on the BIOS Exit menu.

If you have saved EEPROM values that prevent you from accessing BIOS menus, the board can be reset to factory

defaults as follows:

1) Turn the system off.

2) Remove the jumpers from JP15 and JP16.

3) Turn the system on and enter the BIOS Main Menu using the F2 key.

4) Select Load Defaults from the Exit menu.

5) Install the jumpers to JP15 and JP16.

6) Save the restored defaults to CMOS and EEPROM.

Updating the BIOS FLASH PROM

The most recent EBC-C384 BIOS is available on the WinSystems website. However, it is highly recommended that an

Applications Engineer be consulted prior to any BIOS FLASH PROM update. If the BIOS PROM is updated, the steps

described above must be followed to reset the CMOS and EEPROM to the newly loaded factory defaults and to clear the

data from the previous BIOS version.

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CABLES

Part Number Description

CBL-SET-384-2 Cable set for EBC-C384 includes:

ADP-IO-USB-001 Dual 8-pin, 2-mm. 4 USB ports

CBL-173-G-1-1.0 20-pin ribbon to two 9-pin male D connector adapter

CBL-234-G-1-1.375 14-pin ribbon to 15-pin D-sub CRT adapter

CBL-236-G-2-1.5 Power cable (unterminated)

CBL-247-G-1-1.0 1-ft., Multi-I/O adapter

CBL-343-G-1-1.375 PS/2 Mouse Adapter

CBL-AUDIO2-102-12 Audio 2x15, 1.25-mm. to Jack, 12-in. Stereo Audio, UL1429

CBL-RST-402-18 Reset, Harness for EPX (2-pin)

CBL-USB4-002-12 4x USB ports with two, 8-pin, 2-mm connectors

BAT-LTC-E-36-16-1 External 3.6V, 1650 mAH battery with plug-in connector

Additional Cables

CBL-129-4 4ft., ribbon cable, 50-pin. both ends with 50-pin socket termination

CBL-266-G-2-0.75 44-pin, IDE Socket Cable

CBL-343-G-1-1.375 PS/2 Mouse Adapter

CBL-AUDIO5-102-12 Audio 2x15, 1.25-mm. to Jack, 12-in. 5.1 Audio, UL1429

CBL-AUDIO7-100-14 Audio 2x15, 1.25-mm. Unterminated, 14-in.

CBL-AUDIO7-102-12 Audio 2x15, 1.25-mm. to Jack, 12-in. 7.1 Audio, UL1429

CBL-BKLT-000-14 Backlight 1x11 1-mm., Unterminated Pico-Clasp

CBL-LVDS24-000-14 LVDS 2x20, 1-mm. to Unterminated 14-in. CBL-PWR-600-14 Power ATX and Reset, .1 Molex, 14-in. Unterminated CBL-SATA-701-20 SATA, Latching, Mirror, Straight 20-in. long CBL-USB4-000-14 USB 2x10, 1-mm. Unterminated 14-in. CBL-USB4-001-12 USB 2 of 2x10-mm., Pico Clasp 12-in.

External Batteries

BAT-LTC-E-36-16-1 External 3.6V, 1650 mAH battery with plug-in connector

BAT-LTC-E-36-27-1 External 3.6V, 2700 mAH battery with plug-in connector

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See WinSystems website.

SOFTWARE DRIVERS

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Electrical

Power

SPECIFICATIONS

VCC +5V ±5% required, 2.9A typical

MODEL EBC-C384-D2-1

Typical 2.9A

Maximum 3.5A

Standby (S3) 300 mA

MTBF

Mechanical

Dimensions 5.75” x 8.00” (147 mm x 203 mm)

Weight 16 oz (453.59 g) (with heatsink)

Environmental

Operating Temperature -40°C to 75°C *

Random Vibration

Mechanical Shock

220, 692 hours (EBC-C384-D2-0) Bellcore TR-332, Issue 6 at 55 degress C

MIL-STD-202G, Method 214A, Condition D .1g/Hz (11.95g rms), 20 minutes per axis, 3 axis

MIL-STD-202G, Method 213B, Condition A 50g half-sine, 11 ms duration per axis, 3 axis

* - Thermal proles can vary greatly depending on the operating system and applications being used.

WinSystems uses the Intel TAT (Thermal Analysis Tool) for testing with Intel processors. This program

heavily loads the system and creates a worst case scenario for the single board computer. Specic real world

applications will rarely tax the system as heavily and may allow for extending the fanless operational range.

WinSystems conducts temperature verication with PassMark BurnInTest to provide a more realistic real world

example. The PassMark BurnInTest is performed with all internal tests operating at 50% duty cycle.

Thermal Qualication Testing

Air Flow

SBC Test Application

EBC-C384-S2-0 PassMark BurnInTest 150 -40 85 1.66 No

EBC-C384-S2-0 Intel TAT 150 -40 85 1.66 No

EBC-C384-S2-0 PassMark BurnInTest 0 -40 85 1.66 No

EBC-C384-S2-0 Intel TAT 0 -40 70 1.66 No

EBC-C384-D2-0 PassMark BurnInTest Onboard Fan -40 75 1.80 No

EBC-C384-D2-0 Intel TAT Onboard Fan -40 75 1.80 No

(linear

ft/min)

Low

Temp

(Celsius)

High

Temp

(Celsius)

CPU Freq.

(GHz)

CPU

Throttling

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MECHANICAL DRAWING - TOP VIEW

0 .205 [5.20]* .362 [9.20]*

1.150 [29.20]

[8.30]

.423 [10.74]

.498

.327

[12.65]

.750 [19.05]

.200 [5.08]

.308 [7.83]

.875 [22.23]

1.724 [43.79]

1.900 [48.26]

2.000 [50.80]

3.050 [77.47]

3.806 [96.67]

4.150 [105.41]

4.660 [118.36]

5.350 [135.89]

5.550 [140.97]

1.841 [46.77]

2.650 [67.31]

5.800 [147.32]

6.375 [161.93]

6.750 [171.45]

7.125 [180.98]

7.600 [193.04]

.305 [7.75]

1.391 [35.33]

2.350 [59.69]

2.800 [71.12]

3.381 [85.88]

4.407 [111.94]

[133.35]5.250

6.192 [157.27]

6.950 [176.53]

7.600 [193.04]

7.800 [198.12]

.134 [3.41]

1.875 [47.63]

5.056 [128.41]

5.700 [144.78]

(8 PLCS)

.125 THRU

.250 MOUNTING AREA

140703

.115 [2.92]

3.028 [76.92]

3.538 [89.87]

6.066 [154.07]

1.295 [32.88]

4.624 [117.44]

4.789 [121.64]

.436 [11.07]

3.685 [93.61]

5.652 [143.55]

MECHANICAL DRAWING - BOTTOM VIEW

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APPENDIX - A

BEST PRACTICES

POWER SUPPLY

The power supply and how it is connected to the Single Board Computer (SBC) is very important.

Avoid Electrostatic Discharge (ESD)

Only handle the SBC and other bare electronics when electrostatic discharge (ESD) protection is in place. Having a wrist strap and a fully grounded workstation is the minimum ESD protection required before the ESD seal on the product bag is broken.

Power Supply Budget

Evaluate your power supply budget. It is usually good practice to budget 2X the typical power requirement for all of your devices.

Zero-Load Power Supply

Use a zero-load power supply whenever possible. A zero-load power supply does not require a minimum power load to regulate. If a zero-load power supply is not appropriate for your application, then verify that the single board computer’s typical load is not lower than the power supply’s minimum load. If the single board computer does not draw enough power to meet the power supply’s minimum load, then the power supply will not regulate properly and can cause damage to the SBC.

Use Proper Power Connections (Voltage)

When verifying the voltage, you should always measure it at the power connector on the SBC. Measuring at the power supply does not account for voltage drop through the wire and connectors.

The single board computer requires +5V (±5%) to operate. Verify the power connections. Incorrect voltages can cause catastrophic damage.

Populate all of the +5V and ground connections. Most single board computers will have multiple power and ground pins, and all of them should be populated. The more copper connecting the power supply to the single board computer the better.

Adjusting Voltage

If you have a power supply that will allow you to adjust the voltage, it is a good idea to set the voltage at the power connector of the SBC to 5.1V. The SBC can tolerate up to 5.25V, so setting your power supply to provide 5.1V is safe and allows for a small amount of voltage drop that will occur over time as the power supply ages and the connector contacts oxidize.

Power Harness

Minimize the length of the power harness. This will reduce the amount of voltage drop between the power supply and the single board computer.

Gauge Wire

Use the largest gauge wire that you can. Most connector manufacturers have a maximum gauge wire they recommend for their pins. Try going one size larger; it usually works and the extra copper will help your system perform properly over time.

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Contact Points

WinSystems’ boards mostly use connectors with gold nish contacts. Gold nish contacts are used exclusively on high speed connections. Power and lower speed peripheral connectors may use a tin nish as an alternative

contact surface. It is critical that the contact material in the mating connectors is matched properly (gold to gold and tin to tin). Contact areas made with dissimilar metals can cause oxidation/corrosion resulting in unreliable connections.

Pin Contacts

Often the pin contacts used in cabling are not given enough attention. The ideal choice for a pin contact would include a design similar to Molex’s or Trifurcons’ design, which provides three distinct points to maximize the contact area and improve connection integrity in high shock and vibration applications.

POWER DOWN

Make sure the system is completely off/powered down before connecting anything.

Power Supply OFF

The power supply should always be off before it is connected to the single board computer.

I/O Connections OFF

I/O Connections should also be off before connecting them to the single board computer or any I/O cards. Connecting hot signals can cause damage whether the single board computer is powered or not.

MOUNTING AND PROTECTING THE SINGLE BOARD COMPUTER

Do Not Bend or Flex the SBC

Never bend or ex the single board computer. Bending or exing can cause

irreparable damage. Single board computers are especially sensitive to

exing or bending around Ball-Grid-Array (BGA) devices. BGA devices are extremely rigid by design and exing or bending the single board computer

can cause the BGA to tear away from the printed circuit board.

Mounting Holes

The mounting holes are plated on the top, bottom and through the barrel of the hole and are connected to the single board computer’s ground plane. Traces are often routed in the inner layers right below, above or around the mounting holes.

Never use a drill or any other tool in an attempt to make the holes larger.

Never use screws with oversized heads. The head could come in contact with nearby components causing a short or physical damage.

Never use self-tapping screws; they will compromise the walls of the mounting hole.

Never use oversized screws that cut into the walls of the mounting holes.

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Always use all of the mounting holes. By using all of the mounting holes you will provide the support the single board computer needs to prevent bending or

exing.

MOUNTING AND PROTECTING THE SINGLE BOARD COMPUTER (continued)

Plug or Unplug Connectors Only on Fully Mounted Boards

Never plug or unplug connectors on a board that is not fully mounted. Many

of the connectors t rather tightly and the force needed to plug or unplug them could cause the single board computer to be exed.

Avoid cutting of the SBC

Never use star washers or any fastening hardware that will cut into the single board computer.

Avoid Overtightening of Mounting Hardware

Causing the area around the mounting holes to compress could damage interlayer traces around the mouting holes.

Use Appropriate Tools

Always use tools that are appropriate for working with small hardware. Large tools can damage components around the mounting holes.

Placing the SBC on Mounting Standoffs

Be careful when placing the single board computer on the mounting standoffs. Sliding the board around until the standoffs are visible from the top can cause component damage on the bottom of the single board computer.

Avoid Conductive Surfaces

Never allow the single board computer to be placed on a conductive surface. Almost all single board computers use a battery to backup the clock-calendar and CMOS memory. A conductive surface such as a metal bench can short the battery causing premature failure.

ADDING PC/104 BOARDS TO YOUR STACK

Be careful when adding PC/104 boards to your stack.

Never allow the power to be turned on when a PC/104 board has been improperly plugged onto the stack. It is possible to misalign the PC/104 card and leave a row of pins on the end or down the long side hanging out of the connector. If power is applied with these pins misaligned, it will cause the I/O board to be damaged beyond repair.

CONFORMAL COATING

Applying conformal coating to a WinSystems product will not in itself void the product warranty, if it is properly removed prior to return. Coating may change thermal characteristics and impedes our ability to test, diagnose, and repair products. Any coated product sent to WinSystems for repair will be returned at customer expense and no service will be performed.

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OPERATIONS / PRODUCT MANUALS

Every single board computer has an Operations manual or Product manual.

Manual Updates

Operations/Product manuals are updated often. Periodicially check the WinSystems website (http://www.winsystems.com) for revisions.

Check Pinouts

Always check the pinout and connector locations in the manual before plugging in a cable. Many single board computers will have identical headers for different functions and plugging a cable into the wrong header can have disastrous results.

Contact an Applications Engineer with questions

If a diagram or chart in a manual does not seem to match your board, or if you have additional questions, contact your Applications Engineer.

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APPENDIX - B

POST CODES

If the system hangs before the BIOS can process the error, the value displayed at the I/O port I/O address 80h is the last

test that performed. In this case, the screen does not display an error code.

The following is a list of the checkpoint codes written at the start of each test and their corresponding audio beep codes

issued for terminal errors.

Code Beeps Location Description

01h IPMI initialization

02h Verify real mode

03h Disable non-maskable interrupt (NMI)

04h Get CPU type

06h Hardware initialization

07h Chipset BIOS deshadow

08h Chipset initialization

09h Set IN POST ag

0Ah CPU initialization

0Bh CPU cache on

0Ch Cache initialization

0Eh I/O initialization

0Fh FDISK initialization

10h Power management initialization

11h Register initialization

12h Restore CR0

13h PCI bus master reset

14h 8742 initialization (keyboard/embedded controller)

16h 1-2-2-3 Checksum BIOS ROM

17h Pre-size RAM (initialize cache before memory auto size)

18h Timer initialization (8254 CTC)

1Ah DMA initialization (8237 DMAC)

1Ch Reset PIC (8259 PIC)

20h 1-3-1-1 Test DRAM refresh

22h 1-3-1-3 Test 8742 Keyboard Controller

24h Set huge ES (segment register to 4 GB)

26h Enable A20

28h Auto size DRAM

29h POST memory manager (PMM) initialization

2Ah Zero base (clear 512 KB base RAM)

2Bh Enhanced CMOS initialization

2Ch 1-3-4-1

2Eh 1-3-4-3

2Fh Pre-sys shadow (Enable cache before system BIOS shadow)

30h Base RAM High (RAM failure on data bits xxxx* of high byte)

32h Compute speed (test CPU bus-clock frequency)

33h Post Dispatch Manager (PDM) initialization

34h CMOS test

35h Register re-initialization

36h Check shutdown (perform warm restart)

Address test (RAM failure on address line xxxx*)

Base RAM Low (RAM failure on data bits xxxx* of low

byte)

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Code Beeps Location Description

37h Chipset re-initialization

38h System shadow (shadow BIOS ROM)

39h Cache re-initialization

3Ah Cache auto-size

3Bh Debug server initialization

3Ch Advanced chipset initialization

3Dh Advanced register conguration

3Eh Read hardware

3Fh RomPilot memory initialization

40h Speed

41h RomPilot initialization

42h Interrupt vectors initialization

44h Set BIOS interrupt

45h Device initialization

46h 2-1-2-3 Check ROM copyright

48h Cong (Check video conguration against CMOS)

49h PCI initialization

4Ah Video initialization (Initialize all video adapters)

4Bh QuietBoot start

4Ch Video shadow (Shadow video BIOS)

4Eh Copyright display

4Fh MultiBoot-XP initialization

50h CPU type display

51h EISA initialization

52h Keyboard test

54h Set key click (if enabled)

55h USB initialization

56h Enabled keyboard

57h 1394 Firewire initialization

58h 2-2-3-1

59h POST display service (PDS) initialization

5Ah Display prompt Press F2 to enter SETUP

5Bh CPU cache off

5Ch Test RAM between 512 KB to 640 KB

60h Test extended memory

62h Test extended memory address

64h Jumper to UserPatch1

66h Congure advanced cache registers

67h Initialize Multi Processor APIC

68h Cache conguration (enable internal and external caches)

69h PM setup System Management Mode (SMM)

6Ah Display external L2 cache size

6Bh Load custom defaults (optional)

6Ch Display shadow-area messages

70h Display error messages

72h Check for conguration errors

HOT (Test for unexpected interrupts)

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Code Beeps Location Description

74h RTC test

76h Keyboard test

7Ah Key lock

7Ch Hardware interrupts

7Dh Intelligent System Monitoring (ISM) initialization

7Eh Coprocessor initialization (if present)

80h I/O initialization (before)

81h Late device initialization

82h RS-232 initialization

83h FDISK cong IDE

84h LPT initialization

85h PCI PCC initialization (PC-compatible PnP ISA devices)

86h I/O initialization (after)

87h Motherboard Congurable Devices (MCD) initialization

88h BIOS data-area initialization (BDA)

89h Enable Non-Maskable Interrupt (NMI)

8Ah Extended BIOS Extended Data Area (EBDA)

8Bh Mouse initialization

8Ch Floppy initialization

8Fh FDISK fast pre-initialization

90h FDISK initialization

91h FDISK fast initialization

92h Jump to UserPatch2

93h Build MPTABLE for multi-processor boards

95h CDROM initialization

96h Clear huge ES

97h MultiProcessor table x-up

98h 1-2 Option ROM scan

99h FDISK check SMART

9Ah Miscellaneous shadow (shadow option ROMs)

9Bh PM CPU speed

9Ch Power Management (PM) setup

9Dh Intialize security engine

9Eh IRQS

9Fh FDISK fast initialization #2

A0h Time of day - set

A2h Keylock test

A4h Key rate initialization (typematic rate)

A8h Erase F2 prompt

AAh Scan for F2 keystroke

ACh Setup check

AEh Clear bootag

B0h Error check

B1h RomPilot unload

B2h POST done - prepare to boot operating system

B4h 1 One beep (before boot)

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Code Beeps Location Description

B5h Terminate QuietBoot

B6h Check password

B7h ACPI initialization

B8h System initialization

B9h Prepare to boot

BAh DMI - SMBIOS initialization

BBh BCV (Boot Connection Vectors) initialization

BCh Parity - clear parity checkers

BDh MultiBoot-XP boot menu display

BEh Clear screen

BFh Check reminders (virus and backup)

C0h INT19 - boot

C1h POST Error Manager (PEM) - Initialization

C2h POST Error Manager (PEM) - Logging initialization

C3h POST Error Manager (PEM) - Initialize error display function

C4h POST Error Manager (PEM) - Initialize system error handler

C5h PNP’ed dual CMOS

C6h Initialize note dock

C7h Initialize note dock late

C8h Force check

C9h Extended checksum

Embedded Extensions

Code Description

CAh TP_SERIAL_KEY - Redirect INT15h to serial keyboard

CBh

CCh TP_SERIAL_VID - Redirect INT10h to enable remote serial video

CDh TP_PCMATA - Re-map I/O and memory for PCMCIA

CEh TP_PEN_INIT - Initialize digitizer and display message

CFh TP_XBDA_FAIL - Extended BIOS Data Area (XBDA) failure

WARRANTY INFORMATION

(http://www.winsystems.com/warranty.cfm)

WinSystems warrants to Customer that for a period of two (2) years from the date of shipment any Products and Software

purchased or licensed hereunder which have been developed or manufactured by WinSystems shall be free of any

material defects and shall perform substantially in accordance with WinSystems’ specications therefore. With respect

to any Products or Software purchased or licensed hereunder which have been developed or manufactured by others,

WinSystems shall transfer and assign to Customer any warranty of such manufacturer or developer held by WinSystems,

provided that the warranty, if any, may be assigned. Notwithstanding anything herein to the contrary, this warranty granted

by WinSystems to the Customer shall be for the sole benet of the Customer, and may not be assigned, transferred or

conveyed to any third party. The sole obligation of WinSystems for any breach of warranty contained herein shall be, at its

option, either (i) to repair or replace at its expense any materially defective Products or Software, or (ii) to take back such

Products and Software and refund the Customer the purchase price and any license fees paid for the same. Customer

shall pay all freight, duty, broker’s fees, insurance charges for the return of any Products or Software to WinSystems

under this warranty. WinSystems shall pay freight and insurance charges for any repaired or replaced Products or

Software thereafter delivered to Customer within the United States. All fees and costs for shipment outside of the United

States shall be paid by Customer. The foregoing warranty shall not apply to any Products of Software which have been

subject to abuse, misuse, vandalism, accidents, alteration, neglect, unauthorized repair or improper installations.

THERE ARE NO WARRANTIES BY WINSYSTEMS EXCEPT AS STATED HEREIN, THERE ARE NO OTHER

WARRANTIES EXPRESS OR IMPLIED INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, IN NO EVENT SHALL WINSYSTEMS BE LIABLE

FOR CONSEQUENTIAL, INCIDENTIAL OR SPECIAL DAMAGES INCLUDING, BUT NOT LIMITED TO, DAMAGES

FOR LOSS OF DATA, PROFITS OR GOODWILL. WINSYSTEMS’ MAXIMUM LIABILITY FOR ANY BREACH OF

THIS AGREEMENT OR OTHER CLAIM RELATED TO ANY PRODUCTS, SOFTWARE, OR THE SUBJECT MATTER

HEREOF, SHALL NOT EXCEED THE PURCHASE PRICE OR LICENSE FEE PAID BY CUSTOMER TO WINSYSTEMS

FOR THE PRODUCTS OR SOFTWARE OR PORTION THEREOF TO WHICH SUCH BREACH OR CLAIM PERTAINS.

WARRANTY SERVICE

1. To obtain service under this warranty, obtain a return authorization number. In the United States, contact the

WinSystems’ Service Center for a return authorization number. Outside the United States, contact your local sales agent

for a return authorization number.

2. You must send the product postage prepaid and insured. You must enclose the products in an anti-static bag

to protect from damage by static electricity. WinSystems is not responsible for damage to the product due to static

electricity.

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WinSystems EBC-C384-D User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

TABLE OF CONTENTS

BEFORE YOU BEGIN

Visual Index - Top View (Connectors)

Visual Index - Bottom View

Jumper Reference

INTRODUCTION

FEATURES

System

Memory

FUNCTIONALITY

I/O Port Map

Interrupt Map

PCI Devices and Functions

Watchdog Timer

Real-Time Clock/Calendar

STATUS LED

D6 - Status LED

CONNECTOR REFERENCE

POWER

J6 - Power and Reset

J26 - Fan Power

J2 - Push Button Reset

J3 - ATX Signals

BATTERY BACKUP

J14 - External Battery

VIDEO

J19 - ANALOG VGA

J20 - LVDS

J24 - Backlight Power

JP13 - Panel Power

AUDIO

J16 - HD Audio

SP1 - Speaker

MULTI-I/O

J7 - Multi-I/O (COM1, COM2, Keyboard, LPT)

MOUSE

J1 - Mouse

SERIAL

J10 - COM3, COM4

J4, J5 - USB

SERIAL ATA

J23, J25 - SATA

COMPACTFLASH

J28 - CompactFlash

PARALLEL ATA

J11 - PATA

ETHERNET

J13, J8 - Gigabit Ethernet

DIGITAL I/O

J9, J12 - Digital I/O

JP5/JP8 - Digital I/O Power

Register Details

PC/104 BUS

J15, J17 - PC/104

PC/104-Plus BUS

J18 - PC/104-Plus

MiniPCI

J27 - MiniPCI Socket

MiniPCI Device Interface (CN1)

BIOS SUPPLEMENTAL

BIOS SETTINGS STORAGE OPTIONS

CABLES

SOFTWARE DRIVERS

SPECIFICATIONS

MECHANICAL DRAWING - TOP VIEW

MECHANICAL DRAWING - BOTTOM VIEW

APPENDIX - A

BEST PRACTICES

APPENDIX - B

POST CODES

WARRANTY INFORMATION