Winstron ME3 Schematics
5
4
3
2
1
ME3 Block Diagram
Intel CPU
Meron 2M/4M SV
FSB:667 or 800 MHz
CLK GEN
D D
G792
22
REALTEK RTM875
3
4,5,6
Host BUS
Project code : 91.4X601.001
PCB P/N :
Revision :
533/667MHz
DDRII
Slot 0
DDRII
Slot 1
DDRII 667 Channel A
13,14
DDRII 667 Channel B
13,14
Crestline-GM/GML
AGTL+ CPU I/F
INTEGRATED GRAHPICS
LVDS, CRT I/F
DDR I/F
7,8,9,10,11,12
DMI I/F
PCIE x 16
nVIDIA
NB8M-GS
44,45,46
TV OUT
CRT
LCD
HDMI
15
15
16
17
100MHz
Power Switch
C C
G577
Mini Card_2
Robson
RJ45
CONN
23
23
25
Mic In
Line In
B B
INT.SPKR
Line Out
(SPDIF)
New card
Mini Card_1
802.11a/b/g/n
10/100 Controller
Realtek
RTL8101E
AMP
G1432
AMP
G1412
35
35
Codec
ALC662
34
PCI-E x 1
23
PCI-E x 2
23
24
PCI-E x 1
AZALIA
INTEL
ICH8-M
10 USB 2.0/1.1 ports
(10/100/1000Mb)ETHERNET
High Definition Audio
ATA 66/100
ACPI 1.1
LPC I/F
PCI/PCI BRIDGE
Graphics RAM
256-Mbit
27MHz
32.768KHz
USB 2.0
GDDR3
47,48
Finger print
Camera
RF
USB X 4
Realtek
RTL5158
26
26
or
26
28
27
EEPROM
Blue tooth
MS/MS Pro/xD/
MMC/SD
4 in 1
46
26
27
SYSTEM DC/DC
TPS51120
INPUTS
DCBATOUT
OUTPUTS
5V_S3
3V_S5
SYSTEM DC/DC
MAX8743
INPUTS
DCBATOUT
OUTPUTS
1D05V_S0
1D8V_S3
SYSTEM DC/DC
FAN5234
INPUTS
DCBATOUT
OUTPUTS
VGA_CORE_S0
11A
MAXIM CHARGER
MAX8725
INPUTS
OUTPUTS
BT+
DCBATOUT
18V 3.0A
5V 100mA
CPU DC/DC
MAX8736ETL
INPUTS
OUTPUTS
VCC_CORE
DCBATOUT
0.844~1.3V
44A
PCB LAYER
Signal 1
L1:
GND
L2:
Signal 2
L3:
L4:
Signal 3
GND
L5:
L6:
VCC
Signal 4L7:
Signal 5
RJ11
MDC Card
AZALIA
MODEM
28
INT. MIC Array
Digital
A A
HDMI
(SPDIF)
E-SATA
CONN
28
5
Codec
ALC268
E-SATA
SIL3531
29
SATA
HDD
4
30
18,19,20,21
CDROM
PATASATA
30
CAPACITY
BUTTON
33
Winbond
WPC8763
Touch
Pad
33 33
3
KBC
INT.
KB
LPC BUS
SPI
31
32.768KHz
Flash Rom
W25X80-VSS
32
TPM
SLB9635TT
32.768KHz
2
32
LPC
DEBUG
CONN.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
32
Block Diagram
Block Diagram
Block Diagram
A3
A3
A3
L8:
GND
L9:
Signal 5
L10:
Prepare by Steven CF Chou
Prepare by Steven CF Chou
Prepare by Steven CF Chou
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete SA
ME3-Discrete SA
ME3-Discrete SA
151Monday, July 30, 2007
151Monday, July 30, 2007
151Monday, July 30, 2007
of
of
1
of
A
B
C
D
E
INTEL ICH8-M STRAP PIN
Signal Usage/When Sampled
HDA_SDOUT XOR Chain Entrance/
4 4
HDA_SYNC
GNT2#
GPIO20
GNT3#
GNT0#
SPI_CS1#
INTVRMEN
3 3
LAN100_SLP
SATALED#
SPKR
TP3
GPIO33/
HDA_DOCK_EN#
PCIE Port Config 1 bit1,
Rising Edge of PWROK
PCIE Port Config 1 bit0,
Rising Edge of PWROK.
PCIE Port Config 2 bit0,
Rising Edge of PWROK.
Reserved
Top-Block Swap Override.
Rising Edge of PWROK.
Boot BIOS Destination
Selection.
Rising Edge of PWROK.
Integrated VccSus1_05
VccSus1_5 and VccCL1_5
VRM Enable/Disable.Always
sampled.
Integrated VccLAN1_05
VccCL1_05 VRM enable
/Disable. Always sampled.
PCIE LAN REVERSAL.Rising
Edge of PWROK.
No Reboot.
Rising Edge of PWROK.
XOR Chain Entrance.
Rising Edge of PWROK.
Flash Descriptor Security
Override Strap
Rising Edge of PWROK.
2 2
INTEL CRESTLINE STRAP PIN
CFG Strap HIGH 1LOW 0
CFG 5
CFG 8
Low Power PCI Express Normal Low Power mode
CFG 9
PCI Express Graphics
Lane Reversal
CFG 16
FSB Dynamic ODT Disabled Enabled
CFG 19
DMI Lane Reserved Normal Operation Reserved Lane
CFG 20
Concurrent SDVO/PCIE
SDVO_CTRL_DATA
SDVO Present
1 1
CFG 12
CFG 13
LL(00)
LH(01)
HL(10)
HH(11)
U45 : 71.0NB8M.00U (VGA)
U35: 71.00662.00G (Audio)
U28: 71.08763.B0G (KBC)
D
U74: 71.08101.B0G (LAN)
U26: 71.ICH8M.C0U (SB)
U18: 71.PM965.A0U (NB)
TV1: 22.10021.H21
Hole,Spring
HDMI1: 22.10296.011
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
Table of Content
Table of Content
Table of Content
ME3-Discrete
ME3-Discrete
ME3-Discrete
E
251Friday, September 14, 2007
251Friday, September 14, 2007
251Friday, September 14, 2007
of
of
of
Allows entrance to XOR Chain testing when TP3
Comment
pulled low at rising edge of PWROK.When TP3 not
pulled low at rising edge of PWROK,sets bit1 of
RPC.PC(Config Registers:offset 224h)
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Sets bit2 of RPC.PC(Config Registers:Offset 224h)
Weak Internal PULL-DOWN.NOTE:This signal should
not be pull HIGH.
Sampled low:Top-Block Swap mode(inverts A16 for all
cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
Enables integrated VccSus1_05,VccSus1_5 and
VccCL1_5 VRM when sampled high
Enables integrated VccLAN1_05,VccCL1_05 VRM
when sampled high
This signal has weak internal pull-up.
set bit27 of MPC.LR(Device28:Function0:Offset D8)
If sampled high, the system is strapped to the
"No Reboot" mode(ICH8M will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
This signal should not be pull low unless using
XOR Chain testing.
Internal Pull-Up.If sampled low,the Flash Descriptor
Security will be overidden.if high,the Security
measures defined in the Flash Descriptor will be in
effect.
This should only be used in manufacturing
environments
DMI X 2 DMI X 4
★
Lane Reversal Normal Mode(Lanes
Only PCIE or SDVO
is operation
NO SDVO Card
Present
XOR/ALL-Z
Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation
★
★
A
★
number in order)
★
★
PCIE and SDVO are
operation simultaneous
SDVO Card Present
★
B
XOR Chain Entrance Strap
ICH_RSVD
A16 swap override strap
PCI_GNT#3
BOOT BIOS Strap
PCI_GNT#0 BOOT BIOS Location
integrated VccSus1_05,VccSus1_5,VccCL1_5
SM_INTVRMEN
integrated VccLan1_05VccCL1_05
LAN100_SLP
AZ_DOUT_ICH
tp3
0
0
10
low = A16 swap override enable
high = default
SPI_CS#1
10
1
1
Description
0
1
Normal Operation(default)
Set PCIE port cofig bit1
11
SPI10
PCI
LPC(Default)
High=Enable Low=Disable
High=Enable Low=Disable
RSVD
Enter XOR Chain
DEFAULE HIGH
No Reboot Strap
LOW = DefauleSPKR
High=No Reboot
INTEL ICH8-M INTEGRATED
8.2K PULL HIGH
MB: 07230
LED: 07537
FP: 07546
Audio: 07545
USB: 07547
PULL-UPS and PULL-DOWNS
HDA_BIT_CLK
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GNT[3:0]
GPIO[20]
LDA[3:0]#/FHW[3:0]#
LAN_RXD[2:0]
LDRQ[0]
LDRQ[1]/GPIO23
PME#
PWRBTN#
SATALED#
SPI_CS1#
SPI_CLK
SPI_MOSI
SPI_MISO
TACH_[3:0]
SPKR
TP[3]
USB[9:0][P,N]
CL_RST#
C
SIGNAL Resistor Type/Value
PULL-DOWN 20K
NONE
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 15K
TBD
A
3D3V_S0 3D3V_S0_CK505
L15
L15
1 2
MLB-160808-18-GP
MLB-160808-18-GP
12
C343
C343
SC1U10V3KX-3GP
SC1U10V3KX-3GP
5
DY
DY
DY
12
12
C330
C330
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C603
C603
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
12
12
C596
C596
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C598
C598
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C618
C618
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C597
C597
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
D D
3D3V_S0
R354
R354
1D25V_S0
MLB-160808-18-GP
MLB-160808-18-GP
12
C300
C300
SC1U10V3KX-3GP
SC1U10V3KX-3GP
L18
L18
1 2
1 2
12
0R3-0-U-GP
0R3-0-U-GP
DY
DY
C341
C341
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DY
DY
12
C601
C601
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C610
C610
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C605
C605
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C611
C611
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C619
C619
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D25V_S0_CK505_IO
C C
CLKSATAREQ#20
CLKREQ#_B7
PCLK_FWH32
CLK_PCI_TCG32
PCLK_KBC31
CLK_PCI_ICH18
CLK_14M_ICH20
3D3V_S0_CK505
12
B B
3D3V_S0_CK505
DY
DY
12
R336
R336
10KR2J-3-GP
10KR2J-3-GP
ITP_EN
12
R337
R337
10KR2J-3-GP
10KR2J-3-GP
12
R347
R347
10KR2J-3-GP
10KR2J-3-GP
PCI2_TME
12
R341
R341
10KR2J-3-GP
10KR2J-3-GP
DY
DY
SB
ITP_EN Output
0 SRC8
1 CPU_ITP
Design Note:
1. All of Input pin didn't have internal pull up resistor.
2. Clock Request (CR) function are enable by registers.
3. CY28548 integrated serial resistor of differential clock,
so put 0 ohm serial resistor in the schematic.
5
4
12
C599
C599
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
X2
X2
1 2
X-14D31818M-36GP
X-14D31818M-36GP
12
C321
C321
SC33P50V2JN-3GP
SC33P50V2JN-3GP
C607 SC4D7P50V2CN-1GPC607 SC4D7P50V2CN-1GP
12
C337
C337
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C303SC4D7P50V2CN-1GP C303SC4D7P50V2CN-1GP
C302SC4D7P50V2CN-1GP C302SC4D7P50V2CN-1GP
C301SC4D7P50V2CN-1GP C301SC4D7P50V2CN-1GP
1 2
CLK_48M_ICH20
H_STP_PCI#20
H_STP_CPU#20
ICH_SMBCLK13,14,20
ICH_SMBDATA13,14,20
CK_PWRGD20
R149 33R2J-2-GPR149 33R2J-2-GP
R153 33R2J-2-GPR153 33R2J-2-GP
R154 33R2J-2-GPR154 33R2J-2-GP
R155 33R2J-2-GPR155 33R2J-2-GP
12
C606SC4D7P50V2CN-1GP C606SC4D7P50V2CN-1GP
1 2
R338 33R2J-2-GPR338 33R2J-2-GP
1 2
1 2
1 2
1 2
R340 33R2J-2-GPR340 33R2J-2-GP
1 2
CLK_XTAL_OUTCLK_XTAL_IN
CLK_XTAL_IN
CLK_XTAL_OUT
FSA
3
12
C322
C322
SC33P50V2JN-3GP
SC33P50V2JN-3GP
3
2
17
45
44
7
6
63
8
10
PCI2_TME
11
12
27_SEL
13
ITP_EN
14
FSB
64
FSC
5
55
RTM875-606-LF-GP
RTM875-606-LF-GP
FS_C FS_B FS_A CPU
1 0 1 100M
0 0 1 133M
0 1 0 200M
0 1 1 166M
U24
U24
XIN
XOUT
FSLA/USB48
PCI_STOP#/SRC-5
CPU_STOP#/SRC-5#
SCLK
SDATA
CK_PWRGD/PD#
CR#_A/PCI-0
CR#_B/PCI-1
TME/PCI-2
SRC-5_EN/PCI-3
27M_SEL/PCI-4
ITP_EN/PCIF-5
FSLB/TEST_MODE
FSLC/TEST_SEL/REF
RESET#
3D3V_S0_CK505
23
4
9
16
46
62
VDD_48
VDD_PCI
VDD_REF
VDD_SRC
VDD_CPU
GND_REF
GND_PCI
GND_48
1
15
18
22
1D25V_S0_CK505_IO
19
27
VDD_IO
VDD_PLL3
GND_IO
GND_SRC
GND_SRC
GND_SRC
GND_CPU
26
30
36
49
59
33
43
52
56
VDD_SRC_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_CPU_IO
VDD_PLL3_IO
GND_PLL3
GND
65
SRC-8/CPU_ITP
SRC-8#/CPU_ITP#
SRC-7/CR#_F
SRC-7#/CR#_E
CR#_H/SRC-11
CR#_G/SRC-11#
CR#_C/SRC-3
CR#_D/SRC-3#
SRC-2/SATA
SRC-2#/SATA#
SRC-1#/SE2
SRC-0/DOT96
SRC-0#/DOT96#
3D3V_S0_CK505
12
R145
R145
10KR2J-3-GP
10KR2J-3-GP
12
R146
R146
10KR2J-3-GP
10KR2J-3-GP
DY
DY
2
CPU-0
CPU-0#
CPU-1
CPU-1#
SRC-6
SRC-6#
SRC-10
SRC-10#
SRC-9
SRC-9#
SRC-4
SRC-4#
SRC-1/SE1
27_SEL
61
60
58
57
54
53
51
50
48
47
41
42
40
39
37
38
34
35
31
32
28
29
24
25
20
21
CPU_BCLK
CPU_BCLK#
MCH_BCLK
MCH_BCLK#
CPU_XDP
CPU_XDP#
PCIE_LAN
PCIE_LAN#
PCIE_MINI1
PCIE_MINI1#
PCIE_NEW
PCIE_NEW#
PCIE_MINI2
PCIE_MINI2#
MCH_3GPLL
MCH_3GPLL#
PCIE_ICH
PCIE_ICH#
PCIE_SATA
PCIE_SATA#
27MHZ
27MHZSS
REFCLKP
REFCLKN
RN40
RN40
RN29
RN29
RN32
RN32
RN36
RN36
RN39
RN39
RN41
RN41
RN45
RN45
RN43
RN43
1
4
2 3
1
4
2 3
1
4
2 3
1
4
2 3
1
4
2 3
2 3
1
4
R367 10KR2J-3-GPR367 10KR2J-3-GP
RN44
RN44
R169
2 3
1
4
2 3
1
4
2 3
1
4
RN37
RN37
2 3
1
4
RN33
RN33
2 3
1
4
2 3
1
4
RN31
RN31
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
1 2
DYR169
DY
1 2
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN0J-6-GP
SRN33J-5-GP-U
SRN33J-5-GP-U
SRN0J-6-GP
SRN0J-6-GP
10KR2J-3-GP
10KR2J-3-GP
1
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7
CLK_PCIE_ESATA 29
CLK_PCIE_ESATA# 29
CLK_PCIE_LAN 24
CLK_PCIE_LAN# 24
CLK_PCIE_MINI1 23
CLK_PCIE_MINI1# 23
CLK_PCIE_NEW 23
CLK_PCIE_NEW# 23
3D3V_S0
NEWCARD_CLKREQ# 23
CLK_PCIE_MINI2 23
CLK_PCIE_MINI2# 23
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_ICH 20
CLK_PCIE_ICH# 20
CLK_PCIE_SATA 19
CLK_PCIE_SATA# 19
VGA_27MHZ 47
VGA_27MHZSS 47
PEG_REFCLKP 45
PEG_REFCLKN 45
27_SEL PIN 20 PIN 21 PIN 24 PIN 25
CPU_BSEL25
CPU_BSEL15
CPU_BSEL05
4
1 2
R339 10KR2J-3-GPR339 10KR2J-3-GP
1 2
R342 0R0402-PADR342 0R0402-PAD
1 2
R163 2K2R2J-2-GPR163 2K2R2J-2-GP
R334 1KR2J-1-GPR334 1KR2J-1-GP
1 2
R138 1KR2J-1-GPR138 1KR2J-1-GP
1 2
R335 1KR2J-1-GPR335 1KR2J-1-GP
1 2
3
FSC
FSB
FSA
MCH_CLKSEL0 7
MCH_CLKSEL1 7
MCH_CLKSEL2 7
0 DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100
1 SRCT0 SRCC0 27M_NSS 27M_SS
<Variant Name>
<Variant Name>
<Variant Name>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Clock generator CY28548
Clock generator CY28548
Clock generator CY28548
2
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
1
351Tuesday, August 21, 2007
351Tuesday, August 21, 2007
351Tuesday, August 21, 2007
A
of
of
of
5
C
A
4
3
2
1
H_A#[3..35]7
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
D D
H_ADSTB#07
H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47
C
H_ADSTB#17
H_A20M#19
H_FERR#19
H_IGNNE#19
H_STPCLK#19
H_INTR19
H_NMI19
H_SMI#
TP26TPAD28 TP26TPAD28
TP28TPAD28 TP28TPAD28
TP19TPAD28 TP19TPAD28
TP24TPAD28 TP24TPAD28
TP17TPAD28 TP17TPAD28
TP25TPAD28 TP25TPAD28
TP18TPAD28 TP18TPAD28
TP30TPAD28 TP30TPAD28
TP23TPAD28 TP23TPAD28
TP29TPAD28 TP29TPAD28
TP15TPAD28 TP15TPAD28
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
CPU_RSVD01
CPU_RSVD02
CPU_RSVD03
CPU_RSVD04
CPU_RSVD05
CPU_RSVD06
CPU_RSVD07
CPU_RSVD08
CPU_RSVD09
CPU_RSVD10
CPU_RSVD11
B B
1 OF 4
1 OF 4
U56A
U56A
J4
A3#
L5
A4#
L4
A5#
K5
A6#
M3
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L2
A13#
P4
A14#
P1
A15#
R1
A16#
M1
ADSTB0#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L1
REQ4#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U1
A23#
R4
A24#
T5
A25#
T3
A26#
W2
A27#
W5
A28#
Y4
A29#
U2
A30#
V4
A31#
W3
A32#
AA4
A33#
AB2
A34#
AA3
A35#
V1
ADSTB1#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD#M4
N5
RSVD#N5
T2
RSVD#T2
V3
RSVD#V3
B2
RSVD#B2
C3
RSVD#C3
D2
RSVD#D2
D22
RSVD#D22
D3
RSVD#D3
F6
RSVD#F6
B1
KEY_NC
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
XDP/ITP SIGNALS CONTROL
XDP/ITP SIGNALS CONTROL
THERMAL
THERMAL
PROCHOT#
ICH
ICH
THERMTRIP#
HCLK
HCLK
RESERVED
RESERVED
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
THRMDA
THRMDC
BCLK0
BCLK1
TDI
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
XDP_DBRESET#
C20
D21
A24
B25
H_THERMTRIP#
C7
CLK_CPU_BCLK
A22
CLK_CPU_BCLK#
A21
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_IERR#
H_INIT#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
H_THERMDA
H_THERMDC
original value:BGA479-SKT6-GPU1
H_ADS# 7
H_BNR# 7
H_BPRI# 7
H_DEFER# 7
H_DRDY# 7
H_DBSY# 7
H_BR0# 7
H_INIT# 19,32
H_LOCK# 7
H_RESET# 7
H_TRDY# 7
H_HIT# 7
H_HITM# 7
TP21 TPAD28TP21 TPAD28
TP16 TPAD28TP16 TPAD28
TP12 TPAD28TP12 TPAD28
TP22 TPAD28TP22 TPAD28
TP14 TPAD28TP14 TPAD28
XDP_DBRESET# 20
H_THERMTRIP# 7,19
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
layout note:Zo =55
ohm , 0.5" MAX for
GTLREF
H_RS#0 7
H_RS#1 7
H_RS#2 7
1 2
R132 68R3J-GPR132 68R3J-GP
1D05V_S0
12
R131
R131
56R2J-4-GP
56R2J-4-GP
CPU_PROCHOT# 38
1D05V_S0
H_THERMDA 22
H_THERMDC 22
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
layout note : Change R237 to 649 ohm if using XTP to ITP adapter
XDP_DBRESET#
XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
R129
R129
1 2
1KR2J-1-GP
1KR2J-1-GP
1 2
R114 54D9R2F-L1-GPR114 54D9R2F-L1-GP
1 2
R115 54D9R2F-L1-GPR115 54D9R2F-L1-GP
1 2
R116 54D9R2F-L1-GPR116 54D9R2F-L1-GP
1 2
R110 54D9R2F-L1-GPR110 54D9R2F-L1-GP
3D3V_S0
1D05V_S0
CPU_PROCHOT#
1D05V_S0
12
DY
DY
CBE
MMBT3904WT1G-GP
MMBT3904WT1G-GP
R135
R135
56R2J-4-GP
56R2J-4-GP
DY
DY
Q7
Q7
5
OCP# 20
XDP_TRST#
XDP_TCK
4
3
1 2
R111 51R2F-2-GPR111 51R2F-2-GP
1 2
R112 54D9R2F-L1-GPR112 54D9R2F-L1-GP
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
of
of
of
4
4
4
1
A
51Wednesday, August 15, 2007
51Wednesday, August 15, 2007
51Wednesday, August 15, 2007
5
A
4
3
2
1
H_D#[0..63]7
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
TP31TPAD28 TP31TPAD28
TP35TPAD28 TP35TPAD28
TP33TPAD28 TP33TPAD28
TP13TPAD28 TP13TPAD28
TP34TPAD28 TP34TPAD28
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
D D
H_DSTBN#07
H_DSTBP#07
H_DINV#07
C C
H_DSTBN#17
H_DSTBP#17
H_DINV#17
C586
C586
CPU_BSEL03
CPU_BSEL13
CPU_BSEL23
V_CPU_GTLREF
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
DY
DY
PLACE C173 close to the TEST4 PIN,
make sure TEST3,TEST4,TEST5 trace
routing is reference to GND and
away other noisy signals
B B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0
166
200
0
00
1
U56B
U56B
E22
D0#
F24
D1#
E26
D2#
G22
D3#
F23
D4#
G25
D5#
E25
D6#
E23
D7#
K24
D8#
G24
D9#
J24
D10#
J23
D11#
H22
D12#
F26
D13#
K22
D14#
H23
D15#
J26
DSTBN0#
H26
DSTBP0#
H25
DINV0#
N22
D16#
K25
D17#
P26
D18#
R23
D19#
L23
D20#
M24
D21#
L22
D22#
M23
D23#
P25
D24#
P23
D25#
P22
D26#
T24
D27#
R24
D28#
L25
D29#
T25
D30#
N25
D31#
L26
DSTBN1#
M26
DSTBP1#
N24
DINV1#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL0
B23
BSEL1
C21
BSEL2
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
11
2 OF 4
2 OF 4
DATA GRP0 DATA GRP1
DATA GRP0 DATA GRP1
DATA GRP2DATA GRP3
DATA GRP2DATA GRP3
MISC
MISC
DPRSTP#
PWRGOOD
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPSLP#
DPWR#
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP0
COMP1
R136 27D4R2F-L1-GPR136 27D4R2F-L1-GP
COMP2
R137 54D9R2F-L1-GPR137 54D9R2F-L1-GP
COMP3
R113 27D4R2F-L1-GPR113 27D4R2F-L1-GP
R109 54D9R2F-L1-GPR109 54D9R2F-L1-GP
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOODH_PWRGOODH_PWRGOODH_PWRGOOD
H_CPUSLP#
PSI#
H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7
1 2
1 2
1 2
1 2
H_DPRSTP# 7,19,38
H_DPSLP# 19
H_DPWR# 7
H_PWRGOOD 19
H_CPUSLP# 7
PSI# 38
Resistor Placed
within 0.5" of CPU
pin. Trace should
be at least 25 mils
away from any other
toggling signal .
COMP[0,2] trace
width is 18 mils.
COMP[1,3] trace
width is 4 mils .
VCC_CORE_S0 VCC_CORE_S0
U56C
U56C
A7
VCC
A9
VCC
A10
VCC
A12
VCC
A13
VCC
A15
VCC
A17
VCC
A18
VCC
A20
VCC
B7
VCC
B9
VCC
B10
VCC
B12
VCC
B14
VCC
B15
VCC
B17
VCC
B18
VCC
B20
VCC
C9
VCC
C10
VCC
C12
VCC
C13
VCC
C15
VCC
C17
VCC
C18
VCC
D9
VCC
D10
VCC
D12
VCC
D14
VCC
D15
VCC
D17
VCC
D18
VCC
E7
VCC
E9
VCC
E10
VCC
E12
VCC
E13
VCC
E15
VCC
E17
VCC
E18
VCC
E20
VCC
F7
VCC
F9
VCC
F10
VCC
F12
VCC
F14
VCC
F15
VCC
F17
VCC
F18
VCC
F20
VCC
AA7
VCC
AA9
VCC
AA10
VCC
AA12
VCC
AA13
VCC
AA15
VCC
AA17
VCC
AA18
VCC
AA20
VCC
AB9
VCC
AC10
VCC
AB10
VCC
AB12
VCC
AB14
VCC
AB15
VCC
AB17
VCC
AB18
VCC
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
3 OF 4
3 OF 4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
R130
R130
R123
R123
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
VCC_SENSE
VSS_SENSE
VCC_SENSE
VSS_SENSE
1 2
1 2
R121 100R2F-L1-GP-UR121 100R2F-L1-GP-U
Close to CPU pin
within 500mils
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
CPU_VID[0..6] 38
VCC_SENSE 38
VSS_SENSE 38
1 2
R122 100R2F-L1-GP-UR122 100R2F-L1-GP-U
1 2
1D05V_S0
TC13
TC13
SE330U2VDM-6-GP
SE330U2VDM-6-GP
12
DY
DY
1D5V_S0
C282
C282
12
12
VCC_CORE_S0
C289
C289
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
Length match within
25 mils . The trace
width/space/other is
20/7/25 .
layout note:
place C3 near
PIN B26
1D05V_S0
Close to CPU
pin AD26
Z0=55 ohm
with in
500mils .
5
R331
R331
1KR2F-3-GP
1KR2F-3-GP
1 2
V_CPU_GTLREF
12
R332
R332
2KR2F-3-GP
2KR2F-3-GP
C587
C587
12
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
4
3
2
Meron(2/3)-AGTL+/PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
1
of
of
of
5
5
5
A
51Wednesday, August 15, 2007
51Wednesday, August 15, 2007
51Wednesday, August 15, 2007
5
A
4 OF 4
4 OF 4
U56D
U56D
A4
VSS
D D
C C
B B
A8
VSS
A11
VSS
A14
VSS
A16
VSS
A19
VSS
A23
VSS
AF2
VSS
B6
VSS
B8
VSS
B11
VSS
B13
VSS
B16
VSS
B19
VSS
B21
VSS
B24
VSS
C5
VSS
C8
VSS
C11
VSS
C14
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C25
VSS
D1
VSS
D4
VSS
D8
VSS
D11
VSS
D13
VSS
D16
VSS
D19
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E11
VSS
E14
VSS
E16
VSS
E19
VSS
E21
VSS
E24
VSS
F5
VSS
F8
VSS
F11
VSS
F13
VSS
F16
VSS
F19
VSS
F2
VSS
F22
VSS
F25
VSS
G4
VSS
G1
VSS
G23
VSS
G26
VSS
H3
VSS
H6
VSS
H21
VSS
H24
VSS
J2
VSS
J5
VSS
J22
VSS
J25
VSS
K1
VSS
K4
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L21
VSS
L24
VSS
M2
VSS
M5
VSS
M22
VSS
M25
VSS
N1
VSS
N4
VSS
N23
VSS
N26
VSS
P3
VSS
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
5
4
Place these capacitors on L1
(North side ,Secondary Layer)
Place these capacitors on L1
(North side ,Secondary Layer)
1D05V_S0
C249
C247
C247
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
C249
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
4
VCC_CORE_S0
VCC_CORE_S0
C248
C248
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
3
C258
C258
C271
C271
C251
C251
12
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C559
C559
C532
C532
12
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C263
C263
C268
C268
C267
12
12
DY
DY
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C257
C257
C256
C256
12
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C267
12
12
DY
DY
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C275
C275
C558
C558
12
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
2
C274
C274
C272
C272
12
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C540
C540
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
1
Mid Frequencd
Decoupling
Place these
3
C278
C278
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
C279
C279
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
C280
C280
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
2
inside socket
cavity on L1
(North side
Secondary)
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(3/3)-GND&Bypass
Meron(3/3)-GND&Bypass
Meron(3/3)-GND&Bypass
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
1
A
51Monday, July 30, 2007
51Monday, July 30, 2007
51Monday, July 30, 2007
of
of
of
6
6
6
A
1 OF 10
1 OF 10
U18A
12
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
B3
C2
W1
W2
B6
E5
B9
A9
H_RCOMP
R144
R144
24D9R2F-L-GP
24D9R2F-L-GP
U18A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
H_ADSTB#0
H_ADSTB#1
HOST
HOST
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
R325
R325
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
1D05V_S0
12
12
100R2F-L1-GP-U
100R2F-L1-GP-U
R323
R323
221R2F-2-GP
221R2F-2-GP
H_A#3
J13
H_A#4
B11
H_A#5
C11
H_A#6
M11
H_A#7
C15
H_A#8
F16
H_A#9
L13
H_A#10
G17
H_A#11
C14
H_A#12
K16
H_A#13
B13
H_A#14
L16
H_A#15
J17
H_A#16
B14
H_A#17
K19
H_A#18
P15
H_A#19
R17
H_A#20
B16
H_A#21
H20
H_A#22
L19
H_A#23
D17
H_A#24
M17
H_A#25
N16
H_A#26
J19
H_A#27
B18
H_A#28
E19
H_A#29
B17
H_A#30
B15
H_A#31
E17
H_A#32
C18
H_A#33
A19
H_A#34
B19
H_A#35
N19
H_ADS#
G12
H_ADSTB#0
H17
H_ADSTB#1
G20
H_BNR#
C8
H_BPRI#
E8
H_BR0#
F12
H_DEFER#
D6
H_DBSY#
C10
CLK_MCH_BCLK
AM5
CLK_MCH_BCLK#
AM7
H_DPWR#
H8
H_DRDY#
K7
H_HIT#
E4
H_HITM#
C6
H_LOCK#
G10
H_TRDY#
B7
H_DINV#0
K5
H_DINV#1
L2
H_DINV#2
AD13
H_DINV#3
AE13
H_DSTBN#0
M7
H_DSTBN#1
K3
H_DSTBN#2
AD2
H_DSTBN#3
AH11
H_DSTBP#0
L7
H_DSTBP#1
K2
H_DSTBP#2
AC2
H_DSTBP#3
AJ10
H_REQ#0
M14
H_REQ#1
E13
H_REQ#2
A11
H_REQ#3
H13
H_REQ#4
B12
H_RS#0
E12
H_RS#1
D7
H_RS#2
D8
H_SWNGH_VREF
12
C577
C577
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note :
Place C153 near
pin B3 of NB
4
4
H_A#[3..35] 4H_D#[0..63]5
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5
H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5
H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5
H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4
H_RS#0 4
H_RS#1 4
H_RS#2 4
PM_PWROK20,22
VGATE_PWRGD20,38
12
C252
SC2D2U10V3ZY-1GP
C252
SC2D2U10V3ZY-1GP
SM_RCOMP_VOH
SM_RCOMP_VOL
C265
C265
1 2
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
PM_EXTTS#0
PM_EXTTS#1
CLKREQ#_B
CFG[17:3] have internal pull up
CFG[19:18] have internal pull down
R300 10KR2J-3-GPR300 10KR2J-3-GP
R288 10KR2J-3-GPR288 10KR2J-3-GP
R284 10KR2J-3-GPR284 10KR2J-3-GP
From Astro demo schematic
0R2J-2-GP
0R2J-2-GP
DY
DY
R277
R277
1 2
1 2
R278 0R0402-PADR278 0R0402-PAD
R314 2K2R2J-2-GPR314 2K2R2J-2-GP
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
D D
C C
1D05V_S0
R133
R133
R141
R141
12
12
54D9R2F-L1-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
H_RESET#4
H_CPUSLP#5
H_VREF
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWNG
H_RCOMP
H_SCOMP
H_SCOMP#
H_RESET#
H_CPUSLP#
B B
layout note :
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
Layout Note :
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
1D05V_S0
12
R320
R320
1KR2F-3-GP
1KR2F-3-GP
12
R319
R319
2KR2F-3-GP
2KR2F-3-GP
Layout Note :
Place C151 within 100 mils of NB
12
C568
C568
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
5
1D8V_S3
12
12
C255
C255
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
12
12
C264
C264
1 2
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
DDR_A_MA1413
DDR_B_MA1414
1 2
1 2
1 2
PM_BMBUSY#20
H_DPRSTP#5,19,38
PM_EXTTS#013
PM_EXTTS#114
H_THERMTRIP#4,19
DPRSLPVR20,38
1 2
1 2
R291 2K2R2J-2-GPR291 2K2R2J-2-GP
3
R125
R125
1KR2F-3-GP
1KR2F-3-GP
R126
R126
3K01R2F-3-GP
3K01R2F-3-GP
R127
R127
1KR2F-3-GP
1KR2F-3-GP
3D3V_S0
MCH_CLKSEL03
MCH_CLKSEL13
MCH_CLKSEL23
TP98TP98
TP102TP102
TP100TP100
TP105TP105
TP106TP106
TP96TP96
TP99TP99
TP97TP97
TP104TP104
TP101TP101
TP95TP95
TP93TP93
TP92TP92
PM_POK_R
CFG9
ICH_SDVO_DATA
3
DDR_A_MA14
DDR_B_MA14
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG16
CFG18
CFG19
CFG20
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST_R#
H_THERMTRIP#
DPRSLPVR
P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
G41
L39
L36
J36
AW49
AV20
N20
G36
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
PLT_RST_R#
2 OF 10
2 OF 10
U18B
U18B
RSVD#P36
RSVD#P37
RSVD#R35
RSVD#N35
RSVD#AR12
RSVD#AR13
RSVD#AM12
RSVD#AN13
RSVD#J12
RSVD#AR37
RSVD#AM36
RSVD#AL36
RSVD#AM37
RSVD#D20
RSVD#H10
RSVD#B51
RSVD#BJ20
RSVD#BK22
RSVD#BF19
RSVD#BH20
RSVD#BK18
RSVD#BJ18
RSVD#BF23
RSVD#BG23
RSVD#BC23
RSVD#BD24
RSVD#BJ29
RSVD#BE24
RSVD#BH39
RSVD#AW20
RSVD#BK20
RSVD#C48
RSVD#D47
RSVD#B44
RSVD#C44
RSVD#A35
RSVD#B37
RSVD#B36
RSVD#B34
RSVD#C34
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#0
PM_EXT_TS#1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC#BJ51
NC#BK51
NC#BK50
NC#BL50
NC#BL49
NC#BL3
NC#BL2
NC#BK1
NC#BJ1
NC#E1
NC#A5
NC#C51
NC#B50
NC#A50
NC#A49
NC#BK2
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
R316
R316
1 2
100R2J-2-GP
100R2J-2-GP
RSVD
RSVD
DDR MUXING
DDR MUXING
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF#AR49
SM_VREF#AW4
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK
CLK
DMI
DMI
CFG PM NC
CFG PM NC
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MISC ME GRAPHICS VID
MISC ME GRAPHICS VID
2
AV29
SM_CK0
BB23
SM_CK1
BA25
SM_CK3
AV23
SM_CK4
AW30
SM_CK#0
BA23
SM_CK#1
AW25
SM_CK#3
AW23
SM_CK#4
BE29
SM_CKE0
AY32
SM_CKE1
BD39
SM_CKE3
BG37
SM_CKE4
BG20
SM_CS#0
BK16
SM_CS#1
BG16
SM_CS#2
BE13
SM_CS#3
BH18
SM_ODT0
BJ15
SM_ODT1
BJ14
SM_ODT2
BE16
SM_ODT3
BK31
BL31
BL15
SM_RCOMP
SM_RCOMP#
BK14
AR49
AW4
B42
C42
H48
H47
K44
PEG_CLK
K45
PEG_CLK#
AN47
DMI_RXN0
AJ38
DMI_RXN1
AN42
DMI_RXN2
AN46
DMI_RXN3
AM47
DMI_RXP0
AJ39
DMI_RXP1
AN41
DMI_RXP2
AN45
DMI_RXP3
AJ46
DMI_TXN0
AJ41
DMI_TXN1
AM40
DMI_TXN2
AM44
DMI_TXN3
AJ47
DMI_TXP0
AJ42
DMI_TXP1
AM39
DMI_TXP2
AM43
DMI_TXP3
E35
GFX_VID0
A39
GFX_VID1
C38
GFX_VID2
B39
GFX_VID3
E36
GFX_VR_EN
AM49
CL_CLK
AK50
CL_DATA
AT43
CL_PWROK
AN49
CL_RST#
AM50
CL_VREF
H35
K36
G39
CLKREQ#
G40
ICH_SYNC#
A37
TEST1
R32
TEST2
PLT_RST1# 18,20,23,29,31,32,45
2
1
FOR Calero: 80.6 ohm
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_RCOMP
SM_RCOMP#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DFGT_VID0
DFGT_VID1
DFGT_VID2
DFGT_VID3
DFGT_VR_EN
CLPWROK_MCH
CL_VREF
ICH_SDVO_CLK
ICH_SDVO_DATA
MCH_ICH_SYNC#
TEST1_GMCH
TEST2_GMCH
R298
R298
20KR2J-L2-GP
20KR2J-L2-GP
Crestline: 20 ohm
M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14
M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14
DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14
DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14
M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14
1D8V_S3
1 2
R128 20R2F-GPR128 20R2F-GP
1 2
R315 20R2F-GPR315 20R2F-GP
DDR_VREF_S3
1 2
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
DDR_VREF_S3
CLK_MCH_3GPLL 3
CLK_MCH_3GPLL# 3
DMI_TXN0 20
DMI_TXN1 20
DMI_TXN2 20
DMI_TXN3 20
DMI_TXP0 20
DMI_TXP1 20
DMI_TXP2 20
DMI_TXP3 20
DMI_RXN0 20
DMI_RXN1 20
DMI_RXN2 20
DMI_RXN3 20
DMI_RXP0 20
DMI_RXP1 20
DMI_RXP2 20
DMI_RXP3 20
TP91TP91
TP27TP27
TP88TP88
TP87TP87
TP94TP94
1 2
R308 0R0402-PADR308 0R0402-PAD
CRESTLINE(1/6)-AGTL+/DMI/DDR2
CRESTLINE(1/6)-AGTL+/DMI/DDR2
CRESTLINE(1/6)-AGTL+/DMI/DDR2
VGATE_PWRGD 20,38
CL_RST# 20
TP90TP90
TP89TP89
CLKREQ#_B 3
MCH_ICH_SYNC# 20
1 2
R124 0R0402-PADR124 0R0402-PAD
R292
R292
2K2R2J-2-GP
2K2R2J-2-GP
DY
DY
ICH_SDVO_DATA
ICH_SDVO_CLK
1D25V_S0
CL_CLK0 20
CL_DATA0 20
12
C215
C215
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
1
2D5V_S0
12
1 2
12
R98
R98
392R2F-GP
392R2F-GP
7
7
7
12
R290
R290
2K2R2J-2-GP
2K2R2J-2-GP
DY
DY
R99
R99
1KR2F-3-GP
1KR2F-3-GP
of
of
of
A
51Wednesday, August 15, 2007
51Wednesday, August 15, 2007
51Wednesday, August 15, 2007
5
A
4
3
2
1
DDR_A_D[0..63] 13
DDR_A_BS[0..2] 13
SA_BS0
SA_BS1
SA_BS2
SA_CAS#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS#
SA_WE#
DDR_A_DM[0..7] 13
DDR_A_DQS[0..7] 13
DDR_A_DQS#[0..7] 13
DDR_A_MA[0..13] 13
DDR_A_BS0
BB19
DDR_A_BS1
BK19
DDR_A_BS2
BF29
DDR_A_CAS#
BL17
DDR_A_DM0
AT45
DDR_A_DM1
BD44
DDR_A_DM2
BD42
DDR_A_DM3
AW38
DDR_A_DM4
AW13
DDR_A_DM5
BG8
DDR_A_DM6
AY5
DDR_A_DM7
AN6
DDR_A_DQS0
AT46
DDR_A_DQS1
BE48
DDR_A_DQS2
BB43
DDR_A_DQS3
BC37
DDR_A_DQS4
BB16
DDR_A_DQS5
BH6
DDR_A_DQS6
BB2
DDR_A_DQS7
AP3
DDR_A_DQS#0
AT47
DDR_A_DQS#1
BD47
DDR_A_DQS#2
BC41
DDR_A_DQS#3
BA37
DDR_A_DQS#4
BA16
DDR_A_DQS#5
BH7
DDR_A_DQS#6
BC1
DDR_A_DQS#7
AP2
DDR_A_MA0
BJ19
DDR_A_MA1
BD20
DDR_A_MA2
BK27
DDR_A_MA3
BH28
DDR_A_MA4
BL24
DDR_A_MA5
BK28
DDR_A_MA6
BJ27
DDR_A_MA7
BJ25
DDR_A_MA8
BL28
DDR_A_MA9
BA28
DDR_A_MA10
BC19
DDR_A_MA11
BE28
DDR_A_MA12
BG30
DDR_A_MA13
BJ16
DDR_A_RAS#
BE18
SA_RCVEN#
AY20
DDR_A_WE#
BA19
5 OF 10
5 OF 10
U18E
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_A_CAS# 13 DDR_B_CAS# 14
DDR_A_RAS# 13
TP107TP107
DDR_A_WE# 13
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
U18E
AP49
SB_DQ0
AR51
SB_DQ1
AW50
SB_DQ2
AW51
SB_DQ3
AN51
SB_DQ4
AN50
SB_DQ5
AV50
SB_DQ6
AV49
SB_DQ7
BA50
SB_DQ8
BB50
SB_DQ9
BA49
SB_DQ10
BE50
SB_DQ11
BA51
SB_DQ12
AY49
SB_DQ13
BF50
SB_DQ14
BF49
SB_DQ15
BJ50
SB_DQ16
BJ44
SB_DQ17
BJ43
SB_DQ18
BL43
SB_DQ19
BK47
SB_DQ20
BK49
SB_DQ21
BK43
SB_DQ22
BK42
SB_DQ23
BJ41
SB_DQ24
BL41
SB_DQ25
BJ37
SB_DQ26
BJ36
SB_DQ27
BK41
SB_DQ28
BJ40
SB_DQ29
BL35
SB_DQ30
BK37
SB_DQ31
BK13
SB_DQ32
BE11
SB_DQ33
BK11
SB_DQ34
BC11
SB_DQ35
BC13
SB_DQ36
BE12
SB_DQ37
BC12
SB_DQ38
BG12
SB_DQ39
BJ10
SB_DQ40
BL9
SB_DQ41
BK5
SB_DQ42
BL5
SB_DQ43
BK9
SB_DQ44
BK10
SB_DQ45
BJ8
SB_DQ46
BJ6
SB_DQ47
BF4
SB_DQ48
BH5
SB_DQ49
BG1
SB_DQ50
BC2
SB_DQ51
BK3
SB_DQ52
BE4
SB_DQ53
BD3
SB_DQ54
BJ2
SB_DQ55
BA3
SB_DQ56
BB3
SB_DQ57
AR1
SB_DQ58
AT3
SB_DQ59
AY2
SB_DQ60
AY3
SB_DQ61
AU2
SB_DQ62
AT2
SB_DQ63
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
D D
4 OF 10
4 OF 10
U18D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
C C
B B
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
U18D
AR43
SA_DQ0
AW44
SA_DQ1
BA45
SA_DQ2
AY46
SA_DQ3
AR41
SA_DQ4
AR45
SA_DQ5
AT42
SA_DQ6
AW47
SA_DQ7
BB45
SA_DQ8
BF48
SA_DQ9
BG47
SA_DQ10
BJ45
SA_DQ11
BB47
SA_DQ12
BG50
SA_DQ13
BH49
SA_DQ14
BE45
SA_DQ15
AW43
SA_DQ16
BE44
SA_DQ17
BG42
SA_DQ18
BE40
SA_DQ19
BF44
SA_DQ20
BH45
SA_DQ21
BG40
SA_DQ22
BF40
SA_DQ23
AR40
SA_DQ24
AW40
SA_DQ25
AT39
SA_DQ26
AW36
SA_DQ27
AW41
SA_DQ28
AY41
SA_DQ29
AV38
SA_DQ30
AT38
SA_DQ31
AV13
SA_DQ32
AT13
SA_DQ33
AW11
SA_DQ34
AV11
SA_DQ35
AU15
SA_DQ36
AT11
SA_DQ37
BA13
SA_DQ38
BA11
SA_DQ39
BE10
SA_DQ40
BD10
SA_DQ41
BD8
SA_DQ42
AY9
SA_DQ43
BG10
SA_DQ44
AW9
SA_DQ45
BD7
SA_DQ46
BB9
SA_DQ47
BB5
SA_DQ48
AY7
SA_DQ49
AT5
SA_DQ50
AT7
SA_DQ51
AY6
SA_DQ52
BB7
SA_DQ53
AR5
SA_DQ54
AR8
SA_DQ55
AR9
SA_DQ56
AN3
SA_DQ57
AM8
SA_DQ58
AN10
SA_DQ59
AT9
SA_DQ60
AN9
SA_DQ61
AM9
SA_DQ62
AN11
SA_DQ63
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
DDR SYSTEM MEMORRY A
DDR SYSTEM MEMORRY A
SA_RCVEN#
DDR_B_D[0..63] 14
DDR_B_BS[0..2] 14
DDR_B_DM[0..7] 14
DDR_B_DQS[0..7] 14
DDR_B_DQS#[0..7] 14
DDR_B_MA[0..13] 14
DDR_B_BS0
AY17
SB_BS0
SB_BS1
SB_BS2
SB_CAS#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_RAS#
SB_RCVEN#
SB_WE#
BG18
BG36
BE17
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_RAS#
SB_RCVEN#
DDR_B_WE#
DDR_B_RAS# 14
TP108TP108
DDR_B_WE# 14
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRESTLINE(2/6)-DDR2 A/B CH
CRESTLINE(2/6)-DDR2 A/B CH
CRESTLINE(2/6)-DDR2 A/B CH
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
1
of
of
of
8
8
8
A
51Wednesday, August 15, 2007
51Wednesday, August 15, 2007
51Wednesday, August 15, 2007
5
A
3 OF 10
3 OF 10
U18C
U18C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
D D
C C
B B
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#0
E51
LVDSA_DATA#1
F49
LVDSA_DATA#2
G50
LVDSA_DATA0
E50
LVDSA_DATA1
F48
LVDSA_DATA2
G44
LVDSB_DATA#0
B47
LVDSB_DATA#1
B45
LVDSB_DATA#2
E44
LVDSB_DATA0
A47
LVDSB_DATA1
A45
LVDSB_DATA2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL0
P33
TV_DCONSEL1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
E33
CRT_VSYNC
C32
CRT_TVO_IREF
F33
CRT_HSYNC
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
PEG_COMPI
PEG_COMPO
LVDS
LVDS
TV VGA
TV VGA
PCI_EXPRESS GRAPHICS
PCI_EXPRESS GRAPHICS
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
4
1D05V_S0
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
1 2
R281 24D9R2F-L-GPR281 24D9R2F-L-GP
PEGCOMP
PEG_RXP15 45
PEG_RXP14 45
PEG_RXP13 45
PEG_RXP12 45
PEG_RXP11 45
PEG_RXP10 45
PEG_RXP9 45
PEG_RXP8 45
PEG_RXP7 45
PEG_RXP6 45
PEG_RXP5 45
PEG_RXP4 45
PEG_RXP3 45
PEG_RXP2 45
PEG_RXP1 45
PEG_RXP0 45
PEG_RXN15 45
PEG_RXN14 45
PEG_RXN13 45
PEG_RXN12 45
PEG_RXN11 45
PEG_RXN10 45
PEG_RXN9 45
PEG_RXN8 45
PEG_RXN7 45
PEG_RXN6 45
PEG_RXN5 45
PEG_RXN4 45
PEG_RXN3 45
PEG_RXN2 45
PEG_RXN1 45
TXN0
TXN1
TXN2
TXN3
TXN4
TXN5
TXN6
TXN7
TXN8
TXN9
TXN10
TXN11
TXN12
TXN13
TXN14
TXN15
TXP0
TXP1
TXP2
TXP3
TXP4
TXP5
TXP6
TXP7
TXP8
TXP9
TXP10
TXP11
TXP12
TXP13
TXP14
TXP15
PEG_RXN0 45
1 2
C460 SCD1U10V2KX-5GPC460 SCD1U10V2KX-5GP
1 2
C478 SCD1U10V2KX-5GPC478 SCD1U10V2KX-5GP
1 2
C455 SCD1U10V2KX-5GPC455 SCD1U10V2KX-5GP
1 2
C211 SCD1U10V2KX-5GPC211 SCD1U10V2KX-5GP
1 2
C212 SCD1U10V2KX-5GPC212 SCD1U10V2KX-5GP
1 2
C473 SCD1U10V2KX-5GPC473 SCD1U10V2KX-5GP
1 2
C469 SCD1U10V2KX-5GPC469 SCD1U10V2KX-5GP
1 2
C458 SCD1U10V2KX-5GPC458 SCD1U10V2KX-5GP
1 2
C490 SCD1U10V2KX-5GPC490 SCD1U10V2KX-5GP
1 2
C462 SCD1U10V2KX-5GPC462 SCD1U10V2KX-5GP
1 2
C464 SCD1U10V2KX-5GPC464 SCD1U10V2KX-5GP
1 2
C447 SCD1U10V2KX-5GPC447 SCD1U10V2KX-5GP
1 2
C457 SCD1U10V2KX-5GPC457 SCD1U10V2KX-5GP
1 2
C449 SCD1U10V2KX-5GPC449 SCD1U10V2KX-5GP
1 2
C208 SCD1U10V2KX-5GPC208 SCD1U10V2KX-5GP
1 2
C444 SCD1U10V2KX-5GPC444 SCD1U10V2KX-5GP
1 2
C461 SCD1U10V2KX-5GPC461 SCD1U10V2KX-5GP
1 2
C479 SCD1U10V2KX-5GPC479 SCD1U10V2KX-5GP
1 2
C454 SCD1U10V2KX-5GPC454 SCD1U10V2KX-5GP
1 2
C210 SCD1U10V2KX-5GPC210 SCD1U10V2KX-5GP
1 2
C213 SCD1U10V2KX-5GPC213 SCD1U10V2KX-5GP
1 2
C472 SCD1U10V2KX-5GPC472 SCD1U10V2KX-5GP
1 2
C470 SCD1U10V2KX-5GPC470 SCD1U10V2KX-5GP
1 2
C459 SCD1U10V2KX-5GPC459 SCD1U10V2KX-5GP
1 2
C494 SCD1U10V2KX-5GPC494 SCD1U10V2KX-5GP
1 2
C463 SCD1U10V2KX-5GPC463 SCD1U10V2KX-5GP
1 2
C465 SCD1U10V2KX-5GPC465 SCD1U10V2KX-5GP
1 2
C446 SCD1U10V2KX-5GPC446 SCD1U10V2KX-5GP
1 2
C456 SCD1U10V2KX-5GPC456 SCD1U10V2KX-5GP
1 2
C448 SCD1U10V2KX-5GPC448 SCD1U10V2KX-5GP
1 2
C209 SCD1U10V2KX-5GPC209 SCD1U10V2KX-5GP
1 2
C445 SCD1U10V2KX-5GPC445 SCD1U10V2KX-5GP
PEGCOMP trace
width and spacing
is 20/25 mils.
PEG_TXP15 45
PEG_TXP14 45
PEG_TXP13 45
PEG_TXP12 45
PEG_TXP11 45
PEG_TXP10 45
PEG_TXP9 45
PEG_TXP8 45
PEG_TXP7 45
PEG_TXP6 45
PEG_TXP5 45
PEG_TXP4 45
PEG_TXP3 45
PEG_TXP2 45
PEG_TXP1 45
PEG_TXP0 45
PEG_TXN15 45
PEG_TXN14 45
PEG_TXN13 45
PEG_TXN12 45
PEG_TXN11 45
PEG_TXN10 45
PEG_TXN9 45
PEG_TXN8 45
PEG_TXN7 45
PEG_TXN6 45
PEG_TXN5 45
PEG_TXN4 45
PEG_TXN3 45
PEG_TXN2 45
PEG_TXN1 45
PEG_TXN0 45
3
2
1
Strap Pin Table
010 = FSB 800MHz
CFG[2:0] FSB Freq select
CFG5 (DMI select)
CFG6 Reserved
CFG7 (CPU Strap)
CFG8 (Low power PCIE)
(PCIE Graphics Lane Reversal)
CFG9
CFG[11:10] Reserved
CFG[13:12] (XOR/ALLZ)
CFG[15:14] Reserved
CFG16 (FSB Dynamic ODT)
CFG[18:17] Reversed
SDVO_CTRLDATA 0 = No SDVO Device Present *
CFG19(DMI Lane Reversal)
CFG20(PCIE/SDVO consurrent)
011 = FSB 667MHz
Others = Reserved
0 = DMI x 2
1 = DMI x 4 *
0 = Reserved
1 = Mobile CPU *
0 = Normal mode
1 = Low Power mode *
0 = Reverse Lane
1 = Normal Operation *
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)*
0 = Disable
1 = Enable *
1 = SDVO Device Present
0 = Normal Operation *
(Lane number in Order)
1 = Reverse lane
0 = Only PCIE or SDVO is operational *
1 = PCIE/SDVO are operating simu.
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRESTLINE(3/6)-VGA/LVDS/TV
CRESTLINE(3/6)-VGA/LVDS/TV
CRESTLINE(3/6)-VGA/LVDS/TV
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Wednesday, August 15, 2007
Date: Sheet
Wednesday, August 15, 2007
Date: Sheet
Wednesday, August 15, 2007
Date: Sheet
5
4
3
2
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
1
of
of
of
951
951
951
A
5
A
D D
1D25V_S0_HPLL
1D8V_S0_TXLVDS
3D3V_S0
R97
R97
1 2
0R0603-PAD
0R0603-PAD
C C
1D25V_S0
R143
R143
R139
R139
1 2
0R0603-PAD
0R0603-PAD
1 2
0R0805-PAD
0R0805-PAD
1D25V_S0_SM_CK
12
C512
C512
12
C581
C581
DY
DY
DY
DY
12
12
C524
C524
C519
C519
1D25V_S0_MPLL
3D3V_S0_PEG_BG
12
C218
C218
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D25V_S0_PEGPLL
1D25V_S0_A_SM
12
C582
C582
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
ST22U6D3VBM-1GP
ST22U6D3VBM-1GP
12
C527
C527
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C499
C499
12
C562
C562
12
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
C552
C552
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
20mil
B B
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
1D5V_S0_TVDAC
1D25V_S0_HPLL
1D25V_S0_PEGPLL
4
J32
VCC_SYNC
A33
VCCA_CRT_DAC
B33
VCCA_CRT_DAC
A30
VCCA_DAC_BG
B32
VSSA_DAC_BG
B49
VCCA_DPLLA
H49
VCCA_DPLLB
AL2
VCCA_HPLL
AM2
VCCA_MPLL
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
U51
VCCA_PEG_PLL
AW18
VCCA_SM
AV19
VCCA_SM
AU19
VCCA_SM
AU18
VCCA_SM
AU17
VCCA_SM
AT22
VCCA_SM
AT21
VCCA_SM
AT19
VCCA_SM
AT18
VCCA_SM
AT17
VCCA_SM
AR17
VCCA_SM_NCTF
AR16
VCCA_SM_NCTF
BC29
VCCA_SM_CK
BB29
VCCA_SM_CK
C25
VCCA_TVA_DAC
B25
VCCA_TVA_DAC
C27
VCCA_TVB_DAC
B27
VCCA_TVB_DAC
B28
VCCA_TVC_DAC
A28
VCCA_TVC_DAC
M32
VCCD_CRT
L29
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41
VCCD_LVDS
H42
VCCD_LVDS
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
U18H
U18H
8 OF 10
8 OF 10
POWER
POWER
A LVDS PLL CRT
A LVDS PLL CRT
AXD
AXD
VCC_AXD_NCTF
A PEG
A PEG
SM CK
SM CK
TV A CK A SM
TV A CK A SM
DMI
DMI
LVDS TV/CRT
LVDS TV/CRT
VTT
VTT
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXF
VCC_AXF
AXF
AXF
VCC_AXF
VCC_DMI
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_TX_LVDS
VCC_HV
VCC_HV
HV
HV
VCC_PEG
VCC_PEG
VCC_PEG
PEG
PEG
VCC_PEG
VCC_PEG
VCC_RXR_DMI
VCC_RXR_DMI
VTTLF
VTTLF
VTTLF
VTTLF
VTTLF
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
1D05V_S0
VTTLF1
VTTLF2
VTTLF3
ST220U2VBM-3GP
ST220U2VBM-3GP
12
TC18
TC18
DY
DY
1D25V_S0_AXD
C545
C545
12
1D05V_S0_PEG
20mil
C283
C283
12
3
C509
C509
12
12
C503
C503
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
1D25V_S0_AXF
1D25V_S0_DMI
1D8V_S3_SM_CK
C284
C284
12
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C504
C504
C565
C565
12
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
R140
R140
1 2
0R0805-PAD
0R0805-PAD
C538
C538
SC10U10V5KX-2GP
SC10U10V5KX-2GP
3D3V_S0_HV
12
C571
C571
12
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
C506
C506
2
Intel spec:
VCC_RXR_DMI , Imax=200 mA
1D25V_S0_DMI
R102
R102
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
1D25V_S0
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C207
C207
12
1D25V_S0_PEGPLL
C205
C205
SC10U10V5KX-2GP
SC10U10V5KX-2GP
1 2
0R0603-PAD
0R0603-PAD
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C214
C214
12
1D25V_S0
L12
L12
1 2
BLM18PG121SN-1GP
BLM18PG121SN-1GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
1D25V_S0
MV-2
1D05V_S0_PEG
DY
DY
DY
C198
C198
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D05V_S0_PEG
12
1D05V_S0
DY
C201
C201
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
Intel spec:
VCC_PEX ,Imax=1200 mA
60mil
SC10U10V5KX-2GP
SC10U10V5KX-2GP
12
TC3
TC3
TC17
TC17
ST220U2VBM-3GP
ST220U2VBM-3GP
ST220U2VBM-3GP
ST220U2VBM-3GP
D19
D19
21
SSM5818SLPT-GP
SSM5818SLPT-GP
C194
C194
12
3D3V_S0
R81
R81
1 2
0R0805-PAD
0R0805-PAD
1D05V_S0_D
R108
R108
10R2J-2-GP
10R2J-2-GP
1D05V_S0
12
1D25V_S0_AXF
DY
DY
12
R295
R295
0R0402-PAD
0R0402-PAD
12
C544
C544
1D8V_S3_SM_CK
12
C535
C535
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
1D5V_S0_TVDAC
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
C525
C525
12
1D25V_S0_HPLL
12
C575
C575
1D25V_S0_MPLL
12
C288
C288
SC10U10V5KX-2GP
SC10U10V5KX-2GP
3D3V_S0_HV
12
C530
C530
1
R311
R311
1 2
0R0603-PAD
0R0603-PAD
12
C539
C539
SC1U16V3ZY-GP
SC1U16V3ZY-GP
R103
R103
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
0R0805-PAD
0R0805-PAD
C547
C547
12
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
R328
R328
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C526
C526
0R0805-PAD
0R0805-PAD
12
L29
L29
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
BLM18AG121SN-1GP
BLM18AG121SN-1GP
C573
C573
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
L13
L13
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
BLM18AG121SN-1GP
BLM18AG121SN-1GP
C281
C281
12
12
C501
C501
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1D25V_S0
1D8V_S3
1D5V_S0
1D25V_S0
1D25V_S0
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRESTLINE(4/6)-PWR
CRESTLINE(4/6)-PWR
CRESTLINE(4/6)-PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
5
4
3
2
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
1
of
of
of
10
10
10
A
51Sunday, September 09, 2007
51Sunday, September 09, 2007
51Sunday, September 09, 2007
5
A
7 OF 10
7 OF 10
U18G
1D05V_S0
D D
C574
C574
C534 SCD22U10V2KX-1GPC534 SCD22U10V2KX-1GP
C533 SCD1U16V2ZY-2GPC533 SCD1U16V2ZY-2GP
12
12
ST220U2VBM-3GP
ST220U2VBM-3GP
C520 SCD22U10V2KX-1GPC520 SCD22U10V2KX-1GP
12
12
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
TC12
TC12
C C
1D05V_S0
12
12
C563
C563
C566
C566
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
B B
C516 SCD1U16V2ZY-2GPC516 SCD1U16V2ZY-2GP
C513 SCD1U16V2ZY-2GPC513 SCD1U16V2ZY-2GP
C518 SCD1U16V2ZY-2GPC518 SCD1U16V2ZY-2GP
C510
C510
C549
C549
12
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
12
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
12
12
12
U18G
AB33
VCC_NCTF
AB36
VCC_NCTF
AB37
VCC_NCTF
AC33
VCC_NCTF
AC35
VCC_NCTF
AC36
VCC_NCTF
AD35
VCC_NCTF
AD36
VCC_NCTF
AF33
VCC_NCTF
AF36
VCC_NCTF
AH33
VCC_NCTF
AH35
VCC_NCTF
AH36
VCC_NCTF
AH37
VCC_NCTF
AJ33
VCC_NCTF
AJ35
VCC_NCTF
AK33
VCC_NCTF
AK35
VCC_NCTF
AK36
VCC_NCTF
AK37
VCC_NCTF
AD33
VCC_NCTF
AJ36
VCC_NCTF
AM35
VCC_NCTF
AL33
VCC_NCTF
AL35
VCC_NCTF
AA33
VCC_NCTF
AA35
VCC_NCTF
AA36
VCC_NCTF
AP35
VCC_NCTF
AP36
VCC_NCTF
AR35
VCC_NCTF
AR36
VCC_NCTF
Y32
VCC_NCTF
Y33
VCC_NCTF
Y35
VCC_NCTF
Y36
VCC_NCTF
Y37
VCC_NCTF
T30
VCC_NCTF
T34
VCC_NCTF
T35
VCC_NCTF
U29
VCC_NCTF
U31
VCC_NCTF
U32
VCC_NCTF
U33
VCC_NCTF
U35
VCC_NCTF
U36
VCC_NCTF
V32
VCC_NCTF
V33
VCC_NCTF
V36
VCC_NCTF
V37
VCC_NCTF
AL24
VCC_AXM_NCTF
AL26
VCC_AXM_NCTF
AL28
VCC_AXM_NCTF
AM26
VCC_AXM_NCTF
AM28
VCC_AXM_NCTF
AM29
VCC_AXM_NCTF
AM31
VCC_AXM_NCTF
AM32
VCC_AXM_NCTF
AM33
VCC_AXM_NCTF
AP29
VCC_AXM_NCTF
AP31
VCC_AXM_NCTF
AP32
VCC_AXM_NCTF
AP33
VCC_AXM_NCTF
AL29
VCC_AXM_NCTF
AL31
VCC_AXM_NCTF
AL32
VCC_AXM_NCTF
AR31
VCC_AXM_NCTF
AR32
VCC_AXM_NCTF
AR33
VCC_AXM_NCTF
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS NCTF
VSS NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VCC NCTF
VCC NCTF
POWER
POWER
VSS SCBVSS AXM
VSS SCBVSS AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VSS AXM NCTF
VSS AXM NCTF
1D05V_S0 3D3V_S0
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
CH751H-40PT-1GP
CH751H-40PT-1GP
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
4
TP32TP32
TP36TP36
TP37TP37
TP38TP38
TP9TP9
TP11TP11
1D05V_S0
D29
D29
KA
R303
R303
10R2J-2-GP
10R2J-2-GP
12
TC4
TC4
DY
DY
12
3
1D8V_S3
12
C555SC1U10V3KX-3GP C555SC1U10V3KX-3GP
2
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
1D05V_S0
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
C529 SCD1U16V2ZY-2GPC529 SCD1U16V2ZY-2GP
12
C569SCD1U16V2ZY-2GP C569SCD1U16V2ZY-2GP
12
1D05V_S0
R305
R305
VCC_GMCH1
1 2
0R0603-PAD
0R0603-PAD
C514
C514
C259
C259
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C508 SCD01U16V2KX-3GPC508 SCD01U16V2KX-3GP
12
12
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1D05V_S0
C553 SCD1U16V2ZY-2GPC553 SCD1U16V2ZY-2GP
12
12
C548SC10U10V5KX-2GP C548SC10U10V5KX-2GP
12
ST220U2VBM-3GP
ST220U2VBM-3GP
TC19
TC19
12
C554SC10U10V5KX-2GP C554SC10U10V5KX-2GP
ST220U2VBM-3GP
ST220U2VBM-3GP
U18F
U18F
AT35
VCC
AT34
VCC
AH28
VCC
AC32
VCC
AC31
VCC
AK32
VCC
AJ31
VCC
AJ28
VCC
AH32
VCC
AH31
VCC
AH29
VCC
AF32
VCC
R30
VCC
AU32
VCC_SM
AU33
VCC_SM
AU35
VCC_SM
AV33
VCC_SM
AW33
VCC_SM
AW35
VCC_SM
AY35
VCC_SM
BA32
VCC_SM
BA33
VCC_SM
BA35
VCC_SM
BB33
VCC_SM
BC32
VCC_SM
BC33
VCC_SM
BC35
VCC_SM
BD32
VCC_SM
BD35
VCC_SM
BE32
VCC_SM
BE33
VCC_SM
BE35
VCC_SM
BF33
VCC_SM
BF34
VCC_SM
BG32
VCC_SM
BG33
VCC_SM
BG35
VCC_SM
BH32
VCC_SM
BH34
VCC_SM
BH35
VCC_SM
BJ32
VCC_SM
BJ33
VCC_SM
BJ34
VCC_SM
BK32
VCC_SM
BK33
VCC_SM
BK34
VCC_SM
BK35
VCC_SM
BL33
VCC_SM
AU30
VCC_SM
R20
VCC_AXG
T14
VCC_AXG
W13
VCC_AXG
W14
VCC_AXG
Y12
VCC_AXG
AA20
VCC_AXG
AA23
VCC_AXG
AA26
VCC_AXG
AA28
VCC_AXG
AB21
VCC_AXG
AB24
VCC_AXG
AB29
VCC_AXG
AC20
VCC_AXG
AC21
VCC_AXG
AC23
VCC_AXG
AC24
VCC_AXG
AC26
VCC_AXG
AC28
VCC_AXG
AC29
VCC_AXG
AD20
VCC_AXG
AD23
VCC_AXG
AD24
VCC_AXG
AD28
VCC_AXG
AF21
VCC_AXG
AF26
VCC_AXG
AA31
VCC_AXG
AH20
VCC_AXG
AH21
VCC_AXG
AH23
VCC_AXG
AH24
VCC_AXG
AH26
VCC_AXG
AD31
VCC_AXG
AJ20
VCC_AXG
AN14
VCC_AXG
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
LIB C
6 OF 10
6 OF 10
VCC CORE
VCC CORE
POWER
POWER
VCC SM
VCC SM
VCC GFX
VCC GFX
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC SM LF
VCC SM LF
1
C550
C550
C537
C537
12
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C476SC1U10V3KX-3GP C476SC1U10V3KX-3GP
C495SCD47U16V3ZY-3GP C495SCD47U16V3ZY-3GP
C557SCD22U10V2KX-1GP C557SCD22U10V2KX-1GP
C498SC1U10V3KX-3GP C498SC1U10V3KX-3GP
12
12
12
C567SCD1U16V2ZY-2GP C567SCD1U16V2ZY-2GP
C576SCD22U10V2KX-1GP C576SCD22U10V2KX-1GP
12
12
12
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRESTLINE(5/6)-PWR/GND
CRESTLINE(5/6)-PWR/GND
CRESTLINE(5/6)-PWR/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
of
of
of
11
11
11
A
51Monday, July 30, 2007
51Monday, July 30, 2007
51Monday, July 30, 2007
5
A
U18I
U18I
A13
VSS
A15
VSS
A17
VSS
A24
VSS
D D
C C
B B
AA21
VSS
AA24
VSS
AA29
VSS
AB20
VSS
AB23
VSS
AB26
VSS
AB28
VSS
AB31
VSS
AC10
VSS
AC13
VSS
AC3
VSS
AC39
VSS
AC43
VSS
AC47
VSS
AD1
VSS
AD21
VSS
AD26
VSS
AD29
VSS
AD3
VSS
AD41
VSS
AD45
VSS
AD49
VSS
AD5
VSS
AD50
VSS
AD8
VSS
AE10
VSS
AE14
VSS
AE6
VSS
AF20
VSS
AF23
VSS
AF24
VSS
AF31
VSS
AG2
VSS
AG38
VSS
AG43
VSS
AG47
VSS
AG50
VSS
AH3
VSS
AH40
VSS
AH41
VSS
AH7
VSS
AH9
VSS
AJ11
VSS
AJ13
VSS
AJ21
VSS
AJ24
VSS
AJ29
VSS
AJ32
VSS
AJ43
VSS
AJ45
VSS
AJ49
VSS
AK20
VSS
AK21
VSS
AK26
VSS
AK28
VSS
AK31
VSS
AK51
VSS
AL1
VSS
AM11
VSS
AM13
VSS
AM3
VSS
AM4
VSS
AM41
VSS
AM45
VSS
AN1
VSS
AN38
VSS
AN39
VSS
AN43
VSS
AN5
VSS
AN7
VSS
AP4
VSS
AP48
VSS
AP50
VSS
AR11
VSS
AR2
VSS
AR39
VSS
AR44
VSS
AR47
VSS
AR7
VSS
AT10
VSS
AT14
VSS
AT41
VSS
AT49
VSS
AU1
VSS
AU23
VSS
AU29
VSS
AU3
VSS
AU36
VSS
AU49
VSS
AU51
VSS
AV39
VSS
AV48
VSS
AW1
VSS
AW12
VSS
AW16
VSS
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
5
9 OF 10
9 OF 10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
4
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
3
10 OF 10
10 OF 10
U18J
U18J
C46
VSS
C50
VSS
C7
VSS
D13
VSS
D24
VSS
D3
VSS
D32
VSS
D39
VSS
D45
VSS
D49
VSS
E10
VSS
E16
VSS
E24
VSS
E28
VSS
E32
VSS
E47
VSS
F19
VSS
F36
VSS
F4
VSS
F40
VSS
F50
VSS
G1
VSS
G13
VSS
G16
VSS
G19
VSS
G24
VSS
G28
VSS
G29
VSS
G33
VSS
G42
VSS
G45
VSS
G48
VSS
G8
VSS
H24
VSS
H28
VSS
H4
VSS
H45
VSS
J11
VSS
J16
VSS
J2
VSS
J24
VSS
J28
VSS
J33
VSS
J35
VSS
J39
VSS
K12
VSS
K47
VSS
K8
VSS
L1
VSS
L17
VSS
L20
VSS
L24
VSS
L28
VSS
L3
VSS
L33
VSS
L49
VSS
M28
VSS
M42
VSS
M46
VSS
M49
VSS
M5
VSS
M50
VSS
M9
VSS
N11
VSS
N14
VSS
N17
VSS
N29
VSS
N32
VSS
N36
VSS
N39
VSS
N44
VSS
N49
VSS
N7
VSS
P19
VSS
P2
VSS
P23
VSS
P3
VSS
P50
VSS
R49
VSS
T39
VSS
T43
VSS
T47
VSS
U41
VSS
U45
VSS
U50
VSS
V2
VSS
V3
VSS
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
3
2
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
CRESTLINE(6/6)-PWR/GND
CRESTLINE(6/6)-PWR/GND
CRESTLINE(6/6)-PWR/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
ME3-Discrete
ME3-Discrete
ME3-Discrete
2
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
51Monday, July 30, 2007
51Monday, July 30, 2007
51Monday, July 30, 2007
of
of
of
12
12
12
1
A
5
4
3
2
1
DDR_A_DQS#[0..7]8
DDR_A_D[0..63]8
DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8
D D
C C
B B
A A
Layout Note:
Place near DM1
1D8V_S3
DY
DY
DY
C223
C223
C242
C242
12
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
DDR_VREF_S0
DY
DY
C474
C474
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_CAS#
DDR_CKE1_DIMMA DDR_A_MA14
12
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
DY
DY
C483
C483
C468
C468
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN13 SRN56J-4-GPRN13 SRN56J-4-GP
1
2 3
RN16 SRN56J-4-GPRN16 SRN56J-4-GP
1
2 3
RN54 SRN56J-4-GPRN54 SRN56J-4-GP
1
2 3
RN19 SRN56J-4-GPRN19 SRN56J-4-GP
1
2 3
RN22 SRN56J-4-GPRN22 SRN56J-4-GP
1
2 3
RN25 SRN56J-4-GPRN25 SRN56J-4-GP
1
2 3
RN49 SRN56J-4-GPRN49 SRN56J-4-GP
1
2 3
5
12
C250
C250
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
C481
C481
4
4
4
4
4
4
4
DY
C260
C260
12
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
DY
DY
C497
C497
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_VREF_S0
4
4
4
4
4
4
4
12
12
RN8 SRN56J-4-GPRN8 SRN56J-4-GP
RN51 SRN56J-4-GPRN51 SRN56J-4-GP
RN11 SRN56J-4-GPRN11 SRN56J-4-GP
RN52 SRN56J-4-GPRN52 SRN56J-4-GP
RN53 SRN56J-4-GPRN53 SRN56J-4-GP
RN55 SRN56J-4-GPRN55 SRN56J-4-GP
RN50 SRN56J-4-GPRN50 SRN56J-4-GP
C266
C266
C493
C493
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
C228
C228
12
C507
C507
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
23
1
23
1
23
1
23
1
23
1
23
1
23
DDR_A_BS[0..2]8
C515
C515
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
C219
C219
C502
C502
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_A_BS2
DDR_CKE0_DIMMA
DDR_A_MA7
DDR_A_MA6
DDR_A_MA12
DDR_A_MA9
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
M_ODT0
DDR_A_MA13
DDR_A_MA11
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C237
C237
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C243
C243
C231
C231
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C234
C234
C227
C227
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note:
Place these resistors
closely DM1,all
trace length Max=1.5"
4
TC5
TC5
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
ST220U2VBM-3GP
ST220U2VBM-3GP
12
C253
C253
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_VREF_S3
DDR_A_MA147
M_ODT07
M_ODT17
DDR_VREF_S3
C84
C84
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BS2 DDR_A_DM0
DDR_A_BS0
DDR_A_BS1
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
M_ODT0
M_ODT1
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
12
C90
C90
3
MH1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND
MH1
DM2
DM2
DDR2-200P-20-GP-U
DDR2-200P-20-GP-U
RAS#
WE#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
MH2
108
109
113
110
115
79
80
30
CK0
32
164
CK1
166
10
26
52
67
130
147
170
185
195
197
199
R321 10KR2J-3-GPR321 10KR2J-3-GP
198
SA0
R322 10KR2J-3-GPR322 10KR2J-3-GP
200
SA1
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
MH2
2
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
ICH_SMBDATA
ICH_SMBCLK
1 2
1 2
1D8V_S3
<Variant Name>
<Variant Name>
<Variant Name>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
DDR_A_RAS# 8
DDR_A_WE# 8
DDR_A_CAS# 8
DDR_CS0_DIMMA# 7
DDR_CS1_DIMMA# 7
DDR_CKE0_DIMMA 7
DDR_CKE1_DIMMA 7
M_CLK_DDR0 7
M_CLK_DDR#0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
ICH_SMBDATA 3,14,20
ICH_SMBCLK 3,14,20
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C570
PM_EXTTS#0 7
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
C570
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
1
3D3V_S0
12
C572
C572
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
of
13 51Wednesday, August 15, 2007
13 51Wednesday, August 15, 2007
13 51Wednesday, August 15, 2007
5
DDR_B_DQS#[0..7]8
DDR_B_D[0..63]8
DDR_B_DM[0..7]8
DDR_B_DQS[0..7]8
C467
C467
12
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
C239
C239
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_VREF_S0
DDR_B_MA[0..13]8
12
12
RN10
RN10
4
RN7
RN7
4
RN14
RN14
4
RN12
RN12
4
RN15
RN15
4
RN24
RN24
4
RN6
RN6
4
SRN56J-4-GP
SRN56J-4-GP
C238
C238
C262
C262
DDR_B_BS[0..2]8
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C491
C491
12
C233
C233
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
DY
DY
C187
C187
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C240
C240
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_B_MA12
DDR_B_MA9
DDR_CKE3_DIMMB
DDR_B_MA11
DDR_B_MA5DDR_B_MA0
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
M_ODT2
DDR_B_MA13
DDR_B_BS2DDR_B_MA14
DDR_CKE2_DIMMB
D D
C C
B B
A A
Layout Note:
Place near DM2
1D8V_S3
DY
DY
C480
C480
C245
12
C254
C254
5
12
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
C204
C204
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
C245
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
DY
DY
C220
C220
4
4
4
4
4
4
4
C551
C551
12
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
DDR_VREF_S0
DY
DY
C246
C246
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN17 SRN56J-4-GPRN17 SRN56J-4-GP
DDR_B_MA3
DDR_B_MA1
RN20 SRN56J-4-GPRN20 SRN56J-4-GP
DDR_B_MA10
DDR_B_BS0
RN18 SRN56J-4-GPRN18 SRN56J-4-GP
DDR_B_BS1
RN21 SRN56J-4-GPRN21 SRN56J-4-GP
DDR_CS2_DIMMB#
DDR_B_RAS#
RN23 SRN56J-4-GPRN23 SRN56J-4-GP
DDR_B_WE#
DDR_B_CAS#
RN26 SRN56J-4-GPRN26 SRN56J-4-GP
DDR_CS3_DIMMB#
M_ODT3
RN9 SRN56J-4-GPRN9 SRN56J-4-GP
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C244
C244
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
DY
DY
C230
C230
C261
C261
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
C241
C241
C224
C224
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
DY
C203
C203
C232
C232
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note:
Place these resistors
closely DM2,all
trace length Max=1.5"
DDR_VREF_S3
DDR_B_MA147
M_ODT27
M_ODT37
DDR_VREF_S3
C77
C77
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3
3
12
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_BS2
DDR_B_BS0
DDR_B_BS1
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
M_ODT2
M_ODT3
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
C85
C85
MH1
DM1
DM1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND
MH1
DDR2-200P-21-GP-U
DDR2-200P-21-GP-U
RAS#
WE#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
VDDSPD
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
MH2
2
108
109
113
110
115
79
80
30
CK0
32
164
CK1
166
10
26
52
67
130
147
170
185
195
197
SCL
199
R327 10KR2J-3-GPR327 10KR2J-3-GP
198
SA0
R330 10KR2J-3-GPR330 10KR2J-3-GP
200
SA1
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
VSS
8
VSS
9
VSS
12
VSS
15
VSS
18
VSS
21
VSS
24
VSS
27
VSS
28
VSS
33
VSS
34
VSS
39
VSS
40
VSS
41
VSS
42
VSS
47
VSS
48
VSS
53
VSS
54
VSS
59
VSS
60
VSS
65
VSS
66
VSS
71
VSS
72
VSS
77
VSS
78
VSS
121
VSS
122
VSS
127
VSS
128
VSS
132
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
149
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
165
VSS
168
VSS
171
VSS
172
VSS
177
VSS
178
VSS
183
VSS
184
VSS
187
VSS
190
VSS
193
VSS
196
VSS
201
MH2
2
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
ICH_SMBDATA
ICH_SMBCLK
1 2
1 2
1D8V_S3
1
DDR_B_RAS# 8
DDR_B_WE# 8
DDR_B_CAS# 8
DDR_CS2_DIMMB# 7
DDR_CS3_DIMMB# 7
DDR_CKE2_DIMMB 7
DDR_CKE3_DIMMB 7
M_CLK_DDR2 7
M_CLK_DDR#2 7
M_CLK_DDR3 7
M_CLK_DDR#3 7
ICH_SMBDATA 3,13,20
ICH_SMBCLK 3,13,20
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
PM_EXTTS#1 7
<Variant Name>
<Variant Name>
<Variant Name>
Title
Title
Title
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
12
C585
C585
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
ME3-Discrete
ME3-Discrete
ME3-Discrete
C578
C578
12
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
14 51Wednesday, August 15, 2007
14 51Wednesday, August 15, 2007
14 51Wednesday, August 15, 2007
1
3D3V_S0
of
of
of
A
CRT I/F & CONNECTOR
Layout Note:
Place these resistors
close to the CRT-out
connector
4 4
VGA_RED46
VGA_GREEN46
VGA_BLUE46
12
R25
R25
150R2F-1-GP
150R2F-1-GP
12
12
R19
R19
150R2F-1-GP
150R2F-1-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
R17
R17
150R2F-1-GP
150R2F-1-GP
12
C44
C44
Layout Note:
* Must be a ground return path between this ground and the ground on
B
SB
L7
L7
1 2
BLM18BB470SN1-GP
BLM18BB470SN1-GP
L4
L4
1 2
BLM18BB470SN1-GP
BLM18BB470SN1-GP
L1
L1
1 2
BLM18BB470SN1-GP
12
C34
C34
SC10P50V2JN-4GP
SC10P50V2JN-4GP
BLM18BB470SN1-GP
12
C29
C29
SC10P50V2JN-4GP
SC10P50V2JN-4GP
12
C43
C43
SC2P50V2CN-GP
SC2P50V2CN-GP
C
12
C22
C22
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
DY
CRT_R
CRT_G
CRT_B
12
12
C33
C33
C28
C28
SC2P50V2CN-GP
SC2P50V2CN-GP
SC2P50V2CN-GP
SC2P50V2CN-GP
DY
TP4TPAD30 TP4TPAD30
TP3TPAD30 TP3TPAD30
TP2TPAD30 TP2TPAD30
CRT_R
1
CRT_G
1
CRT_B
1
D
F1
F1
12
POLYSW-1A6V-3-GP
POLYSW-1A6V-3-GP
6
1
7
2
8
3
9
4
10
5
20.20424.015
20.20424.015
5V_CRT_S0_D
CRT1
CRT1
17
11
12
13
14
15
16
VIDEO-15-57-GP-U1
VIDEO-15-57-GP-U1
SC33P50V2JN-3GP
SC33P50V2JN-3GP
E
5V_S05V_CRT_S0
D1
D1
K A
CH751H-40PT-1GP
CH751H-40PT-1GP
1
23
RN3
RN3
SRN2K7J-3-GP
SRN2K7J-3-GP
DY
DY
C75
C75
4
SC22P50V2JN-4GP
SC22P50V2JN-4GP
12
12
5V_CRT_S0
C60
C60
DY
DY
DDC_DATA_CON
JVGA_HS
JVGA_VS
DDC_CLK_CON
SC22P50V2JN-4GP
SC22P50V2JN-4GP
12
12
C26
C24
C24
DY
DY
C26
SC33P50V2JN-3GP
SC33P50V2JN-3GP
DY
DY
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
3 3
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
Hsync & Vsync level shift
GMCH_HSYNC46
14
4
GMCH_VSYNC46
2 2
Layout Note:
close to the TV-out connector
VGA_TV_LUMA46
VGA_TV_CRMA46
1 1
VGA_TV_COMP46
12
R258
R258
12
R250
R250
12
R256
R256
A
SC82P50V2JN-3GP
SC82P50V2JN-3GP
150R2F-1-GP
150R2F-1-GP
SC82P50V2JN-3GP
SC82P50V2JN-3GP
150R2F-1-GP
150R2F-1-GP
SC82P50V2JN-3GP
SC82P50V2JN-3GP
150R2F-1-GP
150R2F-1-GP
5 6
U5B TSAHCT125PW-GPU5B TSAHCT125PW-GP
7
C442 SC8P250V2CC-GPC442 SC8P250V2CC-GP
1 2
12
BLM18BB221SN1D-GP
BLM18BB221SN1D-GP
C440
C440
C429 SC8P250V2CC-GPC429 SC8P250V2CC-GP
1 2
12
BLM18BB221SN1D-GP
BLM18BB221SN1D-GP
C425
C425
SB
C437 SC8P250V2CC-GPC437 SC8P250V2CC-GP
1 2
12
BLM18BB221SN1D-GP
BLM18BB221SN1D-GP
C433
C433
1 2
L26
L26
SB
1 2
L23
L23
1 2
L24
L24
SB
12
C441
C441
SC82P50V2JN-3GP
SC82P50V2JN-3GP
12
C426
C426
SC82P50V2JN-3GP
SC82P50V2JN-3GP
12
C434
C434
SC82P50V2JN-3GP
SC82P50V2JN-3GP
5V_S0
12
14
1
2 3
U5A TSAHCT125PW-GPU5A TSAHCT125PW-GP
7
C16
C16
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
HSYNC_5
RN2
RN2
VSYNC_5
1
2 3
SRN33J-5-GP-U
SRN33J-5-GP-U
TV OUT CONN
TV1
TV1
4
LUMA
6
CRMA
7
COMP
5
NC#5
MINDIN7-18-GP
MINDIN7-18-GP
22.10021.H31
22.10021.H31
B
TV_LUMA
TV_CRMA
TV_COMP
NC#2
GND
GND
GND
GND
4
JVGA_HS
JVGA_VS
2
1
3
8
9
VGA_DDCDATA46
VGA_DDCCLK46
TV_COMP
TV_CRMA
TV_LUMA
C
D16
D16
3
BAV99TPT-GP
BAV99TPT-GP
3
3
D18
D18
BAV99TPT-GP
BAV99TPT-GP
D14
D14
BAV99TPT-GP
BAV99TPT-GP
3D3V_S0
4
SRN2K7J-3-GP
SRN2K7J-3-GP
RN4
RN4
1
2 3
U8
U8
5
6
DDC_CLK & DATA level shift
3D3V_S0
2
1
2
1
2
1
3D3V_S0
34
2
2N7002DW-1-GP
2N7002DW-1-GP
1
DDC_DATA_CON
DDC_CLK_CON
D
CRT_R
CRT_G
CRT_B
DDC_DATA_CON
DDC_CLK_CON
JVGA_HS
JVGA_VS
<Variant Name>
<Variant Name>
<Variant Name>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
D8BAV99-7-F-GPDYD8BAV99-7-F-GP
D4BAV99-7-F-GPDYD4BAV99-7-F-GP
D2BAV99-7-F-GPDYD2BAV99-7-F-GP
D12BAV99-7-F-GPDYD12BAV99-7-F-GP
D13BAV99-7-F-GPDYD13BAV99-7-F-GP
D5BAV99-7-F-GPDYD5BAV99-7-F-GP
D3BAV99-7-F-GPDYD3BAV99-7-F-GP
CRT/TV CONNECTOR
CRT/TV CONNECTOR
CRT/TV CONNECTOR
ME3-Discrete
ME3-Discrete
ME3-Discrete
2
3
DY
1
2
3
DY
1
2
3
DY
1
2
3
DY
1
2
3
DY
1
2
3
DY
1
2
3
DY
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
15 51Thursday, September 13, 2007
15 51Thursday, September 13, 2007
15 51Thursday, September 13, 2007
E
of
of
of
LCD1
LCD1
46
47
48
49
50
51
52
53
54 55
IPEX-CON44-2-GP
IPEX-CON44-2-GP
20.F0713.044
20.F0713.044
LCD/INVERTER CONN
DCBATOUT
12
C1
45
NP1
1
2
3
4
5
6
LCD_5V
7
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NP2
TP1 TPAD30TP1 TPAD30
LCDVDD_EN46
C1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C6
C6
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
LDDC_CLK 46
LDDC_DATA 46
BLON_OUT 31
BRIGHTNESS 31
VGA_TXACLK- 46
VGA_TXACLK+ 46
VGA_TXAOUT0- 46
VGA_TXAOUT0+ 46
VGA_TXAOUT1- 46
VGA_TXAOUT1+ 46
VGA_TXAOUT2- 46
VGA_TXAOUT2+ 46
VGA_TXBCLK- 46
VGA_TXBCLK+ 46
VGA_TXBOUT0- 46
VGA_TXBOUT0+ 46
VGA_TXBOUT1- 46
VGA_TXBOUT1+ 46
VGA_TXBOUT2- 46
VGA_TXBOUT2+ 46
R15
R15
100KR2J-1-GP
100KR2J-1-GP
1 2
LCDVDD_S0
12
C7
C7
40 mil
LCDVDD_S0
12
C13
C13
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
3D3V_S0
40 mil
3D3V_S0
12
C12
C12
12
C9
C9
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
U4
U4
1
IN#1
2
OUT
3
EN
4
GND
G5281RC1U-GP
G5281RC1U-GP
LDDC_DATA
LDDC_CLK
1 2
1 2
1 2
GND
IN#8
IN#7
IN#6
IN#5
3D3V_S0
SB
R53710KR2J-3-GP R53710KR2J-3-GP
C8
C8
SC1000P50V3JN-GP
SC1000P50V3JN-GP
C10
C10
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
9
8
7
6
5
4
RN1
RN1
SRN4K7J-8-GP
SRN4K7J-8-GP
1
2 3
BLON_OUT
BRIGHTNESS
LED CONN
I=3.57 mA
R244
CHG_LED#_CN
STBY_LED#_CN
CAP_LED#_CN
NUM_LED#_CN
R244
1 2
255R2F-L-GP
255R2F-L-GP
R245
R245
1 2
255R2F-L-GP
255R2F-L-GP
I=3.57 mA
R23
R23
1 2
255R2F-L-GP
255R2F-L-GP
I=3.57 mA
R22
R22
1 2
255R2F-L-GP
255R2F-L-GP
POWER_LED#_CN
CHG_LED#
I=3.6 mA
R34
R34
1 2
255R2F-L-GP
255R2F-L-GP
STBY_LED#
CAP_LED#
TSAHCT08PWR-1GP
TSAHCT08PWR-1GP
MEDIA_LED#MEDIA_LED#_CN
TSAHCT08PWR-1GP
TSAHCT08PWR-1GP
NUM_LED#
TSAHCT08PWR-1GP
TSAHCT08PWR-1GP
R32
R32
1 2
100R2J-2-GP
100R2J-2-GP
C
E
R2
R2
PDTC124EU-1-GP
PDTC124EU-1-GP
C
E
R2
R2
PDTC124EU-1-GP
PDTC124EU-1-GP
U7A
U7A
U7B
U7B
6
U7C
U7C
8
POWER_LED#
12
Q13
Q13
R1
R1
B
Q14
Q14
R1
R1
B
5V_S0
147
3
5V_S0
147
5V_S0
147
U7D
U7D
EC1
EC1
TSAHCT08PWR-1GP
TSAHCT08PWR-1GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC
TP212TPAD30 TP212TPAD30
TP214TPAD30 TP214TPAD30
MEDIA_LED#_CN
TP219TPAD30 TP219TPAD30
STBY_LED#_CN
TP220TPAD30 TP220TPAD30
TP215TPAD30 TP215TPAD30
CHG_LED#_CN
TP216TPAD30 TP216TPAD30
TP218TPAD30 TP218TPAD30
TP217TPAD30 TP217TPAD30
TP221TPAD30 TP221TPAD30
TP222TPAD30 TP222TPAD30
TP223TPAD30 TP223TPAD30
TP224TPAD30 TP224TPAD30
CHG_LED 31
STBY_LED 31
1
2
4
5
9
10
11
5V_S0
147
CDROM_LED# 30
SATA_LED# 19
NUMLK_LED# 31
12
13
POWER_LED#_CN
CAPS_LED# 31
PWR_LED# 31
CAP_LED#_CN
NUM_LED#_CN
KBC_PWR_BTN#_CN
5V_S05V_S5
CN1
CN1
13
1
2
3
4
5
6
7
8
9
10
11
12
14
ACES-CON12-4-GP
ACES-CON12-4-GP
Place Top side and
close to connector
SC
TP213TPAD30TP213TPAD30
TP225TPAD30TP225TPAD30
LCDVDD_S0
LCDVDD_S0_R
1 2
R9 150R2F-1-GPR9 150R2F-1-GP
U1
U1
1
2
3 4
2N7002DW-7F-GP
2N7002DW-7F-GP
R247
R247
1 2
12
EC30
EC30
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3D3V_AUX_S5
12
100R2J-2-GP
100R2J-2-GP
12
R400
R400
10KR2J-3-GP
10KR2J-3-GP
C659
C659
SC1000P50V3JN-GP
SC1000P50V3JN-GP
DY
DY
KBC_PWR_BTN# 31
<Variant Name>
<Variant Name>
<Variant Name>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
LCD CONN & LED
LCD CONN & LED
LCD CONN & LED
ME3-Discrete
ME3-Discrete
ME3-Discrete
16 51Thursday, September 13, 2007
16 51Thursday, September 13, 2007
16 51Thursday, September 13, 2007
of
5V_S5
R14
R14
10KR2J-3-GP
10KR2J-3-GP
6
LCDVDD_ON#LCDVDD_EN
5
1 2
KBC_PWR_BTN#_CN
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