Winstron GW50 Schematics

5

Crystal

14.318MHz

D D

Four Peaks (15") Block Diagram

CLK GEN.

ICS 9LPRS365

3

Mobile CPU

Penryn

HOST BUS 667/800/1066MHz@1.05V

DDR3

800/1033 MHz

12,13

DDR3

800/1033 MHz

C C

B B

Int MIC

40

MIC In

40

INT.SPKR

1.5W

40

Line Out (No-SPDIF)

RJ11

12,13

Codec

ALC268

OP AMP

APL2057

MODEM

MDC Card

Crystal

32.768MHz

AZALIA

38

39

27

HDD SATA

ODD SATA

(Module Bay)

SATA

Cantiga

AGTL+ CPU I/F DDR Memory I/F

INTEGRATED GRAHPICS

LVDS, CRT I/F

X4 DMI 400MHz

ICH9M

6 PCIe ports

PCI/PCI BRIDGE

ACPI 2.0 4 SATA

12 USB 2.0/1.1 ports

ETHERNET (10/100/1000MbE)

High Definition Audio

LPC I/F

Serial Peripheral I/F

Matrix Storage Technology(DO)

Active Managemnet Technology(DO)

Mini USB

24

23

Blue Tooth

Finger Printer

6,7,8,9,10,11

C-Link0

19,20,21,22

26

29

MIC in/Line-out/Line-in

4, 5

USB

4

PCIex16

PCI

SPI

PCIe

C Link1 LPC BUS

Camera

USB 4 Port

SMSC

EMC2102

37

VGA Borad

(MXM Connector)

BIOS (4MB)

42

Crystal 25MHz

Crystal

32.768MHz

28

SWITCH PI5C3257QE

SWITCH PS8122QFN48G

46

CardBus

OZ711MZ0

Crystal

24.576MHz

IEEE1394 TSB43AB22A

Intel 82567

LAN

Giga LAN

30,31

New Card

KBC

Winbond

WPCE773LA0DG

INT.

Touch

KB

Pad

41 41

MS/MS Pro/xD /MMC/SD

5 in 1

PCMCIA SLOT

SMART CARD

1394x2

25

SWITCH

32

PI3L500ZFEX

PWR SW TPS2231

34 34

Mini Card Mini Card

Kedron

SPI

41

a/b/g/n

BIOS (1MB)

Launch Buttom

36

42

16

PSx2

3

LCD

15

CRT

17

CRT

DVI

18

DVI

31

35

TXFM RJ45

(Robson2/3G)

(WLAN)

LPC

DEBUG CONN.

TPM

SLB9635TT1D1

33 33

42

2

ezDockII/II+

USB/Express Card/MediaBay/1394*2port RJ45/RJ11/PS2*2/Serial Port/Parallel Port/CRT/TV/DVI-D/SPDIF/MIC in/Line in/Line out/AC Jack

LAN

Parallel-port

SuperIO

PC87383MG

FIR

Seria-port

44

Crystal

32.768MHz

Project code: 91.4Z901.001 PCB P/N : 48.4Z901.011 REVISION : -1M

44,45

2nd Battery

PCB STACKUP

TOP

VCC

S

GND

BOTTOM

1

SYSTEM DC/DC

TPS51125

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51124

INPUTS OUTPUTS

DCBATOUT

RT9026

1.5V_S3

G9131

3D3V_S0 2D5V_S0

TPS51117

DCBATOUT 1D8V_S0

CHARGER

DCBATOUT

CPU DC/DC

INPUTS

DCBATOUT

GFX DC/DC

INPUTS

DCBATOUT

OUTPUTS

5V_S5(7A) 3D3V_S5(7A) 5V_AUX_S5 3D3V_AUX_S5

1D05V_M(16A) 1D5V_S3(12A)

DDR_VREF_S3 (1.2A)

(300mA)

(9.4A)

BQ24750

OUTPUTSINPUTS

CHG_PWR

18V 6.0A

ISL6266A

OUTPUTS VCC_CORE

0~1.3V 38A

ISL6263

OUTPUTS

VCC_GFXCORE

0~1.3V

6.5A

50

51

52

54

55

49

53

A A

Four Peaks

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev A2

A2

A2 Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Four Peaks

1

-1M

157Friday, November 21, 2008

-1M

of

A

ICH9M Functional Strap Definitions

Signal

HDA_SDOUT

HDA_SYNC

4 4

GNT2#/ GPIO53

GPIO20 GNT1#/

GPIO51

GNT3#/ GPIO55

GNT0#: SPI_CS1#/ GPIO58

SPI_MOSI

3 3

GPIO49

SATALED#

SPKR

TP3

GPIO33/ HDA_DOCK _EN#

Usage/When Sampled

XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK

PCIE config1 bit0, Rising Edge of PWROK.

PCIE config2 bit2, Rising Edge of PWROK.

Reserved ESI Strap (Server Only)

Rising Edge of PWROK

Top-Block Swap Override. Rising Edge of PWROK.

Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.

Integrated TPM Enable, Rising Edge of CLPWROK

DMI Termination Voltage, Rising Edge of PWROK.

PCI Express Lane Reversal. Rising Edge of PWROK.

No Reboot. Rising Edge of PWROK.

XOR Chain Entrance. Rising Edge of PWROK.

Flash Descriptor Security Override Strap Rising Edge of PWROK

Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down

This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high.

ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile.

Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Sample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.

The signal is required to be low for desktop applications and required to be high for mobile applications.

Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)

If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.

This signal should not be pull low unless using XOR Chain testing.

Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister.

ICH9 EDS 642879 Rev.1.5

Comment

2 2

B

ICH9M Integrated Pull-up

page 92

and Pull-down Resistors

SIGNAL Resistor Type/Value

CL_CLK[1:0] CL_DATA[1:0] CL_RST0# DPRSLPVR/GPIO16 ENERGY_DETECT HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GLAN_DOCK#

GNT[3:0]#/GPIO[55,53,51]

GPIO[20] GPIO[49] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED#

SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI SPI_MISO SPKR TACH_[3:0] TP[3] USB[11:0][P,N]

C

Cantiga chipset and ICH9M I/O controller Hub strapping configuration

ICH9 EDS 642879 Rev.1.5

PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K

The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller

PULL-DOWN 20K

PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 15K

SDVO_CTRLDATA

D

Montevina Platform Design guide 22339 0.5

Pin Name

CFG[2:0]

CFG[4:3] CFG8 CFG[15:14] CFG[18:17]

CFG5 CFG6

CFG7

CFG9

CFG10 PCIE Loopback enable

CFG[13:12]

CFG16

CFG19

CFG20

L_DDC_DATA

NOTE:

1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal.

2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

Strap Description

FSB Frequency Select

Reserved

DMI x2 Select iTPM Host

Interface

Intel Management engine Crypto strap

PCIE Graphics Lane

XOR/ALL

FSB Dynamic ODT

DMI Lane Reversal

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe

SDVO Present

Local Flat Panel (LFP) Present

Configuration

000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved

0 = DMI x2

1 = DMI x4

0= The iTPM Host Interface is enabled(Note2)

1=The iTPM Host Interface is disalbed(default)

0 = Transport Layer Security (TLS) cipher suite with no confidentiality

1 = TLS cipher suite with confidentiality (default)

0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane Numbered in order

0 = Enable (Note 3)

1= Disabled (default)

00 = Reserve 10 = XOR mode Enabled 01 = ALLZ mode Enabled (Note 3)

11 = Disabled (default)

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled 0 = Normal operation(Default):

Lane Numbered in Order

1 = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1)

0 = Only Digital Display Port or PCIE is operational (Default)

1 =Digital display Port and PCIe are operting simulataneously via the PEG port

0 =No SDVO Card Present (Default)

1 = SDVO Card Present

0 = LFP Disabled (Default)

1= LFP Card Present; PCIE disabled

E

page 218

(Default)

SMBus

SMBC_G792

KBC

BAT_SCL

PCI Routing

INT REQ

G:CARDBUS

AD22TI7412

B:1394 F:Flash Media G:SD Host

page 17

GNTIDSEL

0 0

1 1

PCIE Routing

LANE1 LANE2 LANE3 NewCard WLAN

LAN BCM5787M MiniCard WLAN

USB Table

USB

Pair

0 1 2 3 4 5

7 8

Device NC NC USB2 USB4 USB3 BLUETOOTH WEBCAM6 FT MINICARD

SMB_CLK

ICH9M

SMBC_ICH

9 NEW1

Thermal

MXM

BATTERY

LAN

CK505

DDR

Four Peaks

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet of

Reference

Four Peaks

of

257Friday, November 21, 2008

-1M

3D3V_M

R240

1 2

0R0603-PAD

-1

3D3V_48MPWR_S0

DY

A

12

C271

C272

SC1U16V3ZY-GP

SC4D7U6D3V3KX-GP

B

3D3V_CLKPLL_S0

SC4D7U10V5ZY-3GP

12

C303

12

C285

C

R295

0R3-0-U-GP

SCD1U16V2ZY-2GP

DY

-1

3D3V_M

12

1D05V_M

R293

1 2

0R0603-PAD

SCD1U16V2ZY-2GP

12

C301

C304

SCD1U16V2ZY-2GP

12

C308

12

C295

SCD1U16V2ZY-2GP

12

C297

D

12

C310

SCD1U16V2ZY-2GP

12

C279

3D3V_CLKGEN_S0

SCD1U16V2ZY-2GP

SC4D7U10V5ZY-3GP

12

C294

C278

SCD1U16V2ZY-2GP

12

C309

1 2

0R0603-PAD

12

C288

E

3D3V_M

-1

R294

SCD1U16V2ZY-2GP

4 4

CL=20pF±0.2pF

C276

SC27P50V2JN-2-GP

1 2

C275

1 2

SC27P50V2JN-2-GP

R266

SC27P50V2JN-2-GP

R605

1 2

DY

R610

1 2

12

PCLKCLK2 PCLKCLK3 PCLKCLK4 PCLKCLK5

PCLKCLK2

3D3V_M

DY

3 3

R607

10KR2J-3-GP

R264

10KR2J-3-GP

PCLK_PCM_TI25

PCLK_PCM_O230

2 2

DY

10KR2J-3-GP

1 2

10KR2J-3-GP

1 2

R606

10KR2J-3-GP

1 2

-1M(6/25)

R265

1 2

12

C676

DY

SC20P50V2JN-1GP

12

C677

DY

SC20P50V2JN-1GP

DY

R248

SC22P50V2JN-4GP

R249 33R2J-2-GPR249 33R2J-2-GP

R424 22R2J-2-GPR424 22R2J-2-GP

10KR2J-3-GP

1 2

12

10KR2J-3-GP

ICS9LPRS365YGLFT setting table

PIN NAME DESCRIPTION

Byte 5, bit 7 0 = PCI0 enabled (default)

PCI0/CR#_A

PCI1/CR#_B

PCI2/TME

1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair

Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair

0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed

PCI3

1 1

PCI4/27M_SEL PCI_F5/ITP_EN

SRCT3/CR#_C

0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# 1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#

0 =SRC8/SRC8# 1 = ITP/ITP#

Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair

A

GEN_XTAL_IN

12

X5

X-14D31818M-44GP

GEN_XTAL_OUT_R

SC20P50V2JN-1GP

R270 10MR2J-L-GP

DY

R263

1 2

0R0402-PAD

CLK48_ICH20

CPU_SEL04,7

SC22P50V2JN-4GP

-1M(6/25)

C678

PCLK_SIO44 PCLK_O231

PCLK_KBC41 PCLK_ICH20

CPU_SEL14,7 CPU_SEL24,7

CLK_ICH1420

PCLK_SIO_144

B

12

DY

SC20P50V2JN-1GP

12

-1(5/9)

DY

1 2

SC20P50V2JN-1GP

12

C680

DY

12

DY

C682

R274 33R2J-2-GPR274 33R2J-2-GP R273 2K2R2J-2-GPR273 2K2R2J-2-GP

3D3V_M

CLK_PWRGD20

10KR2J-3-GP

C679

10KR2J-3-GP

R267 22R2J-2-GPR267 22R2J-2-GP R250 22R2J-2-GPR250 22R2J-2-GP

R247 22R2J-2-GPR247 22R2J-2-GP R246 33R2J-2-GPR246 33R2J-2-GP

SC20P50V2JN-1GP

C681

R268 10KR2J-3-GPR268 10KR2J-3-GP

RN47

2 3 1

SRN33J-5-GP-U

12

C683

SC18P50V2JN-1-GP

-1M(6/25)

PIN NAME DESCRIPTION

SRCC3/CR#_D

SRCC7/CR#_E

SRCT7/CR#_F

SRCC11/CR#_G

SRCT11/CR#_H

GEN_XTAL_OUT

DY

CLK48

12

PCLKCLK0 PCLKCLK1 PCLKCLK2 PCLKCLK3 PCLKCLK4 PCLKCLK5

CPU_SEL2_RCPU_SEL2_R

12 12

PM_STPPCI#20

PM_STPCPU#20

SMBC_ICH12,13,22

SMBD_ICH12,13,22

R278

12 12

12

4

-1

-1(5/14)

PCLK_TPM42

3D3V_48MPWR_S0

3D3V_CLKGEN_S0

9

46

62

16

23

PCLKCLK3

4

VDDREF

GND48

15

18

VDD48

GNDPCI

1

VDDPCI

VDDSRC

VDDCPU

VDDPLL3

GNDREF

GND

GNDSRC

22

30

36

49

SATACLKREQ#20 CLK_MCH_OE#7

TP198TPAD30 TP198TPAD30

MXM_CLKREQ#46

U29

3

X1

2

X2

17

USB_48MHZ/FSLA

45

PCI_STOP#

44

CPU_STOP#

7

SCLK

6

SDATA

63

CK_PWRGD/PD#

8

PCI0/CR#_A

10

PCI1/CR#_B

11

PCI2/TME

12

PCI3

13

PCI4/27_SELECT

14

PCI_F5/ITP_EN

64

FSLB/TEST_MODE

5

REF0/FSLC/TEST_SEL

55

NC#55

ICS9LPRS365BKLFT-GP-U

71.09365.A03

2nd = 71.00875.C03

R238

12

22R2J-2-GP

12

C675

SC20P50V2JN-1GP

Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair

Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_F controls SRC6

Byte 6, bit 6 0 = SRC7 enabled (default) 1= CR#_F controls SRC8

Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9

Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10

C

3D3V_CLKPLL_S0

33

43

52

56

19

27

VDD96_IO

VDDSRC_IO

VDDPLL3_IO

27MHZ_NONSS/SRCT1/SE1

GND

GNDSRC

GNDCPU

26

59

65

CPUT0

VDDCPU_IO

27MHZ_SS/SRCC1/SE2

GND

CPUC0

CPUT1_F CPUC1_F

CPUT2_ITP/SRCT8

CPUC2_ITP/SRCC8

SRCT7/CR#_F

SRCC7/CR#_E

SRCT6 SRCC6

SRCT10 SRCC10

SRCT11/CR#_H

SRCC11/CR#_G

SRCT9 SRCC9

SRCT4 SRCC4

SRCT3/CR#_C

SRCC3/CR#_D

SRCT2/SATAT

SRCC2/SATAC

SRCT0/DOTT_96

SRCC0/DOTC_96

RN94

1 2 3 4 5

SRN470J-3-GP

D

61 60

58 57

54 53

51 50

48 47

41 42

40 39

37 38

34 35

31 32

28 29

24 25

20 21

PCLKCLK0

8

PCLKCLK1

7

CLK_PCIE_DOCK

6

CLK_PCIE_DOCK#

CLK_PCIE_PEG_1 CLK_PCIE_PEG_1#

DREFSSCLK_1 DREFSSCLK_1#

DREFCLK_1 DREFCLK_1#

3D3V_S0

123

45

678

Four Peaks

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

RN23

2 3 1

DIS

UMA

2 3 1

4

UMA

RN93

RN93 SRN10KJ-6-GP

SRN10KJ-6-GP

SEL2 FSC

1 0

RN23 SRN0J-6-GP

SRN0J-6-GP

4

RN21

RN21 SRN0J-6-GP

SRN0J-6-GP

4

RN20

1

SRN0J-6-GP

23

SEL1

SEL0

FSB

FSA

01

01 01 0 00 0

Clock Generator

Four Peaks

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6

CLK_PCIE_NEW 34 CLK_PCIE_NEW# 34

CLK_PCIE_ICH 20 CLK_PCIE_ICH# 20

CLK_PCIE_PEG 46 CLK_PCIE_PEG# 46

CLK_PCIE_DOCK 44 CLK_PCIE_DOCK# 44

CLK_PCIE_MINI2 36 CLK_PCIE_MINI2# 36

CLK_PCIE_MINI1 36 CLK_PCIE_MINI1# 36

CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7

CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19

DREFSSCLK 7 DREFSSCLK# 7

DREFCLK 7 DREFCLK# 7

CPU

FSB

100M 133M

1 01

166M 200M

533M 667M 800M

1067M266M

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

357Friday, November 21, 2008

of

357Friday, November 21, 2008

of

357Friday, November 21, 2008

E

X

-1M

A

B

C

D

E

H_A#[35..3]6

4 4

H_ADSTB#06 H_REQ#[4..0]6

3 3

H_ADSTB#16

H_A20M#19

H_FERR#19

H_IGNNE#19

H_STPCLK#19

2 2

H_INTR19 H_NMI19 H_SMI#19

TP74TPAD30 TP74TPAD30

H_A#[35..3]

R128

1 2

0R0402-PAD

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

-1

H_STPCLK#_R

1 OF 4

CPU1A

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD#M4

N5

RSVD#N5

T2

RSVD#T2

V3

RSVD#V3

B2

RSVD#B2

C3

RSVD#C3

D2

RSVD#D2

D22

RSVD#D22

D3

RSVD#D3

F6

RSVD#F6

B1

KEY_NC

BGA479-SKT6-GPU7

62.10079.001

2nd: 62.10053.401

ADDR GROUP 0

ADDR GROUP 1

XDP/ITP SIGNALS CONTROL

XDP/ITP SIGNALS CONTROL THERMAL

THERMAL

PROCHOT#

ICH

THERMTRIP#

HCLK

RESERVED

XDP_TDI XDP_TMS

XDP_BPM#5

ADS# BNR# BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM0# BPM1# BPM2# BPM3# PRDY# PREQ#

TCK TDO

TMS

TRST#

DBR#

THRMDA THRMDC

BCLK0 BCLK1

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3 G2

G6 E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

AB3 AB5 AB6 C20

D21 A24 B25

C7

A22 A21

XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

-1(5/14)

RN96

1 2 3

SRN56J-4-GP

R89 54D9R2F-L1-GP

1 2

DY

TP53 TPAD30TP53 TPAD30

-1

1D05V_S0

12

R127

R127 56R2J-4-GP

56R2J-4-GP

H_RS#[2..0] 6

1D05V_S0

Place testpoint on H_IERR# with a GND

0.1" away

H_THERMDA

H_THERMDC

12

R121

R121 68R2-GP

68R2-GP

R28

1 2

0R2J-2-GP

DY

PM_THRMTRIP-A# 7,19,47

PH @ page48

Layout Note: "CPU_GTLREF0"

0.5" max length.

H_ADS# 6 H_BNR# 6

H_BPRI# 6

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6

H_BREQ#0 6

H_IERR#

H_INIT# 19 H_LOCK# 6

H_CPURST# 6

H_TRDY# 6 H_HIT# 6

H_HITM# 6

TP19 TPAD30TP19 TPAD30 C494 TP24 TPAD30TP24 TPAD30 TP16 TPAD30TP16 TPAD30 TP25 TPAD30TP25 TPAD30 TP23 TPAD30TP23 TPAD30 TP22 TPAD30TP22 TPAD30 TP26 TPAD30TP26 TPAD30 TP32 TPAD30TP32 TPAD30 TP29 TPAD30TP29 TPAD30 TP30 TPAD30TP30 TPAD30 TP31 TPAD30TP31 TPAD30 TP72 TPAD30TP72 TPAD30

CPU_PROCHOT#_1

H_THERMDA 37 H_THERMDC 37

R495

1 2

0R0402-PAD

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3

4

12

CPU_PROCHOT#_R 49

should connect toPM_THRMTRIP# without T-ingICH9 and MCH

1D05V_S0

1KR2F-3-GP

1KR2F-3-GP R100

R100

1 2 12

R90

2KR2F-3-GP

1 2

DY

R129 1KR2J-1-GP

1 2

DY

R130 1KR2J-1-GP

C443

DY

SCD1U10V2KX-4GP

C494 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

DY

CPU_GTLREF0

12

DY

C82

SC1KP50V2KX-1GP

TEST1

TEST2

TEST4

12

CPU1B

H_D#0

E22

H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8

H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14

H_DSTBN#06 H_DSTBP#06 H_DINV#06

H_DSTBN#16 H_DSTBP#16 H_DINV#16

TP69TPAD30 TP69TPAD30 TP9TPAD30 TP9TPAD30

TP79TPAD30 TP79TPAD30

CPU_SEL03,7 CPU_SEL13,7 CPU_SEL23,7

Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals

H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

TEST1 TEST2

RSVD_CPU_12

TEST4 RSVD_CPU_13 RSVD_CPU_14RSVD_CPU_11

D0#

F24

D1#

E26

D2#

G22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

D9#

J24

D10#

J23

D11#

H22

D12#

F26

D13#

K22

D14#

H23

D15#

J26

DSTBN0#

H26

DSTBP0#

H25

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L23

D20#

M24

D21#

L22

D22#

M23

D23#

P25

D24#

P23

D25#

P22

D26#

T24

D27#

R24

D28#

L25

D29#

T25

D30#

N25

D31#

L26

DSTBN1#

M26

DSTBP1#

N24

DINV1#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL0

B23

BSEL1

C21

BSEL2

BGA479-SKT6-GPU7

2 OF 4

DATA GRP0 DATA GRP1

DATA GRP2DATA GRP3

DSTBN2# DSTBP2#

DSTBN3# DSTBP3#

MISC

DPRSTP#

PWRGOOD

D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47#

DINV2#

D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#

DINV3# COMP0

COMP1 COMP2 COMP3

DPSLP#

DPWR#

SLP#

PSI#

H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0]

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25 Y26 AA26 U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23 AE25 AF24 AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1 E5

B5 D24 D6 D7 AE6

Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

H_DINV#[3..0] 6 H_DSTBN#[3..0] 6 H_DSTBP#[3..0] 6 H_D#[63..0] 6

H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6

H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6

R467 27D4R2F-L1-GPR467 27D4R2F-L1-GP

1 2

R461 54D9R2F-L1-GPR461 54D9R2F-L1-GP

1 2

R96 27D4R2F-L1-GPR96 27D4R2F-L1-GP

1 2

R97 54D9R2F-L1-GPR97 54D9R2F-L1-GP

1 2

H_DPRSTP# 7,19,49 H_DPSLP# 19 H_DPWR# 6 H_PWRGD 19,47 H_CPUSLP# 6 PSI# 49

1 1

RN95

XDP_TCK XDP_TRST#

All place within 2" to CPU

A

RN95

1 2 3

SRN56J-4-GP

B

4

-1(5/9)

C

H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# H_INIT# H_CPURST#

Place these TP on button-side, easy to measure.

TP66 TPAD30TP66 TPAD30 TP76 TPAD30TP76 TPAD30 TP94 TPAD30TP94 TPAD30 TP105 TPAD30TP105 TPAD30 TP92 TPAD30TP92 TPAD30 TP187 TPAD30TP187 TPAD30 TP71 TPAD30TP71 TPAD30

D

Four Peaks

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

CPU (1 of 2)

Four Peaks

E

457Friday, November 21, 2008

-1M

A

B

C

D

E

VCC_CORE

4 4

3 3

AA10 AA12

2 2

1 1

AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

CPU1C

A7

VCC

A9

VCC

A10

VCC

A12

VCC

A13

VCC

A15

VCC

A17

VCC

A18

VCC

A20

VCC

B7

VCC

B9

VCC

B10

VCC

B12

VCC

B14

VCC

B15

VCC

B17

VCC

B18

VCC

B20

VCC

C9

VCC

C10

VCC

C12

VCC

C13

VCC

C15

VCC

C17

VCC

C18

VCC

D9

VCC

D10

VCC

D12

VCC

D14

VCC

D15

VCC

D17

VCC

D18

VCC

E7

VCC

E9

VCC

E10

VCC

E12

VCC

E13

VCC

E15

VCC

E17

VCC

E18

VCC

E20

VCC

F7

VCC

F9

VCC

F10

VCC

F12

VCC

F14

VCC

F15

VCC

F17

VCC

F18

VCC

F20

VCC

AA7

VCC

AA9

VCC VCC VCC VCC VCC VCC VCC VCC

AB9

VCC VCC VCC VCC VCC VCC VCC VCC

BGA479-SKT6-GPU7

3 OF 4

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP

VCCA VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

VCC_CORE

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

C117

SCD1U10V2KX-4GP

GAP-CLOSE-PWR

C94

12

VCC_CORE

12

VCC_CORE

12

C481

G26

1 2

G22

1 2

SCD1U10V2KX-4GP

H_VID[6..0] 49

12

R79

R79 100R2F-L1-GP-U

100R2F-L1-GP-U

R73

R73 100R2F-L1-GP-U

100R2F-L1-GP-U

12

C477

SCD1U10V2KX-4GP

DY

VCC_CORE

1D05V_S0

DY

12

C476

C482

SCD1U10V2KX-4GP

C480

TC11

1D5V_VCCA_S0

C482

SCD1U10V2KX-4GP

DY

12

C123

SC10U6D3V5MX-3GP

ST220U6D3VDM-20GP

2nd = 80.22715.39L

layout note: "1D5V_VCCA_S0" as short as possible

12

C121

SCD01U16V2KX-3GP

VCC_SENSE 49

VSS_SENSE 49

Layout Note:

VCCSENSE and VSSSENSE lines

should be of equal length.

Layout Note:

Provide a test point (with

no stub) to connect a

differential probe

between VCCSENSE and

VSSSENSE at the location

where the two 54.9ohm

resistors terminate the

55 ohm transmission line.

SCD1U10V2KX-4GP

DY

12

C479

C125

SC10U6D3V5MX-3GP

L5

1 2

HCB1608KF121T30-GP

C126

68.00230.041

SC10U6D3V5MX-3GP

A11 A14 A16

TP10

TPAD30

DY

12

C67

C76

SC10U6D3V5MX-3GP

1D5V_S0

C76

SC10U6D3V5MX-3GP

12

C77

SC10U6D3V5MX-3GP

12

C70

C473

SC10U6D3V5MX-3GP

1D05V_S0

DY

12

SC10U6D3V5MX-3GP

C115

12

C124

12

C107

SCD1U10V2KX-4GP

12

C472

SC10U6D3V5MX-3GP

12

C98

SCD1U10V2KX-4GP

12

C485

C484

SC10U6D3V5MX-3GP

C484

SC10U6D3V5MX-3GP

DY

12

C99

C108

SCD1U10V2KX-4GP

12

C101

C102

SC10U6D3V5MX-3GP

SC4D7U6D3V3KX-GP

SC10U6D3V5MX-3GP

12

C104

SC4D7U6D3V3KX-GP

A19 A23 AF2

B11 B13 B16 B19 B21 B24

C11 C14 C16 C19

C22 C25

D11 D13 D16 D19 D23 D26

E11 E14 E16 E19 E21 E24

F11 F13 F16 F19

F22 F25

G23 G26

H21 H24

J22 J25

K23 K26

L21 L24

M22 M25

N23 N26

G4 G1

M2 M5

4 OF 4

CPU1D

A4

VSS

A8

VSS VSS VSS VSS VSS VSS VSS

B6

VSS

B8

VSS VSS VSS VSS VSS VSS VSS

C5

VSS

C8

VSS VSS VSS VSS VSS

C2

VSS VSS VSS

D1

VSS

D4

VSS

D8

VSS VSS VSS VSS VSS VSS VSS

E3

VSS

E6

VSS

E8

VSS VSS VSS VSS VSS VSS VSS

F5

VSS

F8

VSS VSS VSS VSS VSS

F2

VSS VSS VSS VSS VSS VSS VSS

H3

VSS

H6

VSS VSS VSS

J2

VSS

J5

VSS VSS VSS

K1

VSS

K4

VSS VSS VSS

L3

VSS

L6

VSS VSS VSS VSS VSS VSS VSS

N1

VSS

N4

VSS VSS VSS

P3

VSS

BGA479-SKT6-GPU7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

TP15

TP15 TPAD30

TPAD30

TPAD30 TP17

TP17 TP75

TP75 TPAD30

TPAD30

TP78

TP78 TPAD30

TPAD30 TP13

TP13 TPAD30

TPAD30

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

A

B

C

D

Date: Sheet of

CPU (2 of 2)

Four Peaks

E

-1M

557Friday, November 21, 2008

-1M

5

H_SWING

C158

SCD1U10V2KX-4GP

H_RCOMP

1D05V_S0

12

R153

R153 221R2F-2-GP

221R2F-2-GP

12

R147

R147 100R2F-L1-GP-U

100R2F-L1-GP-U

D D

H_SWING routing Trace width and Spacing use 10 / 20 mil

H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )

12

C C

H_RCOMP routing Trace width and Spacing use 10 / 20 mil

1 2

24D9R2F-L-GP

R144

Place them near to the chip ( < 0.5")

B B

1D05V_S0

R152

R152 1KR2F-3-GP

1KR2F-3-GP

1 2

12

R150

R150 2KR2F-3-GP

2KR2F-3-GP

4

H_AVREF

H_D#[63..0]

SCD1U16V2ZY-2GP

12

C161

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_CPURST#4 H_CPUSLP#4

AD14

AA13

AA11 AD11 AD10 AD13

AE12

AE14

AE11

AG2

M11

N12

P13

N10

Y10 Y12 Y14

AA8

AA9

AE9 AA2 AD8 AA3 AD3 AD7

AF3 AC1 AE3 AC3

AE8 AD6

C12 E11

A11 B11

F2

G8

F8 E6

G2

H6 H2 F6 D4 H3

M9

J1 J2

J6 P2 L2 R2 N9 L6

M5

J3 N2 R1 N5 N6

N8 L7

M3

Y3 Y6

Y7

W2

Y9

C5 E3

H_D#[63..0]4

3

NB1A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

HOST

1 OF 10

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

2

H_A#[35..3]

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4

H_BPRI# 4

H_BREQ#0 4

H_DEFER# 4

H_DBSY# 4

CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3

H_DPWR# 4

H_DRDY# 4 H_HIT# 4 H_HITM# 4

H_LOCK# 4 H_TRDY# 4

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

1

H_A#[35..3] 4

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

A A

5

4

3

2

Four Peaks

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (1 of 6)

Size Document Number Rev

Date: Sheet of

Cantiga (1 of 6)

Four Peaks

657Friday, November 21, 2008

1

-1M

1D05V_M3D3V_M

5

000 = FSB 1067MHz 010 = FSB 800MHz

Low = DMI x 2CFG5 (DMI select) High = DMI x 4

High = The ITPM Host Interface is disabled

Low = The ITPM Host Interface is enabled

Low = Intel Management Engine Crypto Transport Layer Security (TLS) cipher site with no confidentiality High = Intel Management Engine Crypto TLS Cipher suite with confidentiality

*

High = Normal operation:Lane Numbered in Order

High = Disabled

*

High = Dynamic ODT Enabled

High = Reverse Lanes DMI x 4 mode[MCH->ICH]: (0->3, 2->1, 1->2 and 0->3) DMI x 2 mode[MCH->ICH]: (3->0, 2->1)

Low = Only Digital Display Port (SDVO/iHDMI) or PCIE is operational High = Digital Display Port (SDVO/DP/iHDMI) and PCIE are operating simulatneously via the PEG port

Low = No SDVO Card Present High = SDVO Card Present

Low = LFP Disabled High = LFP Card Present; PCIE disabled

Low = DisplayPort Disabled High = DisplayPort Device Present

1D5V_S3

CFG18 CFG19 CFG20 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

12

80D6R2F-L-GP

U66

DY

1

CS#

VCC

2

SO

HOLD#

3

WP#

SCLK

4

GND

MX25L2005MC-15G-GP

R186

R186 80D6R2F-L-GP

80D6R2F-L-GP

R182

SI

-1 0425

8 7 6 5

M_RCOMPP

M_RCOMPN

PLT_RST1#20,34,36,41,42,44,46

PM_THRMTRIP-A#4,19,47

PM_DPRSLPVR20,49

*

H_DPRSTP#4,19,49

PM_EXTTS#012,13

PWROK20,47

011 = FSB 667MHz Others = Reserved

*

PM_SYNC#20

R215

1 2

0R0402-PAD

SC100P50V2JN-3GP

TP123TPAD30 TP123TPAD30

*

-1

12

R149100R2J-2-GP R149100R2J-2-GP C159

C159

DY

R172

1 2

0R0402-PAD

TP102 TPAD30TP102 TPAD30 TP103 TPAD30TP103 TPAD30 TP104 TPAD30TP104 TPAD30 TP106 TPAD30TP106 TPAD30

*

CPU_SEL03,4 CPU_SEL13,4 CPU_SEL23,4

PM_EXTTS#1 PWROK_GD

RSTIN# NB_THERMTRIP#

12

-1

CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9

CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

Strap Pin Table

CFG[2:0] FSB Freq select

CFG4:3; 8; 11; 14:15; 17; 18 Reserved

CFG6 (ITPM Host Interface)

CFG7 (Intel Management Engine Crypto Strap)

D D

CFG9 (PCIE Graphics Lane) Low = Reverse Lanes, 15->0, 14->1 etc...

CFG10 (PCIE Loopback enable) Low = Enabled

CFG12 (ALLZ) Low = ALLZ mode Enabled

CFG13 (XOR) Low = XOR mode Enabled

CFG16 (FSB Dynamic ODT) Low = Dynamic ODT Disabled

CFG19 (DMI Lane Reversal) Low = Noraml operation: Lane Numbered in Order

CFG20 (Digital Display Port (SDVO/DP /iHDMI) Concurrent with PCIE)

SDVO_CTRLDATA (SDVO Present) L_DDC_DATA (Local Flat Panel (LFP) Present) DDPC_CTRLDATA (Digital Display Present)

C C

3D3V_S0

R187 2K21R2F-GP

1 2

DY

R185 4K02R2F-GP

1 2

DY

R193 4K02R2F-GP

1 2

DY

R159 2K21R2F-GP

1 2

DY

R174 2K21R2F-GP

1 2

DY

R547 2K21R2F-GP

1 2

DY

R180 2K21R2F-GP

1 2

DY

R168 2K21R2F-GP

1 2

DY

R166 2K21R2F-GP

1 2

DY

R176 2K21R2F-GP

1 2

DY

R173 2K21R2F-GP

1 2

DY

R171 2K21R2F-GP

1 2

DY

R170 2K21R2F-GP

1 2

DY

R175 2K21R2F-GP

1 2

DY

R165 2K21R2F-GP

1 2

DY

R162 2K21R2F-GP

1 2

DY

B B

DY

R167 2K21R2F-GP

1 2

DY

R169 2K21R2F-GP

1 2

DY

-1

A A

5

CLK_MCH_OE#

LCTLA_CLK LCTLB_DATA

PM_EXTTS#0 PM_EXTTS#1

ME_TCK ME_TDI ME_TDO ME_TMS

DY

1 2

10KR2J-3-GP

RN17

4

SRN10KJ-5-GP

SRN10KJ-5-GP RN18

RN18

4

SRN10KJ-5-GP

NB1B

M36

RESERVED#M36

N36

RESERVED#N36

R33

RESERVED#R33

T33

RESERVED#T33

AH9

RESERVED#AH9

AH10

RESERVED#AH10

AH12

RESERVED#AH12

AH13

RESERVED#AH13

K12

RESERVED#K12

AL34

RESERVED#AL34

AK34

RESERVED#AK34

AN35

RESERVED#AN35

AM35

RESERVED#AM35

T24

RESERVED#T24

B31

RESERVED#B31

B2

RESERVED#B2

M1

RESERVED#M1

AY21

RESERVED#AY21

BG23

RESERVED#BG23

BF23

RESERVED#BF23

BH18

RESERVED#BH18

BF18

RESERVED#BF18

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC#BG48

BF48

NC#BF48

BD48

NC#BD48

BC48

NC#BC48

BH47

NC#BH47

BG47

NC#BG47

BE47

NC#BE47

BH46

NC#BH46

BF46

NC#BF46

BG45

NC#BG45

BH44

NC#BH44

BH43

NC#BH43

BH6

NC#BH6

BH5

NC#BH5

BG4

NC#BG4

BH3

NC#BH3

BF3

NC#BF3

BH2

NC#BH2

BG2

NC#BG2

BE2

NC#BE2

BG1

NC#BG1

BF1

NC#BF1

BD1

NC#BD1

BC1

NC#BC1

F1

NC#F1

A47

NC#A47

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

R197

3D3V_S0

UMA

1 23

4

3D3V_S0

4

2 OF 10

AP24 AT21 AV24 AU20

AR24 AR21 AU24 AV20

BC28 AY28 AY36 BB36

BA17 AY16 AV16 AR13

BD17 AY17 BF15 AY13

M_RCOMPP

BG22

M_RCOMPN

BH21

SM_RCOMP_VOH

BF28

SM_RCOMP_VOL

BH28 AV42

AR36

SM_REXT

BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

GFXVR_EN

C34

AH37 AH36

CLPWROK_R

AN36 AJ35

MCH_CLVREF

AH34

for HDMI port C

N28 M28 G36 E36 K36 H36

MCH_TSATN#

B12

B28 B30 B29 C29 A28

MCH_TSATN# 41

GFXVR_EN 53

M_CLK_DDR0 12 M_CLK_DDR1 12 M_CLK_DDR2 13 M_CLK_DDR3 13

M_CLK_DDR#0 12 M_CLK_DDR#1 12 M_CLK_DDR#2 13 M_CLK_DDR#3 13

M_CKE0 12 M_CKE1 12 M_CKE2 13 M_CKE3 13

M_CS0# 12 M_CS1# 12 M_CS2# 13 M_CS3# 13

M_ODT0 12 M_ODT1 12 M_ODT2 13 M_ODT3 13

R164 499R2F-2-GPR164 499R2F-2-GP

1 2

DREFCLK# 3

DREFSSCLK# 3

CLK_MCH_3GPLL 3

CLK_MCH_3GPLL# 3

DMI_TXN0 20 DMI_TXN1 20 DMI_TXN2 20 DMI_TXN3 20

DMI_TXP0 20 DMI_TXP1 20 DMI_TXP2 20 DMI_TXP3 20

DMI_RXN0 20 DMI_RXN1 20 DMI_RXN2 20 DMI_RXN3 20

DMI_RXP0 20 DMI_RXP1 20 DMI_RXP2 20 DMI_RXP3 20

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4

R211

1 2

0R2J-2-GP

DREFCLK 3

DREFSSCLK 3

GMCH_HDMI_CLK 18

GMCH_HDMI_DATA 18 CLK_MCH_OE# 3 MCH_ICH_SYNC# 20

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0

SB_CK#_1 SA_CKE_0

SA_CKE_1 SB_CKE_0

RSVD

SB_CKE_1 SA_CS#_0

SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1

DMI

GRAPHICS VID

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

NC

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

1D05V_S0

12

R155

56R2J-4-GP

GFXVR_EN

1 2

DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

R553

R553 100KR2F-L1-GP

100KR2F-L1-GP

CFG

PM

MCH_TSATN#

3

SM_PWROK 47

0.75V

DDR3_DRAMRST# 12,13

GFX_VID[4..0] 53

CL_CLK0 20

CL_DATA0 20 M_PWROK 20,47 CL_RST#0 20

C215

-1

R196 1KR2F-3-GPR196 1KR2F-3-GP

12

R188

R188 3K01R2F-3-GP

3K01R2F-3-GP

12

R184

R184 1KR2F-3-GP

1KR2F-3-GP

1 2

3

DDR_VREF_S3

12

C221

SCD1U10V2KX-4GP

GMCH_DDCCLK17 GMCH_DDCDATA17

1D05V_M

R203

R203 1KR2F-3-GP

1KR2F-3-GP

1 2

12

R212

499R2F-2-GP

FOR Cantiga:500 ohm Teenah: 392 ohm

SCD1U10V2KX-4GP

1D5V_S3

C203

C203 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

C197

C197 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

12

layout take note

L_BKLTCTL15 GMCH_BL_ON41

CLK_DDC_EDID15 DAT_DDC_EDID15

GMCH_LCDVDD_ON15

R208

0R2J-2-GP

UMA

GMCH_BLUE44

GMCH_GREEN44

GMCH_RED44

GMCH_HSYNC17 GMCH_VSYNC17

SM_RCOMP_VOH

C205

C205 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SM_RCOMP_VOL

C201

C201 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

LCTLA_CLK

LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID

GMCH_LCDVDD_ON

LIBG L_LVBG

TP110TPAD30 TP110TPAD30

12

GMCH_TXACLK-15 GMCH_TXACLK+15 GMCH_TXBCLK-15 GMCH_TXBCLK+15

GMCH_TXAOUT0-15 GMCH_TXAOUT1-15 GMCH_TXAOUT2-15

GMCH_TXAOUT0+15 GMCH_TXAOUT1+15 GMCH_TXAOUT2+15

GMCH_TXBOUT0-15 GMCH_TXBOUT1-15 GMCH_TXBOUT2-15

GMCH_TXBOUT0+15 GMCH_TXBOUT1+15 GMCH_TXBOUT2+15

TV_DACA

TV_DACB

TV_DACC

GMCH_BLUE GMCH_GREEN GMCH_RED

GMCH_DDCCLK GMCH_DDCDATA

GMCH_HS

1 2

UMA

R199 33R2F-3-GP

GMCH_VS

1 2

UMA

R194 33R2F-3-GP

CRT_IREF

1 2

UMA

R192 1K02R2F-1-GP

FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm

CRT_IREF routing Trace width use 20 mil

DREFCLK DREFCLK#

DREFSSCLK DREFSSCLK#

NB1C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

SRN0J-6-GP

1 2 3

RN49

DIS

SRN0J-6-GP

1 2 3

RN50

DIS

2

R204 49D9R2F-GPR204 49D9R2F-GP

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

1 2 1 2 1 2 1 2 1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2 1 2 1 2 1 2 1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

0R2J-2-GP

R210

1D05V_S0

Close to GMCH as 500 mils.

12

C243 SCD1U10V2KX-5GPC243 SCD1U10V2KX-5GP C619 SCD1U10V2KX-5GPC619 SCD1U10V2KX-5GP C617 SCD1U10V2KX-5GPC617 SCD1U10V2KX-5GP C245 SCD1U10V2KX-5GPC245 SCD1U10V2KX-5GP C250 SCD1U10V2KX-5GP

C250 SCD1U10V2KX-5GP C616 SCD1U10V2KX-5GP

C616 SCD1U10V2KX-5GP C253 SCD1U10V2KX-5GP

C253 SCD1U10V2KX-5GP C241 SCD1U10V2KX-5GP

C241 SCD1U10V2KX-5GP C229 SCD1U10V2KX-5GP

C229 SCD1U10V2KX-5GP C231 SCD1U10V2KX-5GP

C231 SCD1U10V2KX-5GP C232 SCD1U10V2KX-5GP

C232 SCD1U10V2KX-5GP C613 SCD1U10V2KX-5GP

C613 SCD1U10V2KX-5GP C235 SCD1U10V2KX-5GP

C235 SCD1U10V2KX-5GP C237 SCD1U10V2KX-5GP

C237 SCD1U10V2KX-5GP C238 SCD1U10V2KX-5GP

C238 SCD1U10V2KX-5GP C612 SCD1U10V2KX-5GP

C612 SCD1U10V2KX-5GP C244 SCD1U10V2KX-5GPC244 SCD1U10V2KX-5GP

C620 SCD1U10V2KX-5GPC620 SCD1U10V2KX-5GP C618 SCD1U10V2KX-5GPC618 SCD1U10V2KX-5GP C246 SCD1U10V2KX-5GPC246 SCD1U10V2KX-5GP C251 SCD1U10V2KX-5GP

C251 SCD1U10V2KX-5GP C615 SCD1U10V2KX-5GP

C615 SCD1U10V2KX-5GP C252 SCD1U10V2KX-5GP

C252 SCD1U10V2KX-5GP C242 SCD1U10V2KX-5GP

C242 SCD1U10V2KX-5GP C228 SCD1U10V2KX-5GP

C228 SCD1U10V2KX-5GP C230 SCD1U10V2KX-5GP

C230 SCD1U10V2KX-5GP C233 SCD1U10V2KX-5GP

C233 SCD1U10V2KX-5GP C614 SCD1U10V2KX-5GP

C614 SCD1U10V2KX-5GP C234 SCD1U10V2KX-5GP

C234 SCD1U10V2KX-5GP C236 SCD1U10V2KX-5GP

C236 SCD1U10V2KX-5GP C239 SCD1U10V2KX-5GP

C239 SCD1U10V2KX-5GP C611 SCD1U10V2KX-5GP

C611 SCD1U10V2KX-5GP

UMA

3 OF 10

PEG_CMP

T37

PEG_COMPI

T36

PEG_COMPO

H44

PEG_RX#_0

J46

PEG_RX#_1

L44

PEG_RX#_2

L40

PEG_RX#_3

N41

PEG_RX#_4

P48

PEG_RX#_5

N44

PEG_RX#_6

T43

PEG_RX#_7

U43

PEG_RX#_8

Y43

PEG_RX#_9

Y48

PEG_RX#_10

Y36

PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

GTXN0 GTXN1 GTXN2 GTXN3 GTXN4 GTXN5 GTXN6 GTXN7 GTXN8 GTXN9 GTXN10 GTXN11 GTXN12 GTXN13 GTXN14 GTXN15

GTXP0 GTXP1 GTXP2 GTXP3 GTXP4 GTXP5 GTXP6 GTXP7 GTXP8 GTXP9 GTXP10 GTXP11 GTXP12 GTXP13 GTXP14 GTXP15

PEG_RXP3

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

-1

4

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

1

PEG_RXN[15..0] 46

PEG_RXP[15..0] 46

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

DVI_DETECT# 18

GMCH_BL_ON

GMCH_LCDVDD_ON

LIBG

CRT_IREF

GMCH_VS

GMCH_HS

GMCH_BLUE

GMCH_GREEN

GMCH_RED

FOR Discrete,change to 0 ohm

63.R0034.1DL

R177

75R2J-1-GP

1 2

UMA

R178

75R2J-1-GP

1 2

UMA

R179

75R2J-1-GP

1 2

UMA

Cantiga (2 of 6)

Four Peaks

1

PEG_TXN[15..0] 18,46

PEG_TXP[15..0] 18,46

UMA

R200

1 2

100KR2J-1-GP

UMA

R201

1 2

100KR2J-1-GP

UMA

R216

1 2

2K37R2F-GP

DIS

R195

1 2

0R2J-2-GP

R198

1 2

0R2J-2-GP

DIS

R202

1 2

0R2J-2-GP

DIS

R189

UMA

150R2F-1-GP

1 2

R190

UMA

150R2F-1-GP

1 2

R191

UMA

150R2F-1-GP

1 2

TV_DACA

TV_DACB

TV_DACC

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

757Friday, November 21, 2008

-1M

of

5

NB1D

M_A_DQ[63..0]12

D D

C C

B B

M_A_DQ[63..0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

NB1D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

DDR SYSTEM MEMORY A

4 OF 10

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

4

BD21 BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6

M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8

M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_DM[7..0]

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_BS#0 12 M_A_BS#1 12 M_A_BS#2 12

M_A_RAS# 12

M_A_CAS# 12

M_A_WE# 12

M_A_DM[7..0] 12

M_A_DQS[7..0] 12

M_A_DQS#[7..0] 12

M_A_A[14..0] 12

3

NB1E

M_B_DQ[63..0]13

M_B_DQ[63..0]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

NB1E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

2

5 OF 10

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

M_B_DM0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8

M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_DM[7..0]

M_B_DQS[7..0]

M_B_DQS#[7..0]

M_B_A[14..0]

M_B_RAS# 13 M_B_CAS# 13 M_B_WE# 13

1

M_B_BS#0 13 M_B_BS#1 13 M_B_BS#2 13

M_B_DM[7..0] 13

M_B_DQS[7..0] 13

M_B_DQS#[7..0] 13

M_B_A[14..0] 13

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

Cantiga (3 of 6)

Four Peaks

857Friday, November 21, 2008

1

-1M

5

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

VCC_GFXCORE

SM_LF1_GMCH SM_LF2_GMCH SM_LF3_GMCH SM_LF4_GMCH SM_LF5_GMCH SM_LF6_GMCH SM_LF7_GMCH

7 OF 10

1D5V_S3

D D

VCC_GFXCORE

C C

B B

VCC_AXG_SENSE53 VSS_AXG_SENSE53

U60(ISL6263ACRZ-T-GP) place near Cantiga

NB1G

AP33

VCC_SM

AN33

VCC_SM

BH32

VCC_SM

BG32

VCC_SM

BF32

VCC_SM

BD32

VCC_SM

BC32

VCC_SM

BB32

VCC_SM

BA32

VCC_SM

AY32

VCC_SM

AW32

VCC_SM

AV32

VCC_SM

AU32

VCC_SM

AT32

VCC_SM

AR32

VCC_SM

AP32

VCC_SM

AN32

VCC_SM

BH31

VCC_SM

BG31

VCC_SM

BF31

VCC_SM

BG30

VCC_SM

BH29

VCC_SM

BG29

VCC_SM

BF29

VCC_SM

BD29

VCC_SM

BC29

VCC_SM

BB29

VCC_SM

BA29

VCC_SM

AY29

VCC_SM

AW29

VCC_SM

AV29

VCC_SM

AU29

VCC_SM

AT29

VCC_SM

AR29

VCC_SM

AP29

VCC_SM

BA36

VCC_SM/NC

BB24

VCC_SM/NC

BD16

VCC_SM/NC

BB21

VCC_SM/NC

AW16

VCC_SM/NC

AW13

VCC_SM/NC

AT13

VCC_SM/NC

Y26

VCC_AXG

AE25

VCC_AXG

AB25

VCC_AXG

AA25

VCC_AXG

AE24

VCC_AXG

AC24

VCC_AXG

AA24

VCC_AXG

Y24

VCC_AXG

AE23

VCC_AXG

AC23

VCC_AXG

AB23

VCC_AXG

AA23

VCC_AXG

AJ21

VCC_AXG

AG21

VCC_AXG

AE21

VCC_AXG

AC21

VCC_AXG

AA21

VCC_AXG

Y21

VCC_AXG

AH20

VCC_AXG

AF20

VCC_AXG

AE20

VCC_AXG

AC20

VCC_AXG

AB20

VCC_AXG

AA20

VCC_AXG

T17

VCC_AXG

T16

VCC_AXG

AM15

VCC_AXG

AL15

VCC_AXG

AE15

VCC_AXG

AJ15

VCC_AXG

AH15

VCC_AXG

AG15

VCC_AXG

AF15

VCC_AXG

AB15

VCC_AXG

AA15

VCC_AXG

Y15

VCC_AXG

V15

VCC_AXG

U15

VCC_AXG

AN14

VCC_AXG

AM14

VCC_AXG

U14

VCC_AXG

T14

VCC_AXG

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

POWER

VCC SMVCC GFX

7 OF 10

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC GFX NCTF

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

VCC SM LF

4

R158

R158 0R5J-5-GP

0R5J-5-GP

DIS

1 2

VCC_GFXCORE

12

TC13

ST220U2D5VBM-2GP

DY

UMA

Place on the Edge Coupling CAP

12

C153

C162

C180

SCD1U10V2KX-4GP

place near Cantiga

3

1D05V_M

12

C211

SC10U6D3V5MX-3GP

Coupling CAP 370 mils from the Edge

12

C178

C167

C179

SC10U6D3V5MX-3GP

UMA

12

C188

C190

SC10U6D3V5MX-3GP

UMA

SC10U6D3V5MX-3GP

UMA

SC10U6D3V5MX-3GP

-1 04/25

SCD1U10V2KX-4GP

C206

12

DY

C191

SC1U10V3ZY-6GP

SCD1U10V2KX-4GP

UMA

FOR VCC SM

SCD1U10V2KX-4GP

C207

C210

12

DY

UMA

12

C175

C189

SCD1U10V2KX-4GP

UMA

SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP

C204

12

1D5V_S3

SC10U6D3V5MX-3GP

C171

12

Place on the Edge

SCD47U16V3ZY-3GP

12

C185

SCD22U10V2KX-1GP

12

C218

C216

C227

SC1U10V3KX-3GP

2

FOR VCC CORE

12

C199

SC10U6D3V5MX-3GP

C212

SC10U6D3V5MX-3GP

12

Coupling CAP

C195

SCD22U10V2KX-1GP

C202

12

DY

12

C208

SCD1U10V2KX-4GP

DY

SCD1U10V2KX-4GP

G32

1 2

GAP-CLOSE-PWR

12

C186

SCD1U10V2KX-4GP

VCC_GMCH_35

NB1F

AG34

VCC

AC34

VCC

AB34

VCC

AA34

VCC

Y34

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33

VCC

AC33

VCC

AA33

VCC

Y33

VCC

W33

VCC

V33

VCC

U33

VCC

AH28

VCC

AF28

VCC

AC28

VCC

AA28

VCC

AJ26

VCC

AG26

VCC

AE26

VCC

AC26

VCC

AH25

VCC

AG25

VCC

AF25

VCC

AG24

VCC

AJ23

VCC

AH23

VCC

AF23

VCC

T32

VCC

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

VCC CORE

POWER

6 OF 10

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

VCC NCTF

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

1

1D05V_M

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga (4 of 6)

Four Peaks

1

957Friday, November 21, 2008

-1M

of

5

5V_S0

SC1U16V3ZY-GP

12

BC5

UMA

D D

1D05V_M

C C

R502

R502 0R0603-PAD

0R0603-PAD

1 2

FCM1608KF-1-GP

1 2

L23

120ohm 100MHz

FCM1608KF-1-GP

1 2

L22

120ohm 100MHz

1D05V_M

B B

1 2

BLM18BB221SN1D-GP

220ohm 100MHz

1D5V_S0

1 2

0R0402-PAD

A A

180ohm 100MHz

Imax = 300 mA

U57

UMA

1

VIN

2

GND EN/EN#3NC#4

RT9198-33PBR-GP

74.09198.G7F

2nd = 74.09091.J3F

65mA

R595

12

0R3-0-U-GP

UMA

65mA

R593

12

0R3-0-U-GP

UMA

-1

1D05V_SUS_MCH_PLL2

L9

-1

R181

L7

1 2

HCB1608K-181T20GP

UMA

12

UMA

5

VOUT

4

SC10U6D3V5MX-3GP

12

C630

UMA

SC10U6D3V5MX-3GP

12

C631

UMA

M_VCCA_HPLL

12

C510

M_VCCA_MPLL

12

C502

1D05V_RUN_PEGPLL

12

C249

C249 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5VRUN_TVDAC

C192

SCD01U16V2KX-3GP

12

C198

SCD01U16V2KX-3GP

UMA

5

3D3V_S0_DAC

BC6

SC1U16V3ZY-GP

M_VCCA_DPLLA

SCD1U10V2KX-4GP

12

C625

UMA

M_VCCA_DPLLB

SCD1U10V2KX-4GP

12

C629

UMA

24mA

SC4D7U6D3V3KX-GP

12

C515

C515 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

12

1D5VRUN_QDAC

12

C194

SCD1U10V2KX-4GP

UMA

C549

SC22U6D3V5MX-2GP

12

UMA

12

R589

R589 0R2J-2-GP

0R2J-2-GP

DIS

12

R592

R592 0R2J-2-GP

0R2J-2-GP

DIS

139.2mA

12

C514

C514 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

58.7mA

C187

SCD1U10V2KX-4GP

12

R183

0R2J-2-GP

DIS

3D3V_S0_DAC

0R3-0-U-GP

SC

3D3V_S0_DAC

R539

1 2

BLM18HG102SN-1GP

UMA

68.00084.A01

1D5V_S0

1D05V_M

480mA

24mA

1D05V_SUS_MCH_PLL2

SCD1U10V2KX-4GP

12

C516

R540

12

UMA

5mA

C567

UMA

SC1KP50V2KX-1GP

1 2

0R0402-PAD

C200

SC10U6D3V5MX-3GP

12

DY

1D05V_M

157.2mA

1D8V_S0

60.3mA

4

SCD01U16V2KX-3GP

C572

C568

12

UMA

12

R542

R542 0R2J-2-GP

0R2J-2-GP

DIS

SC2D2U10V3KX-1GP

1D8V_TXLVDS_S0

C225

-1

R590

C559

12

DY

SC10U6D3V5MX-3GP

12

C628

C626

DY

3D3V_S0_DAC

0R2J-2-GP

R205

R205 0R2J-2-GP

0R2J-2-GP

1 2

R220

1 2

0R2J-2-GP

UMA

4

3D3V_CRTDAC_S0

SCD1U10V2KX-4GP

12

UMA

VCCA_PEG_BG

12

C624

C624 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C193

SC4D7U6D3V3KX-GP

12

DY

SC2D2U6D3V3MX-1-GP

12

C621

R534

1 2

UMA

R538

DIS

C247

50mA

1D8V_SUS_DLVDS

12

R543

R543 0R2J-2-GP

0R2J-2-GP

DIS

M_VCCA_DAC_BG

M_VCCA_DPLLA M_VCCA_DPLLB M_VCCA_HPLL M_VCCA_MPLL

13.2mA

1D05V_RUN_PEGPLL

SC1U10V3KX-3GP

SCD1U10V2KX-4GP

12

VCC_HDA

1D5VRUN_TVDAC 1D5VRUN_QDAC

1D05V_RUN_PEGPLL

12

SCD1U10V2KX-4GP

12

C217

SCD1U10V2KX-4GP

UMA

C240

SC10U6D3V5MX-3GP

50mA

UMA

AD48

AA48

AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16

AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25

AM24 AM23

AA47

12

R209

R209 0R2J-2-GP

0R2J-2-GP

DIS

AD1 AE1

AL25 AL24 AL23

M25

M38

B27 A26

A25 B25

F47 L48

J48 J47

B24 A24

A32

L28 AF1

L37

3

NB1H

VCCA_CRT_DAC VCCA_CRT_DAC

VCCA_DAC_BG VSSA_DAC_BG

VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL

VCCA_LVDS VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM

VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF

VCCA_TV_DAC VCCA_TV_DAC

VCC_HDA

VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL

VCCD_LVDS VCCD_LVDS

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

3

CRTPLLA PEGA SM

A LVDS

POWER

A CK

TV

HDA

D TV/CRT

LVDS

AXF

VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK

SM CK

VCC_TX_LVDS

HV

PEG

DMI

VTTLF

8 OF 10

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

VTT

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

VCC_AXF VCC_AXF VCC_AXF

VCC_HV VCC_HV VCC_HV

VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG

VCC_DMI VCC_DMI VCC_DMI VCC_DMI

VTTLF VTTLF VTTLF

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47 C35

B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

106mA

VTTLF1 VTTLF2 VTTLF3

1

2

12

C138

C169

SC4D7U6D3V3KX-GP

322mA

12

C84

1D8V_TXLVDS_S0

3D3V_HV_S0

1782mA

12

C176

456mA

1

C149

C146

2

SCD47U6D3V2KX-GP

2

1

1D05V_S0

852mA73mA

12

SC4D7U6D3V3KX-GP

SC1U10V3KX-3GP

12

SC4D7U6D3V3KX-GP

1

C160

2

C174

SC2D2U6D3V3MX-1-GP

1D05V_S0

BAT54-7-F-GP

1D05V_M

SC10U6D3V5MX-3GP

12

C85

SCD1U10V2KX-4GP

C181

C226

SC1KP50V2KX-1GP

C226

SC1KP50V2KX-1GP

12

C196

12

C623

SCD47U6D3V2KX-GP

1

C132

C165

2

SC4D7U6D3V3KX-GP

SCD47U6D3V2KX-GP

D40

1

3

2nd = 83.BAT54.D81

200mA

R160

1 2

1R2F-GP

119mA

12

UMA

1D05V_M

SC10U6D3V5MX-3GP

12

C184

SCD1U10V2KX-4GP

12

C562

Title

Size Document Number Rev

Date: Sheet of

12

2

C622

SC1U10V3KX-3GP

C622

SC1U10V3KX-3GP

SC10U6D3V5MX-3GP

C152

TC12

DY

SCD1U10V2KX-4GP

ST220U6D3VDM-20GP

2nd = 80.22715.39L

1D05V_HV_S0

1D5V_S3

1D5V_SUS_SM_CK_RC

12

UMA

SC10U6D3V5MX-3GP

12

C173

12

C627

3D3V_S0 3D3V_HV_S0

R558

12

1 2

R559

0R0402-PAD

10R2J-2-GP

12

R585

R585 0R2J-2-GP

0R2J-2-GP

DIS

1D05V_M

SC10U6D3V5MX-3GP

Cantiga (5 of 6)

Four Peaks

0R0402-PAD

C177

1 2

SC10U6D3V5MX-3GP

1D8V_S0

R594

R594 0R3-0-U-GP

0R3-0-U-GP

12

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

10 57Friday, November 21, 2008

1

-1

SCD1U10V2KX-4GP

12

C588

-1M

5

NB1I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

VSS

AD47

VSS

AB47

VSS

D D

C C

B B

A A

5

Y47

VSS

T47

VSS

N47

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

VSS

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

4

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

4

3

10 OF 10

NB1J

BG21

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

R17 M17 H17 C17

BA16

AU16 AN16

N16 K16 G16

E16 BG15 AC15

W15

A15 BG14

AA14

C14 BG13 BC13

BA13

AN13

AJ13

AE13

N13

L13 G13 E13

BF12 AV12 AT12

AM12

AA12

J12 A12

BD11

BB11

AY11 AN11 AH11

Y11 N11 G11 C11

BG10

AV10

AT10

AJ10 AE10 AA10

M10 BF9 BC9 AN9

AM9

AD9

G9

B9 BH8 BB8 AV8 AT8

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

3

VSS VSS VSS VSS

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

NCTF_VSS_SCB#BH48

NCTF_VSS_SCB#BH1

NCTF TEST PIN:

A3,C1,A48,BH1,BH48

NCTF TEST PIN:

A3,C1,A48,BH1,BH48

VSS SCB

10 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS NCTF

VSS_NCTF VSS_NCTF

NCTF_VSS_SCB#A48

NCTF_VSS_SCB#C1

NCTF_VSS_SCB#A3

NC#E1 NC#D2 NC#C3 NC#B4 NC#A5

NC#A6 NC#A43 NC#A44 NC#B45 NC#C46

NC

NC#D47 NC#B47 NC#A46 NC#F48 NC#E48 NC#C48 NC#B48

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

2

TP178 TPAD30TP178 TPAD30

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Cantiga (6 of 6)

Four Peaks

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1M

11 57Friday, November 21, 2008

1

-1M

A

B

C

D

E

DDR3 SOCKET_1

4 4

DM1

M_A_A[14..0]8

TP96TP96

M_A_BS#28 M_A_BS#08

M_A_BS#18

M_A_DQ[63..0]8

3 3

2 2

Layout Note：Near Pin 126

DDR_VREF_S3

12

C143

SC2D2U6D3V3MX-1-GP

C140

C140 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

：

DDR_VREF_S3

C220

A

Near Pin 1

12

SC2D2U6D3V3MX-1-GP

12

C224

C224 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Layout Note

1 1

M_A_DQS#[7..0]8

M_A_DQS[7..0]8

DDR_VREF_S3

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_ODT07 M_ODT17

DDR_VREF_S3 DDR_VREF_S3

DDR3_DRAMRST#7,13

12

C100

C96

SC1U10V3ZY-6GP

B

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

SC10U6D3V5MX-3GP

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-9-GP

62.10017.G11

High 5.2mm

RAS# CAS#

CKE0 CKE1

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115 114

CS0#

121

CS1#

73 74

101

CK0

103

CK0#

102

CK1

104

CK1#

M_A_DM0

11

DM0

M_A_DM1M_A_DM1

28

DM1

M_A_DM2M_A_DM2

46

DM2

M_A_DM3M_A_DM3

63

DM3

M_A_DM4M_A_DM4

136

DM4

M_A_DM5M_A_DM5

153

DM5

M_A_DM6M_A_DM6

170

DM6

M_A_DM7M_A_DM7

187

DM7

SMBD_ICH

200

SDA

SMBC_ICH

202

SCL

198 199

DDRA_SA0

197

SA0

DDRA_SA1

201

SA1

77 122

1D5V_S3

125 75

76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

C

M_A_RAS# 8 M_A_WE# 8 M_A_CAS# 8

M_CS0# 7 M_CS1# 7

M_CKE0 7 M_CKE1 7

M_CLK_DDR0 7 M_CLK_DDR#0 7

M_CLK_DDR1 7 M_CLK_DDR#1 7

SMBD_ICH 3,13,22 SMBC_ICH 3,13,22

PM_EXTTS#0 7,13

RN71

2 3 1

SRN10KJ-5-GP

M_A_DM[7..0] 8

4

-1(5/9)

1D5V_S3

3D3V_M

12

C93

SC2D2U6D3V2MX-GP

C95

SCD1U16V2ZY-2GP

DY

-1 04/25

12

C507

C565

SC10U6D3V5MX-3GP

SCD1U16V2ZY-2GP

12

C156

12

C527

C172

SC10U6D3V5MX-3GP

DY

SCD1U16V2ZY-2GP

12

C151

C166

D

12

C154

C150

SC10U6D3V5MX-3GP

DY

C168

SCD1U16V2ZY-2GP

12

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

DDR3 Socket

Four Peaks

E

-1M

of

12 57Friday, November 21, 2008

of

12 57Friday, November 21, 2008

of

12 57Friday, November 21, 2008

A

B

C

D

E

4 4

M_B_A[14..0]8

M_B_BS#28 M_B_BS#08

M_B_BS#18

M_B_DQ[63..0]8

3 3

Layout Note：Near Pin 126

2 2

DDR_VREF_S3

12

C500

SC2D2U6D3V3MX-1-GP

C496

C496 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

M_B_DQS#[7..0]8

：

C219

12

SC2D2U6D3V3MX-1-GP

Near Pin 1

12

C223

C223 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

M_B_DQS[7..0]8

DDR_VREF_S3

Layout Note

DDR_VREF_S3

1 1

DDR3 SOCKET_2

DM2

M_B_A0

DDR3_DRAMRST#7,12

TP95TP95

12

M_ODT27 M_ODT37

C87

SC1U10V3ZY-6GP

M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8

M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9

M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

DDR_VREF_S3 DDR_VREF_S3

12

C90

SC10U6D3V5MX-3GP

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-8-GP

62.10017.G21

NP1

NP2

110

RAS#

113

WE#

115

CAS#

114

CS0#

121

CS1#

73

CKE0

74

CKE1

101

CK0

103

CK0#

102

CK1

104

CK1#

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

EVENT#

199

VDDSPD

197

SA0

201

SA1

77

NC#1

122

NC#2

125

NC#/TEST

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

NORMAL TYPE

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

DDRB_SA0 DDRB_SA1

1D5V_S3

10KR2J-3-GP

R113

R113 R103

R103

10KR2J-3-GP

M_B_RAS# 8 M_B_WE# 8 M_B_CAS# 8

M_CS2# 7 M_CS3# 7

M_CKE2 7 M_CKE3 7

M_CLK_DDR2 7 M_CLK_DDR#2 7

M_CLK_DDR3 7 M_CLK_DDR#3 7

M_B_DM[7..0] 8

SMBD_ICH 3,12,22 SMBC_ICH 3,12,22

PM_EXTTS#0 7,12

12 12

3D3V_M

DY

12

C105

SC2D2U6D3V2MX-GP

C111

SCD1U16V2ZY-2GP

1D5V_S3

DY

12

C164

12

C137

C163

C147

SC10U6D3V5MX-3GP

SCD1U16V2ZY-2GP

12

C148

C139

C142

SC10U6D3V5MX-3GP

SCD1U16V2ZY-2GP

DY

12

C157

12

DY

12

C155

TC22

SC10U6D3V5MX-3GP

12

C170

TC22

SC10U6D3V5MX-3GP

ST330U6VDM-2-GP

SCD1U16V2ZY-2GP

High 9.2 mm

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3 Termination Resistor

Size Document Number Rev

Date: Sheet

A

B

C

D

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Four Peaks

E

-1M

of

13 57Friday, November 21, 2008

of

13 57Friday, November 21, 2008

of

13 57Friday, November 21, 2008

5

D D

C C

4

LEFT_BTN1

1

2 4

3

RIGHT_BTN1

3 5

1

2 4

3 5

TP_RIGHT 29,41TP_LEFT 29,41

2

1

SW-TACT-122-GP

62.40009.681

62.40009.671

BlueTooth ON/OFF

BT_BTN#41

3G_BTN#41

WIRELESS_BTN#_1

SCD1U16V2ZY-2GP

4

B B

A A

5

WIRELESS_BTN#41

WLAN_BTN1

123

4

SW-SS3-CMSC-V-T-GP

62.40066.001

62.40068.001

12

EC87

EC86

DY

SCD1U16V2ZY-2GP

5

1 2 3 4 5

12

EC90

DY

SCD1U16V2ZY-2GP

RN42

SRN470J-3-GP

Check Wireless Button left or right

8 7 6

SW-TACT-122-GP

62.40009.681

62.40009.671

Wireless ON/OFF

62.40018.401

BT_BTN1

BT_BTN1 SW-SLIDE68-GP

SW-SLIDE68-GP

A

B

BLT_BTN#_1

BLT_BTN#_1 WIRELESS_BTN#_1 3G_BTN#_1

3

62.40018.411

C

D

NP1

NP2

3G_BTN#_1

RN43

1 2 3 4 5

SRN10KJ-6-GP

8 7 6

3D3V_S0

Four Peaks

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

SWITCH / Button

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

SWITCH / Button

Four Peaks

1

-1M

14 57Friday, November 21, 2008

-1M

-1 04/23

CCD1

5 1 2

3 4

6

ACES-CON4-GP-U1

20.F0714.004

20.F1000.004

CCD_PWR USBPN8

USBPP8

CCD1 Conn. Test Point

CCD_PWR USBPN8 USBPP8

1 1 1

TP225 AFTE30-GPTP225 AFTE30-GP TP227 AFTE30-GPTP227 AFTE30-GP TP228 AFTE30-GPTP228 AFTE30-GP

LCD/INVERTER/CCD CONN

LCDVDD

SCD1U16V2ZY-2GP

12

C8

TXBCLK+ TXBCLKG72_TXBOUT2+ G72_TXBOUT2G72_TXBOUT1+ G72_TXBOUT1G72_TXBOUT0+ G72_TXBOUT0TXACLK+ TXACLKG72_TXAOUT2+ G72_TXAOUT2G72_TXAOUT1+ G72_TXAOUT1G72_TXAOUT0+ G72_TXAOUT0-

SC100P50V2JN-3GPC7SC100P50V2JN-3GP

12

C7

C8

DY

-1

R9 0R2J-2-GP

R9 0R2J-2-GP R10 0R2J-2-GP

R10 0R2J-2-GP

R13 0R0402-PADR13 0R0402-PAD

1 2

R14 0R0402-PADR14 0R0402-PAD

1 2

R15 0R0402-PADR15 0R0402-PAD

1 2

R16 0R0402-PADR16 0R0402-PAD

1 2

-1(5/9)

R11 0R2J-2-GP

R11 0R2J-2-GP R12 0R2J-2-GP

R12 0R2J-2-GP

R7

DY

R8

DY

12 12

DY

Place near LCD conn.

0R2J-2-GP

0R2J-2-GP 0R2J-2-GP

0R2J-2-GP

12 12

12

R4

10KR2J-3-GPR410KR2J-3-GP

G72_TXBCLK+ 46

G72_TXBCLK- 46

G72_TXBOUT2+ 46

G72_TXBOUT2- 46

G72_TXBOUT1+ 46

G72_TXBOUT1- 46

G72_TXBOUT0+ 46

G72_TXBOUT0- 46

G72_TXACLK+ 46

G72_TXACLK- 46

G72_TXAOUT2+ 46

G72_TXAOUT2- 46

G72_TXAOUT1+ 46

G72_TXAOUT1- 46

G72_TXAOUT0+ 46

G72_TXAOUT0- 46

USBPN820

USBPP820

LCD_CB_SEL41

DCBATOUT

POLYSW-1D1A24V-GP

BRIGHTNESS_CN_L BLON_OUT_L

R2 0R2J-2-GPR2 0R2J-2-GP R1 0R2J-2-GPR1 0R2J-2-GP

LCD_EDID_CLK LCD_EDID_DAT

CCD_PWR BRIGHTNESS_CN_L

BLON_OUT_L

F2

1 2

69.50007.A31

2 3 1

USBPN8_R

12

USBPP8_R

12

3D3V_S0

C379

12

SC10U35V0ZY-GP

RN46

4

SRN33J-5-GP-U

41

2 4

6

8 10 12 14 16 18 20 22 24 26 28 30

42

BRIGHTNESS_CN

BLON_OUT

LCD1

1 3

5 7 9 11 13 15 17 19 21 23 25 27 29 3132 3334 3536 3738 3940

ACES-CONN40A-2GP

20.F0993.040

20.F1048.040

SC100P50V2JN-3GP

12

C10

L_BKLTCTL 7 BRIGHTNESS 41 BLON_OUT 41

G72_TXACLKG72_TXACLK+ G72_TXAOUT2G72_TXAOUT2+

G72_TXAOUT0G72_TXAOUT0+ G72_TXAOUT1G72_TXAOUT1+

G72_TXBCLKG72_TXBCLK+ G72_TXBOUT2G72_TXBOUT2+

G72_TXBOUT0G72_TXBOUT0+ G72_TXBOUT1G72_TXBOUT1+

RN11

1 2 3 4 5

SRN0J-7-GP

UMA

RN10

1 2 3 4 5

SRN0J-7-GP

UMA

RN5

1 2 3 4 5

SRN0J-7-GP

UMA

RN6

1 2 3 4 5

SRN0J-7-GP

UMA

Inverter Pin Pin

8 7 6

GMCH_TXACLK- 7

GMCH_TXACLK+ 7

GMCH_TXAOUT2- 7

GMCH_TXAOUT2+ 7

GMCH_TXAOUT0- 7

GMCH_TXAOUT0+ 7

GMCH_TXAOUT1- 7

GMCH_TXAOUT1+ 7

GMCH_TXBCLK- 7

GMCH_TXBCLK+ 7

GMCH_TXBOUT2- 7

GMCH_TXBOUT2+ 7

Symbol 1 2 3 4 5 6

CCD Pin Pin

Symbol 1

Vin Vin PWM BLON GND GND

GND

2 GND

5V

8 7 6

GMCH_TXBOUT0- 7

GMCH_TXBOUT0+ 7

GMCH_TXBOUT1- 7

GMCH_TXBOUT1+ 7

3 4

USB-

5

USB+

LCDVDD_ON

DY

3D3V_S0

12

DY

12

C672

SC10U10V5KX-2GP

DY

1 2

R251

PGOOD

GND

EN

ADJ

VIN

VOUT

VDD4NC#5

GND

9

R251 330R2J-3-GP

330R2J-3-GP

RT9025-25PSP-GP

74.09025.03D

R348

100KR2J-1-GP

U67

1 2 3

DY

Vout = 0.8 x (R1+R2)/R2 = 3.44V

-1M(5/27)

GMCH_LCDVDD_ON7

R599

R599 100R2F-L1-GP-U

100R2F-L1-GP-U

8 7 6 5

3D3V_S0

SC1U10V3ZY-6GPC6SC1U10V3ZY-6GP

LCDVDD

12

C6

3D3V_S0

Layout 40 mil

SCD1U16V2ZY-2GP

12

C5

DY

U1

1

IN#1

2

OUT

3

EN

4

GND

G5281RC1U-GP

GND IN#8 IN#7 IN#6 IN#5

9 8 7 6 5

-1

C4

SC4D7U10V5ZY-3GPC4SC4D7U10V5ZY-3GP

12

LCD_EDID_CLK46 LCD_EDID_DAT46

CLK_DDC_EDID7 DAT_DDC_EDID7

SRN0J-6-GP

1

4

2 3

RN51

UMA

Four Peaks

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

LCD CONN

UMA

1 2

R5 0R2J-2-GP

LCDVDD_ON46

DY

12

DY

LCDVDD5V_S0

12

C464

SC10U10V5KX-2GP

CCD_PWR

12

C377

12

C378

SC4D7U10V5ZY-3GP

SCD1U16V2ZY-2GP

DIS

R3

R3 10KR2J-3-GP

10KR2J-3-GP

1 2

F1

FUSE-1A6V-2-GP

1

23

SRN2K2J-1-GP

SRN2K2J-1-GP RN26

RN26

4

LCD_EDID_CLK LCD_EDID_DAT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Four Peaks

of

15 57Friday, November 21, 2008

-1M

5

FRONT_PWRLED#_Q

EBC

Q4

DDTC143ZUA-7-F-GP

D D

Q4

R2

R1

4

-1

1 2

R81 75R2J-1-GPR81 75R2J-1-GP

R80

1 2

100R2J-2-GP

FRONT_PWRLED#_E 31

LED

3D3V_S5

3

2

DDTC143ZUA-7-F-GP

Q47

R2

EBC

R1

-1

1 2

R629 1K13R2F-1-GPR629 1K13R2F-1-GP

BLT_LED#_1_R

1

SB

BT_LED1

AK

LED-B-77-GP-U2

83.01221.I70

Blue-tooth LED

5V_S0

FRONT_PWRLED41

FRONT_PWRLED#_R

R75

STDBY_LED#_Q

EBC

Q2

DDTC143ZUA-7-F-GP

STDBY_LED41

C C

DC_BATFULL41

CHARGE_LED41

DDTC143ZUA-7-F-GP

Q2

Q45

Q46

R2

EBC

R1

1 2

R76 75R2J-1-GPR76 75R2J-1-GP

R625

1 2

R626

1 2

100R2J-2-GP

-1

100R2J-2-GP

STDBY_LED#_R

DC_BATFULL#_R

CHARGE_LED#_R

LEDCN1

Power CN Test Point

B B

3D3V_S0 NUM_LED# CAP_LED# MEDIA_LED#

1 1 1 1

TP240 AFTE30-GPTP240 AFTE30-GP TP41 AFTE30-GPTP41 AFTE30-GP TP37 AFTE30-GPTP37 AFTE30-GP TP38 AFTE30-GPTP38 AFTE30-GP

-1M(5/27)

ACES-CON6-8GP

20.K0228.006

20.K0286.006

PWR_LED1

3 2

LED-YG-50-GP

83.19223.B70

CHARGER_LED1

LED-YG-50-GP

83.19223.B70

C113

1 2

SC1U16V3ZY-GP

MEDIA_LED#_1

SC1KP50V2KX-1GP

1

EC15

4

Power LED

STDBY_LED#_E 31

3 2

4

Charger LED

7 1 2

3 4 5 6

8

-1(05/14)

3D3V_AUX_S5

-1(05/14)

3D3V_S0

NUM_LED# CAP_LED#

1 2

EC16

EC13

SC1KP50V2KX-1GP

WLAN_LED#36

R123

0R0402-PAD

-1(5/9)

-1

WLAN_LED#

WLAN_TEST_LED41

2nd = 84.27002.N31

MEDIA_LED# 19

R628

1 2

33R2J-2-GP

KBC_PWRBTN#_CN31,44

BT_LED41

SC

3G_LED#36

Q44

2N7002-11-GP

G

DDTC143ZUA-7-F-GP

NUM_LED41

DDTC143ZUA-7-F-GP

CAP_LED41

2N7002-11-GP

S D

Q10

Q9

R2

EBC

R1

R647

1 2

33R2J-2-GP

WLAN_TEST_LED

NUM_LED#_R

3D3V_AUX_S5

12

R616

R616 10KR2J-3-GP

10KR2J-3-GP

KBC_PWRBTN#_CN

G97

G97 GAP-OPEN

GAP-OPEN

2 1

3G_LED#_L

G

470R2J-2-GP

S D

R126

1 2

100R2J-2-GP

R118

1 2

100R2J-2-GP

12

R614

1 2

R627 820R2J-GPR627 820R2J-GP

1 2

R630 430R2J-GPR630 430R2J-GP

-1

WLAN_LED#_R

3G_LED#_R

Q48

2N7002-11-GP

2nd = 84.27002.N31

NUM_LED#

CAP_LED#CAP_LED#_R

KBC_PWRBTN# 41

12

C649

C649 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

WLAN_LED1 LED-Y-70-GP

AK

83.01221.Q70

3G_LED1

AK

LED-G-147-GP

83.01221.N70

D17

3

DY

BAV99PT-GP-U

2

1

3D3V_S0

3D3V_AUX_S5

A A

5

4

3

2

Four Peaks

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

LED&POWERBD CONN

Size Document Number Rev

Date: Sheet of

LED&POWERBD CONN

Four Peaks

16 57Friday, November 21, 2008

1

-1M

A

Layout Note: Place these resistors close to the CRT-out connector

CRT_R_SYS44

4 4

CRT_G_SYS44

CRT_B_SYS44

12

R511

150R2F-1-GP

12

R488

R499

150R2F-1-GP

Ferrite bead impedance: 10 ohm@100MHz

12

C522

DY

12

SC3P50V2CN-1-GP

C504

DY

12

C492

DY

SC3P50V2CN-1-GP

Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector.

3 3

Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

L26

1 2

FCB1608CF-GP

68.00230.021

L24

1 2

FCB1608CF-GP

68.00230.021

L21

1 2

FCB1608CF-GP

68.00230.021

SC3P50V2CN-1-GP

B

C

D

E

Hsync & Vsync level shift

CRT_R

CRT_G

CRT_B

12

C523

SC6D8P50V2DN-GP

C505

C493

SC6D8P50V2DN-GP

R519

1 2

10KR2J-3-GP

DOCK_ON_3#

5V_S0

R513

R513 100KR2J-1-GP

100KR2J-1-GP

1 2

SYS_CRT_ON#DOCK_IN#

Q41

Q41 2N7002-11-GP

S D

2N7002-11-GP

2ND = 84.27002.N31

14

5 6

7

G

-1

DIS

RN55

CRT_HSYNC46 CRT_VSYNC46

GMCH_HSYNC7 GMCH_VSYNC7

2 3 1

SRN0J-6-GP

SRN0J-6-GP RN52

RN52

1 2 3

SRN0J-6-GP

UMA

4

VSYNC_4

HSYNC_4

14

9 8

7

5V_S0

2 3

U54B

4

TSAHCT125PW-GP

5V_S0

12 11

10

U54C

TSAHCT125PW-GP

14

1

TSAHCT125PW-GP

7

CRT_VSYNC1_1

14

13

7

12

C501

C501 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U54A

CRT_HSYNC1_1

U54D

CRT_HSYNC2

TSAHCT125PW-GP

CRT_VSYNC2

RN54

2 3 1

SRN0J-6-GP

DOCK_IN# 18,38,41,44,45

RN53

1 2 3

SRN33J-5-GP-U

For System CRT

CRT_HSYNC1 CRT_VSYNC1

4

-1(5/9)

For Dock CRT

4

DOCK_HSYNC 44 DOCK_VSYNC 44

Function

DOCK_CRT_SEL#

SYSTEM H

LDOCK

CRT I/F & CONNECTOR

DDC_CLK & DATA level shift

2 2

CRT1

17

CRT_R

DAT_DDC1_5

12

C533

CRT_B CRT_VSYNC1

12

SC100P50V2JN-3GP

C498

6 1

1 1

7 2 8 3 9

CRT_DEC#41,44

SC100P50V2JN-3GP

R474

470R2J-2-GP

SC18P50V2JN-1-GP

CRT_IN#_R

12

C488

4 10

6 1

12

8

3 14 10

5 16

VIDEO-15-79-GP-U

20.20722.015

20.20717.015

BAV99PT-GP-U

3

D6

MH1 11 7

CRT_G

2

CRT_HSYNC1

13

5V_CRT_S0

9 4

CLK_DDC1_5

15 MH2

2

DY

3D3V_S0

1

5V_CRT_S0

RN32

SRN2K2J-1-GP

-1

UMA

12

C497

C499

12

C491

SCD01U16V2KX-3GP

SC18P50V2JN-1-GP

SC100P50V2JN-3GP

SC18P50V2JN-1-GP

GMCH_DDCDATA7 GMCH_DDCCLK7

CRT_DDCDATA46 CRT_DDCCLK46

UMA

RN56

2 3 1

SRN0J-6-GP

1 2 3

RN57

DIS

DAT_DDC1_5_QDAT_DDC1_5_QDAT_DDC1_5_QDAT_DDC1_5_Q

4

DAT_DDC1_5_QDAT_DDC1_5_QDAT_DDC1_5_QDAT_DDC1_5_Q

CLK_DDC1_5_QCLK_DDC1_5_QCLK_DDC1_5_QCLK_DDC1_5_QCLK_DDC1_5_QCLK_DDC1_5_Q

5

A

B

C

D

5V_CRT_S0

3D3V_S0

SC

F3

4

1

2 3

1 2

FUSE-1D1A6V-4GP-U

U56

5 6

2N7002DW-1-GP

2nd = 84.27002.C3F

Four Peaks

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

5V_CRT_DDC

34 2 1

CRT CONN

5V_S0

D37

D37 RB551V30-GP

RB551V30-GP

83.R5003.H8H

K A

500mA

678

RN33

SRN10KJ-6-GP

123

4 5

CRT_IN#_R

DAT_DDC1_5 44

CLK_DDC1_5 44

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Four Peaks

17 57Friday, November 21, 2008

E

3D3V_S0

of

-1M

5

4

3

2

1

DVI1

28

TMDS_TX0-_MB TMDS_TX0+_MB

D D

TMDS_TXC+_MB TMDS_TXC-_MB

17 18

26 19

20 21 22 23 24

25 27

TYCO-CONN24-3R-6-GP-U

From MXM

TMDS_A_TX2-46 TMDS_A_TX2+46 TMDS_A_TX1-46 TMDS_A_TX1+46

C C

B B

TMDS_A_TX0-46 TMDS_A_TX0+46 TMDS_A_TXC-46 TMDS_A_TXC+46

From NB

PEG_TXN07,46 PEG_TXP07,46 PEG_TXN17,46 PEG_TXP17,46

PEG_TXN27,46 PEG_TXP27,46 PEG_TXN37,46 PEG_TXP37,46

-1(05/14)

30 NP1

9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8

NP2 29

RN13

DIS

4 5 3 2 1

SRN0J-7-GP

RN9

DIS

4 5 3 2 1

SRN0J-7-GP

RN12

UMA

1 2 3 4 5

SRN0J-7-GP

RN7

UMA

1 2 3 4 5

SRN0J-7-GP

TMDS_TX1-_MB TMDS_TX2-_MB TMDS_TX1+_MB TMDS_TX2+_MB

5V_S0_DVI

12

EC62

DY

SC220P50V2JN-3GP

6 7 8

8 7 6

CH1 CH2

SRN4K7J-8-GP

DVI_TMDS_SCL DVI_TMDS_SDA

DVI_TMDS_SDA

12

DY

EC61

SC220P50V2JN-3GP

DVI DOCK

LH

3D3V_S0

R19

R19 0R2J-2-GP

0R2J-2-GP

DIS

1 2

VBIAS

R18

R18 0R2J-2-GP

0R2J-2-GP

UMA

1 2

A A

5

5V_S0_DVI

4

RN25

1

DVI_A_HPD_1

C9

1 2

DVI_TX_R_0DVI_TX_R_0+ DVI_TX_R_CLKDVI_TX_R_CLK+

DVI_TX_R_1DVI_TX_R_1+

DVI_TX_R_2DVI_TX_R_2+

DVI_DETECT_R

12

R636

R636 20KR2J-L2-GP

20KR2J-L2-GP

UMA

-1

5V_S0

2 3

BAV99-5-GP

EC64 SCD1U10V2KX-4GP

EC64 SCD1U10V2KX-4GP C376 SC1U16V3ZY-GPC376 SC1U16V3ZY-GP

C12

C14

1 2

SCD1U10V2KX-4GP

UMA

D31

1 2

G

4

12

DY

12

3D3V_S0

C11

SCD1U10V2KX-4GP

3D3V_S0

12

S D

2

DY

3

1 2

SCD1U10V2KX-4GP

UMA

R637

R637 20KR2J-L2-GP

20KR2J-L2-GP

Q49

Q49 2N7002-11-GP

2N7002-11-GP

1

NV_DVI_CLK NV_DVI_DAT HPD_SRC

R23

499R2F-2-GP

1 2

SMBD_Therm37,41,46 SMBC_Therm37,41,46

5V_S0_DVI

-1(5/9)

3D3V_S0

12

C13

SC2D2U10V3KX-1GP

U2

37

IN2P

38

IN2N

39

VCC

40

IN3P

41

IN3N

42

GND

43

IN4P

44

IN4N

45

SCL_SRC

46

SDA_SRC

47

HPD_SRC

48

REXT

49

GND

PS8122QFN48G-GP

71.08122.A03

R439

1 2

0R0402-PAD

1 2

R648 0R0402-PADR648 0R0402-PAD

R17

1 2

4K7R2F-GP

DVI_A_HPD_1 DVI_TMDS_SDA

DVI_TMDS_SCL

DVI_DETECT# 7

R638

R638 7K5R2F-1-GP

7K5R2F-1-GP

UMA

2ND = 84.27002.N31

1

2

VBIAS

35

33

36

34

IN1P

IN1N

CEXT

VBIAS

SW/SDA_CTL1OE#/SCL_CTL2I2C_CTL_EN3HPD14SDA1_AUX1N5SCL1_AUX1P6OUT1D4N8OUT1D4P9OUT1D3N11OUT1D3P

SCL_CTL

SDA_CTL

SB

32

OUT2D1P

30

31

OUT2D1N

7

27

29

28

GND

OUT2D2P

OUT2D2N

MODE/I2C_ADDR

VCC

10

3D3V_S0

26

25

VCC

OUT2D3P

OUT2D3N

SCL2_AUX2P SDA2_AUX2N

GND

12

ISO_PREP#20

GMCH_HDMI_CLK7

GMCH_HDMI_DATA7

24

OUT2D4P

23

OUT2D4N

22

GND

21 20 19

HPD2

18 17

OUT1D1P

16

OUT1D1N

15

VCC

14

OUT1D2P

13

OUT1D2N

DOCK_IN

DVI_DETECT_R HPD_SRC

DVI_A_HPD46

3

I2C_ADDR

3D3V_S0

DY

R87

1 2

0R2J-2-GP

1 2

4K7R2J-2-GP

DY

TMDS_SCL 44 TMDS_SDA 44

TMDS_HPD_DOCK 44

I2C_ADDR SDA_CTL SCL_CTL

R134

R21 1KR2J-1-GP

R21 1KR2J-1-GP R22 1KR2J-1-GP

R22 1KR2J-1-GP

1 2

R6 4K7R2F-GPR6 4K7R2F-GP

1 2

R86 1KR2J-1-GP

1 2

R135 1KR2J-1-GP

UMA

1 2 1 2

DIS

DY

DY DY

DY

5V_S0

RN4

UMA

2 3 1

3D3V_S0

D23

D23 RB551V30-GP

RB551V30-GP

83.R5003.H8H

K A

5V_S0_DVI

4

SRN0J-6-GP

SRN4K7J-8-GP

NV_DVI_CLK NV_DVI_DAT

BSS138-7F-GP

3D3V_S0

4

RN3

UMA

1

2 3

TMDS_TXC+_DOCK 44 TMDS_TXC-_DOCK 44 TMDS_TX0+_DOCK 44 TMDS_TX0-_DOCK 44 TMDS_TX1+_DOCK 44 TMDS_TX1-_DOCK 44 TMDS_TX2+_DOCK 44 TMDS_TX2-_DOCK 44

TO DOCK CONN TO SYSTEM CONN

TMDS_TXC+_MB TMDS_TXC-_MB TMDS_TX0+_MB TMDS_TX0-_MB TMDS_TX1+_MB TMDS_TX1-_MB TMDS_TX2+_MB TMDS_TX2-_MB

3D3V_S0

12

R85

R85 10KR2F-2-GP

10KR2F-2-GP

DOCK_IN

DS

Q5

2

G

NV_DVI_CLK 46 NV_DVI_DAT 46

DOCK_IN# 17,38,41,44,45

Four Peaks

Title

Size Document Number Rev

Custom

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DVI CONNECTOR

Four Peaks

18 57Friday, November 21, 2008

1

-1M

of

Winstron GW50 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual