Winbond Electronics W981616AH Datasheet

W981616AH

512K × 2 BANKS × 16 BITS SDRAM

GENERAL DESCRIPTION

W981616AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words × 2 banks × 16 bits. Using pipelined architecture and 0.20 µm process technology,
W981616AH delivers a data bandwidth of up to 332M bytes per second (-6). For different applications
the W981616AH is sorted into the following speed grades: -6, -7, and -8.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981616AH is ideal for main memory in
high performance applications.

FEATURES

• 3.3V ±0.3V power supply

• Up to 166 MHz clock frequency

• 524,288 words x 2 banks x 16 bits organization

• Auto Refresh and Self Refresh

• CAS latency: 2 and 3

• Burst Length: 1, 2, 4, 8, and full page

• Burst read, Single Write Mode

• Byte data controlled by UDQM and LDQM

• Auto-precharge and controlled precharge

• 4K refresh cycles/64 mS

• Interface: LVTTL

• Packaged in 50-pin, 400 mil TSOP II

PIN CONFIGURATION

V

DQ0
DQ1

V Q

SS

DQ2
DQ3

V Q

CC

DQ4
DQ5

V Q

SS

DQ6

DQ7

V Q

CC

LDQM

WE
CAS
RAS

A10

VCC

1

CC

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

CS

19

BA

20
21

A0

22

A1

23

A2
A3

24
25

50

V

SS

49

DQ15

DQ14

48

V Q

SS

47

DQ13

46

DQ12

45

V Q

CC

44

DQ11

43

DQ10

42

V Q

SS

41

DQ9

40

DQ8

39

V Q

CC

38
37

NC

36

UDQM

35

CLK

34

CKE

33

NC

32

A9

31

A8

30

A7

29

A6
A5

28
27

A4

26

V

SS

Publication Release Date: February 2000

- 1 - Revision A2

W981616AH

PIN DESCRIPTION

PIN NUMBER PIN NAME FUNCTION DESCRIPTION

20−24,
27−32

19 BA Bank Select Select bank to activate during row address latch time,

2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49

18

17

16

15
36, 14 UDQM/

35 CLK Clock Inputs System clock used to sample inputs on the rising

34 CKE Clock Enable CKE controls the clock activation and deactivation.

1, 25 VCC Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
26, 50 VSS Ground Ground for input buffers and logic circuit inside

7, 13, 38, 44, VCCQ Power (+3.3V)

4, 10, 41, 47 VSSQ Ground for I/O

33, 37 NC No Connection No connection

A0−A10

DQ0−DQ15

CS

RAS

CAS

WE

LDQM

Address Multiplexed pins for row and column address.

Row address: A0−A10. Column address: A0−A7.

or bank to read/write during column address latch
time.

Data Input/

Output

Chip Select Disable or enable the command decoder. When

Row Address

Strobe

Column

Address Strobe

Write Enable

Input/Output

Mask

for I/O buffer

buffer

Multiplexed pins for data input and output.

command decoder is disabled, new command is
ignored and previous operation continues.

Command input. When sampled at the rising edge of
the clock,

be executed.
Referred to

Referred to
The output buffer is placed at Hi-Z (with latency of 2)

when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.

edge of clock.

When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.

DRAM.
Separated power from VCC, used for output buffers to

improve noise immunity.
Separated ground from VSS, used for output buffers

to improve noise immunity.

RAS, CAS

RAS

RAS

and WE define the operation to

- 2 -

BLOCK DIAGRAM

W981616AH

CLK

CKE

CS

RAS

CAS

WE

A10

A0

A9
BA

CLOCK

BUFFER

COMMAND
DECODER

ADDRESS

BUFFER

REFRESH
COUNTER

CONTROL

SIGNAL

GENERATOR

MODE

REGISTER

COLUMN

COUNTER

COLUMN DECODER

R
O
W

CELL ARRAY

D
E
C
O
D
E
R

SENSE AMPLIFIER

DATA CONTROL

CIRCUIT

COLUMN DECODER

R
O
W

CELL ARRAY

D
E
C
O
D
E
R

SENSE AMPLIFIER

BANK #0

BANK #1

DQ

BUFFER

DQ0

DQ15

LDQM
UDQM

Note: The cell array configuration is 2048 * 256 * 16

Publication Release Date: February 2000

- 3 - Revision A2

W981616AH

RAS, CAS, CS

RAS

RAS

CAS

FUNCTIONAL DESCRIPTION

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs during power up, all VCC and VCCQ pins must be ramp up simultaneously to the
specified voltage when the input signals are held in the "NOP" state. The power up voltage must not
exceed VCC +0.3V on any of the input pins or V
is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles
(CBR) are also required before or after programming the Mode Register to ensure proper subsequent
operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low

signals of
this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

and WE at the positive edge of the clock. The address input data during

CC

supplies. After power up, an initial pause of 200 µS

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to

command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and
vice versa) is the Bank-to-Bank delay time (t
active is specified as tRAS(max.).

RCD

). Once a bank has been activated it must be precharged before another Bank

activate in EDO DRAM. The delay from when the Bank Activate

RRD

). The maximum time that each bank can be held

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by
setting
level defines whether the access cycle is a read operation (WE high), or a write operation (WE low).

The address inputs determine the starting column address. Reading or writing to a different row within
an activated bank requires the bank be precharged and a new Bank Activate command be issued.
When more than one bank is activated, interleaved bank Read or Write operations are possible. By
using the programmed burst length and alternating the access and precharge operations between
multiple banks, seamless data access operation among many different pages can be realized. Read
or Write Commands can also be issued to the same bank or between active banks on every clock
cycle.

high and

low at the clock rising edge after minimum of t

RCD

delay. WE pin voltage

- 4 -

Burst Read Command

CAS

RAS

CAS

RAS

W981616AH

The Burst Read command is initiated by applying logic low level to CS and
and WE high at the rising edge of the clock. The address inputs determine the starting column

address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.

while holding

Burst Write Command

The Burst Write command is initiated by applying logic low level to CS,

high at the rising edge of the clock. The address inputs determine the starting column address.
Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the
Write Command is issued. The remaining data inputs must be supplied on each subsequent rising
clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.

and WE while holding

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When
the previous burst is interrupted, the remaining addresses are overridden by the new address and
data will be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is
full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst

Publication Release Date: February 2000

- 5 - Revision A2

W981616AH

RAS

CAS

CAS

DATA

Access Address

Bust Length

A8 A7 A6 A5 A4 A3 A2 A1 A0

Stop Command is defined by having
the clock. The data DQs go to a high impedance state after a delay, which is equal to the

Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.

and

high with CS and WE low at the rising edge of

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address, which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2

Table 2 Address Sequence of Sequential Mode

DATA Access Address Burst Length
Data 0 n BL = 2 (disturb address is A0)
Data 1 n + 1 No address carry from A0 to A1
Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)
Data 3 n + 3 No address carry from A1 to A2
Data 4 n + 4
Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)
Data 6 n + 6 No address carry from A2 to A3
Data 7 n + 7

.

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2
Data 1

Data 2
Data 3
Data 4
Data 5
Data 6
Data 7

A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0

A8 A7 A6 A5 A4 A3 A2 A1 A0

A8 A7 A6 A5 A4 A3 A2 A1 A0

A8 A7 A6 A5 A4 A3 A2 A1 A0

A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 4

BL = 8

- 6 -

W981616AH

CAS

RAS

CAS

RAS, CAS

Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled

burst cycle. The number of clocks is determined by
A Read or Write Command with auto-precharge can not be interrupted before the entire burst

operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge command is
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation
one clock delay from the last burst write cycle. This delay is referred to as Write t
undergoing auto-precharge can not be reactivated until t
tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge Command, the interval
between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy t

RAS

(min).

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS,

of the clock. The Precharge Command can be used to precharge each bank separately or all banks
simultaneously. Three address bits, A10, and BA, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge
time (tRP).

and WE are low and

latency.

DPL

. The bank

DPL

and tRP are satisfied. This is referred to as

is high at the rising edge

Self Refresh Command

The Self-Refresh Command is defined by having CS,
at the rising edge of the clock. All banks must be idle prior to issuing the Self-Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self-Refresh Operation to save power. The device
will exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued
after tRC from the end of Self Refresh command.

If, during normal operation, Auto-Refresh cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 Auto-Refresh cycles should be completed just prior to entering and just
after exiting the Self-Refresh mode.

and CKE held low with WE high

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations;
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.

Publication Release Date: February 2000

- 7 - Revision A2

W981616AH

RAS, CAS

RAS, CAS

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCES(min) + tCK(min).

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when CS is low with
clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the

Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one-clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.

, and WE held high at the rising edge of the

, and WE signals become don't cares.

- 8 -

W981616AH

TABLE OF OPERATING MODES

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.

TABLE 1 TRUTH TABLE (NOTE 1, 2)

Command Device

Bank Active
Bank Precharge
Precharge All
Write
Write with

State

Idle H X X V V V L L H H
Any H X X V L X L L H L

Any H X X X H X L L H L
Active (3) H X X V L V L H L L
Active (3) H X X V H V L H L L

CKEn-1 CKEn DQM BA A10 A9-0

CS

RAS

CAS

WE

Autoprecharge
Read
Read with

Active (3) H X X V L V L H L H
Active (3) H X X V H V L H L H

Autoprecharge
Mode Register Set
No-Operation
Burst Stop
Device Deselect
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit

Clock Suspend Mode

Idle H X X V V V L L L L

Any H X X X X X L H H H
Active (4) H X X X X X L H H L

Any H X X X X X H X X X

Idle H H X X X X L L L H

Idle H L X X X X L L L H

Idle

(S.R)

Active H L X X X X X X X X

L
L

H
H

X X X X X X X X H L X H X H X

X

Entry
Power Down Mode

Entry
Clock Suspend Mode

Idle
Active (5)

Active L H X X X X X X X X

H
H

L
L

X X X X X X X X H L X H X H X

X

Exit
Power Down Mode Exit

Data Write/Output

Any

(Power

down)
Active H X L X X X X X X X

L
L

H
H

X X X X X X X X H L X H X H X

X

Enable

Data Write/Output

Active H X H X X X X X X X

Disable

Notes:
(1) V = Valid, X = Don't care, L = Low Level, H = High Level

(2) CKEn signal is input level when commands are provided.
(3) These are state of bank designated by BA signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.

Publication Release Date: February 2000

- 9 - Revision A2

W981616AH

RAS, CAS, WE

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT NOTES

Input, Output Voltage VIN, V
Power Supply Voltage VCC, VCCQ
Operating Temperature T
Storage Temperature T
Soldering Temperature (10s) T
Power Dissipation PD 1 W 1
Short Circuit Output Current I

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to 70°C)

PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES

OUT

-0.3 − 4.6

-0.3 − 4.6

OPR
STG

SOLDER

260 °C 1

OUT

50 mA 1

0 − 70

-55 − 150

V 1
V 1

°

C 1

°C 1

Power Supply Voltage VCC 3.0 3.3 3.6 V 2
Power Supply Voltage (for I/O

VCCQ 3.0 3.3 3.6 V 2

Buffer)
Input High Voltage VIH 2.0 - VCC +0.3 V 2
Input Low Voltage VIL -0.3 - 0.8 V 2

Note: VIH (max.) = VCC/VCCQ +1.2V for pulse width < 5 nS

IL

V

(min.) = VSS/VSSQ -1.2V for pulse width < 5 nS

CAPACITANCE

(VCC = 3.3V, TA = 25 °C, f = 1MHz)

PARAMETER SYM. MIN. MAX. UNIT

Input Capacitance (A0 to A10, BA, CS,

,

UDQM, LDQM, CKE)
Input Capacitance (CLK) - 4 pf
Input/Output capacitance (DQ0 to DQ15) CIO - 6.5 pf

Note: These parameters are periodically sampled and not 100% tested

CI - 4 pf

- 10 -

W981616AH

DC CHARACTERISTICS

(VCC = 3.3V ±0.3V, TA = 0°~70°C)

PARAMETER SYM. -6

Operating Current

1 bank operation I

CC1

MAX.

100 90 80 mA 3
tCK = min., tRC = min.
Active precharge command
cycling without burst
operation

Standby Current
tCK = min.,

IH

V

/L = V

CS

IH

(min.) /V

= V

IH

IL

CKE = VIH I

(max.)

CC2

50 45 40 3

Bank: inactive state
CKE = V

(Power down mode)

Standby Current
CLK = VIL,

VIH/L = V

CS

IH

(min.) /V

= V

IH

IL

(max.)

CKE = V

IL

IH

CC2P

I

2 2 2 3

CC2S

I

10 8 6

Bank: inactive state
CKE = V

(Power down mode)

No Operating Current
tCK = min.,

CS

= V

IH

(min.)

CKE = VIH I

IL

CC2PS

I

CC3

2 2 2

55 50 45

Bank: active state (2 banks)
CKE = V

(Power Down mode)

IL

Burst Operating Current (tCK = min.)

CC3P

I

5 5 5

CC4

I

130 110 100 3, 4
Read/ Write command cycling
Auto Refresh Current (tCK = min.)

CC5

I

90 80 70 3
Auto refresh command cycling
Self Refresh Current (CKE = 0.2V)

CC6

I

2 2 2

Self refresh mode

-7

MAX.

-8

MAX.

UNIT NOTES

PARAMETER SYM. MIN. MAX. UNIT NOTES

Input Leakage Current

I

I(L)

-5 5

µA

(0V ≤ VIN ≤ VCC, all other pins not under test = 0V)
Output Leakage Current

(Output disable , 0V ≤ V

OUT

≤ VCCQ )

LVTTL OutputT ″H″ Level Voltage

OUT

(I

= -2 mA)

LVTTL Output ″L″ Level Voltage

OUT

(I

= 2 mA)

O(L)

I

V

V

OH

OL

-5 5

µA

2.4 - V

- 0.4 V

Publication Release Date: February 2000

- 11 - Revision A2

W981616AH

AC CHARACTERISTICS

(VCC = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70 °C, Notes: 5, 6, 7, 8)

PARAMETER SYM.

MIN. MAX. MIN. MAX. MIN. MAX.

Ref/Active to Ref/Active Command Period t
Active to Precharge Command Period t
Active to Read/Write Command Delay

RC

RAS

RCD

t

Time
Read/Write(a) to Read/Write(b)Command

CCD

t

Period
Precharge to Active(b) Command Period t
Active(a) to Active(b) Command Period t
Write Recovery Time CL* = 2 t
CL* = 3
CLK Cycle Time CL* = 2 t
CL* = 3
CLK High Level Width t
CLK Low Level Width t
Access Time from CLK CL* = 2 t

RP

RPD

WR

CK

CH
CL
AC

CL* = 3 5.5 5.5 6

Output Data Hold Time t
Output Data High Impedance Time t
Output Data Low Impedance Time t
Power Down Mode Entry Time t
Transition Time of CLK (Rise and Fall) t
Data-in-Set-up Time t
Data-in Hold Time t
Address Set-up Time t
Address Hold Time t
CKE Set-up Time t
CKE Hold Time t
Command Set-up Time t
Command Hold Time t
Refresh Time t
Mode Register Set Cycle Time t

OH
HZ

LZ
SB

T
DS
DH

AS

AH

CKS

CKH
CMS
CMH

REF

RSC

-6 -7 -8 UNIT

60 70 72 nS
42 100000 48 100000 48 100000
18 20 20

1 1 1 Cycle

18 20 20 nS
12 14 16
10 10 10

6 7 8

10 1000 10 1000 10 1000

6 1000 7 1000 8 1000

2.5 3 3

2.5 3 3
7 7 7

2 2.5 3
2 6 2.5 7 3 8
0 0 0
0 6 0 7 0 8

0.3 10 0.3 10 0.3 10

1.5 2 2

1 1 1

1.5 2 2

1 1 1

1.5 2 2

1 1 1

1.5 2 2

1 1 1

64 64 64 mS

12 14 16 nS

- 12 -