Winbond Electronics W981216BH Datasheet

W981216BH

2M × 4 BANKS × 16 BIT SDRAM

GENERAL DESCRIPTION

W981216BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 2M words × 4 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology, W981216BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the personal computer industrial standard, W981216BH is sorted into three speed grades: -7, -75 and 8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the

PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W981216BH is ideal for main memory in high performance applications.

FEATURES

• 3.3V ±0.3V Power Supply

• Up to 143 MHz Clock Frequency

• 2,097,152 Words × 4 banks × 16 bits organization

• Auto Refresh and Self Refresh

• CAS Latency: 2 and 3

• Burst Length: 1, 2, 4, 8, and full page

• Burst Read, Single Writes Mode

• Byte Data Controlled by DQM

• Power-Down Mode

• Auto-precharge and Controlled Precharge

• 4K Refresh cycles / 64 mS

• Interface: LVTTL

• Packaged in TSOP II 54 pin, 400 mil - 0.80

KEY PARAMETERS

SYM. DESCRIPTION MIN.

/MAX.

tCK Clock Cycle Time Min. 7 nS 7.5 nS 8 nS tAC Access Time from CLK Max. 5.4 nS 5.4 nS 6 nS tRP Precharge to Active Command Min. 15 nS 20 nS 20 nS

tRCD Active to Read/Write Command Min. 15 nS 20 nS 20 nS

ICC1 Operation Current (Single bank) Max. 80 mA 75 mA 70 mA

CC4

Burst Operation Current Max. 100 mA 95 mA 90 mA

ICC6 Self-Refresh Current Max. 2 mA 2 mA 2 mA

Publication Release Date: October 2000

- 1 - Revision A1

-7

(PC133, CL2)

-75

(PC133, CL3)

-8H

(PC100)

PIN CONFIGURATION

W981216BH

DQ0

VCCQ

DQ1 DQ2

VSSQ

DQ3 DQ4

VCCQ

DQ5 DQ6

VSSQ

DQ7

LDQM

CAS RAS

BS0 BS1

A10/AP

A0 A1 A2 A3

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28

DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 V

DQ10 DQ9 VCCQ DQ8 V

NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4

- 2 -

PIN DESCRIPTION

W981216BH

PIN NUMBER PIN NAME

23 − 26, 22,

29 − 35

20, 21 BS0, BS1

2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48,

50, 51, 53

39, 15 UDQM/

38 CLK Clock Inputs System clock used to sample inputs on the rising edge

37 CKE Clock Enable CKE controls the clock activation and deactivation.

1, 14, 27 VCC Power (+3.3V) Power for input buffers and logic circuit inside DRAM.

28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM.

3, 9, 43, 49 VCCQ Power (+3.3V)

6, 12, 46, 52 VSSQ Ground for I/O

36, 40 NC No Connection No connection

A0 − A11

DQ0 − DQ15

RAS

CAS

LDQM

FUNCTION DESCRIPTION

Address Multiplexed pins for row and column address.

Row address: A0 − A11. Column address: A0 − A8.

Bank Select Select bank to activate during row address latch time,

or bank to read/write during address latch time.

Data Input/

Output

Chip Select Disable or enable the command decoder. When

Row Address

Strobe

Column Address

Strobe

Write Enable

Input/Output

Mask

for I/O Buffer

Buffer

Multiplexed pins for data output and input.

command decoder is disabled, new command is ignored and previous operation continues.

Command input. When sampled at the rising edge of the clock,

operation to be executed. Referred to

Referred to The output buffer is placed at Hi-Z (with latency of 2)

when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency.

of clock.

When CKE is low, Power Down mode, Suspend mode or Self Refresh mode is entered.

Separated power from VCC, used for output buffers to improve noise.

Separated ground from VSS, used for output buffers to improve noise.

RAS, CAS

RAS

and WE define the

Publication Release Date: October 2000

- 3 - Revision A1

BLOCK DIAGRAM

W981216BH

A10

A11 BS0 BS1

CLK

CKE

CAS

RAS

CLOCK

BUFFER

COMMAND

DECODER

ADDRESS

BUFFER

REFRESH COUNTER

CONTROL

GENERATOR

COLUMN

COUNTER

SIGNAL

MODE

COLUMN DECODER

R O W

CELL ARRAY

E C O D E R

SENSE AMPLIFIER

COLUMN DECODER

R O W

CELL ARRAY

D E C

BANK #2

O D E R

SENSE AMPLIFIER

BANK #0

DATA CONTROL

CIRCUIT

COLUMN DECODER

R O W

CELL ARRAY

E C O D E R

SENSE AMPLIFIER

COLUMN DECODER

R O W

CELL ARRAY

BANK #3

C O D E R

SENSE AMPLIFIER

BANK #1

BUFFER

DMn

DQ0

DQ15

UDQM LDQM

Note: The cell array configuration is 4096 * 512 * 16.

- 4 -

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT

W981216BH

Input/Output Voltage V Power Supply Voltage VCC, V Operating Temperature T Storage Temperature T Soldering Temperature (10s) T

IN, VOUT

CCQ

OPR

STG

SOLDER

260

-0.3 − VCC +0.3

-0.3 − 4.6 0 − 70

-55 − 150

V V

° ° °

C C

C Power Dissipation PD 1 W Short Circuit Output Current IOUT 50 mA

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to 70°C)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Power Supply Voltage VCC 3.0 3.3 3.6 V Power Supply Voltage (for I/O

Buffer) Input High Voltage VIH 2.0 - VCC +0.3 V Input Low Voltage VIL -0.3 - 0.8 V

Note: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 nS

VCCQ 3.0 3.3 3.6 V

CAPACITANCE

= 3.3V, f = 1 MHz, TA = 25°C)

PARAMETER SYMBOL MIN. MAX. UNIT

Input Capacitance (A0 to A11, BS0, BS1, CS,

RAS, CAS

, WE , DQM,

CKE) Input Capacitance (CLK) CCLK - 3.5 pf Input/Output capacitance CIO - 6.5 pf

Note: These parameters are periodically sampled and not 100% tested.

Publication Release Date: October 2000

- 5 - Revision A1

CI - 3.8 pf

AC CHARACTERISTICS AND OPERATING CONDITION

(Vcc = 3.3V ± 0.3V, TA = 0° to 70°C; Notes: 5, 6, 7, 8)

PARAMETER SYM.

MIN. MAX. MIN. MAX. MIN. MAX.

Ref/Active to Ref/Active Command Period

Active to precharge Command Period

Active to Read/Write Command Delay Time

Read/Write(a) to Read/Write(b)Command Period

Precharge to Active Command Period

Active(a) to Active(b) Command Period

Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 CL* = 3

tRC

RAS

RCD

CCD

tRP

RRD

tWR

tCK

7 1000 7.5

CLK High Level width tCH 2.5 CLK Low Level width tCL 2.5

Access Time from CLK CL* = 2

Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK

(Rise and Fall) Data-in Set-up Time

Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time

*CL = CAS Latency

CL* = 3

tAC

5.4 5.4 6 nS

tOH

tHZ

tLZ

tSB

tDS tDH tAS tAH

CKS

CKH

CMS

CMH

REF

RSC

-7

(PC133, CL2)

57 65 68

42 100000 45 100000 48 100000

15 20 20

1 1 1 Cycle

15 20 20

15 15 20

7.5 7 7.5

7.5

10 10

1000 10 1000 10 1000

2.5

5.4 6 6

3 3 3 3 7 3 7.5 3 8 0 0 0 0 7 0 7.5 0 8

0.5

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

64 64 64 mS

14 15 16 nS

10 0.5

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

W981216BH

-75

(PC133, CL3)

1000 8 1000

3 3

10 0.5

2 1 2 1 2 1 2 1

-8H

(PC100)

UNIT

- 6 -

W981216BH

DC CHARACTERISTICS

(VCC = 3.3V ± 0.3V, TA = 0°− 70°C)

PARAMETER SYM.

MIN. MAX.

Operating Current

= min., tRC = min.

Active precharge command cycling without burst operation

Standby Current

= min, CS = VIH

VIH / L = VIH (min.)/ VIL (max.) Bank: Inactive state

Standby Current CLK = VIL, CS= VIH

VIH / L = VIH (min.)/ VIL (max.) BANK: Inactive state

No Operating Current

= min., CS = VIH (min.)

BANK: Active state (4 banks)

Burst Operating Current

= min.

Read/ Write command cycling Auto Refresh Current

= min.

Auto refresh command cycling Self Refresh Current

Self Refresh Mode CKE = 0.2V

1 bank operation

CKE = VIH I

CKE = VIL

(Power Down mode)

CKE = VIH I

CKE = VIL

(Power down mode)

CKE = VIH I

CKE = VIL

(Power down mode)

ICC1 80 75 70 3

CC2

CC2P

CC2S

ICC2PS 1 1 1 mA

CC3

CC3P

CC4

CC5

CC6

-7

(PC133, CL2)

40 35 30 3

1 1 1 3

10 10 10

60 55 50

10 10 10

100 95 90 3, 4

170 160 150 3

2 2 2

-75

(PC133, CL3)

MIN. MAX. MIN. MAX.

-8H

(PC100)

UNIT NOTES

PARAMETER SYMBOL MIN. MAX. UNIT NOTES

Input Leakage Current (0V ≤ V

≤ V

, all other pins not under test = 0V)

Output Leakage Current (Output disable , 0V ≤ V LVTTL Output ″H″ Level Voltage (I

= -2 mA )

OUT

LVTTL Output ″L″ Level Voltage (I

= 2 mA )

OUT

≤ V

CCQ

)

I(L)

IO(L) -5 5

VOH 2.4 - V

-5 5

- 0.4 V

µA

Publication Release Date: October 2000

- 7 - Revision A1

W981216BH

Notes:

1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.

2. All voltages are referenced to VSS

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC.

4. These parameters depend on the output loading conditions. Specified values are obtained with output open.

5. Power up sequence is further described in the "Functional Description" section.

6. AC Testing Conditions

Output Reference Level 1.4V/1.4V Output Load See diagram below Input Signal Levels 2.4V/0.4V Transition Time (Rise and Fall) of Input Signal 2 nS Input Reference Level 1.4V

1.4 V

50 ohms

Output

Z = 50 ohms

50 pF

AC TEST LOAD

7. Transition times are measured between VIH and VIL.

8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.

- 8 -

W981216BH

(S.R.)

L H H x x x x x x x x H L x H x H x x

Active (5)

H L L x x x x x x x x H L x H x H x x

(power L L H H x x x x x x x x H L x H x H x x

OPERATION MODE

Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.

Table 1 Truth Table (Note (1), (2))

COMMAND DEVICE

Bank Active Idle H x x v v v L L H H Bank Precharge Any H x x v L x L L H L Precharge All Any H x x x H x L L H L Write Active (3) H x x v L v L H L L Write with Autoprecharge Active (3) H x x v H v L H L L Read Active (3) H x x v L v L H L H Read with Autoprecharge Active (3) H x x v H v L H L H Mode Register Set Idle H x x v v v L L L L No - Operation Any H x x x x x L H H H Burst Stop Active (4) H x x x x x L H H L Device Deselect Any H x x x x x H x x x Auto - Refresh Idle H H x x x x L L L H Self - Refresh Entry Idle H L x x x x L L L H Self Refresh Exit

STATE

idle

CKEN-1 CKEN DQM BS0, 1 A10

A0−A9

A11

CS RAS CAS WE

Clock suspend Mode Entry Active H L x x x x x x x x Power Down Mode Entry

Clock Suspend Mode Exit Active L H x x x x x x x x Power Down Mode Exit

Data write/Output Enable Active H x L x x x x x x x Data Write/Output Disable Active H x H x x x x x x x

Notes: (1) v = valid x = Don't care L = Low Level H = High Level (2) CKEn signal is input level when commands are provided.

CKEn-1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

Idle

Any

Publication Release Date: October 2000

- 9 - Revision A1

W981216BH

FUNCTIONAL DESCRIPTION

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs.

During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.3V on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

RSC

has

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t specified as t

(max).

RAS

). Once a bank has been activated it must be precharged before another Bank

RCD

). The maximum time that each bank can be held active is

RRD

Read and Write Access Modes

After a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of t level defines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address.

Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.

delay. WE pin voltage

RCD

- 10 -

W981216BH

Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.

Burst Write Command

The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst

Publication Release Date: October 2000

- 11 - Revision A1

W981216BH

read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA ACCESS ADDRESS BURST LENGTH

Data 0 n BL = 2 (disturb address is A0) Data 1 n + 1 No address carry from A0 to A1

Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1) Data 3 n + 3 No address carry from A1 to A2 Data 4 n + 4 Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2) Data 6 n + 6 No address carry from A2 to A3 Data 7 n + 7

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA ACCESS ADDRESS BUST LENGTH

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 Data 1

Data 2 Data 3 Data 4 Data 5 Data 6 Data 7

A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 4

BL = 8

- 12 -

W981216BH

Auto-Precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to as Write tWR. The bank undergoing auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as t

, Data-in to Active delay (t

DAL

between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t

(min).

RAS

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP).

= tWR + tRP). When using the Auto-precharge Command, the interval

DAL

Self Refresh Command

The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time.

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode.

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t device.

Publication Release Date: October 2000

- 13 - Revision A1

) of the

REF

+ 28 hidden pages