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W88112F
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Winbond Electronics W88112F, W88111AF Datasheet

W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
Table Of Contents
GENERAL DESCRIPTION ________________________________________________________________5
BLOCK DIAGRAM_______________________________________________________________________6
PIN CONFIGURATION ___________________________________________________________________7
PIN DESCRIPTIONS______________________________________________________________________8
REGISTERS DESCRIPTION______________________________________________________________12
Publication Release Date: Aug, 1996
- 1 - Preliminary/Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
Publication Release Date: Aug, 1996
- 2 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
Publication Release Date: Aug, 1996
- 3 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
REGISTER TABLE______________________________________________________________________57
D.C. CHARACTERISTICS________________________________________________________________ 61
PACKAGE DIMENSIONS ________________________________________________________________62
Preliminary/Confidential
Publication Release Date: Aug, 1996
- 4 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
GENERAL DESCRIPTION
The Winbond W88111AF/W88112F supports ATAPI CD-ROM specification (SFF 8020). Some ATAPI operations are executed by hardware to minimize system overhead, including ATAPI command and packet transfer, data transfer, ATAPI Soft Reset command, and Executive Drive Diagnostics command. It also features shadow drive support.
The Winbond W88111AF/W88112F supports various types of microprocessors, DRAMs, and DSPs. The W88111AF/W88112F supports up to 12/20-fold drive speed. It also supports CD-ROM, CD-
ROM/XA, CD-I, Video-CD, Photo-CD , and CD-Plus formats. The functions of W88111AF/W88112F include CD-ROM data de-scrambling, real-time error
correction of Layer 3 Reed-Solomon Product-like Code (RSPC), error detection, and data transfer to the host.
The W88111AF/W88112F features real-time ECC correction of one byte per P-word and Q-word. It can also perform repeated ECC passes to increase the reliability of data.
The W88111AF/W88112F supports up to 1Mbytes of DRAM. It also supports ring-control-register to add flexibility of external RAM control.
The host interface of W88111AF/W88112F supports data transfer using PIO, single word DMA, and multi-word DMA modes. There is an 8-byte FIFO to improve the IDE interface throughput.
The W88111AF/W88112F supports multi-block-transfer from external RAM to the host. * The W88112F supports accelerated error correction/detection to improve system performance. * The W88112F supports automatic target header search, automatic header comparison, and decoder
interrupt status collection to reduce firmware overhead.
W88111AF/W88112F GENERAL FEATURES
⇒ Supports ATAPI CD-ROM standard (SFF 8020) ⇒ Supports CD-ROM, CD-ROM/XA, CD-I, Video-CD, Photo-CD, and CD-Plus formats ⇒ Supports drive speed up to 12-fold ⇒ Supports various types of microprocessors and DSPs ⇒ Supports various types of industry-standard DRAMs ⇒ Supports ring-control-register to add flexibility of DRAM control ⇒ Supports CD-ROM data descrambling ⇒ Supports real-time correction of one byte error per P-word and Q-word ⇒ Supports error detection of CD-ROM data ⇒ Supports repeated error correction and error detection passes ⇒ 8-byte FIFO to improve IDE interface throughput ⇒ Data transfer to host in PIO, single word DMA, and multi-word DMA modes ⇒ Multi-block transfer ⇒ 100-pin PQFP
Publication Release Date: Aug, 1996
- 5 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
W88112F ENHANCED FEATURES
⇒ Supports drive speed up to 20-fold with 45ns DRAM ⇒ Up to 33% acceleration of error correction/detection ⇒ Automatic target header search ⇒ Automatic header comparison ⇒ Decoder interrupt status collection ⇒ Status valid timing control for high drive speed
BLOCK DIAGRAM
Subcode Interface
DSP
Sync Detector
& Descrambler
External RAM
Manager
Data FIFO
8 bytes
Preliminary/Confidential
DRAM
Micro-
Processor
ECC Corrector & EDC Checker
Microprocessor
Interface
HOST
Interface
Command Packet FIFO
12 bytes
ATAPI
Interface
Publication Release Date: Aug, 1996
- 6 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
PIN CONFIGURATION
R
R
A
A
1
2
GND
RA3 RA11 RA12 RA13 RA15
NC
LRCK
SDATA
BCK
C2PO
PAR/DJ
CLKO XOUT
XIN
GND
SCSB
WFCK
SCSYN
EXCK
HRSTb
UD0
UD1
NC UD2 UD3 UD4 UD5 UD6
GND
0
1
0
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
313233343536373839404142434445464748495
R
A
A
A
5
4
0
R
R
N
A
A
A
A
D
9
7
6
8
G
R
R
R
R
W88111AF
/W88112F
Preliminary/Confidential
R
R
A
R
V
W
D
D
1
E
1
D
4
b
R
R
R
R
A
R
O
N
D
C
0
D
D
1
E
3
2
0
b
818283848586878889909192939495969798991
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
0
GND RD6 RD7 RD5 RD4 CRSTb DD7 DD8 NC DD6 DD9 DD5 DD10 DD4 GND DD11 NC DD3 DD12 DD2 ARSTb DD13 NC DD1 DD14 DD0 DD15 DMARQ HWR GND
U
U
U
U
U
U
D
C
D
R
R
W
7
C
S
D
R
S
b
b
b
C
I
A
S
S
S
N
3
1
P
T
b
b
b
b
P
D
V
D
D
I
G
H
I
D
D
A
D
A
A
O
N
I
2
D
0
1
C
D
A
S
G
1
b
6 b
H
I
O
M
R
R
R
A
D
Q
D
C
b
Y
K b
Publication Release Date: Aug, 1996
- 7 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
PIN DESCRIPTIONS
The following convention is used in the pin description table below:
• (I) denotes an input
• (O) denotes an output
• (OZ) denotes a tri-state output
• (OD) denotes an open-drain output
• (I/O) denotes a bi-directional signal
Miscellaneous Pins
NAME NO. TYPE PIN DESCRIPTION
PAR/PJ
CLKO
XIN XOUT HRSTb ARSTb
CRSTb VDD GND
NC
12
13
15 14
21 60
75
41, 89
1, 16, 30, 46,
51, 66, 80, 94
7, 24, 58, 64,
72, 86
I/O RAM Parity Data/Drive Jumper - As a RAM parity bit when
PJSEL (19h.6) is high and as a drive select jumper when PJSEL is low.
O Clock Output - If CLKOS (1Ah.3) is low, CLKO pin will supply
clock signal of one-half the crystal frequency. If CLKOS is high, CLKO pin will supply normal crystal frequency.
I
Crystal Input/Output - Normally, XIN and XOUT are connected to a crystal.
O
I Host Reset - A pin receives reset signal from the host.
OD ATAPI Reset - After receiving an ATAPI Soft Reset command,
this pin becomes active-low when ARSTEN (2Fh.3) is enabled.
I Chip Reset - Forcing this input low to reset the whole chip.
Power Supply Pin - 5.0V ± 5% Ground Pin
No Connected Pin
Preliminary/Confidential
Micro-controller Interface
NAME NO. TYPE PIN DESCRIPTION
UD[7:0]
URS URDb UWRb UCSb
22, 23, 25, 26,
27, 28, 29, 31
32 33 34 35
I/OZ Microprocessor Data Bus - Bi-directional processor data lines.
I Register Select - To select address register or internal register. I Microprocessor Read Strobe - A low-active signal. I Microprocessor Write Strobe - A low-active signal. I Microprocessor Chip Select - A low-active signal.
- 8 - Preliminary/ Confidential Revision A0.1
Publication Release Date: Aug, 1996
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
UINTb
36
OD Microprocessor Interrupt - A signal can be externally wired-OR
Host Interface
NAME
DD[15:0]
DA[2:0] DASPb
CS3b
CS1b
PDIAGb
IOCS16b
HIRQ
DMACKb
IORDY
HRDb HWRb DMARQ
NO.
54, 56, 59, 62, 65, 68, 70, 73, 74, 71, 69, 67,
63, 61, 57, 55
40, 44, 42
37
38
39
43
45
47
48
49
50 52 53
TYPE PIN DESCRIPTION
I/OZ Host Data Bus - Signals enable data transfer between the host
I Host Address Bus - Signals to access various ATAPI registers.
I/OD Drive Active/Drive 1 Present - A time-multiplexed signal
I Host Chip Select 1 - A signal used to select the host Control
I Host Chip Select 0 - A signal used to select the host Command
I/OD Passed Diagnostics - A signal asserted by Drive 1 to indicate to
OD 16-bit I/O Select - During PIO transfer, this signal becomes
OZ Host Interrupt - A signal to request an interrupt service from
I DMA Acknowledge - A signal used for DMA transfer by the host
OZ I/O Channel Ready - When W88111AF/W88112F is not ready
I Host I/O Read - The read strobe signal. I Host I/O Write - The write strobe signal.
OZ DMA Request - A signal asserted for DMA data transfer when
Preliminary/Confidential
with other interrupt sources.
and W88111AF/W88112F.
indicating whether a drive is active, or Drive 1 is present.
Block Registers.
Block Registers.
Drive 0 that diagnostics is completed.
active-high to indicate a 16-bit data transfer.
host.
when DMARQ is ready.
for a data transfer request, this signal is negated for extension of the host data transfer cycle within any host register access.
W88111AF/W88112F is ready to transfer data to or from the host.
ATAPI Register Definition
ADDRESSES FUNCTIONS
CS1b CS3b DA2 DA1 DA0 Read Write
Control block registers
N A 1 1 0 Alternate status Device control
Publication Release Date: Aug, 1996
- 9 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Command block registers
A N 0 0 0 Data A N 0 0 1 ATAPI Error Register ATAPI Features A N 0 1 0 ATAPI Interrupt Reason Register A N 0 1 1 Reserved for SAM TAG Bytes A N 1 0 0 ATAPI Byte Count Register (bits 0-7) A N 1 0 1 ATAPI Byte Count Register (bits 8-15) A N 1 1 0 Drive Select A N 1 1 1 ATAPI Status ATA Command
Note : A = signal asserted, N = signal negated
Preliminary/Confidential
DSP Interface
NAME NO. TYPE PIN DESCRIPTION
LRCK 8 I L/R Channel Clock - Left and right channels are distinguished by
this signal. SDATA 9 I Serial Data - Serial data from DSP is received from this input. BCK 10 I Bit Clock - Bit clock from DSP is received from this input. C2PO 11 I C2 Pointer - C2 error flag from DSP is received from this input.
Subcode Interface
NAME NO. TYPE PIN DESCRIPTION
SCSD 17 I Subcode Serial Data - Subcode serial data from DSP is
received from this input. WFCK 18 I Write Frame Clock - Write frame clock from DSP is received
from this input. SCSYN 19 I Subcode Sync - Subcode sync from DSP is received from this
input. EXCK 20 I/O External Clock - A pin programmed as input or output to supply
bit clock for subcode.
External RAM Interface
NAME NO. TYPE PIN DESCRIPTION
ROEb RWEb
84 88
O External RAM Output Enable - External RAM read strobe. O External RAM Write Enable - External RAM write strobe.
Publication Release Date: Aug, 1996
- 10 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
RD[7:0]
RA[9:0]
RA[13:10]
RA[15:14]
78, 79, 77, 76,
81, 82, 87, 85
91, 92, 93, 95, 96, 97, 2, 100,
99, 98
5, 4, 3, 83
6, 90
I/O RAM Data Bus - Data bus for external RAM.
O RAM Address Bus - Address bus for external RAM.
O External RAM Column Address Strobe - External RAM column
O External RAM Row Address Strobe - External RAM row
Preliminary/Confidential
address strobe.
address strobe.
Publication Release Date: Aug, 1996
- 11 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
REGISTERS DESCRIPTION
IR - Index Register (read/write)
When URS(pin 32) is low, the Index Register can be accessed by the microprocessor. The value in IR specifies which internal register to be accessed by microprocessor when URS(pin 32) is high. Note that the 4 least significant bits of IR will increase following each read or write to any register except for PFAR(00h). Since IR does not automatically increase from 00h to 01h, consecutive reads to address 00h will repeatedly read register PFAR(00h). This feature accelerates read operation of ATAPI Command Packet.
PFAR - Packet FIFO Access Register - (read 00h)
While SCoD(20h.2) is high, the ATAPI Command Packet issued from host is received by the 12-byte Packet FIFO. Flag TENDb(01h.6) is used to check if the Packet FIFO is full. The microprocessor can read the ATAPI Command Packet by repeatedly read register PFAR(00h). Once the FIFO becomes empty, the value FFh will be returned if microprocessor read PFAR.
The Packet FIFO can also be used to receive command parameter less than 12 bytes. First, the control bit SCoD(20h.2) is set high to select the Packet FIFO to be addressed by the ATAPI Data port. When DRQ(37h.3) changes from 0 to 1, the lower 4 bits of ATBLO(34h) is latched as the FIFO threshold. Upon the number of bytes in the FIFO reaches the threshold, flag TENDb(01h.6) becomes active-low and flag FPKT(30h.1) becomes active-high. Once FPKT becomes high, any data writes to the ATAPI Data port is rejected.
INTCTL - Interrupt Control Register - (write 01h)
Bit 7: PFNEEN - Packet FIFO Not Empty Interrupt Enable
UINTb(pin 36) is activated when PFNEb(01h.7) becomes active-low if this bit is high.
Bit 6: TENDEN - Transfer End Interrupt Enable
UINTb(pin36) is activated when TENDb(01h.6) becomes active-low if this bit is high. TENDEN is also automatically enabled if the host issues the Packet Command(A0h) while HIIEN(2Eh.7) is high and drive is selected.
Bit 5: SRIEN - Sector Ready Interrupt Enable
UINTb(pin36) is activated when SRIb(01h.5) becomes active-low if this bit is high.
Publication Release Date: Aug, 1996
- 12 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
Bits 4, 3, 2: Reserved
Bit 1: DTEN - Data Transfer Enable
Set DTEN high enables the data transfer logic. This bit should be set before any of the following data transfers is triggered:
• Host write to the Packet FIFO
• Host read from external RAM
• Host read from DF0 to DF7
In order to reduce the interference of microprocessor, DTEN is also automatically enabled during the following operation:
• Trigger ADTT(17h.2)
• Host issues ATAPI Packet Command(A0h) while APKTEN(18h.7) is enabled and drive is
selected
Bit 0: Reserved
INTREA - Interrupt Reason Register - (read 01h)
Bit 7: PFNEb - Packet FIFO Not Empty Interrupt Flag
This bit becomes active-low after Packet FIFO receives any data issued by the host through ATAPI Data port. UINTb(pin 36) is activated when PFNEb becomes active-low if PFNEEN(01h.7) is enabled. PFNEb is deactivated after the last byte is read by microprocessor through register PFAR(00h).
Bit 6: TENDb - Transfer End Interrupt Flag
This bit becomes active-low at the end of the following data transfers:
• Host writes to the Packet FIFO
• Host read from external RAM
• Host read from registers DF0(40h) to DF7(47h)
Flags TDIR(30h.5) and FPKT(30h.1) can be used to determine which type of transfer end occurs. UINTb(pin36) is activated when TENDb becomes active-low if TENDEN(01h.6) is enabled. Writing any value to register TACK(07h) deactivates this flag.
Bit 5: SRIb - Sector Ready Interrupt Flag
This bit is used to indicate that one sector is ready to be accessed. Reading register STAT3(0Fh) deactivates SRIb.
Publication Release Date: Aug, 1996
- 13 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
Bit 4: HCIb - Host Command Interrupt Flag
This bit is activated by the following events:
• Host issues ATAPI Soft Reset Command, if ARSTIEN(2Fh.1) is enabled
• Host issues command to a non-exist slave drive, if SHIEN(2Eh.2) is enabled
• Host issues Execute Drive Diagnostics Command, if HIIEN(2Eh.7) is enabled
• ATAC(2Fh.6) becomes active-high, if HIIEN(2Eh.7) is enabled
• Host set bit SRST in ATAPI Device Control Register, if HIIEN(2Eh.7) is enabled
Bit 3: TBSYb - Transfer Busy Flag
This bit becomes active-low when the data transfer to host is triggered by the following events:
• Writing any value to register THTRG(06h)
• Setting bit ADTT(17h.2) high
After host reads the last byte to be transferred, TBSYb is deactivated.
Bit 2: MBTIb - Multi-Block Transfer Interrupt Flag
This bit is activated by the following events:
• RPINT(30h.3) becomes active-high while RPIEN(2Ah.5) is enabled
• MBTI(30h.4) becomes active-high while MBKIEN(13h.2) is enabled
The microprocessor can read register MISS2(30h) to tell which event occurs.
Bit 1: DFRDYb - Data FIFO Ready
After data transfer is triggered, the 8-byte Data FIFO is automatically filled. This bit is used to indicate that the Data FIFO is ready to be read by the host.
Bit 0: SCIb - Subcode Interrupt Flag
If SCIEN(2Ch.4) is enabled, this bit becomes active-low when one of the following events occurs:
• ISS(22h.0) becomes active-high
• NESBK(22h.1) becomes active-high
• MSS(22h.2) becomes active-high
When Subcode Interrupt is activated, the microprocessor can read register SUBSTA(22h) to determine the reason of interrupt. Writing register SCIACK(22h) deactivates Subcode Interrupt.
Publication Release Date: Aug, 1996
- 14 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
TBCL/TBCH - Transfer Byte/Word Counter - (read/write 02h/03h)
Before triggering data transfer, the number of bytes or words to be transferred should be set through 12-bit Transfer Byte/Word Counter. The number of bytes minus 1 should be written to this counter while using 8-bit data transfer. The number of words minus 1 should be written to this counter while using 16-bit data transfer. After host reads one byte or word, the counter is decreased by one till Transfer End Interrupt is activated when this counter becomes zero.
TACL/TACH - Transfer Address Counter - (write 04h/05h)
Before triggering data transfer, the external RAM address of data to be transferred should be set through 16-bit Transfer Address Counter. This number in this counter specifies the first available data address relative to the beginning of the block. The block number should also be specified through Transfer Block registers TBL/TBH(24h/25h). After one byte/word is read by host, TACL/TACH are increased to the next available data address.
TBL/TBH - Transfer Block Register - (read/write 24h/25h)
Before triggering data transfer, the external RAM block of data to be transferred should be set through Transfer Block Registers. TBL/TBH form a 9-bit register that is used to specify the first RAM block to be transferred, while TACL/TACH(04h/ 05h) specify the starting address relative to the beginning of this RAM block. The RAM block number in TBL/TBH is not increased automatically at the end of each transfer unless multi-block transfer is used by specifying register MBTC0(12h).
THTRG - Transfer to Host Trigger Register - (write 06h)
This register is used to trigger data transfer regardless of what value is written. When bit UDTS(1Fh.6) is low, the data transfer from external RAM to the host after THTRG is
triggered. Triggering THTRG automatically fills the Data FIFO and then flag DFRDYb(01h.1) becomes active-low when the Data FIFO becomes ready.
When bit UDTS(1Fh.6) is high, the path of data transfer is from registers DF0-DF7(40h-47h) to the host. In this case, the data count, less than 8, should be set using registers TBCL(02h) before triggering THTRG and bit UDTT(1Fh.7) should be set to 1 followed by 0 after triggering THTRG.
Publication Release Date: Aug, 1996
- 15 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
TACK - Transfer Acknowledge - (write 07h)
Writing register TACK deactivates TENDb(01h.6) and its corresponding microprocessor interrupt regardless of what data is written.
HEAD0 to HEAD3 - Header Registers - (read 03h to 07h)
These four registers are used to hold the information of Header Bytes of each sector. Header Registers should be read soon after STAVAb(0F.7) becomes active-low. Note that the header bytes are untrustful if wrong mode is set while ECC is enabled. If the bit SHDEN(0Bh.0) is enabled, registers HEAD0-3 are used to hold subheader bytes instead.
BIAL/BIAH - Buffering Initial Address Register - (write 08h/09h)
Before enabling the external RAM buffering, BIAL/BIAH should be set to control the location of the first byte follows data sync for each data sector. The RAM block for buffering is controlled by the number in registers DDBL/DDBH(28h/29h) plus one. For convenience of following data transfer, the microprocessor should set proper value to BIAH/BIAL(FF,F0h for mode-1 and FF,E8h for mode-2) after the mode is determined so that the first user data byte will locate at offset 00h of each data block.
BACL, BACH - Buffering Address Counter - (read 0Ah/0Bh)
After enabling the external RAM buffering, Buffering Write Counter are automatically increased by two , beginning from the value specified by BIAL/BIAH, every time a data word is buffered.
EIAL/EIAH - ECC Initial Address Register- (read 08h/09h, write 0Ch/0Dh)
EIAL/EIAH are used to hold the initial address offset of the data block to be corrected. The content of BIAL/BIAH(08h/09h) will be automatically loaded to EIAL/EIAH at the beginning of each data sync, making it unnecessary to read or write EIAL/EIAH during normal operation. The RAM block for ECC is controlled by the number in registers DDBL/DDBH(28h/29h).
Publication Release Date: Aug, 1996
- 16 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
SCBL/SCBH - Subcode Block Register - (read/write 26h/27h)
SCBL/SCBH form a 9-bit register that contains a block number of the latest available subcode data that can be read by the host. The number in SCBL/SCBH plus 1 points to the RAM block that is buffering incoming subcode. The number in SCBL/SCBH is increased by one at the end of subcode block buffering.
DDBL/DDBH - Decoded Data Block Register - (read/write 28h/29h)
DDBL/DDBH form a 9-bit register that contains the number of the latest available decoded data block after decoder interrupt occurs. This block number should be used to specify TBL/TBH(24h/25h) before triggering data transfer to the host. This decoded-data-block-number plus 1 points to the DRAM block that is buffering incoming serial data and increases by one at the end of each data block buffering.
CTRL0 - Control Register 0 - (write 0Ah)
Bit 7: DECEN - Decoding Logic Enable
Setting this bit high enables the decoding logic.
Bit 5: EDCEN - Error Detect and Correct Enable
Setting this bit high enables the ECC and EDC logic.
Bit 4: ACEN - Automatic Correction Enable
When this bit is set high during MODE 2 ECC, the type of error correction is automatically determined by the setting of the FORM bit in the subheader byte. When this bit is low during MODE 2 ECC, the type of error correction is controlled by F2RQ(0Bh.2).
Bit 2: BUFEN - Buffering Enable
Setting this bit high enables incoming DSP data buffering. When this bit is high, the values of register HEAD0-3(04h-07h) and SUBH0-3(14h-17h) are retrieved from external RAM rather than from incoming serial data. When BUFEN is low, any setting of QCEN or PCEN is meaningless.
Bit 1: QCEN - Q-codeword Correction Enable
When this bit is high, Q-codeword RSPC correction logic is enabled.
Publication Release Date: Aug, 1996
- 17 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Bit 0: PCEN - P-codeword Correction Enable
When this bit is high, P-codeword RSPC correction logic is enabled.
Bit 6,3: Reserved
DECEN
0Ah.7
1 1 1 1 1 Q-P correction 1 1 1 1 0 Q-correction 1 1 1 0 1 P-correction 1 1 1 0 0 Write-only CRC 1 0 0 0 0 Disk-monitor no buffering 0 X X X X Decoder
BUFEN
0Ah.2
EDCEN
0Ah.5
QCEN
0Ah.1
PCEN
0Ah.0
Decoder
Mode
disable
Preliminary/Confidential
Operation
Flow
Q → P → CRC Q → CRC P → CRC
no operation
CTRL1 - Control Register 1 - (write 0Bh)
Bit 7: SIEN - Sync Insertion Enable
When this bit is high, the sector boundary is determined by internal sync insertion logic.
Bit 6: SDEN - Sync Detection Enable
When this bit is high, the sector boundary is determined by incoming serial data.
Bit 5: DSCREN - Descrambler Enable
Setting this bit high enables the descrambling logic.
Bit 4: CWEN - Corrected Data Write Enable
Setting this bit high enables corrected data to be written to the external RAM.
Bit 3: M2RQ - Mode 2 ECC Request
Setting this bit high enables the mode 2 ECC correction logic. Mode 1 ECC correction will be performed if this bit is low.
Publication Release Date: Aug, 1996
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W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
Bit 2: F2RQ - Form 2 Request
Setting this bit high requests the data to be processed by the mode-2 form-2 format if M2RQ(0Bh.3) is high.
Bit 1: MCRQ - Mode Byte Check Request
When this bit is high, ECC logic will check the 4th header byte with the setting of M2RQ(0Bh.3) to determine if ECC correction needs to be performed.
Bit 0: SHDEN - Subheader Switch Enable
When this bit is high, registers HEAD0-3 are used to provide subheader bytes.
STAT0 - Status Register 0 - (read 0Ch)
Bit 7: CRCOK - Cyclic Redundancy Check OK
This bit is used to indicate whether the Cyclic Redundancy Check of the latest available sector is passed.
Bit 6: ILSYN - Illegal Sync Pattern
If SDEN(0Bh.6) is high, this bit becomes high when a sync pattern is detected less than 2352 bytes after last sync pattern was detected/inserted.
Bit 5: NOSYN - No Sync Pattern
If SIEN(0Bh.7) is high, this bit becomes high when a sync pattern is not detected at 2352 bytes after last sync pattern was detected/inserted.
Bit 4: LBKF - Long Block Flag
If SIEN(0Bh.7) is low, this bit becomes high when a sync pattern is not detected at 2352 bytes after last sync pattern was detected/inserted.
Bit 3: WSHORT - Word Short
This bit becomes high when the incoming serial data rate is too high to be processed by W88111AF/W88112F.
Bit 2: SBKF - Short Block Flag
If SDEN(0Bh.6) is low, this bit becomes high when a sync pattern is detected less than 2352 bytes after last sync pattern was detected/inserted.
Publication Release Date: Aug, 1996
- 19 - Preliminary/ Confidential Revision A0.1
W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Status Flag
ILSYN(0Ch.6) x 1 re-synchronize internal sync logic NOSYN(0Ch.5) 1 x internal sync logic provide internal sector
LBKF(0Ch.4) 0 x internal sync logic do not provide internal
SBKF(0Ch.2) x 0 do not re-synchronize internal sync logic
SIEN
(0Bh.7)
SDEN
(0Bh.6)
Internal Operation
boundary
sector boundary
Preliminary/Confidential
Bit 1: FDIF - Fast Decoder Interrupt Flag
If FDIEN(10h.3) is enabled, this bit becomes high when the Header/Subheader bytes are ready after ECC is complete and before CRC is complete. Meanwhile, UINTb(pin 36) and STAVAb(0Fh.7) become active-low thus accelerate the following microprocessor operations. FDIF is deactivated when CRC is complete. UINTb(pin 36) also becomes low-active when CRC is complete. So if FDIEN(10h.3) is enabled, CRCVAb(10h.7) should be used to determine whether the CRCOK(0Ch.7) is available when interrupt becomes active.
Bit 0: UEBK - Incorrectable Errors in Block
This bit is used to indicate that at least one data is corrected in the latest available data block.
STAT1 - Status Register 1 - (read 0Dh)
Bit 4: HDERA - Header Erasure
This bit is high if there is at least one erasure flag detected in header bytes excluding mode byte. Erasure in mode byte will cause RMOD3-0(0Eh.7-4) all become high.
Bit 0: SHDERA - Subheader Erasure
This bit is high if erasure flags are detected for both bytes in at least one subheader byte-pairs.
Erasures are latched from pin C2PO if BUFEN(0Ah.2) is disabled. Otherwise, header and subheader bytes are retrieved from external RAM while the following sector is being buffered.
Publication Release Date: Aug, 1996
- 20 - Preliminary/ Confidential Revision A0.1
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