Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Winbond for
any damages resulting from such improper use or sales.
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-1 - Revision 0.54
W83L784R
Preliminary
TABLE OF CONTENTS
1. GENERAL DESCRIPTION....................................................................................................................5
2.3POWER GOOD .........................................................................................................................................6
6.6.2 Voltage ........................................................................................................................................26
6.6.3 Fan ..............................................................................................................................................26
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-4 - Revision 0.54
W83L784R
Preliminary
1. GENERAL DESCRIPTION
W83L784R is an evolving product of W83782D --- Winbond's most popular hardware status
monitoring IC. Specifically designed for the Notebook system, W83L784R can be used to monitor
several critical hardware parameters of the system, including power supply voltages, fan speeds, and
temperatures, which are very important for a high-end Notebook system to work stably and properly.
An 8-bit analog-to-digital converter (ADC) was built inside W83L784R. The W83L784R can
monitor 4 analog voltage inputs, 2 fan tachometer inputs, one on-chip internal temperature sensor
and 2 remote temperature sensors. The remote temperature sensing can be performed by
thermistors, or 2N3904 NPN-type transistors, or directly from IntelTM Deschutes CPU thermal diode
output. The W83L784R provides 2 PWM (pulse width modulation) outputs for the fan speed control
to support the } Thermal Cruise
programmable temperature under the hardware control. Another Fan speed control mode is }Speed
}
Cruise
low active outputs such as fan fault and Battery low which could issue the hardware warning signals
when the fan speed or battery voltage drop out of the preset range. Also the W83L784R provides:
power good reset for 3V and 5V; power down mode for power saving; fault pin for necessary H/W
shutdown control; SMI#, OVT#, GPO# signals for system protection events; I2CTM serial bus interface.
Through the application software or BIOS, the users can read all the monitored parameters of
system from time to time. And a pop-up warning can be also activated when the monitored item was
out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, or
IntelTM LDCM (LanDesk Client Management), or other management application software. Also the
users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to
activate one programmable and maskable interrupts. For the spacing saving consideration of the
Notebook system, W83L784R is in the package of 209mil 20pins-SSOP.
to Keep the fan operating in the specific r.p.m.. On the other hand, the W83L784R provides
TM
~ system, which can maintain the CPU or system in the specific
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-5 - Revision 0.54
W83L784R
Preliminary
2. FEATURES
2.1 Monitoring Items
•
2 thermal inputs from remote thermistors or 2N3904 NPN-type transistors or PentiumTM II
(Deschutes) thermal diode output
•
One on-chip temperature detection
•
4 voltage inputs
--- typical for Vcore, +3.3V, +5V, Battery
•
2 sets of fan speed control and fan speed monitoring input
•
WATCHDOG comparison of all monitored values
•
Programmable hysteresis and setting points (alarm thresholds) for all monitored items
2.2 Actions Enabling
• Issue fan fault signal as fans are abnomally stopped
•
Issue battery low signal as bettery voltage is abnomally out of range
•
2 PWM (pulse width modulation) outputs for fan speed control to support } Thermal Cruise
} Speed Cruise
--- Automatically maintain the CPU or system in the specific temperature or keep the fans in the
specific speed under the H/W control
•
Issue SMI#, OVT#, GPO to activate system protection
•
PWR_DN# setting for the Power down mode
•
Warning signal pop-up in application software
TM
~
TM
~ or
2.3 Power Good
•
Issue RESET# outputs as the Power Good signal when 3V and 5V rise across a reset threshold.
2.4 General
•
I2CTM serial bus interface
•
IntelTM LDCM (DMI driver 2.0) support
•
AcerTM ADM (DMI driver 2.0) support
•
Winbond hardware monitoring application software (Hardware Doctor
Windows 95/98
•
Meet WfM 2.0 (Wired for Management) spec.
•
5V Vcc operation
TM
) support, for both
2.5 Package
•
20-pin SSOP (209mil)
Confidential, For Beta-site Only Publication Release Date: Sep.
-6 - Revision 0.54
1999
3. KEY SPECIFICATIONS
•
Voltage monitoring accuracy ±1% (Max)
•
Monitoring Temperature Range and Accuracy
- 40°C to +120°C ± 3°C(Max)
•
Supply Voltage 5V
•
Operating Supply Current 2 mA typ.
•
Power Down Suppy Current 10 uA typ.
•
ADC Resolution 8 Bits
4. PIN CONFIGURATION
W83L784R
Preliminary
FANIN1/GPO1
FANIN2/GPO2
PWMOUT1
PWMOUT2
FANFAULT#/GPO3
PWR_DN#
SMI#
OVT#
SCL
SDA
10
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
VCC
CPUT1/PII1
CPUT2/PII2
VREF
VIN1
RESET#
VIN2(+3.3VIN)
VIN3(VBAT)
GND
BATFAULT#/GPO4
Confidential, For Beta-site Only Publication Release Date: Sep.
-7 - Revision 0.54
1999
5. PIN DESCRIPTION
I/O
- TTL level bi-directional pin with 12 mA source-sink capability
12t
I/O
- TTL level and schmitt trigger
12ts
OUT12 - Output pin with 12 mA source-sink capability
AOUT - Output pin(Analog)
OD12 - Open-drain output pin with 12 mA sink capability
INt - TTL level input pin
INts - TTL level input pin and schmitt trigger
AIN - Input pin(Analog)
W83L784R
Preliminary
PIN NAME PIN NO.
FANIN1 /
1 INts /
GPO1
TYPE DESCRIPTION
0V to +5V amplitude fan tachometer input. (Default) /
OUT12
General purpose output .
This multi-functional pin is programmable.
FANIN2 /
GPO2
2 INts /
OUT12
0V to +5V amplitude fan tachometer input. (Default) /
General purpose output .
This multi-functional pin is programmable.
PWMOUT13 OD
/
12
OUT12
Fan speed control PWM output. This pin is
default
open-drain. It
can be programmed as an output pin which can drive a HIGH or
a LOW.
PWMOUT24 OD
/
12
OUT12
Fan speed control PWM output. This pin is
default
open-drain. It
can be programmed as an output pin which can drive a HIGH or
a LOW.
FANFAULT# /
GPO3
5 OD12 Active-Low output. This pin will be a logic LOW when fan1 or
fan2 is abnormally stopped. (Default) /
General purpose output .
This multi-functional pin is programmable.
PWR_DN# 6
INt
Power down input. When set this pin LOW, all output pins would
be tristate except the pin15 RESET# which will keep HIGH.
SMI# 7 OD12 System Management Interrupt.
OVT# 8 OD12 Over temperature Shutdown Output.
SCL 9 INts Serial Bus Clock.
SDA 10 OD12 Serial Bus bi-directional Data.
BATFAULT#
/
GPO4
11 OD12 Active-Low output. This pin will be a logic LOW when Battery
abnormally drops below the low limit or above the high limit.
(Default) /
General purpose output .
This multi-functional pin is programmable.
GND 12 Ground Ground.
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-8 - Revision 0.54
W83L784R
Preliminary
Pin Discription, continued
PIN NAME PIN NO.
VIN3(VBAT) 13 AIN 0V to 4.096V FSR Analog Inputs. ( This pin should be
VIN2(+3.3VIN)
RESET# 15 OUT12 Active-Low reset output. RESET# remains LOW while the
VIN1(VCORE) 16 AIN 0V to 4.096V FSR Analog Inputs.
VREF 17 AOUT Reference Voltage.
CPUT2 /
PII2
CPUT1 /
PII1
VCC 20 POWER +5VCC power supply input.
14 AIN 0V to 4.096V FSR Analog Inputs. (This pin should be
18 AIN Thermistor terminal input.(Default) /
19 AIN Thermistor terminal input.(Default) /
TYPE DESCRIPTION
connected to DC BATTERY. If this voltage is above 4.096V, it
should be reduced with the external resistors so that the input
voltage will be under 4.096V. )
connected to 3VCC .)
5VCC and +3.3V are below the reset threshold. It remains
LOW for 200ms after the reset condition is terminated .
PentiumTM II diode input.
This multi-functional pin is programmable.
PentiumTM II diode input.
This multi-functional pin is programmable.
Confidential, For Beta-site Only Publication Release Date: Sep.
-9 - Revision 0.54
1999
W83L784R
Preliminary
6. FUNCTIONAL DESCRIPTION
6.1 General Description
The W83L784R provides at most 4 analog positive inputs, 2 fan speed monitors, 2 sets for
fan PWM (Pulse Width Modulation) Smart Fan Control , 2 remote thermal inputs from remote
thermistors or 2N3904 transistors or Pentium
thermal detection. W83L784R also provides the power good (reset) output for 3V and 5V power
detection and two fault output pins issuing hardware warning if battery and fans become abnormal.
When start the monitor function on the chip, the watch dog machine monitor every function and store
the value to registers. If the monitor value exceeds the limit value, the interrupt status will be set to 1.
6.2 Access Interface
The W83L784R provides I2C Serial Bus to read/write internal reigsters. In the W83L784R
there are three serial bus address. The first address defined at CR[4Ah] can read/write all registers
excluding CPUT1/CPUT2 temperature sensor registers and its address default value is 0101101. The
address for CPUT1 defined at CR[4Bh] bit2-0 only read/write CPUT1 temperature sensor registers
and the address default value is 1001001. The address for CPUT2 defined at CR[4Bh] bit2-0 only
read/write CPUT1 temperature sensor registers and the address default value is 1001000.
TM
II (Deschutes) thermal diode outputs and one on-chip
6.2.1 The first serial bus access timing are shown as follow:
(a) Serial bus write to internal address register followed by the data byte
SCL
SDA
0
0101101D7D6D5D4D3D2D1D0
Start By
Master
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
Frame 1
Serial Bus Address Byte
SCL
(Continued)
SDA (Continued)
78078
R/W
Ack
by
784R
0
D7D6D5D4D3D2D1D0
Frame 2
Internal Index Register Byte
Frame 3
Data Byte
78
784R
Ack
Stop
by
by
Master
Ack
784R
by
Confidential, For Beta-site Only Publication Release Date: Sep.
-10 - Revision 0.54
1999
(b) Serial bus write to internal address register only
W83L784R
Preliminary
SCL
SDA
0
0101101D7D6D5D4D3D2D1D0
Start By
Master
Frame 1
Serial Bus Address Byte
Figure 2. Serial Bus Write to Internal Address Register Only
78078
R/W
Ack
by
784R
0
Frame 2
Internal Index Register Byte
Ack
784R
Stop by
by
Master
(c) Serial bus read from a register with the internal address register prefer to desired location
SCL
SDA
0
0101101D7D6D5D4D3D2D1D0
Start By
Master
Frame 1
Serial Bus Address Byte
Figure 3. Serial Bus Read from Internal Address Register
78078
R/W
Ack
by
784R
0
Frame 2
Internal Index Register Byte
Ack
Master
Stop by
by
Master
6.2.2 The serial bus timing of the temperature CPUT1 and CPUT2 is shown as follow:
(a) Typical 2-byte read from preset pointer location (Temp, TOS, T
SCL
0
78078
......
)
HYST
07
SDA
0101101D7D1D0
Start By
Master
Frame 1
Serial Bus Address Byte
Figure 4. Typical 2-Byte Read From Preset Pointer Location
R/W
Ack
784R
...
by
Frame 2
MSB Data Byte
D7D1D0
...
Master
Ack
by
Frame 3
LSB Data Byte
No Ack
Master
Stop by
Master
by
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-11 - Revision 0.54
W83L784R
Preliminary
(b) Typical pointer set followed by immediate read for 2-byte register (Temp, TOS, T
Frame 2
Pointer Byte
Ack
by
Master
4
D1 D0
07
D7D1D0
...
Frame 5
LSB Data Byte
Ack
784R
by
SCL
SDA
SCL
SDA
0
1001A2A1A0 R/W
Start By
Master
0
Frame 1
Serial Bus Address Byte
780
000000
Ack
by
784R
78078
......
1001A2A1A0 R/W
Start By
Master
Frame 3
Serial Bus Address Byte
0
Figure 5. Typical Pointer Set Followed by Immediate Read for 2-Byte Register
D7D1D0
...
Ack
by
784R
Frame 4
MSB Data Byte
(c) Typical read 1-byte from configuration register with preset pointer
SCL
SDA
0
1001A2A1A0 R/WD1D5D4D3D6
Start By
Master
Frame 1
Serial Bus Address Byte
780
D7D2
Ack
by
782D
Frame 2
Data Byte
8
7
D0
No Ack
by
Master
HYST
No Ack
by
Master
Stop by
Master
)
Stop by
Master
Figure 6. Typical 1-Byte Read From Configuration With Preset Pointer
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-12 - Revision 0.54
W83L784R
(d) Typical pointer set followed by immediate read from configuration register
Preliminary
0
1001A2A1A0 R/W
Start By
Master
0
1001A2A1A0 R/W
Serial Bus Address Byte
Frame 1
Serial Bus Address Byte
Frame 3
SCL (Cont..)
SDA (Cont..)
Repea
Start
Master
SCL
SDA
By
Figure 7. Typical Pointor Set Followed by Immediate Read from Temp 2/3 Configuration Register
(e) Temperature configuration register Write
SCL
SDA
0
1001A2A1A0 R/W
Start By
Master
Frame 1
Serial Bus Address Byte
780
000000
Ack
by
784R
780
D7D5D4
D6D3
Ack
by
784R
780
0000000
Ack
by
784R
Frame 4
MSB Data Byte
Pointer Byte
Frame 2
Frame 2
Pointer Byte
4
4
D2D1D0
D1 D0
D1 D0
7
No Ack
Master
78
78
8
by
Ack
by
784R
Ack
784R
...
...
by
Stop by
Master
SCL (Cont...)
SDA (Cont...)
0
00D4D3D2D10D0
Configuration Data Byte
Figure 8. Configuration Register Write
Frame 3
78
Ack
784R
Stop
by
by
Master
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-13 - Revision 0.54
(f) Temperature TOS and T
SCL
SDA
0
1001A2A1A0 R/W
Start By
Master
Serial Bus Address Byte
HYST
Frame 1
write
780
Ack
by
784R
W83L784R
Preliminary
4
0
0
0000
Frame 2
Pointer Byte
D1 D0
78
Ack
by
784R
SCL (Cont...)
SDA (Cont...)
0
D6D5D4D3D2D1D7D0
Frame 3
MSB Data Byte
Figure 9. Configuration Register Write
78
078
D6D5D4D3D2D1D7D0
Ack
by
784R
Frame 4
LSB Data Byte
Ack
Stop
by
by
784R
Master
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-14 - Revision 0.54
W83L784R
CPUT1
Preliminary
6.3 Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB.
Really, the application of the PC monitoring would most often be connected to power suppliers. The
CPU V-core voltage and +3.3V voltage can directly connected to these analog inputs. The 5VSB and
battery inputs should be reduced a factor with external resistors so as to obtain the input range. As
Figure 10 shows.
Positive Inputs
Typical Thermister
Connection
**The connections of CPUT2
is same as CPUT1
VIN1(VCORE)
VIN2(+3.3V)
10V(Battery DC)
R
10K, 1%
R
THM
10K, 25 C
VCC
232K, 1%
R1
VIN3(VBAT)
VREF
R2
99K, 1%
Pin 16
Pin 14
Pin 20
Pin 13
Pin 17
Pin 19
8-bit ADC
with
16mV LSB
Figure. 10.
6.3.1 Monitor over 4.096V voltage:
The input voltage VIN3 can be expressed as following equation.
R
VINV
3
=×
BAT DC
−
2
RR
+
12
The value of R1 and R2 can be selected to 232K Ohms and 99K Ohms, respectively, when the input
voltage V
is 10V. The node voltage of VIN3 can be subject to less than 4.096V for the maximun
BAT-DC
input range of the 8-bit ADC. The pin 24 is connected to the power supply VCC with +5V. There are
two functions in this pin with 5V. The first function is to supply internal analog power in the W83L784R
and the second function is that this voltage with 5V is connected to internal serial resistors to monitor
the +5V voltage. The value of two serial resistors are 34K ohms and 50K ohms so that input voltage
to ADC is 2.98V which is less than 4.096V of ADC maximum input voltage. The express equation can
represent as follows.
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-15 - Revision 0.54
W83L784R
Preliminary
K
50
VVCC
=×
in
5034
where VCC is set to 5V.
6.3.2 Power good for 3V and 5V
On power up, once VCC(5V) reaches 1V, RESET# will be a logic low. As 3V and VCC(5V)
rise, RESET# remains asserted. If 3V and VCC(5V) both exceed the reset threshold, RESET
becomes a logic high after a time equal to the reset pulse width (tRST, typically 200ms).(Figure 11).
If a power fail or a brownout happens(i.e. 3V or VCC(5V) drops below the threshold), RESET# output
is asserted. As long as the 3V and VCC(5V) remain below the reset threshold, RESET# output
remains asserted. Therefore, a brownout condition that interrupts a previously initiated reset pulse
causes an additional 200ms delay from the time the latest interruption occurred. On power-on, once
3Vor VCC(5V) drops below the reset threshold, RESET# are guaranteed to be asserted for VCC ≥ 1V.
3.3V
4
3
2
1
0
V
RST
V
RST
Ω
KK
+
ΩΩ
≅
2 98
.
V
The time of voltage over 4V
is less than tRST
VCC
5
4
3
2
1
0
RESET
V
RST
5
tRST
0
V
RST
VCC
5
4
3
2
1
0
5
RESET
0
tRST
V
RS
V
RS
Figure 11
Confidential, For Beta-site Only Publication Release Date: Sep.
1999
-16 - Revision 0.54
V
RS
tRST
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