Winbond Electronics W83977EF-PW, W83977EF-AW Datasheet

W83977EF

WINBOND I/O

W83977EF Data Sheet Revision History

1 n.a. 06/01/98 0.40

2

3 n.a. 12/30/03 0.5 Remove W83977CTF Part

4 03/07/03 1.0 Update the new version on web

5

6

7

8

9

10

Pages Dates Version

4,7,49,50,53,55,
90,91

P86~P110

06/16/98 0.41

04/25/03 1.1 Add Chapter 10 Configuration Register

Version

on Web

Main Contents

First published.
For Beta Site customers only

Data correction

Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result in
personal injury. Winbond customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.

TABLE OF CONTENTS

W83977EF

GENERAL DESCRIPTION ..................................................................................................................... 1

FEATURES ............................................................................................................................................. 2

PIN CONFIGURATION ........................................................................................................................... 5

1.0 PIN DESCRIPTION.......................................................................................................................... 6

1.1 H

OST INTERFACE

1.2 G

ENERAL PURPOSE

1.3 S

ERIAL PORT INTERFACE

1.4 I

NFRARED INTERFACE

1.5 M

ULTI-MODE PARALLEL PORT

1.6 FDC I

1.7 KBC I

1.8 POWER PINS .............................................................................................................................. 18

1.9 ACPI I

2.0 FDC FUNCTIONAL DESCRIPTION............................................................................................... 19

2.1 W83977EF FDC .......................................................................................................................... 19

2.1.1 AT interface...........................................................................................................................19

2.1.2 FIFO (Data)...........................................................................................................................19

2.1.3 Data Separator............................................................. .........................................................20

2.1.4 Write Precompensation..................................................................................................... ....20

2.1.5 Perpendicular Recording Mode ............................................................................................21

2.1.5 Perpendicular Recording Mode ............................................................................................21

2.1.6 FDC Core..............................................................................................................................21

2.1.7 FDC Commands ...................................................................................................................21

2.2 R

2.2.1 Status Register A (SA Register) (Read base address + 0) ..................................................33

2.2.2 Status Register B (SB Register) (Read base address + 1) ..................................................35

2.2.3 Digital Output Register (DO Register) (Write base address + 2)..........................................37

2.2.4 Tape Drive Register (TD Register) (Read base address + 3) ..............................................37

2.2.5 Main Status Register (MS Register) (Read base address + 4) ............................................38

2.2.6 Data Rate Register (DR Register) (Write base address + 4) ...............................................38

2.2.7 FIFO Register (R/W base address + 5)................................................................................40

2.2.8 Digital Input Register (DI Register) (Read base address + 7)..............................................42

2.2.9 Configuration Control Register (CC Register) (Write base address + 7) ............................. 43

NTERFACE
NTERFACE

NTERFACE

EGISTER DESCRIPTIONS

............................................................................................................................. 6

I/O P

..................................................................................................................... 10

............................................................................................................................ 16

............................................................................................................................ 18

........................................................................................................................... 18

.......................................................................................................... 8

ORT

.................................................................................................................. 9

........................................................................................................ 11

............................................................................................................... 33

3.0 UART PORT.................................................................................................................................... 45

3.1 U

NIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER

3.2 R

EGISTER ADDRESS

3.2.1 UART Control Register (UCR) (Read/Write) ........................................................................45

3.2.2 UART Status Register (USR) (Read/Write)..........................................................................48

3.2.3 Handshake Control Register (HCR) (Read/Write)........... ... .... .... .... ... .... .... ........ ... .... .... .... ....48

-II - Revision 1.1

...................................................................................................................... 45

(UART A, UART B) .................................... 45

Publication Release Date: April 2003

W83977EF

3.2.4 Handshake Status Register (HSR) (Read/Write) .................................................................49

3.2.5 UART FIFO Control Register (UFR) (Write only)..................................................................50

3.2.6 Interrupt Status Register (ISR) (Read only)..........................................................................51

3.2.7 Interrupt Control Register (ICR) (Read/Write) ......................................................................52

3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ....................................................52

3.2.9 User-defined Register (UDR) (Read/Write).......................................................................... 52

4.0 INFRARED (IR) PORTS ................................................................................................................. 54

4.1 IR PORT ...................................................................................................................................... 54

5.0 PARALLEL PORT ......................................................................................................................... 55

5.1 P

RINTER INTERFACE LOGIC

5.2 E

NHANCED PARALLEL PORT

5.2.1 Data Swapper.................................................................................................................56

5.2.2 Printer Status Buffer ............................................................................. .... ... .... .... .... .... ... .57

5.2.3 Printer Control Latch and Printer Control Swapper........................................................ 58

5.2.4 EPP Address Port............................................................................................................58

5.2.5 EPP Data Port 0-3...........................................................................................................59

5.2.6 Bit Map of Parallel Port and EPP Registers ................................................................... .59

5.2.7 EPP Pin Descriptions...................................................................................................... 60

5.2.8 EPP Operation.................................................................................................................60

5.3 E

XTENDED CAPABILITIES PARALLEL

5.3.1 ECP Register and Mode Definitions................................................................................61

5.3.2 Data and ecpAFifo Port ...................................................................................................62

5.3.3 Device Status Register (DSR)........................................................................................62

5.3.4 Device Control Register (DCR) .......................................................................................63

5.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010................................................................ .64

5.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011........................................... .... .... ... ........ .... ... .64

5.3.7 TFIFO (Test FIFO Mode) Mode = 110 ............................................................................64

5.3.8 CNFGA (Configuration Register A) Mode = 111............................................................. 64

5.3.9 CNFGB (Configuration Register B) Mode = 111............................................................. 64

5.3.10 ECR (Extended Control Register) Mode = all .................................................................65

5.3.11 Bit Map of ECP Port Registers ........................................................................................ 66

5.3.12 ECP Pin Descriptions ............................................................ ....... .... .... .... .... ... .... .... .... ... .67

5.3.13 ECP Operation........................................................ .... ... .... .... .... .... ... ........ .... ... .... .... .... ... .68

5.3.14 FIFO Operation........................................... .... .... .... .... ... .... .... .... ... .... ........ ... .... .... .... .... ... .6 8

5.3.15 DMA Transfers.................................................................................................................69

5.3.16 Programmed I/O (NON-DMA) Mode ....................................................................... .... ... .69

5.4

5.5 E

E

XTENSION
XTENSION

FDD M
2FDD M

............................................................................................................ 55

(EPP)................................................................................................. 56

(ECP) P

(EXTFDD) .......................................................................................... 69

ODE

(EXT2FDD) ...................................................................................... 69

ODE

........................................................................... 61

ORT

6.

KEYBOARD CONTROLLER ..................................................................................................... 70

6.1 O

UTPUT BUFFER

6.2 I

NPUT BUFFER

6.3 S

TATUS REGISTER

6.4 C

6.5 H

6.6 ONN

-III - Revision 1.1

OMMANDS

ARDWARE

6.5.1 KB Control Register (Logic Device 5, CR-F0).................................................................74

6.5.2 Port 92 Control Register (Default Value = 0x24).............................................................74

OW

........................................................................................................................... 70

.............................................................................................................................. 70

........................................................................................................................ 71

............................................................................................................................... 72

GATEA20/K

/ S

ECURITY KEYBOARD AND MOUSE WAKE-UP

EYBOARD RESET CONTROL LOGIC

........................................................... 73

.............................................................. 75

Publication Release Date: April 2003

W83977EF

6.6.1

6.6.2 Keyboard Password Wake-Up Function ........................................................................75

6.6.3 Mouse Wake-Up Function........................................................................................ .......75

7.0 GENERAL PURPOSE I/O .............................................................................................................. 76

7.1 B

7.2 A

7.2.1 Interrupt Steering.............................................................................................................80

7.2.2 Watch Dog Timer Output.................................................................................................81

7.2.3 Power LED.......................................................................................................................81

7.2.4 General Purpose Address Decoder ................................................................................ 81

8.0 PLUG AND PLAY CONFIGURATION....................................................................................... 82

8.1 C

8.1.1 Extended Function Registers .......................................................................... .... .... .... ... .82

8.1.2 Extended Functions Enable Registers (EFERs) .............................................................83

8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)
83

8.2 C

8.2.1 Enter the extended function mode........................................................................................83

8.2.2 Configurate the configuration registers.................................................................................84

8.2.3 Exit the extended function mode...........................................................................................84

8.2.4 Software programming example...........................................................................................84

9.0 ACPI REGISTERS FEATURES................................................................................................. 85

10.0 CONFIGURATION REGISTER ................................................................................................... 86

10.1 C

10.2 L

10.3 L

10.4 L

10.5 L

10.6 L

10.7 L

10.8 L

10.9 L

Keyboard Wake-Up Function ..........................................................................................75

I/O

ASIC
LTERNATE

OMPATIBLE PN

FUNCTIONS

I/O F

................................................................................................................ 78

UNCTIONS

P ..................................................................................................................... 82

....................................................................................................... 80

ONFIGURATION SEQUENCE

HIP (GLOBAL
OGICAL DEVICE
OGICAL DEVICE
OGICAL DEVICE
OGICAL DEVICE
OGICAL DEVICE
OGICAL DEVICE
OGICAL DEVICE
OGICAL DEVICE

) C

ONTROL REGISTER

0 (FDC) ........................................................................................................... 92

1 (P

2 (UART A)¢) .................................................................................................. 96

3 (UART B) ..................................................................................................... 97

5 (KBC) ......................................................................................................... 100

7 (GP I/O P
8 (GP I/O P

A (ACPI) ........................................................................................................ 110

.......................................................................................................... 83

............................................................................................ 86

ARALLEL PORT

) .......................................................................................... 96

I) .......................................................................................... 101

ORT

II) ......................................................................................... 105

ORT

11.0 SPECIFICATIONS ...................................................................................................................... 117

11.1 A

11.2 DC CHARACTERISTICS........................................................................................................117

11.3 AC C

-IV - Revision 1.1

BSOLUTE MAXIMUM RATINGS

HARACTERISTICS

11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec....................................................121

11.3.2 UART/Parallel Port...........................................................................................................123

11.3.3 Parallel Port Mode Parameters........................................................................................123

11.3.4 EPP Data or Address Read Cycle Timing Parameters ...................................................124

11.3.5 EPP Data or Address Write Cycle Timing Parameters....................................................125

11.3.6 Parallel Port FIFO Timing Parameters.............................................................................126

11.3.7 ECP Parallel Port Forward Timing Parameters...............................................................126

11.3.8 ECP Parallel Port Reverse Timing Parameters...............................................................126

................................................................................................... 117

.............................................................................................................. 121

Publication Release Date: April 2003

W83977EF

11.3.9 KBC Timing Parameters ..................................................................................................127

11.3.10 GPIO Timing Parameters...............................................................................................127

11.3.11 Keyboard/Mouse Timing Parameters............................................................................128

12.0 TIMING WAVEFORMS .............................................................................................................. 129

12.1 FDC......................................................................................................................................... 129

12.2 UART/P

12.2.1 Modem Control Timing.....................................................................................................131

12.3 P

12.3.1 Parallel Port Timing..........................................................................................................132

12.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) .....................................................133

12.3.3 EPP Data or Address Write Cycle (EPP Version 1.9) ....................................... .... .... ......134

12.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) .....................................................135

12.3.5 EPP Data or Address Write Cycle (EPP Version 1.7) .....................................................136

12.3.6 Parallel Port FIFO Timing.................................................................................................136

12.3.7 ECP Parallel Port Forward Timing...................................................................................137

12.3.8 ECP Parallel Port Reverse Timing...................................................................................137

12.4 KBC......................................................................................................................................... 138

12.4.1 Write Cycle Timing...........................................................................................................138

12.4.2 Read Cycle Timing...........................................................................................................138

12.4.3 Send Data to K/B .............................................................................................................138

12.4.4 Receive Data from K/B.............................................. .... ... ........ .... ... .... .... .... ... .... .... .... ......138

12.4.5 Input Clock.......................................................................................................................139

12.4.6 Send Data to Mouse .................................................................................................. ...... 139

12.4.7 Receive Data from Mouse ........................................... .... .... .... .... ... .... .... ........ ... .... .... .... ..139

12.5 GPIO W

12.6 M

12.7 K

ARALLEL

ARALLEL PORT

RITE TIMING DIAGRAM

ASTER RESET

EYBOARD/MOUSE WAKE-UP TIMING

...................................................................................................................... 130

........................................................................................................................ 132

.................................................................................................. 140

(MR) T

.................................................................................................... 140

IMING

......................................................................................... 140

13.0 APPLICATION CIRCUITS.......................................................................................................... 141

13.1 P

13.2 P

13.3 F

14.0 ORDERING INFORMATION ...................................................................................................... 143

15.0 HOW TO READ THE TOP MARKING ...................................................................................... 143

16.0 PACKAGE DIMENSIONS.......................................................................................................... 144

-V - Revision 1.1

ARALLEL PORT EXTENSION
ARALLEL PORT EXTENSION

OUR

FDD M

..................................................................................................................... 143

ODE

FDD ............................................................................................. 141

2FDD ........................................................................................... 142

Publication Release Date: April 2003

W83977EF

GENERAL DESCRIPTION

The

W83977EF

integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plug­and-play registers for the whole chip --- plus additional powerful features:
controller with PS/2 mouse support, 14 general purpose I/O ports, full 16-bit address decoding,
OnNow keyboard Wake-Up, OnNow mouse Wake-Up.

The disk drive adapter functions of
the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data
rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide
range of functions integrated onto the W83977EF greatly reduces the number of components required
for interfacing with floppy disk drives. The

2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s.
The

W83977EF

serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupt system. Both
UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud
rates of

The
also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or
two external floppy disk drives to be connected.

The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
demand of Windows 95

W83977EF

Interface), which includes support of legacy and ACPI power management through

function pins.
The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable

ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEY
Phoenix MultiKey/42

The
General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a predefined alternate function.

The W83977EF also supports Power-loss control, and makes the system never miss to detect any
Wake-Up event provided by the chipset such as INTEL PIIX4

W83977EF

I/O space resource are flexible to adjust to meet ISA PnP requirement. Moreover
to meet the specification of PC98's requirement in the power management:
Power Management).

Another benifit is that
W83977ATF. Thus makes the design very flexible.

230k, 460k

W83977EF

W83977EF

is an evolving product from Winbond's most popular I/O chip W83877F --- which

, 8042 keyboard

ACPI

W83977EF

provides two high-speed serial communication ports (UARTs), one of which supports

, or

921k bps

supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and

TM

provides functions that complies with

W83977EF

provides a set of flexible I/O control functions to the system designer through a set of

is made to fully comply with

also has auto power management to reduce power consumption.

TM

, or customer code.

W83977EF

which support higher speed modems.

, which makes system resource allocation more efficient than ever.

Microsoft PC98 Hardware Design Guide

is of the same pin assignment of W83977AF, W83977F, W83977TF,

include a floppy disk drive controller compatible with

W83977EF

supports four 360K, 720K, 1.2M, 1.44M, or

(Advanced Configuration and Power

ACPI

SMI

TM

.

. IRQs, DMAs, and

W83977EF

and

ACPI

DPM

or

SCI

TM

2,

-

is made
(Device

Publication Release Date: April 2003

-1 - Revision 1.1

W83977EF

FEATURES

General

• Plug & Play 1.0A compatible

• Support 12 IRQs, 4 DMA channels, full 16-bit address decoding

• Capable of ISA Bus IRQ Sharing

• Compliant with

• Support

• Report ACPI status interrupt by SCI# signal issued from any of the 12 IQRs pins or GPIO xx

• Programmable configuration settings

• single 24/48 Mhz clock input

Microsoft PC98

(Device Power Management),

DPM

FDC

• Compatible with IBM PC AT disk drive systems

• Variable write pre-compensation with track selectable capability

• Support vertical recording format

• DMA enable logic

• 16-byte data FIFOs

• Support floppy disk drives and tape drives

• Detects all overrun and underrun conditions

• Built-in address mark detection circuit to simplify the read electronics

• FDD anti-virus functions with software write protect and FDD write enable signal (write data signal

was forced to be inactive)

Support up to four 3.5-inch or 5.25-inch floppy disk drives

•

Completely compatible with industry standard 82077

•

360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate

•

Support

•

3-mode FDD, and its Win95 driver

Hardware Design Guide

ACPI

UART

• Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs

MIDI compatible

•

Fully programmable serial-interface characteristics:

•

--- 5, 6, 7 or 8-bit characters

--- Even, odd or no parity bit generation/detection

--- 1, 1.5 or 2 stop bits generation

Publication Release Date: April 2003

-2 - Revision 1.1

W83977EF

• Internal diagnostic capabilities:

--- Loop-back controls for communications link fault isolation

--- Break, parity, overrun, framing error simulation

Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (2

•

Maximum baud rate up to

•

921k bps

for 14.769 Mhz and 1.5M bps for 24 Mhz

Infrared

• Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps

Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps

•

Parallel Port

• Compatible with IBM parallel port

Support PS/2 compatible bi-directional parallel port

•

• Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification

Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification

•

• Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and

B through parallel port

Enhanced printer port back-drive current protection

•

Keyboard Controller

8042 based with optional F/W from AMIKKEY

•

• With 2K bytes of programmable ROM, and 256 bytes of RAM

Asynchronous Access to Two Data Registers and One status Register

•

Software compatibility with the 8042 and PC87911 microcontrollers

•

• Support PS/2 mouse

Support port 92

•

• Support both interrupt and polling modes

•

Fast Gate A20 and Hardware Keyboard Reset

• 8 Bit Timer/ Counter

Support binary and BCD arithmetic

•

• 6MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency

TM

-2, Phoenix MultiKey/42

TM

or customer code

16

-1)

Publication Release Date: April 2003

-3 - Revision 1.1

W83977EF

General Purpose I/O Ports

• 14 programmable general purpose I/O ports; 6 dedicate, 8 optional

• General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog

timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control
I/O pins

OnNow Funtions

Keyboard Wake-Up by programmable keys

•

Mouse Wake-Up by programmable buttons

•

Package

• 128-pin PQFP

Publication Release Date: April 2003

-4 - Revision 1.1

PIN CONFIGURATION

I

I

R

R

Q

Q

1

1

1

2

1

1

0

0

1

2

IRQ14/GP14
IRQ15/GP15

IOR#

IOW#

AEN

IOCHRDY

VCC

DACK0#/GP16

SCI#/DRQ0/GP17

VSS

DACK1#

DRQ1

DACK2#

DRQ2

DACK3#

DRQ3

D0

D1
D2

D3
D4

D5

D6
D7
MR

TC

103
104

105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

12

W83977EF

P

P

A

P

A

N

W

N

S

R

S

W

C

S

W

O

T

M

I

U

L

I

N

T

#

#

#

I
R

I

I

I

Q

R

R

R

1

Q

Q

Q

0

4

3

1

9

9

1

9

7

8

0

9

0

4

3

5

6

I
R
Q
5

969

7

I

I

R

R

Q

Q

C

7

6

5949392

9

8

I
R

A

V

A

Q9N

1

S

1

4

S

5

9

9089888

1

1

1

121

1

4

1

3

0

A

A

1

1

2

3

15161

A

A

V

1

C

011

C

8

8

8

5

6

7

4

1

1

9

8

7

A

9

5

8
180

222

7

797

7

8

262

2

3

425

8

8

2

3

2

2

0

1

#

/

/

/

/

G

G

G

V

P

P

A1A2A3A4A6A7A8A

S

2

2

A

B

3

2

0

7

7

7

7

7

7

3

6

4

2

5

1

2

3

2

3

8

2

9

7

031

/

K

G
P
2
1

7
0

3
3

/

M

P

R

C

R

C

2

I

L

I

L

0

B

K

A

K

6

6

6

6

6

9

6

8

7

5

64

VBAT
XTAL1

63
62

VSS

61

XTAL2
MDATA

60

KDATA

59

KBLOCK/GP13

58

KBRST/GP12

57

GA20/GP11

56

VCC

55

DCDB#

54

SOUTB/PEN48

53
52

SINB

51

DTRB#

50

RTSB

49

DSRB#

48

CTSB#

47

DCDA#

46

SOUTA/PENKBC

45

SINA

44

DTRA#/PNPCSV#

43

RTSA#/HEFRAS
DSRA#

42
41

CTSA#

40

CIRRX/GP24

39

3

3

3

3

3

5

4

6

8

7

SUSCIN#/GP25

D

D

C

R

R

L

V

V

K

D

D

I

E

N

E

N

N

1

0

1

/

//

/

/

T

H

D

R

W

R

E

P

S

D

K

A

A

A

C

K

D

T

H

0

A

G

,
G
P

0

,
/

S
C

I

/

/

/

/

/

/

W

W

E

D

/

M

S

D

D

D

O

T

I

S

S

E

B

R

A

B

P

V

S

/

B

E

I

C

L

M

U

N

C

C

O

S

D

T

A

Y
E
X

P

P

/

P

V

D

D

A

D

S

C

7

6

S

5

K

P

/

P

/

P

P

P

P

D

S

D

D

D

D

0

L

1

3

4

2

I
N

I

I

/

/

/

/

I
N
I
T

R

E

A

R

S

T

F

T

R

R

X

D

B

R

X

Publication Release Date: April 2003

-5 - Revision 1.1

1.0 PIN DESCRIPTION

Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.

I/O6t - TTL level bi-directional pin with 6 mA source-sink capability

I/O8t - TTL level bi-directional pin with 8 mA source-sink capability

I/O8 - CMOS level bi-directional pin with 8 mA source-sink capability

I/O

- TTL level bi-directional pin with 12 mA source-sink capability

12t

I/O12 - CMOS level bi-directional pin with 12 mA source-sink capability

I/O

- CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor

16u

I/OD

- CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor

16u

I/O

- TTL level bi-directional pin with 24 mA source-sink capability

24t

OUT8t - TTL level output pin with 8 mA source-sink capability

OUT

- TTL level output pin with 12 mA source-sink capability

12t

OD12 - Open-drain output pin with 12 mA sink capability

OD24 - Open-drain output pin with 24 mA sink capability

INt - TTL level input pin

INc - CMOS level input pin

INcu - CMOS level input pin with internal pull-up resitor

INcs - CMOS level Schmitt-triggered input pin

INts - TTL level Schmitt-triggered input pin

IN

- TTL level Schmitt-triggered input pin with internal pull-up resistor

tsu

W83977EF

1.1 Host Interface

SYMBOL PIN I/O FUNCTION

A0−A10

74-84 IN

A11-A14 86-89 INt System address bus bits 11-14

A15 91 INt System address bus bit 15

D0−D5

D6−D7

109-114 I/O

116-117 I/O

IOR# 105 INts CPU I/O read signal

IOW# 106 INts CPU I/O write signal

AEN 107 INts System address bus enable

IOCHRDY 108 OD24 In EPP Mode, this pin is the IO Channel Ready output to extend

MR 118 INts Master Reset; Active high; MR is low during normal operations.

System address bus bits 0-10

t

System data bus bits 0-5

12t

System data bus bits 6-7

12t

the host read/write cycle.

Publication Release Date: April 2003

-6 - Revision 1.1

W83977EF

1.1 Host Interface, continued

SYMBOL PIN I/O FUNCTION

DACK0# 119 IN

GP16
(WDTO)

P15 I/O

DRQ0 121 OUT

GP17
(PLEDO)

P14 I/O

SCI# OUT

DACK1# 122 INts DMA Channel 1 Acknowledge signal

DRQ1 123 OUT

DACK2# 124 INts DMA Channel 2 Acknowledge signal

DRQ2 125 OUT

DACK3# 126 INts DMA Channel 3 Acknowledge signal

DRQ3 127 OUT

TC 128 INts Terminal Count. When active, this pin indicates termination of a

IRQ1 99 OUT

IRQ3 98 OUT

IRQ4 97 OUT

IRQ5 96 OUT

IRQ6 95 OUT

IRQ7 94 OUT

IRQ9 92 OUT

IRQ10 100 OUT

IRQ11 101 OUT

IRQ12 102 OUT

I/O

I/O

DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00,

tsu

default)

General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)

12t

Alternate function from GP16: Watch dog timer output

KBC P15 I/O port. (CR2C bit 5_4 = 10)

12t

DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default)

12t

General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01)

12t

Alternate Function from GP17: Power LED output.

KBC P14 I/O port (CR2C bit 7_6 = 10)

12t

System Control Interrupt (CR2C bit 7_6 = 11)

12t

DMA Channel 1 request signal

12t

DMA Channel 2 request signal

12t

DMA Channel 3 request signal

12t

DMA transfer.

Interrupt request 1

12t

Interrupt request 3

12t

Interrupt request 4

12t

Interrupt request 5

12t

Interrupt request 6

12t

Interrupt request 7

12t

Interrupt request 9

12t

Interrupt request 10

12t

Interrupt request 11

12t

Interrupt request 12

12t

Publication Release Date: April 2003

-7 - Revision 1.1

W83977EF

1.1 Host Interface, continued

SYMBOL PIN I/O FUNCTION

IRQ14 103 OUT

GP14 I/O

(GPACS1#) Alternate Function 1 from GP14: General purpose address

(P17) Alternate Function 2 from GP14: KBC P17 I/O port.

PLEDO OUT

IRQ15 104 OUT

GP15

(GPACS2#)

(P12) Alternate Function 2 from GP15: KBC P12 I/O port.

WDT OUT

CLKIN 1 INt 24 or 48 MHz clock input, selectable through bit 5 of CR24.

I/O

Interrupt request 14. (CR2C bit 1_0 = 00, default)

12t

General purpose I/O port 1 bit 4. (CR2C bit 1_0 = 01)

12t

decode output.

Power LED output. (CR2C bit 1_0 = 10)

12t

Interrupt request 15.(CR2C bit 3_2 = 00, default)

12t

General purpose I/O port 1 bit 5. (CR2C bit 3_2 = 01)

12t

Alternate Function 1 from GP15: General purpose address write
enable output.

Watch-Dog timer output. (CR2C bit 3_2 = 10)

12t

1.2 General Purpose I/O Port

SYMBOL PIN I/O FUNCTION

PWR_CTL# 69 OD

GP20

I/O

(KBRST)

SMI # 70 OD

GP21 I/O

(P13) Alternate Function from GP21: KBC P13 I/O port.

P16 I/O

PANSWOT#

72 OD

GP22

(P14) Alternate Function from GP22: KBC P14 I/O port.

Power supply control

16u

General purpose I/O port 2 bit 0.

16tu

Alternate Function from GP20: Keyboard reset (KBC P20)

12t

For the power management, the

management events, that generate and

is active low by the power

SMI

SCI

(CR2B bit 4_3 = 00, default)

General purpose I/O port 2 bit 1. (CR2B bit 4_3 = 01)

12t

KBC P16 I/O port. (CR2B bit 4_3 = 10)

12t

Panel Switch output. (CR2B bit 5 = 0, default)

12t

I/O

General purpose I/O port 2 bit 2. (CR2B bit 5 = 1)

12t

in ACPI mode.

Publication Release Date: April 2003

-8 - Revision 1.1

1.2 General Purpose I/O Port ,continued

SYMBOL PIN I/O FUNCTION

PANSWIN#

GP23

(P15) Alternate Function from GP23: KBC P15 I/O port

SUSC#

(GA20)

GP25 I/O12 General purpose I/O port 2 bit 5.

73 INt

I/O

12t

39 IN

Panel Switch input. (CR2B bit 7_6 = 00, default)

General purpose I/O port 2 bit 3. (CR2B bit 7_6 = 01)

Suspend C input

ts

Alternate Function from GP25: GATE A20 (KBC P21)

1.3 Serial Port Interface

SYMBOL PIN I/O FUNCTION

CTSA#

CTSB#

DSRA#

DSRB#

41

48

42

49

IN

IN

Clear To Send is the modem control input.

t

The function of these pins can be tested by reading Bit 4 of the
handshake status register.

Data Set Ready. An active low signal indicates the modem or

t

data set is ready to establish a communication link and transfer
data to the UART.

W83977EF

RTSA#

HEFRAS

RTSB#

43

During power-on reset, this pin is pulled down internally and is

50 I/O

UART A Request To Send. An active low signal informs the

I/O

8t

modem or data set that the controller is ready to send data.

defined as HEFRAS, which provides the power-on value for
CR26 bit 6 (HEFRAS). A 4.7 k
pull up. (select 370H as configuration I/O port

UART B Request To Send. An active low signal informs the

8t

modem or data set that the controller is ready to send data.

is recommended if intends to

Ω

′s address)

Publication Release Date: April 2003

-9 - Revision 1.1

1.3 Serial Port Interface, continued

SYMBOL PIN I/O FUNCTION

DTRA#

PNPCSV#

44

I/O

UART A Data Terminal Ready. An active low signal informs the

8t

modem or data set that the controller is ready to communicate.

During power-on reset, this pin is pulled down internally and is
defined as PNPCSV#, which provides the power-on value for
CR24 bit 0 (PNPCSV#). A 4.7 k
pull up. (clear the default value of FDC, UARTs, and PRT)

Ω is recommended if intends to

W83977EF

DTRB#

SINA
SINB

SOUTA

PENKBC

SOUTB

PEN48

DCDA#

DCDB#

RIA#

RIB#

51

45, 52 IN

46

53

47

54

65

66

1.4 Infrared Interface

UART B Data Terminal Ready. An active low signal informs the

I/O

8t

modem or data set that controller is ready to communicate.

Serial Input. Used to receive serial data through the

t

communication link.

I/O

UART A Serial Output. Used to transmit serial data out to the

8t

communication link.

During power-on reset, this pin is pulled down internally and is
defined as PENKBC, which provides the power-on value for
CR24 bit 2 (ENKBC). A 4.7 k
intends to pull up. (enable KBC)

I/O8t UART B Serial Output. During power-on reset, this pin is pulled

down internally and is defined as PEN48, which provides the
power-on value for CR24 bit 6 (EN48). A 4.7 k
recommended if intends to pull up.

IN

IN

Data Carrier Detect. An active low signal indicates the modem or

t

data set has detected a data carrier.

Ring Indicator. An active low signal indicates that a ring signal is

t

being received from the modem or data set.

Ω resistor is recommended if

Ω resistor is

SYMBOL PIN I/O FUNCTION

IRRX 37 INcs Infrared Receiver input.

IRTX 38 OUT

Infrared Transmitter Output.

12t

Publication Release Date: April 2003

-10 - Revision 1.1

W83977EF

1.5 Multi-Mode Parallel Port

The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.

SYMBOL PIN I/O FUNCTION

SLCT 18 INt

OD12

OD12

PE

19 INt

OD12

OD

PRINTER MODE: SLCT

An active high input on this pin indicates that the printer is
selected. This pin is pulled high internally. Refer to description of
the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

WE2#

This pin is for Extension FDD B; its function is the same as the
WE# pin of FDC.

EXTENSION 2FDD MODE: WE2#

This pin is for Extension FDD A and B; it function is the same as
the WE# pin of FDC.

PRINTER MODE: PE

An active high input on this pin indicates that the printer has
detected the end of the paper. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.

EXTENSION FDD MODE: WD2#

This pin is for Extension FDD B; its function is the same as the
WD# pin of FDC.

EXTENSION 2FDD MODE: WD2#

12

This pin is for Extension FDD A and B; its function is the same as
the WD# pin of FDC.

Publication Release Date: April 2003

-11 - Revision 1.1

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

BUSY

ACK# 22 INt

ERR#

21 INt

OD12

OD12

OD12

OD12

34

IN

OD12

OD

PRINTER MODE: BUSY

An active high input indicates that the printer is not ready to
receive data. This pin is pulled high internally. Refer to
description of the parallel port for definition of this pin in ECP and
EPP mode.

EXTENSION FDD MODE: MOB2#

This pin is for Extension FDD B; the function of this pin is the
same as the MOB# pin of FDC.

EXTENSION 2FDD MODE:MOB2#

This pin is for Extension FDD A and B; the function of this pin is
the same as the MOB# pin of FDC.

PRINTER MODE: ACK#

An active low input on this pin indicates that the printer has
received data and is ready to accept more data. This pin is
pulled high internally. Refer to description of the parallel port for
definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: DSB2#

This pin is for the Extension FDD B; its functions is the same as
the DSB# pin of FDC.

EXTENSION 2FDD MODE: DSB2#

This pin is for Extension FDD A and B; it functions is the same as
the DSB# pin of FDC.

PRINTER MODE: ERR#

t

An active low input on this pin indicates that the printer has
encountered an error condition. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.

EXTENSION FDD MODE: HEAD2#

This pin is for Extension FDD B; its function is the same as the
HEAD#pin of FDC.

12

EXTENSION 2FDD MODE: HEAD2#

This pin is for Extension FDD A and B; its function is the same as
the HEAD# pin of FDC.

W83977EF

Publication Release Date: April 2003

-12 - Revision 1.1

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

SLIN# 32 OD12

OD12

OD12

INIT#

33 OD12

OD

OD

PRINTER MODE: SLIN#

Output line for detection of printer selection. This pin is pulled
high internally. Refer to description of the parallel port for
definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:STEP2#

This pin is for Extension FDD B; its function is the same as the
STEP# pin of FDC.

EXTENSION 2FDD MODE: STEP2#

This pin is for Extension FDD A and B; its function is the same as
the STEP# pin of FDC.

PRINTER MODE: INIT#

Output line for the printer initialization. This pin is pulled high
internally. Refer to description of the parallel port for definition of
this pin in ECP and EPP mode.

EXTENSION FDD MODE: DIR2#

12

This pin is for Extension FDD B; its function is the same as the
DIR# pin of FDC.

EXTENSION 2FDD MODE: DIR2#

12

This pin is for Extension FDD A and B; its function is the same as
the DIR# pin of FDC.

AFD# 35 OD12

OD12

OD12

PRINTER MODE: AFD#

An active low output from this pin causes the printer to auto feed
a line after a line is printed. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.

EXTENSION FDD MODE: DRVDEN0

This pin is for Extension FDD B; its function is the same as the
DRVDEN0 pin of FDC.

EXTENSION 2FDD MODE: DRVDEN0

This pin is for Extension FDD A and B; its function is the same as
the DRVDEN0 pin of FDC.

W83977EF

Publication Release Date: April 2003

-13 - Revision 1.1

W83977EF

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

STB# 36 OD12 PRINTER MODE: STB#

An active low output is used to latch the parallel data into the
printer. This pin is pulled high internally. Refer to description of
the parallel port for definition of this pin in ECP and EPP mode.

- EXTENSION FDD MODE: This pin is a tri-state output.

- EXTENSION 2FDD MODE: This pin is a tri-state output.

31 I/O

PD0

INt EXTENSION FDD MODE: INDEX2#

INt EXTENSION 2FDD MODE: INDEX2#

30 I/O

PD1

29 I/O

PD2

PRINTER MODE: PD0

24t

Parallel port data bus bit 0. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.

This pin is for Extension FDD B; the function of this pin is the
same as the INDEX# pin of FDC. It is pulled high internally.

This pin is for Extension FDD A and B; the function of this pin is
the same as the INDEX# pin of FDC. It is pulled high internally.

PRINTER MODE: PD1

24t

Parallel port data bus bit 1. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.

INt

EXTENSION FDD MODE: TRAK02#

This pin is for Extension FDD B; the function of this pin is the
same as the TRAK0# pin of FDC. It is pulled high internally.

IN

EXTENSION. 2FDD MODE: TRAK02#

t

This pin is for Extension FDD A and B; the function of this pin is
the same as the TRAK0# pin of FDC. It is pulled high internally.

PRINTER MODE: PD2

24t

Parallel port data bus bit 2. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.

INt

EXTENSION FDD MODE: WP2#

This pin is for Extension FDD B; the function of this pin is the
same as the WP# pin of FDC. It is pulled high internally.

INt

EXTENSION. 2FDD MODE: WP2#

This pin is for Extension FDD A and B; the function of this pin is
the same as the WP# pin of FDC. It is pulled high internally.

Publication Release Date: April 2003

-14 - Revision 1.1

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

PD3

28 I/O

INt

INt

PRINTER MODE: PD3

24t

Parallel port data bus bit 3. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: RDATA2#
This pin is for Extension FDD B; the function of this pin is the

same as the RDATA# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: RDATA2#
This pin is for Extension FDD A and B; this function of this pin is

the same as the RDATA# pin of FDC. It is pulled high internally.

PRINTER MODE: PD4

INt

IN

24t

Parallel port data bus bit 4. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: DSKCHG2#
This pin is for Extension FDD B; the function of this pin is the

same as the DSKCHG# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: DSKCHG2#

t

27 I/O

PD4

This pin is for Extension FDD A and B; this function of this pin is
the same as the DSKCHG# pin of FDC. It is pulled high internally.

OD

-

-

-

PRINTER MODE: PD5

24t

Parallel port data bus bit 5. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.

PRINTER MODE: PD6

24t

Parallel port data bus bit 6. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

EXTENSION. 2FDD MODE: MOA2#

24

This pin is for Extension FDD A; its function is the same as the
MOA# pin of FDC.

PD5

PD6

26 I/O

24 I/O

W83977EF

Publication Release Date: April 2003

-15 - Revision 1.1

W83977EF

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

PD7

1.6 FDC Interface

SYMBOL PIN I/O FUNCTION

DRVDEN0 2 OD24 Drive Density Select bit 0.

DRVDEN1 3 OD24 Drive Density Select bit 1. (CR2A bit 1_0 = 00, default)

GP10 IO

(IRQIN1) Alternate Function from GP10: Interrupt channel input.

P12 IO

SCI# OUT

HEAD# 5 OD24 Head select. This open drain output determines which disk drive

WE# 9 OD24 Write enable. An open drain output.

WD# 10 OD24 Write data. This logic low open drain writes pre-compensation

STEP# 11 OD24 Step output pulses. This active low open drain output produces

DIR# 12 OD24 Direction of the head step motor. An open drain output.

MOB# 13 OD24 Motor B On. When set to 0, this pin enables disk drive 1. This is

23 I/O

OD

PRINTER MODE: PD7

24t

Parallel port data bus bit 7. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

-

EXTENSION 2FDD MODE: DSA2#

24

This pin is for Extension FDD A; its function is the same as the
DSA# pin of FDC.

General purpose I/O port 1 bit 0. (CR2A bit 1_0 = 01)

24t

KBC P12 I/O port. (CR2A bit 1_0 = 10)

24t

System Control Interrupt (CR2A bit 1_0 = 11)

12t

head is active.
Logic 1 = side 0
Logic 0 = side 1

serial data to the selected FDD. An open drain output.

a pulse to move the head to another track.

Logic 1 = outward motion

Logic 0 = inward motion

an open drain output.

Publication Release Date: April 2003

-16 - Revision 1.1

W83977EF

1.6 FDC Interface, continued

SYMBOL PIN I/O FUNCTION

DSA# 14 OD24 Drive Select A. When set to 0, this pin enables disk drive A.

This is an open drain output.

DSB# 15 OD24 Drive Select B. When set to 0, this pin enables disk drive B.

This is an open drain output.

MOA# 16 OD24 Motor A On. When set to 0, this pin enables disk drive 0. This is

an open drain output.

DSKCHG# 4 INcs Diskette change. This signal is active low at power on and

whenever the diskette is removed. This input pin is pulled up
internally by a 1 K
7 of L0-CRF0 (FIPURDWN).

RDATA# 6 INcs The read data input signal from the FDD. This input pin is pulled

up internally by a 1 K
bit 7 of L0-CRF0 (FIPURDWN).

WP# 7 INcs Write protected. This active low Schmitt input from the disk drive

indicates that the diskette is write-protected. This input pin is
pulled up internally by a 1 K
disabled by bit 7 of L0-CRF0 (FIPURDWN).

TRAK0# 8 INcs Track 0. This Schmitt-triggered input from the disk drive is active

low when the head is positioned over the outermost track. This
input pin is pulled up internally by a 1 K
can be disabled by bit 7 of L0-CRF0 (FIPURDWN).

INDEX# 17 INcs This Schmitt-triggered input from the disk drive is active low

when the head is positioned over the beginning of a track marked
by an index hole. This input pin is pulled up internally by a 1 K
resistor. The resistor can be disabled by bit 7 of L0-CRF0
(FIPURDWN).

Ω resistor. The resistor can be disabled by bit

Ω resistor. The resistor can be disabled by

Ω resistor. The resistor can be

Ω resistor. The resistor

Ω

Publication Release Date: April 2003

-17 - Revision 1.1

W83977EF

1.7 KBC Interface

SYMBOL PIN I/O FUNCTION

KDATA 59 I/O

MDATA 60 I/O

KCLK 67 I/O

MCLK 68 I/O

GA20 56 I/O

GP11 I/O

(IRQIN2) Alternate Function from GP11: Interrupt channel input.

KBRST 57 I/O

GP12 I/O

(WDTO) Alternate Function 1 from GP12 : Watchdog timer output.

KBLOCK 58 INts W83C45 KINH (P17) Input. (CR2B bit 0 = 0, default)

GP13 I/O

Keyboard Data

16u

PS2 Mouse Data

16u

Keyboard Clock

16u

PS2 Mouse Clock

16u

KBC GATE A20 (P21) Output. (CR2A bit 6 = 0, default)

12t

General purpose I/O port 1 bit 1. (CR2A bit 6 = 1)

12t

W83C45 Keyboard Reset (P20) Output. (CR2A bit 7 = 0, default)

12t

General purpose I/O port 1 bit 2. (CR2A bit 7 = 1)

12t

General purpose I/O port 1 bit 3. (CR2B bit 0 = 1)

16t

1.8 POWER PINS

SYMBOL PIN FUNCTION

VCC 20, 55, 85,

+5V power supply for the digital circuitry

115

VSB 71 +5V stand-by power supply for the digital circuitry

GND 25, 62, 90,

Ground

120

1.9 ACPI Interface

SYMBOL PIN I/O FUNCTION

VBAT 64 NA battery voltage input

XTAL1 63 INC 32.768Khz Clock Input

XTAL2 61 O8t 32.768Khz Clock Output

Publication Release Date: April 2003

-18 - Revision 1.1

W83977EF

2.0 FDC FUNCTIONAL DESCRIPTION

2.1 W83977EF FDC

The floppy disk controller of the W83977EF integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to 2 M bits/sec data rate.

The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.

2.1.1 AT interface

The interface consists of the standard asynchronous signals:RD#, WR#, A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.

2.1.2 FIFO (Data)

The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and
DIO bits in the Main Status Register.

The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage
of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with a FIFO. The data are based upon the following
formula:

THRESHOLD #

× (1/DATA/RATE) *8 - 1.5 µS = DELAY

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500K BPS

1 Byte
2 Byte
8 Byte

15 Byte

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1M BPS

1 Byte
2 Byte
8 Byte

15 Byte

-19 - Revision 1.1

Data Rate

× 16 µS - 1.5 µS = 14.5 µS

1

16 µS - 1.5 µS = 30.5 µS

2

×

8

× 16 µS - 1.5 µS = 6.5 µS

16 µS - 1.5 µS = 238.5 µS

15

×

Data Rate

1

× 8 µS - 1.5 µS = 6.5 µS

8 µS - 1.5 µS = 14.5 µS

2

×

8

× 8 µS - 1.5 µS = 62.5 µS

15

8 µS - 1.5 µS = 118.5 µS

×

Publication Release Date: April 2003

W83977EF

At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.

An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.

DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the
DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK# and
addresses need not be valid.

Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed
by the FDC based only onDACK#. This mode is only available when the FDC has been configured
into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above
operation is performed by using the new VERIFY command. No DMA operation is needed.

¡

2.1.3 Data Separator

The function of the data separator is to lock onto the incoming serial read data. When a lock is
achieved the serial front end logic of the chip is provided with a clock which is synchronized to the
read data. The synchronized clock, called the Data Window, is used to internally sample the serial
data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel
conversion logic separates the read data into clock and data bytes.

The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized
and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for
every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on
speed. A digital integrator is used to keep track of the speed changes in the input data stream.

2.1.4 Write Precompensation

The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk
drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media
and the floppy drive.

The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known. Depending upon the pattern, the bit is shifted either early or late
relative to the surrounding bits.

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W83977EF

2.1.5 Perpendicular Recording Mode

The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented
vertically. This scheme packs more data bits into the same area.

FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.

A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the
FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.

2.1.6 FDC Core

The W83977EF FDC is capable of performing twenty commands. Each command is initiated by a
multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.

Command

The microprocessor issues all required information to the controller to perform a specific operation.

Execution

The controller performs the specified operation.

Result

After the operation is completed, status information and other housekeeping information is provided to
the microprocessor.

2.1.7 FDC Commands

Command Symbol Descriptions:

C: Cylinder number 0 - 256

D: Data Pattern

DIR: Step Direction

DIR = 0, step out

DIR = 1, step in

DS0: Disk Drive Select 0

DS1: Disk Drive Select 1

DTL: Data Length

EC: Enable Count

EOT: End of Track

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EFIFO: Enable FIFO

EIS: Enable Implied Seek

EOT: End of track

FIFOTHR: FIFO Threshold

GAP: Gap length selection

GPL: Gap Length

H: Head number

HDS: Head number select

HLT: Head Load Time

HUT: Head Unload Time

LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset

MFM: MFM or FM Mode

MT: Multitrack

N: The number of data bytes written in a sector

NCN: New Cylinder Number

ND: Non-DMA Mode

OW: Overwritten

PCN: Present Cylinder Number

POLL: Polling Disable

PRETRK: Precompensation Start Track Number

R: Record

RCN: Relative Cylinder Number

R/W: Read/Write

SC: Sector/per cylinder

SK: Skip deleted data address mark

SRT: Step Rate Time

ST0: Status Register 0

ST1: Status Register 1

ST2: Status Register 2

ST3: Status Register 3

WG: Write gate alters timing of WE

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(1) Read Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 0 1 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0

W

W

W -------------------- DTL -----------------------

Execution Data transfer between the

Result R

R

W

W

W

W

R

R

R

R

R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information prior
to command execution

FDD and system

Status information after
command execution

Sector ID information after
command execution

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(2) Read Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 1 1 0 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0

W

W

W

W

W

W

W -------------------- DTL -----------------------

Execution Data transfer between the

Result R

R

R

R

R

R

R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information prior
to command execution

FDD and system

Status information after
command execution

Sector ID information after
command execution

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