Winbond Electronics W83759A Datasheet

W83759A

ADVANCED VL-IDE DISK CONTROLLER

GENERAL DESCRIPTION

The W83759A is an advanced version of Winbond's popular VL-IDE interface chip, the W83759. The W83759A retains all of the features and compatibility of the W83759 (the chip meets the ANSI ATA

4.0 specification for IDE hard disk operation and the VESA VL-Bus 2.0 specification for PC local bus devices) while incorporating new features to meet Enhanced IDE, SFF-8011, ATA-2, and Fast-ATA specifications.

Supports Disk Capacity of Greater than 528 MB

The W83759A's driver can handle remapping from BIOS CHS mode to HDD LBA mode. This scheme enables users to break the 528 MB per drive barrier, allowing full use of BIOS INT13 CHS information in drives with a capacity of up to 8.4 GB.

High Speed Host Transfer Rate

The W83759A supports Enhanced IDE PIO mode 3 and Fast ATA PIO mode 3 and 4 timing; jumper settings or driver programming can be used to select the PIO mode and a 33 or 50 MHz VL-Bus clock. Different programming timing can be selected for different drives in the same system. The burst transfer rate is shown in the following table.

ATA PIO

MODE

0 600 3.33 Option 1 383 5.22 Option 2 240 8.33 Option 3 180 11.1 Required 4 120 16.6 Required

IDE COMMAND CYCLE

TIME (nS)

BURST TRANSFER

RATE (MB/sec)

IORDY THROTTLE

CONTROL

Dual IDE Channels

Like the W83759, the W83759A supports a secondary IDE address (170h-177h/376h) and IRQ15 for applications with four hard disk drives. Additionally, the primary and secondary channels can be independently enabled or disabled by jumper settings or software programming.

Non-disk IDE Peripherals

Because the command cycle can be programmed individually for each drive and dual IDE channels are supported, non-disk IDE peripherals (such as an ATAPI CD-ROM or tape drive) can be attached to the secondary IDE without affecting the transfer rate of the ATA disk drive. Sales of ATAPI IDE CD-ROMs are expected to grow rapidly as these devices become a standard part of many users' desktop PC setup.

Publication Release Date: May 1995

- 1 - Revision A1

Enhanced IDE/Fast ATA Dual Channel Structure

W83759A

Primary Channel

40-pins

Disk

< 8.4 GB

PD0

The W83759A provides all of the next-generation ATA-IDE requirements, including support for high capacity disk drives, high speed host transfers, multiple IDE peripherals, and non-disk IDE peripherals. It makes high-performance, low-cost, easy-to-use IDE machines possible.

The W83759A is pin-to-pin backward compatible with the W83759. In addition to the advanced features described above, the W83759A supports automatic power-down, standby, and suspend APM power management states for green PC applications. This new chip is packaged in a 100-pin QFP.

The table below compares the W83759 and W83759A:

Dual Channel IDE Yes Yes

8.4 G Max. Cap. Software Driving Software Driving

Disk

< 8.4 GB

PD1

W83759 W83759A

Secondary Channel

40-pins

CD ROM

ATAPI ATAPI

SD0

SD1

Tape

PIO Mode 3, 4 Control No Yes* DMA Mode Control No Yes* IOCHRDY Control No Yes* IDE Timing Control Jumper Jumper or Driver* Prefetch Control No Yes* Power Saving Control No Yes* ATAPI Protocol Software Driving Software Driving

* All control is drive-by-drive (per drive selectability)

- 2 -

W83759A

FEATURES

• Pin-to-pin backward compatible with W83759 VL-IDE Interface chip

• VESA VL-Bus Rev 2.0 compatible, connects directly to local bus and four IDE drives

• Direct interface to various ANSI ATA/ATA-2/FAST ATA/IDE-2/Enhanced IDE drives

• Supports 32 and 16-bit data transfer

• Fully software programmable for command active/recovery time and address setup, data hold

time

• Built-in VL-Bus to 16-bit IO data buffer for special applications

• Fully supports Enhanced IDE features, including Fast PIO, Mode 3/4, IORDY flow control,

prefetch control

• Supports dual channels to allow up to four drives or non-disk devices (ATAPI CD-ROM and tape

drives)

• Pipeline pre-fetched reads and posted writes for concurrent disk and host operations

• Independent access timing for all drives (primary/secondary and master/slave)

• All Enhanced IDE new features may be disabled/enabled via driver or power-on setting by per

drive selectability

• ATA/Mode 0-4 PIO speed may be set as default timing of each drive via power-on jumper setting

• Supports slave DMA mode protocol (reserved)

• Supports auto power-down, standby, suspend APM power management state for green PCs

• Primary and secondary channel can be independently enabled/disabled by software or jumper

setting

• Supports drivers for DOS, Windows, OS/2, UNIX, and Netware

• Packaged in 100-pin QFP

Publication Release Date: May 1995

- 3 - Revision A1

PIN CONFIGURATION

I

D

7

8

Sa

m

mp

pl

le

e

Te

xt

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

X

IDD6 IDD5 IDD4 IDD3 IDD2

IDD1

IDD0

GND

LCLK

GND

Vcc LDEV LRDY

RDYRTN

LADS

HWR

HMIO

IORDY/HDC

SYSRST

ADV

81

X

82

X

83

X

84

X

85

X

86

X

87

X

88

X

89

X

90

X

91

X

92

X

93

X

94

X

95

X

96

X

97

X

98

X

99

X

100

1 2 3 4 5

Sa

m

mp

pl

le

e

Te

xt

W83759A

/ I

E

S

T

N

E

I

S

D

T

I

D

/

E

/

I

D

1

9

1

2

0

Sa

Sa mp

mpl

mp

le

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Te

Tex

Te

t

xt

6 7 8 9

Sa

mpl

mp

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Tex

Te

xt

t

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I

D

E

D

I

1

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3

4

5

W

Sa

mpl

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Tex

t

10 11 12 13 14 15 16

Sa

mpl

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Tex

t

Sa mp le Te xt

E

I

A

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2

1

0

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,

M

S

I

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P

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0

1

R

1

Sa

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C

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Sa mp le Te xt

17 18 19 20 21 22 23 24 25 26 27 28 29 30

Sa mp le Te xt

/

D

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A

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C

H

K

/

,

/

I

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I

D

V

D

E

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0

A

O

C

S

E

S

D

L

H

1

0

7

XXXXX

XXXXX XXXXX XXXXX

S

D

5

6

XXXXX XXXXX

S

D

2

1

4

3

0

X

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

AEN

X

XIOW

X

XIOR

X

SA1

X

SA0

X

HD0

X

HD1

X

HD2

X

HD3

X

Vcc

X

GND

X

HD4

X

HD5

X

HD6

X

HD7

X

HD8

X

HD9

X

HD10

X

HD11

X

HD12

/

H

B

A

E

2

0

H

G

H

A

3

4

5

A

6

9

7

8

H

D

3

2

1

0

9

8

H

N

D

2

7

6

5

D

2

4

3

2

1

H

D

2

1

0

9

8

7

H

D

1

6

5

4

3

- 4 -

PIN DESCRIPTION

SYSRST

LADS

HDC

HMIO

HWR

BE2

BE0

BE2

LDEV

LRDY

SYMBOL PIN TYPE DESCRIPTION

VL-Bus Interface

ADV 100 I-PU Advanced mode indicator.

When high, chip is in W83759A mode. When low, chip is in W83759 mode.

LCLK 89 I VL-Bus clock.

99 I System reset.

When active, the power-on setting pin acts as input.

95 I Address data strobe.

An active low input signal indicates that there is a valid address and command on the bus.

W83759A

IORDY

/

98 I In W83759A mode: Enhanced IDE IORDY flow control input. Used

to throttle disk's PIO data transfers to improve PIO mode. In W83759 mode: Host data or code status. Used to distinguish between IO and interrupt or halt cycles.

97 I-PU Host memory or I/O status.

Used to distinguish between memory and I/O cycles.

96 I Host write or read status.

Used to distinguish between write and read cycles. 1 2

92 O Local device.

93 Tri-O Local ready.

I Byte enable bits 2 and 0 from the host CPU address bus.

These active low inputs specify which bytes will be valid for host

read and write data transfers. When

a 32-bit hard disk data transfer cycle when

An active low output signal which indicates that the current host

CPU command cycle is a valid W83759A I/O address (1F0h or

170h).

An active low output that indicates when a CPU transfer has been

completed. During a cycle

high. When the cycle is completed,

pulled low and will remain active for one T-state. Then it will drive

high for one T-state before finally being disabled to end the

sequence.

This signal is shared with all other VL-Bus targets and driven by

W83759A only during cycles W83759A has claimed as its own.

will first be enabled and driven

is low, the host performs

is active.

will immediately be

Publication Release Date: May 1995

- 5 - Revision A1

Pin Description, continued

RDYRTN

RDY

[

]

VGAOEH

VGAOEL

IDE0CS0

SYSRST

IDE0CS0

SYSRST

IDE0CS1

SYSRST

IDE0CS1

SYSRST

SYMBOL PIN TYPE DESCRIPTION

94 I Ready return.

An active low signal that indicates the end of the current host CPU transfer.

Usually CPU.

HA[9:2] 10-3 I Host address bits 9 through 2 from the host address bus.

is tied directly to the

signal of the host

W83759A

HD[31:0]

PRDYEN

/

SRDYEN

/

11−14 19−39 42−45

61 I/O

62 I/O

I/O Host data.

This is the 32-bit bidirectional data bus that connects to the host CPU. HD[7:0] define the lowest data byte, while D[31:24] define

the most significant byte by the normally in a high-impedance state and is driven by the

W83759A only during data register (1F0h or 170h) read cycles and VGA (

When

-PU

rising edge of PRDYEN: A high input enables the IORDY flow control function of

the primary channel (IDE0) and a low input disables the IDE0's flow control function.

output used to select the command block registers in the IDE0 drive (1F0h−1F7h).

When rising edge of

SRDYEN: A high input enables the IORDY flow control function of the secondary channel (IDE1) and a low disables the IDE1's flow control function.

= 0 or

Drive Interface

is active, this is an input that latches on the

: When

is active, this is an input that latches on the

BE 2:0 signals. The HD bus is

= 0) read cycles.

.

is inactive, this pin is an active low

.

: When output used to select the alternate status register of the control block registers in the IDE0 drive (3F6).

- 6 -

is inactive, this pin is an active low

Pin Description, continued

IDE1CS0

SYSRST

IDE1CS0

SYSRST

IDE1CS1

SYSRST

IDE1CS1

SYSRST

EMD

1

IDEIOR

SYSRST

EMD1

EMD

0

IDEIOR

EMD1

EMD

0

SYMBOL PIN TYPE DESCRIPTION

W83759A

ENIDE

/

TEST

/

63 I/O

-PU

64 I/O

-PU

70 I/O

-PU

When edge of

ENIDE: In W83759 mode (ADV = low), this power-on-setting pin controls if the chip enable or disable. In W83759A mode (ADV = high), this pin controls if the IDE0 channel enable or disable. A high input enables and a low input disables the IDE0 channel.

output and is used to select the command block registers in the IDE1 drive (170h−177h).

When edge of

TEST: In W83759 mode, this power-on-setting pin controls whether both dual channels are enabled or only the primary channel is enabled. A high input enables IDE0 and IDE1 simultaneously and a low input enables IDE0 only. In W83759A mode, this pin controls whether the IDE1 channel enable or disable controls the IDE0 channel as ENIDE.

output used to select the alternate status register of the control block registers in the IDE1 drive (376).

When edge of

is active, this is an input that latches on the rising

.

: When

is active, this is an input that latches on the rising

.

: When

is active, this is an input that latches on the rising

.

is inactive, this pin is an active low

: This power-on-setting pin combines with initial enhanced timing mode of hard disk access cycles when the enhanced mode is selected via the POSS3 configuration register.

: Drive I/O read. An active low output that enables data to

be read from the drive. The duration and repetition rate of cycles are determined by the type of IDE drive, as specified by

MD1 and MD0, in W83759 mode or by W83759A enhanced mode.

Publication Release Date: May 1995

- 7 - Revision A1

and

to set the

in

Pin Description, continued

EMD

0

IDEIOW

SYSRST

EMD

0

EMD

1

IDEIOW

IDEIOR

SYSRST

SYMBOL PIN TYPE DESCRIPTION

W83759A

/

MD1

/IDEA2,

MD0

/IDEA1

71 I/O

-PU

69

I/O

-PD

68

When edge of

: This power-on-setting pin combines with

is active, this is an input that latches on the rising

.

to set the initial enhanced timing mode of hard disk access cycles when the enhanced mode is selected via the POSS3 configuration register.

ATA PIO mode

2

3

4

Access Time

240 nS

180 nS

120 nS

EMD1

1

0

EMD0

1

0

1

0

: Drive I/O write. An active low output that enables data to

be written to the drive. The duration and repetition rate of cycles are determined by the type of IDE drive, as specified by

.

When on the rising edge of

is active, these pins function as inputs and latch

.

MD1, MD0: ATA mode of IDE Drive. MD0 and MD1 are used to select the hard disk access time.

ATA PIO mode

0

0+

1

2

Access Time

600 nS

500 nS

400 nS

240 nS

EMD1

0

1

EMD0

0

1

0

1

IDEA2, IDEA1: IDE drive address bits 2 and 1. Drive address bits 2 and 1 are outputs to the IDE connector for register selection in the drive.

- 8 -

Pin Description, continued

SYSRST

VGAOEH

VGAOEL

XIOR

XIOW

SYMBOL PIN TYPE DESCRIPTION

W83759A

SP1

/IDEA0

IDD[15:0]

SA[1:0] 47, 46 I ISA address bits 1 and 0.

67 I/O

72−87

-PD

I/O

-PU

When rising edge of

SP1: VL-Bus speed select. A high input configures the W83759A to run at from 33 MHz to 50 MHz; a low input configures the W83759A to run at under 33 MHz.

IDEA0: IDE drive address bit 0. Drive address bit 0 is output to the IDE connector for register selection in the drive.

When on the rising edge of

As power-on setting pins, IDD[15:8] are latched to the POSS3 register and IDD[7:0] are latched to the POSS2 register.

As the drive data bus, bits 15 through 0 are the 16-bit bidirectional data bus that connects to the IDE drive.

IDD[7:0] define the lowest data byte. The IDD bus is normally in a pull-high state and is driven with valid data by the W83759A only

during IDE or VGA (

ISA-Bus Interface

Used to select the hard disk I/O registers.

is active, this pin is an input that latches on the

is active, these pins function as inputs and latch

= 0) write cycles.

.

= 0 or

SD[7:0] 58-51 I/O These signals provide data bus bits 0 through 7 for the CPU and

IDE I/O devices. SD0 is the least significant bit and SD7 is the most significant bit.

48 I

49 I

AEN 50 I When this line is active (high), the DMA controller has control of

instructs the hard disk I/O device to drive its data onto the

SD data bus.

instructs the hard disk I/O device to read the data on the

SD data bus.

the address bus. A low is the address enable.

Publication Release Date: May 1995

- 9 - Revision A1

Pin Description, continued

SUSP

DACK

VGAOEH

SUSP

DACK

VGAOEH

DMASL

VGAOEL

ISDENH

SYSRST

DMASL

VGAOEL

ISDENH

SYMBOL PIN TYPE DESCRIPTION

Special Bus Control Interface

W83759A

, ,

59 I-PU This pin is a multi-function input pin.

: In suspend enable mode, indicates that the W83759A will enter the suspend state when low and resume operation when high.

: In DMA transfer enable mode, used to indicate when the

DMA transfer cycle occurs.

: In VGA buffer enable mode, this active low input controls the input enable for the data transceivers that connect the ID[15:0] pins to the HD[31:16] pins.

,

/

60 I/O

-PU

When rising edge of

: This power-on setting pin combines with SUSPEN

is active, this pin is an input that latches on the

.

(IDD11 power-on setting pin) to determine which mode the W83759A is in.

DMASL

1

0

SUSPEN

X

1

0

Mode

VGA buffer enable

Suspend enable

DMA transfer enable

Vcc 41, 65,

91

GND 15, 40,

66, 88, 90

: In VGA buffer enable mode, this active low input controls the input enable for the data transceivers that connect the ID[15:0] pins to the HD[15:0] pins.

: In DMA transfer enable mode, this output pin controls the activity of the high byte buffer between IDD[15:8] and SD[15:8].

+5V power supply

Ground reference

- 10 -

W83759A

CONFIGURATION REGISTERS

Several configuration registers are implemented in the W83759A. These registers are accessible in single-chip mode through the index/data port. The index/data port address is 1B4h/1B8h or 134h/138h, depending on whether pin IDD0 is high or low at power-on.

When the W83759A is in multi-chip mode (IDD1 is low at power-on setting), an ID code should be written to 1B0h/130h (IDIN port). The W83759A will then enter the programming sequence if the ID code matches the chip ID (determined by IDD2, IDD3 at power-on setting) or leave the programming sequence if the ID code does not match. After the chip has entered the programming sequence, the chip ID can be read by reading 1BCh/13Ch (IDOUT port).

IDD0_P is HIGH IDD0_P is LOW IDIN port (W/O) 1B0h* 130h** Index port (R/W) 1B4h 134h data port (R/W) 1B8h 138h IDOUT port (R/O) 1BCh 13Ch

* The alias base addresses of 1B0h are XB0h and YB0h, where "X" means 0, 4, 8, C and "Y" means 1, 5, 9, D. ** The alias base addresses of 130h are X30h and Y30h, where "X" means 0, 4, 8, C and "Y" means 1, 5, 9, D.

Index map of configuration registers:

INDEX Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 80h(R/O)

POSS1 81h(R/W) POSP1 82h(R/O) POSS2 83h(R/W) POSP2 84h(R/O) POSS3 85h(R/W) POSP3 86h(R/W) ALTCTL 87h(R/O) REVID 88h(R/W) PD0TIM0 89h(R/W) PD0TIM1 8Ah(R/W) PD1TIM0 8Bh(R/W) PD1TIM1 8Ch(R/W) SD0TIM0 8Dh(R/W) SD0TIM1 8Eh(R/W) SD1TIM0 8Fh(R/W) SD1TIM1

ADV SP1 MD1 MD0 PRDYEN SRDYEN IDEN1 IDEN0 8Fh

ADV_P SP1_P MD1_P MD0_P PRDYEN_P SRDYEN_P IDEN1_P IDEN0_P 8Fh

PD0LEN PD1LEN SD0LEN SD1LEN DSL1 DSL0 CRLK# CRSL FFh

PD0LE_P PD1LEN_P SD0LEN_P SD1LEN_P DSL1_P DSL0_P CRLK#_P CRSL_P FFh

PD0EM# PD1EM# SD0EM# SD1EM# SUSPEN STBY# APD SWAP# FFh PD0EM#_P PD1EM#_P SD0EM#_P SD1EM#_P SUSPEN_P STBY#_P APD_P SWAP#_P FFh DMASL#_PReserved EMD1 EMD0 PEMD1_P PEMD0_P SEMD1_P SEMD0_P 80h

DMASL# Reserved PDRV SDRV Rev 3 Rev 2 Rev 1 Rev 0 8Ah

PD0ACT3 PD0ACT2 PD0ACT1 PD0ACT0 PD0RCV3 PD0RCV2 PD0RCV1 PD0RCV0 00h PD0AST1 PD0AST0 PD0DHT1 PD0DHT0 PD0PRE# PD0DMA# PD0RDY# PD0ADV 00h PD1ACT3 PD1ACT2 PD1ACT1 PD1ACT0 PD1RCV3 PD1RCV2 PD1RCV1 PD1RCV0 00h PD1AST1 PD1AST0 PD1DHT1 PD1DHT0 PD1PRE# PD1DMA# PD1RDY# PD1ADV 00h SD0ACT3 SD0ACT2 SD0ACT1 SD0ACT0 SD0RCV3 SD0RCV2 SD0RCV1 SD0RCV0 00h SD0AST1 SD0AST0 SD0DHT1 SD0DHT0 SD0PRE# SD0DMA# SD0RDY# SD0ADV 00h SD1ACT3 SD1ACT2 SD1ACT1 SD1ACT0 SD1RCV3 SD1RCV2 SD1RCV1 SD1RCV0 00h SD1AST1 SD1AST0 SD1DHT1 SD1DHT0 SD1PRE# SD1DMA# SD1RDY# SD1ADV 00h

Value

Publication Release Date: May 1995

- 11 - Revision A1

W83759A

CRX80h (POSS1) Read Only Power-on Setting Status 1

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

ADV SP1 MD1 MD0 PRDYEN SRDYEN IDEN1 IDEN0

Bit 7 ADV Power-on setting value of ADV pin

Initial application mode

0 1

Bit 6 SP1 Power-on setting value of IDEA0 pin

0 1

Bit 5, 4 MD1, MD0 Power-on setting value of IDEA2, IDEA1 pin

Bit 3 PRDYEN Power-on setting value of IDE0CS0 pin

Bit 2 SRDYEN Power-on setting value of IDE0CS1 pin

No advanced mode application Advanced mode application

Select VESA bus operating CLK VLCLK 33 MHz

VLCLK > 33 MHz

Default HDD host transfer mode MD1 MD0 0 0 Mode 0 (cycle time = 600 nS) 0 1 Mode 0+ (cycle time = 500 nS) 1 0 Mode 1 (cycle time = 400 nS) 1 1 Mode 2 (cycle time = 240 nS)

Initial state of primary channel IOCHRDY flow control 0 Disable IOCHRDY flow control 1 Enable IOCHRDY flow control

Initial state of secondary channel IOCHRDY flow control 0 Disable IOCHRDY flow control 1 Enable IOCHRDY flow control

Bit 1, 0 IDEN1, IDEN0 Power-on setting value of IDE1CS1, IDE1CS0 pins

Initial state of IDE ENable control

when ADV_P = 0

IDEN1 IDEN0 Primary IDE Secondary IDE X 0 disabled disabled 0 1 enabled disabled 1 1 enabled enabled

- 12 -

W83759A

Continued

when ADV_P = 1

CRX81h (POSP1) Read / Write Power-on Setting Programming 1

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADV_P SP1_P MD1_P MD0_P PRDYEN_P SRDYEN_P IDEN1_P IDEN0_P

After power-on, the content of the POSP1 register is equal to that of the POSS1 register. The host can program POSP1 to modify the power-on settings.

Bit 7 ADV_P Programming application mode

IDEN1 IDEN0 Primary IDE Secondary IDE 0 0 disabled disabled

1 0 disabled enabled 0 1 enabled disabled 1 1 enabled enabled

0 No advanced mode application 1 Advanced mode application

Bit 6 SP1_P Select VESA bus operating CLK

0 VLCLK 33 MHz 1 VLCLK > 33 MHz

Bit 5, 4 MD1_P,

MD0_P

Bit 3 PRDYEN_P Primary channel IOCHRDY flow control

Bit 2 SRDYEN_P Secondary channel IOCHRDY flow control

Bit 1, 0 IDEN1_P,

IDEN0_P

Select default HDD host transfer mode MD1_P MD0_P 0 0 Mode 0 (cycle time = 600 nS) 0 1 Mode 0+ (cycle time = 500 nS) 1 0 Mode 1 (cycle time = 400 nS) 1 1 Mode 2 (cycle time = 240 nS)

0 Disable IOCHRDY flow control 1 Enable IOCHRDY flow control

IDE ENable control

Publication Release Date: May 1995

- 13 - Revision A1