Winbond Electronics W83697HF Datasheet
W83697HF/F
WINBOND I/O
W83697HF/F Data Sheet Revision History
1 n.a. 08/23/99 0.40
2 98, 107, 116 11/15/99 0.41 H/W monitor register correction
3 All 11/15/2000 0.50 New composition
4
5
6
7
8
9
10
Pages Dates Version
All
9/3/2001 0.6
2/19/2002 0.7 New Update
Version
on Web
Main Contents
First published.
For Beta Site customers only
Add W83697F pin assignment & Notice
Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Winbond customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Winbond for any damages resulting
from such improper use or sales.
W83697HF/F
TABLE OF CONTENTS
GENERAL DESCRIPTION.....................................................................................................1
1. PIN DESCRIPTION.....................................................................................................5
1.1 LPC INTERFACE................................................................................................................................................................6
1.2 FDC INTERFACE ................................................................................................................................................................7
1.3 MULTI-MODE PARALLEL PORT...................................................................................................................................8
1.4 SERIAL PORT INTERFACE............................................................................................................................................13
1.5 INFRARED PORT............................................................................................................................................................. 14
1.6 FRESH ROM INTERFACE ..............................................................................................................................................14
1.7 HARDWARE MONITO R INTERFACE........................................................................................................................ 15
1.8 GAME PORT & MIDI PORT...........................................................................................................................................16
1.9 POWER PINS.....................................................................................................................................................................17
2. LPC (LOW PIN COUNT) INTERFACE.....................................................................18
3. FDC FUNCTIONAL DESCRIPTION........................................................................19
3.1 W83697HF FDC.................................................................................................................................................................19
3.1.1 AT interface...............................................................................................................................................................19
3.1.2 FIFO (Data)..............................................................................................................................................................19
3.1.3 Data Separator.........................................................................................................................................................20
3.1.4 Write Precompensation...........................................................................................................................................20
3.1.5 FDC Core ..................................................................................................................................................................21
3.1.6 FDC Commands.......................................................................................................................................................21
3.1.7 FDC Commands.......................................................................................................................................................21
3.2 REGISTER DESCRIPTIONS............................................................................................................................................34
3.2.1 Status Register A (SA Register) (Read base address + 0)...............................................................................34
3.2.2 Status Register B (SB Register) (Read base address + 1)...............................................................................36
3.2.3 D igital Output Register (DO Register) (Write base address + 2)..................................................................38
3.2.4 Tape Drive Register (TD Register) (Read base address + 3)..........................................................................38
3.2.5 Main Status Register (MS Register) (Read base address + 4).......................................................................39
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W83697HF/F
3.2.6 Data Rate Register (DR Register) (Write base address + 4)...........................................................................40
3.2.7 FIFO Register (R/W base address + 5)................................................................................................................41
3.2.8 Digital Input Register (DI Register) (Read base address + 7).......................................................................44
3.2.9 Configuration Control Register (CC Register) (Write base address + 7)....................................................45
4. UART PORT.................................................................................................................46
4.1 UNIVERSAL ASYNCHRONOUS REC EIVER/TRANSMITTER (UART A, UART B)...........................................46
4.2 REGISTER ADDRESS......................................................................................................................................................46
4.2.1 UART Control Register (UCR) (Read/Write).....................................................................................................46
4.2.2 UART Status Register (USR) (Read/Write).........................................................................................................48
4.2.3 Handshake Control Register (HCR) (Read/Write)...........................................................................................50
4.2.4 Handshake Status Register (HSR) (Read/Write)...............................................................................................51
4.2.5 UART FIFO Control Register (UFR) (Write only) .............................................................................................52
4.2.6 Interrupt Status Register (ISR) (Read only).......................................................................................................53
4.2.7 Interrupt Control Register (ICR) (Read/Write).................................................................................................54
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)..............................................................................54
4.2.9 Use r-defined Register (UDR) (Read/Write)........................................................................................................55
5. CIR RECEIVER PORT...............................................................................................56
5.1 CIR REGISTERS................................................................................................................................................................56
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read) ....................................................................................56
5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR) ................................................................................................56
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR)....................................................................................................56
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)........................57
5.1.5 Bank0.Reg4 - CIR Control Register (CTR) .........................................................................................................58
5.1.6 Bank0.Reg5 - UART Line Status Register (USR) ..............................................................................................59
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG)...........................................................................59
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) ..........................................................................................60
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL).....................................................................................61
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID).......................................................................................................62
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3).....................62
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)..............................................................................................62
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH)............................................................................................62
6. PARALLEL PORT......................................................................................................63
6.1 PRINTER INTERFACE LOGIC ........................................................................................................................................ 63
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- II - Revision 0.70
W83697HF/F
6.2 ENHANCED PARALLEL PORT (EPP)..........................................................................................................................64
6.2.1 Data Swapper...........................................................................................................................................................65
6.2.2 Printer Status Buffer................................................................................................................................................65
6.2.3 Printer Control Latch and Printer Control Swapper.......................................................................................66
6.2.4 EPP Address Port.....................................................................................................................................................66
6.2.5 EPP Data Port 0-3...................................................................................................................................................67
6.2.6 Bit Map of Parallel Port and EPP Registers......................................................................................................67
6.2.7 EPP Pin Descriptions..............................................................................................................................................68
6.2.8 EPP Operation.........................................................................................................................................................68
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT.............................................................................................. 69
6.3.1 ECP Register and Mode Definitions....................................................................................................................69
6.3.2 Data and ecpAFifo Port..........................................................................................................................................70
6.3.3 Device Status Register (DSR)................................................................................................................................70
6.3.4 Device Control Register (DCR)............................................................................................................................71
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010...................................................................................................72
6.3.6 ecpDFifo (ECP Dat a FIFO) Mode = 011............................................................................................................72
6.3.7 tFifo (Test FIFO Mode) Mode = 110...................................................................................................................72
6.3.8 cnfgA (Configuration Register A) Mode = 111 .................................................................................................72
6.3.9 cnfgB (Configuration Register B) Mode = 111 .................................................................................................72
6.3.10 ecr (Extended Control Register) Mode = all...................................................................................................73
6.3.11 Bit Map of ECP Port Registers ............................................................................................................................74
6.3.12 ECP Pin Descriptions...........................................................................................................................................75
6.3.13 ECP Operation.......................................................................................................................................................76
6.3.14 FIFO Operation.....................................................................................................................................................76
6.3.15 DMA Transfers........................................................................................................................................................77
6.3.16 Programmed I/O (NON- DMA) Mode.................................................................................................................77
6.4 EXTENSION FDD MODE (EXTFDD)............................................................................................................................ 77
6.5 EXTENSION 2FDD MODE (EXT2FDD)........................................................................................................................77
7. GENERAL PURPOSE I/O ...........................................................................................78
8. ACPI REGISTERS FEATURES .................................................................................81
9. HARDWARE MONITOR..........................................................................................82
9.1 GENERAL DESCRIPTION...............................................................................................................................................82
9.2 ACCESS INTERFAC E......................................................................................................................................................82
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- III - Revision 0.70
W83697HF/F
9.2.1 LPC interface............................................................................................................................................................82
9.3 ANALOG INPUTS............................................................................................................................................................ 84
9.3.1 Monitor over 4.096V voltage:...............................................................................................................................84
9.3.2 Monitor negative voltage:.....................................................................................................................................85
9.3.3 Temperature Measurement Machine....................................................................................................................86
9.4 FAN SPEED COUNT AND FAN SPEED CONTROL..................................................................................................87
9.4.1 Fan speed count.......................................................................................................................................................87
9.4.2 Fan speed control....................................................................................................................................................89
9.5 SMI# INTERRUPT MODE..............................................................................................................................................90
9.5.1 Voltage SMI# mode :...............................................................................................................................................90
9.5.2 Fan SMI# mode :......................................................................................................................................................90
9.5.3 Temperature SMI# mode.........................................................................................................................................91
9.5.4 The W83697HF temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is programmed
at CR[4Ch] bit 6. .....................................................................................................................................................92
9.6 OVT# INTERRUPT MODE ..............................................................................................................................................93
9.7 REGISTERS AND RAM................................................................................................................................................... 94
9.7.1 Address Register (Port x5h)...................................................................................................................................94
9.7.2 Data Register (Port x6h)........................................................................................................................................97
9.7.3 Configuration Register ¾ Index 40h.....................................................................................................................97
9.7.4 Interrupt Status Register 1¾ Index 41h ................................................................................................................98
9.7.5 Interrupt Status Register 2 ¾ Index 42h ...............................................................................................................98
9.7.6 SMI# Mask Register 1 ¾ Index 43h.......................................................................................................................99
9.7.7 SMI# Mask Register 2 ¾ Index 44h.......................................................................................................................99
9.7.8 Reserved Register ¾ Index 45h...........................................................................................................................100
9.7.9 Chassis Clear Register -- Index 46h.................................................................................................................. 100
9.7.10 VID/Fan Divisor Register ¾ Index 47h...........................................................................................................100
9.7.11 Value RAM ¾ Index 20h - 3Fh or 60h - 7Fh (auto-increment) ................................................................... 101
9.7.12 Device ID Register - Index 49h.........................................................................................................................102
9.7.13 Pin Control Register - Index 4Bh ....................................................................................................................102
9.7.14 SMI#/OVT# Property Select Register - Index 4Ch........................................................................................103
9.7.15 FAN IN/OUT and BEEP Control Register - Index 4Dh ................................................................................ 103
9.7.16 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (No Auto Increase)............................................. 104
9.7.17 Winbond Vendor ID Register - Index 4Fh (No Auto Increase)..................................................................105
9.7.18 Winbond Test Register -- Index 50h - 55h (Bank 0).................................................................................... 105
9.7.19 BEEP Control Register 1-- Index 56h (Bank 0)...........................................................................................105
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- IV - Revision 0.70
W83697HF/F
9.7.20 BEEP Control Register 2-- Index 57h (Bank 0)...........................................................................................106
9.7.21 Chip ID -- Index 58h (Bank 0).........................................................................................................................107
9.7.22 Reserved Register -- Index 59h (Bank 0)......................................................................................................107
9.7.23 PWMOUT1 Control -- Index 5Ah (Bank 0) ....................................................................................................108
9.7.24 PWMOUT2 Control -- Index 5Bh (Bank 0) ....................................................................................................108
9.7.25 PWMOUT1/2 Clock Select -- Index 5Ch (Bank 0).......................................................................................108
9.7.26 VBAT Monitor Control Register -- Index 5Dh (Bank 0).............................................................................108
9.7.27 Reserved Register -- 5Eh (Bank 0)................................................................................................................109
9.7.28 Reserved Register -- Index 5Fh (Bank 0)......................................................................................................109
9.7.29 Temperature Sensor 2 Temperature (High Byte) Register - Index 50h (Bank 1)...................................109
9.7.30 Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h (Bank 1)....................................109
9.7.31 Temperature Sensor 2 Configuration Register - Index 52h (Bank 1)......................................................110
9.7.32 Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1)........................................110
9.7.33 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h (Bank 1).........................................111
9.7.34 Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h (Bank 1)..........................111
9.7.35 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h (Bank 1)...........................112
9.7.36 Interrupt Status Register 3 -- Index 50h (BANK4).......................................................................................112
9.7.37 SMI# Mask Register 3 -- Index 51h (BANK 4) ...........................................................................................113
9.7.38 Reserved Register -- Index 52h (Bank 4)....................................................................................................... 113
9.7.39 BEEP Control Register 3-- Index 53h (Bank 4)...........................................................................................113
9.7.40 Temperature Sensor 1 Offset Register -- Index 54h (Bank 4).....................................................................114
9.7.41 Temperature Sensor 2 Offset Register -- Index 55h (Bank 4).....................................................................114
9.7.42 Reserved Register -- Index 57h--58h...............................................................................................................114
9.7.43 Real Time Hardware Status Register I -- Index 59h (Bank 4) ....................................................................115
9.7.44 Real Time Hardware Status Register II -- Index 5Ah (Bank 4)..................................................................115
9.7.45 Real Time Hardware Status Register III -- Index 5Bh (Bank 4).................................................................116
9.7.46 Reserved Register -- Index 5Ch (Bank 4).......................................................................................................117
9.7.47 VID Output Register -- Index 5Dh (Bank 4)..................................................................................................117
9.7.48 Value RAM 2¾ Index 50h - 5Ah (auto-increment) (BANK 5)....................................................................117
9.7.49 Winbond Test Register -- Index 50h (Bank 6)...............................................................................................117
9.7.50 FAN 1 Pre-Scale Register ndex00h ............................................................................................................. 117
9.7.51 FAN 1 Duty Cycle Select Register-- 01h (Bank 0).......................................................................................118
9.7.52 FAN 2 Pre-Scale Register -- Index 02h............................................................................................................118
9.7.53 FAN2 Duty Cycle Select Register-- Index 03h ..............................................................................................119
9.7.54 FAN Configuration Register-- Index 04h....................................................................................................... 119
Publication Release Date: Feb. 2002
- V - Revision 0.70
W83697HF/F
9.7.55 CPUT1 Target Temperature Register/ Fan 1 Target Speed Register -- Index 05h.................................120
9.7.56 CPUT2 Target Temperature Register/ Fan 2 Target Speed Register -- Index 06h.................................120
9.7.57 Tolerance of Target Temperature or Target Speed Register -- Index 07h..............................................121
9.7.58 Fan 1 PWM Stop Duty Cycle Register -- Index 08h .....................................................................................121
9.7.59 Fan 2 PWM Stop Duty Cycle Register -- 09h (Bank 0)...............................................................................121
9.7.60 Fan 1 Start- up Duty Cycle Register -- Index 0Ah.........................................................................................122
9.7.61 Fan 2 Start- up Duty Cycle Register -- Index 0Bh.........................................................................................122
9.7.62 Fan 1 Stop Time Register -- Index 0Ch...........................................................................................................122
9.7.63 Fan 2 Stop Time Register -- Index 0Dh...........................................................................................................122
9.7.64 Fan Step Down Time Register -- Index 0Eh...................................................................................................123
9.7.65 Fan Step Up Time Register -- Index 0Fh ........................................................................................................123
10. CONFIGURATION REGISTER..............................................................................124
10.1 PLUG AND PLAY CONFIGURATION......................................................................................................................124
10.2 COMPATIBLE PNP......................................................................................................................................................124
10.2.1 Extended Function Registers...........................................................................................................................124
10.2.2 Extended Functions Enable Registers (EFERs)...........................................................................................125
10.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs).................125
10.3 CONFIGURATION SEQUENCE .................................................................................................................................126
10.3.1 Enter the extended function mode...................................................................................................................126
10.3.2 Configurate the configuration registers........................................................................................................126
10.3.3 Exit the extended function mode ......................................................................................................................126
10.3.4 Software programming example......................................................................................................................126
10.4 CHIP (GLOBAL) CONTROL REGISTER....................................................................................................................128
10.5 LOGICAL DEVICE 0 (FDC)..........................................................................................................................................132
10.6 LOGICAL DEVICE 1 (PARALLEL PORT).................................................................................................................136
10.7 LOGICAL DEVICE 2 (UART A) ..................................................................................................................................137
10.8 LOGICAL DEVICE 3 (UART B)..................................................................................................................................137
10.9 LOGICAL DEVICE 6 (CIR)...........................................................................................................................................139
10.10 LOGICAL DEVICE 7 (GAME PORT GPIO PORT 1)...............................................................................................139
10.11 LOGICAL DEVICE 8 (MIDI PORT AND G PIO PORT 5)....................................................................................... 140
10.12 LOGICAL DEVICE 9 (GPIO PORT 2 ~ G PIO PORT 4 ).......................................................................................... 142
10.13 LOGICAL DEVICE A (ACPI).....................................................................................................................................144
10.14 LOGICAL DEVICE B (HARDWARE MONITO R)..................................................................................................148
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W83697HF/F
11. ORDERING INSTRUCTION...................................................................................149
12. HOW TO READ THE TOP MARKING..................................................................149
13. PACKAGE DIMENSIONS.......................................................................................150
Publication Release Date: Feb. 2002
- VII - Revision 0.70
W83697HF/F
GENERAL DESCRIPTION
The W83697HF is evolving product from Winbond's most popular I/O family. They feature a whole new
interface, namely LPC (Low Pin Count) interface, which will be supported in the new generation chip-set.
This interface as its name suggests is to provide an economical implementation of I/O's interface with lower
pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin
counts are saved in LPC I/O comparing to ISA implementation. With this additional freedom, we can
implement more devices on a single chip as demonstrated in W83697HF's integration of Game Port and
MIDI Port. It is fully transparent in terms of software which means no BIOS or device driver update is needed
except chip-specific configuration.
The disk drive adapter functions of W83697HF include a floppy disk drive controller compatible with the
industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate
selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of
functions integrated onto the W83697HF greatly reduces the number of components required for interfacing
with floppy disk drives. The W83697HF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and
data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s.
The W83697HF provides two high-speed serial communication ports (UARTs), one of which supports serial
Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate
generator, complete modem control capability, and a processor interrupt system. Both UARTs provide
legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or
921k bps which support higher speed modems. In addition, the W83697HF provides IR functions: IrDA 1.0
(SIR for 1.152K bps) and TV remote IR (Consumer IR, supporting NEC, RC -5, extended RC-5, and RECS -
80 protocols).
The W83697HF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also
Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins,
also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk
drives to be connected.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug -and-play feature demand
of Windows 95/98TM, which makes system resource allocation more efficient than ever.
The W83697HF provides a set of flexible I/O control functions to the system designer through a set of
General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to
provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in power
down mode (VCC is off).
The W83697HF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide, and
meet the requirements of ACPI.
The W83697HF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and
can be applied to all standard PC game control devices, They are very important for a entertainment or
consumer computer.
Publication Release Date: Feb. 2002
- 1 - Revision 0.70
W83697HF
The W83697HF provides Flash ROM interface . That can support up to 4M legacy flash ROM.
The W83697HF support hardware status monitoring for personal computers. It can be used to monitor
several critical hardware parameters of the system, including power supply voltages, fan speeds, and
temperatures, which are very important for a high-end computer system to work stably and properly.
Moreover, W83697HF support the Smart Fan control system, including the “Thermal CruiseTM” and “Speed
CruiseTM” functions. Smart Fan can make system more stable and user friendly.
FEATURES
General
• Meet LPC Spec. 1.01
• Support LDRQ#(LPC DMA), SERIRQ (serial IRQ)
• Include all the features of Winbond I/O W83877TF
• Integrate Hardware Monitor functions
• Compliant with Microsoft PC98/PC99 Hardware Design Guide
• Support DPM (Device Power Management), ACPI
• Programmable configuration settings
• Single 24 or 48 MHz clock input
FDC
• Compatible with IBM PC AT disk drive systems
• Variable write pre -compensation with track selectable capability
• Support vertical recording format
• DMA enable logic
• 16 -byte data FIFOs
• Support floppy disk drives and tape drives
• Detects all overrun and underrun conditions
• Built-in address mark detection circuit to simplify the read electronics
• FDD anti -virus functions with software write protect and FDD write enable signal (write data signal
was forced to be inactive)
• Support up to four 3.5 -inch or 5.25-inch floppy disk drives
• Completely compatible with industry standard 82077
• 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
•
Support 3-mode FDD, and its Win95/98 driver
Publication Release Date:Feb. 2002
- 2 - Revision 0.70
W83697HF
UART
• Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
• MIDI compatible
• Fully programmable serial -interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop bits generation
• Internal diagnostic capabilities:
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation
• Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1)
• Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz
Infrared
• Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
• Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
• Support Consumer IR with Wake-Up function.
Parallel Port
• Compatible with IBM parallel port
• Support PS/2 compatible bi-directional parallel port
• Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification
• Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification
• Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and
B through parallel port
• Enhanced printer port back -drive current protection
Game Port
• Support two separate Joysticks
• Support every Joystick two axes (X,Y) and two buttons (S1,S2) controllers
MIDI Port
• The baud rate is 31.25 Kbaud
• 16 -byte input FIFO
•
16 -byte output FIFO
- 3 - Revision 0.70
Publication Release Date:Feb. 2002
W83697HF
Flash ROM Interface
• Support up to 4M flash ROM
General Purpose I/O Ports
• 48 programmable general purpose I/O ports
• General purpose I/O ports can serve as simple I/O ports, watch dog timer output, power LED
output, infrared I/O pins, suspend LED output, Beep output
• Functional in power down mode
Hardware Monitor Functions
• Smart fan control system, support “Thermal CruiseTM” and “Speed CruiseTM”
• 2 thermal inputs from optionally remote thermistors or 2N3904 transistors or PentiumTM II/III thermal
diode output
• 6 positive voltage inputs (typical for +12V, -12V, +5V, -5V, +3.3V, Vcore)
• 2 intrinsic voltage monitoring (typical for Vbat, +5VSB)
• 2 fan speed monitoring inputs
• 2 fan speed control
• Build in Case open detection circuit
• WATCHDOG comparison of all monitored values
• Programmable hysteresis and setting points for all monitored items
• Over temperature indicate output
• Automatic Power On voltage detection Beep
• Issue SMI#, IRQ, OVT# to activate system protection
• Winbond Hardware DoctorTM Sup port
• Intel LDCMTM / Acer ADMTM compatible
Package
• 128 -pin PQFP
Publication Release Date:Feb. 2002
- 4 - Revision 0.70
PIN CONFIGURATION FOR 697HF
W83697HF
VTIN2
VTIN1
AVCC
VREF
VCORE
+3.3VIN
+12VIN
-12VIN
-5VIN
AGND
FANIO2
FANIO1
FANPWM2
FANPWM1
OVT#/SMI#
MSI/GP51/WDTO
MSO/GP50/PLED
BEEP
GPAS2/GP17
GPBS2/GP16
GPAY/GP15
GPBY/GP14
GPBX/GP13
GPAX/GP12
GPBS1/GP11
GPAS1/GP10
PME#
MEMR#/GP53
VBAT
1
0101099
2 1
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435363738
DRVDEN0
MEMW#/GP52
CIRRX
VSB
CASEOPEN#
989
79695949392
0
VCC
DSB#
DSA#
MOA#
INDEX#
ROMCS#/GP54
XD3/GP23
XD2/GP22
XD1/GP21
XD0/GP20
9
9089888
1
GND
XD6/GP26
XD5/GP25
XD4/GP24
78685
XA3/GP33
XA2/GP32
XA0/GP30
XA1/GP31
XD7/GP27
8483828180797
XA5/GP35
XA4/GP34
W83697HF
WE#
WD#
DIR#
MOB#
STEP#
WP#
TRAK0#
HEAD#
RDATA#
DSKCHG#
GND
CLKIN#
PCICLK
VCC3
LDRQ#
SERIRQ
LAD3
XA9/GP41
XA8/GP40
XA7/GP37
XA6/GP36
8777675
LAD2
LAD1
LAD0
LFRAME#
VCC
XA11/GP43
XA10/GP42
747
372
PE
SLCT
LRESET#
XA16/GP55
XA15/GP47
XA14/GP46
XA13/GP45
XA12/GP44
706
7
686
1
9
PD7
ACK#
BUSY
ERR#
SLIN#
IRTX
XA18/GP57
XA17/GP56
6
6
6
7
5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
PD4
PD5
PD6
IRRX
RIB#
DCDB#
SOUTB
GND
SINB
DTRB#
RTSB#
DSRB#
CTSB#
RIA#
DCDA#
SOUTA
SINA
DTRA#
RTSA#
DSRA#
CTSA#
STB#
VCC
AFD#
INIT#
PD0
PD1
PD2
PD3
Publication Release Date:Feb. 2002
- 5 - Revision 0.70
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O8t - TTL level bi-directional pin with 8 mA source-sink capability
I/O
- TTL level bi-directional pin with 12 mA source-sink capability
12t
I/O
- 3.3V TTL level bi-directional pin with 12 mA source-sink capability
12tp3
I/OD
- TTL level bi-directional pin open drain output with 12 mA sink capability
12t
I/O
- TTL level bi-directional pin with 24 mA source-sink capability
24t
OUT
- TTL level output pin with 12 mA source -sink capability
12t
OUT
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INcs - CMOS level Schmitt-trigger input pin
INt - TTL level input pin
INtd - TTL level input pin with internal pull down resistor
INts - TTL level Schmitt-trigger input pin
IN
- 3.3V TTL level output pin with 12 mA source-sink capability
12tp3
- 3.3V TTL level Schmitt-trigger input pin
tsp3
W83697HF
1.1 LPC Interface
SYMBOL PIN I/O FUNCTION
CLKIN 17 INt System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz input.
PME#
PCICLK 19 IN
LDRQ# 20 O
SERIRQ 21 I/OD12t Serial IRQ input/Output.
LAD[3:0] 23- 26 I/O
LFRAME#
LRESET#
98 OD12 Generated PME event.
PCI clock input.
tsp3
Encoded DMA Request signal.
12tp3
These signal lines communicate address, control, and data
12tp3
information over the LPC bus between a host and a peripheral.
27 IN
28 IN
Indicates start of a new cycle or termination of a broken cycle.
tsp3
Reset signal. It can connect to PCIRST# signal on the host.
tsp3
Publication Release Date:Feb. 2002
- 6 - Revision 0.70
1.2 FDC Interface
SYMBOL PIN I/O FUNCTION
DRVDEN0 1 OD24 Drive Density Select bit 0.
W83697HF
INDEX#
MOA#
DSB#
DSA#
MOB#
DIR#
STEP#
WD#
WE#
TRAK0#
WP#
RDATA#
2 INcs This Schmitt-triggered input from the disk drive is active low when
the head is positioned over the beginning of a track marked by an
index hole. This input pin is pulled up internally by a 1 KΩ
resistor. The resistor can be disabled by bit 7 of L0-CRF0
(FIPURDWN).
3 OD24 Motor A On. When set to 0, this pin enables disk drive 0. This is
an open drain output.
4 OD24 Drive Select B. When set to 0, this pin enables disk drive B. This
is an open drain output.
6 OD24 Drive Select A. When set to 0, this pin enables disk drive A. This
is an open drain output.
7 OD24 Motor B On. When set to 0, this pin enables disk drive 1. This is
an open drain output.
8 OD24 Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
9 OD24 Step output pulses. This active low open drain output produces a
pulse to move the head to another track.
10 OD24 Write data. This logic low open drain writes pre-compensation
serial data to the selected FDD. An open drain output.
11 OD24 Write enable. An open drain output.
12 INcs Track 0. This Schmitt- triggered input from the disk drive is active
low when the head is positioned over the outermost track. This
input pin is pulled up internally by a 1 KΩ resistor. The resistor
can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
13 INcs Write protected. This active low Schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin is
pulled up internally by a 1 KΩ resistor. The resistor can be
disabled by bit 7 of L0- CRF0 (FIPURDWN).
14 INcs The read data input signal from the FDD. This input pin is pulled
up internally by a 1 KΩ resistor. The resistor can be disabled by
bit 7 of L0-CRF0 (FIPURDWN).
Publication Release Date:Feb. 2002
- 7 - Revision 0.70
1.2 FDC Interface, continued
SYMBOL PIN I/O FUNCTION
HEAD#
DSKCHG#
15 OD24 Head select. This open drain output determines which disk drive
head is active.
Logic 1 = side 0
Logic 0 = side 1
16 INcs Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up
internally by a 1 KΩ resistor. The resistor can be disabled by bit 7
of L0 -CRF0 (FIPURDWN).
1.3 Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.
SYMBOL PIN I/O FUNCTION
SLCT 29 INt
OD12
OD12
PE
OD12
30 INt
OD
PRINTER MODE:
An active h igh input on this pin indicates that the printer is
selected. This pin is pulled high internally. Refer to the
description of the parallel port for definition of this pin in ECP and
EPP mode.
EXTENSION FDD MODE: WE2#
This pin is for Extension FDD B; its function is the same as the
EXTENSION 2FDD MODE: WD2#
12
pin of FDC.
WE#
EXTENSION 2FDD MODE: WE2#
This pin is for Extension FDD A and B; its function is the same as
the
PRINTER MODE:
An active high input on this pin indicates that the printer has
detected the end of the paper. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of this
pin in ECP and EPP mode.
EXTENSION FDD MODE: WD2#
This pin is for Extension FDD B; its function is the same as the
WD#
This pin is for Extension FDD A and B; its function is the same as
the
pin of FDC.
WE#
pin of FDC.
pin of FDC.
WD#
W83697HF
Publication Release Date:Feb. 2002
- 8 - Revision 0.70
1.3 Multi-Mode Parallel Port, continued
SYMBOL PIN I/O FUNCTION
BUSY 31 INt
PRINTER MODE:
An active high input indicates that the printer is not ready to
receive data. This pin is pulled high internally. Refer to the
description of the parallel port for definition of this pin in ECP and
EPP mode.
OD12
OD
EXTENSION FDD MODE: MOB2#
This pin is for Extension FDD B; its function is the same as the
MOB# pin of FDC.
EXTENSION 2FDD MODE: MOB2#
12
This pin is for Extension FDD A and B; its function is the same as
the MOB# pin of FDC.
ACK# 32 INt
OD12
OD
PRINTER MODE: ACK#
An acti ve low input on this pin indicates that the printer has
received data and is ready to accept more data. This pin is pulled
high internally. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DSB2#
This pin is for the Extension FDD B; its functions is the same as
the DSB# pin of FDC.
EXTENSION 2FDD MODE: DSB2#
12
This pin is for Extension FDD A and B; its function is the same as
the DSB# pin of FDC.
ERR#
33
INt
OD12
OD12
PRINTER MODE: ERR#
An active low input on this pin indicates that the printer has
encountered an error condition. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of this
pin in ECP and EPP mode.
EXTENSION FDD MODE: HEAD2#
This pin is for Extension FDD B; its function is the same as the
HEAD#pin of FDC.
EXTENSION 2FDD MODE: HEAD2#
This pin is for Extension FDD A and B; its function is the same as
the HEAD# pin of FDC.
W83697HF
Publication Release Date:Feb. 2002
- 9 - Revision 0.70
1.3 Multi-Mode Parallel Port, continued
SYMBOL PIN I/O FUNCTION
SLIN# 34 OD12
OD12
OD12
INIT#
AFD# 44 OD12
43 OD12
OD12
OD12
OD12
OD12
PRINTER MODE: SLIN#
Output line for detection of printer selection. This pin is pulled high
internally. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: STEP2#
This pin is for Extension FDD B; its function is the same as the
STEP# pin of FDC.
EXTENSION 2FDD MODE: STEP2#
This pin is for Extension FDD A and B; its function is the same as
the STEP# pin of FDC.
PRINTER MODE: INIT#
Output line for the printer initialization. This pin is pulled high
internally. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DIR2#
This pin is for Extension FDD B; its function is the same as the
DIR# pin of FDC.
EXTENSION 2FDD MODE: DIR2#
This pin is for Extension FDD A and B; its function is the same as
the DIR# pin of FDC.
PRINTER MODE: AFD#
An active low output from this pin causes the printer to auto feed a
line after a line is printed. This pin is pulled high internally. Refer to
the description of the parallel port for the definition of this pin in
ECP and EPP mode.
EXTENSION FDD MODE: DRVDEN0
This pin is for Extension FDD B; its function is the same as the
DRVDEN0 pin of FDC.
EXTENSION 2FDD MODE: DRVDEN0
This pin is for Extension FDD A and B; its function is the same as
the DRVDEN0 pin of FDC.
W83697HF
Publication Release Date:Feb. 2002
- 10 - Revision 0.70
W83697HF
1.3 Multi-Mode Parallel Port, continued
SYMBOL PIN I/O FUNCTION
STB# 46 OD12 PRINTER MODE: STB#
An active low output is used to latch the parallel data into the
printer. This pin is pulled high internally. Refer to the description of
the parallel port for the definition of this pin in ECP and EPP mode.
- EXTENSION FDD MODE: This pin is a tri-state output.
- EXTENSION 2FDD MODE: This pin is a tri-state output.
PD0
INt
INt EXTENSION 2FDD MODE: INDEX2#
PD1
PD2
42 I/O
41 I/O
40 I/O
PRINTER MODE: PD0
12t
Parallel port data bus bit 0. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: INDEX2#
This pin is for Extension FDD B; its function is the same as the
INDEX# pin of FDC. It is pulled high internally.
This pin is for Extension FDD A and B; its function is the same as
the INDEX# pin of FDC. It is pulled high internally.
PRINTER MODE: PD1
12t
Parallel port data bus bit 1. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
INt
INt
INt
INt
EXTENSION FDD MODE: TRAK02#
Thi s pin is for Extension FDD B; its function is the same as the
TRAK0# pin of FDC. It is pulled high internally.
EXTENSION. 2FDD MODE: TRAK02#
This pin is for Extension FDD A and B; its function is the same as
the TRAK0# pin of FDC. It is pulled high internally.
PRINTER MODE: PD2
12t
Parallel port data bus bit 2. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: WP2#
This pin is for Extension FDD B; its function is the same as the
WP# pin of FDC. It is pulled high internally.
EXTENSION. 2FDD MODE: WP2#
This pin is for Extension FDD A and B; its function is the same as
the WP# pin of FDC. It is pulled high internally.
Publication Release Date:Feb. 2002
- 11 - Revision 0.70
1.3 Multi-Mode Parallel Port, continued
SYMBO L PIN I/O FUNCTION
PD3
39 I/O
INt
INt
PRINTER MODE: PD3
12t
Parallel port data bus bit 3. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: RDATA2#
This pin is for Extension FDD B; its function is the same as the
RDATA# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: RDATA2#
This pin is for Extension FDD A and B; its function is the same as
the RDATA# pin of FDC. It is pulled high internally.
PD4
38 I/O
INt
INt
PRINTER MODE: PD4
12t
Parallel port data bus bit 4. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DSKCHG2#
This pin is for Extension FDD B; the function of this pin is the same
as the DSKCHG# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: DSKCHG2#
This pin is for Extension FDD A and B; this function of this pin is
the same as the DSKCHG# pin of FDC. It is pulled high internally.
PD5
PD6
PD7
37 I/O
36 I/OD
OD12
35 I/OD
OD12
PRINTER MODE: PD5
12t
Parallel port data bus bit 5. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
PRINTER MODE: PD6
12t
Parallel port data bus bit 6. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION. 2FDD MODE: MOA2#
This pin is for Extension FDD A; its function is the same as the
MOA# pin of FDC.
PRINTER MODE: PD7
12t
Parallel port data bus bit 7. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: DSA2#
This pin is for Extension FDD A; its function is the same as the
DSA# pin of FDC.
W83697HF
Publication Release Date:Feb. 2002
- 12 - Revision 0.70
1.4 Serial Port Interface
SYMBOL PIN I/O FUNCTION
CTSA#
CTSB#
DSRA#
DSRB#
RTSA#
HEFRAS
RTSB#
DTRA#
PNPCSV#
DTRB#
SINA
SINB
SOUTA
PENROM#
SOUTB
PEN48
DCDA#
DCDB#
RIA#
RIB#
47
55
48
56
49
During power-on reset, this pin is pulled down internally and is
57 I/O8t UART B Request To Send. An active low signal informs the modem
50
58
51
59
52
61
53
62
54
63
INt Clear To Send. It is the modem control input.
The function of these pins can be tested by reading bit 4 of the
handshake status register.
INt Data Set Ready. An active low signal indicates the modem or data
set is ready to establish a communication link and transfer data to
the UART.
I/O8t UART A Request To Send. An active low signal informs the modem
or data set that the controller is ready to send data.
defined as HEFRAS, which provides the power-on value for CR26 bit
6 (HEFRAS). A 4.7 kΩ is recommended if intends to pull up.
(select 4EH as configuration I/O port′s address)
or data set that the controller is ready to send data.
I/O8t UART A Data Terminal Ready. An active low signal informs the
modem or data set that the controller is ready to communicate.
During power-on reset, this pin is pulled down internally and is
defined as
bit 0 (
(clear the default value of FDC, UARTs, and PRT)
I/O8t UART B Data Terminal Ready. An active low signal informs the
modem or data set that controller is ready to communicate.
INt Serial Input. It is used to receive serial data through the
communication link.
I/O8t UART A Serial Output. It is used to transmit serial data out to the
communication link.
During power on reset , this pin is pulled down internally and is
defined as PENROM#, which provides the power on value for CR24
bit 1. A 4.7kΩ is recommended if intends to pull up .
I/O8t UART B Serial Output. During power-on reset, this pin is pulled
down internally and is defined as PEN48, which provides the poweron value for CR24 bit 6 (EN48). A 4.7 kΩ resistor is recommended
if intends to pull up.
INt Data Carrier Detect. An active low signal indicates the modem or
data set has detected a data carrier.
INt Ring Indicator. An active low signal indicates that a ring signal is
being received from the modem or data set.
PNPCSV#
PNPCSV#
, which provides the power-on value for CR24
). A 4.7 kΩ is recommended if intends to pull up.
W83697HF
Publication Release Date:Feb. 2002
- 13 - Revision 0.70
1.5 Infrared Port
SYMBOL PIN I/O FUNCTION
IRRX
IRTX
CIRRX# 100 INt
64 Ints
Alternate Function Input: Infrared Receiver input.
General purpose I/O port 3 bit 6.
65 OUT12t Alternate Function Output: Infrared Transmitter Output.
General purpose I/O port 3 bit 7.
Consumer IR receiving input. This pin can Wake-Up system from
S5
cold.
1.6 Fresh ROM Interface
SYMBOL PIN I/O FUNCTION
XA18-XA16
GP57-GP55
XA15-XA10
GP47-GP42
XA9 -XA8
GP41-GP40
XA7 -XA0
GP37-GP30
XD7-XD4
GP27-GP24
XD3-XD0
GP23-GP20
ROMCS#
GP54
MEMR#
GP53
MEMW#
GP52
66- 68 I/O
I/OD
69- 74 I/O
I/OD
76- 77 I/O
I/OD
78- 85 O
I/OD
86- 89 O
I/OD
91- 94 I/O
I/OD
95 I/O
I/OD
96 I/O
I/OD
97 I/O
I/OD
Flash ROM interface Address[18:16]
12t
General purpose I/O port 5 bit7-5
12t
Flash ROM interface Address[15:10]
12t
G eneral purpose I/O port 4 bit7-2
12t
Flash ROM interface Address[9:8]
12t
General purpose I/O port 4 bit1-0
12t
Flash ROM interface Address[7:0]
General purpose I/O port 3 bit7-0
12t
Flash ROM interface Data Bus[7:4]
General purpose I/O port 2 bit7-4
12t
Flash ROM interface Data Bus [3:0]
12t
General purpose I/O port 2 bit3-0
12t
Flash ROM interface Chip Select
12t
General purpose I/O port 5 bit4
12t
Flash ROM interface Memory Read Enable
12t
General purpose I/O port 5 bit3
12t
Flash ROM interface Memory Write Enable
12t
General purpose I/O port 5 bit2
12t
W83697HF
Publication Release Date:Feb. 2002
- 14 - Revision 0.70
W83697HF
1.7 Hardware Monitor Interface
SYMBOL PIN I/O FUNCTION
CASEOPEN#
VBAT 102 Power Battery Voltage Input
VTIN2 103 AIN Temperature sensor 2 input. It is used for CPU temperature
VTIN1 104 AIN Temperature sensor 1 input. It is used for system temperature
VREF 106 AOUT Reference Voltage for temperature measuration.
VCORE 107 AIN 0V to 4.096V FSR Analog Inputs.
+3.3VIN 108 AIN 0V to 4.096V FSR Analog Inputs.
+12VIN 109 AIN 0V to 4.096V FSR Analog Inputs.
-12VIN 110 AIN 0V to 4.096V FSR Analog Inputs.
101 INt CASE OPEN. An active low signal from an external device when
case is opened.
measuration.
measuration.
-5VIN 111 AIN 0V to 4.096V FSR Analog Inputs.
FANIO[2:1] 113 -
114
FANPWM[2:
1]
OVT# /
SMI#
BEEP
115 -
116
117 OD12 Over temperature Shutdown Output. It indicated the VTIN1 or
118 OD12 Beep function for hardware monitor. This pin is low after system
I/O
0V to +5V amplitude fan tachometer input.
12ts
Alternate Function: Fan on- off control output.
These multifunctional pins can be programmable input or output.
O12 Fan speed control. Use the Pulse Width Modulatuion (PWM)
technic knowledge to control the Fan's RPM.
VTIN2 is over temperature limit.
System Management Interrupt.
reset.
Publication Release Date:Feb. 2002
- 15 - Revision 0.70
1.8 Game Port & MIDI Port
SYMBOL PIN I/O FUNCTION
MSI
GP51
WDTO
MSO
GP50
PLED
GPAS2
GP17
GPBS2
GP16
GPAY
GP15
GPBY
GP14
GPBX
GP13
GPAX
GP12
GPBS1
GP11
GPAS1
GP10
119 INt
I/OD
12
OD
24t
120 OUT12t
I/OD
12
OD
24t
121 INcs
I/OD12
122 INcs
I/OD12
123 I/OD
124 I/OD12
125 I/OD12
126 I/OD12
127 INcs
128 INcs
12
I/OD12
I/OD12
I/OD12
I/OD12
I/OD12
I/OD12
MIDI serial data input .
General purpose I/O port 5 bit 1.
Alternate Function Output(Default)
Power LED output, this signal is low after system reset.
MIDI serial data output.
General purpose I/O port 5 bit 0.
Alternate Function :
Watch dog timer output.
Active-low, Joystick I switch input 2. This pin has an internal pullup resistor. (Default)
General purpose I/O port 1 bit 7.
Active-low, Joystick II switch input 2. This pin has an internal pullup resistor. (Default)
General purpose I/O port 1 bit 6.
Joystick I timer pin. this pin connect to Y positioning variable
resistors for the Josystick. (Default)
General purpose I/O port 1 bit 5.
Joystick II timer pin. this pin connect to Y positioning variable
resistors for the Josystick. (Default)
General purpose I/O port 1 bit 4.
Joystick II timer pin. this pin connect to X positioning variable
resistors for the Josystick. (Default)
General purpose I/O port 1 bit 3.
Joystick I timer pin. this pin connect to X positioning variable
resistors for the Josystick. (Default)
Ge neral purpose I/O port 1 bit 2.
Active-low, Joystick II switch input 1. This pin has an internal pull up resistor. (Default)
General purpose I/O port 1 bit 1.
Active-low, Joystick I switch input 1. This pin has an internal pullup resistor. (Default)
General purpose I/O port 1 bit 0.
W83697HF
Publication Release Date:Feb. 2002
- 16 - Revision 0.70
W83697HF
1.9 POWER PINS
SYMBOL PIN FUNCTION
VCC 5, 45, 75, +5V power supply for the digital circuitry.
VSB 99 +5V stand-by power supply for the digital circuitry.
VCC3V 22 +3.3V power supply for driving 3V on host interface.
AVCC 105 Analog VCC input. Internally supplier to all analog circuitry.
AGND 112 Internally connected to all analog circuitry. The ground reference
for all analog inputs..
GND 18, 60, 90, Ground.
Publication Release Date:Feb. 2002
- 17 - Revision 0.70
W83697HF
2. LPC (LOW PIN COUNT) INTERFACE
LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and peripheral
(Winbond I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general characteristics of
the interface implemented in Winbond LPC I/O are:
• One control line, namely LFRAME#, which is used by the host to start or stop transfers. No peripherals
drive this signal.
• The LAD[3:0] bus, which communicates information serially. The information conveyed are cycle type,
cycle direction, chip select ion, address, data, and wait states.
• MR (master reset) of Winbond ISA I/O is replaced with a active low reset signal, namely LRESET#, in
Winbond LPC I/O.
• An additional 33 MHz PCI clock is needed in Winbond LPC I/O for synchronization.
• DMA requests are issued through LDRQ#.
• Interrupt requests are issued through SERIRQ.
• Power management events are issued through PME#.
Comparing to its ISA counterpart, LPC implementation saves up to 40 pin counts free for integrating more
devices on a single chip.
The transition from ISA to LPC is transparent in terms of software which means no BIOS or device driver
update is needed except chip-specific configuration.
Publication Release Date:Feb. 2002
- 18 - Revision 0.70
W83697HF/F
Data Rate
3. FDC FUNCTIONAL DESCRIPTION
3.1 W83697HF FDC
The floppy disk controller of the W83697HF integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to 2 M bits/sec data rate.
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
3.1.1 AT interface
The interface consists of the standard asynchronous signals:
a data bus. The address lines select between the configuration registers, the FIFO and control/status
registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2
register sets are a superset of the registers found in a PC/AT.
3.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and
DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage of
the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with a FIFO. The data are based upon the foll owing formula:
THRESHOLD # × (1/DATA/RATE) *8 - 1.5 µS = DELAY
FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500K BPS
1 Byte 1 × 16 µS - 1.5 µS = 14.5 µS
2 Byte 2 × 16 µS - 1.5 µS = 30.5 µS
8 Byte 8 × 16 µS - 1.5 µS = 6.5 µ S
15 Byte 15 × 16 µS - 1.5 µS = 238.5 µS
FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
1 Byte 1 × 8 µS - 1.5 µ S = 6.5 µS
2 Byte 2 × 8 µS - 1.5 µ S = 14.5 µS
8 Byte 8 × 8 µS - 1.5 µ S = 62.5 µS
15 Byte 15 × 8 µS - 1.5 µS = 118.5 µS
, WR#, A0-A3, IRQ, DMA control, and
RD#
Publication Release Date: Feb. 2002
- 19 - Revision 0.70
W83697HF/F
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove
the remaining data so that the result phase may be entered.
DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the
DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK# and
addresses need not be valid.
Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by
the FDC based only on DACK#. This mode is only available when the FDC has been configured into byte
mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is
performed by using the new VERIFY command. No DMA operation is needed.¡@
3.1.3 Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved
the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The
sync hronized clock, called the Data Window, is used to internally sample the serial data portion of the
bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates
the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized
and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for
every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed.
A digital integrator is used to keep track of the speed changes in the input data stream.
3.1.4 Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk
drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media
and the floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known. Depending upon the pattern, the bit is shifted either early or late
relative to the surrounding bits.
Publication Release Date: Feb. 2002
- 20 - Revision 0.70
W83697HF/F
3.1.5 Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically.
This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.
A single command puts the FDC into perpendicular mode. All other commands operate as they normally
do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases
the host interface bottleneck due to the speed of data transfer to or from the disk.
3.1.6 FDC Core
The W83697HF FDC is capable of performing twenty commands. Each command is initiated by a multi byte transfer from the microprocessor. The result can also be a multi- byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.
Command
The microprocessor issues all required information to the controller to perform a specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status information and other housekeeping information is provided to
the microprocessor.
3.1.7 FDC Commands
Command Symbol Descriptions:
C: Cylinder number 0 - 256
D: Data Pattern
DIR: Step Direction
DIR = 0, step out
DIR = 1, step in
DS0: Disk Drive Select 0
DS1: Disk Drive Select 1
DTL: Data Length
EC: Enable Count
EOT: End of Track
EFIFO: Enable FIFO
EIS: Enable Implied Seek
Publication Release Date: Feb. 2002
- 21 - Revision 0.70
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